Index: /firmware/FTM/doc/v5.1/FTM_firmware_specs_v5-1.aux =================================================================== --- /firmware/FTM/doc/v5.1/FTM_firmware_specs_v5-1.aux (revision 14288) +++ /firmware/FTM/doc/v5.1/FTM_firmware_specs_v5-1.aux (revision 14288) @@ -0,0 +1,121 @@ +\relax +\citation{DRS4} +\citation{LMK03000} +\citation{FTM-Schematics} +\@writefile{toc}{\contentsline {chapter}{\numberline {1}Introduction}{2}} +\@writefile{lof}{\addvspace {10\p@ }} +\@writefile{lot}{\addvspace {10\p@ }} +\newlabel{cha:Introduction}{{1}{2}} +\@writefile{toc}{\contentsline {chapter}{\numberline {2}Trigger-ID}{4}} +\@writefile{lof}{\addvspace {10\p@ }} +\@writefile{lot}{\addvspace {10\p@ }} +\newlabel{cha:Trigger-ID}{{2}{4}} +\@writefile{lot}{\contentsline {table}{\numberline {2.1}{\ignorespaces The transmission protocol to broadcast the trigger-ID to the FAD boards}}{4}} +\newlabel{tab:Trigger-ID broadcast}{{2.1}{4}} +\@writefile{lot}{\contentsline {table}{\numberline {2.2}{\ignorespaces Trigger-Type 1}}{4}} +\newlabel{tab:Trigger-Type 1}{{2.2}{4}} +\@writefile{lot}{\contentsline {table}{\numberline {2.3}{\ignorespaces Trigger-Type 2}}{5}} +\newlabel{tab:Trigger-Type 2}{{2.3}{5}} +\citation{W5300} +\@writefile{toc}{\contentsline {chapter}{\numberline {3}FTM Commands}{6}} +\@writefile{lof}{\addvspace {10\p@ }} +\@writefile{lot}{\addvspace {10\p@ }} +\newlabel{cha:FTM-Commands}{{3}{6}} +\@writefile{lot}{\contentsline {table}{\numberline {3.1}{\ignorespaces FTM command structure}}{7}} +\newlabel{tab:FTM-command-structure}{{3.1}{7}} +\@writefile{lot}{\contentsline {table}{\numberline {3.2}{\ignorespaces FTM command ID listing}}{7}} +\newlabel{tab:FTM-command-ID}{{3.2}{7}} +\@writefile{lot}{\contentsline {table}{\numberline {3.3}{\ignorespaces Command parameters for the 'read' command; only for the static data block single addresses can be read.}}{7}} +\newlabel{tab:FTM-read-command-param}{{3.3}{7}} +\@writefile{lot}{\contentsline {table}{\numberline {3.4}{\ignorespaces Command parameters for the 'write' command; only the static data block can be written, therefore parameter value 0x2 is not used.}}{7}} +\newlabel{tab:FTM-write-command-param}{{3.4}{7}} +\@writefile{lot}{\contentsline {table}{\numberline {3.5}{\ignorespaces Command parameters for the 'autosend on/off' command}}{7}} +\newlabel{tab:FTM-as-command-param}{{3.5}{7}} +\@writefile{lot}{\contentsline {table}{\numberline {3.6}{\ignorespaces Command parameters for the 'config single FTU' command}}{9}} +\newlabel{tab:FTM-cfsingleFTU-command-param}{{3.6}{9}} +\@writefile{lot}{\contentsline {table}{\numberline {3.7}{\ignorespaces Command parameters for the 'start run' command: "start run" means an "endless" run, i.e. no pre-defined number of events; if a number of events X is specified, this is done with a 32-bit unsigned long integer (big endian).}}{9}} +\newlabel{tab:FTM-start-command-param}{{3.7}{9}} +\@writefile{lot}{\contentsline {table}{\numberline {3.8}{\ignorespaces Command parameters for the 'crate reset' command: the command parameter may only contain a single "1" corresponding to only one crate reset at a time.}}{9}} +\newlabel{tab:FTM-reset-command-param}{{3.8}{9}} +\citation{ds557} +\citation{ds610} +\citation{wp267} +\citation{wp266} +\citation{LMK03000} +\citation{LMK03000} +\@writefile{toc}{\contentsline {chapter}{\numberline {4}FTM data blocks}{10}} +\@writefile{lof}{\addvspace {10\p@ }} +\@writefile{lot}{\addvspace {10\p@ }} +\newlabel{cha:FTM-data-block}{{4}{10}} +\@writefile{lot}{\contentsline {table}{\numberline {4.1}{\ignorespaces Structure of a data package as sent by the FTM to the FTMcontrol software. The start and end delimiters are the same as used for the FAD boards.}}{10}} +\newlabel{tab:FTM-package}{{4.1}{10}} +\@writefile{toc}{\contentsline {section}{\numberline {4.1}Static data block}{10}} +\newlabel{sec:Static-data-block}{{4.1}{10}} +\gdef \LT@i {\LT@entry + {1}{51.20975pt}\LT@entry + {1}{203.20688pt}\LT@entry + {3}{188.92177pt}} +\@writefile{lot}{\contentsline {table}{\numberline {4.4}{Overview of the FTM static data block}}{12}} +\newlabel{tab:FTM-trigger-master-static-data-block}{{4.4}{12}} +\citation{FLD-Schematics} +\citation{LMK03000} +\citation{FTUspecs} +\@writefile{lot}{\contentsline {table}{\numberline {4.2}{\ignorespaces Header structure for sending a data block or error message, wherq 'SD' stands for the static data block and `DD' for the dynamic data block.}}{13}} +\newlabel{tab:FTM-header}{{4.2}{13}} +\@writefile{lot}{\contentsline {table}{\numberline {4.3}{\ignorespaces Encoding of the status of the FTM board in the header. In this context `LOCKED` means that the PLL of the Clock conditioner \cite {LMK03000} is locked.}}{13}} +\newlabel{tab:STATUS}{{4.3}{13}} +\citation{MAX6662} +\@writefile{lot}{\contentsline {table}{\numberline {4.5}{\ignorespaces FTM general settings register}}{14}} +\newlabel{tab:FTM-general-settings-register}{{4.5}{14}} +\@writefile{lot}{\contentsline {table}{\numberline {4.6}{\ignorespaces 'on-board status LEDs' register}}{14}} +\newlabel{tab:FTM-LED-register}{{4.6}{14}} +\@writefile{toc}{\contentsline {section}{\numberline {4.2}Dynamic data block}{14}} +\newlabel{sec:Dynamic-data-block}{{4.2}{14}} +\gdef \LT@ii {\LT@entry + {1}{51.20975pt}\LT@entry + {1}{322.56075pt}} +\@writefile{lot}{\contentsline {table}{\numberline {4.7}{\ignorespaces Register for the period [ms] of calibration and pedestal events}}{15}} +\newlabel{tab:FTM-frequency-register}{{4.7}{15}} +\@writefile{lot}{\contentsline {table}{\numberline {4.8}{\ignorespaces Register defining the sequence of LP1, LP2 and pedestal events; 5 bits used per value. By setting e.g. LP1/LP2/PED = 3/2/1, the systems generates 3 LP1 triggers, followed by 2 LP2 triggers, followed by 1 PED trigger (if they are also activated in the 'general settings' register). The distance between the triggers is defined with another register (table\nobreakspace {}4.7\hbox {}).}}{15}} +\newlabel{tab:FTM-ratio-register}{{4.8}{15}} +\@writefile{lot}{\contentsline {table}{\numberline {4.9}{\ignorespaces Light pulser 1 amplitude register}}{15}} +\newlabel{tab:LP1-amplitude-register}{{4.9}{15}} +\@writefile{lot}{\contentsline {table}{\numberline {4.10}{\ignorespaces Light pulser 2 amplitude register}}{15}} +\newlabel{tab:LP2-amplitude-register}{{4.10}{15}} +\@writefile{lot}{\contentsline {table}{\numberline {4.11}{\ignorespaces Structure of the two majority coincidence (n-out-of-40) registers; the binary value in these registers is the minimum number n of FTU trigger primitives required to trigger an event (physics or calibration)}}{15}} +\newlabel{tab:FTM-majority}{{4.11}{15}} +\gdef \LT@iii {\LT@entry + {1}{48.00613pt}\LT@entry + {1}{347.18793pt}} +\@writefile{lot}{\contentsline {table}{\numberline {4.12}{FTM dynamic data block}}{16}} +\newlabel{tab:FTM-dynamic-data-block}{{4.12}{16}} +\@writefile{toc}{\contentsline {section}{\numberline {4.3}FTU list}{16}} +\newlabel{sec:FTU-List}{{4.3}{16}} +\citation{ds557} +\citation{ds610} +\citation{wp267} +\citation{wp266} +\@writefile{lot}{\contentsline {table}{\numberline {4.13}{FTU list}}{17}} +\newlabel{tab:FTU-list}{{4.13}{17}} +\@writefile{lot}{\contentsline {table}{\numberline {4.14}{\ignorespaces Address of FTU board and number of pings until response. In case there is no response at all, this number is set to 0.}}{17}} +\newlabel{tab:FTU-crate-number-and-address}{{4.14}{17}} +\citation{FTUspecs} +\citation{FTUspecs} +\bibstyle{unsrt} +\@writefile{toc}{\contentsline {chapter}{\numberline {5}FTU communication error handling}{18}} +\@writefile{lof}{\addvspace {10\p@ }} +\@writefile{lot}{\addvspace {10\p@ }} +\newlabel{cha:Error-handling}{{5}{18}} +\@writefile{lot}{\contentsline {table}{\numberline {5.1}{\ignorespaces FTU communication error message (after standard header); for a description of the FTU data package, see \cite {FTUspecs}.}}{18}} +\newlabel{tab:error-message}{{5.1}{18}} +\bibcite{DRS4}{1} +\bibcite{LMK03000}{2} +\bibcite{FTM-Schematics}{3} +\bibcite{W5300}{4} +\bibcite{ds557}{5} +\bibcite{ds610}{6} +\bibcite{wp267}{7} +\bibcite{wp266}{8} +\bibcite{MAX6662}{9} +\bibcite{FTUspecs}{10} +\bibcite{FLD-Schematics}{11} Index: /firmware/FTM/doc/v5.1/FTM_firmware_specs_v5-1.log =================================================================== --- /firmware/FTM/doc/v5.1/FTM_firmware_specs_v5-1.log (revision 14288) +++ /firmware/FTM/doc/v5.1/FTM_firmware_specs_v5-1.log (revision 14288) @@ -0,0 +1,319 @@ +This is pdfTeX, Version 3.141592-1.40.3 (Web2C 7.5.6) (format=pdflatex 2010.5.3) 27 JUL 2012 13:36 +entering extended mode +**FTM_firmware_specs_v5-1.tex +(./FTM_firmware_specs_v5-1.tex +LaTeX2e <2005/12/01> +Babel and hyphenation patterns for english, usenglishmax, dumylang, noh +yphenation, arabic, basque, bulgarian, coptic, welsh, czech, slovak, german, ng +erman, danish, esperanto, spanish, catalan, galician, estonian, farsi, finnish, + french, greek, monogreek, ancientgreek, croatian, hungarian, interlingua, ibyc +us, indonesian, icelandic, italian, latin, mongolian, dutch, norsk, polish, por +tuguese, pinyin, romanian, russian, slovenian, uppersorbian, serbian, swedish, +turkish, ukenglish, ukrainian, loaded. +(/usr/share/texmf/tex/latex/base/report.cls +Document Class: report 2005/09/16 v1.4f Standard LaTeX document class +(/usr/share/texmf/tex/latex/base/size11.clo +File: size11.clo 2005/09/16 v1.4f Standard LaTeX file (size option) +) +\c@part=\count79 +\c@chapter=\count80 +\c@section=\count81 +\c@subsection=\count82 +\c@subsubsection=\count83 +\c@paragraph=\count84 +\c@subparagraph=\count85 +\c@figure=\count86 +\c@table=\count87 +\abovecaptionskip=\skip41 +\belowcaptionskip=\skip42 +\bibindent=\dimen102 +) +(/usr/share/texmf/tex/latex/float/float.sty +Package: float 2001/11/08 v1.3d Float enhancements (AL) +\c@float@type=\count88 +\float@exts=\toks14 +\float@box=\box26 +\@float@everytoks=\toks15 +\@floatcapt=\box27 +) +(/usr/share/texmf/tex/latex/graphics/graphicx.sty +Package: graphicx 1999/02/16 v1.0f Enhanced LaTeX Graphics (DPC,SPQR) + +(/usr/share/texmf/tex/latex/graphics/keyval.sty +Package: keyval 1999/03/16 v1.13 key=value parser (DPC) +\KV@toks@=\toks16 +) +(/usr/share/texmf/tex/latex/graphics/graphics.sty +Package: graphics 2006/02/20 v1.0o Standard LaTeX Graphics (DPC,SPQR) + +(/usr/share/texmf/tex/latex/graphics/trig.sty +Package: trig 1999/03/16 v1.09 sin cos tan (DPC) +) +(/usr/lib/texmf/tex/latex/config/graphics.cfg +File: graphics.cfg 2007/01/18 v1.5 graphics configuration of teTeX/TeXLive +) +Package graphics Info: Driver file: pdftex.def on input line 90. + +(/usr/share/texmf/tex/latex/pdftex-def/pdftex.def +File: pdftex.def 2007/01/08 v0.04d Graphics/color for pdfTeX +\Gread@gobject=\count89 +)) +\Gin@req@height=\dimen103 +\Gin@req@width=\dimen104 +) +(/usr/share/texmf/tex/latex/ltxmisc/url.sty +\Urlmuskip=\muskip10 +Package: url 2005/06/27 ver 3.2 Verb mode for urls, etc. +) +(/usr/share/texmf/tex/latex/base/fontenc.sty +Package: fontenc 2005/09/27 v1.99g Standard LaTeX package + +(/usr/share/texmf/tex/latex/base/t1enc.def +File: t1enc.def 2005/09/27 v1.99g Standard LaTeX file +LaTeX Font Info: Redeclaring font encoding T1 on input line 43. +)) +(/usr/share/texmf/tex/latex/amsmath/amsmath.sty +Package: amsmath 2000/07/18 v2.13 AMS math features +\@mathmargin=\skip43 + +For additional information on amsmath, use the `?' option. +(/usr/share/texmf/tex/latex/amsmath/amstext.sty +Package: amstext 2000/06/29 v2.01 + +(/usr/share/texmf/tex/latex/amsmath/amsgen.sty +File: amsgen.sty 1999/11/30 v2.0 +\@emptytoks=\toks17 +\ex@=\dimen105 +)) +(/usr/share/texmf/tex/latex/amsmath/amsbsy.sty +Package: amsbsy 1999/11/29 v1.2d +\pmbraise@=\dimen106 +) +(/usr/share/texmf/tex/latex/amsmath/amsopn.sty +Package: amsopn 1999/12/14 v2.01 operator names +) +\inf@bad=\count90 +LaTeX Info: Redefining \frac on input line 211. +\uproot@=\count91 +\leftroot@=\count92 +LaTeX Info: Redefining \overline on input line 307. +\classnum@=\count93 +\DOTSCASE@=\count94 +LaTeX Info: Redefining \ldots on input line 379. +LaTeX Info: Redefining \dots on input line 382. +LaTeX Info: Redefining \cdots on input line 467. +\Mathstrutbox@=\box28 +\strutbox@=\box29 +\big@size=\dimen107 +LaTeX Font Info: Redeclaring font encoding OML on input line 567. +LaTeX Font Info: Redeclaring font encoding OMS on input line 568. +\macc@depth=\count95 +\c@MaxMatrixCols=\count96 +\dotsspace@=\muskip11 +\c@parentequation=\count97 +\dspbrk@lvl=\count98 +\tag@help=\toks18 +\row@=\count99 +\column@=\count100 +\maxfields@=\count101 +\andhelp@=\toks19 +\eqnshift@=\dimen108 +\alignsep@=\dimen109 +\tagshift@=\dimen110 +\tagwidth@=\dimen111 +\totwidth@=\dimen112 +\lineht@=\dimen113 +\@envbody=\toks20 +\multlinegap=\skip44 +\multlinetaggap=\skip45 +\mathdisplay@stack=\toks21 +LaTeX Info: Redefining \[ on input line 2666. +LaTeX Info: Redefining \] on input line 2667. +) +(/usr/share/texmf/tex/latex/tools/longtable.sty +Package: longtable 2004/02/01 v4.11 Multi-page Table package (DPC) +\LTleft=\skip46 +\LTright=\skip47 +\LTpre=\skip48 +\LTpost=\skip49 +\LTchunksize=\count102 +\LTcapwidth=\dimen114 +\LT@head=\box30 +\LT@firsthead=\box31 +\LT@foot=\box32 +\LT@lastfoot=\box33 +\LT@cols=\count103 +\LT@rows=\count104 +\c@LT@tables=\count105 +\c@LT@chunks=\count106 +\LT@p@ftn=\toks22 +) +(/usr/share/texmf/tex/latex/ltxmisc/parskip.sty +Package: parskip 2001/04/09 non-zero parskip adjustments +) +(/usr/share/texmf/tex/latex/psnfss/pifont.sty +Package: pifont 2005/04/12 PSNFSS-v9.2a Pi font support (SPQR) +LaTeX Font Info: Try loading font information for U+pzd on input line 63. + +(/usr/share/texmf/tex/latex/psnfss/upzd.fd +File: upzd.fd 2001/06/04 font definitions for U/pzd. +) +LaTeX Font Info: Try loading font information for U+psy on input line 64. + +(/usr/share/texmf/tex/latex/psnfss/upsy.fd +File: upsy.fd 2001/06/04 font definitions for U/psy. +)) +(/usr/share/texmf/tex/latex/tools/array.sty +Package: array 2005/08/23 v2.4b Tabular extension package (FMi) +\col@sep=\dimen115 +\extrarowheight=\dimen116 +\NC@list=\toks23 +\extratabsurround=\skip50 +\backup@length=\skip51 +) (./FTM_firmware_specs_v5-1.aux) +\openout1 = `FTM_firmware_specs_v5-1.aux'. + +LaTeX Font Info: Checking defaults for OML/cmm/m/it on input line 29. +LaTeX Font Info: ... okay on input line 29. +LaTeX Font Info: Checking defaults for T1/cmr/m/n on input line 29. +LaTeX Font Info: ... okay on input line 29. +LaTeX Font Info: Checking defaults for OT1/cmr/m/n on input line 29. +LaTeX Font Info: ... okay on input line 29. +LaTeX Font Info: Checking defaults for OMS/cmsy/m/n on input line 29. +LaTeX Font Info: ... okay on input line 29. +LaTeX Font Info: Checking defaults for OMX/cmex/m/n on input line 29. +LaTeX Font Info: ... okay on input line 29. +LaTeX Font Info: Checking defaults for U/cmr/m/n on input line 29. +LaTeX Font Info: ... okay on input line 29. + +(/usr/share/texmf/tex/context/base/supp-pdf.tex +[Loading MPS to PDF converter (version 2006.09.02).] +\scratchcounter=\count107 +\scratchdimen=\dimen117 +\scratchbox=\box34 +\nofMPsegments=\count108 +\nofMParguments=\count109 +\MPscratchCnt=\count110 +\MPscratchDim=\dimen118 +\MPnumerator=\count111 +\everyMPtoPDFconversion=\toks24 +) +LaTeX Font Info: Try loading font information for T1+cmtt on input line 31. + (/usr/share/texmf/tex/latex/base/t1cmtt.fd +File: t1cmtt.fd 1999/05/25 v2.5h Standard LaTeX font definitions +) [1 + +{/var/lib/texmf/fonts/map/pdftex/updmap/pdftex.map}] (./FTM_firmware_specs_v5-1 +.toc) +\tf@toc=\write3 +\openout3 = `FTM_firmware_specs_v5-1.toc'. + + [1 + +] +Chapter 1. +[2 + +] [3] +Chapter 2. +[4 + +] [5] +Chapter 3. + +Overfull \hbox (4.20976pt too wide) in paragraph at lines 259--266 + [][] + [] + +[6 + +] [7] [8] [9] +Chapter 4. + +Overfull \hbox (14.21452pt too wide) in paragraph at lines 404--423 + [][] + [] + + +LaTeX Warning: `!h' float specifier changed to `!ht'. + + +LaTeX Warning: `h' float specifier changed to `ht'. + + +Underfull \vbox (badness 10000) detected at line 498 + [] + +[10 + +] [11] +Overfull \hbox (3.71858pt too wide) in paragraph at lines 575--580 + [][] + [] + + +LaTeX Warning: `h' float specifier changed to `ht'. + + +LaTeX Warning: `h' float specifier changed to `ht'. + + +LaTeX Warning: `h' float specifier changed to `ht'. + + +LaTeX Warning: `h' float specifier changed to `ht'. + +[12] + +LaTeX Warning: `!h' float specifier changed to `!ht'. + + +LaTeX Warning: `!h' float specifier changed to `!ht'. + + +LaTeX Warning: `!h' float specifier changed to `!ht'. + +[13] [14] +Underfull \vbox (badness 10000) detected at line 837 + [] + +[15] +Underfull \vbox (badness 10000) detected at line 955 + [] + +[16] [17] +Chapter 5. +[18 + +] [19 + +] (./FTM_firmware_specs_v5-1.aux) ) +Here is how much of TeX's memory you used: + 2114 strings out of 94070 + 24811 string characters out of 1165710 + 92855 words of memory out of 3500000 + 5375 multiletter control sequences out of 10000+50000 + 24774 words of font info for 60 fonts, out of 1200000 for 2000 + 645 hyphenation exceptions out of 8191 + 27i,11n,20p,514b,273s stack positions out of 5000i,500n,6000p,200000b,5000s +{/usr/share/texmf/fonts/enc/dvips/cm-super/c +m-super-t1.enc}{/usr/share/texmf/fonts/enc/dvips/ai/aicmsy.enc}{/usr/share/texm +f/fonts/enc/dvips/ai/aicmmi.enc}{/usr/share/texmf/fonts/enc/dvips/ai/aicmtext.e +nc}< +/usr/share/texmf/fonts/type1/bluesky/cm/cmr8.pfb> +< +/usr/share/texmf/fonts/type1/public/cm-super/sfti1095.pfb> +Output written on FTM_firmware_specs_v5-1.pdf (20 pages, 276622 bytes). +PDF statistics: + 135 PDF objects out of 1000 (max. 8388607) + 0 named destinations out of 1000 (max. 131072) + 1 words of extra memory for PDF output out of 10000 (max. 10000000) + Index: /firmware/FTM/doc/v5.1/FTM_firmware_specs_v5-1.tex =================================================================== --- /firmware/FTM/doc/v5.1/FTM_firmware_specs_v5-1.tex (revision 14288) +++ /firmware/FTM/doc/v5.1/FTM_firmware_specs_v5-1.tex (revision 14288) @@ -0,0 +1,1080 @@ +\documentclass[a4paper,11pt]{report} + +\usepackage{float} +\usepackage{graphicx} +\usepackage{url} +\usepackage[T1]{fontenc} +\usepackage{amsmath} +\usepackage{longtable} +\usepackage{parskip} +\usepackage{pifont} +\usepackage{array} + +\setlength{\oddsidemargin}{0cm} +\setlength{\evensidemargin}{0cm} +\setlength{\topmargin}{0cm} + +\textwidth 6.2in +\textheight 9in +\columnsep 0.25in + +\pagestyle{plain} +\setcounter{tocdepth}{1} + +\title{\vspace*{-7cm} \Huge \bf FTM Firmware Specifications} +\author{\Large Patrick Vogler\footnote{Contact for questions and suggestions concerning this + document: {\tt patrick.vogler@phys.ethz.ch}}, Quirin Weitzel} +\date{\vspace*{0.5cm} \Large v5.1~~~-~~~July 2012} + +\begin{document} + +\maketitle + +\newpage + +\tableofcontents + +%--------------------------------------------------------------------------------- + +\chapter{Introduction} +\label{cha:Introduction} + +The FTM (FACT Trigger Master) board collects the trigger primitives from all +40 FTU boards (FACT Trigger Unit) and generates the trigger signal for the +FACT camera. The trigger logic is a 'n-out-of-40' majority coincidence of all +trigger primitives. Beside the trigger, the FTM board also generates a +trigger-ID (see chapter \ref{cha:Trigger-ID}). It is controlled from outside +via ethernet. Two auxiliary RS-485 interfaces are also available in hardware, +but not yet supported in firmware. + +In addition to the trigger, the FTM board also generates other fast control +signals: Time-Marker (TIM), DRS \cite{DRS4} reference clock (CLD) and +reset. These four fast control signals are distributed to the FAD (FACT Analog +to Digital) boards via two FFC (FACT Fast Control) boards. The FTM board also +provides, via the TIM line, the signal for the DRS timing calibration. In order +to generate the CLD DRS reference clock, as well as the time-marker signal for +DRS timing calibration, the FTM board uses a clock conditioner +\cite{LMK03000}. + +The FTM board has two time counters, the 'timestamp counter' and the 'on-time +counter'. While the 'timestamp counter' runs continuously, the 'on-time +counter' only counts when the camera trigger is enabled, i.e. when no FAD board +is busy and not during the dead time. Both counters are reset at the beginning and +at the end of a run. + +The FTM board further serves as slow control master for the 40 FTU boards. The +slow control of the FTU boards and the distribution of the trigger-ID to the +FAD boards are performed via dedicated RS-485 buses. Because the FAD as well +as the FTU boards are arranged in crates of 10 boards each, the FTM board has +four connectors, one for each crate. Running over these connectors there are +two RS-485 buses (one for FTU slow control and one for the trigger-ID) besides +the busy signal from the FAD boards and the crate reset. + +In addition, the FTM board controls the two FLPs (FACT Light Pulser) via four +LVDS signals each. Light pulser~1 (also known as `external lightpulser`) is +located in the mirror dish, light pulser~2 (also known as `internal lightpulser`) +inside the camera shutter. There are also digital auxiliary in- and +outputs according to the NIM (Nuclear Instrumentation Module) standard, for +example for external triggers and veto, and to have the signals accessible. + +The main component of the FTM board is a FPGA (Xilinx Spartan +XC3SD3400A-4FGG676C), fulfilling the main functions within the board. The +purpose of this document is to provide specifications needed for the +understanding of the firmware of this FPGA and the software (called 'FTMcontrol' +in the following) controlling the FTM board. For further information about the +FTM board hardware please refer to \cite{FTM-Schematics}. + +\chapter{Trigger-ID} +\label{cha:Trigger-ID} + +For each processed trigger the FTM board generates a unique trigger-ID to be +broadcasted to all FAD boards and added to the event data. This trigger-ID +consists of a 32 bit trigger number, a two byte trigger type indicator and a +checksum. The transmission protocol for the trigger-ID broadcast is shown in +table \ref{tab:Trigger-ID broadcast}. + +\begin{table}[htbp] +\centering +\begin{tabular}{|l|l|}\hline +byte no & content\\\hline\hline +0 & Trigger-No first byte (least significant byte) \\\hline +1 & Trigger-No second byte\\\hline +2 & Trigger-No third byte\\\hline +3 & Trigger-No forth byte (most significant byte)\\\hline +4 & Trigger-Type 1\\\hline +5 & Trigger-Type 2\\\hline +6 & CRC-8-CCITT (checksum)\\\hline +\end{tabular} +\caption{The transmission protocol to broadcast the trigger-ID to the FAD boards} +\label{tab:Trigger-ID broadcast} +\end{table} + +A Cyclic Redundancy Check (CRC) over byte 0 - 5 is used to evaluate the +integrity of the trigger-ID. An 8-CCITT CRC has been chosen which is based on +the polynomial $x^8 + x^2 + x + 1$ (00000111, omitting the most significant +bit). The resulting 1-byte checksum comprises the last byte of the trigger-ID. +The transmission of the trigger-ID to the FAD boards is done by means of +dedicated RS-485 buses (one per crate). + +In the first byte of the trigger type indicator (see table +\ref{tab:Trigger-Type 1}) n0 - n5 indicate the number of trigger primitives +required for a trigger, thus the 'n' of the 'n-out-of-40' majority +coincidence. The two flags 'external trigger 1' and 'external trigger 2', +when set, indicate a trigger from the corresponding NIM inputs. See also +section \ref{sec:Static-data-block} and table \ref{tab:FTM-majority} for +further information. + +\begin{table}[htbp] +\centering +%\begin{small} +\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline + Bit7 & Bit6 & Bit5 & Bit4 & Bit3 & Bit2 & Bit1 & Bit0\\\hline\hline + n5 & n4 & n3 & n2 & n1 & n0 & external trigger 2 & external trigger 1\\\hline +\end{tabular} +%\end{small} +\caption{Trigger-Type 1} +\label{tab:Trigger-Type 1} +\end{table} + +\begin{table}[htbp] +\centering +\begin{small} +\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline +Bit7 & Bit6 & Bit5 & Bit4 & Bit3 & Bit2 & Bit1 & Bit0\\\hline\hline +TIM source & LP\_set\_3 & LP\_set\_2 & LP\_set\_1 & LP\_set\_0 & pedestal & LP\_2 & LP\_1\\\hline +\end{tabular} +\end{small} +\caption{Trigger-Type 2} +\label{tab:Trigger-Type 2} +\end{table} + +The 'TIM source' bit in 'Trigger-Type 2' (see table \ref{tab:Trigger-Type 2}) +indicates the source of the timemarker signal: a '0' indicates the timemarker +being produced in the FPGA while a '1' indicates the timemarker coming from +the clock conditioner. The flags 'LP\_1' and 'LP\_2' are set when the +corresponding lightpulser has flashed while the 'pedestal' flag is set in case +of a pedestal (random) trigger. An event having none of these flags set +indicates a physics event. +% The bits 'LP\_set\_0' to 'LP\_set\_3' are used to +% code information about the light pulser settings. They only have a meaning in +% case of calibration events. +The bits 'LP\_set\_0' to 'LP\_set\_3' can be used in the future to +code information about the light pulser settings. They only have a meaning in +case of calibration events, but are not yet filled by the firmware (only zeros). + + +\chapter{FTM Commands} +\label{cha:FTM-Commands} + +The communication between the FTM board and the FTMcontrol software, including +the corresponding commands, protocols and data, is based on 16-bit words and +big-endian. This is to facilitate the data-transmission over the Wiznet W5300 +ethernet interface \cite{W5300}. + +The basic structure of all commands is the same and given in table +\ref{tab:FTM-command-structure}. After a start delimiter, the second word +identifies the command. Next there is a parameter further refining the +command, e.g. what to read. The fourth and fifth words are spares and should +contain zeros only. Starting from the sixth word, an optional data block of +variable size is following. This data block differs in length and content +depending on command and parameter. In case of 'read' instructions, the +corresponding data block is sent back. + +%The FTM board must answer every command by sending back the appropriate data +%block or by simply sending back the instruction where there is no datablock to +%be sent back. All 'read' commands to the FTM board do not contain any data +%blocks, but the FTM boards response does. In case of 'read' and 'write' +%instructions, the datablock is to be sent back. When 'start run' or 'stop run' +%commands are used, the FTM board 'mirrors' them, i.e. sends them back for +%confirmation. + +\begin{table}[p] +\centering +\begin{tabular}{|l|l|}\hline + word no & content\\\hline\hline + 0 & start delimiter ('@') \\\hline + 1 & command ID \\\hline + 2 & command parameter \\\hline + 3 & spare: containing 0x0000\\\hline + 4 & spare: containing 0x0000 \\\hline + 5 & data block (optional and of variable size)\\\hline + ... & ...\\\hline + X & data block\\\hline +\end{tabular} +\caption{FTM command structure} +\label{tab:FTM-command-structure} +\end{table} + +So far eight different commands are foreseen: 'read', 'write', 'start run', +'stop run', 'ping FTUs', 'crate reset', 'autosend on/off' and 'config single FTU' (see table +\ref{tab:FTM-command-ID}). The command parameters of the 'read' and 'write' +commands are shown in table~\ref{tab:FTM-read-command-param} and +table~\ref{tab:FTM-write-command-param}, respectively. With the 'autosend +on/off' command it is possible to switch off the automatic sending of trigger +rates and error messages (see table~\ref{tab:FTM-as-command-param}). + +The 'config single FTU' command has as its parameters a crate and a board number +as it is shown in table~\ref{tab:FTM-cfsingleFTU-command-param}. +Before the 'config single FTU' command can be meaningfully executed, the corresponding +data has to be written into the static data block (see section~\ref{sec:Static-data-block}), +using e.g. 'write single address' commands. +The 'config single FTU' command then writes the new configuration to the corresponding FTU board, +even if a run is ongoing. + +\begin{table}[p] +\centering +\begin{tabular}{|r|r|}\hline + command-ID: bits & \\\cline{1-1} + 15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command\\\hline\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & read \\\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 & write \\\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & start run / take X events\\\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 & stop run \\\hline + 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 \vline 0 & ping all FTUs \\\hline + 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 & crate reset \\\hline + 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 & autosend on/off \\\hline + 0 \vline 1 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 & config single FTU \\\hline +\end{tabular} +\caption{FTM command ID listing} +\label{tab:FTM-command-ID} +\end{table} + +\begin{table}[p] +\centering +\begin{tabular}{|r|r|r|}\hline + command parameter: bits & & \\\cline{1-1} + 15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & read complete static data block & no\\\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 & read complete dynamic data block & no\\\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & read single address of static data block & address\\\hline + %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & read trigger list & no\\\hline +\end{tabular} +\caption{Command parameters for the 'read' command; only for the static data + block single addresses can be read.} +\label{tab:FTM-read-command-param} +\end{table} + +\begin{table}[p] +\centering +\begin{tabular}{|r|r|r|}\hline + command parameter: bits & & \\\cline{1-1} + 15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & write complete static data block & all configuration data\\\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & write single address of static data block & address + data\\\hline +\end{tabular} +\caption{Command parameters for the 'write' command; only the static data + block can be written, therefore parameter value 0x2 is not used.} +\label{tab:FTM-write-command-param} +\end{table} + +\begin{table}[p] +\centering +\begin{tabular}{|r|r|r|}\hline + command parameter: bits & & \\\cline{1-1} + 15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 & reports disabled & no\\\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & reports enabled & no\\\hline +\end{tabular} +\caption{Command parameters for the 'autosend on/off' command} +\label{tab:FTM-as-command-param} +\end{table} + + + +\begin{table}[p] +\centering +\begin{tabular}{|c|c|c|c|c|c|}\hline +\multicolumn{4}{|c|}{command parameter: bits} & \multicolumn{2}{c|}{ }\\\hline %cline{1-1} + 15 ... 11 & 10 ... 8 & 7 ... 2 & 1 ... 0 & command & data block\\\hline\hline + 0 & slot no & 0 & crate no & configure FTU & no\\\hline +\end{tabular} +\caption{Command parameters for the 'config single FTU' command} +\label{tab:FTM-cfsingleFTU-command-param} +\end{table} + + +%\begin{table}[htbp] +%\centering +%\begin{tabular}{|r|r|r|}\hline +% command parameter: bits & & \\\cline{1-1} +% 15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline +% 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline0 \vline 0 \vline0 \vline1 & write static data & static data block\\\hline +%\end{tabular} +%\caption{Command parameters for the 'write' command} +%\label{tab:FTM-write-command-param} +%\end{table} + +In table \ref{tab:FTM-start-command-param} the parameters to start a run are +listed. The type of the run is fully described in the FTM configuration +(static data block, see section~\ref{sec:Static-data-block}), which always has +to be sent by the FTMcontrol before starting a run. Therefore the only +option is to start an "endless" run or to take X events (Not yet implemented in firmware) instead. +In the latter +case X is defined by a two words (32 bit) long unsigned integer, making up the +command data block. The 'start run' command enables the transmission of +trigger signals (physics, calibration or pedestal) to the FAD boards and +resets the trigger and time counters. There is no parameter for stopping a +run. If a number of events has been specified ('take X events'), the run will +terminate if either the 'stop run' command is received or the requested number +of events is reached. In any case the trigger and time counters are reset, +too. + +\begin{table}[p] +\centering +\begin{tabular}{|r|r|r|}\hline + command parameter: bits & & \\\cline{1-1} + 15 ... 8 \vline7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & start run & no \\\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 & take X events & number of events X \\\hline + %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & start taking pedestals & no \\\hline + %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 1 & take X pedestals events & number of events X \\\hline + %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 & start calibration run & no \\\hline + %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 1 & take X calibration events & number of events X \\\hline +\end{tabular} +\caption{Command parameters for the 'start run' command: "start run" means an + "endless" run, i.e. no pre-defined number of events; if a number of events X + is specified, this is done with a 32-bit unsigned long integer (big endian).} +\label{tab:FTM-start-command-param} +\end{table} + +%\begin{table}[htbp] +%\centering +%\begin{tabular}{|r|r|r|}\hline +% command parameter: bits & & \\\cline{1-1} +% 15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline +% 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & stop run & no\\\hline +%\end{tabular} +%\caption{Command parameter for the 'stop run' command} +%\label{tab:FTM-stop-command-param} +%\end{table} + +In case of a 'ping FTUs' command the FTM will address the FTUs one by one and +readout their DNA. The results are collected in the FTU list (see section +\ref{sec:FTU-List}), which is sent back to the FTMcontrol. There are no +parameters for this command. With the 'crate reset' command the FTU and FAD boards of a +particular crate are rebooted (only the FPGAs), where the command parameter defines the +crate number (see table \ref{tab:FTM-reset-command-param}). Only one crate +reset at a time is possible, i.e. the FTM firmware does not allow to reset +multiple crates in one command. + +\begin{table}[p] +\centering +\begin{tabular}{|r|r|r|}\hline + command parameter: bits & & \\\cline{1-1} + 15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & reset crate 0 & no\\\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 & reset crate 1 & no\\\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & reset crate 2 & no\\\hline + 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 & reset crate 3 & no\\\hline +\end{tabular} +\caption{Command parameters for the 'crate reset' command: the command parameter may only contain a single "1" + corresponding to only one crate reset at a time.} +\label{tab:FTM-reset-command-param} +\end{table} + +\chapter{FTM data blocks} +\label{cha:FTM-data-block} + +The trigger master features two main data blocks, named 'static data block' +and 'dynamic data block' in the following. They are implemented in the +firmware as block-RAM. In addition, there is the so-called 'FTU list', which +is filled only on request ('ping FTUs' command). If any of these blocks is +sent to the FTMcontrol (either automatically or on demand), a header with a +size of 14 words is added, and the whole data package is put between a start +and an end delimiter (see table~\ref{tab:FTM-package}). The header is +identical for all data blocks and contains solely read-only information: the +type and length of the package, the FTM status, the FTM board ID (57-bit +Xilinx device DNA \cite{ds557, ds610, wp267, wp266}), a firmware ID and the +readings of the trigger counter and time stamp counter since last reset (see +table~\ref{tab:FTM-header}). + +\begin{table}[h] +\centering +\begin{tabular}{|c|c|c|c|}\hline + start delimiter & header & data block & end delimiter \\\hline + 0xFB01 & 14 words & optional size & 0x04FE\\\hline +\end{tabular} +\caption{Structure of a data package as sent by the FTM to the FTMcontrol + software. The start and end delimiters are the same as used for the FAD boards.} +\label{tab:FTM-package} +\end{table} + +\begin{table}[h!] +\centering +\begin{tabular}{|l|l|c|}\hline + word no & content & description\\\hline\hline + 0x000 & type of data package & 1: SD, 2: DD, 3: FTU-list, 4: error, 5: single SD-word\\\hline + 0x001 & length of data package & after header, including end delimiter\\\hline + 0x002 & status of FTM & see table \ref{tab:STATUS}\\\hline + 0x003 & board ID bits 63...48 & FPGA device DNA\\\hline + 0x004 & board ID bits 47...32 & FPGA device DNA\\\hline + 0x005 & board ID bits 31...16 & FPGA device DNA\\\hline + 0x006 & board ID bits 15... 0 & FPGA device DNA\\\hline + 0x007 & firmware ID & defined as a VHDL constant\\\hline + 0x008 & trigger counter bits 31...16 & at read-out time\\\hline + 0x009 & trigger counter bits 15... 0 & at read-out time\\\hline + 0x00A & time stamp bits 63...48 & filled up with zeros\\\hline + 0x00B & time stamp bits 47...32 & at read-out time\\\hline + 0x00C & time stamp bits 31...16 & at read-out time\\\hline + 0x00D & time stamp bits 15... 0 & at read-out time\\\hline +\end{tabular} +\caption{Header structure for sending a data block or error message, wherq + 'SD' stands for the static data block and `DD' for the dynamic + data block.} +\label{tab:FTM-header} +\end{table} + +In table \ref{tab:STATUS} the encoding of the status of the FTM is shown. + +\begin{table}[h] +\centering +\begin{tabular}{|c|c|}\hline + status & value \\\hline\hline + IDLE\_NOT\_LOCKED & 0x0001\\\hline + CONFIG & 0x0002 \\\hline + RUNNING\_NOT\_LOCKED & 0x0003\\\hline + IDLE & 0x0101\\\hline + RUNNING & 0x0103\\\hline +\end{tabular} +\caption{Encoding of the status of the FTM board in the header. + In this context `LOCKED` means that the PLL of the Clock + conditioner \cite{LMK03000} is locked.} +\label{tab:STATUS} +\end{table} + + +\section{Static data block} +\label{sec:Static-data-block} + +The static data block contains all the settings needed to configure and +operate the FTM. It has to be written by the FTMcontrol each time before a run +is started or, in general, some component has to be reprogrammed. In +addition, whenever the FTM board receives a new static data block, it performs +a complete reconfiguration including a reprogramming of the FTUs. +As an exception, the clock conditioner is only reprogrammed, if its settings +really changed. When a new static data block is received during a run, it +is written to the memeory, but subsequently ignored. +Table~\ref{tab:FTM-trigger-master-static-data-block} summarizes the +static data block. More details about the individual registers can be found in +the subsequent tables. + +%These settings are readable and writable by the main control using the +%corresponding commands 'read static data block' or 'write static data block', +%respectively. There is one exception from writability: In case the static +%data block is read back, the first eleven words (address 0..A) are identical +%with the dynamic data block and the trigger list shown in +%\ref{tab:FTM-trigger-master-dynamic-data-block} and +%\ref{tab:FTM-trigger-list}. These first eleven words can only be read and not +%written. The board ID is supposed to be the Xilinx device DNA \cite{ds557, +% ds610, wp267, wp266}, the 57 bit device ID of the FPGA. When using the +%'write static data block' command, the static data block must start with the +%'general settings register' at address 0x00B. So there is an offset in the +%addresses of 0x00B between the 'read-out-version' and the 'write-version' of +%the static data block. + +\begin{longtable}[h]{|l|l|c|}\hline +\centering +word no & content & description\\\hline\hline +0x000 & general settings & see table~\ref{tab:FTM-general-settings-register} and text\\\hline +0x001 & on-board status LEDs & see table~\ref{tab:FTM-LED-register}\\\hline +0x002 & light pulser and pedestal trigger period & see table~\ref{tab:FTM-frequency-register} and text\\\hline +0x003 & sequence of LP1, LP2 and PED triggers & see table~\ref{tab:FTM-ratio-register} and text\\\hline + +0x004 & light pulser 1 amplitude & see table~\ref{tab:LP1-amplitude-register} and text\\\hline +0x005 & light pulser 2 amplitude & see table~\ref{tab:LP2-amplitude-register} and text\\\hline +0x006 & light pulser 1 delay & 8ns + delay value*4ns\\\hline +0x007 & light pulser 2 delay & 8ns + delay value*4ns\\\hline + +0x008 & majority coincidence n (for physics) & see table~\ref{tab:FTM-majority} and text\\\hline +0x009 & majority coincidence n (for calibration) & see table~\ref{tab:FTM-majority} and text\\\hline +0x00A & trigger delay & 8ns + delay value*4ns, 10 bits used\\\hline +0x00B & timemarker delay & 8ns + delay value*4ns, 10 bits used\\\hline +0x00C & dead time & 8ns + value*4ns, 16 bits used\\\hline +0x00D & clock conditioner R0 bits 31...16 & \\\hline +0x00E & clock conditioner R0 bits 15...0 & \\\hline +0x00F & clock conditioner R1 bits 31...16 & \\\hline +0x010 & clock conditioner R1 bits 15...0 & \\\hline +0x011 & clock conditioner R8 bits 31...16 & \\\hline +0x012 & clock conditioner R8 bits 15...0 & \\\hline +0x013 & clock conditioner R9 bits 31...16 & \\\hline +0x014 & clock conditioner R9 bits 15...0 & \\\hline +0x015 & clock conditioner R11 bits 31...16 & \\\hline +0x016 & clock conditioner R11 bits 15...0 & \\\hline +0x017 & clock conditioner R13 bits 31...16 & \\\hline +0x018 & clock conditioner R13 bits 15...0 & \\\hline +0x019 & clock conditioner R14 bits 31...16 & \\\hline +0x01A & clock conditioner R14 bits 15...0 & \\\hline +0x01B & clock conditioner R15 bits 31...16 & \\\hline +0x01C & clock conditioner R15 bits 15...0 & \\\hline +0x01D & maj. coinc. window (for physics) & 8ns + value*4ns, 4 bits used\\\hline +0x01E & maj. coinc. window (for calibration) & 8ns + value*4ns, 4 bits used \\\hline +0x01F & spare & \\\hline +0x020 & enables patch 0 board 0 crate 0 & see FTU documentation\\\hline +0x021 & enables patch 1 board 0 crate 0 & see FTU documentation\\\hline +0x022 & enables patch 2 board 0 crate 0 & see FTU documentation\\\hline +0x023 & enables patch 3 board 0 crate 0 & see FTU documentation\\\hline +0x024 & DAC$\_$A board 0 crate 0 & see FTU documentation \\\hline +0x025 & DAC$\_$B board 0 crate 0 & see FTU documentation \\\hline +0x026 & DAC$\_$C board 0 crate 0 & see FTU documentation \\\hline +0x027 & DAC$\_$D board 0 crate 0 & see FTU documentation \\\hline +0x028 & DAC$\_$H board 0 crate 0 & see FTU documentation \\\hline +0x029 & Prescaling board 0 crate 0 & (value+1)/2~[s], also autosend period \\\hline +0x02A & enables patch 0 board 1 crate 0 & see FTU documentation \\\hline +0x02B & enables patch 1 board 1 crate 0 & see FTU documentation \\\hline +0x02C & enables patch 2 board 1 crate 0 & see FTU documentation \\\hline +0x02D & enables patch 3 board 1 crate 0 & see FTU documentation \\\hline +0x02E & DAC$\_$A board 1 crate 0 & see FTU documentation \\\hline +0x02F & DAC$\_$B board 1 crate 0 & see FTU documentation \\\hline +0x030 & DAC$\_$C board 1 crate 0 & see FTU documentation \\\hline +0x031 & DAC$\_$D board 1 crate 0 & see FTU documentation \\\hline +0x032 & DAC$\_$H board 1 crate 0 & see FTU documentation \\\hline +0x033 & Prescaling board 1 crate 0 & see FTU documentation \\\hline +... & ... & \\\hline +0x1A6 & enables patch 0 board 9 crate 3 & see FTU documentation \\\hline +0x1A7 & enables patch 1 board 9 crate 3 & see FTU documentation \\\hline +0x1A8 & enables patch 2 board 9 crate 3 & see FTU documentation \\\hline +0x1A9 & enables patch 3 board 9 crate 3 & see FTU documentation \\\hline +0x1AA & DAC$\_$A board 9 crate 3 & see FTU documentation \\\hline +0x1AB & DAC$\_$B board 9 crate 3 & see FTU documentation \\\hline +0x1AC & DAC$\_$C board 9 crate 3 & see FTU documentation \\\hline +0x1AD & DAC$\_$D board 9 crate 3 & see FTU documentation \\\hline +0x1AE & DAC$\_$H board 9 crate 3 & see FTU documentation \\\hline +0x1AF & Prescaling board 9 crate 3 & see FTU documentation \\\hline +0x1B0 & active FTU list crate 0 & see FTU documentation \\\hline +0x1B1 & active FTU list crate 1 & see FTU documentation \\\hline +0x1B2 & active FTU list crate 2 & see FTU documentation \\\hline +0x1B3 & active FTU list crate 3 & see FTU documentation \\\hline +\caption{Overview of the FTM static data block} +\label{tab:FTM-trigger-master-static-data-block} +\end{longtable} + +The FTM general settings register is detailed in table +\ref{tab:FTM-general-settings-register}. The 'TIM\_CLK' bit defines whether +the time marker is generated by the FPGA ('TIM\_CLK' = 0, default for physics +data taking), or whether it is generated by the clock conditioner ('TIM\_CLK' += 1, e.g. for DRS timing calibration). The 'ext\_veto', 'ext\_trig\_1' and +'ext\_trig\_2' bits enable (1) or disable (0) the NIM inputs for the external +veto and trigger signals, respectively. In order to select which trigger +sources are active during a run, the bits 'LP1', 'LP2', 'ped' and 'trigger' +are foreseen (0 disabled, 1 enabled). During a physics run, for example, +'LP1', 'ped' and 'trigger' should all be set to generate interleaved +calibration and pedestal events as well as activate the 'n-out-of-40' trigger +input. For a didicated pedestal run only 'ped' should be set, since in this +case the FTM sends directly a trigger to the FADs. For calibration runs it +depends on whether the external (LP1) or internal (LP2) light pulser is used: +For the first case 'LP1' and 'trigger' have to be set, since here the full +trigger chain is involved and the camera triggers based on G-APD signals. +For the second case only 'LP2' is needed, because the shutter is closed and the +FTM sends the trigger signal directly to the FADs (like for pedestal +events). Bits 8 to 15 of the general settings register are not used up to now. + + +\begin{table}[h] +\centering +\begin{small} +\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|}\hline +Bit & 15...8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\\hline +Content & x & trigger & ped & LP2 & LP1 & ext\_trig\_2 & ext\_trig\_1& ext\_veto & TIM\_CLK \\\hline +\end{tabular} +\end{small} +\caption{FTM general settings register} +\label{tab:FTM-general-settings-register} +\end{table} + +%\begin{table}[!h] +%\centering +%\begin{tabular}{|l|l|}\hline +%TIM\_CClk & description \\\hline\hline +%0 & Time marker generated in the FPGA \\\hline +%1 & Time marker generated by the clock conditioner \\\hline +%\end{tabular} +%\caption{FTM Time marker indication} +%\label{tab:FTM-Time-marker-indication} +%\end{table} + +%\begin{table}[!h] +%\centering +%\begin{tabular}{|l|l|}\hline +%ena$\_$ext$\_$Veto & description \\\hline\hline +%0 & disable external trigger veto\\\hline +%1 & enable external trigger veto \\\hline +%\end{tabular} +%\caption{FTM external trigger} +%\label{tab:FTM-external-trigger} +%\end{table} + +%\begin{table}[!h] +%\centering +%\begin{tabular}{|l||l|}\hline +%ena\_LP1 & description \\\hline\hline +%0 & disable light pulser 1 \\\hline +%1 & enable light pulser 1\\\hline +%\end{tabular} +%\caption{FTM light pulser 1} +%\label{tab:FTM-light-pulser-1} +%\end{table} + +%\begin{table}[!h] +%\centering +%\begin{tabular}{|l||l|}\hline +%ena\_LP2 & description \\\hline\hline +%0 & disable light pulser 2 \\\hline +%1 & enable light pulser 2 \\\hline +%\end{tabular} +%\caption{FTM light pulser 2} +%\label{tab:FTM-light-pulser-2} +%\end{table} + +%\begin{table}[!h] +%\centering +%\begin{tabular}{|l||l|}\hline +%ena\_Ped & description \\\hline\hline +%0 & disable interleaved pedestal trigger \\\hline +%1 & enable interleaved pedestal trigger \\\hline +%\end{tabular} +%\caption{FTM interleaved pedestals} +%\label{tab:FTM-interleaved-pedestals} +%\end{table} + +%\begin{table}[!h] +%\centering +%\begin{small} +%\begin{tabular}{|l||l|}\hline +%ena\_LLC & description \\\hline\hline +%0 & disable low level calibration pulses \\\hline +%1 & enable low level calibration pulses \\\hline +%\end{tabular} +%\end{small} +%\caption{FTM low level calibration pulses} +%\label{tab:FTM-low-level-calibration-pulses} +%\end{table} + +The 'on-board status LEDs' register shown in table \ref{tab:FTM-LED-register} +allows to switch a total of eight LEDs on the FTM board for debugging purposes +by setting the corresponding bit high. + +\begin{table}[h] +\centering +\begin{small} +\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|}\hline +Bit & 15...8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\\hline +Content & x & red$\_$3 & red$\_$2 & gn$\_$1 & ye$\_$1 & red$\_$1 & gn$\_$0 & ye$\_$0 & red$\_$0 \\\hline +\end{tabular} +\end{small} +\caption{'on-board status LEDs' register} +\label{tab:FTM-LED-register} +\end{table} + +The period (time distance, see table \ref{tab:FTM-frequency-register}), with +which light pulser and pedestal triggers are sent, is stored in the register +at address 0x002. It is given in [ms] and adjustable between 1\,ms and +1023\,ms (10 bits used). The next register defines the sequence of LP1, LP2 +and pedestal events (see table \ref{tab:FTM-ratio-register}). + +\begin{table}[h] +\centering +\begin{small} +\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline +Bit & 15 - 10 & 9 & 8 & ... & 2 & 1 & 0 \\\hline +Content & x & PERIOD\_9 & PERIOD\_8 & ... & PERIOD\_2 & PERIOD\_1 & PERIOD\_0 \\\hline +\end{tabular} +\end{small} +\caption{Register for the period [ms] of calibration and pedestal events} +\label{tab:FTM-frequency-register} +\end{table} + +\begin{table}[h] +\centering +\begin{small} +\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|}\hline +Bit & 15 & 14 & ... & 10 & 9 & ... & 5 & 4 & ... & 0 \\\hline +Content & x & ped\_S4 & ... & ped\_S0 & LP2\_S4 & ... & LP2\_S0 & LP1\_S4 & ... & LP1\_S0 \\\hline +\end{tabular} +\end{small} +\caption{Register defining the sequence of LP1, LP2 and pedestal events; 5 + bits used per value. By setting e.g. LP1/LP2/PED = 3/2/1, the systems + generates 3 LP1 triggers, followed by 2 LP2 triggers, followed by 1 PED + trigger (if they are also activated in the 'general settings' register). + The distance between the triggers is defined with another register + (table~\ref{tab:FTM-frequency-register}).} +\label{tab:FTM-ratio-register} +\end{table} + +%\begin{table}[!h] +%\centering +%\begin{tiny} +%\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|}\hline +%Bit & 15 - 10 & 9 & 8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\\hline +%Function & x & LPR2\_9 & LPR2\_8 & LPR2\_7 & LPR2\_6 & LPR2\_5 & LPR2\_4 & LPR2\_3 & LPR2\_2 & LPR2\_1 & LPR2\_0 \\\hline +%\end{tabular} +%\end{tiny} +%\caption{Light pulser 2 frequency register at address 0x00E: This register contains the pulse rate of the light +% pulser 2 in Hz.} +%\label{tab:Light-pulser-2-frequancy-register} +%\end{table} + +In order to define the amplitude and characteristics of the light pulses that +are generated by the LP1 and the LP2 system, the registers 'LP1 amplitude' and +'LP2 amplitude' are used, respectively. These registers are presented in +table~\ref{tab:LP1-amplitude-register} and table~\ref{tab:LP2-amplitude-register}. +The two most significant bits allow to switch on additional LEDs, while the six +least significant bits are used for the FM (frequency modulation) on the +light pulser board. These six bits (FM1\_5 ... FM1\_0 and FM2\_5 ... FM2\_0, +respectively) are frequency dividing factors and the resulting frequency for the +feedback is $ f_{FM} = \frac{5MHz}{25 + \mid FM1\_5 ... FM1\_0 \mid} $. + +This FM signal is used for stabilizing the amplitude +of the light pulses, see the schematics \cite{FLD-Schematics}. + +The light pulser systems are controlled from the FTM by means of four LVDS control lines: +The first line goes directly to the LED driver circuit and triggers a lightpulse. +The FM signal is on the second line. +The third and forth line allow to switch on additional LEDs. + +\begin{table}[!h] +\centering +\begin{small} +\begin{tabular}{|l|l|l|l|l|}\hline +Bit & 15 & 14 & 13 ... 6 & 5 ... 0 \\\hline +Content & add\_LEDs1\_1& add\_LEDs1\_0 & x & FM1\_5 ... FM1\_0 \\\hline +\end{tabular} +\end{small} +\caption{Light pulser 1 amplitude register} +\label{tab:LP1-amplitude-register} +\end{table} + + +\begin{table}[!h] +\centering +\begin{small} +\begin{tabular}{|l|l|l|l|l|}\hline +Bit & 15 & 14 & 13 ... 6 & 5 ... 0 \\\hline +Content & add\_LEDs2\_1& add\_LEDs2\_0 & x & FM2\_5 ... FM2\_0 \\\hline +\end{tabular} +\end{small} +\caption{Light pulser 2 amplitude register} +\label{tab:LP2-amplitude-register} +\end{table} + +The different settings of the 'n-out-of-40' logic (physics or calibration +events) are stored in two separate registers, which both have a structure +according to table~\ref{tab:FTM-majority}. + +\begin{table}[!h] +\centering +\begin{small} +\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline +Bit & 15...6 & 5 & 4 & 3 & 2 &1 & 0 \\\hline +Content & x & n5 & n4 & n3 & n2 & n1 & n0 \\\hline +\end{tabular} +\end{small} +\caption{Structure of the two majority coincidence (n-out-of-40) registers; the binary value + in these registers is the minimum number n of FTU trigger primitives required to trigger an event (physics or calibration)} +\label{tab:FTM-majority} +\end{table} + +In addition, there are several registers in the static data block to define +delays (e.g. for the trigger). Also a general dead time to be applied after +each trigger can be set (to compensate for the delay of the busy line). The +clock conditioner settings are specified at address 0x00D to 0x01C (LMK03000 +from National Semiconductor, for more details see \cite{LMK03000}). + +Starting at address 0x020, the FTU settings are stored. The FTM always holds +the complete FTU parameters in the static data block. For the meaning of these +registers, please refer to the FTU firmware specifications document +\cite{FTUspecs}. The register at address 0x029 is special in the sense that, +in addition to its normal meaning, it also defines the time period with which +the FTU rates are sent automatically to the FTMcontrol software. In case not +all FTUs are connected during e.g. the testing phase, or a FTU is broken, the +'active FTU list' registers can be used to disable certain boards. Bits 9...0 +of one of the active FTU lists (address 0x1B0 to 0x1B3, corresponding to crate +0 to 3) contain the "active" flag for every FTU board. Setting a bit activates +the corresponding FTU board while a "0" deactivates it. + +\section{Dynamic data block} +\label{sec:Dynamic-data-block} +The dynamic data block shown in table \ref{tab:FTM-dynamic-data-block} +contains permanently updated data stored inside the FTM FPGA. It contains the +actual on-time counter reading, the board temperatures (not yet supported) and the trigger rates +measured by the FTUs. The on-board 12-bit temperature +sensors are MAX6662 chips from Maxim Products. For more information about +these components and their data see \cite{MAX6662}. +This data block is updated and sent periodically by the +FTM. Thus the FTMcontrol software receives periodically a corresponding data +package via ethernet. The counting interval of the FTU board 0 on crate 0 +('prescaling' register) defines the period. When sending the dynamic +data block, the header defined in table~\ref{tab:FTM-header} is added at the +beginning. + +\newpage + +% \begin{table}[h] +% \centering +\begin{longtable}[!h]{|l|l|}\hline +word no & content\\\hline\hline +0x000 & on-time counter at read-out time bits 63...48, filled up with zeros \\\hline +0x001 & on-time counter at read-out time bits 47...32 \\\hline +0x002 & on-time counter at read-out time bits 31...16 \\\hline +0x003 & on-time counter at read-out time bits 15...0 \\\hline +% 0x004 & temperature sensor 0: component U45 on the FTM schematics \cite{FTM-Schematics}\\\hline +% 0x005 & temperature sensor 1: U46 \\\hline +% 0x006 & temperature sensor 2: U48 \\\hline +% 0x007 & temperature sensor 3: U49 \\\hline +0x004 & temperature sensor 0: not used so far\\\hline +0x005 & temperature sensor 1: not used so far\\\hline +0x006 & temperature sensor 2: not used so far\\\hline +0x007 & temperature sensor 3: not used so far\\\hline +0x008 & rate counter bit 29...16 patch 0 board 0 crate 0 \\\hline +0x009 & rate counter bit 15...0 patch 0 board 0 crate 0 \\\hline +0x00A & rate counter bit 29...16 patch 1 board 0 crate 0 \\\hline +0x00B & rate counter bit 15...0 patch 1 board 0 crate 0 \\\hline +0x00C & rate counter bit 29...16 patch 2 board 0 crate 0 \\\hline +0x00D & rate counter bit 15...0 patch 2 board 0 crate 0 \\\hline +0x00E & rate counter bit 29...16 patch 3 board 0 crate 0 \\\hline +0x00F & rate counter bit 15...0 patch 3 board 0 crate 0 \\\hline +0x010 & rate counter bit 29...16 total board 0 crate 0 \\\hline +0x011 & rate counter bit 15...0 total board 0 crate 0\\\hline +0x012 & Overflow register board 0 crate 0 \\\hline +0x013 & CRC-error register board 0 crate 0 \\\hline +0x014 & rate counter bit 29...16 patch 0 board 1 crate 0 \\\hline +0x015 & rate counter bit 15...0 patch 0 board 1 crate 0 \\\hline +0x016 & rate counter bit 29...16 patch 1 board 1 crate 0 \\\hline +0x017 & rate counter bit 15...0 patch 1 board 1 crate 0 \\\hline +0x018 & rate counter bit 29...16 patch 2 board 1 crate 0 \\\hline +0x019 & rate counter bit 15...0 patch 2 board 1 crate 0 \\\hline +0x01A & rate counter bit 29...16 patch 3 board 1 crate 0 \\\hline +0x01B & rate counter bit 15...0 patch 3 board 1 crate 0 \\\hline +0x01C & rate counter bit 29...16 total board 1 crate 0 \\\hline +0x01D & rate counter bit 15...0 total board 1 crate 0 \\\hline +0x01E & Overflow register board 1 crate 0 \\\hline +0x01F & CRC-error register board 1 crate 0 \\\hline +... & ... \\\hline +0x1E7 & CRC-error register board 9 crate 3 \\\hline +% \end{longtable} +\caption{FTM dynamic data block} +\label{tab:FTM-dynamic-data-block} +\end{longtable} + +%\section{Trigger-list} +%\label{sec:trigger-list} +%The FTM board records all triggers in a list, the so-called trigger-list. +%This trigger-list comprises a maximum of 50 triggers. The first eleven words +%are the same as in the static- and dynamic data block. During data-taking-, +%calibration- and trigger runs, the Trigger-list is automatically sent to the +%main control each time the 50 triggers are reached or the run is finished. In +%addition, the Trigger-list can also be read-out by the main control with the +%according command. In case the run finishes or is terminated, as well as when +%read out manually, the trigger list might be shorter than 50 events. + +%% \begin{table}[h] +%% \centering +%\begin{longtable}[h]{|l|l|}\hline +%address & content\\\hline\hline +%0x000 & board ID bit 63 - 48 \\\hline +%0x001 & board ID bit 47 - 32\\\hline +%0x002 & board ID bit 31 - 16\\\hline +%0x003 & board ID bit 15 - 0\\\hline +%0x004 & firmware ID \\\hline +%0x005 & Trigger counter at read-out time bits 31 .. 16 \\\hline +%0x006 & Trigger counter at read-out time bits 15 .. 0\\\hline +%0x007 & Time stamp counter at read-out time bits 47 .. 32 \\\hline +%0x008 & Time stamp counter at read-out time bits 31 .. 16 \\\hline +%0x009 & Time stamp counter at read-out time bits 15 .. 0 \\\hline +%0x00A & spare \\\hline + +%0x00B & on-time counter at read-out time bits 47 .. 32 \\\hline +%0x00C & on-time counter at read-out time bits 31 .. 16 \\\hline +%0x00D & on-time counter at read-out time bits 15 .. 0 \\\hline + +%0x00E & 1st event Trigger-ID \\\hline +%0x00F & 1st event Trigger-ID \\\hline +%0x010 & 1st event Trigger-ID \\\hline +%0x011 & 1st event Trigger primitives crate 0 \\\hline +%0x012 & 1st event Trigger primitives crate 1 \\\hline +%0x013 & 1st event Trigger primitives crate 2 \\\hline +%0x014 & 1st event Trigger primitives crate 3 \\\hline +%0x015 & 1st event Time stamp counter at trigger time bits 47 .. 32 \\\hline +%0x016 & 1st event Time stamp counter at trigger time bits 31 .. 16 \\\hline +%0x017 & 1st event Time stamp counter at trigger time bits 15 .. 0 \\\hline + +%0x018 & 2nd event Trigger-ID \\\hline +%0x019 & 2nd event Trigger-ID \\\hline +%0x01A & 2nd event Trigger-ID \\\hline +%0x01B & 2nd event Trigger primitives crate 0 \\\hline +%0x01C & 2nd event Trigger primitives crate 1 \\\hline +%0x01D & 2nd event Trigger primitives crate 2 \\\hline +%0x01E & 2nd event Trigger primitives crate 3 \\\hline +%0x01F & 2nd event Time stamp counter at trigger time bits 47 .. 32 \\\hline +%0x020 & 2nd event Time stamp counter at trigger time bits 31 .. 16 \\\hline +%0x021 & 2nd event Time stamp counter at trigger bits 15 .. 0 \\\hline +%... & ...\\\hline +%0x1F8 & 50th event Trigger-ID \\\hline +%0x1F9 & 50th event Trigger-ID \\\hline +%0x1FA & 50th event Trigger-ID \\\hline +%0x1FB & 50th event Trigger primitives crate 0 \\\hline +%0x1FC & 50th event Trigger primitives crate 1 \\\hline +%0x1FD & 50th event Trigger primitives crate 2 \\\hline +%0x1FE & 50th event Trigger primitives crate 3 \\\hline +%0x1FF & 50th event Time stamp counter at trigger time bits 47 .. 32 \\\hline +%0x200 & 50th event Time stamp counter at trigger time bits 31 .. 16 \\\hline +%0x201 & 50th event Time stamp counter at trigger bits 15 .. 0 \\\hline + +%% \end{longtable} +%\caption{FTM trigger list} +%\label{tab:FTM-trigger-list} +%\end{longtable} + +\section{FTU list} +\label{sec:FTU-List} +When the FTM board receives the 'ping all FTUs' instruction, it sends a ping +command to all FTU boards and gathers the FTU boards responses to a list. This +list is called 'FTU list' and shown in table \ref{tab:FTU-list}. When the FTU +list is complete, it is sent back via ethernet with the header defined in +table~\ref{tab:FTM-header}. + +\begin{longtable}[!h]{|l|l|}\hline +address & content\\\hline\hline +0x000 & total number of responding FTU boards\\\hline +0x001 & number of responding FTU boards belonging to crate 0 \\\hline +0x002 & number of responding FTU boards belonging to crate 1 \\\hline +0x003 & number of responding FTU boards belonging to crate 2 \\\hline +0x004 & number of responding FTU boards belonging to crate 3 \\\hline +0x005 & active FTU list crate 0 \\\hline +0x006 & active FTU list crate 1 \\\hline +0x007 & active FTU list crate 2 \\\hline +0x008 & active FTU list crate 3 \\\hline +0x009 & address of first FTU board and number of sent pings until response\\\hline +0x00A & DNA of first FTU board bit 63 ... 48\\\hline +0x00B & DNA of first FTU board bit 47 ... 32\\\hline +0x00C & DNA of first FTU board bit 31 ... 16\\\hline +0x00D & DNA of first FTU board bit 15 ... 0\\\hline +0x00E & CRC error counter reading of first FTU board\\\hline +0x00F & address of second FTU board and number of sent pings until response\\\hline +0x010 & DNA of second FTU board bit 63 ... 48\\\hline +0x011 & DNA of second FTU board bit 47 ... 32\\\hline +0x012 & DNA of second FTU board bit 31 ... 16\\\hline +0x013 & DNA of second FTU board bit 15 ... 0\\\hline +0x014 & CRC error counter reading of second FTU board\\\hline +... & ...\\\hline +0x0F8 & CRC error counter reading of last FTU board\\\hline +\caption{FTU list} +\label{tab:FTU-list} +\end{longtable} + +In case there is no response to a 'ping' for a certain FTU address, there are +up to two repetitions. If there is still no answer, only zeros are written +into the FTU list for this particular board. A responding FTU board gets a +regular entry, including the number of 'ping' sent until response. The number +of pings is coded together with the FTU board address as shown in table +\ref{tab:FTU-crate-number-and-address}. The two bits 'pings\_0' and 'pings\_1' +contain the number of 'pings' until response of an FTU board (coded in +binary). The 'DNA' of the FTU board is the device DNA \cite{ds557, ds610, + wp267, wp266} of the FPGA on the responding FTU board. This is a unique 57 +bit serial number unambiguously identifying every Xilinx FPGA. In the most +significant word (bit 63 ... 48) bits 63 down to 57 are filled with zeros. + +\begin{table}[!h] +\centering +\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|}\hline +Bit & 15 ... 10 & 9 & 8 & 7 & 6 & 5 & ... & 0 \\\hline +Content & x ... x & pings\_1 & pings\_0 & x & x & A5 & ... & A0 \\\hline +\end{tabular} +\caption{Address of FTU board and number of pings until response. In case + there is no response at all, this number is set to 0.} +\label{tab:FTU-crate-number-and-address} +\end{table} + +\chapter{FTU communication error handling} +\label{cha:Error-handling} + +When the FTM board is communicating with a FTU board via RS-485, the FTU board +has to respond within 2\,ms (after the last byte was transmitted). If this +timeout expires, or the response sent back by the FTU board is incorrect, the +FTM resends the datapacket after the timeout. If this second attempt is still +unsuccessful, a third and last attempt will be made by the FTM board. An error +message will be sent to the FTMcontrol whenever a FTU board does not send a +correct answer after the first call by the FTM board. This message (see +table~\ref{tab:error-message}) contains, after the standard header (see +table~\ref{tab:FTM-header}), the number of calls until response (0 if no +response at all), and the corresponding data packet which was sent to the FTU +board. In order to avoid massive error messages for e.g. test setups with +single FTUs, the 'active FTU list' can be employed to disable FTUs from the +bus. In that case the FTM will not try to contact the corresponding boards. + +\begin{table}[!h] + \centering + \begin{tabular}{|l|l|}\hline + word no & content\\\hline\hline + 0x000 & number of calls until response (0 if no response at all)\\\hline + 0x001 ... 0x01C & slow control data packet sent to FTU (28 words/bytes)\\\hline + \end{tabular} + \caption{FTU communication error message (after standard header); for a + description of the FTU data package, see \cite{FTUspecs}.} + \label{tab:error-message} +\end{table} + +%--------------------------------------------------------------------------------- + +\bibliographystyle{unsrt} +%\bibliography{FTM-Com} + +\begin{thebibliography}{1} + +\bibitem{DRS4} +Paul Scherrer Institut PSI. +\newblock {\em DRS4 9 Channel, 5 GSPS Switched Capacitor Array}. +\newblock http://drs.web.psi.ch +\newblock datasheet. + +\bibitem{LMK03000} +National Semiconductor Corporation. +\newblock {\em LMK03000 Family Precision Clock Conditioner with integrated + VCO}, 2008. +\newblock datasheet. + +\bibitem{FTM-Schematics} +ETH Z{\"u}rich, IPP. +\newblock {\em FTM Schematics}, 2010. + +\bibitem{W5300} +WIZnet Co.Ltd. +\newblock {\em W5300 Fully Hardwired Network protocol Embedded Ethernet + Controller}, 2008. +\newblock datasheet. + +\bibitem{ds557} +Xilinx. +\newblock {\em Spartan-3AN FPGA Family Data Sheet}, 2009. + +\bibitem{ds610} +Xilinx. +\newblock {\em Spartan-3A DSP FPGA Family: Data Sheet}, 2009. + +\bibitem{wp267} +Xilinx. +\newblock {\em Advanced Security Schemes for Spartan-3A/3AN/3A DSP FPGAs}, + 2007. + +\bibitem{wp266} +Xilinx. +\newblock {\em Security Solutions Using Spartan-3 Generation FPGAs}, 2008. + +\bibitem{MAX6662} +Maxim Integrated Products. +\newblock {\em 12-Bit plus Sign Temperature Sensor with SPI-Compatible Serial + Interface MAX6662}, 2001. +\newblock datasheet. + +\bibitem{FTUspecs} +ETH Z{\"u}rich, IPP. +\newblock {\em FTU Firmware Specifications v3}, 2010. + + +\bibitem{FLD-Schematics} +ETH Z{\"u}rich, IPP. +\newblock {\em FLD Schematics, FACT light driver}, 2010. + + +\end{thebibliography} + +\end{document} Index: /firmware/FTM/doc/v5.1/FTM_firmware_specs_v5-1.toc =================================================================== --- /firmware/FTM/doc/v5.1/FTM_firmware_specs_v5-1.toc (revision 14288) +++ /firmware/FTM/doc/v5.1/FTM_firmware_specs_v5-1.toc (revision 14288) @@ -0,0 +1,8 @@ +\contentsline {chapter}{\numberline {1}Introduction}{2} +\contentsline {chapter}{\numberline {2}Trigger-ID}{4} +\contentsline {chapter}{\numberline {3}FTM Commands}{6} +\contentsline {chapter}{\numberline {4}FTM data blocks}{10} +\contentsline {section}{\numberline {4.1}Static data block}{10} +\contentsline {section}{\numberline {4.2}Dynamic data block}{14} +\contentsline {section}{\numberline {4.3}FTU list}{16} +\contentsline {chapter}{\numberline {5}FTU communication error handling}{18}