Index: /FPGA/FTU/FTU_top.vhd
===================================================================
--- /FPGA/FTU/FTU_top.vhd	(revision 156)
+++ /FPGA/FTU/FTU_top.vhd	(revision 157)
@@ -28,23 +28,50 @@
 --use UNISIM.VComponents.all;
 
+
+
 entity FTU_top is
   port(
-    ext_clk   : IN  STD_LOGIC;                     --external clock from FTU board
-    brd_add   : IN  STD_LOGIC_VECTOR(7 downto 0);  --global board address
-    patch1    : IN  STD_LOGIC;                     --logic signal from first trigger patch
-    patch2    : IN  STD_LOGIC;                     --logic signal from second trigger patch
-    patch3    : IN  STD_LOGIC;                     --logic signal from third trigger patch
-    patch4    : IN  STD_LOGIC;                     --logic signal from fourth trigger patch
-    trig_prim : IN  STD_LOGIC;                     --logic signal from n-out-of-4 circuit
-    miso      : IN  STD_LOGIC;                     --serial data from DAC
-    rx        : IN  STD_LOGIC;                     --serial data from FTM
-    enables   : OUT STD_LOGIC_VECTOR(35 downto 0); --individual enables for analog inputs
-    clr       : OUT STD_LOGIC;                     --clear signal to DAC
-    cs_ld     : OUT STD_LOGIC;                     --chip select or load to DAC
-    sck       : OUT STD_LOGIC;                     --serial clock to DAC
-    mosi      : OUT STD_LOGIC;                     --serial data to DAC
-    tx        : OUT STD_LOGIC                      --serial data to FTM
+    -- global control 
+    ext_clk   : IN  STD_LOGIC;                      -- external clock from FTU board
+    reset     : in  STD_LOGIC;                      -- reset
+    brd_add   : IN  STD_LOGIC_VECTOR(7 downto 0);   -- global board address
+
+    -- rate counters LVDS inputs
+    -- use IBUFDS differential input buffer
+    patch_A_p     : IN  STD_LOGIC;                  -- logic signal from first trigger patch
+    patch_A_n     : IN  STD_LOGIC;           
+    patch_B_p     : IN  STD_LOGIC;                  -- logic signal from second trigger patch
+    patch_B_n     : IN  STD_LOGIC;
+    patch_C_p     : IN  STD_LOGIC;                  -- logic signal from third trigger patch
+    patch_C_n     : IN  STD_LOGIC;
+    patch_D_p     : IN  STD_LOGIC;                  -- logic signal from fourth trigger patch
+    patch_D_n     : IN  STD_LOGIC;
+    trig_prim_p   : IN  STD_LOGIC;                  -- logic signal from n-out-of-4 circuit
+    trig_prim_n   : IN  STD_LOGIC;
+    
+    -- DAC interface
+    -- miso          : IN  STD_LOGIC;                  -- master-in-slave-out
+    sck           : OUT STD_LOGIC;                  -- serial clock to DAC
+    mosi          : OUT STD_LOGIC;                  -- serial data to DAC, master-out-slave-in
+    clr           : OUT STD_LOGIC;                  -- clear signal to DAC
+    cs_ld         : OUT STD_LOGIC;                  -- chip select or load to DAC
+    
+    -- RS-485 interface to FTM
+    rx            : IN  STD_LOGIC;                  -- serial data from FTM
+    tx            : OUT STD_LOGIC;                  -- serial data to FTM
+    rx_en         : OUT STD_LOGIC;                  -- enable RS-485 receiver
+    tx_en         : OUT STD_LOGIC;                  -- enable RS-485 transmitter
+
+    -- analog buffer enable
+    enables_A   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
+    enables_B   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
+    enables_C   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
+    enables_D   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
+
+    -- testpoints
+    TP_A       : out STD_LOGIC_VECTOR(7 downto 0)   -- testpoints    
   );
 end FTU_top;
+
 
 architecture Behavioral of FTU_top is
@@ -86,5 +113,5 @@
   clk_sig   <= ext_clk;
   reset_sig <= '0';--where to get this from?
-  miso_sig  <= miso;
+  -- miso_sig  <= miso;
 
   clr   <= clr_sig;