Index: /FPGA/FTU/FTU_top.vhd
===================================================================
--- /FPGA/FTU/FTU_top.vhd	(revision 206)
+++ /FPGA/FTU/FTU_top.vhd	(revision 207)
@@ -29,11 +29,9 @@
 
 
-
 entity FTU_top is
   port(
     -- global control 
     ext_clk   : IN  STD_LOGIC;                      -- external clock from FTU board
-    reset     : in  STD_LOGIC;                      -- reset
-    brd_add   : IN  STD_LOGIC_VECTOR(7 downto 0);   -- global board address
+    brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- global board address
 
     -- rate counters LVDS inputs
@@ -51,5 +49,4 @@
     
     -- DAC interface
-    -- miso          : IN  STD_LOGIC;                  -- master-in-slave-out
     sck           : OUT STD_LOGIC;                  -- serial clock to DAC
     mosi          : OUT STD_LOGIC;                  -- serial data to DAC, master-out-slave-in
@@ -70,5 +67,5 @@
 
     -- testpoints
-    TP_A       : out STD_LOGIC_VECTOR(7 downto 0)   -- testpoints    
+    TP_A        : out STD_LOGIC_VECTOR(11 downto 0)   -- testpoints    
   );
 end FTU_top;
@@ -99,28 +96,15 @@
   end component;
 
-  signal clk_sig   : STD_LOGIC;
-  signal reset_sig : STD_LOGIC;
-  signal miso_sig  : STD_LOGIC;
-  signal clr_sig   : STD_LOGIC;
-  signal mosi_sig  : STD_LOGIC;
-  signal sck_sig   : STD_LOGIC;
-  signal cs_ld_sig : STD_LOGIC;    
+  signal reset_sig : STD_LOGIC := '0';  -- initialize reset to 0 at power up 
+  signal clk_5M_sig : STD_LOGIC;
 
-  signal clk_5M_sig : STD_LOGIC;
+  type FTU_top_StateType is (Init, Running, Reset);
+  signal FTU_top_State, FTU_top_NextState: FTU_top_StateType;
   
 begin
 
-  clk_sig   <= ext_clk;
-  reset_sig <= '0';--where to get this from?
-  -- miso_sig  <= miso;
-
-  clr   <= clr_sig;
-  mosi  <= mosi_sig;
-  sck   <= sck_sig;
-  cs_ld <= cs_ld_sig;
-
   Inst_FTU_dac_dcm : FTU_dac_dcm
     port map(
-      CLKIN_IN => clk_sig,
+      CLKIN_IN => ext_clk,
       RST_IN => reset_sig,
       CLKFX_OUT => clk_5M_sig,
@@ -133,11 +117,34 @@
       clk   => clk_5M_sig,
       reset => reset_sig,
-      miso  => miso_sig,
-      clr   => clr_sig,
-      mosi  => mosi_sig,
-      sck   => sck_sig,
-      cs_ld => cs_ld_sig      
+      miso  => '0',
+      clr   => clr,
+      mosi  => mosi,
+      sck   => sck,
+      cs_ld => cs_ld      
     );
 
+  --FTU main state machine (two-process implementation)
+
+  FTU_top_Registers: process (ext_clk)
+  begin
+    if Rising_edge(ext_clk) then
+      FTU_top_State <= FTU_top_NextState;
+    end if;
+  end process FTU_top_Registers;
+
+  FTU_top_C_logic: process (FTU_top_State)
+  begin
+    FTU_top_NextState <= FTU_top_State;
+    case FTU_top_State is
+      when Init =>
+        reset_sig <= '0';
+        FTU_top_NextState <= Running;
+      when Running =>
+      when Reset =>
+        reset_sig <= '1';
+        FTU_top_NextState <= Init;
+    end case;
+  end process FTU_top_C_logic;
+  
 end Behavioral;
 
Index: /FPGA/FTU/FTU_top_tb.vhd
===================================================================
--- /FPGA/FTU/FTU_top_tb.vhd	(revision 206)
+++ /FPGA/FTU/FTU_top_tb.vhd	(revision 207)
@@ -42,6 +42,5 @@
       -- global control
       ext_clk   : IN  STD_LOGIC;                      -- external clock from FTU board
-      reset     : in  STD_LOGIC;                      -- reset
-      brd_add   : IN  STD_LOGIC_VECTOR(7 downto 0);   -- global board address
+      brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- global board address
 
       -- rate counters LVDS inputs
@@ -59,5 +58,4 @@
 
       -- DAC interface
-      -- miso          : IN  STD_LOGIC;                  -- master-in-slave-out
       sck           : OUT STD_LOGIC;                  -- serial clock to DAC
       mosi          : OUT STD_LOGIC;                  -- serial data to DAC, master-out-slave-in
@@ -78,5 +76,5 @@
 
       -- testpoints
-      TP_A       : out STD_LOGIC_VECTOR(7 downto 0)   -- testpoints
+      TP_A       : out STD_LOGIC_VECTOR(11 downto 0)   -- testpoints
     );
   end component;
@@ -84,6 +82,5 @@
   --Inputs
   signal ext_clk     : STD_LOGIC := '0';
-  signal reset       : STD_LOGIC := '0';
-  signal brd_add     : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
+  signal brd_add     : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
   signal patch_A_p   : STD_LOGIC := '0';
   signal patch_A_n   : STD_LOGIC := '0';
@@ -96,5 +93,4 @@
   signal trig_prim_p : STD_LOGIC := '0';
   signal trig_prim_n : STD_LOGIC := '0';
-  -- signal miso        : STD_LOGIC := '0';
   signal rx          : STD_LOGIC := '0';
 
@@ -111,5 +107,5 @@
   signal rx_en     : STD_LOGIC;
   signal tx_en     : STD_LOGIC;
-  signal TP_A      : STD_LOGIC_VECTOR(7 downto 0);
+  signal TP_A      : STD_LOGIC_VECTOR(11 downto 0);
   
   -- Clock period definitions
@@ -122,5 +118,4 @@
     port map(
       ext_clk     => ext_clk,
-      reset       => reset,
       brd_add     => brd_add,
       patch_A_p   => patch_A_p,
@@ -134,5 +129,4 @@
       trig_prim_p => trig_prim_p,
       trig_prim_n => trig_prim_n,
-      -- miso        => miso,
       rx          => rx,
       rx_en       => rx_en,