Index: FPGA/FAD/FACT_FAD_TB_lib/hdl/adc_controller_beha.vhd =================================================================== --- FPGA/FAD/FACT_FAD_TB_lib/hdl/adc_controller_beha.vhd (revision 215) +++ FPGA/FAD/FACT_FAD_TB_lib/hdl/adc_controller_beha.vhd (revision 215) @@ -0,0 +1,37 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.adc_controller.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 13:46:10 25.03.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +ENTITY adc_controller IS + PORT( + adc_oeb : OUT STD_LOGIC + ); + +-- Declarations + +END adc_controller ; + +ARCHITECTURE beha OF adc_controller IS +BEGIN + + start_adc_proc: process + begin + adc_oeb <= '1'; + wait for 1 us; + wait for 10 ns; + adc_oeb <= '0'; + wait; + end process start_adc_proc; + +END ARCHITECTURE beha; + Index: FPGA/FAD/FACT_FAD_TB_lib/hdl/clock_generator.vhd =================================================================== --- FPGA/FAD/FACT_FAD_TB_lib/hdl/clock_generator.vhd (revision 215) +++ FPGA/FAD/FACT_FAD_TB_lib/hdl/clock_generator.vhd (revision 215) @@ -0,0 +1,63 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:40:20 01/07/2010 +-- Design Name: +-- Module Name: clock_generator - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +-- hds interface_start +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- synthesis translate_off +entity clock_generator is + generic( + clock_period : time := 20 ns; + reset_time : time := 50 ns + ); + port( + clk : out STD_LOGIC := '0'; + rst : out STD_LOGIC := '0' + ); + +-- Declarations + +end clock_generator ; +-- hds interface_end + +architecture Behavioral of clock_generator is + +begin + + clock_gen_proc: process + begin + clk <= '0'; + wait for clock_period / 2; + clk <= '1'; + wait for clock_period / 2; + end process clock_gen_proc; + + reset_gen_proc: process + begin + rst <= '1'; + wait for reset_time; + rst <= '0'; + wait; + end process reset_gen_proc; + + +end Behavioral; +--synthesis translate_on Index: FPGA/FAD/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd =================================================================== --- FPGA/FAD/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd (revision 215) +++ FPGA/FAD/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd (revision 215) @@ -0,0 +1,160 @@ +-- VHDL Entity FACT_FAD_TB_lib.FAD_main_TB.symbol +-- +-- Created: +-- by - kai.UNKNOWN (E5PCXX) +-- at - 16:53:17 07.05.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.NUMERIC_STD.all; + +ENTITY FAD_main_TB IS +-- Declarations + +END FAD_main_TB ; + +-- +-- VHDL Architecture FACT_FAD_TB_lib.FAD_main_TB.struct +-- +-- Created: +-- by - kai.UNKNOWN (E5PCXX) +-- at - 16:53:17 07.05.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.NUMERIC_STD.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +library FACT_FAD_lib; +use FACT_FAD_lib.fad_definitions.all; +USE ieee.std_logic_textio.all; +LIBRARY std; +USE std.textio.all; +LIBRARY FACT_FAD_test_devices_lib; +USE FACT_FAD_test_devices_lib.drs4_pack.all; + +LIBRARY FACT_FAD_lib; +LIBRARY FACT_FAD_TB_lib; + +ARCHITECTURE struct OF FAD_main_TB IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL RSRLOAD : std_logic := '0'; + SIGNAL SRCLK : std_logic := '0'; + SIGNAL addr : std_logic_vector(9 DOWNTO 0); + SIGNAL clk : std_logic; + SIGNAL cs : std_logic := '1'; + SIGNAL data : std_logic_vector(15 DOWNTO 0); + SIGNAL int : std_logic; + SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL rd : std_logic := '1'; + SIGNAL rst : STD_LOGIC; + SIGNAL trigger_in : STD_LOGIC; + SIGNAL wiz_reset : std_logic := '1'; + SIGNAL wr : std_logic := '1'; + + + -- Component Declarations + COMPONENT FAD_Testboard + PORT ( + clk : IN STD_LOGIC ; + trigger : IN STD_LOGIC ; + wiz_int : IN std_logic ; + RSRLOAD : OUT std_logic := '0'; + SRCLK : OUT std_logic := '0'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + wiz_addr : OUT std_logic_vector (9 DOWNTO 0); + wiz_cs : OUT std_logic := '1'; + wiz_rd : OUT std_logic := '1'; + wiz_reset : OUT std_logic := '1'; + wiz_wr : OUT std_logic := '1'; + wiz_data : INOUT std_logic_vector (15 DOWNTO 0) + ); + END COMPONENT; + COMPONENT clock_generator + GENERIC ( + clock_period : time := 20 ns; + reset_time : time := 50 ns + ); + PORT ( + clk : OUT STD_LOGIC := '0'; + rst : OUT STD_LOGIC := '0' + ); + END COMPONENT; + COMPONENT simple_trigger + GENERIC ( + TRIGGER_TIME : TIME := 16 us; + PULSE_WIDTH : TIME := 1 us + ); + PORT ( + trigger : OUT std_logic + ); + END COMPONENT; + COMPONENT w5300_emulator + PORT ( + addr : IN std_logic_vector (9 DOWNTO 0); + data : INOUT std_logic_vector (15 DOWNTO 0); + rd : IN std_logic ; + wr : IN std_logic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : FAD_Testboard USE ENTITY FACT_FAD_lib.FAD_Testboard; + FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator; + FOR ALL : simple_trigger USE ENTITY FACT_FAD_TB_lib.simple_trigger; + FOR ALL : w5300_emulator USE ENTITY FACT_FAD_TB_lib.w5300_emulator; + -- pragma synthesis_on + + +BEGIN + + -- Instance port mappings. + I_testboard : FAD_Testboard + PORT MAP ( + clk => clk, + trigger => trigger_in, + wiz_int => int, + RSRLOAD => RSRLOAD, + SRCLK => SRCLK, + led => led, + wiz_addr => addr, + wiz_cs => cs, + wiz_rd => rd, + wiz_reset => wiz_reset, + wiz_wr => wr, + wiz_data => data + ); + I_clock_generator : clock_generator + GENERIC MAP ( + clock_period => 20 ns, + reset_time => 50 ns + ) + PORT MAP ( + clk => clk, + rst => rst + ); + I_trigger : simple_trigger + GENERIC MAP ( + TRIGGER_TIME => 16 us, + PULSE_WIDTH => 1 us + ) + PORT MAP ( + trigger => trigger_in + ); + I_w5300 : w5300_emulator + PORT MAP ( + addr => addr, + data => data, + rd => rd, + wr => wr + ); + +END struct; Index: FPGA/FAD/FACT_FAD_TB_lib/hdl/simple_trigger_beha.vhd =================================================================== --- FPGA/FAD/FACT_FAD_TB_lib/hdl/simple_trigger_beha.vhd (revision 215) +++ FPGA/FAD/FACT_FAD_TB_lib/hdl/simple_trigger_beha.vhd (revision 215) @@ -0,0 +1,47 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.simple_trigger.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 14:01:15 10.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.NUMERIC_STD.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library FACT_FAD_lib; +use FACT_FAD_lib.fad_definitions.all; + +entity simple_trigger is + generic( + TRIGGER_TIME : TIME := 16 us; + PULSE_WIDTH : TIME := 1 us + ); + port( + trigger : out std_logic + ); + +-- Declarations + +end simple_trigger ; + + +architecture beha of simple_trigger is +begin + + trigger_proc: process + begin + trigger <= '0'; + wait for TRIGGER_TIME; + trigger <= '1'; + wait for PULSE_WIDTH; + trigger <= '0'; + wait for PULSE_WIDTH; +-- wait; + end process trigger_proc; +end architecture beha; + Index: FPGA/FAD/FACT_FAD_TB_lib/hdl/trigger_counter_beha.vhd =================================================================== --- FPGA/FAD/FACT_FAD_TB_lib/hdl/trigger_counter_beha.vhd (revision 215) +++ FPGA/FAD/FACT_FAD_TB_lib/hdl/trigger_counter_beha.vhd (revision 215) @@ -0,0 +1,43 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.trigger_counter.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 14:36:14 10.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +entity trigger_counter is + port( + trigger_id : out std_logic_vector(47 downto 0); + trigger : in std_logic; + clk : in std_logic + ); + +end entity trigger_counter; + +architecture beha of trigger_counter is + + signal temp_id : integer := 0; + +begin + + trigger_id <= X"AA55" & conv_std_logic_vector(temp_id, 32); + + trigger_incr_proc: process(clk) + begin + if rising_edge(clk) then + if (trigger = '1') then + temp_id <= temp_id + 1; + end if; + end if; + end process trigger_incr_proc; + +end architecture beha; + Index: FPGA/FAD/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd =================================================================== --- FPGA/FAD/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd (revision 215) +++ FPGA/FAD/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd (revision 215) @@ -0,0 +1,86 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.w5300_emulator.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 07:51:36 04.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +entity w5300_emulator is + port( + addr : in std_logic_vector(9 downto 0); + data : inout std_logic_vector(15 downto 0); + rd : in std_logic; + wr : in std_logic + ); +end entity w5300_emulator; + +architecture beha of w5300_emulator is + + signal open_done : std_logic_vector(7 downto 0) := (others => '0'); + signal data_temp : std_logic_vector(15 downto 0); + + signal RSR_0, RSR_1 : std_logic_vector (15 downto 0); + signal FIFOR_CNT : integer := 0; + +begin + + data <= data_temp when (rd = '0') else (others => 'Z'); + data_temp <= data when (wr = '0') else (others => 'Z'); + + set_proc : process + begin + RSR_0 <= X"0000"; + RSR_1 <= X"0000"; + wait for 250 us; + RSR_1 <= X"0001"; + wait for 2 ms; + RSR_1 <= X"0002"; + wait; + end process set_proc; + + w5300_proc : process (addr) + begin + for i in 0 to 7 loop + if (addr = conv_integer(W5300_S0_SSR) + i * 64) then + if (open_done(i) = '0') then + data_temp <= X"0013"; + open_done(i) <= '1'; + else + data_temp <= X"0017"; + end if; + elsif (addr = conv_integer(W5300_S0_TX_FSR) + i * conv_integer(W5300_S_INC)) then + data_temp <= X"0000"; + elsif (addr = conv_integer(W5300_S0_TX_FSR + 2) + i * conv_integer(W5300_S_INC)) then + data_temp <= X"3C00"; + elsif (addr = conv_integer(W5300_S0_RX_RSR)) then + data_temp <= RSR_0; + elsif (addr = conv_integer(W5300_S0_RX_RSR) + 2) then + data_temp <= RSR_1; + elsif (addr = conv_integer(W5300_S0_RX_FIFOR)) then + if (FIFOR_CNT = 0) then + data_temp <= X"A000"; + FIFOR_CNT <= 1; + elsif (FIFOR_CNT = 1) then + data_temp <= X"0500"; + FIFOR_CNT <= 2; + elsif (FIFOR_CNT = 2) then + data_temp <= X"0000"; + end if; + else + null; + end if; + end loop; + end process w5300_proc; + + +end architecture beha; +