Index: FPGA/FAD/FACT_FAD_lib/hdl/DCM_25MHz_38nsPS_BEHAVIORAL.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/DCM_25MHz_38nsPS_BEHAVIORAL.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/DCM_25MHz_38nsPS_BEHAVIORAL.vhd	(revision 215)
@@ -0,0 +1,183 @@
+-- Coregen VHDL wrapper file modified by HDL Designer
+
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
+--------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 10.1.03
+--  \   \         Application : xaw2vhdl
+--  /   /         Filename : DCM_25MHz_38nsPS.vhd
+-- /___/   /\     Timestamp : 03/29/2010 10:34:42
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--Command: xaw2vhdl-st C:\DOKUME~1\FPGA_D~1\LOKALE~1\Temp\coregen_FPGA_Developer\coregen\project\DCM_25MHz_38nsPS.xaw C:\DOKUME~1\FPGA_D~1\LOKALE~1\Temp\coregen_FPGA_Developer\coregen\project\DCM_25MHz_38nsPS
+--Design Name: DCM_25MHz_38nsPS
+--Device: xc3s700a-4fg484
+--
+-- Module DCM_25MHz_38nsPS
+-- Written for synthesis tool: Precision
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+
+entity DCM_25MHz_38nsPS is
+   port ( CLKIN_IN        : in    std_logic; 
+          RST_IN          : in    std_logic; 
+          CLKIN_IBUFG_OUT : out   std_logic; 
+          CLK0_OUT        : out   std_logic; 
+          LOCKED_OUT      : out   std_logic);
+end DCM_25MHz_38nsPS;
+
+architecture BEHAVIORAL of DCM_25MHz_38nsPS is
+
+-- hds translate_off
+
+   attribute CLK_FEEDBACK          : string ;
+   attribute CLKDV_DIVIDE          : string ;
+   attribute CLKFX_DIVIDE          : string ;
+   attribute CLKFX_MULTIPLY        : string ;
+   attribute CLKIN_DIVIDE_BY_2     : string ;
+   attribute CLKIN_PERIOD          : string ;
+   attribute CLKOUT_PHASE_SHIFT    : string ;
+   attribute DESKEW_ADJUST         : string ;
+   attribute DFS_FREQUENCY_MODE    : string ;
+   attribute DLL_FREQUENCY_MODE    : string ;
+   attribute DUTY_CYCLE_CORRECTION : string ;
+   attribute FACTORY_JF            : string ;
+   attribute PHASE_SHIFT           : string ;
+   attribute STARTUP_WAIT          : string ;
+   signal CLKFB_IN        : std_logic;
+   signal CLKIN_IBUFG     : std_logic;
+   signal CLK0_BUF        : std_logic;
+   signal GND_BIT         : std_logic;
+   component IBUFG
+      port ( I : in    std_logic; 
+             O : out   std_logic);
+   end component;
+   
+   component BUFG
+      port ( I : in    std_logic; 
+             O : out   std_logic);
+   end component;
+   
+   component DCM_SP
+      -- synthesis translate_off
+      generic( CLK_FEEDBACK : string :=  "1X";
+               CLKDV_DIVIDE : real :=  2.0;
+               CLKFX_DIVIDE : integer :=  1;
+               CLKFX_MULTIPLY : integer :=  4;
+               CLKIN_DIVIDE_BY_2 : boolean :=  FALSE;
+               CLKIN_PERIOD : real :=  10.0;
+               CLKOUT_PHASE_SHIFT : string :=  "NONE";
+               DESKEW_ADJUST : string :=  "SYSTEM_SYNCHRONOUS";
+               DFS_FREQUENCY_MODE : string :=  "LOW";
+               DLL_FREQUENCY_MODE : string :=  "LOW";
+               DUTY_CYCLE_CORRECTION : boolean :=  TRUE;
+               FACTORY_JF : bit_vector :=  x"C080";
+               PHASE_SHIFT : integer :=  0;
+               STARTUP_WAIT : boolean :=  FALSE;
+               DSS_MODE : string :=  "NONE");
+      -- synthesis translate_on
+      port ( CLKIN    : in    std_logic; 
+             CLKFB    : in    std_logic; 
+             RST      : in    std_logic; 
+             PSEN     : in    std_logic; 
+             PSINCDEC : in    std_logic; 
+             PSCLK    : in    std_logic; 
+             DSSEN    : in    std_logic; 
+             CLK0     : out   std_logic; 
+             CLK90    : out   std_logic; 
+             CLK180   : out   std_logic; 
+             CLK270   : out   std_logic; 
+             CLKDV    : out   std_logic; 
+             CLK2X    : out   std_logic; 
+             CLK2X180 : out   std_logic; 
+             CLKFX    : out   std_logic; 
+             CLKFX180 : out   std_logic; 
+             STATUS   : out   std_logic_vector (7 downto 0); 
+             LOCKED   : out   std_logic; 
+             PSDONE   : out   std_logic);
+   end component;
+   
+   attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X";
+   attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0";
+   attribute CLKFX_DIVIDE of DCM_SP_INST : label is "1";
+   attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "4";
+   attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE";
+   attribute CLKIN_PERIOD of DCM_SP_INST : label is "40.000";
+   attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "FIXED";
+   attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS";
+   attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
+   attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
+   attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE";
+   attribute FACTORY_JF of DCM_SP_INST : label is "C080";
+   attribute PHASE_SHIFT of DCM_SP_INST : label is "243";
+   attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE";
+
+-- hds translate_on
+
+begin
+
+-- hds translate_off
+
+   GND_BIT <= '0';
+   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
+   CLK0_OUT <= CLKFB_IN;
+   CLKIN_IBUFG_INST : IBUFG
+      port map (I=>CLKIN_IN,
+                O=>CLKIN_IBUFG);
+   
+   CLK0_BUFG_INST : BUFG
+      port map (I=>CLK0_BUF,
+                O=>CLKFB_IN);
+   
+   DCM_SP_INST : DCM_SP
+   -- synthesis translate_off
+   generic map( CLK_FEEDBACK => "1X",
+            CLKDV_DIVIDE => 2.0,
+            CLKFX_DIVIDE => 1,
+            CLKFX_MULTIPLY => 4,
+            CLKIN_DIVIDE_BY_2 => FALSE,
+            CLKIN_PERIOD => 40.000,
+            CLKOUT_PHASE_SHIFT => "FIXED",
+            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
+            DFS_FREQUENCY_MODE => "LOW",
+            DLL_FREQUENCY_MODE => "LOW",
+            DUTY_CYCLE_CORRECTION => TRUE,
+            FACTORY_JF => x"C080",
+            PHASE_SHIFT => 243,
+            STARTUP_WAIT => FALSE)
+   -- synthesis translate_on
+      port map (CLKFB=>CLKFB_IN,
+                CLKIN=>CLKIN_IBUFG,
+                DSSEN=>GND_BIT,
+                PSCLK=>GND_BIT,
+                PSEN=>GND_BIT,
+                PSINCDEC=>GND_BIT,
+                RST=>RST_IN,
+                CLKDV=>open,
+                CLKFX=>open,
+                CLKFX180=>open,
+                CLK0=>CLK0_BUF,
+                CLK2X=>open,
+                CLK2X180=>open,
+                CLK90=>open,
+                CLK180=>open,
+                CLK270=>open,
+                LOCKED=>LOCKED_OUT,
+                PSDONE=>open,
+                STATUS=>open);
+   
+
+-- hds translate_on
+
+end BEHAVIORAL;
+
+
+
Index: FPGA/FAD/FACT_FAD_lib/hdl/DCM_25MHz_noPS_BEHAVIORAL.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/DCM_25MHz_noPS_BEHAVIORAL.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/DCM_25MHz_noPS_BEHAVIORAL.vhd	(revision 215)
@@ -0,0 +1,189 @@
+-- Coregen VHDL wrapper file modified by HDL Designer
+
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
+--------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 10.1.03
+--  \   \         Application : xaw2vhdl
+--  /   /         Filename : DCM_25MHz_noPS.vhd
+-- /___/   /\     Timestamp : 03/29/2010 10:36:52
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--Command: xaw2vhdl-st C:/DOKUME~1/FPGA_D~1/LOKALE~1/Temp/coregen_FPGA_Developer/coregen/project/DCM_25MHz_noPS.xaw C:/DOKUME~1/FPGA_D~1/LOKALE~1/Temp/coregen_FPGA_Developer/coregen/project/DCM_25MHz_noPS
+--Design Name: DCM_25MHz_noPS
+--Device: xc3s700a-4fg484
+--
+-- Module DCM_25MHz_noPS
+-- Written for synthesis tool: Precision
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+
+entity DCM_25MHz_noPS is
+   port ( CLKIN_IN        : in    std_logic; 
+          RST_IN          : in    std_logic; 
+          CLKDV_OUT       : out   std_logic; 
+          CLKIN_IBUFG_OUT : out   std_logic; 
+          CLK0_OUT        : out   std_logic; 
+          LOCKED_OUT      : out   std_logic);
+end DCM_25MHz_noPS;
+
+architecture BEHAVIORAL of DCM_25MHz_noPS is
+
+-- hds translate_off
+
+   attribute CLK_FEEDBACK          : string ;
+   attribute CLKDV_DIVIDE          : string ;
+   attribute CLKFX_DIVIDE          : string ;
+   attribute CLKFX_MULTIPLY        : string ;
+   attribute CLKIN_DIVIDE_BY_2     : string ;
+   attribute CLKIN_PERIOD          : string ;
+   attribute CLKOUT_PHASE_SHIFT    : string ;
+   attribute DESKEW_ADJUST         : string ;
+   attribute DFS_FREQUENCY_MODE    : string ;
+   attribute DLL_FREQUENCY_MODE    : string ;
+   attribute DUTY_CYCLE_CORRECTION : string ;
+   attribute FACTORY_JF            : string ;
+   attribute PHASE_SHIFT           : string ;
+   attribute STARTUP_WAIT          : string ;
+   signal CLKDV_BUF       : std_logic;
+   signal CLKFB_IN        : std_logic;
+   signal CLKIN_IBUFG     : std_logic;
+   signal CLK0_BUF        : std_logic;
+   signal GND_BIT         : std_logic;
+   component BUFG
+      port ( I : in    std_logic; 
+             O : out   std_logic);
+   end component;
+   
+   component IBUFG
+      port ( I : in    std_logic; 
+             O : out   std_logic);
+   end component;
+   
+   component DCM_SP
+      -- synthesis translate_off
+      generic( CLK_FEEDBACK : string :=  "1X";
+               CLKDV_DIVIDE : real :=  2.0;
+               CLKFX_DIVIDE : integer :=  1;
+               CLKFX_MULTIPLY : integer :=  4;
+               CLKIN_DIVIDE_BY_2 : boolean :=  FALSE;
+               CLKIN_PERIOD : real :=  10.0;
+               CLKOUT_PHASE_SHIFT : string :=  "NONE";
+               DESKEW_ADJUST : string :=  "SYSTEM_SYNCHRONOUS";
+               DFS_FREQUENCY_MODE : string :=  "LOW";
+               DLL_FREQUENCY_MODE : string :=  "LOW";
+               DUTY_CYCLE_CORRECTION : boolean :=  TRUE;
+               FACTORY_JF : bit_vector :=  x"C080";
+               PHASE_SHIFT : integer :=  0;
+               STARTUP_WAIT : boolean :=  FALSE;
+               DSS_MODE : string :=  "NONE");
+      -- synthesis translate_on
+      port ( CLKIN    : in    std_logic; 
+             CLKFB    : in    std_logic; 
+             RST      : in    std_logic; 
+             PSEN     : in    std_logic; 
+             PSINCDEC : in    std_logic; 
+             PSCLK    : in    std_logic; 
+             DSSEN    : in    std_logic; 
+             CLK0     : out   std_logic; 
+             CLK90    : out   std_logic; 
+             CLK180   : out   std_logic; 
+             CLK270   : out   std_logic; 
+             CLKDV    : out   std_logic; 
+             CLK2X    : out   std_logic; 
+             CLK2X180 : out   std_logic; 
+             CLKFX    : out   std_logic; 
+             CLKFX180 : out   std_logic; 
+             STATUS   : out   std_logic_vector (7 downto 0); 
+             LOCKED   : out   std_logic; 
+             PSDONE   : out   std_logic);
+   end component;
+   
+   attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X";
+   attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0";
+   attribute CLKFX_DIVIDE of DCM_SP_INST : label is "1";
+   attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "4";
+   attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE";
+   attribute CLKIN_PERIOD of DCM_SP_INST : label is "20.000";
+   attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "NONE";
+   attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS";
+   attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
+   attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
+   attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE";
+   attribute FACTORY_JF of DCM_SP_INST : label is "C080";
+   attribute PHASE_SHIFT of DCM_SP_INST : label is "0";
+   attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE";
+
+-- hds translate_on
+
+begin
+
+-- hds translate_off
+
+   GND_BIT <= '0';
+   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
+   CLK0_OUT <= CLKFB_IN;
+   CLKDV_BUFG_INST : BUFG
+      port map (I=>CLKDV_BUF,
+                O=>CLKDV_OUT);
+   
+   CLKIN_IBUFG_INST : IBUFG
+      port map (I=>CLKIN_IN,
+                O=>CLKIN_IBUFG);
+   
+   CLK0_BUFG_INST : BUFG
+      port map (I=>CLK0_BUF,
+                O=>CLKFB_IN);
+   
+   DCM_SP_INST : DCM_SP
+   -- synthesis translate_off
+   generic map( CLK_FEEDBACK => "1X",
+            CLKDV_DIVIDE => 2.0,
+            CLKFX_DIVIDE => 1,
+            CLKFX_MULTIPLY => 4,
+            CLKIN_DIVIDE_BY_2 => FALSE,
+            CLKIN_PERIOD => 20.000,
+            CLKOUT_PHASE_SHIFT => "NONE",
+            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
+            DFS_FREQUENCY_MODE => "LOW",
+            DLL_FREQUENCY_MODE => "LOW",
+            DUTY_CYCLE_CORRECTION => TRUE,
+            FACTORY_JF => x"C080",
+            PHASE_SHIFT => 0,
+            STARTUP_WAIT => FALSE)
+   -- synthesis translate_on
+      port map (CLKFB=>CLKFB_IN,
+                CLKIN=>CLKIN_IBUFG,
+                DSSEN=>GND_BIT,
+                PSCLK=>GND_BIT,
+                PSEN=>GND_BIT,
+                PSINCDEC=>GND_BIT,
+                RST=>RST_IN,
+                CLKDV=>CLKDV_BUF,
+                CLKFX=>open,
+                CLKFX180=>open,
+                CLK0=>CLK0_BUF,
+                CLK2X=>open,
+                CLK2X180=>open,
+                CLK90=>open,
+                CLK180=>open,
+                CLK270=>open,
+                LOCKED=>LOCKED_OUT,
+                PSDONE=>open,
+                STATUS=>open);
+   
+
+-- hds translate_on
+
+end BEHAVIORAL;
+
+
+
Index: FPGA/FAD/FACT_FAD_lib/hdl/adc_buffer_beha.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/adc_buffer_beha.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/adc_buffer_beha.vhd	(revision 215)
@@ -0,0 +1,47 @@
+--
+-- VHDL Architecture FACT_FAD_lib.adc_buffer.beha
+--
+-- Created:
+--          by - kai.UNKNOWN (E5PCXX)
+--          at - 14:57:55 04.05.2010
+--
+-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use ieee.STD_LOGIC_UNSIGNED.all;
+
+library fact_fad_lib;
+use fact_fad_lib.fad_definitions.all;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+USE IEEE.NUMERIC_STD.all;
+USE IEEE.std_logic_signed.all;
+
+ENTITY adc_buffer IS
+   PORT(
+      clk_ps             : IN     std_logic; 
+      adc_data_array     : IN     adc_data_array_type;
+      adc_otr_array      : IN     std_logic_vector (3 DOWNTO 0);
+      adc_data_array_int : OUT    adc_data_array_type;
+      adc_otr            : OUT    std_logic_vector (3 DOWNTO 0)
+   );
+
+-- Declarations
+
+END adc_buffer ;
+
+--
+ARCHITECTURE beha OF adc_buffer IS
+BEGIN
+  adc_buf : process (clk_ps)
+  begin
+    if rising_edge (clk_ps) then
+      adc_data_array_int <= adc_data_array;
+      adc_otr <= adc_otr_array;
+    end if;
+  end process adc_buf;
+END ARCHITECTURE beha;
+
Index: FPGA/FAD/FACT_FAD_lib/hdl/clock_generator_struct.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/clock_generator_struct.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/clock_generator_struct.vhd	(revision 215)
@@ -0,0 +1,95 @@
+-- VHDL Entity FACT_FAD_lib.clock_generator.symbol
+--
+-- Created:
+--          by - kai.UNKNOWN (E5PCXX)
+--          at - 12:09:56 04.05.2010
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY clock_generator IS
+   PORT( 
+      CLK       : IN     std_logic;
+      CLK_25    : OUT    std_logic;
+      CLK_25_PS : OUT    std_logic;
+      CLK_50    : OUT    std_logic
+   );
+
+-- Declarations
+
+END clock_generator ;
+
+--
+-- VHDL Architecture FACT_FAD_lib.clock_generator.struct
+--
+-- Created:
+--          by - kai.UNKNOWN (E5PCXX)
+--          at - 12:09:56 04.05.2010
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.numeric_std.all;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.all;
+
+LIBRARY FACT_FAD_lib;
+
+ARCHITECTURE struct OF clock_generator IS
+
+   -- Architecture declarations
+
+   -- Internal signal declarations
+
+   -- Implicit buffer signal declarations
+   SIGNAL CLK_25_internal : std_logic;
+
+
+   -- Component Declarations
+   COMPONENT dcm_50_to_25
+   PORT (
+      CLKIN_IN        : IN     std_logic;
+      CLK0_OUT        : OUT    std_logic;
+      CLKFX_OUT       : OUT    std_logic;
+      CLKIN_IBUFG_OUT : OUT    std_logic
+   );
+   END COMPONENT;
+   COMPONENT dcm_ps_38ns
+   PORT (
+      CLKIN_IN : IN     std_logic;
+      CLK0_OUT : OUT    std_logic
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : dcm_50_to_25 USE ENTITY FACT_FAD_lib.dcm_50_to_25;
+   FOR ALL : dcm_ps_38ns USE ENTITY FACT_FAD_lib.dcm_ps_38ns;
+   -- pragma synthesis_on
+
+
+BEGIN
+
+   -- Instance port mappings.
+   U_0 : dcm_50_to_25
+      PORT MAP (
+         CLKIN_IN        => CLK,
+         CLKFX_OUT       => CLK_25_internal,
+         CLKIN_IBUFG_OUT => OPEN,
+         CLK0_OUT        => CLK_50
+      );
+   U_1 : dcm_ps_38ns
+      PORT MAP (
+         CLKIN_IN => CLK_25_internal,
+         CLK0_OUT => CLK_25_PS
+      );
+
+   -- Implicit buffered output assignments
+   CLK_25 <= CLK_25_internal;
+
+END struct;
Index: FPGA/FAD/FACT_FAD_lib/hdl/controlRAM_16bit_x256_controlRAM_16bit_x256_a.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/controlRAM_16bit_x256_controlRAM_16bit_x256_a.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/controlRAM_16bit_x256_controlRAM_16bit_x256_a.vhd	(revision 215)
@@ -0,0 +1,139 @@
+-- Coregen VHDL wrapper file modified by HDL Designer
+
+--------------------------------------------------------------------------------
+--     This file is owned and controlled by Xilinx and must be used           --
+--     solely for design, simulation, implementation and creation of          --
+--     design files limited to Xilinx devices or technologies. Use            --
+--     with non-Xilinx devices or technologies is expressly prohibited        --
+--     and immediately terminates your license.                               --
+--                                                                            --
+--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
+--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
+--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
+--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
+--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
+--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
+--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
+--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
+--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
+--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
+--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
+--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
+--     FOR A PARTICULAR PURPOSE.                                              --
+--                                                                            --
+--     Xilinx products are not intended for use in life support               --
+--     appliances, devices, or systems. Use in such applications are          --
+--     expressly prohibited.                                                  --
+--                                                                            --
+--     (c) Copyright 1995-2007 Xilinx, Inc.                                   --
+--     All rights reserved.                                                   --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file controlRAM_16bit_x256.vhd when simulating
+-- the core, controlRAM_16bit_x256. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY controlRAM_16bit_x256 IS
+	port (
+	clka: IN std_logic;
+	dina: IN std_logic_VECTOR(15 downto 0);
+	addra: IN std_logic_VECTOR(7 downto 0);
+	wea: IN std_logic_VECTOR(0 downto 0);
+	douta: OUT std_logic_VECTOR(15 downto 0));
+END controlRAM_16bit_x256;
+
+ARCHITECTURE controlRAM_16bit_x256_a OF controlRAM_16bit_x256 IS
+
+-- hds translate_off
+
+-- synthesis translate_off
+component wrapped_controlRAM_16bit_x256
+	port (
+	clka: IN std_logic;
+	dina: IN std_logic_VECTOR(15 downto 0);
+	addra: IN std_logic_VECTOR(7 downto 0);
+	wea: IN std_logic_VECTOR(0 downto 0);
+	douta: OUT std_logic_VECTOR(15 downto 0));
+end component;
+
+-- Configuration specification 
+	for all : wrapped_controlRAM_16bit_x256 use entity XilinxCoreLib.blk_mem_gen_v2_8(behavioral)
+		generic map(
+			c_has_regceb => 0,
+			c_has_regcea => 0,
+			c_mem_type => 0,
+			c_prim_type => 1,
+			c_sinita_val => "0",
+			c_read_width_b => 16,
+			c_family => "spartan3",
+			c_read_width_a => 16,
+			c_disable_warn_bhv_coll => 0,
+			c_write_mode_b => "WRITE_FIRST",
+			c_init_file_name => "no_coe_file_loaded",
+			c_write_mode_a => "WRITE_FIRST",
+			c_mux_pipeline_stages => 0,
+			c_has_mem_output_regs_b => 0,
+			c_load_init_file => 0,
+			c_xdevicefamily => "spartan3a",
+			c_has_mem_output_regs_a => 0,
+			c_write_depth_b => 256,
+			c_write_depth_a => 256,
+			c_has_ssrb => 0,
+			c_has_mux_output_regs_b => 0,
+			c_has_ssra => 0,
+			c_has_mux_output_regs_a => 0,
+			c_addra_width => 8,
+			c_addrb_width => 8,
+			c_default_data => "0",
+			c_use_ecc => 0,
+			c_algorithm => 1,
+			c_disable_warn_bhv_range => 0,
+			c_write_width_b => 16,
+			c_write_width_a => 16,
+			c_read_depth_b => 256,
+			c_read_depth_a => 256,
+			c_byte_size => 9,
+			c_sim_collision_check => "ALL",
+			c_use_ramb16bwer_rst_bhv => 0,
+			c_common_clk => 0,
+			c_wea_width => 1,
+			c_has_enb => 0,
+			c_web_width => 1,
+			c_has_ena => 0,
+			c_sinitb_val => "0",
+			c_use_byte_web => 0,
+			c_use_byte_wea => 0,
+			c_use_default_data => 0);
+-- synthesis translate_on
+
+-- hds translate_on
+
+BEGIN
+
+-- hds translate_off
+
+-- synthesis translate_off
+U0 : wrapped_controlRAM_16bit_x256
+		port map (
+			clka => clka,
+			dina => dina,
+			addra => addra,
+			wea => wea,
+			douta => douta);
+-- synthesis translate_on
+
+
+-- hds translate_on
+
+END controlRAM_16bit_x256_a;
+
+
Index: FPGA/FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd	(revision 215)
@@ -0,0 +1,152 @@
+--
+-- VHDL Architecture FACT_FAD_lib.controlRAM_manager.beha
+--
+-- Created:
+--          by - Benjamin Krumm.UNKNOWN (EEPC8)
+--          at - 14:35:46 14.04.2010
+--
+-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_arith.ALL;
+USE ieee.std_logic_unsigned.ALL;
+LIBRARY FACT_FAD_LIB;
+USE FACT_FAD_LIB.fad_definitions.ALL;
+
+ENTITY control_manager IS
+   GENERIC( 
+      NO_OF_ROI  : integer := 36;
+      NO_OF_DAC  : integer := 8;
+      ADDR_WIDTH : integer := 8
+   );
+   PORT( 
+      clk               : IN     std_logic;
+      ram_data_out      : IN     std_logic_vector (15 DOWNTO 0);
+      config_ready, config_started : OUT    std_logic := '0';
+      config_start      : IN     std_logic;
+      config_data       : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z');
+      config_addr       : IN     std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0);
+      config_wr_en      : IN     std_logic;
+      config_rd_en      : IN     std_logic;
+      config_data_valid : OUT    std_logic := '0';
+      config_busy       : OUT    std_logic := '0';
+      ram_addr          : OUT    std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0);
+      ram_data_in       : OUT    std_logic_vector (15 DOWNTO 0);
+      ram_write_en      : OUT    std_logic_vector (0 DOWNTO 0);
+      dac_array         : OUT    dac_array_type;
+      roi_array         : OUT    roi_array_type
+   );
+
+-- Declarations
+
+END control_manager ;
+
+ARCHITECTURE beha OF control_manager IS
+  
+  type TYPE_CTRL_STATE is (CTRL_INIT, CTRL_IDLE, CTRL_WAIT_IDLE, CTRL_WRITE,
+                           CTRL_LOAD_ADDR, CTRL_LOAD_WAIT, CTRL_LOAD_DATA, 
+                           CTRL_READ_ADDR, CTRL_READ_WAIT, CTRL_READ_DATA);
+  
+  signal ctrl_state : TYPE_CTRL_STATE := CTRL_INIT;
+  signal addr_cntr : integer range 0 to 2**ADDR_WIDTH - 1 := 0;
+  signal int_dac_array : dac_array_type := DEFAULT_DAC;
+  signal int_roi_array : roi_array_type := DEFAULT_ROI;
+
+BEGIN
+  
+  control_fsm_proc: process (clk)
+  begin
+    
+    if rising_edge(clk) then
+
+      config_busy <= '1';     -- is always busy except in idle mode
+      
+      case ctrl_state is
+        
+        when CTRL_INIT =>
+          addr_cntr <= addr_cntr + 1;
+          ram_addr <= conv_std_logic_vector(addr_cntr, ADDR_WIDTH);
+          config_data_valid <= '0';
+          config_ready <= '0';
+          ctrl_state <= CTRL_INIT;
+          ram_write_en <= "1";
+          if (addr_cntr < NO_OF_ROI) then
+            ram_data_in <= conv_std_logic_vector(int_roi_array(addr_cntr ), 16);
+          elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then
+            ram_data_in <= conv_std_logic_vector(int_dac_array(addr_cntr - NO_OF_ROI), 16);
+          else
+            ram_write_en <= "0"; 
+            ctrl_state <= CTRL_IDLE;
+          end if;
+      
+        when CTRL_IDLE =>
+          addr_cntr <= 0;
+          ram_write_en <= "0";
+          config_busy <= '0';
+          if (config_start = '1') then
+            config_started <= '1';
+            config_ready <= '0';
+            config_data_valid <= '0';
+            ctrl_state <= CTRL_LOAD_ADDR;
+          end if;
+          if (config_wr_en = '1') then
+            config_busy <= '1';
+            config_data <= (others => 'Z');
+            ctrl_state <= CTRL_WRITE;
+          end if;
+          if (config_rd_en = '1') then
+            ram_addr <= config_addr;
+            config_data_valid <= '0';
+--            ctrl_state <= CTRL_READ_ADDR;
+            ctrl_state <= CTRL_READ_WAIT;
+          end if; 
+
+        when CTRL_WAIT_IDLE =>
+          ctrl_state <= CTRL_IDLE; 
+          
+        when CTRL_LOAD_ADDR =>
+          ram_addr <= conv_std_logic_vector(addr_cntr, ADDR_WIDTH);
+          ctrl_state <= CTRL_LOAD_WAIT;
+        when CTRL_LOAD_WAIT =>
+          ctrl_state <= CTRL_LOAD_DATA;
+        when CTRL_LOAD_DATA =>
+          addr_cntr <= addr_cntr + 1;
+          if (addr_cntr < NO_OF_ROI) then
+            roi_array(addr_cntr) <= conv_integer(ram_data_out);
+            ctrl_state <= CTRL_LOAD_ADDR;
+          elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then
+            dac_array(addr_cntr - NO_OF_ROI) <= conv_integer(ram_data_out);
+            ctrl_state <= CTRL_LOAD_ADDR;
+          else
+            addr_cntr <= 0;
+            config_started <= '0';
+            config_ready <= '1';
+            ctrl_state <= CTRL_WAIT_IDLE;
+          end if;
+        
+        when CTRL_WRITE =>
+          ram_data_in <= config_data;
+          ram_addr <= config_addr;
+          ram_write_en <= "1";
+          ctrl_state <= CTRL_IDLE;
+        
+        -- *** IMPORTANT ***
+        -- read address must remain two clock cycles
+        when CTRL_READ_ADDR =>
+          ctrl_state <= CTRL_READ_WAIT;
+        when CTRL_READ_WAIT =>
+          ctrl_state <= CTRL_READ_DATA;
+        when CTRL_READ_DATA =>
+          config_data <= ram_data_out;
+          config_data_valid <= '1';
+          ctrl_state <= CTRL_IDLE;
+        
+        end case;
+        
+    end if;
+    
+  end process control_fsm_proc;
+
+END ARCHITECTURE beha;
+
Index: FPGA/FAD/FACT_FAD_lib/hdl/control_unit_struct.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/control_unit_struct.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/control_unit_struct.vhd	(revision 215)
@@ -0,0 +1,143 @@
+-- VHDL Entity FACT_FAD_lib.control_unit.symbol
+--
+-- Created:
+--          by - kai.UNKNOWN (E5PCXX)
+--          at - 13:32:05 07.05.2010
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_arith.ALL;
+LIBRARY FACT_FAD_LIB;
+USE FACT_FAD_LIB.fad_definitions.ALL;
+
+ENTITY control_unit IS
+   PORT( 
+      clk               : IN     STD_LOGIC;
+      config_addr       : IN     std_logic_vector (7 DOWNTO 0);
+      config_rd_en      : IN     std_logic;
+      config_start      : IN     std_logic;
+      config_wr_en      : IN     std_logic;
+      config_busy       : OUT    std_logic;
+      config_data_valid : OUT    std_logic;
+      config_ready      : OUT    std_logic;
+      config_started    : OUT    std_logic  := '0';
+      dac_array         : OUT    dac_array_type;
+      roi_array         : OUT    roi_array_type;
+      config_data       : INOUT  std_logic_vector (15 DOWNTO 0)
+   );
+
+-- Declarations
+
+END control_unit ;
+
+--
+-- VHDL Architecture FACT_FAD_lib.control_unit.struct
+--
+-- Created:
+--          by - kai.UNKNOWN (E5PCXX)
+--          at - 13:32:05 07.05.2010
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_arith.ALL;
+LIBRARY FACT_FAD_LIB;
+USE FACT_FAD_LIB.fad_definitions.ALL;
+
+LIBRARY FACT_FAD_lib;
+
+ARCHITECTURE struct OF control_unit IS
+
+   -- Architecture declarations
+
+   -- Internal signal declarations
+   SIGNAL ram_addr     : std_logic_VECTOR(7 DOWNTO 0);
+   SIGNAL ram_data_in  : std_logic_VECTOR(15 DOWNTO 0);
+   SIGNAL ram_data_out : std_logic_VECTOR(15 DOWNTO 0);
+   SIGNAL ram_wren     : std_logic_VECTOR(0 DOWNTO 0);
+
+
+   -- Component Declarations
+   COMPONENT controlRAM_16bit_x256
+   PORT (
+      clka  : IN     std_logic ;
+      dina  : IN     std_logic_VECTOR (15 DOWNTO 0);
+      addra : IN     std_logic_VECTOR (7 DOWNTO 0);
+      wea   : IN     std_logic_VECTOR (0 DOWNTO 0);
+      douta : OUT    std_logic_VECTOR (15 DOWNTO 0)
+   );
+   END COMPONENT;
+   COMPONENT control_manager
+   GENERIC (
+      NO_OF_ROI  : integer := 36;
+      NO_OF_DAC  : integer := 8;
+      ADDR_WIDTH : integer := 8
+   );
+   PORT (
+      clk               : IN     std_logic ;
+      ram_data_out      : IN     std_logic_vector (15 DOWNTO 0);
+      config_ready      : OUT    std_logic                      := '0';
+      config_started    : OUT    std_logic                      := '0';
+      config_start      : IN     std_logic ;
+      config_data       : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z');
+      config_addr       : IN     std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0);
+      config_wr_en      : IN     std_logic ;
+      config_rd_en      : IN     std_logic ;
+      config_data_valid : OUT    std_logic                      := '0';
+      config_busy       : OUT    std_logic                      := '0';
+      ram_addr          : OUT    std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0);
+      ram_data_in       : OUT    std_logic_vector (15 DOWNTO 0);
+      ram_write_en      : OUT    std_logic_vector (0 DOWNTO 0);
+      dac_array         : OUT    dac_array_type ;
+      roi_array         : OUT    roi_array_type 
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : controlRAM_16bit_x256 USE ENTITY FACT_FAD_lib.controlRAM_16bit_x256;
+   FOR ALL : control_manager USE ENTITY FACT_FAD_lib.control_manager;
+   -- pragma synthesis_on
+
+
+BEGIN
+
+   -- Instance port mappings.
+   -- synthesis translate_on
+   I_control_ram : controlRAM_16bit_x256
+      PORT MAP (
+         clka  => clk,
+         dina  => ram_data_in,
+         addra => ram_addr,
+         wea   => ram_wren,
+         douta => ram_data_out
+      );
+   I_control_manager : control_manager
+      GENERIC MAP (
+         NO_OF_ROI  => 36,
+         NO_OF_DAC  => 8,
+         ADDR_WIDTH => 8
+      )
+      PORT MAP (
+         clk               => clk,
+         ram_data_out      => ram_data_out,
+         config_ready      => config_ready,
+         config_started    => config_started,
+         config_start      => config_start,
+         config_data       => config_data,
+         config_addr       => config_addr,
+         config_wr_en      => config_wr_en,
+         config_rd_en      => config_rd_en,
+         config_data_valid => config_data_valid,
+         config_busy       => config_busy,
+         ram_addr          => ram_addr,
+         ram_data_in       => ram_data_in,
+         ram_write_en      => ram_wren,
+         dac_array         => dac_array,
+         roi_array         => roi_array
+      );
+
+END struct;
Index: FPGA/FAD/FACT_FAD_lib/hdl/dataRAM_64bit_16bit_dataRAM_64bit_16bit_a.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/dataRAM_64bit_16bit_dataRAM_64bit_16bit_a.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/dataRAM_64bit_16bit_dataRAM_64bit_16bit_a.vhd	(revision 215)
@@ -0,0 +1,145 @@
+-- Coregen VHDL wrapper file modified by HDL Designer
+
+--------------------------------------------------------------------------------
+--     This file is owned and controlled by Xilinx and must be used           --
+--     solely for design, simulation, implementation and creation of          --
+--     design files limited to Xilinx devices or technologies. Use            --
+--     with non-Xilinx devices or technologies is expressly prohibited        --
+--     and immediately terminates your license.                               --
+--                                                                            --
+--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
+--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
+--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
+--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
+--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
+--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
+--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
+--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
+--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
+--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
+--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
+--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
+--     FOR A PARTICULAR PURPOSE.                                              --
+--                                                                            --
+--     Xilinx products are not intended for use in life support               --
+--     appliances, devices, or systems. Use in such applications are          --
+--     expressly prohibited.                                                  --
+--                                                                            --
+--     (c) Copyright 1995-2007 Xilinx, Inc.                                   --
+--     All rights reserved.                                                   --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file dataRAM_64bit_16bit.vhd when simulating
+-- the core, dataRAM_64bit_16bit. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY dataRAM_64bit_16bit IS
+	port (
+	clka: IN std_logic;
+	dina: IN std_logic_VECTOR(63 downto 0);
+	addra: IN std_logic_VECTOR(11 downto 0);
+	wea: IN std_logic_VECTOR(0 downto 0);
+	clkb: IN std_logic;
+	addrb: IN std_logic_VECTOR(13 downto 0);
+	doutb: OUT std_logic_VECTOR(15 downto 0));
+END dataRAM_64bit_16bit;
+
+ARCHITECTURE dataRAM_64bit_16bit_a OF dataRAM_64bit_16bit IS
+
+-- hds translate_off
+
+-- synthesis translate_off
+component wrapped_dataRAM_64bit_16bit
+	port (
+	clka: IN std_logic;
+	dina: IN std_logic_VECTOR(63 downto 0);
+	addra: IN std_logic_VECTOR(11 downto 0);
+	wea: IN std_logic_VECTOR(0 downto 0);
+	clkb: IN std_logic;
+	addrb: IN std_logic_VECTOR(13 downto 0);
+	doutb: OUT std_logic_VECTOR(15 downto 0));
+end component;
+
+-- Configuration specification 
+	for all : wrapped_dataRAM_64bit_16bit use entity XilinxCoreLib.blk_mem_gen_v2_8(behavioral)
+		generic map(
+			c_has_regceb => 0,
+			c_has_regcea => 0,
+			c_mem_type => 1,
+			c_prim_type => 1,
+			c_sinita_val => "0",
+			c_read_width_b => 16,
+			c_family => "spartan3",
+			c_read_width_a => 64,
+			c_disable_warn_bhv_coll => 0,
+			c_write_mode_b => "READ_FIRST",
+			c_init_file_name => "no_coe_file_loaded",
+			c_write_mode_a => "READ_FIRST",
+			c_mux_pipeline_stages => 0,
+			c_has_mem_output_regs_b => 0,
+			c_load_init_file => 0,
+			c_xdevicefamily => "spartan3a",
+			c_has_mem_output_regs_a => 0,
+			c_write_depth_b => 16384,
+			c_write_depth_a => 4096,
+			c_has_ssrb => 0,
+			c_has_mux_output_regs_b => 0,
+			c_has_ssra => 0,
+			c_has_mux_output_regs_a => 0,
+			c_addra_width => 12,
+			c_addrb_width => 14,
+			c_default_data => "0",
+			c_use_ecc => 0,
+			c_algorithm => 1,
+			c_disable_warn_bhv_range => 0,
+			c_write_width_b => 16,
+			c_write_width_a => 64,
+			c_read_depth_b => 16384,
+			c_read_depth_a => 4096,
+			c_byte_size => 9,
+			c_sim_collision_check => "ALL",
+			c_use_ramb16bwer_rst_bhv => 0,
+			c_common_clk => 0,
+			c_wea_width => 1,
+			c_has_enb => 0,
+			c_web_width => 1,
+			c_has_ena => 0,
+			c_sinitb_val => "0",
+			c_use_byte_web => 0,
+			c_use_byte_wea => 0,
+			c_use_default_data => 1);
+-- synthesis translate_on
+
+-- hds translate_on
+
+BEGIN
+
+-- hds translate_off
+
+-- synthesis translate_off
+U0 : wrapped_dataRAM_64bit_16bit
+		port map (
+			clka => clka,
+			dina => dina,
+			addra => addra,
+			wea => wea,
+			clkb => clkb,
+			addrb => addrb,
+			doutb => doutb);
+-- synthesis translate_on
+
+
+-- hds translate_on
+
+END dataRAM_64bit_16bit_a;
+
+
Index: FPGA/FAD/FACT_FAD_lib/hdl/data_generator.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/data_generator.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/data_generator.vhd	(revision 215)
@@ -0,0 +1,268 @@
+--
+-- VHDL Architecture FACT_FAD_lib.data_generator.beha
+--
+-- Created:
+--          by - FPGA_Developer.UNKNOWN (EEPC8)
+--          at - 14:36:14 10.02.2010
+--
+-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library fact_fad_lib;
+use fact_fad_lib.fad_definitions.all;
+
+-- -- Uncomment the following library declaration if instantiating
+-- -- any Xilinx primitives in this code.
+-- library UNISIM;
+-- use UNISIM.VComponents.all;
+
+entity data_generator is
+   port( 
+      clk            : in     std_logic;
+      data_out       : out    std_logic_vector (63 downto 0);
+      addr_out       : out    std_logic_vector (11 downto 0);
+      write_ea       : out    std_logic_vector (0 downto 0) := "0";
+      ram_start_addr : in    std_logic_vector (11 downto 0);
+      ram_write_ea : in std_logic;
+      ram_write_ready : out std_logic := '0';
+      config_start_mm, config_start_cm, config_start_spi : out std_logic := '0';
+      config_ready_mm, config_ready_cm, config_ready_spi : in std_logic;
+      config_started_mm, config_started_cm, config_started_spi : in std_logic;
+      roi_array : in roi_array_type;
+      roi_max : in roi_max_type;
+      sensor_array : in sensor_array_type;
+      sensor_ready : in std_logic;
+      dac_array : in dac_array_type;
+      package_length : in std_logic_vector (15 downto 0);
+      board_id       : in std_logic_vector (3 downto 0);
+      crate_id       : in std_logic_vector (1 downto 0);
+      trigger_id     : in std_logic_vector (47 downto 0);
+      trigger        : in std_logic;
+      s_trigger      : in std_logic;
+      new_config     : in std_logic;
+      config_started : out std_logic := '0';
+      adc_data_array : in adc_data_array_type;
+      adc_oeb : out std_logic := '1';
+      adc_otr : in std_logic_vector (3 downto 0);
+      drs_channel_id : out std_logic_vector (3 downto 0) := (others => '0');
+      drs_dwrite : out std_logic := '1';
+      drs_clk_en, drs_read_s_cell : out std_logic := '0';
+      drs_read_s_cell_ready : in std_logic;
+      drs_s_cell_array : in drs_s_cell_array_type
+      );
+end data_generator ;
+
+architecture Behavioral of data_generator is
+
+type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
+                             WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
+                             WRITE_END_FLAG, WRITE_DATA_STOP,
+                             WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING);
+
+signal state_generate : state_generate_type := INIT;
+signal start_addr : std_logic_vector (11 downto 0) := (others => '0');
+
+signal data_cntr : integer  range 0 to 1024 := 0;
+signal evnt_cntr : std_logic_vector (31 downto 0) := (others => '0');
+signal addr_cntr : integer range 0 to RAM_SIZE_64B := 0;    -- counts 64 bit words
+signal channel_id : integer range 0 to 9 := 0;
+signal adc_wait_cnt : integer range 0 to 7 := 0;
+
+
+begin
+  
+  
+	generate_data : process (clk)
+	begin
+		if rising_edge (clk) then
+		  
+      addr_out <= start_addr + conv_std_logic_vector(addr_cntr, 12);
+	
+			case state_generate is
+			  when INIT =>
+			    state_generate <= CONFIG;
+
+        when CONFIG =>
+          config_started <= '1';
+          -- config config manager
+          config_start_cm <= '1';
+          if (config_started_cm = '1') then
+            state_generate <= CONFIG1;
+          end if;
+        when CONFIG1 =>
+          if (config_ready_cm = '1') then
+            config_started <= '0';
+            config_start_cm <= '0';
+            config_start_mm <= '1';
+          end if;
+          if (config_started_mm = '1') then
+            state_generate <= CONFIG2;
+          end if;
+        when CONFIG2 =>
+          if (config_ready_mm = '1') then
+            config_start_mm <= '0';
+            config_start_spi <= '1';
+          end if;
+          if (config_started_spi = '1') then
+            state_generate <= CONFIG3;
+          end if;
+        when CONFIG3 =>
+          if (config_ready_spi = '1') then
+            config_start_spi <= '0';
+            state_generate <= WRITE_DATA_IDLE;
+          end if;
+
+        when WRITE_DATA_IDLE =>
+          if (new_config = '1') then
+            state_generate <= CONFIG;
+          end if;
+          if (ram_write_ea = '1' and (trigger = '1' or s_trigger = '1')) then
+            -- stop drs, dwrite low
+            drs_dwrite <= '0';
+            -- start reading of drs stop cell
+            drs_read_s_cell <= '1';
+            -- enable adc output
+            adc_oeb <= '0';
+            start_addr <= ram_start_addr;
+            state_generate <= WRITE_HEADER;
+            evnt_cntr <= evnt_cntr + 1;
+          end if;
+				when WRITE_HEADER =>
+				  write_ea <= "1";
+          data_out <= X"0000" & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01";
+					addr_cntr <= addr_cntr + 3;
+					state_generate <= WRITE_BOARD_ID;
+        when WRITE_BOARD_ID =>     -- crate ID & board ID
+          data_out <= (63 downto 10 => '0') & crate_id & "1000" & board_id;
+          addr_cntr <= addr_cntr + 1;
+          state_generate <= WRITE_TEMPERATURES;
+        when WRITE_TEMPERATURES =>     -- temperatures
+          if (sensor_ready = '1') then
+            data_out <= conv_std_logic_vector (sensor_array (3), 16)
+                      & conv_std_logic_vector (sensor_array (2), 16)
+                      & conv_std_logic_vector (sensor_array (1), 16)
+                      & conv_std_logic_vector (sensor_array (0), 16);
+            addr_cntr <= addr_cntr + 1;
+            state_generate <= WRITE_DAC1;
+          end if;
+
+        when WRITE_DAC1 =>
+          data_out <= conv_std_logic_vector (dac_array (3), 16)
+                    & conv_std_logic_vector (dac_array (2), 16)
+                    & conv_std_logic_vector (dac_array (1), 16)
+                    & conv_std_logic_vector (dac_array (0), 16);
+          addr_cntr <= addr_cntr + 1;
+          state_generate <= WRITE_DAC2;
+        when WRITE_DAC2 =>
+          data_out <= conv_std_logic_vector (dac_array (7), 16)
+                    & conv_std_logic_vector (dac_array (6), 16)
+                    & conv_std_logic_vector (dac_array (5), 16)
+                    & conv_std_logic_vector (dac_array (4), 16);
+          addr_cntr <= addr_cntr + 1;
+          state_generate <= WAIT_FOR_STOP_CELL;
+
+        when WAIT_FOR_STOP_CELL =>
+          drs_read_s_cell <= '0';
+          if (drs_read_s_cell_ready = '1') then
+            state_generate <= START_DRS_READING;
+          end if;
+        
+        when START_DRS_READING =>
+          --drs channel number
+          drs_channel_id <= conv_std_logic_vector (channel_id, 4);
+          --starte drs-clocking
+          --adc_oeb <= '0'; -- nur für Emulator
+          drs_clk_en <= '1';
+          adc_wait_cnt <= 0;
+          state_generate <= WRITE_CHANNEL_ID;
+
+        when WRITE_CHANNEL_ID =>    -- write DRS and Channel IDs
+          data_out <= conv_std_logic_vector(0,10) & conv_std_logic_vector(3,2) & conv_std_logic_vector(channel_id,4)
+                    & conv_std_logic_vector(0,10) & conv_std_logic_vector(2,2) & conv_std_logic_vector(channel_id,4)
+                    & conv_std_logic_vector(0,10) & conv_std_logic_vector(1,2) & conv_std_logic_vector(channel_id,4)
+                    & conv_std_logic_vector(0,10) & conv_std_logic_vector(0,2) & conv_std_logic_vector(channel_id,4);
+          addr_cntr <= addr_cntr + 1;
+          state_generate <= WRITE_START_CELL;
+        when WRITE_START_CELL =>    -- write start cells
+          data_out <= "000000" & drs_s_cell_array (3)
+                    & "000000" & drs_s_cell_array (2)
+                    & "000000" & drs_s_cell_array (1)
+                    & "000000" & drs_s_cell_array (0); 
+          addr_cntr <= addr_cntr + 1;
+          state_generate <= WRITE_ROI;
+        when WRITE_ROI =>    -- write ROI
+          data_out <= "00000" & conv_std_logic_vector (roi_array((3) * 9 + channel_id), 11) 
+                    & "00000" & conv_std_logic_vector (roi_array((2) * 9 + channel_id), 11)
+                    & "00000" & conv_std_logic_vector (roi_array((1) * 9 + channel_id), 11)
+                    & "00000" & conv_std_logic_vector (roi_array((0) * 9 + channel_id), 11);
+          addr_cntr <= addr_cntr + 1;
+          state_generate <= WAIT_FOR_ADC;
+        when WAIT_FOR_ADC =>
+          -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+          if (adc_wait_cnt < (4 + 3)) then -- anpassen!!!! -- 3 für Simulation, 4 für FPGA???
+            adc_wait_cnt <= adc_wait_cnt + 1;
+          else
+            state_generate <= WRITE_ADC_DATA;
+          end if;
+        when WRITE_ADC_DATA =>
+          if (data_cntr < roi_max (channel_id)) then
+            data_out <= "000" & adc_otr(3) & adc_data_array(3)
+                      & "000" & adc_otr(2) & adc_data_array(2)
+                      & "000" & adc_otr(1) & adc_data_array(1)
+                      & "000" & adc_otr(0) & adc_data_array(0);
+            addr_cntr <= addr_cntr + 1;
+            state_generate <= WRITE_ADC_DATA;
+            data_cntr <= data_cntr + 1;
+          else
+            drs_clk_en <= '0';
+            --adc_oeb <= '1'; -- nur für Emulator
+            if (channel_id = 8) then
+              state_generate <= WRITE_EXTERNAL_TRIGGER;
+              adc_oeb <= '1';
+            else
+              channel_id <= channel_id + 1;     -- increment channel_id 
+              state_generate <= START_DRS_READING;
+              data_cntr <= 0;
+            end if;
+          end if;
+          
+          
+        when WRITE_EXTERNAL_TRIGGER =>    -- external trigger ID
+          addr_out <= start_addr + conv_std_logic_vector(1, 12);
+          data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16);
+          state_generate <= WRITE_INTERNAL_TRIGGER;
+        when WRITE_INTERNAL_TRIGGER =>    -- internal trigger ID
+          addr_out <= start_addr + conv_std_logic_vector(2, 12);
+          data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16);
+          state_generate <= WRITE_END_FLAG;
+ 				when WRITE_END_FLAG =>
+          data_out <= (63 downto 32 => '0') & X"04FE" & X"4242";
+          addr_cntr <= addr_cntr + 1;
+          state_generate <= WRITE_DATA_END;
+				when WRITE_DATA_END =>
+				  write_ea <= "0";
+					ram_write_ready <= '1';
+					state_generate <= WRITE_DATA_END_WAIT;
+				when WRITE_DATA_END_WAIT =>
+				  state_generate <= WRITE_DATA_STOP;
+      		when WRITE_DATA_STOP =>
+          drs_dwrite <= '1';
+					data_cntr <= 0;
+					addr_cntr <= 0;
+					channel_id <= 0;
+					ram_write_ready <= '0';
+					state_generate <= WRITE_DATA_IDLE;
+				
+				when others =>
+					null;
+					
+			end case; -- state_generate
+		end if; -- rising_edge (clk)
+	end process generate_data;
+
+end Behavioral;
+
+
Index: FPGA/FAD/FACT_FAD_lib/hdl/dcm_50_to_25_BEHAVIORAL.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/dcm_50_to_25_BEHAVIORAL.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/dcm_50_to_25_BEHAVIORAL.vhd	(revision 215)
@@ -0,0 +1,189 @@
+-- Coregen VHDL wrapper file modified by HDL Designer
+
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
+--------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 10.1.03
+--  \   \         Application : xaw2vhdl
+--  /   /         Filename : dcm_50_to_25.vhd
+-- /___/   /\     Timestamp : 04/19/2010 15:54:44
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--Command: xaw2vhdl-st C:/DOKUME~1/kai/LOKALE~1/Temp/coregen_kai/coregen/project/dcm_50_to_25.xaw C:/DOKUME~1/kai/LOKALE~1/Temp/coregen_kai/coregen/project/dcm_50_to_25
+--Design Name: dcm_50_to_25
+--Device: xc3s50a-5tq144
+--
+-- Module dcm_50_to_25
+-- Written for synthesis tool: Precision
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+
+entity dcm_50_to_25 is
+   port ( CLKIN_IN        : in    std_logic; 
+          CLKFX_OUT       : out   std_logic; 
+          CLKIN_IBUFG_OUT : out   std_logic; 
+          CLK0_OUT        : out   std_logic);
+end dcm_50_to_25;
+
+architecture BEHAVIORAL of dcm_50_to_25 is
+
+-- hds translate_off
+
+   attribute CLK_FEEDBACK          : string ;
+   attribute CLKDV_DIVIDE          : string ;
+   attribute CLKFX_DIVIDE          : string ;
+   attribute CLKFX_MULTIPLY        : string ;
+   attribute CLKIN_DIVIDE_BY_2     : string ;
+   attribute CLKIN_PERIOD          : string ;
+   attribute CLKOUT_PHASE_SHIFT    : string ;
+   attribute DESKEW_ADJUST         : string ;
+   attribute DFS_FREQUENCY_MODE    : string ;
+   attribute DLL_FREQUENCY_MODE    : string ;
+   attribute DUTY_CYCLE_CORRECTION : string ;
+   attribute FACTORY_JF            : string ;
+   attribute PHASE_SHIFT           : string ;
+   attribute STARTUP_WAIT          : string ;
+   signal CLKFB_IN        : std_logic;
+   signal CLKFX_BUF       : std_logic;
+   signal CLKIN_IBUFG     : std_logic;
+   signal CLK0_BUF        : std_logic;
+   signal GND_BIT         : std_logic;
+   component BUFG
+      port ( I : in    std_logic; 
+             O : out   std_logic);
+   end component;
+   
+   component IBUFG
+      port ( I : in    std_logic; 
+             O : out   std_logic);
+   end component;
+   
+   -- Period Jitter (unit interval) for block DCM_SP_INST = 0.02 UI
+   -- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.18 ns
+   component DCM_SP
+      -- pragma synthesis_off
+      generic( CLK_FEEDBACK : string :=  "1X";
+               CLKDV_DIVIDE : real :=  2.0;
+               CLKFX_DIVIDE : integer :=  1;
+               CLKFX_MULTIPLY : integer :=  4;
+               CLKIN_DIVIDE_BY_2 : boolean :=  FALSE;
+               CLKIN_PERIOD : real :=  10.0;
+               CLKOUT_PHASE_SHIFT : string :=  "NONE";
+               DESKEW_ADJUST : string :=  "SYSTEM_SYNCHRONOUS";
+               DFS_FREQUENCY_MODE : string :=  "LOW";
+               DLL_FREQUENCY_MODE : string :=  "LOW";
+               DUTY_CYCLE_CORRECTION : boolean :=  TRUE;
+               FACTORY_JF : bit_vector :=  x"C080";
+               PHASE_SHIFT : integer :=  0;
+               STARTUP_WAIT : boolean :=  FALSE;
+               DSS_MODE : string :=  "NONE");
+      -- pragma synthesis_on
+      port ( CLKIN    : in    std_logic; 
+             CLKFB    : in    std_logic; 
+             RST      : in    std_logic; 
+             PSEN     : in    std_logic; 
+             PSINCDEC : in    std_logic; 
+             PSCLK    : in    std_logic; 
+             DSSEN    : in    std_logic; 
+             CLK0     : out   std_logic; 
+             CLK90    : out   std_logic; 
+             CLK180   : out   std_logic; 
+             CLK270   : out   std_logic; 
+             CLKDV    : out   std_logic; 
+             CLK2X    : out   std_logic; 
+             CLK2X180 : out   std_logic; 
+             CLKFX    : out   std_logic; 
+             CLKFX180 : out   std_logic; 
+             STATUS   : out   std_logic_vector (7 downto 0); 
+             LOCKED   : out   std_logic; 
+             PSDONE   : out   std_logic);
+   end component;
+   
+   attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X";
+   attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0";
+   attribute CLKFX_DIVIDE of DCM_SP_INST : label is "5";
+   attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "2";
+   attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE";
+   attribute CLKIN_PERIOD of DCM_SP_INST : label is "20.000";
+   attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "NONE";
+   attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS";
+   attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
+   attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
+   attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE";
+   attribute FACTORY_JF of DCM_SP_INST : label is "C080";
+   attribute PHASE_SHIFT of DCM_SP_INST : label is "0";
+   attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE";
+
+-- hds translate_on
+
+begin
+
+-- hds translate_off
+
+   GND_BIT <= '0';
+   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
+   CLK0_OUT <= CLKFB_IN;
+   CLKFX_BUFG_INST : BUFG
+      port map (I=>CLKFX_BUF,
+                O=>CLKFX_OUT);
+   
+   CLKIN_IBUFG_INST : IBUFG
+      port map (I=>CLKIN_IN,
+                O=>CLKIN_IBUFG);
+   
+   CLK0_BUFG_INST : BUFG
+      port map (I=>CLK0_BUF,
+                O=>CLKFB_IN);
+   
+   DCM_SP_INST : DCM_SP
+   -- pragma synthesis_off
+   generic map( CLK_FEEDBACK => "1X",
+            CLKDV_DIVIDE => 2.0,
+            CLKFX_DIVIDE => 5,
+            CLKFX_MULTIPLY => 2,
+            CLKIN_DIVIDE_BY_2 => FALSE,
+            CLKIN_PERIOD => 20.000,
+            CLKOUT_PHASE_SHIFT => "NONE",
+            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
+            DFS_FREQUENCY_MODE => "LOW",
+            DLL_FREQUENCY_MODE => "LOW",
+            DUTY_CYCLE_CORRECTION => TRUE,
+            FACTORY_JF => x"C080",
+            PHASE_SHIFT => 0,
+            STARTUP_WAIT => FALSE)
+   -- pragma synthesis_on
+      port map (CLKFB=>CLKFB_IN,
+                CLKIN=>CLKIN_IBUFG,
+                DSSEN=>GND_BIT,
+                PSCLK=>GND_BIT,
+                PSEN=>GND_BIT,
+                PSINCDEC=>GND_BIT,
+                RST=>GND_BIT,
+                CLKDV=>open,
+                CLKFX=>CLKFX_BUF,
+                CLKFX180=>open,
+                CLK0=>CLK0_BUF,
+                CLK2X=>open,
+                CLK2X180=>open,
+                CLK90=>open,
+                CLK180=>open,
+                CLK270=>open,
+                LOCKED=>open,
+                PSDONE=>open,
+                STATUS=>open);
+   
+
+-- hds translate_on
+
+end BEHAVIORAL;
+
+
+
Index: FPGA/FAD/FACT_FAD_lib/hdl/dcm_ps_38ns_BEHAVIORAL.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/dcm_ps_38ns_BEHAVIORAL.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/dcm_ps_38ns_BEHAVIORAL.vhd	(revision 215)
@@ -0,0 +1,169 @@
+-- Coregen VHDL wrapper file modified by HDL Designer
+
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
+--------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 10.1.03
+--  \   \         Application : xaw2vhdl
+--  /   /         Filename : dcm_ps_38ns.vhd
+-- /___/   /\     Timestamp : 04/19/2010 15:55:48
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--Command: xaw2vhdl-st C:/DOKUME~1/kai/LOKALE~1/Temp/coregen_kai/coregen/project/dcm_ps_38ns.xaw C:/DOKUME~1/kai/LOKALE~1/Temp/coregen_kai/coregen/project/dcm_ps_38ns
+--Design Name: dcm_ps_38ns
+--Device: xc3s50a-5tq144
+--
+-- Module dcm_ps_38ns
+-- Written for synthesis tool: Precision
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+
+entity dcm_ps_38ns is
+   port ( CLKIN_IN : in    std_logic; 
+          CLK0_OUT : out   std_logic);
+end dcm_ps_38ns;
+
+architecture BEHAVIORAL of dcm_ps_38ns is
+
+-- hds translate_off
+
+   attribute CLK_FEEDBACK          : string ;
+   attribute CLKDV_DIVIDE          : string ;
+   attribute CLKFX_DIVIDE          : string ;
+   attribute CLKFX_MULTIPLY        : string ;
+   attribute CLKIN_DIVIDE_BY_2     : string ;
+   attribute CLKIN_PERIOD          : string ;
+   attribute CLKOUT_PHASE_SHIFT    : string ;
+   attribute DESKEW_ADJUST         : string ;
+   attribute DFS_FREQUENCY_MODE    : string ;
+   attribute DLL_FREQUENCY_MODE    : string ;
+   attribute DUTY_CYCLE_CORRECTION : string ;
+   attribute FACTORY_JF            : string ;
+   attribute PHASE_SHIFT           : string ;
+   attribute STARTUP_WAIT          : string ;
+   signal CLKFB_IN : std_logic;
+   signal CLK0_BUF : std_logic;
+   signal GND_BIT  : std_logic;
+   component BUFG
+      port ( I : in    std_logic; 
+             O : out   std_logic);
+   end component;
+   
+   component DCM_SP
+      -- pragma synthesis_off
+      generic( CLK_FEEDBACK : string :=  "1X";
+               CLKDV_DIVIDE : real :=  2.0;
+               CLKFX_DIVIDE : integer :=  1;
+               CLKFX_MULTIPLY : integer :=  4;
+               CLKIN_DIVIDE_BY_2 : boolean :=  FALSE;
+               CLKIN_PERIOD : real :=  10.0;
+               CLKOUT_PHASE_SHIFT : string :=  "NONE";
+               DESKEW_ADJUST : string :=  "SYSTEM_SYNCHRONOUS";
+               DFS_FREQUENCY_MODE : string :=  "LOW";
+               DLL_FREQUENCY_MODE : string :=  "LOW";
+               DUTY_CYCLE_CORRECTION : boolean :=  TRUE;
+               FACTORY_JF : bit_vector :=  x"C080";
+               PHASE_SHIFT : integer :=  0;
+               STARTUP_WAIT : boolean :=  FALSE;
+               DSS_MODE : string :=  "NONE");
+      -- pragma synthesis_on
+      port ( CLKIN    : in    std_logic; 
+             CLKFB    : in    std_logic; 
+             RST      : in    std_logic; 
+             PSEN     : in    std_logic; 
+             PSINCDEC : in    std_logic; 
+             PSCLK    : in    std_logic; 
+             DSSEN    : in    std_logic; 
+             CLK0     : out   std_logic; 
+             CLK90    : out   std_logic; 
+             CLK180   : out   std_logic; 
+             CLK270   : out   std_logic; 
+             CLKDV    : out   std_logic; 
+             CLK2X    : out   std_logic; 
+             CLK2X180 : out   std_logic; 
+             CLKFX    : out   std_logic; 
+             CLKFX180 : out   std_logic; 
+             STATUS   : out   std_logic_vector (7 downto 0); 
+             LOCKED   : out   std_logic; 
+             PSDONE   : out   std_logic);
+   end component;
+   
+   attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X";
+   attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0";
+   attribute CLKFX_DIVIDE of DCM_SP_INST : label is "1";
+   attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "4";
+   attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE";
+   attribute CLKIN_PERIOD of DCM_SP_INST : label is "50.000";
+   attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "FIXED";
+   attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS";
+   attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
+   attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
+   attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE";
+   attribute FACTORY_JF of DCM_SP_INST : label is "C080";
+   attribute PHASE_SHIFT of DCM_SP_INST : label is "195";
+   attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE";
+
+-- hds translate_on
+
+begin
+
+-- hds translate_off
+
+   GND_BIT <= '0';
+   CLK0_OUT <= CLKFB_IN;
+   CLK0_BUFG_INST : BUFG
+      port map (I=>CLK0_BUF,
+                O=>CLKFB_IN);
+   
+   DCM_SP_INST : DCM_SP
+   -- pragma synthesis_off
+   generic map( CLK_FEEDBACK => "1X",
+            CLKDV_DIVIDE => 2.0,
+            CLKFX_DIVIDE => 1,
+            CLKFX_MULTIPLY => 4,
+            CLKIN_DIVIDE_BY_2 => FALSE,
+            CLKIN_PERIOD => 50.000,
+            CLKOUT_PHASE_SHIFT => "FIXED",
+            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
+            DFS_FREQUENCY_MODE => "LOW",
+            DLL_FREQUENCY_MODE => "LOW",
+            DUTY_CYCLE_CORRECTION => TRUE,
+            FACTORY_JF => x"C080",
+            PHASE_SHIFT => 195,
+            STARTUP_WAIT => FALSE)
+   -- pragma synthesis_on
+      port map (CLKFB=>CLKFB_IN,
+                CLKIN=>CLKIN_IN,
+                DSSEN=>GND_BIT,
+                PSCLK=>GND_BIT,
+                PSEN=>GND_BIT,
+                PSINCDEC=>GND_BIT,
+                RST=>GND_BIT,
+                CLKDV=>open,
+                CLKFX=>open,
+                CLKFX180=>open,
+                CLK0=>CLK0_BUF,
+                CLK2X=>open,
+                CLK2X180=>open,
+                CLK90=>open,
+                CLK180=>open,
+                CLK270=>open,
+                LOCKED=>open,
+                PSDONE=>open,
+                STATUS=>open);
+   
+
+-- hds translate_on
+
+end BEHAVIORAL;
+
+
+
Index: FPGA/FAD/FACT_FAD_lib/hdl/drs_pulser.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/drs_pulser.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/drs_pulser.vhd	(revision 215)
@@ -0,0 +1,251 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.std_logic_signed.all;
+
+library fact_fad_lib;
+use fact_fad_lib.fad_definitions.all;
+
+
+ENTITY drs_pulser is
+     port (
+         -- input CLK; RSRLOAD and SRCLK are derived from this signal
+         CLK : in std_logic;
+         -- async reset;
+         reset : in std_logic;
+         
+         start_endless_mode : in std_logic;
+         start_read_stop_pos_mode : in std_logic;
+
+         SROUT_in_0 : in std_logic;
+         SROUT_in_1 : in std_logic;
+         SROUT_in_2 : in std_logic;
+         SROUT_in_3 : in std_logic;
+
+--         stop_pos_0 : out std_logic_vector(9 downto 0);
+--         stop_pos_1 : out std_logic_vector(9 downto 0);
+--         stop_pos_2 : out std_logic_vector(9 downto 0);
+--         stop_pos_3 : out std_logic_vector(9 downto 0);
+          stop_pos : out drs_s_cell_array_type;
+         stop_pos_valid : out std_logic;
+
+         RSRLOAD : out std_logic;
+         SRCLK : out std_logic;
+         busy :out std_logic
+     );
+end drs_pulser;
+
+
+ARCHITECTURE behavior of drs_pulser IS
+
+type states is (idle, started_endless, started_read_stop_pos , waiting_e, waiting_r, running_e, running_r);
+signal current_state : states := idle;
+signal next_state : states := idle;
+signal CEN,LEN : std_logic;
+
+
+signal local_roi : std_logic_vector (9 downto 0):= (others => '0');
+
+signal flag_read_stop_pos : std_logic := '0';
+
+signal cell_cntr : std_logic_vector (9 downto 0);
+signal cc_en : std_logic;
+signal cc_reset : std_logic;
+
+signal wait_cntr : std_logic_vector (2 downto 0);
+signal wc_en : std_logic;
+signal wc_reset : std_logic;
+
+signal int_stop_pos_0 : std_logic_vector(9 downto 0) := (others => '0');
+signal int_stop_pos_1 : std_logic_vector(9 downto 0) := (others => '0');
+signal int_stop_pos_2 : std_logic_vector(9 downto 0) := (others => '0');
+signal int_stop_pos_3 : std_logic_vector(9 downto 0) := (others => '0');
+
+begin
+     RSRLOAD <= (LEN and CLK);
+     SRCLK <= (CEN and CLK);
+     stop_pos(0) <= int_stop_pos_0;
+     stop_pos(1) <= int_stop_pos_1;
+     stop_pos(2) <= int_stop_pos_2;
+     stop_pos(3) <= int_stop_pos_3;
+     
+
+               
+     state_register: process(clk, reset)
+     begin
+         IF reset = '1' THEN
+           current_state <= idle ;
+         ELSIF clk = '0' and clk'event THEN  -- ! falling edge !
+            current_state <= next_state ;
+         END IF;
+     end process state_register;
+
+    --Folgezustandsberechnung asynchron
+     transition: process(current_state,
+                         start_endless_mode,
+                         start_read_stop_pos_mode,
+                         wait_cntr,
+                         cell_cntr,
+                         local_roi)
+         begin
+             CASE current_state IS
+                 WHEN idle =>            
+                     if start_endless_mode = '1' then
+                         next_state <= started_endless ;                                             
+                     elsif start_read_stop_pos_mode = '1' then
+                         next_state <= started_read_stop_pos ;
+                     end if;
+                     
+                   WHEN started_endless =>
+                     if cell_cntr = conv_std_logic_vector(1,10) then 
+                       next_state <= waiting_e;
+                     end if;
+                     
+                                                                        
+                                     
+                 WHEN started_read_stop_pos =>        
+                     if cell_cntr = conv_std_logic_vector(1,10) then 
+                       next_state <= waiting_r;
+                     end if;
+                     
+                 WHEN waiting_e =>        
+                     if wait_cntr = conv_std_logic_vector(0,3) then
+                       next_state <= running_e;
+                     else 
+                       next_state <= waiting_e;
+                     end if;
+
+                 WHEN waiting_r =>        
+                     if wait_cntr = conv_std_logic_vector(0,3) then
+                       next_state <= running_r;
+                     end if;
+
+                     
+                   WHEN running_e =>
+                      IF (start_endless_mode = '0') THEN
+                        next_state <= idle;
+                      END IF;
+                  
+                  WHEN running_r =>
+                    if cell_cntr >= local_roi THEN
+                     next_state <= idle;
+                  end if;                           
+     END CASE;
+     end process transition;
+
+     output_proc: process(current_state) --Ausgangsberechnung synchron, da current_state sich nur synchron aendert
+         begin
+             case current_state is
+
+                 when idle =>
+                    local_roi <= (others => '0');
+                    flag_read_stop_pos <= '0';
+                    stop_pos_valid <= '1'; 
+                    LEN <= '0'; CEN <= '0';
+                    busy <= '0';
+                    cc_en <= '0'; cc_reset <= '1';
+                    wc_en <= '0'; wc_reset <= '0';
+
+                 when started_endless =>
+                     local_roi <= "0111111111";
+                     flag_read_stop_pos <= '0';
+                     stop_pos_valid <= '0';
+                     LEN <= '1'; CEN <= '0';
+                     busy <= '1';
+                     cc_en <= '1'; cc_reset <= '0';
+                     wc_en <= '0'; wc_reset <= '1';
+
+                 when started_read_stop_pos =>
+                     local_roi <= conv_std_logic_vector(11,10);
+                     flag_read_stop_pos <= '1';
+                     stop_pos_valid <= '0';
+                     LEN <= '1'; CEN <= '0';
+                     busy <= '1';
+                     cc_en <= '1'; cc_reset <= '0';
+                     wc_en <= '0'; wc_reset <= '1';
+ 
+                 when waiting_e | waiting_r =>
+                     local_roi <= local_roi;
+                     stop_pos_valid <= '0'; 
+                     busy <= '1';
+                     LEN <= '0'; CEN <= '0';
+                     cc_en <= '0'; cc_reset <= '0';
+                     wc_en <= '1'; wc_reset <= '0';
+ 
+                 when running_e =>
+                     flag_read_stop_pos <= '0';
+                     stop_pos_valid <= '0'; 
+                     LEN <= '0'; CEN <= '1';
+                     cc_en <= '1'; cc_reset <= '0';
+                     wc_en <= '0'; wc_reset <= '0';
+                     busy <= '1';
+
+              when running_r =>
+                    flag_read_stop_pos <= '1';
+                     stop_pos_valid <= '0'; 
+                     LEN <= '0'; CEN <= '1';
+                     cc_en <= '1'; cc_reset <= '0';
+                     wc_en <= '0'; wc_reset <= '0';
+                     busy <= '1';
+             end case;
+     end process output_proc;
+
+
+     cellcounter: process (clk, cc_reset) begin
+
+         if (cc_reset = '1') then
+           cell_cntr <= (others=>'0');
+         elsif (rising_edge(clk)) then
+           if (cc_en = '1') then
+             cell_cntr <= cell_cntr + 1;
+           end if;
+         end if;
+
+     end process cellcounter;
+
+
+     waitcounter: process (clk, wc_reset) begin
+         if (wc_reset = '1') then
+           wait_cntr <= "011"; -- RSRLOAD -> warte 3 -> SRCLK
+         elsif (rising_edge(clk)) then
+           if (wc_en = '1') then
+             wait_cntr <= wait_cntr - 1;
+           end if;
+         end if;
+     end process waitcounter;
+
+  -- laut DRS4_rev09.pdf Seite 13 Figure 15
+  -- funktioniert das auslesen der Stop bzw. Startadresse so:
+  -- Sende 1x RSRLOAD- und mind. 9 SRCLK- pulse und sample SROUT zur 
+  -- steigenden Flanke von SRCLK. 
+  -- MSB first LSB last, kommen dann die 10 bits, 
+  -- die die Stopposition darstellen.
+  -- 
+  -- diese Architecture liefert immer dann eine steigende Flanke
+  -- auf RSRCLK, wenn CLK eine steigende Flanke hat und CEN='1' ist.
+  -- Die an SROUT zur steigenden Flanke anliegenden Werte werden wie in einem Schieberegister
+  -- Schritt fuer Schritt in die stop_pos_x vectoren geschoben.
+  -- 
+  -- wenn sie 10 schritte weit reingschoben wurden, ist der process fertig.
+  -- es gibt keinen eigenen counter fuer die 10 schritte, der cell counter kann hier
+  -- missbraucht werden.
+  -- 
+  -- da der process eine steigende flanke auf SRCLK braucht um SROUT zu sampeln 
+  -- wird im Prinzip ein Puls aud SRCLK *zuviel* erzeugt, das ist aber egal...
+  --
+  stop_pos_reader: process (CEN, clk, flag_read_stop_pos)
+  begin
+    IF (flag_read_stop_pos = '1') THEN -- nur wenn ich im read_stop_mode bin, laeuft dieser process
+      IF (CEN = '1') THEN -- nur wenn CEN='1' ist kommen SRCLK pulse raus. 
+        IF (rising_edge(CLK)) THEN -- wenn steigende Flanke, dann SROUT samplen.
+          int_stop_pos_0 <= int_stop_pos_0(8 downto 0) & SROUT_in_0;	
+          int_stop_pos_1 <= int_stop_pos_1(8 downto 0) & SROUT_in_1;	
+          int_stop_pos_2 <= int_stop_pos_2(8 downto 0) & SROUT_in_2;	
+          int_stop_pos_3 <= int_stop_pos_3(8 downto 0) & SROUT_in_3;	
+          
+        END IF; -- rising edge CLK
+      END IF; -- CEN ='1'
+    END IF; -- flag_read_stop_pos = '1'
+  end process stop_pos_reader;  
+  
+end behavior;
Index: FPGA/FAD/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd	(revision 215)
@@ -0,0 +1,99 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.std_logic_signed.all;
+
+library fact_fad_lib;
+use fact_fad_lib.fad_definitions.all;
+
+
+ENTITY drs_pulser_dummy is
+     port (
+         CLK : in std_logic;
+        
+         start_endless_mode : in std_logic;
+         start_read_stop_pos_mode : in std_logic;
+
+         SROUT_in_0 : in std_logic;
+         SROUT_in_1 : in std_logic;
+         SROUT_in_2 : in std_logic;
+         SROUT_in_3 : in std_logic;
+
+         stop_pos : out drs_s_cell_array_type;
+         stop_pos_valid : out std_logic := '0';
+
+         RSRLOAD : out std_logic := '0';
+         SRCLK : out std_logic := '0'
+     );
+end drs_pulser_dummy;
+
+
+ARCHITECTURE behavior of drs_pulser_dummy IS
+
+type state_main_type is (MAIN, READ_STOP_POS, ENDLESS_MODE);
+signal state_main : state_main_type := MAIN;
+signal stop_pos_cntr, wait_cntr : integer range 0 to 31 := 0;
+
+signal stop_pos_int : drs_s_cell_array_type;
+signal RSRLOAD_EN, SRCLK_EN : std_logic := '0';
+
+begin
+  
+  
+  main_proc: process (clk) begin
+
+    RSRLOAD <= (clk and RSRLOAD_EN);
+    SRCLK <= (clk and SRCLK_EN);
+
+    if rising_edge(clk) then
+      case state_main is
+        when MAIN =>
+          if (start_read_stop_pos_mode = '1') then
+            RSRLOAD_EN <= '1';
+            stop_pos_valid <= '0';
+            state_main <= READ_STOP_POS;
+          end if;
+          if (start_endless_mode = '1') then
+            RSRLOAD_EN <= '1';
+            state_main <= ENDLESS_MODE;
+          end if;
+          
+        when ENDLESS_MODE =>
+          RSRLOAD_EN <= '0';
+          if (wait_cntr = 3) then
+            SRCLK_EN <= '1';
+          else
+            wait_cntr <= wait_cntr + 1;
+          end if;
+          if (start_endless_mode = '0') then
+            SRCLK_EN <= '0';
+            wait_cntr <= 0;
+            state_main <= MAIN;
+          end if;
+         
+        when READ_STOP_POS =>
+          RSRLOAD_EN <= '0';
+          if (stop_pos_cntr = 10) then
+            stop_pos (0) <= stop_pos_int (0);
+            stop_pos (1) <= stop_pos_int (1);
+            stop_pos (2) <= stop_pos_int (2);
+            stop_pos (3) <= stop_pos_int (3);
+            stop_pos_valid <= '1';
+            stop_pos_cntr <= 0;
+            SRCLK_EN <= '0';
+            state_main <= MAIN;
+          else
+            SRCLK_EN <= '1';
+            stop_pos_int (0) <= stop_pos_int (0) (8 downto 0) & SROUT_in_0;
+            stop_pos_int (1) <= stop_pos_int (1) (8 downto 0) & SROUT_in_1;
+            stop_pos_int (2) <= stop_pos_int (2) (8 downto 0) & SROUT_in_2;
+            stop_pos_int (3) <= stop_pos_int (3) (8 downto 0) & SROUT_in_3;
+            stop_pos_cntr <= stop_pos_cntr + 1;
+          end if;
+            
+      end case; -- state_main
+    end if;
+
+  end process main_proc;
+
+end behavior;
Index: FPGA/FAD/FACT_FAD_lib/hdl/fad_board.ucf
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/fad_board.ucf	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/fad_board.ucf	(revision 215)
@@ -0,0 +1,250 @@
+###########################################################
+# Pin location constraints
+###########################################################
+
+#CLOCK
+NET X_50M LOC  = AF13 | IOSTANDARD=LVCMOS33;		#ok
+
+## single ended trigger input
+NET TRG LOC  = AC8 | IOSTANDARD=LVCMOS33;			#ok
+
+## trigger veto: xilinx output
+NET TRG_V LOC  = AC9 | IOSTANDARD=LVCMOS33;			#ok   
+## NET INIT_B LOC  = AA15 | IOSTANDARD=LVCMOS33;		#ok
+
+
+
+# RS485 Driver
+
+NET RS485_C_DE LOC  = C5 | IOSTANDARD=LVCMOS33;		#ok
+NET RS485_C_RE LOC  = C6 | IOSTANDARD=LVCMOS33;		#ok
+#NET RS485_C_DO LOC  = C7 | IOSTANDARD=LVCMOS33;		#ok
+#NET RS485_C_DI LOC  = C8 | IOSTANDARD=LVCMOS33;		#ok
+
+NET RS485_E_DE LOC  = D20 | IOSTANDARD=LVCMOS33;		#ok
+NET RS485_E_RE LOC  = D21 | IOSTANDARD=LVCMOS33;		#ok
+#NET RS485_E_DO LOC  = D22 | IOSTANDARD=LVCMOS33;		#ok
+#NET RS485_E_DI LOC  = D23 | IOSTANDARD=LVCMOS33;		#ok
+
+
+# BOARD ID  - inputs
+#NET LINE<0> LOC  = Y1 | IOSTANDARD=LVCMOS33;		#ok
+#NET LINE<1> LOC  = Y2 | IOSTANDARD=LVCMOS33;		#ok
+#NET LINE<2> LOC  = AB1 | IOSTANDARD=LVCMOS33;		#ok
+#NET LINE<3> LOC  = AC1 | IOSTANDARD=LVCMOS33;		#ok
+#NET LINE<4> LOC  = AD1 | IOSTANDARD=LVCMOS33;		#ok
+#NET LINE<5> LOC  = AD2 | IOSTANDARD=LVCMOS33;		#ok
+
+# W5300 
+#######################################################
+NET W_D<15> LOC  = D24 | IOSTANDARD=LVCMOS33;		#ok
+NET W_D<14> LOC  = D25 | IOSTANDARD=LVCMOS33;		#ok
+NET W_D<13> LOC  = D26 | IOSTANDARD=LVCMOS33;		#ok
+NET W_D<12> LOC  = E24 | IOSTANDARD=LVCMOS33;		#ok
+NET W_D<11> LOC  = E26 | IOSTANDARD=LVCMOS33;		#ok
+NET W_D<10> LOC  = F25 | IOSTANDARD=LVCMOS33;		#ok
+NET W_D<9> LOC  = F24 | IOSTANDARD=LVCMOS33;		#ok
+NET W_D<8> LOC  = G23 | IOSTANDARD=LVCMOS33;		#ok
+NET W_D<7> LOC  = G24 | IOSTANDARD=LVCMOS33;		#ok
+NET W_D<6> LOC  = J23 | IOSTANDARD=LVCMOS33;		#ok
+NET W_D<5> LOC  = K25 | IOSTANDARD=LVCMOS33;		#ok
+NET W_D<4> LOC  = K26 | IOSTANDARD=LVCMOS33;		#ok
+NET W_D<3> LOC  = J22 | IOSTANDARD=LVCMOS33;		#ok
+NET W_D<2> LOC  = K23 | IOSTANDARD=LVCMOS33;		#ok
+NET W_D<1> LOC  = L22 | IOSTANDARD=LVCMOS33;		#ok
+NET W_D<0> LOC  = M22 | IOSTANDARD=LVCMOS33;		#ok
+
+NET W_A<9> LOC  = V24 | IOSTANDARD=LVCMOS33;		#ok
+NET W_A<8> LOC  = V25 | IOSTANDARD=LVCMOS33;		#ok
+NET W_A<7> LOC  = W23 | IOSTANDARD=LVCMOS33;		#ok
+NET W_A<6> LOC  = Y23 | IOSTANDARD=LVCMOS33;		#ok
+NET W_A<5> LOC  = Y24 | IOSTANDARD=LVCMOS33;		#ok
+NET W_A<4> LOC  = Y25 | IOSTANDARD=LVCMOS33;		#ok
+NET W_A<3> LOC  = AA23 | IOSTANDARD=LVCMOS33;		#ok
+NET W_A<2> LOC  = AA24 | IOSTANDARD=LVCMOS33;		#ok
+NET W_A<1> LOC  = AA25 | IOSTANDARD=LVCMOS33;		#ok
+NET W_A<0> LOC  = Y22 | IOSTANDARD=LVCMOS33;		#ok DUMMY
+
+NET W_WR LOC  = P22 | IOSTANDARD=LVCMOS33;			#ok
+NET W_RD LOC  = R20 | IOSTANDARD=LVCMOS33;			#ok
+NET W_CS LOC  = T20 | IOSTANDARD=LVCMOS33;			#ok
+NET W_INT LOC  = U22 | IOSTANDARD=LVCMOS33;			#ok
+NET W_RES LOC  = U23 | IOSTANDARD=LVCMOS33;			#ok
+
+#NET W_BRDY<3> LOC  = AD26 | IOSTANDARD=LVCMOS33;	#ok
+#NET W_BRDY<2> LOC  = AC26 | IOSTANDARD=LVCMOS33;	#ok
+#NET W_BRDY<1> LOC  = AC25 | IOSTANDARD=LVCMOS33;	#ok
+#NET W_BRDY<0> LOC  = AB26 | IOSTANDARD=LVCMOS33;	#ok
+# Testpoint near W5300 
+#NET W_T<3> LOC  = R19 | IOSTANDARD=LVCMOS33;		#ok
+#NET W_T<2> LOC  = N21 | IOSTANDARD=LVCMOS33;		#ok
+#NET W_T<1> LOC  = M21 | IOSTANDARD=LVCMOS33;		#ok
+#NET W_T<0> LOC  = K21 | IOSTANDARD=LVCMOS33;		#ok
+
+# Platform Flash - serial connection
+#######################################################
+##NET FL_CLK LOC  = AE24 | IOSTANDARD=LVCMOS33;		#ok
+##NET FL_D0 LOC  = AF24 | IOSTANDARD=LVCMOS33;		#ok 
+
+# DRS Signals
+#######################################################
+NET DENABLE LOC  = B1 | IOSTANDARD=LVCMOS25;		#ok
+NET DWRITE LOC  = R2 | IOSTANDARD=LVCMOS25;			#ok
+
+NET SRIN LOC  = E1 | IOSTANDARD=LVCMOS25;			#ok -- nur fuer vollauslese noetig; auf Z legen.
+#NET REFCLK LOC  = AC11 | IOSTANDARD=LVCMOS25;		#ok -- listen to REFCLK possible
+
+
+NET D_A<3> LOC  = N1 | IOSTANDARD=LVCMOS25;			#ok
+NET D_A<2> LOC  = M2 | IOSTANDARD=LVCMOS25;			#ok
+NET D_A<1> LOC  = K2 | IOSTANDARD=LVCMOS25;			#ok
+NET D_A<0> LOC  = H2 | IOSTANDARD=LVCMOS25;			#ok
+
+
+# PLL-Lock input: high active
+#NET D0_PLLLCK LOC  = L3 | IOSTANDARD=LVCMOS25;		#ok
+#NET D1_PLLLCK LOC  = N2 | IOSTANDARD=LVCMOS25;		#ok
+#NET D2_PLLLCK LOC  = AA2 | IOSTANDARD=LVCMOS25;		#ok
+#NET D3_PLLLCK LOC  = AC2 | IOSTANDARD=LVCMOS25;		#ok
+
+# SROUT input: read stop position here
+# bus??
+NET D0_SROUT LOC  = B2 | IOSTANDARD=LVCMOS25;		#ok
+NET D1_SROUT LOC  = E3 | IOSTANDARD=LVCMOS25;		#ok
+NET D2_SROUT LOC  = N4 | IOSTANDARD=LVCMOS25;		#ok
+NET D3_SROUT LOC  = U1 | IOSTANDARD=LVCMOS25;		#ok
+
+# RSRLOAD & SRCLK output: clock out analog samples here
+# 														SRCLK bus??
+NET RSRLOAD LOC  = H1 | IOSTANDARD=LVCMOS25;		#ok
+#
+NET D0_SRCLK LOC  = F2 | IOSTANDARD=LVCMOS25;		#ok
+NET D1_SRCLK LOC  = F3 | IOSTANDARD=LVCMOS25;		#ok
+NET D2_SRCLK LOC  = R3 | IOSTANDARD=LVCMOS25;		#ok
+NET D3_SRCLK LOC  = V1 | IOSTANDARD=LVCMOS25;		#ok
+
+# Testpoints near DRS Chips 
+# oganized in 3 times 4x2 pins
+#NET D_T<0> LOC  = D3 | IOSTANDARD=LVCMOS25;			#ok
+#NET D_T<1> LOC  = G3 | IOSTANDARD=LVCMOS25;			#ok
+#NET D_T<2> LOC  = G4 | IOSTANDARD=LVCMOS25;			#ok
+#NET D_T<3> LOC  = J4 | IOSTANDARD=LVCMOS25;			#ok
+#NET D_T<4> LOC  = K5 | IOSTANDARD=LVCMOS25;			#ok
+#NET D_T<5> LOC  = L4 | IOSTANDARD=LVCMOS25;			#ok
+#NET D_T<6> LOC  = M3 | IOSTANDARD=LVCMOS25;			#ok
+#NET D_T<7> LOC  = T3 | IOSTANDARD=LVCMOS25;			#ok
+#NET D_T<8> LOC  = U2 | IOSTANDARD=LVCMOS25;			#ok
+#NET D_T<9> LOC  = V2 | IOSTANDARD=LVCMOS25;			#ok
+#NET D_T<10> LOC  = W3 | IOSTANDARD=LVCMOS25;		#ok aka D_TA
+#NET D_T<11> LOC  = AA3 | IOSTANDARD=LVCMOS25;		#ok aka D_TB
+
+# ADC Signals
+#######################################################
+NET OE_ADC LOC  = D6 | IOSTANDARD=LVCMOS33;			#ok FIXME was A-OEB
+
+NET A_CLK<0> LOC  = B23 | IOSTANDARD=LVCMOS33; 		#ok aka A0_CLK
+NET A_CLK<1> LOC  = A3 | IOSTANDARD=LVCMOS33;		#ok aka A1_CLK
+NET A_CLK<2> LOC  = AE3 | IOSTANDARD=LVCMOS33;		#ok aka A2_CLK
+NET A_CLK<3> LOC  = AE25 | IOSTANDARD=LVCMOS33;		#ok aka A3_CLK
+
+NET A_OTR<0> LOC  = A22 | IOSTANDARD=LVCMOS33;		#ok aka A0_OTR
+NET A_OTR<1> LOC  = B12 | IOSTANDARD=LVCMOS33;		#ok aka A1_OTR
+NET A_OTR<2> LOC  = AF3 | IOSTANDARD=LVCMOS33;		#ok aka A2_OTR
+NET A_OTR<3> LOC  = AE17 | IOSTANDARD=LVCMOS33;		#ok aka A3_OTR
+
+# ADC data
+NET A0_D<0> LOC  = D13 | IOSTANDARD=LVCMOS33;		#ok 
+NET A0_D<1> LOC  = A15 | IOSTANDARD=LVCMOS33;		#ok
+NET A0_D<2> LOC  = B15 | IOSTANDARD=LVCMOS33;		#ok
+NET A0_D<3> LOC  = B17 | IOSTANDARD=LVCMOS33;		#ok
+NET A0_D<4> LOC  = D16 | IOSTANDARD=LVCMOS33;		#ok
+NET A0_D<5> LOC  = A18 | IOSTANDARD=LVCMOS33;		#ok
+NET A0_D<6> LOC  = B18 | IOSTANDARD=LVCMOS33;		#ok
+NET A0_D<7> LOC  = A19 | IOSTANDARD=LVCMOS33;		#ok
+NET A0_D<8> LOC  = B19 | IOSTANDARD=LVCMOS33;		#ok
+NET A0_D<9> LOC  = A20 | IOSTANDARD=LVCMOS33;		#ok
+NET A0_D<10> LOC  = B21 | IOSTANDARD=LVCMOS33; 		#ok
+NET A0_D<11> LOC  = C22 | IOSTANDARD=LVCMOS33;		#ok
+
+NET A1_D<0> LOC  = B3 | IOSTANDARD=LVCMOS33;		#ok
+NET A1_D<1> LOC  = A4 | IOSTANDARD=LVCMOS33;		#ok
+NET A1_D<2> LOC  = B4 | IOSTANDARD=LVCMOS33;		#ok
+NET A1_D<3> LOC  = B6 | IOSTANDARD=LVCMOS33;		#ok
+NET A1_D<4> LOC  = B7 | IOSTANDARD=LVCMOS33;		#ok
+NET A1_D<5> LOC  = A8 | IOSTANDARD=LVCMOS33;		#ok
+NET A1_D<6> LOC  = B8 | IOSTANDARD=LVCMOS33;		#ok
+NET A1_D<7> LOC  = A9 | IOSTANDARD=LVCMOS33;		#ok
+NET A1_D<8> LOC  = B9 | IOSTANDARD=LVCMOS33;		#ok
+NET A1_D<9> LOC  = A10 | IOSTANDARD=LVCMOS33;		#ok
+NET A1_D<10> LOC  = B10 | IOSTANDARD=LVCMOS33;		#ok
+NET A1_D<11> LOC  = A12 | IOSTANDARD=LVCMOS33;		#ok
+
+NET A2_D<0> LOC  = AD14 | IOSTANDARD=LVCMOS33;		#ok
+NET A2_D<1> LOC  = AD11 | IOSTANDARD=LVCMOS33;		#ok
+NET A2_D<2> LOC  = AD7 | IOSTANDARD=LVCMOS33;		#ok
+NET A2_D<3> LOC  = AE8 | IOSTANDARD=LVCMOS33;		#ok
+NET A2_D<4> LOC  = AF8 | IOSTANDARD=LVCMOS33;		#ok
+NET A2_D<5> LOC  = AE7 | IOSTANDARD=LVCMOS33;		#ok
+NET A2_D<6> LOC  = AC6 | IOSTANDARD=LVCMOS33;		#ok
+NET A2_D<7> LOC  = AE6 | IOSTANDARD=LVCMOS33;		#ok
+NET A2_D<8> LOC  = AF5 | IOSTANDARD=LVCMOS33;		#ok
+NET A2_D<9> LOC  = AD6 | IOSTANDARD=LVCMOS33;		#ok
+NET A2_D<10> LOC  = AF4 | IOSTANDARD=LVCMOS33;		#ok
+NET A2_D<11> LOC  = AE4 | IOSTANDARD=LVCMOS33;		#ok
+
+NET A3_D<0> LOC  = AF25 | IOSTANDARD=LVCMOS33;		#ok
+NET A3_D<1> LOC  = AE23 | IOSTANDARD=LVCMOS33;		#ok
+NET A3_D<2> LOC  = AF23 | IOSTANDARD=LVCMOS33;		#ok
+NET A3_D<3> LOC  = AD22 | IOSTANDARD=LVCMOS33;		#ok
+NET A3_D<4> LOC  = AE21 | IOSTANDARD=LVCMOS33;		#ok
+NET A3_D<5> LOC  = AD21 | IOSTANDARD=LVCMOS33;		#ok
+NET A3_D<6> LOC  = AF20 | IOSTANDARD=LVCMOS33;		#ok
+NET A3_D<7> LOC  = AE20 | IOSTANDARD=LVCMOS33;		#ok
+NET A3_D<8> LOC  = AF19 | IOSTANDARD=LVCMOS33;		#ok
+NET A3_D<9> LOC  = AC22 | IOSTANDARD=LVCMOS33;		#ok
+NET A3_D<10> LOC  = AE19 | IOSTANDARD=LVCMOS33;		#ok
+NET A3_D<11> LOC  = AD19 | IOSTANDARD=LVCMOS33;		#ok
+
+# testpoints near ADC
+
+#NET A0_T<0> LOC  = D8 | IOSTANDARD=LVCMOS33;		#ok
+#NET A0_T<1> LOC  = D9 | IOSTANDARD=LVCMOS33;		#ok
+#NET A0_T<2> LOC  = D10 | IOSTANDARD=LVCMOS33;		#ok
+#NET A0_T<3> LOC  = E10 | IOSTANDARD=LVCMOS33;		#ok
+#NET A0_T<4> LOC  = E12 | IOSTANDARD=LVCMOS33;		#ok
+#NET A0_T<5> LOC  = E14 | IOSTANDARD=LVCMOS33;		#ok
+#NET A0_T<6> LOC  = D17 | IOSTANDARD=LVCMOS33;		#ok
+#NET A0_T<7> LOC  = D18 | IOSTANDARD=LVCMOS33;		#ok
+
+#NET A1_T<0> LOC  = AB9 | IOSTANDARD=LVCMOS33;		#ok
+#NET A1_T<1> LOC  = AB12 | IOSTANDARD=LVCMOS33;		#ok
+#NET A1_T<2> LOC  = AC12 | IOSTANDARD=LVCMOS33;		#ok
+#NET A1_T<3> LOC  = AC14 | IOSTANDARD=LVCMOS33;		#ok
+#NET A1_T<4> LOC  = AC15 | IOSTANDARD=LVCMOS33;		#ok
+#NET A1_T<5> LOC  = AB16 | IOSTANDARD=LVCMOS33; 		#ok
+#NET A1_T<6> LOC  = AC16 | IOSTANDARD=LVCMOS33;		#ok
+#NET A1_T<7> LOC  = AB18 | IOSTANDARD=LVCMOS33;		#ok
+
+
+
+# SPI bus
+#######################################################
+NET S_CLK LOC  = C10 | IOSTANDARD=LVCMOS33;			#ok
+NET MOSI LOC  = C11 | IOSTANDARD=LVCMOS33;			#ok
+NET MISO LOC  = C12 | IOSTANDARD=LVCMOS33;			#ok
+
+NET T0_CS LOC  = C15 | IOSTANDARD=LVCMOS33;			#ok
+NET T1_CS LOC  = C16 | IOSTANDARD=LVCMOS33;			#ok
+NET T2_CS LOC  = C17 | IOSTANDARD=LVCMOS33;			#ok
+NET T3_CS LOC  = C18 | IOSTANDARD=LVCMOS33;			#ok
+NET DAC_CS LOC  = C20 | IOSTANDARD=LVCMOS33;		#ok
+NET EE_CS LOC  = C21 | IOSTANDARD=LVCMOS33; 		#ok
+
+
+
+# LEDs
+#######################################################
+NET LED_0 LOC  = C23 | IOSTANDARD=LVCMOS33; 		#ok -- ??? besser Z
+NET LED_2 LOC  = AD20 | IOSTANDARD=LVCMOS33;		#ok
+NET LED_3 LOC  = T4 | IOSTANDARD=LVCMOS25;			#ok
+
Index: FPGA/FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd	(revision 215)
@@ -0,0 +1,232 @@
+-- VHDL Entity FACT_FAD_lib.FAD_Board.symbol
+--
+-- Created:
+--          by - kai.UNKNOWN (E5PCXX)
+--          at - 15:27:37 19.05.2010
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FAD_Board IS
+   PORT( 
+      A0_D       : IN     std_logic_vector (11 DOWNTO 0);
+      A1_D       : IN     std_logic_vector (11 DOWNTO 0);
+      A2_D       : IN     std_logic_vector (11 DOWNTO 0);
+      A3_D       : IN     std_logic_vector (11 DOWNTO 0);
+      A_OTR      : IN     std_logic_vector (3 DOWNTO 0);
+      D0_SROUT   : IN     std_logic;
+      D1_SROUT   : IN     std_logic;
+      D2_SROUT   : IN     std_logic;
+      D3_SROUT   : IN     std_logic;
+      TRG        : IN     STD_LOGIC;
+      W_INT      : IN     std_logic;
+      X_50M      : IN     STD_LOGIC;
+      A_CLK      : OUT    std_logic_vector (3 DOWNTO 0);
+      D0_SRCLK   : OUT    STD_LOGIC;
+      D1_SRCLK   : OUT    STD_LOGIC;
+      D2_SRCLK   : OUT    STD_LOGIC;
+      D3_SRCLK   : OUT    STD_LOGIC;
+      DAC_CS     : OUT    std_logic;
+      DENABLE    : OUT    std_logic;
+      DWRITE     : OUT    std_logic                     := '1';
+      D_A        : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
+      EE_CS      : OUT    std_logic;
+      LED_0      : OUT    std_logic;
+      LED_2      : OUT    std_logic;
+      LED_3      : OUT    std_logic;
+      MOSI       : OUT    std_logic                     := '0';
+      OE_ADC     : OUT    STD_LOGIC;
+      RS485_C_DE : OUT    std_logic;
+      RS485_C_RE : OUT    std_logic;
+      RS485_E_DE : OUT    std_logic;
+      RS485_E_RE : OUT    std_logic;
+      RSRLOAD    : OUT    std_logic                     := '0';
+      SRIN       : OUT    std_logic;
+      S_CLK      : OUT    std_logic;
+      T0_CS      : OUT    std_logic;
+      T1_CS      : OUT    std_logic;
+      T2_CS      : OUT    std_logic;
+      T3_CS      : OUT    std_logic;
+      TRG_V      : OUT    std_logic;
+      W_A        : OUT    std_logic_vector (9 DOWNTO 0);
+      W_CS       : OUT    std_logic                     := '1';
+      W_RD       : OUT    std_logic                     := '1';
+      W_RES      : OUT    std_logic                     := '1';
+      W_WR       : OUT    std_logic                     := '1';
+      MISO       : INOUT  std_logic;
+      W_D        : INOUT  std_logic_vector (15 DOWNTO 0)
+   );
+
+-- Declarations
+
+END FAD_Board ;
+
+--
+-- VHDL Architecture FACT_FAD_lib.FAD_Board.struct
+--
+-- Created:
+--          by - kai.UNKNOWN (E5PCXX)
+--          at - 15:27:37 19.05.2010
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE IEEE.NUMERIC_STD.all;
+
+LIBRARY FACT_FAD_lib;
+USE FACT_FAD_lib.fad_definitions.all;
+LIBRARY FACT_FAD_test_devices_lib;
+USE FACT_FAD_test_devices_lib.drs4_pack.all;
+USE ieee.std_logic_unsigned.all;
+
+LIBRARY FACT_FAD_lib;
+
+ARCHITECTURE struct OF FAD_Board IS
+
+   -- Architecture declarations
+
+   -- Internal signal declarations
+   SIGNAL CLK_25_PS      : std_logic;
+   SIGNAL CLK_50         : std_logic;
+   SIGNAL SRCLK          : std_logic                    := '0';
+   SIGNAL adc_data_array : adc_data_array_type;
+   SIGNAL board_id       : std_logic_vector(3 DOWNTO 0);
+   SIGNAL crate_id       : std_logic_vector(1 DOWNTO 0);
+   SIGNAL led            : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
+   SIGNAL sensor_cs      : std_logic_vector(3 DOWNTO 0);
+
+
+   -- Component Declarations
+   COMPONENT FAD_main
+   PORT (
+      CLK            : IN     std_logic ;
+      SROUT_in_0     : IN     std_logic ;
+      SROUT_in_1     : IN     std_logic ;
+      SROUT_in_2     : IN     std_logic ;
+      SROUT_in_3     : IN     std_logic ;
+      adc_data_array : IN     adc_data_array_type ;
+      adc_otr_array  : IN     std_logic_vector (3 DOWNTO 0);
+      board_id       : IN     std_logic_vector (3 DOWNTO 0);
+      crate_id       : IN     std_logic_vector (1 DOWNTO 0);
+      trigger        : IN     std_logic ;
+      wiz_int        : IN     std_logic ;
+      CLK_25_PS      : OUT    std_logic ;
+      CLK_50         : OUT    std_logic ;
+      RSRLOAD        : OUT    std_logic                     := '0';
+      SRCLK          : OUT    std_logic                     := '0';
+      adc_oeb        : OUT    std_logic                     := '1';
+      dac_cs         : OUT    std_logic ;
+      drs_channel_id : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
+      drs_dwrite     : OUT    std_logic                     := '1';
+      led            : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
+      mosi           : OUT    std_logic                     := '0';
+      sclk           : OUT    std_logic ;
+      sensor_cs      : OUT    std_logic_vector (3 DOWNTO 0);
+      wiz_addr       : OUT    std_logic_vector (9 DOWNTO 0);
+      wiz_cs         : OUT    std_logic                     := '1';
+      wiz_rd         : OUT    std_logic                     := '1';
+      wiz_reset      : OUT    std_logic                     := '1';
+      wiz_wr         : OUT    std_logic                     := '1';
+      sio            : INOUT  std_logic ;
+      wiz_data       : INOUT  std_logic_vector (15 DOWNTO 0)
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main;
+   -- pragma synthesis_on
+
+
+BEGIN
+   -- Architecture concurrent statements
+   -- HDL Embedded Text Block 1 eb_ID
+   -- hard-wired IDs
+   board_id <= "0101";
+   crate_id <= "01";
+
+   -- HDL Embedded Text Block 2 ADC_CLK
+   -- ADC_CLK 2
+   A_CLK (0) <= CLK_25_PS;
+   A_CLK (1) <= CLK_25_PS;
+   A_CLK (2) <= CLK_25_PS;
+   A_CLK (3) <= CLK_25_PS;                                        
+
+   -- HDL Embedded Text Block 3 ADC_DATA
+   -- ADC_DATA 3 
+   adc_data_array (0) <= A0_D;
+   adc_data_array (1) <= A1_D;
+   adc_data_array (2) <= A2_D;
+   adc_data_array (3) <= A3_D;                                       
+
+   -- HDL Embedded Text Block 4 SRCLK
+   -- SRCLK 4         
+   D0_SRCLK <= SRCLK;
+   D1_SRCLK <= SRCLK;
+   D2_SRCLK <= SRCLK;
+   D3_SRCLK <= SRCLK;                               
+
+   -- HDL Embedded Text Block 5 T_CS
+   -- T_CS 5
+   T0_CS <= sensor_cs (0); 
+   T1_CS <= sensor_cs (1);
+   T2_CS <= sensor_cs (2);
+   T3_CS <= sensor_cs (3);                                      
+
+   -- HDL Embedded Text Block 6 MISC
+   -- MISC 6     
+   TRG_V <= '0';
+   RS485_C_RE <= '1'; 
+   RS485_C_DE <= '0';   
+   RS485_E_RE <= '1';      
+   RS485_E_DE <= '0'; 
+   DENABLE <= '1';
+   SRIN <= 'Z';
+   EE_CS <= '1';
+   LED_0 <= 'Z';
+   LED_2 <= 'Z';
+   LED_3 <= 'Z';
+                                 
+
+
+   -- Instance port mappings.
+   I_testboard_main : FAD_main
+      PORT MAP (
+         CLK            => X_50M,
+         SROUT_in_0     => D0_SROUT,
+         SROUT_in_1     => D1_SROUT,
+         SROUT_in_2     => D2_SROUT,
+         SROUT_in_3     => D3_SROUT,
+         adc_data_array => adc_data_array,
+         adc_otr_array  => A_OTR,
+         board_id       => board_id,
+         crate_id       => crate_id,
+         trigger        => TRG,
+         wiz_int        => W_INT,
+         CLK_25_PS      => CLK_25_PS,
+         CLK_50         => CLK_50,
+         RSRLOAD        => RSRLOAD,
+         SRCLK          => SRCLK,
+         adc_oeb        => OE_ADC,
+         dac_cs         => DAC_CS,
+         drs_channel_id => D_A,
+         drs_dwrite     => DWRITE,
+         led            => led,
+         mosi           => MOSI,
+         sclk           => S_CLK,
+         sensor_cs      => sensor_cs,
+         wiz_addr       => W_A,
+         wiz_cs         => W_CS,
+         wiz_rd         => W_RD,
+         wiz_reset      => W_RES,
+         wiz_wr         => W_WR,
+         sio            => MISO,
+         wiz_data       => W_D
+      );
+
+END struct;
Index: FPGA/FAD/FACT_FAD_lib/hdl/fad_definitions.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/fad_definitions.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/fad_definitions.vhd	(revision 215)
@@ -0,0 +1,107 @@
+--	Package File Template
+--
+--	Purpose: This package defines supplemental types, subtypes, 
+--		 constants, and functions 
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+-- use IEEE.NUMERIC_STD.ALL;
+
+package fad_definitions is
+
+  
+-- Declare constants
+
+-- Network Settings
+  type mac_type is array (0 to 2) of std_logic_vector (15 downto 0);
+  constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"97B4"); 
+  
+  type ip_type is array (0 to 3) of integer;
+  constant NETMASK : ip_type := (255, 255, 255, 0);
+  constant IP_ADDRESS : ip_type := (129, 217, 160, 119);
+  constant GATEWAY : ip_type := (129, 217, 160, 1);
+  constant FIRST_PORT : integer := 5000;
+  
+  constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"01";
+  constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"02";
+  constant PACKAGE_HEADER_LENGTH : integer := 22;
+  constant PACKAGE_END_LENGTH : integer := 2; -- CRC and END-Flag
+  
+  constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset
+
+-- W5300 Registers
+	constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0'); 
+	constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0";
+	constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2";
+	constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4";
+	constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8";
+	constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10";
+	constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14";
+	constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18";
+	constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20";
+	constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22";
+  constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24";
+  constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26";
+  constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28";
+  constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A";
+  constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C";
+  constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E";        	
+  constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30";
+	
+	constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0";
+	constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2";
+	constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4";
+	constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6";
+	constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8";
+	constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A";
+	constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12";
+	constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14";
+	constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20";
+	constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24";
+  constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28";
+	constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E";
+  constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30";
+-- End W5300 registers	
+
+-- 
+  constant W5300_TX_FIFO_SIZE : integer := (15360 / 2); -- Socket TX FIFO-Size in 16 Bit Words
+
+  constant RAM_SIZE_64B : integer := 4096;
+  constant RAM_SIZE_16B : integer := RAM_SIZE_64B * 4;
+
+-- TYPE definitions
+  type roi_max_type is array (0 to 8) of std_logic_vector (10 downto 0);
+  type roi_array_type is array (0 to 35) of integer range 0 to 1024;
+  type drs_s_cell_array_type is array (0 to 3) of std_logic_vector (9 downto 0);
+  type adc_data_array_type is array (0 to 3) of std_logic_vector (11 downto 0);
+
+  type dac_array_type is array (0 to 7) of integer range 0 to 2**16 - 1;
+  type sensor_array_type is array (0 to 3) of integer range 0 to 2**16 - 1;
+  
+--  constant DEFAULT_ROI : roi_array_type := (115, 125, 100, 102, 155, 101,   0, 101, 106, 
+--                                            181, 121, 189, 101, 101, 187,  56, 187, 101,
+--                                              2, 141, 101, 100,  10, 100, 178, 101, 174, 
+--                                             12, 181, 100, 102, 101, 102,   0, 101, 108); 
+  constant DEFAULT_ROI : roi_array_type := (others => 100);
+  
+--  constant DEFAULT_DAC : dac_array_type := (5001, 5002, 5003, 5004, 5005, 5006, 5007, 5008);
+  constant DEFAULT_DAC : dac_array_type := (others => 0);
+
+-- Commands
+  constant CMD_START : std_logic_vector := X"C0";
+  constant CMD_STOP : std_logic_vector := X"30";
+  constant CMD_TRIGGER : std_logic_vector := X"A0";
+  constant CMD_TRIGGER_C : std_logic_vector := X"B0";
+  constant CMD_TRIGGER_S : std_logic_vector := X"20";
+  constant CMD_READ : std_logic_vector := X"0A";
+  constant CMD_WRITE : std_logic_vector := X"05";
+
+-- Declare functions and procedure
+
+
+end fad_definitions;
+
+
Index: FPGA/FAD/FACT_FAD_lib/hdl/fad_main.ucf
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/fad_main.ucf	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/fad_main.ucf	(revision 215)
@@ -0,0 +1,81 @@
+Net clk LOC = E12 | IOSTANDARD=LVCMOS33;
+
+
+## Net reset LOC = R13 | IOSTANDARD=LVCMOS33 | PULLDOWN;
+
+Net wiz_reset LOC = H19 | IOSTANDARD=LVCMOS33;
+Net wiz_cs LOC = J18 | IOSTANDARD=LVCMOS33;
+Net wiz_wr LOC = K18 | IOSTANDARD=LVCMOS33;
+Net wiz_rd LOC = K17 | IOSTANDARD=LVCMOS33;
+Net wiz_int LOC = K19 | IOSTANDARD=LVCMOS33;
+
+## Net trigger CLOCK_DEDICATED_ROUTE = FALSE;
+Net trigger LOC = R13 | IOSTANDARD=LVCMOS33 | PULLDOWN;
+
+Net wiz_addr<0> LOC = B20 | IOSTANDARD=LVCMOS33;
+Net wiz_addr<1> LOC = A20 | IOSTANDARD=LVCMOS33;
+Net wiz_addr<2> LOC = C19 | IOSTANDARD=LVCMOS33;
+Net wiz_addr<3> LOC = B19 | IOSTANDARD=LVCMOS33;
+Net wiz_addr<4> LOC = D19 | IOSTANDARD=LVCMOS33;
+Net wiz_addr<5> LOC = A19 | IOSTANDARD=LVCMOS33;
+Net wiz_addr<6> LOC = D18 | IOSTANDARD=LVCMOS33;
+Net wiz_addr<7> LOC = C18 | IOSTANDARD=LVCMOS33;
+Net wiz_addr<8> LOC = E17 | IOSTANDARD=LVCMOS33;
+Net wiz_addr<9> LOC = A18 | IOSTANDARD=LVCMOS33;
+
+Net wiz_data<0> LOC = B17 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+Net wiz_data<1> LOC = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+Net wiz_data<2> LOC = A17 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+Net wiz_data<3> LOC = D21 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+Net wiz_data<4> LOC = A16 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+Net wiz_data<5> LOC = D22 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+Net wiz_data<6> LOC = A15 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+Net wiz_data<7> LOC = E22 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+Net wiz_data<8> LOC = B15 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+Net wiz_data<9> LOC = F18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+Net wiz_data<10> LOC = A14 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+Net wiz_data<11> LOC = F19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+Net wiz_data<12> LOC = B13 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+Net wiz_data<13> LOC = F20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+Net wiz_data<14> LOC = A13 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+Net wiz_data<15> LOC = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+
+NET led<7> LOC = W21 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET led<6> LOC = Y22 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET led<5> LOC = V20 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET led<4> LOC = V19 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET led<3> LOC = U19 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET led<2> LOC = U20 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET led<1> LOC = T19 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET led<0> LOC = R20 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+
+NET rsrload LOC = B4 | IOSTANDARD = LVCMOS33;
+NET srclk LOC = A4 | IOSTANDARD = LVCMOS33;
+NET clk_50 LOC = B6 | IOSTANDARD = LVCMOS33;
+NET clk_25_ps LOC = A5 | IOSTANDARD = LVCMOS33;
+
+##NET "RX_CLK_N"      LOC = "A11"  | IOSTANDARD = LVCMOS33 ;
+##NET "RX_CLK_P"      LOC = "A12"  | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<19>       LOC = "B4"   | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<18>       LOC = "A4"   | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<17>       LOC = "A5"   | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<16>       LOC = "B6"   | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<15>       LOC = "A6"   | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<14>       LOC = "A7"   | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<13>       LOC = "A8"   | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<12>       LOC = "A9"   | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<11>       LOC = "C10"  | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<10>       LOC = "A10"  | IOSTANDARD = LVCMOS33 ;
+##NET "TX_CLK_N"      LOC = "AB10" | IOSTANDARD = LVCMOS33 ;
+##NET "TX_CLK_P"      LOC = "AA10" | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<9>       LOC = "AA3"  | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<8>       LOC = "AB2"  | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<7>       LOC = "AA4"  | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<6>       LOC = "AB3"  | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<5>       LOC = "AB6"  | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<4>       LOC = "AA6"  | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<3>       LOC = "AB7"  | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<2>       LOC = "Y7"   | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<1>       LOC = "AB8"  | IOSTANDARD = LVCMOS33 ;
+#NET dbg_cntr<0>       LOC = "AA8"  | IOSTANDARD = LVCMOS33 ;
+# 
Index: FPGA/FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd	(revision 215)
@@ -0,0 +1,501 @@
+-- VHDL Entity FACT_FAD_lib.FAD_main.symbol
+--
+-- Created:
+--          by - kai.UNKNOWN (E5PCXX)
+--          at - 15:27:35 19.05.2010
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+LIBRARY FACT_FAD_lib;
+USE FACT_FAD_lib.fad_definitions.all;
+
+ENTITY FAD_main IS
+   PORT( 
+      CLK            : IN     std_logic;
+      SROUT_in_0     : IN     std_logic;
+      SROUT_in_1     : IN     std_logic;
+      SROUT_in_2     : IN     std_logic;
+      SROUT_in_3     : IN     std_logic;
+      adc_data_array : IN     adc_data_array_type;
+      adc_otr_array  : IN     std_logic_vector (3 DOWNTO 0);
+      board_id       : IN     std_logic_vector (3 DOWNTO 0);
+      crate_id       : IN     std_logic_vector (1 DOWNTO 0);
+      trigger        : IN     std_logic;
+      wiz_int        : IN     std_logic;
+      CLK_25_PS      : OUT    std_logic;
+      CLK_50         : OUT    std_logic;
+      RSRLOAD        : OUT    std_logic                     := '0';
+      SRCLK          : OUT    std_logic                     := '0';
+      adc_oeb        : OUT    std_logic                     := '1';
+      dac_cs         : OUT    std_logic;
+      drs_channel_id : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
+      drs_dwrite     : OUT    std_logic                     := '1';
+      led            : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
+      mosi           : OUT    std_logic                     := '0';
+      sclk           : OUT    std_logic;
+      sensor_cs      : OUT    std_logic_vector (3 DOWNTO 0);
+      wiz_addr       : OUT    std_logic_vector (9 DOWNTO 0);
+      wiz_cs         : OUT    std_logic                     := '1';
+      wiz_rd         : OUT    std_logic                     := '1';
+      wiz_reset      : OUT    std_logic                     := '1';
+      wiz_wr         : OUT    std_logic                     := '1';
+      sio            : INOUT  std_logic;
+      wiz_data       : INOUT  std_logic_vector (15 DOWNTO 0)
+   );
+
+-- Declarations
+
+END FAD_main ;
+
+--
+-- VHDL Architecture FACT_FAD_lib.FAD_main.struct
+--
+-- Created:
+--          by - kai.UNKNOWN (E5PCXX)
+--          at - 15:27:36 19.05.2010
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use ieee.STD_LOGIC_UNSIGNED.all;
+
+library fact_fad_lib;
+use fact_fad_lib.fad_definitions.all;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+USE IEEE.NUMERIC_STD.all;
+USE IEEE.std_logic_signed.all;
+
+LIBRARY FACT_FAD_lib;
+LIBRARY FACT_FAD_TB_lib;
+
+ARCHITECTURE struct OF FAD_main IS
+
+   -- Architecture declarations
+
+   -- Internal signal declarations
+   SIGNAL CLK_25                 : std_logic;
+   SIGNAL adc_data_array_int     : adc_data_array_type;
+   SIGNAL adc_otr                : std_logic_vector(3 DOWNTO 0);
+   SIGNAL addr_out               : std_logic_vector(11 DOWNTO 0);
+   SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0);
+   SIGNAL config_busy            : std_logic;
+   SIGNAL config_data            : std_logic_vector(15 DOWNTO 0);
+   SIGNAL config_data_valid      : std_logic;
+   SIGNAL config_rd_en           : std_logic;
+   SIGNAL config_ready           : std_logic;
+   SIGNAL config_ready_cm        : std_logic;
+   SIGNAL config_ready_spi       : std_logic;
+   SIGNAL config_start           : std_logic                     := '0';
+   SIGNAL config_start_cm        : std_logic;
+   SIGNAL config_start_spi       : std_logic                     := '0';
+   SIGNAL config_started         : std_logic;
+   SIGNAL config_started_cu      : std_logic                     := '0';
+   SIGNAL config_started_mm      : std_logic;
+   SIGNAL config_started_spi     : std_logic                     := '0';
+   SIGNAL config_wr_en           : std_logic;
+   SIGNAL dac_array              : dac_array_type;
+   SIGNAL data_out               : std_logic_vector(63 DOWNTO 0);
+   SIGNAL drs_clk_en             : std_logic                     := '0';
+   SIGNAL drs_read_s_cell        : std_logic                     := '0';
+   SIGNAL drs_read_s_cell_ready  : std_logic;
+   SIGNAL drs_s_cell_array       : drs_s_cell_array_type;
+   SIGNAL new_config             : std_logic                     := '0';
+   SIGNAL package_length         : std_logic_vector(15 DOWNTO 0);
+   SIGNAL ram_addr               : std_logic_vector(13 DOWNTO 0);
+   SIGNAL ram_data               : std_logic_vector(15 DOWNTO 0);
+   SIGNAL ram_start_addr         : std_logic_vector(11 DOWNTO 0);
+   SIGNAL ram_write_ea           : std_logic;
+   SIGNAL ram_write_ready        : std_logic                     := '0';
+   SIGNAL roi_array              : roi_array_type;
+   SIGNAL roi_max                : roi_max_type;
+   SIGNAL s_trigger              : std_logic                     := '0';
+   SIGNAL sensor_array           : sensor_array_type;
+   SIGNAL sensor_ready           : std_logic;
+   SIGNAL trigger_id             : std_logic_vector(47 DOWNTO 0);
+   SIGNAL wiz_busy               : std_logic;
+   SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0)  := (others => '0');
+   SIGNAL wiz_ram_start_addr     : std_logic_vector(13 DOWNTO 0) := (others => '0');
+   SIGNAL wiz_write_ea           : std_logic                     := '0';
+   SIGNAL wiz_write_end          : std_logic                     := '0';
+   SIGNAL wiz_write_header       : std_logic                     := '0';
+   SIGNAL wiz_write_length       : std_logic_vector(16 DOWNTO 0) := (others => '0');
+   SIGNAL write_ea               : std_logic_vector(0 DOWNTO 0)  := "0";
+
+   -- Implicit buffer signal declarations
+   SIGNAL CLK_25_PS_internal : std_logic;
+   SIGNAL CLK_50_internal    : std_logic;
+
+
+   -- Component Declarations
+   COMPONENT adc_buffer
+   PORT (
+      adc_data_array     : IN     adc_data_array_type;
+      adc_otr_array      : IN     std_logic_vector (3 DOWNTO 0);
+      clk_ps             : IN     std_logic;
+      adc_data_array_int : OUT    adc_data_array_type;
+      adc_otr            : OUT    std_logic_vector (3 DOWNTO 0)
+   );
+   END COMPONENT;
+   COMPONENT clock_generator
+   PORT (
+      CLK       : IN     std_logic ;
+      CLK_25    : OUT    std_logic ;
+      CLK_25_PS : OUT    std_logic ;
+      CLK_50    : OUT    std_logic 
+   );
+   END COMPONENT;
+   COMPONENT control_unit
+   PORT (
+      clk               : IN     STD_LOGIC ;
+      config_addr       : IN     std_logic_vector (7 DOWNTO 0);
+      config_rd_en      : IN     std_logic ;
+      config_start      : IN     std_logic ;
+      config_wr_en      : IN     std_logic ;
+      config_busy       : OUT    std_logic ;
+      config_data_valid : OUT    std_logic ;
+      config_ready      : OUT    std_logic ;
+      config_started    : OUT    std_logic  := '0';
+      dac_array         : OUT    dac_array_type ;
+      roi_array         : OUT    roi_array_type ;
+      config_data       : INOUT  std_logic_vector (15 DOWNTO 0)
+   );
+   END COMPONENT;
+   COMPONENT dataRAM_64bit_16bit
+   PORT (
+      clka  : IN     std_logic ;
+      dina  : IN     std_logic_VECTOR (63 DOWNTO 0);
+      addra : IN     std_logic_VECTOR (11 DOWNTO 0);
+      wea   : IN     std_logic_VECTOR (0 DOWNTO 0);
+      clkb  : IN     std_logic ;
+      addrb : IN     std_logic_VECTOR (13 DOWNTO 0);
+      doutb : OUT    std_logic_VECTOR (15 DOWNTO 0)
+   );
+   END COMPONENT;
+   COMPONENT data_generator
+   PORT (
+      clk                   : IN     std_logic ;
+      data_out              : OUT    std_logic_vector (63 DOWNTO 0);
+      addr_out              : OUT    std_logic_vector (11 DOWNTO 0);
+      write_ea              : OUT    std_logic_vector (0 DOWNTO 0) := "0";
+      ram_start_addr        : IN     std_logic_vector (11 DOWNTO 0);
+      ram_write_ea          : IN     std_logic ;
+      ram_write_ready       : OUT    std_logic                     := '0';
+      config_start_mm       : OUT    std_logic                     := '0';
+      config_start_cm       : OUT    std_logic                     := '0';
+      config_start_spi      : OUT    std_logic                     := '0';
+      config_ready_mm       : IN     std_logic ;
+      config_ready_cm       : IN     std_logic ;
+      config_ready_spi      : IN     std_logic ;
+      config_started_mm     : IN     std_logic ;
+      config_started_cm     : IN     std_logic ;
+      config_started_spi    : IN     std_logic ;
+      roi_array             : IN     roi_array_type ;
+      roi_max               : IN     roi_max_type ;
+      sensor_array          : IN     sensor_array_type ;
+      sensor_ready          : IN     std_logic ;
+      dac_array             : IN     dac_array_type ;
+      package_length        : IN     std_logic_vector (15 DOWNTO 0);
+      board_id              : IN     std_logic_vector (3 DOWNTO 0);
+      crate_id              : IN     std_logic_vector (1 DOWNTO 0);
+      trigger_id            : IN     std_logic_vector (47 DOWNTO 0);
+      trigger               : IN     std_logic ;
+      s_trigger             : IN     std_logic ;
+      new_config            : IN     std_logic ;
+      config_started        : OUT    std_logic                     := '0';
+      adc_data_array        : IN     adc_data_array_type ;
+      adc_oeb               : OUT    std_logic                     := '1';
+      adc_otr               : IN     std_logic_vector (3 DOWNTO 0);
+      drs_channel_id        : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
+      drs_dwrite            : OUT    std_logic                     := '1';
+      drs_clk_en            : OUT    std_logic                     := '0';
+      drs_read_s_cell       : OUT    std_logic                     := '0';
+      drs_read_s_cell_ready : IN     std_logic ;
+      drs_s_cell_array      : IN     drs_s_cell_array_type 
+   );
+   END COMPONENT;
+   COMPONENT drs_pulser_dummy
+   PORT (
+      CLK                      : IN     std_logic;
+      SROUT_in_0               : IN     std_logic;
+      SROUT_in_1               : IN     std_logic;
+      SROUT_in_2               : IN     std_logic;
+      SROUT_in_3               : IN     std_logic;
+      start_endless_mode       : IN     std_logic;
+      start_read_stop_pos_mode : IN     std_logic;
+      RSRLOAD                  : OUT    std_logic  := '0';
+      SRCLK                    : OUT    std_logic  := '0';
+      stop_pos                 : OUT    drs_s_cell_array_type;
+      stop_pos_valid           : OUT    std_logic  := '0'
+   );
+   END COMPONENT;
+   COMPONENT memory_manager
+   PORT (
+      clk                    : IN     std_logic ;
+      config_start           : IN     std_logic ;
+      ram_write_ready        : IN     std_logic ;
+      roi_array              : IN     roi_array_type ;
+      ram_write_ea           : OUT    std_logic                      := '0';
+      config_ready           : OUT    std_logic                      := '0';
+      config_started         : OUT    std_logic                      := '0';
+      roi_max                : OUT    roi_max_type                   := (others => conv_std_logic_vector (0, 11));
+      package_length         : OUT    std_logic_vector (15 DOWNTO 0) := (others => '0');
+      wiz_ram_start_addr     : OUT    std_logic_vector (13 DOWNTO 0) := (others => '0');
+      wiz_write_length       : OUT    std_logic_vector (16 DOWNTO 0) := (others => '0');
+      wiz_number_of_channels : OUT    std_logic_vector (3 DOWNTO 0)  := (others => '0');
+      wiz_write_ea           : OUT    std_logic                      := '0';
+      wiz_write_header       : OUT    std_logic                      := '0';
+      wiz_write_end          : OUT    std_logic                      := '0';
+      wiz_busy               : IN     std_logic ;
+      ram_start_addr         : OUT    std_logic_vector (11 DOWNTO 0) := (others => '0')
+   );
+   END COMPONENT;
+   COMPONENT spi_interface
+   PORT (
+      clk_50MHz      : IN     std_logic ;
+      config_start   : IN     std_logic ;
+      dac_array      : IN     dac_array_type ;
+      config_ready   : OUT    std_logic ;
+      config_started : OUT    std_logic  := '0';
+      dac_cs         : OUT    std_logic ;
+      mosi           : OUT    std_logic  := '0';
+      sclk           : OUT    std_logic ;
+      sensor_array   : OUT    sensor_array_type ;
+      sensor_cs      : OUT    std_logic_vector (3 DOWNTO 0);
+      sensor_ready   : OUT    std_logic ;
+      sio            : INOUT  std_logic 
+   );
+   END COMPONENT;
+   COMPONENT w5300_modul
+   PORT (
+      clk               : IN     std_logic ;
+      wiz_reset         : OUT    std_logic                      := '1';
+      addr              : OUT    std_logic_vector (9 DOWNTO 0);
+      data              : INOUT  std_logic_vector (15 DOWNTO 0);
+      cs                : OUT    std_logic                      := '1';
+      wr                : OUT    std_logic                      := '1';
+      led               : OUT    std_logic_vector (7 DOWNTO 0)  := (OTHERS => '0');
+      rd                : OUT    std_logic                      := '1';
+      int               : IN     std_logic ;
+      write_length      : IN     std_logic_vector (16 DOWNTO 0);
+      ram_start_addr    : IN     std_logic_vector (13 DOWNTO 0);
+      ram_data          : IN     std_logic_vector (15 DOWNTO 0);
+      ram_addr          : OUT    std_logic_vector (13 DOWNTO 0);
+      data_valid        : IN     std_logic ;
+      busy              : OUT    std_logic                      := '1';
+      write_header_flag : IN     std_logic ;
+      write_end_flag    : IN     std_logic ;
+      fifo_channels     : IN     std_logic_vector (3 DOWNTO 0);
+      s_trigger         : OUT    std_logic                      := '0';
+      new_config        : OUT    std_logic                      := '0';
+      config_started    : IN     std_logic ;
+      config_addr       : OUT    std_logic_vector (7 DOWNTO 0);
+      config_data       : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z');
+      config_wr_en      : OUT    std_logic                      := '0';
+      config_rd_en      : OUT    std_logic                      := '0';
+      config_busy       : IN     std_logic 
+   );
+   END COMPONENT;
+   COMPONENT trigger_counter
+   PORT (
+      trigger_id : OUT    std_logic_vector (47 DOWNTO 0);
+      trigger    : IN     std_logic ;
+      clk        : IN     std_logic 
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer;
+   FOR ALL : clock_generator USE ENTITY FACT_FAD_lib.clock_generator;
+   FOR ALL : control_unit USE ENTITY FACT_FAD_lib.control_unit;
+   FOR ALL : dataRAM_64bit_16bit USE ENTITY FACT_FAD_lib.dataRAM_64bit_16bit;
+   FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator;
+   FOR ALL : drs_pulser_dummy USE ENTITY FACT_FAD_lib.drs_pulser_dummy;
+   FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager;
+   FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface;
+   FOR ALL : trigger_counter USE ENTITY FACT_FAD_TB_lib.trigger_counter;
+   FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul;
+   -- pragma synthesis_on
+
+
+BEGIN
+
+   -- Instance port mappings.
+   U_3 : adc_buffer
+      PORT MAP (
+         clk_ps             => CLK_25_PS_internal,
+         adc_data_array     => adc_data_array,
+         adc_otr_array      => adc_otr_array,
+         adc_data_array_int => adc_data_array_int,
+         adc_otr            => adc_otr
+      );
+   U_0 : clock_generator
+      PORT MAP (
+         CLK       => CLK,
+         CLK_25    => CLK_25,
+         CLK_25_PS => CLK_25_PS_internal,
+         CLK_50    => CLK_50_internal
+      );
+   U_2 : control_unit
+      PORT MAP (
+         clk               => CLK_50_internal,
+         config_addr       => config_addr,
+         config_rd_en      => config_rd_en,
+         config_start      => config_start_cm,
+         config_wr_en      => config_wr_en,
+         config_busy       => config_busy,
+         config_data_valid => config_data_valid,
+         config_ready      => config_ready_cm,
+         config_started    => config_started_cu,
+         dac_array         => dac_array,
+         roi_array         => roi_array,
+         config_data       => config_data
+      );
+   I_main_dataRAM : dataRAM_64bit_16bit
+      PORT MAP (
+         clka  => CLK_25,
+         dina  => data_out,
+         addra => addr_out,
+         wea   => write_ea,
+         clkb  => CLK_50_internal,
+         addrb => ram_addr,
+         doutb => ram_data
+      );
+   I_main_data_generator : data_generator
+      PORT MAP (
+         clk                   => CLK_25,
+         data_out              => data_out,
+         addr_out              => addr_out,
+         write_ea              => write_ea,
+         ram_start_addr        => ram_start_addr,
+         ram_write_ea          => ram_write_ea,
+         ram_write_ready       => ram_write_ready,
+         config_start_mm       => config_start,
+         config_start_cm       => config_start_cm,
+         config_start_spi      => config_start_spi,
+         config_ready_mm       => config_ready,
+         config_ready_cm       => config_ready_cm,
+         config_ready_spi      => config_ready_spi,
+         config_started_mm     => config_started_mm,
+         config_started_cm     => config_started_cu,
+         config_started_spi    => config_started_spi,
+         roi_array             => roi_array,
+         roi_max               => roi_max,
+         sensor_array          => sensor_array,
+         sensor_ready          => sensor_ready,
+         dac_array             => dac_array,
+         package_length        => package_length,
+         board_id              => board_id,
+         crate_id              => crate_id,
+         trigger_id            => trigger_id,
+         trigger               => trigger,
+         s_trigger             => s_trigger,
+         new_config            => new_config,
+         config_started        => config_started,
+         adc_data_array        => adc_data_array_int,
+         adc_oeb               => adc_oeb,
+         adc_otr               => adc_otr,
+         drs_channel_id        => drs_channel_id,
+         drs_dwrite            => drs_dwrite,
+         drs_clk_en            => drs_clk_en,
+         drs_read_s_cell       => drs_read_s_cell,
+         drs_read_s_cell_ready => drs_read_s_cell_ready,
+         drs_s_cell_array      => drs_s_cell_array
+      );
+   U_1 : drs_pulser_dummy
+      PORT MAP (
+         CLK                      => CLK_25,
+         start_endless_mode       => drs_clk_en,
+         start_read_stop_pos_mode => drs_read_s_cell,
+         SROUT_in_0               => SROUT_in_0,
+         SROUT_in_1               => SROUT_in_1,
+         SROUT_in_2               => SROUT_in_2,
+         SROUT_in_3               => SROUT_in_3,
+         stop_pos                 => drs_s_cell_array,
+         stop_pos_valid           => drs_read_s_cell_ready,
+         RSRLOAD                  => RSRLOAD,
+         SRCLK                    => SRCLK
+      );
+   I_main_memory_manager : memory_manager
+      PORT MAP (
+         clk                    => CLK_25,
+         config_start           => config_start,
+         ram_write_ready        => ram_write_ready,
+         roi_array              => roi_array,
+         ram_write_ea           => ram_write_ea,
+         config_ready           => config_ready,
+         config_started         => config_started_mm,
+         roi_max                => roi_max,
+         package_length         => package_length,
+         wiz_ram_start_addr     => wiz_ram_start_addr,
+         wiz_write_length       => wiz_write_length,
+         wiz_number_of_channels => wiz_number_of_channels,
+         wiz_write_ea           => wiz_write_ea,
+         wiz_write_header       => wiz_write_header,
+         wiz_write_end          => wiz_write_end,
+         wiz_busy               => wiz_busy,
+         ram_start_addr         => ram_start_addr
+      );
+   U_4 : spi_interface
+      PORT MAP (
+         clk_50MHz      => CLK_50_internal,
+         config_start   => config_start_spi,
+         dac_array      => dac_array,
+         config_ready   => config_ready_spi,
+         config_started => config_started_spi,
+         dac_cs         => dac_cs,
+         mosi           => mosi,
+         sclk           => sclk,
+         sensor_array   => sensor_array,
+         sensor_cs      => sensor_cs,
+         sensor_ready   => sensor_ready,
+         sio            => sio
+      );
+   I_main_ethernet : w5300_modul
+      PORT MAP (
+         clk               => CLK_50_internal,
+         wiz_reset         => wiz_reset,
+         addr              => wiz_addr,
+         data              => wiz_data,
+         cs                => wiz_cs,
+         wr                => wiz_wr,
+         led               => led,
+         rd                => wiz_rd,
+         int               => wiz_int,
+         write_length      => wiz_write_length,
+         ram_start_addr    => wiz_ram_start_addr,
+         ram_data          => ram_data,
+         ram_addr          => ram_addr,
+         data_valid        => wiz_write_ea,
+         busy              => wiz_busy,
+         write_header_flag => wiz_write_header,
+         write_end_flag    => wiz_write_end,
+         fifo_channels     => wiz_number_of_channels,
+         s_trigger         => s_trigger,
+         new_config        => new_config,
+         config_started    => config_started,
+         config_addr       => config_addr,
+         config_data       => config_data,
+         config_wr_en      => config_wr_en,
+         config_rd_en      => config_rd_en,
+         config_busy       => config_busy
+      );
+   I_main_ext_trigger : trigger_counter
+      PORT MAP (
+         trigger_id => trigger_id,
+         trigger    => trigger,
+         clk        => CLK_50_internal
+      );
+
+   -- Implicit buffered output assignments
+   CLK_25_PS <= CLK_25_PS_internal;
+   CLK_50    <= CLK_50_internal;
+
+END struct;
Index: FPGA/FAD/FACT_FAD_lib/hdl/fad_testboard_struct.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/fad_testboard_struct.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/fad_testboard_struct.vhd	(revision 215)
@@ -0,0 +1,251 @@
+-- VHDL Entity FACT_FAD_lib.FAD_Testboard.symbol
+--
+-- Created:
+--          by - kai.UNKNOWN (E5PCXX)
+--          at - 11:34:39 18.05.2010
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FAD_Testboard IS
+   PORT( 
+      clk       : IN     STD_LOGIC;
+      trigger   : IN     STD_LOGIC;
+      wiz_int   : IN     std_logic;
+      CLK_25_PS : OUT    std_logic;
+      CLK_50    : OUT    std_logic;
+      RSRLOAD   : OUT    std_logic                     := '0';
+      SRCLK     : OUT    std_logic                     := '0';
+      led       : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
+      wiz_addr  : OUT    std_logic_vector (9 DOWNTO 0);
+      wiz_cs    : OUT    std_logic                     := '1';
+      wiz_rd    : OUT    std_logic                     := '1';
+      wiz_reset : OUT    std_logic                     := '1';
+      wiz_wr    : OUT    std_logic                     := '1';
+      wiz_data  : INOUT  std_logic_vector (15 DOWNTO 0)
+   );
+
+-- Declarations
+
+END FAD_Testboard ;
+
+--
+-- VHDL Architecture FACT_FAD_lib.FAD_Testboard.struct
+--
+-- Created:
+--          by - kai.UNKNOWN (E5PCXX)
+--          at - 11:34:39 18.05.2010
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE IEEE.NUMERIC_STD.all;
+
+LIBRARY FACT_FAD_lib;
+USE FACT_FAD_lib.fad_definitions.all;
+LIBRARY FACT_FAD_test_devices_lib;
+USE FACT_FAD_test_devices_lib.drs4_pack.all;
+USE ieee.std_logic_unsigned.all;
+
+LIBRARY FACT_FAD_lib;
+LIBRARY FACT_FAD_test_devices_lib;
+
+ARCHITECTURE struct OF FAD_Testboard IS
+
+   -- Architecture declarations
+
+   -- Internal signal declarations
+   SIGNAL SROUT_in_0     : std_logic;
+   SIGNAL SROUT_in_1     : std_logic;
+   SIGNAL SROUT_in_2     : std_logic;
+   SIGNAL SROUT_in_3     : std_logic;
+   SIGNAL adc_data       : STD_LOGIC_VECTOR(11 DOWNTO 0);
+   SIGNAL adc_data_array : adc_data_array_type;
+   SIGNAL adc_oeb        : STD_LOGIC;
+   SIGNAL adc_otr        : STD_LOGIC;
+   SIGNAL adc_otr_array  : std_logic_vector(3 DOWNTO 0);
+   SIGNAL board_id       : std_logic_vector(3 DOWNTO 0);
+   SIGNAL crate_id       : std_logic_vector(1 DOWNTO 0);
+   SIGNAL dac_cs         : std_logic;
+   SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0');
+   SIGNAL drs_dwrite     : std_logic                    := '1';
+   SIGNAL rst            : STD_LOGIC;
+   SIGNAL sclk           : std_logic;
+   SIGNAL sensor_cs      : std_logic_vector(3 DOWNTO 0);
+   SIGNAL sio            : std_logic;
+   SIGNAL trigger_int    : STD_LOGIC                    := '0';
+
+   -- Implicit buffer signal declarations
+   SIGNAL CLK_25_PS_internal : std_logic;
+
+
+   -- Component Declarations
+   COMPONENT FAD_main
+   PORT (
+      CLK            : IN     std_logic ;
+      SROUT_in_0     : IN     std_logic ;
+      SROUT_in_1     : IN     std_logic ;
+      SROUT_in_2     : IN     std_logic ;
+      SROUT_in_3     : IN     std_logic ;
+      adc_data_array : IN     adc_data_array_type ;
+      adc_otr_array  : IN     std_logic_vector (3 DOWNTO 0);
+      board_id       : IN     std_logic_vector (3 DOWNTO 0);
+      crate_id       : IN     std_logic_vector (1 DOWNTO 0);
+      trigger        : IN     std_logic ;
+      wiz_int        : IN     std_logic ;
+      CLK_25_PS      : OUT    std_logic ;
+      CLK_50         : OUT    std_logic ;
+      RSRLOAD        : OUT    std_logic                     := '0';
+      SRCLK          : OUT    std_logic                     := '0';
+      adc_oeb        : OUT    std_logic                     := '1';
+      dac_cs         : OUT    std_logic ;
+      drs_channel_id : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
+      drs_dwrite     : OUT    std_logic                     := '1';
+      led            : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
+      sclk           : OUT    std_logic ;
+      sensor_cs      : OUT    std_logic_vector (3 DOWNTO 0);
+      wiz_addr       : OUT    std_logic_vector (9 DOWNTO 0);
+      wiz_cs         : OUT    std_logic                     := '1';
+      wiz_rd         : OUT    std_logic                     := '1';
+      wiz_reset      : OUT    std_logic                     := '1';
+      wiz_wr         : OUT    std_logic                     := '1';
+      sio            : INOUT  std_logic ;
+      wiz_data       : INOUT  std_logic_vector (15 DOWNTO 0)
+   );
+   END COMPONENT;
+   COMPONENT FAD_adc_emulator
+   PORT (
+      adc_oeb  : IN     STD_LOGIC ;
+      clk      : IN     STD_LOGIC ;
+      rst      : IN     STD_LOGIC ;
+      adc_data : OUT    STD_LOGIC_VECTOR (11 DOWNTO 0);
+      adc_otr  : OUT    STD_LOGIC 
+   );
+   END COMPONENT;
+   COMPONENT debouncer
+   GENERIC (
+      WIDTH : INTEGER := 17
+   );
+   PORT (
+      clk         : IN     STD_LOGIC ;
+      --           rst : in  STD_LOGIC;
+      trigger_in  : IN     STD_LOGIC ;
+      trigger_out : OUT    STD_LOGIC  := '0'
+   );
+   END COMPONENT;
+   COMPONENT max6662_emulator
+   GENERIC (
+      DRS_TEMPERATURE : integer := 51
+   );
+   PORT (
+      sclk      : IN     std_logic;
+      sensor_cs : IN     std_logic_vector (3 DOWNTO 0);
+      sio       : INOUT  std_logic
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : FAD_adc_emulator USE ENTITY FACT_FAD_test_devices_lib.FAD_adc_emulator;
+   FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main;
+   FOR ALL : debouncer USE ENTITY FACT_FAD_test_devices_lib.debouncer;
+   FOR ALL : max6662_emulator USE ENTITY FACT_FAD_test_devices_lib.max6662_emulator;
+   -- pragma synthesis_on
+
+
+BEGIN
+   -- Architecture concurrent statements
+   -- HDL Embedded Text Block 1 eb_ID
+   -- hard-wired IDs
+   board_id <= "0101";
+   crate_id <= "01";
+
+   -- HDL Embedded Text Block 2 eb1
+   -- eb1 2           
+   adc_data_array (0) <= adc_data;
+   adc_data_array (1) <= adc_data;
+   adc_data_array (2) <= adc_data;
+   adc_data_array (3) <= adc_data;
+   adc_otr_array(0) <= adc_otr;
+   adc_otr_array(1) <= adc_otr;
+   adc_otr_array(2) <= adc_otr;
+   adc_otr_array(3) <= adc_otr;                            
+
+   -- HDL Embedded Text Block 3 eb2
+   -- eb2 3  
+   SROUT_in_0 <= '1';
+   SROUT_in_1 <= '0';
+   SROUT_in_2 <= '1';
+   SROUT_in_3 <= '0';
+                                         
+
+
+   -- Instance port mappings.
+   I_testboard_main : FAD_main
+      PORT MAP (
+         CLK            => clk,
+         SROUT_in_0     => SROUT_in_0,
+         SROUT_in_1     => SROUT_in_1,
+         SROUT_in_2     => SROUT_in_2,
+         SROUT_in_3     => SROUT_in_3,
+         adc_data_array => adc_data_array,
+         adc_otr_array  => adc_otr_array,
+         board_id       => board_id,
+         crate_id       => crate_id,
+         trigger        => trigger_int,
+         wiz_int        => wiz_int,
+         CLK_25_PS      => CLK_25_PS_internal,
+         CLK_50         => CLK_50,
+         RSRLOAD        => RSRLOAD,
+         SRCLK          => SRCLK,
+         adc_oeb        => adc_oeb,
+         dac_cs         => dac_cs,
+         drs_channel_id => drs_channel_id,
+         drs_dwrite     => drs_dwrite,
+         led            => led,
+         sclk           => sclk,
+         sensor_cs      => sensor_cs,
+         wiz_addr       => wiz_addr,
+         wiz_cs         => wiz_cs,
+         wiz_rd         => wiz_rd,
+         wiz_reset      => wiz_reset,
+         wiz_wr         => wiz_wr,
+         sio            => sio,
+         wiz_data       => wiz_data
+      );
+   I_testboard_adc : FAD_adc_emulator
+      PORT MAP (
+         adc_oeb  => adc_oeb,
+         clk      => CLK_25_PS_internal,
+         rst      => rst,
+         adc_data => adc_data,
+         adc_otr  => adc_otr
+      );
+   I_testboard_debouncer : debouncer
+      GENERIC MAP (
+         WIDTH => 12
+      )
+      PORT MAP (
+         clk         => CLK_25_PS_internal,
+         trigger_in  => trigger,
+         trigger_out => trigger_int
+      );
+   I0 : max6662_emulator
+      GENERIC MAP (
+         DRS_TEMPERATURE => 51
+      )
+      PORT MAP (
+         sclk      => sclk,
+         sio       => sio,
+         sensor_cs => sensor_cs
+      );
+
+   -- Implicit buffered output assignments
+   CLK_25_PS <= CLK_25_PS_internal;
+
+END struct;
Index: FPGA/FAD/FACT_FAD_lib/hdl/memory_manager_beha.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/memory_manager_beha.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/memory_manager_beha.vhd	(revision 215)
@@ -0,0 +1,267 @@
+--
+-- VHDL Architecture FACT_FAD_lib.memory_manager.beha
+--
+-- Created:
+--          by - kai.UNKNOWN (E5PCXX)
+--          at - 14:33:25 02.03.2010
+--
+-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use ieee.STD_LOGIC_UNSIGNED.all;
+
+library FACT_FAD_lib;
+use FACT_FAD_lib.fad_definitions.all;
+
+-- library UNISIM;
+-- use UNISIM.VComponents.all;
+-- USE IEEE.NUMERIC_STD.all;
+
+ENTITY memory_manager IS
+   PORT( 
+      clk : IN std_logic;
+      config_start : IN std_logic;
+      ram_write_ready : IN std_logic;
+      roi_array : IN roi_array_type;
+      ram_write_ea : OUT std_logic := '0';
+      config_ready, config_started : OUT std_logic := '0';
+      roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11));
+      package_length : OUT std_logic_vector (15 downto 0) := (others => '0');
+      wiz_ram_start_addr : OUT std_logic_vector (13 downto 0) := (others => '0');
+      wiz_write_length : OUT std_logic_vector (16 downto 0) := (others => '0');
+      wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0');
+      wiz_write_ea : OUT std_logic := '0';
+      wiz_write_header : OUT std_logic := '0';
+      wiz_write_end : OUT std_logic := '0';
+      wiz_busy : IN std_logic;
+      ram_start_addr : OUT std_logic_vector (11 DOWNTO 0) := (others => '0')
+   );
+
+-- Declarations
+
+END memory_manager ;
+
+--
+ARCHITECTURE beha OF memory_manager IS
+
+type state_mm_type is (MM_CONFIG, MAX_ROI, MAX_ROI1, MAX_ROI2, FIFO_CALC, RAM_CALC, RAM_CALC1, RAM_CALC2, MM_MAIN, MM_MAIN1);
+signal state_mm : state_mm_type := MM_CONFIG;
+
+--type roi_array_type is array (0 to 35) of integer range 0 to 1024;
+type roi_max_array_type is array (0 to 8) of integer range 0 to 1024;
+type channel_size_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE;
+type fifo_write_length_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE;
+type fifo_channels_array_type is array (0 to 8) of integer range 0 to 9;
+type fifo_package_size_ram_type is array (0 to 8) of integer range 0 to RAM_SIZE_16B;
+
+signal roi_max_array : roi_max_array_type := (others => 0);
+
+-- size of channel groups (16 bit)
+signal channel_size : channel_size_type := (others => 0);
+-- write length of packages (16 bit)
+signal fifo_write_length : fifo_write_length_type := (others => 0);
+-- number of channels per package
+signal fifo_channels_array : fifo_channels_array_type := (others => 0);
+-- size of packages in ram (16 bit)
+signal fifo_package_size_ram : fifo_package_size_ram_type := (others => 0);
+--
+signal event_size_ram : integer range 0 to RAM_SIZE_16B := 0;
+signal event_size_ram_64b : integer range 0 to RAM_SIZE_64B := 0;
+signal event_size : integer range 0 to RAM_SIZE_16B := 0;
+
+signal drs_id : integer range 0 to 4 := 0;
+signal channel_id : integer range 0 to 9 := 0;
+signal channel_index : integer range 0 to 9 := 0;
+signal package_index : integer range 0 to 9 := 0;
+signal number_of_packages : integer range 0 to 9 := 0;
+signal max_events_ram, events_in_ram : integer range 0 to 2048;
+signal event_start_addr : integer range 0 to (RAM_SIZE_64B - 1);
+signal write_start_addr : integer range 0 to (RAM_SIZE_16B - 1);
+signal event_ready_flag : std_logic := '0';
+
+signal roi_index : integer range 0 to 45 := 0;
+signal temp_roi : integer range 0 to 1024 := 0;
+
+BEGIN
+  
+  mm : process (clk)
+  begin
+    if rising_edge (clk) then
+      case state_mm is
+    
+        when MM_CONFIG =>
+          if (config_start = '1') then
+            config_started <= '1';
+            roi_max_array <= (others => 0);
+            channel_size <= (others => 0);
+            fifo_write_length <= (others => 0);
+            fifo_channels_array <= (others => 0);
+            event_size <= 0;
+            ram_write_ea <= '0';
+            state_mm <= MAX_ROI;
+          end if;
+        
+        -- calculate max ROIs and channel sizes
+        when MAX_ROI =>
+          roi_index <= (drs_id * 9) + channel_id;
+          state_mm <= MAX_ROI1;
+        when MAX_ROI1 =>
+          temp_roi <= roi_array (roi_index);
+          state_mm <= MAX_ROI2;
+        when MAX_ROI2 =>
+          if (channel_id < 9) then
+            if ( temp_roi > roi_max_array (channel_id)) then
+              roi_max_array (channel_id) <= temp_roi;
+            end if;
+            channel_size (channel_id) <= channel_size (channel_id) + temp_roi + 3;
+            drs_id <= drs_id + 1;
+            state_mm <= MAX_ROI;
+            if (drs_id = 3) then
+              drs_id <= 0;
+              channel_id <= channel_id + 1;
+            end if;
+          else
+            drs_id <= 0;
+            channel_id <= 0;
+            channel_size (0) <= channel_size (0) + PACKAGE_HEADER_LENGTH;
+            channel_size (8) <= channel_size (8) + PACKAGE_END_LENGTH;
+            state_mm <= FIFO_CALC;
+          end if;
+        
+        -- calculate number of channels that fit in FIFO
+        when FIFO_CALC =>
+          if (channel_id < 9) then
+            if ((fifo_write_length (package_index) + channel_size (channel_id)) <= W5300_TX_FIFO_SIZE) then
+              fifo_write_length (package_index) <= fifo_write_length (package_index) + channel_size (channel_id);
+              fifo_channels_array (package_index) <= fifo_channels_array (package_index) + 1;
+              channel_id <= channel_id + 1;
+              event_size <= event_size + channel_size (channel_id);
+            else
+              package_index <= package_index + 1;
+            end if;
+          else
+            number_of_packages <= package_index + 1;
+            package_index <= 0;
+            channel_index <= 0;
+            channel_id <= 0;
+            fifo_package_size_ram <= (others => 0);
+            fifo_package_size_ram (0) <= PACKAGE_HEADER_LENGTH + 6; 
+            event_size_ram <= 0;
+            event_size_ram_64b <= 0;
+            max_events_ram <= 0;           
+            state_mm <= RAM_CALC;
+          end if;
+          
+        when RAM_CALC =>
+          if (package_index < number_of_packages) then
+            if (channel_index < fifo_channels_array (package_index)) then
+              fifo_package_size_ram (package_index) <= fifo_package_size_ram (package_index) + ((roi_max_array (channel_id) + 3) * 4);
+              channel_index <= channel_index + 1;
+              channel_id <= channel_id + 1;
+            else
+              package_index <= package_index + 1;
+              event_size_ram <= event_size_ram + fifo_package_size_ram (package_index);
+              channel_index <= 0;
+            end if;
+          else
+            fifo_package_size_ram (package_index - 1) <= fifo_package_size_ram (package_index - 1) + 4;
+            event_size_ram <= event_size_ram + 4; -- Size of Event in RAM (16 Bit), + CRC + Endflag + 2 Spare               
+            state_mm <= RAM_CALC1;
+          end if;
+        when RAM_CALC1 =>
+          max_events_ram <= max_events_ram + 1;
+          if ((max_events_ram * event_size_ram) <= RAM_SIZE_16B) then
+            state_mm <= RAM_CALC1;
+          else
+            max_events_ram <= max_events_ram - 1;
+            state_mm <= RAM_CALC2;
+          end if;
+        when RAM_CALC2 =>
+          event_size_ram_64b <= (event_size_ram / 4);
+          events_in_ram <= 0;
+          event_start_addr <= 0;
+          write_start_addr <= 0;
+          package_index <= 0;
+          channel_id <= 0;
+          ram_start_addr <= (others => '0');
+          ram_write_ea <= '1';
+          config_started <= '0';
+          config_ready <= '1';
+          package_length <= conv_std_logic_vector (event_size, 16);
+          for i in 0 to 8 loop
+            roi_max(i) <= conv_std_logic_vector(roi_max_array(i), 11);
+          end loop;
+          state_mm <= MM_MAIN;
+          
+        when MM_MAIN =>
+          state_mm <= MM_MAIN1;
+          if ((ram_write_ready = '1') and (event_ready_flag = '0')) then
+            ram_write_ea <= '0';
+            events_in_ram <= events_in_ram + 1;
+            if ((event_start_addr + event_size_ram_64b) < (RAM_SIZE_64B - event_size_ram_64b)) then
+              event_start_addr <= event_start_addr + event_size_ram_64b;
+            else
+              event_start_addr <= 0;
+            end if;
+            event_ready_flag <= '1';
+          end if;
+          wiz_write_ea <= '0'; -- ?????
+    
+        when MM_MAIN1 =>
+          state_mm <= MM_MAIN;
+          if (config_start = '1') then
+            config_ready <= '0';
+            if (events_in_ram = 0) then
+              state_mm <= MM_CONFIG;
+            end if;
+          end if;
+          if (event_ready_flag = '1') then
+            if (events_in_ram < max_events_ram) then
+              ram_write_ea <= '1';
+              ram_start_addr <= conv_std_logic_vector(event_start_addr, 12);
+              event_ready_flag <= '0';
+            end if;
+          end if;
+          if ((events_in_ram > 0) and (wiz_busy = '0')) then
+            if (package_index < number_of_packages) then
+              wiz_ram_start_addr <= conv_std_logic_vector(write_start_addr, 14);
+              wiz_write_length <= conv_std_logic_vector(fifo_write_length (package_index), 17);
+              wiz_number_of_channels <= conv_std_logic_vector(fifo_channels_array (package_index), 4);
+              wiz_write_ea <= '1';
+              package_index <= package_index + 1;
+              if (package_index = 0) then
+                -- first package -> write header
+                wiz_write_header <= '1';
+              else
+                wiz_write_header <= '0';
+              end if;
+              if (package_index = (number_of_packages - 1)) then
+                -- last package -> write end-flag
+                wiz_write_end <= '1';
+                -- next address 
+                if ((write_start_addr + event_size_ram) < (RAM_SIZE_16B - event_size_ram)) then
+                  write_start_addr <= write_start_addr + event_size_ram;
+                else
+                  write_start_addr <= 0;
+                end if;
+              else
+                write_start_addr <= write_start_addr + fifo_package_size_ram (package_index);
+                wiz_write_end <= '0';
+              end if;
+            else
+              events_in_ram <= events_in_ram - 1;
+              package_index <= 0;
+            end if;
+        end if;
+        
+          
+      end case; -- state_mm
+    end if;
+  end process mm; 
+  
+   
+  
+END ARCHITECTURE beha;
+
Index: FPGA/FAD/FACT_FAD_lib/hdl/spi_clock_gen_beha.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/spi_clock_gen_beha.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/spi_clock_gen_beha.vhd	(revision 215)
@@ -0,0 +1,47 @@
+--
+-- VHDL Architecture FACT_FAD_lib.spi_clock_generator.beha
+--
+-- Created:
+--          by - Benjamin Krumm.UNKNOWN (EEPC8)
+--          at - 14:49:19 01.04.2010
+--
+-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY spi_clock_generator IS
+   GENERIC( 
+      CLK_DIVIDER : integer := 25   --2 MHz @ 50 MHz
+   );
+   PORT( 
+      clk  : IN     std_logic;
+      sclk : OUT    std_logic  := '0'
+   );
+END spi_clock_generator ;
+
+ARCHITECTURE beha OF spi_clock_generator IS
+  
+BEGIN
+  
+  spi_clk_proc: process (clk)
+    variable Z: integer range 0 to clk_divider - 1;
+  begin
+    if rising_edge(clk) then
+      if (Z < clk_divider - 1) then 
+        Z := Z + 1;
+      else 
+        Z := 0;
+      end if;
+      if (Z = 0) then 
+        sclk <= '1';
+      end if;
+      if (Z = clk_divider / 2) then 
+        sclk <= '0';
+      end if;
+    end if;
+  end process spi_clk_proc;
+
+END ARCHITECTURE beha;
Index: FPGA/FAD/FACT_FAD_lib/hdl/spi_controller_beha.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/spi_controller_beha.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/spi_controller_beha.vhd	(revision 215)
@@ -0,0 +1,117 @@
+--
+-- VHDL Architecture FACT_FAD_lib.spi_controller.beha
+--
+-- Created:
+--          by - Benjamin Krumm.UNKNOWN (EEPC8)
+--          at - 10:37:20 12.04.2010
+--
+-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY spi_controller IS
+   PORT( 
+      clk          : IN     std_logic;
+      sio          : INOUT  std_logic := 'Z';
+      mosi         : OUT    std_logic := '0';
+      dac_id       : IN     std_logic_vector (2 DOWNTO 0);
+      sensor_id    : IN     std_logic_vector (1 downto 0);
+      data         : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z');
+      dac_cs       : OUT    std_logic := '1';
+      sensor_cs    : OUT    std_logic_vector (3 DOWNTO 0) := (others => '1');
+      dac_start    : IN     std_logic;
+      dac_ready    : OUT    std_logic := '0';
+      sensor_start : IN     std_logic;
+      sensor_valid : OUT    std_logic := '0'
+   );
+END spi_controller ;
+
+ARCHITECTURE beha OF spi_controller IS
+  
+  type TYPE_SPI_STATE is (SPI_IDLE, SPI_LOAD_DAC, SPI_LOAD_COMMAND, SPI_GET_TEMP);
+   
+  signal spi_state     : TYPE_SPI_STATE := SPI_IDLE;
+  signal spi_cycle_cnt : integer range 0 to 25 := 0;
+  signal shift_reg     : std_logic_vector (23 downto 0) := (others => '0');
+  signal data_reg      : std_logic_vector (15 downto 0) := (others => '0');
+  
+BEGIN
+  
+  spi_write_proc: process (clk)
+  begin
+    if falling_edge(clk) then
+      dac_cs <= '1';
+      sensor_cs <= (others => '1');
+      sio <= 'Z';
+      mosi <= '0';
+      data <= (others => 'Z');
+      case spi_state is
+        when SPI_IDLE =>
+          if (dac_start = '1') then
+            dac_ready <= '0';
+            spi_state <= SPI_LOAD_COMMAND; 
+          elsif (sensor_start = '1') then
+            sensor_valid <= '0';
+            spi_state <= SPI_LOAD_COMMAND;
+          end if;
+          
+        when SPI_LOAD_COMMAND =>
+          spi_cycle_cnt <= 0;
+            if (sensor_start = '1') then
+              shift_reg <= X"C1" & X"0000";   -- command: Temperature register read
+              spi_state <= SPI_GET_TEMP;
+            elsif (dac_start = '1') then
+              shift_reg <= "0011" & '0' & dac_id & data;
+              spi_state <= SPI_LOAD_DAC;
+            end if;
+        
+        -- start temperature sensor read  
+        when SPI_GET_TEMP =>
+          if (spi_cycle_cnt < 24) then -- must be on more cause MAX6662 provides data on falling edge
+            sensor_cs(conv_integer(sensor_id)) <= '0';
+            sensor_valid <= '0';
+            spi_cycle_cnt <= spi_cycle_cnt + 1;
+            if (spi_cycle_cnt < 9) then -- send data
+              sio <= shift_reg(23);
+              shift_reg <= shift_reg(22 downto 0) & shift_reg(23);
+            end if;
+          else
+            data <= data_reg;             
+            sensor_valid <= '1';
+            spi_state <= SPI_IDLE;
+          end if;
+        
+        -- start loading DACs 
+       when SPI_LOAD_DAC => 
+          dac_cs <= '0';
+          if (spi_cycle_cnt < 24) then
+            mosi <= shift_reg(23);
+            shift_reg <= shift_reg(22 downto 0) & shift_reg(23);
+            dac_ready <= '0';
+            spi_cycle_cnt <= spi_cycle_cnt + 1;
+            spi_state <= SPI_LOAD_DAC;
+          else
+            dac_cs <= '1';
+            dac_ready <= '1';
+            spi_state <= SPI_IDLE;
+          end if;
+      end case;
+    end if;
+  end process spi_write_proc;
+  
+  -- MAX6662 input must be read with rising edge
+  spi_read_proc: process (clk) 
+  begin
+    if rising_edge(clk) then
+      if (spi_state = SPI_GET_TEMP and spi_cycle_cnt >= 9) then
+        data_reg(0) <= sio;
+        data_reg(15 downto 1) <= data_reg(14 downto 0);
+      end if;
+    end if;
+  end process spi_read_proc; 
+    
+END ARCHITECTURE beha;
+
Index: FPGA/FAD/FACT_FAD_lib/hdl/spi_distributor_beha.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/spi_distributor_beha.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/spi_distributor_beha.vhd	(revision 215)
@@ -0,0 +1,144 @@
+--
+-- VHDL Architecture FACT_FAD_lib.spi_distributor.beha
+--
+-- Created:
+--          by - Benjamin Krumm.UNKNOWN (EEPC8)
+--          at - 09:24:21 23.04.2010
+--
+-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+LIBRARY FACT_FAD_lib;
+USE FACT_FAD_lib.fad_definitions.all;
+
+ENTITY spi_distributor IS
+  GENERIC(
+    CLK_DIVIDER : integer := 10**6
+  );
+  PORT(
+    clk               : IN 			std_logic;
+    config_start      : IN 			std_logic;
+    config_ready, config_started      : OUT   std_logic := '0'; 
+    sensor_valid      : OUT 		std_logic := '0';
+    dac_array         : IN 			dac_array_type;
+    sensor_array      : OUT 		sensor_array_type; 
+    dac_config_start  : OUT   std_logic := '0';
+    dac_config_ready  : IN    std_logic;
+    sensor_read_start : OUT   std_logic := '0';
+    sensor_read_valid : IN    std_logic;
+    dac_id            : OUT   std_logic_vector(2 downto 0) := (others => '0');
+    sensor_id         : OUT   std_logic_vector(1 downto 0) := (others => '0');
+    data              : INOUT std_logic_vector(15 downto 0) := (others => 'Z')
+  );
+END ENTITY spi_distributor;
+
+ARCHITECTURE beha OF spi_distributor IS
+
+  type TYPE_SPI_DISTRIBUTION_STATE is (INIT, IDLE, READ_SENSOR, CONFIG_DAC);
+    
+  signal spi_distr_state       : TYPE_SPI_DISTRIBUTION_STATE := INIT;
+  signal int_sensor_read_start : std_logic := '0';
+  signal int_sensor_valid      : std_logic := '0';
+  signal int_sensor_array      : sensor_array_type;
+  signal sensor_id_cnt         : integer range 0 to 4 := 0;
+  signal dac_id_cnt            : integer range 0 to 7 := 0;
+  
+  
+BEGIN
+  
+  spi_distribute_proc: process (clk)
+  begin
+    
+    if rising_edge(clk) then
+      data <= (others => 'Z');
+      case spi_distr_state is
+        when INIT =>
+          data <= (others => 'Z');
+          int_sensor_valid <= '0';
+          spi_distr_state <= READ_SENSOR;
+        when IDLE =>
+          if (int_sensor_valid = '1') then
+            sensor_array <= int_sensor_array;
+            sensor_valid <= '1';
+          end if;
+          data <= (others => 'Z');
+         -- start DAC configuration
+          if (config_start = '1' AND int_sensor_valid = '1') then
+            config_started <= '1';
+            config_ready <= '0';
+            dac_config_start <= '1';
+            dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length);
+            data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length);
+            spi_distr_state <= CONFIG_DAC;
+          -- start temperature sensor reading
+          elsif (dac_config_ready <= '1' AND int_sensor_read_start = '1') then
+            int_sensor_valid <= '0';
+            sensor_read_start <= '1';
+            sensor_id <= conv_std_logic_vector(sensor_id_cnt, sensor_id'length);
+            spi_distr_state <= READ_SENSOR;
+          end if;
+       
+        -- sensor reading   
+        when READ_SENSOR =>
+          sensor_read_start <= '1';
+          sensor_id <= conv_std_logic_vector(sensor_id_cnt, sensor_id'length);
+          if (sensor_read_valid = '1') then
+            int_sensor_array(sensor_id_cnt) <= conv_integer(data);
+            sensor_read_start <= '0';
+            if (sensor_id_cnt < 3) then
+              sensor_id_cnt <= sensor_id_cnt + 1;
+              sensor_read_start <= '1';
+              spi_distr_state <= READ_SENSOR;
+            else
+              sensor_id_cnt <= 0;
+              sensor_valid <= '0';
+              int_sensor_valid <= '1';
+              spi_distr_state <= IDLE;
+            end if;
+          end if;
+          
+        -- DAC configuration
+        when CONFIG_DAC =>
+          dac_config_start <= '1';
+          dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length);
+          data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length);
+          if (dac_config_ready = '1') then
+            dac_config_start <= '0';
+            if (dac_id_cnt < 7) then 
+              dac_id_cnt <= dac_id_cnt + 1;
+              dac_config_start <= '1';
+              spi_distr_state <= CONFIG_DAC;
+            else
+              dac_id_cnt <= 0;
+              config_started <= '0';
+              config_ready <= '1';
+              spi_distr_state <= IDLE;
+            end if;
+          end if; 
+      end case;  
+    end if;
+    
+  end process spi_distribute_proc;
+
+  sensor_tmr_proc: process (clk)
+    variable Z: integer range 0 to (CLK_DIVIDER - 1);
+  begin
+    if rising_edge(clk) then
+      int_sensor_read_start <= '0';
+      if (Z < CLK_DIVIDER - 1) then 
+        Z := Z + 1;
+      else 
+        Z := 0;
+      end if;
+      if (Z = 0) then 
+        int_sensor_read_start <= '1';
+      end if;
+    end if;
+  end process sensor_tmr_proc;
+  
+  
+END ARCHITECTURE beha;
+
Index: FPGA/FAD/FACT_FAD_lib/hdl/spi_interface_struct.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/spi_interface_struct.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/spi_interface_struct.vhd	(revision 215)
@@ -0,0 +1,176 @@
+-- VHDL Entity FACT_FAD_lib.spi_interface.symbol
+--
+-- Created:
+--          by - kai.UNKNOWN (E5PCXX)
+--          at - 14:16:38 19.05.2010
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+LIBRARY FACT_FAD_lib;
+USE FACT_FAD_lib.fad_definitions.all;
+
+ENTITY spi_interface IS
+   PORT( 
+      clk_50MHz      : IN     std_logic;
+      config_start   : IN     std_logic;
+      dac_array      : IN     dac_array_type;
+      config_ready   : OUT    std_logic;
+      config_started : OUT    std_logic  := '0';
+      dac_cs         : OUT    std_logic;
+      mosi           : OUT    std_logic  := '0';
+      sclk           : OUT    std_logic;
+      sensor_array   : OUT    sensor_array_type;
+      sensor_cs      : OUT    std_logic_vector (3 DOWNTO 0);
+      sensor_ready   : OUT    std_logic;
+      sio            : INOUT  std_logic
+   );
+
+-- Declarations
+
+END spi_interface ;
+
+--
+-- VHDL Architecture FACT_FAD_lib.spi_interface.struct
+--
+-- Created:
+--          by - kai.UNKNOWN (E5PCXX)
+--          at - 14:16:38 19.05.2010
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+LIBRARY FACT_FAD_lib;
+USE FACT_FAD_lib.fad_definitions.all;
+
+LIBRARY FACT_FAD_lib;
+
+ARCHITECTURE struct OF spi_interface IS
+
+   -- Architecture declarations
+
+   -- Internal signal declarations
+   SIGNAL dac_config_ready : std_logic;
+   SIGNAL dac_config_start : std_logic;
+   SIGNAL dac_id           : std_logic_vector(2 DOWNTO 0);
+   SIGNAL data             : std_logic_vector(15 DOWNTO 0);
+   SIGNAL sensor_id        : std_logic_vector(1 DOWNTO 0);
+   SIGNAL sensor_start     : std_logic;
+   SIGNAL sensor_valid     : std_logic;
+
+   -- Implicit buffer signal declarations
+   SIGNAL sclk_internal : std_logic;
+
+
+   -- Component Declarations
+   COMPONENT spi_clock_generator
+   GENERIC (
+      CLK_DIVIDER : integer := 25      --2 MHz @ 50 MHz
+   );
+   PORT (
+      clk  : IN     std_logic;
+      sclk : OUT    std_logic  := '0'
+   );
+   END COMPONENT;
+   COMPONENT spi_controller
+   PORT (
+      clk          : IN     std_logic;
+      dac_id       : IN     std_logic_vector (2 DOWNTO 0);
+      dac_start    : IN     std_logic;
+      sensor_id    : IN     std_logic_vector (1 DOWNTO 0);
+      sensor_start : IN     std_logic;
+      dac_cs       : OUT    std_logic                      := '1';
+      dac_ready    : OUT    std_logic                      := '0';
+      mosi         : OUT    std_logic                      := '0';
+      sensor_cs    : OUT    std_logic_vector (3 DOWNTO 0)  := (others => '1');
+      sensor_valid : OUT    std_logic                      := '0';
+      data         : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z');
+      sio          : INOUT  std_logic                      := 'Z'
+   );
+   END COMPONENT;
+   COMPONENT spi_distributor
+   GENERIC (
+      CLK_DIVIDER : integer := 10**6
+   );
+   PORT (
+      clk               : IN     std_logic;
+      config_start      : IN     std_logic;
+      dac_array         : IN     dac_array_type;
+      dac_config_ready  : IN     std_logic;
+      sensor_read_valid : IN     std_logic;
+      config_ready      : OUT    std_logic                      := '0';
+      config_started    : OUT    std_logic                      := '0';
+      dac_config_start  : OUT    std_logic                      := '0';
+      dac_id            : OUT    std_logic_vector (2 DOWNTO 0)  := (others => '0');
+      sensor_array      : OUT    sensor_array_type;
+      sensor_id         : OUT    std_logic_vector (1 DOWNTO 0)  := (others => '0');
+      sensor_read_start : OUT    std_logic                      := '0';
+      sensor_valid      : OUT    std_logic                      := '0';
+      data              : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z')
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : spi_clock_generator USE ENTITY FACT_FAD_lib.spi_clock_generator;
+   FOR ALL : spi_controller USE ENTITY FACT_FAD_lib.spi_controller;
+   FOR ALL : spi_distributor USE ENTITY FACT_FAD_lib.spi_distributor;
+   -- pragma synthesis_on
+
+
+BEGIN
+
+   -- Instance port mappings.
+   I_spi_clkgen : spi_clock_generator
+      GENERIC MAP (
+         CLK_DIVIDER => 25         --2 MHz @ 50 MHz
+      )
+      PORT MAP (
+         clk  => clk_50MHz,
+         sclk => sclk_internal
+      );
+   I_spi_controller : spi_controller
+      PORT MAP (
+         clk          => sclk_internal,
+         sio          => sio,
+         mosi         => mosi,
+         dac_id       => dac_id,
+         sensor_id    => sensor_id,
+         data         => data,
+         dac_cs       => dac_cs,
+         sensor_cs    => sensor_cs,
+         dac_start    => dac_config_start,
+         dac_ready    => dac_config_ready,
+         sensor_start => sensor_start,
+         sensor_valid => sensor_valid
+      );
+   I_spi_distributor : spi_distributor
+      GENERIC MAP (
+         CLK_DIVIDER => 4*10**3
+      )
+      PORT MAP (
+         clk               => sclk_internal,
+         config_start      => config_start,
+         config_ready      => config_ready,
+         config_started    => config_started,
+         sensor_valid      => sensor_ready,
+         dac_array         => dac_array,
+         sensor_array      => sensor_array,
+         dac_config_start  => dac_config_start,
+         dac_config_ready  => dac_config_ready,
+         sensor_read_start => sensor_start,
+         sensor_read_valid => sensor_valid,
+         dac_id            => dac_id,
+         sensor_id         => sensor_id,
+         data              => data
+      );
+
+   -- Implicit buffered output assignments
+   sclk <= sclk_internal;
+
+END struct;
Index: FPGA/FAD/FACT_FAD_lib/hdl/w5300_modul.vhd
===================================================================
--- FPGA/FAD/FACT_FAD_lib/hdl/w5300_modul.vhd	(revision 215)
+++ FPGA/FAD/FACT_FAD_lib/hdl/w5300_modul.vhd	(revision 215)
@@ -0,0 +1,777 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    11:48:48 11/10/2009 
+-- Design Name: 
+-- Module Name:    w5300_modul - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library FACT_FAD_lib;
+use FACT_FAD_lib.fad_definitions.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+ENTITY w5300_modul IS
+   PORT( 
+      clk            : IN     std_logic;
+      wiz_reset      : OUT    std_logic                     := '1';
+      addr           : OUT    std_logic_vector (9 DOWNTO 0);
+      data           : INOUT  std_logic_vector (15 DOWNTO 0);
+      cs             : OUT    std_logic                     := '1';
+      wr             : OUT    std_logic                     := '1';
+      led            : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
+      rd             : OUT    std_logic                     := '1';
+      int            : IN     std_logic;
+      write_length   : IN     std_logic_vector (16 DOWNTO 0);
+      ram_start_addr : IN     std_logic_vector (13 DOWNTO 0);
+      ram_data       : IN     std_logic_vector (15 DOWNTO 0);
+      ram_addr       : OUT    std_logic_vector (13 DOWNTO 0);
+      data_valid     : IN     std_logic;
+      busy           : OUT    std_logic                     := '1';
+      write_header_flag, write_end_flag : IN std_logic;
+      fifo_channels : IN std_logic_vector (3 downto 0);
+      s_trigger : OUT std_logic := '0';
+      new_config : OUT std_logic := '0';
+      config_started : in std_logic;
+      config_addr : out std_logic_vector (7 downto 0);
+      config_data : inout std_logic_vector (15 downto 0) := (others => 'Z');
+      config_wr_en : out std_logic := '0';
+      config_rd_en : out std_logic := '0';
+      config_busy : in std_logic
+   );
+
+-- Declarations
+
+END w5300_modul ;
+
+architecture Behavioral of w5300_modul is
+
+type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
+                         INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1,
+                         SI, SI1, SI2, SI3, SI4, SI5, SI6,	ESTABLISH, EST1, CONFIG, MAIN, CHK_RECEIVED, READ_DATA);
+type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
+                          WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3); 
+type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
+type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
+type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END);
+
+signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
+
+signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0');
+signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0');
+signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0');
+signal adc_data_addr : std_logic_vector (13 DOWNTO 0);
+
+signal state_init, next_state , next_state_tmp : state_init_type := RESET;
+signal count : std_logic_vector (2 downto 0) := "000";
+signal state_write : state_write_type := WR_START;
+signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
+signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
+signal state_read_data : state_read_data_type := RD_1;
+
+signal interrupt_ignore : std_logic := '1';
+signal int_flag : std_logic := '0';
+signal ram_access : std_logic := '0';
+
+signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0');
+signal data_cnt : integer := 0;
+signal drs_cnt : integer :=0;
+signal channel_cnt : integer range 0 to 9 :=0;
+signal socket_cnt : std_logic_vector (2 downto 0) := "000";
+signal roi_max : std_logic_vector (10 downto 0);
+signal data_end : integer := 0;
+
+signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
+signal write_length_bytes : std_logic_vector (16 downto 0);
+
+signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
+signal chk_recv_cntr : integer range 0 to 10000 := 0;
+signal rx_packets_cnt : std_logic_vector (15 downto 0);
+signal next_packet_data : std_logic := '0';
+signal new_config_flag : std_logic := '0';
+
+signal trigger_stop : std_logic := '1';
+
+signal local_write_length   : std_logic_vector (16 DOWNTO 0);
+signal local_ram_start_addr : std_logic_vector (13 DOWNTO 0);
+signal local_ram_addr       : std_logic_vector (13 downto 0);
+signal local_socket_nr      : std_logic_vector (2 DOWNTO 0);
+signal local_write_header_flag, local_write_end_flag : std_logic;
+signal local_fifo_channels : std_logic_vector (3 downto 0);
+
+begin
+
+  --synthesis translate_off
+  RST_TIME <= X"00120";
+  --synthesis translate_on
+
+	w5300_init_proc : process (clk, int)
+	begin
+		
+		if rising_edge (clk) then
+
+			-- Interrupt low
+			if (int = '0') and (interrupt_ignore = '0') then
+				case state_interrupt_1 is
+					when IR1_01 =>
+						int_flag <= '1';
+						busy <= '1';
+						state_interrupt_1 <= IR1_02;
+					when IR1_02 =>
+						state_interrupt_1 <= IR1_03;
+					when IR1_03 =>
+						state_init <= INTERRUPT;
+						socket_cnt <= "000";
+						ram_access <= '0';
+						zaehler <= X"00000";
+						count <= "000";
+						int_flag <= '0';
+						interrupt_ignore <= '1';
+						state_interrupt_1 <= IR1_04;
+					when others =>
+						null;
+				end case;
+			end if; -- int = '0'
+			
+			if int_flag = '0' then
+				case state_init is
+					-- Interrupt
+					when INTERRUPT =>
+						case state_interrupt_2 is
+							when IR2_01 =>
+								par_addr <= W5300_IR;
+								state_init <= READ_REG;
+								next_state <= INTERRUPT;
+								state_interrupt_2 <= IR2_02;
+							when IR2_02 =>
+								if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
+									state_interrupt_2 <= IR2_03;
+								else
+                  socket_cnt <= socket_cnt + 1;
+                  if (socket_cnt = 7) then
+                    state_interrupt_2 <= IR2_06;
+                  else
+                    state_interrupt_2 <= IR2_02;
+                  end if; 
+								end if;
+							when IR2_03 =>
+								par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
+								state_init <= READ_REG;
+								next_state <= INTERRUPT;
+								state_interrupt_2 <= IR2_04;
+							when IR2_04 =>
+								par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
+								par_data <= data_read; -- clear Interrupts
+								state_init <= WRITE_REG;
+								next_state <= INTERRUPT;
+								state_interrupt_2 <= IR2_05;
+							when IR2_05 =>
+								par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
+								par_data <= X"0010"; -- CLOSE
+								state_init <= WRITE_REG;
+								next_state <= INTERRUPT;
+								socket_cnt <= socket_cnt + 1;
+								if (socket_cnt = 7) then
+								  state_interrupt_2 <= IR2_06;
+								else
+								  state_interrupt_2 <= IR2_01;
+								end if; 
+
+							when IR2_06 =>
+								state_interrupt_1 <= IR1_01;
+								state_interrupt_2 <= IR2_01;
+								socket_cnt <= "000";
+								state_init <= RESET;
+						end case;
+						
+					-- reset W5300
+					when RESET =>
+						zaehler <= zaehler + 1;
+            wiz_reset <= '0';
+            led <= X"FF";
+						if (zaehler >= X"00064") then -- wait 2µs
+							wiz_reset <= '1';
+						end if;	
+						if (zaehler = RST_TIME) then -- wait 10ms
+							zaehler <= X"00000";
+							socket_cnt <= "000";
+							count <= "000";
+							ram_access <= '0';
+							interrupt_ignore <= '0';
+							rd <= '1';
+							wr <= '1';
+							cs <= '1';
+							state_write <= WR_START;
+							state_init <= INIT;
+						end if;
+						
+					-- Init
+					when INIT =>
+						par_addr <= W5300_MR;
+						par_data <= X"0000";
+						state_init <= WRITE_REG;
+						next_state <= IM;
+						
+					-- Interrupt Mask
+					when IM =>
+						par_addr <= W5300_IMR;
+						par_data <= X"00FF"; -- S0-S7 Interrupts
+						state_init <= WRITE_REG;
+						next_state <= MT;
+						
+					-- Memory Type
+					when MT =>
+					  par_addr <=	W5300_MTYPER;
+					  par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer
+					  state_init <= WRITE_REG;
+					  next_state <= STX;
+					  
+					-- Socket TX Memory Size
+					when STX =>
+					  par_data <= X"0F0F"; -- 15K TX
+
+					 	par_addr <= W5300_TMS01R;
+					 	state_init <=WRITE_REG;
+					 	next_state <= STX1;
+          when STX1 =>
+            par_addr <= W5300_TMS23R;
+            state_init <=WRITE_REG;
+            next_state <= STX2;
+          when STX2 =>
+            par_addr <= W5300_TMS45R;
+            state_init <=WRITE_REG;
+            next_state <= STX3;
+          when STX3 =>
+            par_addr <= W5300_TMS67R;
+            state_init <=WRITE_REG;
+            next_state <= SRX;
+			 		
+          -- Socket RX Memory Size
+          when SRX =>
+            par_data <= X"0101"; -- 1K RX
+             
+            par_addr <= W5300_RMS01R;
+            state_init <=WRITE_REG;
+            next_state <= SRX1;
+          when SRX1 =>
+            par_addr <= W5300_RMS23R;
+            state_init <=WRITE_REG;
+            next_state <= SRX2;
+          when SRX2 =>
+            par_addr <= W5300_RMS45R;
+            state_init <=WRITE_REG;
+            next_state <= SRX3;
+          when SRX3 =>
+            par_addr <= W5300_RMS67R;
+            state_init <=WRITE_REG;
+            next_state <= MAC;
+	  
+					-- MAC
+					when MAC =>
+						par_addr <= W5300_SHAR;
+						par_data <= MAC_ADDRESS (0);
+						state_init <= WRITE_REG;
+						next_state <= MAC1;
+					when MAC1 =>
+						par_addr <= W5300_SHAR + 2;
+						par_data <= MAC_ADDRESS (1);
+						state_init <= WRITE_REG;
+						next_state <= MAC2;
+					when MAC2 =>
+						par_addr <= W5300_SHAR + 4;
+						par_data <= MAC_ADDRESS (2);
+						state_init <= WRITE_REG;
+						next_state <= GW;
+						
+					-- Gateway
+					when GW =>
+						par_addr <= W5300_GAR;
+						par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8);
+						par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8);
+						state_init <= WRITE_REG;
+						next_state <= GW1;
+					when GW1 =>
+						par_addr <= W5300_GAR + 2;
+						par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8);
+						par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8);
+						state_init <= WRITE_REG;
+						next_state <= SNM;
+						
+					-- Subnet Mask
+					when SNM =>
+						par_addr <= W5300_SUBR;
+						par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8);
+						par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8);
+						state_init <= WRITE_REG;
+						next_state <= SNM1;
+					when SNM1 =>
+						par_addr <= W5300_SUBR + 2;
+						par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8);
+						par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8);
+						state_init <= WRITE_REG;
+						next_state <= IP;
+					-- Own IP-Address
+					when IP =>
+						par_addr <= W5300_SIPR;
+						par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8);
+						par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8);
+						state_init <= WRITE_REG;
+						next_state <= IP1;
+					when IP1 =>
+						par_addr <= W5300_SIPR + 2;
+						par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8);
+						par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8);
+						state_init <= WRITE_REG;
+						next_state <= SI;
+
+					-- Socket Init
+					when SI =>
+						par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
+						par_data <= X"0101"; -- ALIGN, TCP
+						state_init <= WRITE_REG;
+						next_state <= SI1;
+					-- Sx Interrupt Mask
+					when SI1 =>
+						par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
+						par_data <= X"000A"; -- TIMEOUT, DISCON
+						state_init <= WRITE_REG;
+						next_state <= SI2;
+					when SI2 =>
+						par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
+						par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
+						state_init <= WRITE_REG;
+						next_state <= SI3;
+					when SI3 =>
+						par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
+						par_data <= X"0001"; -- OPEN
+						state_init <= WRITE_REG;
+						next_state <= SI4;
+					when SI4 =>
+						par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
+						state_init <= READ_REG;
+						next_state <= SI5;
+					when SI5 =>
+						if (data_read (7 downto 0) = X"13") then -- is open?
+							state_init <= SI6;
+						else
+							state_init <= SI4;
+						end if;
+					when SI6 =>
+						par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
+						par_data <= X"0002"; -- LISTEN
+						state_init <= WRITE_REG;
+						socket_cnt <= socket_cnt + 1;
+						if (socket_cnt = 7) then
+						  socket_cnt <= "000";
+						  next_state <= ESTABLISH; -- All Sockets open
+						else
+						  next_state <= SI; -- Next Socket
+						end if;
+				  -- End Socket Init
+						
+					when ESTABLISH =>
+						par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
+						state_init <= READ_REG;
+						next_state <= EST1;
+					when EST1 =>
+						led <= data_read (7 downto 0);
+						case data_read (7 downto 0) is
+							when X"17" => -- established
+                if (socket_cnt = 7) then
+                  socket_cnt <= "000";
+                  busy <= '0';
+                  state_init <= MAIN;
+                else
+                  socket_cnt <= socket_cnt + 1;
+                  state_init <= ESTABLISH;
+                end if;
+							when others =>
+								state_init <= ESTABLISH;
+						end case;
+					
+					when CONFIG =>
+            led <= X"F0";
+					  new_config <= '1';
+					  if (config_started = '1') then
+					    led <= X"0F";
+					    new_config <= '0';
+					    busy <= '0';
+					    state_init <= MAIN;
+					  end if;
+					
+          -- main "loop"
+					when MAIN =>
+            if (trigger_stop = '1') then
+					    s_trigger <= '0';
+					  end if;
+            if (chk_recv_cntr = 1000) then
+              chk_recv_cntr <= 0;
+              state_read_data <= RD_1;
+              state_init <= READ_DATA;
+              busy <= '1';
+            else
+              chk_recv_cntr <= chk_recv_cntr + 1;  
+  						  if (data_valid = '1') then
+                local_write_length <= write_length;
+                local_ram_start_addr <= ram_start_addr;
+                local_ram_addr <= (others => '0');
+                local_write_header_flag <= write_header_flag;
+                local_write_end_flag <= write_end_flag;
+                local_fifo_channels <= fifo_channels;
+							  next_state <= MAIN;
+							  state_init <= WRITE_DATA;
+							  busy <= '1';
+              end if;
+						end if;
+
+					-- read data from socket 0  
+          when READ_DATA =>
+            case state_read_data is
+              when RD_1 =>
+                par_addr <= W5300_S0_RX_RSR;
+                state_init <= READ_REG;
+                next_state <= READ_DATA;
+                state_read_data <= RD_2;
+              when RD_2 =>
+                socket_rx_received (31 downto 16) <= data_read;
+                par_addr <= W5300_S0_RX_RSR + X"2";
+                state_init <= READ_REG;
+                next_state <= READ_DATA;
+                state_read_data <= RD_3;
+              when RD_3 =>
+                socket_rx_received (15 downto 0) <= data_read;
+                state_read_data <= RD_4;
+              when RD_4 =>
+                if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
+                  rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
+                  state_read_data <= RD_5;
+                else
+                  busy <= '0';
+                  state_init <= MAIN;
+                end if;
+              when RD_5 =>
+                if (rx_packets_cnt > 0) then
+                  rx_packets_cnt <= rx_packets_cnt - '1';
+                  par_addr <= W5300_S0_RX_FIFOR;
+                  state_init <= READ_REG;
+                  next_state <= READ_DATA;
+                  state_read_data <= RD_6;
+                else
+                  state_read_data <= RD_END;
+--                  if (new_config_flag = '1') then
+--                    new_config_flag <= '0';
+--                    state_init <= CONFIG;
+--                  else
+--                    busy <= '0';
+--                    state_init <= MAIN;
+--                  end if;
+                end if;
+              when RD_6 =>
+                led <= data_read (15 downto 8);
+                -- read command
+                if (next_packet_data = '0') then
+                  case data_read (15 downto 8) is
+                    when CMD_TRIGGER =>
+                      trigger_stop <= '1';
+                      s_trigger <= '1';
+                      state_read_data <= RD_WAIT;
+                    when CMD_TRIGGER_C =>
+                      trigger_stop <= '0';
+                      s_trigger <= '1';
+                      state_read_data <= RD_WAIT;
+                    when CMD_TRIGGER_S =>
+                      trigger_stop <= '1';
+                      state_read_data <= RD_WAIT;
+                    when CMD_WRITE =>
+                      next_packet_data <= '1';
+                      config_addr <= data_read (7 downto 0);
+                      state_read_data <= RD_5;
+                    when others =>
+                      state_read_data <= RD_5;
+                  end case;
+                -- read data
+                else
+                  if (config_busy = '0') then
+                    config_data <= data_read;
+                    config_wr_en <= '1';
+                    new_config_flag <= '1';
+                    next_packet_data <= '0';
+                    state_read_data <= RD_WAIT;
+                  end if;
+                end if;
+              when RD_WAIT =>
+                state_read_data <= RD_WAIT1;
+              when RD_WAIT1 =>
+                config_data <= (others => 'Z');
+                config_wr_en <= '0';
+                state_read_data <= RD_5;
+              when RD_END =>
+                par_addr <= W5300_S0_CR;
+                par_data <= X"0040"; -- RECV
+                state_init <= WRITE_REG;
+                if (new_config_flag = '1') then
+                  new_config_flag <= '0';
+                  next_state <= CONFIG;
+                else
+                  busy <= '0';
+                  next_state <= MAIN;
+                end if;
+
+            end case; -- state_data_read
+                
+    
+
+					when WRITE_DATA =>
+						case state_write is
+						  when WR_START =>
+						    if (local_write_header_flag = '1') then
+						      ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ????
+						    end if;
+						    state_write <= WR_WAIT1;
+						  when WR_WAIT1 =>
+						    state_write <= WR_LENGTH;
+							when WR_LENGTH =>
+							  if (local_write_header_flag = '1') then
+							    local_socket_nr <= ram_data (2 downto 0);
+							  end if;
+								next_state_tmp <= next_state;
+								write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2)
+								data_cnt <= 0;
+								state_write <= WR_01;
+							-- Check FIFO Size
+							when WR_01 =>
+								par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
+								state_init <= READ_REG;
+								next_state <= WRITE_DATA;
+								state_write <= WR_02;
+							when WR_02 =>
+								socket_tx_free (31 downto 16) <= data_read;
+								par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
+								state_init <= READ_REG;
+								next_state <= WRITE_DATA;
+								state_write <= WR_03;
+							when WR_03 =>
+								socket_tx_free (15 downto 0) <= data_read;
+								state_write <= WR_04;
+							when WR_04 =>
+								if (socket_tx_free (16 downto 0) < write_length_bytes) then
+									state_write <= WR_01;
+								else
+								  if (local_write_header_flag = '1') then
+									  state_write <= WR_FIFO;
+									else
+									  state_write <= WR_ADC;
+									end if; 
+								end if;
+							
+							-- Fill FIFO
+
+							-- Write Header
+							when WR_FIFO =>
+                ram_addr <= local_ram_start_addr + local_ram_addr;
+							  state_write <= WR_FIFO1;
+							when WR_FIFO1 =>
+ 								data_cnt <= data_cnt + 1;
+								if (data_cnt < PACKAGE_HEADER_LENGTH) then --???
+								  local_ram_addr <= local_ram_addr + 1;
+								  if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words
+								    local_ram_addr <= local_ram_addr + 2;
+								  end if;
+								  if (data_cnt = 9) then -- skip empty words
+								    local_ram_addr <= local_ram_addr + 4;
+								  end if;  
+									par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
+									ram_access <= '1';
+									state_init <= WRITE_REG;
+									next_state <= WRITE_DATA;
+									state_write <= WR_FIFO;
+								else
+									state_write <= WR_ADC;
+								end if;
+							-- End Write Header
+							
+							-- Write ADC-Data
+							---- Start...
+							when WR_ADC =>
+							  adc_data_addr <= local_ram_start_addr + local_ram_addr;
+							  drs_cnt <= 0;
+							  channel_cnt <= 1;
+                data_cnt <= 0;
+							  roi_max <= (others => '0');
+							  data_end <= 3;
+							  state_write <= WR_ADC1;
+
+							---- Write Channel
+							when WR_ADC1 =>
+							  -- read ROI and set end of Channel-Data
+							  if (data_cnt = 3) then
+							    data_end <= conv_integer (ram_data) + 3;
+							    if (ram_data > roi_max) then
+							      roi_max <= ram_data (10 downto 0);
+							    end if;
+							  end if;
+							  ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4);
+                state_write <= WR_ADC2;
+							when WR_ADC2 =>
+                if (data_cnt < data_end) then
+                  par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
+                  ram_access <= '1';
+                  state_init <= WRITE_REG;
+                  next_state <= WRITE_DATA;
+                  data_cnt <= data_cnt + 1;
+                  state_write <= WR_ADC1;
+                else
+                  -- Next DRS
+                  if (drs_cnt < 3) then
+                    drs_cnt <= drs_cnt + 1;
+                    data_cnt <= 0;
+                    data_end <= 3;
+                    state_write <= WR_ADC1;
+                  else
+                    -- Next Channel
+                    if (channel_cnt < local_fifo_channels) then
+                      channel_cnt <= channel_cnt + 1;
+                      roi_max <= (others => '0');
+                      drs_cnt <= 0;
+                      data_cnt <= 0;
+                      data_end <= 3;
+                      adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
+                      state_write <= WR_ADC1;
+                    else
+                      -- Ready
+                      if (local_write_end_flag = '1') then
+                        state_write <= WR_ENDFLAG;
+                      else
+                        state_write <= WR_05;
+                      end if;
+                    end if;
+                  end if;    
+                end if;
+							-- End Write ADC-Data
+
+              -- Write End Package Flag
+              when WR_ENDFLAG =>
+                ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
+                state_write <= WR_ENDFLAG1;
+              when WR_ENDFLAG1 =>
+                par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
+                ram_access <= '1';
+                state_init <= WRITE_REG;
+                next_state <= WRITE_DATA;
+                state_write <= WR_ENDFLAG2;
+              when WR_ENDFLAG2 =>
+                ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1;
+                state_write <= WR_ENDFLAG3;
+              when WR_ENDFLAG3 =>
+                state_init <= WRITE_REG;
+                next_state <= WRITE_DATA;
+                state_write <= WR_05;
+              
+              -- End Write End Package Flag
+
+              --Send FIFO
+							when WR_05 =>
+							  ram_access <= '0';
+								par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
+								par_data <= (0 => write_length_bytes (16), others => '0');
+								state_init <= WRITE_REG;
+								state_write <= WR_06;
+							when WR_06 =>
+								par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
+								par_data <= write_length_bytes (15 downto 0);
+								state_init <= WRITE_REG;
+								state_write <= WR_07;
+							when WR_07 =>
+								par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
+								par_data <= X"0020"; -- Send
+								state_init <= WRITE_REG;
+								state_write <= WR_08;
+							when others =>
+ 								busy <= '0';
+								state_init <= next_state_tmp;
+								state_write <= WR_START;
+						end case;
+						-- End WRITE_DATA
+						
+					when READ_REG =>
+						case count is
+							when "000" =>
+								cs <= '0';
+								rd <= '0';
+								wr <= '1';
+								data <= (others => 'Z'); -- !!!!!!!!!!
+								count <= "001";
+								addr <= par_addr;
+							when "001" =>
+								count <= "010";
+							when "010" =>
+								count <= "100";
+							when "100" =>
+								data_read <= data;
+								count <= "110";
+							when "110" =>
+								count <= "111";
+							when "111" =>
+								cs <= '1';
+								rd <= '1';
+								count <= "000";
+								state_init <= next_state;
+							when others =>
+								null;
+						end case;
+					
+					when WRITE_REG =>
+						case count is
+							when "000" =>
+								cs <= '0';
+								wr <= '0';
+								rd <= '1';
+								addr <= par_addr; 
+								if (ram_access = '1') then
+									data <= ram_data;
+								else
+									data <= par_data;
+								end if;
+								count <= "100";
+							when "100" =>
+								count <= "101";
+							when "101" =>
+								count <= "110";
+							when "110" =>
+								cs <= '1';
+								wr <= '1';
+								state_init <= next_state;
+								count <= "000";
+							when others =>
+								null;
+						end case;
+					
+					when others =>
+						null;
+				end case;
+			end if; -- int_flag = '0'
+
+		end if; -- rising_edge (clk)
+
+	end process w5300_init_proc;
+
+end Behavioral;
+
