/* $ZEL: f1_map.h,v 1.2 2004/05/27 23:10:14 wuestner Exp $ */

/*
 * Copyright (c) 2004
 * 	Peter Wuestner.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifndef _straw_map_h_
#define _straw_map_h_

struct straw_cm_regs {
        u_int32_t   ident;
        u_int32_t   sr;                     /* Status Register */
#define SR_EVENT        0x0010L
#define SR_DATA_AVAIL   0x0020L
#define SR_ATTENT       0x0040L

        u_int32_t   cr;                     /* Control Register, 4 bit */
/* noch unbenutzt */

        u_int32_t   res1;
        u_int32_t   jtag_csr;               /* JTAG control/status */
        u_int32_t   jtag_data;              /* JTAG data */
};

struct straw_reg {
    u_int32_t ident;
    u_int32_t sc;
    u_int32_t optical_cr;
    u_int32_t dsp_sc;
    u_int32_t dummy;
};

/* bits in in_out */
#define straw_io_flat_out1 (1<<0)
#define straw_io_flat_out2 (1<<1)
#define straw_io_flat_out3 (1<<2)
#define straw_io_flat_out4 (1<<3)
#define straw_io_lemo_out1 (1<<4)
#define straw_io_lemo_out2 (1<<5)
#define straw_io_lemo_out3 (1<<6)
/* clear is (io_*_out?)<<16 */
#define straw_io_flat_in1 (1<<16)
#define straw_io_flat_in2 (1<<17)
#define straw_io_flat_in3 (1<<18)
#define straw_io_flat_in4 (1<<19)
#define straw_io_lemo_in1 (1<<20)
#define straw_io_lemo_in2 (1<<21)
#define straw_io_lemo_in3 (1<<22)

/* bits in dsp_sc */
#define straw_dsp_run        (1<<8)
#define straw_dsp_boot_eprom (1<<9)
#define straw_dsp_boot_ctrl  (1<<11)

#define straw_dsp_available  (1<<24)
#define straw_dsp_flag0      (1<<28)
#define straw_dsp_flag1      (1<<29)
#define straw_dsp_flag2      (1<<30)
#define straw_dsp_flag3      (1<<31)

/* error codes */
#define straw_sis3100_re_berr        0x211 /* Bus Error */
#define straw_sis3100_re_retr        0x212 /* Retry */
#define straw_sis3100_re_atimeout    0x214 /* Arbitration timeout */

#endif
