Index: FPGA/FTU/test_firmware/FTU_test1.vhd =================================================================== --- FPGA/FTU/test_firmware/FTU_test1.vhd (revision 228) +++ (revision ) @@ -1,162 +1,0 @@ ----------------------------------------------------------------------------------- --- Company: ETH Zurich, Institute for Particle Physics --- Engineer: P. Vogler, Q. Weitzel --- --- Create Date: 04/05/2010 --- Design Name: --- Module Name: FTU_test1 - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: Test firmware for FTU board, switch on/off enable signals --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity FTU_test1 is - port( - -- global control - ext_clk : IN STD_LOGIC; -- external clock from FTU board - --reset : in STD_LOGIC; -- reset - brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- global board address (not local) - - -- rate counters LVDS inputs - -- use IBUFDS differential input buffer - patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch - patch_A_n : IN STD_LOGIC; - patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch - patch_B_n : IN STD_LOGIC; - patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch - patch_C_n : IN STD_LOGIC; - patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch - patch_D_n : IN STD_LOGIC; - trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit - trig_prim_n : IN STD_LOGIC; - - -- DAC interface - -- miso : IN STD_LOGIC; -- master-in-slave-out - sck : OUT STD_LOGIC; -- serial clock to DAC - mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in - clr : OUT STD_LOGIC; -- clear signal to DAC - cs_ld : OUT STD_LOGIC; -- chip select or load to DAC - - -- RS-485 interface to FTM - rx : IN STD_LOGIC; -- serial data from FTM - tx : OUT STD_LOGIC; -- serial data to FTM - rx_en : OUT STD_LOGIC; -- enable RS-485 receiver - tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter - - -- analog buffer enable - enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs - enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs - enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs - enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs - - -- testpoints - TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints - ); -end FTU_test1; - -architecture Behavioral of FTU_test1 is - - component FTU_test1_dcm - port( - CLKIN_IN : IN STD_LOGIC; - CLKFX_OUT : OUT STD_LOGIC; - CLKIN_IBUFG_OUT : OUT STD_LOGIC - ); - end component; - - component Clock_Divider - port( - clock : IN STD_LOGIC; - enable_out : OUT STD_LOGIC - ); - end component; - - signal clk_5M_sig : STD_LOGIC; - signal enable_sig : STD_LOGIC; - -begin - - Inst_FTU_test1_dcm : FTU_test1_dcm - port map( - CLKIN_IN => ext_clk, - CLKFX_OUT => clk_5M_sig, - CLKIN_IBUFG_OUT => open - ); - - Inst_Clock_Divider : Clock_Divider - port map ( - clock => clk_5M_sig, - enable_out => enable_sig - ); - - enables_A(8) <= enable_sig; - enables_B(8) <= enable_sig; - enables_C(8) <= enable_sig; - enables_D(8) <= enable_sig; - -end Behavioral; - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity Clock_Divider is - port( - clock : in std_logic; - enable_out: out std_logic - ); -end entity Clock_Divider; - -architecture RTL of Clock_Divider is - - constant max_count : integer := 5000000/1000000; -- for simulation - --constant max_count : integer := 5000000/1; -- for implementation - constant final_count : integer := 3; - -begin - - process(clock) - variable count : integer range 0 to max_count; - variable count2 : integer range 0 to final_count; - begin - if rising_edge(clock) then - --enable_out <= '0'; - if count2 = final_count then - enable_out <= '0'; - else - if count < max_count/2 then - enable_out <= '0'; - count := count + 1; - elsif count < max_count then - enable_out <= '1'; - count := count + 1; - else - count := 0; - enable_out <= '0'; - count2 := count2 + 1; - end if; - end if; - end if; - end process; - -end architecture RTL; Index: FPGA/FTU/test_firmware/FTU_test1/FTU_test1.vhd =================================================================== --- FPGA/FTU/test_firmware/FTU_test1/FTU_test1.vhd (revision 233) +++ FPGA/FTU/test_firmware/FTU_test1/FTU_test1.vhd (revision 233) @@ -0,0 +1,162 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 04/05/2010 +-- Design Name: +-- Module Name: FTU_test1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTU board, switch on/off enable signals +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTU_test1 is + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + --reset : in STD_LOGIC; -- reset + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- global board address (not local) + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + -- miso : IN STD_LOGIC; -- master-in-slave-out + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); +end FTU_test1; + +architecture Behavioral of FTU_test1 is + + component FTU_test1_dcm + port( + CLKIN_IN : IN STD_LOGIC; + CLKFX_OUT : OUT STD_LOGIC; + CLKIN_IBUFG_OUT : OUT STD_LOGIC + ); + end component; + + component Clock_Divider + port( + clock : IN STD_LOGIC; + enable_out : OUT STD_LOGIC + ); + end component; + + signal clk_5M_sig : STD_LOGIC; + signal enable_sig : STD_LOGIC; + +begin + + Inst_FTU_test1_dcm : FTU_test1_dcm + port map( + CLKIN_IN => ext_clk, + CLKFX_OUT => clk_5M_sig, + CLKIN_IBUFG_OUT => open + ); + + Inst_Clock_Divider : Clock_Divider + port map ( + clock => clk_5M_sig, + enable_out => enable_sig + ); + + enables_A(8) <= enable_sig; + enables_B(8) <= enable_sig; + enables_C(8) <= enable_sig; + enables_D(8) <= enable_sig; + +end Behavioral; + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity Clock_Divider is + port( + clock : in std_logic; + enable_out: out std_logic + ); +end entity Clock_Divider; + +architecture RTL of Clock_Divider is + + constant max_count : integer := 5000000/1000000; -- for simulation + --constant max_count : integer := 5000000/1; -- for implementation + constant final_count : integer := 3; + +begin + + process(clock) + variable count : integer range 0 to max_count; + variable count2 : integer range 0 to final_count; + begin + if rising_edge(clock) then + --enable_out <= '0'; + if count2 = final_count then + enable_out <= '0'; + else + if count < max_count/2 then + enable_out <= '0'; + count := count + 1; + elsif count < max_count then + enable_out <= '1'; + count := count + 1; + else + count := 0; + enable_out <= '0'; + count2 := count2 + 1; + end if; + end if; + end if; + end process; + +end architecture RTL; Index: FPGA/FTU/test_firmware/FTU_test1/FTU_test1_dcm.vhd =================================================================== --- FPGA/FTU/test_firmware/FTU_test1/FTU_test1_dcm.vhd (revision 233) +++ FPGA/FTU/test_firmware/FTU_test1/FTU_test1_dcm.vhd (revision 233) @@ -0,0 +1,88 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.1 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTU_test1_dcm.vhd +-- /___/ /\ Timestamp : 05/04/2010 17:27:08 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /home/qweitzel/CT3-FACT/fact_repos.svn/FPGA/FTU/test_firmware/FTU_test1_dcm.xaw /home/qweitzel/CT3-FACT/fact_repos.svn/FPGA/FTU/test_firmware/FTU_test1_dcm +--Design Name: FTU_test1_dcm +--Device: xc3s400an-4fgg400 +-- +-- Module FTU_test1_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 6.54 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTU_test1_dcm is + port ( CLKIN_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic); +end FTU_test1_dcm; + +architecture BEHAVIORAL of FTU_test1_dcm is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 20, + CLKFX_MULTIPLY => 2, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>GND_BIT, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>open, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: FPGA/FTU/test_firmware/FTU_test1/FTU_test1_dcm_arwz.ucf =================================================================== --- FPGA/FTU/test_firmware/FTU_test1/FTU_test1_dcm_arwz.ucf (revision 233) +++ FPGA/FTU/test_firmware/FTU_test1/FTU_test1_dcm_arwz.ucf (revision 233) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = NONE; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 20; +INST DCM_SP_INST CLKFX_MULTIPLY = 2; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 20.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: FPGA/FTU/test_firmware/FTU_test1/FTU_test1_tb.vhd =================================================================== --- FPGA/FTU/test_firmware/FTU_test1/FTU_test1_tb.vhd (revision 233) +++ FPGA/FTU/test_firmware/FTU_test1/FTU_test1_tb.vhd (revision 233) @@ -0,0 +1,174 @@ +-------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 05/04/2010 +-- Design Name: +-- Module Name: /home/qweitzel/FPGA/FACT/FTU/test_firmware/FTU_test1_tb.vhd +-- Project Name: FTU_test1_sim01 +-- Target Device: +-- Tool versions: +-- Description: Testbench for test1 entity of FACT FTU board +-- +-- VHDL Test Bench Created by ISE for module: FTU_test1 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity FTU_test1_tb is +end FTU_test1_tb; + +architecture behavior of FTU_test1_tb is + + -- Component Declaration for the Unit Under Test (UUT) + + component FTU_test1 + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + --reset : in STD_LOGIC; -- reset + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- global board address (not local) + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + -- miso : IN STD_LOGIC; -- master-in-slave-out + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); + end component; + + --Inputs + signal ext_clk : STD_LOGIC := '0'; + --signal reset : STD_LOGIC := '0'; + signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); + signal patch_A_p : STD_LOGIC := '0'; + signal patch_A_n : STD_LOGIC := '0'; + signal patch_B_p : STD_LOGIC := '0'; + signal patch_B_n : STD_LOGIC := '0'; + signal patch_C_p : STD_LOGIC := '0'; + signal patch_C_n : STD_LOGIC := '0'; + signal patch_D_p : STD_LOGIC := '0'; + signal patch_D_n : STD_LOGIC := '0'; + signal trig_prim_p : STD_LOGIC := '0'; + signal trig_prim_n : STD_LOGIC := '0'; + -- signal miso : STD_LOGIC := '0'; + signal rx : STD_LOGIC := '0'; + + --Outputs + signal enables_A : STD_LOGIC_VECTOR(8 downto 0); + signal enables_B : STD_LOGIC_VECTOR(8 downto 0); + signal enables_C : STD_LOGIC_VECTOR(8 downto 0); + signal enables_D : STD_LOGIC_VECTOR(8 downto 0); + signal clr : STD_LOGIC; + signal cs_ld : STD_LOGIC; + signal sck : STD_LOGIC; + signal mosi : STD_LOGIC; + signal tx : STD_LOGIC; + signal rx_en : STD_LOGIC; + signal tx_en : STD_LOGIC; + signal TP_A : STD_LOGIC_VECTOR(11 downto 0); + + -- Clock period definitions + constant ext_clk_period : TIME := 20 ns; + +begin + + -- Instantiate the Unit Under Test (UUT) + uut: FTU_test1 + port map( + ext_clk => ext_clk, + --reset => reset, + brd_add => brd_add, + patch_A_p => patch_A_p, + patch_A_n => patch_A_n, + patch_B_p => patch_B_p, + patch_B_n => patch_B_n, + patch_C_p => patch_C_p, + patch_C_n => patch_C_n, + patch_D_p => patch_D_p, + patch_D_n => patch_D_n, + trig_prim_p => trig_prim_p, + trig_prim_n => trig_prim_n, + -- miso => miso, + rx => rx, + rx_en => rx_en, + enables_A => enables_A, + enables_B => enables_B, + enables_C => enables_C, + enables_D => enables_D, + clr => clr, + cs_ld => cs_ld, + sck => sck, + mosi => mosi, + tx => tx, + tx_en => tx_en, + TP_A => TP_A + ); + + -- Clock process definitions + ext_clk_proc: process + begin + ext_clk <= '0'; + wait for ext_clk_period/2; + ext_clk <= '1'; + wait for ext_clk_period/2; + end process ext_clk_proc; + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + wait for 100ms; + + wait for ext_clk_period*10; + + -- insert stimulus here + + wait; + end process stim_proc; + +end; Index: FPGA/FTU/test_firmware/FTU_test1_dcm.vhd =================================================================== --- FPGA/FTU/test_firmware/FTU_test1_dcm.vhd (revision 228) +++ (revision ) @@ -1,88 +1,0 @@ --------------------------------------------------------------------------------- --- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. --------------------------------------------------------------------------------- --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx --- \ \ \/ Version : 11.1 --- \ \ Application : xaw2vhdl --- / / Filename : FTU_test1_dcm.vhd --- /___/ /\ Timestamp : 05/04/2010 17:27:08 --- \ \ / \ --- \___\/\___\ --- ---Command: xaw2vhdl-st /home/qweitzel/CT3-FACT/fact_repos.svn/FPGA/FTU/test_firmware/FTU_test1_dcm.xaw /home/qweitzel/CT3-FACT/fact_repos.svn/FPGA/FTU/test_firmware/FTU_test1_dcm ---Design Name: FTU_test1_dcm ---Device: xc3s400an-4fgg400 --- --- Module FTU_test1_dcm --- Generated by Xilinx Architecture Wizard --- Written for synthesis tool: XST --- Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI --- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 6.54 ns - -library ieee; -use ieee.std_logic_1164.ALL; -use ieee.numeric_std.ALL; -library UNISIM; -use UNISIM.Vcomponents.ALL; - -entity FTU_test1_dcm is - port ( CLKIN_IN : in std_logic; - CLKFX_OUT : out std_logic; - CLKIN_IBUFG_OUT : out std_logic); -end FTU_test1_dcm; - -architecture BEHAVIORAL of FTU_test1_dcm is - signal CLKFX_BUF : std_logic; - signal CLKIN_IBUFG : std_logic; - signal GND_BIT : std_logic; -begin - GND_BIT <= '0'; - CLKIN_IBUFG_OUT <= CLKIN_IBUFG; - CLKFX_BUFG_INST : BUFG - port map (I=>CLKFX_BUF, - O=>CLKFX_OUT); - - CLKIN_IBUFG_INST : IBUFG - port map (I=>CLKIN_IN, - O=>CLKIN_IBUFG); - - DCM_SP_INST : DCM_SP - generic map( CLK_FEEDBACK => "NONE", - CLKDV_DIVIDE => 2.0, - CLKFX_DIVIDE => 20, - CLKFX_MULTIPLY => 2, - CLKIN_DIVIDE_BY_2 => FALSE, - CLKIN_PERIOD => 20.000, - CLKOUT_PHASE_SHIFT => "NONE", - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", - DFS_FREQUENCY_MODE => "LOW", - DLL_FREQUENCY_MODE => "LOW", - DUTY_CYCLE_CORRECTION => TRUE, - FACTORY_JF => x"C080", - PHASE_SHIFT => 0, - STARTUP_WAIT => FALSE) - port map (CLKFB=>GND_BIT, - CLKIN=>CLKIN_IBUFG, - DSSEN=>GND_BIT, - PSCLK=>GND_BIT, - PSEN=>GND_BIT, - PSINCDEC=>GND_BIT, - RST=>GND_BIT, - CLKDV=>open, - CLKFX=>CLKFX_BUF, - CLKFX180=>open, - CLK0=>open, - CLK2X=>open, - CLK2X180=>open, - CLK90=>open, - CLK180=>open, - CLK270=>open, - LOCKED=>open, - PSDONE=>open, - STATUS=>open); - -end BEHAVIORAL; - - Index: FPGA/FTU/test_firmware/FTU_test1_dcm_arwz.ucf =================================================================== --- FPGA/FTU/test_firmware/FTU_test1_dcm_arwz.ucf (revision 228) +++ (revision ) @@ -1,17 +1,0 @@ -# Generated by Xilinx Architecture Wizard -# --- UCF Template Only --- -# Cut and paste these attributes into the project's UCF file, if desired -INST DCM_SP_INST CLK_FEEDBACK = NONE; -INST DCM_SP_INST CLKDV_DIVIDE = 2.0; -INST DCM_SP_INST CLKFX_DIVIDE = 20; -INST DCM_SP_INST CLKFX_MULTIPLY = 2; -INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; -INST DCM_SP_INST CLKIN_PERIOD = 20.000; -INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; -INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; -INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; -INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; -INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; -INST DCM_SP_INST FACTORY_JF = C080; -INST DCM_SP_INST PHASE_SHIFT = 0; -INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: FPGA/FTU/test_firmware/FTU_test1_tb.vhd =================================================================== --- FPGA/FTU/test_firmware/FTU_test1_tb.vhd (revision 228) +++ (revision ) @@ -1,174 +1,0 @@ --------------------------------------------------------------------------------- --- Company: ETH Zurich, Institute for Particle Physics --- Engineer: P. Vogler, Q. Weitzel --- --- Create Date: 05/04/2010 --- Design Name: --- Module Name: /home/qweitzel/FPGA/FACT/FTU/test_firmware/FTU_test1_tb.vhd --- Project Name: FTU_test1_sim01 --- Target Device: --- Tool versions: --- Description: Testbench for test1 entity of FACT FTU board --- --- VHDL Test Bench Created by ISE for module: FTU_test1 --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity FTU_test1_tb is -end FTU_test1_tb; - -architecture behavior of FTU_test1_tb is - - -- Component Declaration for the Unit Under Test (UUT) - - component FTU_test1 - port( - -- global control - ext_clk : IN STD_LOGIC; -- external clock from FTU board - --reset : in STD_LOGIC; -- reset - brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- global board address (not local) - - -- rate counters LVDS inputs - -- use IBUFDS differential input buffer - patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch - patch_A_n : IN STD_LOGIC; - patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch - patch_B_n : IN STD_LOGIC; - patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch - patch_C_n : IN STD_LOGIC; - patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch - patch_D_n : IN STD_LOGIC; - trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit - trig_prim_n : IN STD_LOGIC; - - -- DAC interface - -- miso : IN STD_LOGIC; -- master-in-slave-out - sck : OUT STD_LOGIC; -- serial clock to DAC - mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in - clr : OUT STD_LOGIC; -- clear signal to DAC - cs_ld : OUT STD_LOGIC; -- chip select or load to DAC - - -- RS-485 interface to FTM - rx : IN STD_LOGIC; -- serial data from FTM - tx : OUT STD_LOGIC; -- serial data to FTM - rx_en : OUT STD_LOGIC; -- enable RS-485 receiver - tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter - - -- analog buffer enable - enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs - enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs - enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs - enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs - - -- testpoints - TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints - ); - end component; - - --Inputs - signal ext_clk : STD_LOGIC := '0'; - --signal reset : STD_LOGIC := '0'; - signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); - signal patch_A_p : STD_LOGIC := '0'; - signal patch_A_n : STD_LOGIC := '0'; - signal patch_B_p : STD_LOGIC := '0'; - signal patch_B_n : STD_LOGIC := '0'; - signal patch_C_p : STD_LOGIC := '0'; - signal patch_C_n : STD_LOGIC := '0'; - signal patch_D_p : STD_LOGIC := '0'; - signal patch_D_n : STD_LOGIC := '0'; - signal trig_prim_p : STD_LOGIC := '0'; - signal trig_prim_n : STD_LOGIC := '0'; - -- signal miso : STD_LOGIC := '0'; - signal rx : STD_LOGIC := '0'; - - --Outputs - signal enables_A : STD_LOGIC_VECTOR(8 downto 0); - signal enables_B : STD_LOGIC_VECTOR(8 downto 0); - signal enables_C : STD_LOGIC_VECTOR(8 downto 0); - signal enables_D : STD_LOGIC_VECTOR(8 downto 0); - signal clr : STD_LOGIC; - signal cs_ld : STD_LOGIC; - signal sck : STD_LOGIC; - signal mosi : STD_LOGIC; - signal tx : STD_LOGIC; - signal rx_en : STD_LOGIC; - signal tx_en : STD_LOGIC; - signal TP_A : STD_LOGIC_VECTOR(11 downto 0); - - -- Clock period definitions - constant ext_clk_period : TIME := 20 ns; - -begin - - -- Instantiate the Unit Under Test (UUT) - uut: FTU_test1 - port map( - ext_clk => ext_clk, - --reset => reset, - brd_add => brd_add, - patch_A_p => patch_A_p, - patch_A_n => patch_A_n, - patch_B_p => patch_B_p, - patch_B_n => patch_B_n, - patch_C_p => patch_C_p, - patch_C_n => patch_C_n, - patch_D_p => patch_D_p, - patch_D_n => patch_D_n, - trig_prim_p => trig_prim_p, - trig_prim_n => trig_prim_n, - -- miso => miso, - rx => rx, - rx_en => rx_en, - enables_A => enables_A, - enables_B => enables_B, - enables_C => enables_C, - enables_D => enables_D, - clr => clr, - cs_ld => cs_ld, - sck => sck, - mosi => mosi, - tx => tx, - tx_en => tx_en, - TP_A => TP_A - ); - - -- Clock process definitions - ext_clk_proc: process - begin - ext_clk <= '0'; - wait for ext_clk_period/2; - ext_clk <= '1'; - wait for ext_clk_period/2; - end process ext_clk_proc; - - -- Stimulus process - stim_proc: process - begin - -- hold reset state for 100ms. - wait for 100ms; - - wait for ext_clk_period*10; - - -- insert stimulus here - - wait; - end process stim_proc; - -end;