Changeset 234 for FPGA/FTU/ftu_board.ucf


Ignore:
Timestamp:
Jul 1, 2010, 10:31:43 AM (11 years ago)
Author:
qweitzel
Message:
ucf file for FTU updated
File:
1 edited

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  • FPGA/FTU/ftu_board.ucf

    r219 r234  
    55# Pin location constraints
    66#
    7 # by Patrick Vogler
     7# by Patrick Vogler, Quirin Weitzel
     8# 01 July 2010
    89########################################################
    910
     
    1112#Clock
    1213#######################################################
    13 NET Clk LOC = Y11 | IOSTANDARD=LVCMOS33;               
     14NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk     
    1415
    1516
    1617# RS-485 Interface
    1718#######################################################
    18 NET 485_RE LOC  = T20 | IOSTANDARD=LVCMOS33;           
    19 NET 485_DE LOC  = U20 | IOSTANDARD=LVCMOS33;           
    20 NET 485_DO LOC  = U19 | IOSTANDARD=LVCMOS33;           
    21 NET 485_DI LOC  = R20 | IOSTANDARD=LVCMOS33;           
     19NET rx_en LOC  = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver             
     20NET tx_en LOC  = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter           
     21NET tx    LOC  = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM         
     22NET rx    LOC  = R20 | IOSTANDARD=LVCMOS33;               # 485_DI: serial data from FTM
    2223
    2324
    24 # Board ID  - inputs
     25# Board ID - inputs
     26# local board-ID "solder programmable"
    2527#######################################################
    26 NET P0 LOC  = C4 | IOSTANDARD=LVCMOS33;         
    27 NET P1 LOC  = C5 | IOSTANDARD=LVCMOS33;         
    28 NET P2 LOC  = C6 | IOSTANDARD=LVCMOS33;         
    29 NET P3 LOC  = C7 | IOSTANDARD=LVCMOS33;         
    30 NET P4 LOC  = C8 | IOSTANDARD=LVCMOS33;         
    31 NET P5 LOC  = B8 | IOSTANDARD=LVCMOS33;         
    32 NET P6 LOC  = C9 | IOSTANDARD=LVCMOS33;
    33 NET P7 LOC  = B9 | IOSTANDARD=LVCMOS33;
     28NET brd_id<0> LOC  = C4 | IOSTANDARD=LVCMOS33; # P0             
     29NET brd_id<1> LOC  = C5 | IOSTANDARD=LVCMOS33; # P1             
     30NET brd_id<2> LOC  = C6 | IOSTANDARD=LVCMOS33; # P2             
     31NET brd_id<3> LOC  = C7 | IOSTANDARD=LVCMOS33; # P3             
     32NET brd_id<4> LOC  = C8 | IOSTANDARD=LVCMOS33; # P4             
     33NET brd_id<5> LOC  = B8 | IOSTANDARD=LVCMOS33; # P5             
     34NET brd_id<6> LOC  = C9 | IOSTANDARD=LVCMOS33; # P6     
     35NET brd_id<7> LOC  = B9 | IOSTANDARD=LVCMOS33; # P7     
    3436
    3537
    3638# Board Addresses
     39# geographical slot address
    3740#######################################################
    38 NET ADDR0 LOC  = A15 | IOSTANDARD=LVCMOS33;
    39 NET ADDR1 LOC  = B15 | IOSTANDARD=LVCMOS33;
    40 NET ADDR2 LOC  = A16 | IOSTANDARD=LVCMOS33;
    41 NET ADDR3 LOC  = A17 | IOSTANDARD=LVCMOS33;
    42 NET ADDR4 LOC  = A18 | IOSTANDARD=LVCMOS33;
    43 NET ADDR5 LOC  = B18 | IOSTANDARD=LVCMOS33;
     41NET brd_add<0> LOC  = A15 | IOSTANDARD=LVCMOS33; # ADDR0
     42NET brd_add<1> LOC  = B15 | IOSTANDARD=LVCMOS33; # ADDR1
     43NET brd_add<2> LOC  = A16 | IOSTANDARD=LVCMOS33; # ADDR2
     44NET brd_add<3> LOC  = A17 | IOSTANDARD=LVCMOS33; # ADDR3
     45NET brd_add<4> LOC  = A18 | IOSTANDARD=LVCMOS33; # ADDR4
     46NET brd_add<5> LOC  = B18 | IOSTANDARD=LVCMOS33; # ADDR5
    4447
    4548
    4649# DAC SPI Interface
    4750#######################################################
    48 NET MOSI LOC  = E20 | IOSTANDARD=LVCMOS33;                     
    49 NET SCK LOC  = E19 | IOSTANDARD=LVCMOS33;                       
    50 NET DAC_CS LOC  = E18 | IOSTANDARD=LVCMOS33;                   
    51 NET DAC_CRL LOC  = D20 | IOSTANDARD=LVCMOS33;                  
     51NET mosi   LOC  = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in              
     52NET sck    LOC  = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC                   
     53NET cs_ld  LOC  = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC                 
     54NET clr    LOC  = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC       
    5255
    5356
     
    5558######################################################
    5659# on Connector J5
    57 NET TP0_0 LOC  = B3 | IOSTANDARD=LVCMOS33;
    58 NET TP1_0 LOC  = A3 | IOSTANDARD=LVCMOS33;
    59 NET TP2_0 LOC  = A4 | IOSTANDARD=LVCMOS33;
    60 NET TP3_0 LOC  = B5 | IOSTANDARD=LVCMOS33;
     60NET TP_A<0> LOC  = B3 | IOSTANDARD=LVCMOS33;  # TP0_0
     61NET TP_A<1> LOC  = A3 | IOSTANDARD=LVCMOS33;  # TP1_0
     62NET TP_A<2> LOC  = A4 | IOSTANDARD=LVCMOS33;  # TP2_0
     63NET TP_A<3> LOC  = B5 | IOSTANDARD=LVCMOS33;  # TP2_0
    6164
    6265# on Connector J6
    63 NET TP4_0 LOC  = A5 | IOSTANDARD=LVCMOS33;
    64 NET TP5_0 LOC  = A6 | IOSTANDARD=LVCMOS33;
    65 NET TP6_0 LOC  = B7 | IOSTANDARD=LVCMOS33;
    66 NET TP7_0 LOC  = A7 | IOSTANDARD=LVCMOS33;
     66NET TP_A<4> LOC  = A5 | IOSTANDARD=LVCMOS33;  # TP4_0
     67NET TP_A<5> LOC  = A6 | IOSTANDARD=LVCMOS33;  # TP5_0
     68NET TP_A<6> LOC  = B7 | IOSTANDARD=LVCMOS33;  # TP6_0
     69NET TP_A<7> LOC  = A7 | IOSTANDARD=LVCMOS33;  # TP7_0
    6770
    6871# on Connector J7
    69 NET TP8_0 LOC  = B11  | IOSTANDARD=LVCMOS33;
    70 NET TP9_0 LOC  = A12  | IOSTANDARD=LVCMOS33;
    71 NET TP10_0 LOC  = B12 | IOSTANDARD=LVCMOS33;
    72 NET TP11_0 LOC  = A14 | IOSTANDARD=LVCMOS33;
     72NET TP_A<8>  LOC  = B11  | IOSTANDARD=LVCMOS33;  # TP8_0
     73NET TP_A<9>  LOC  = A12  | IOSTANDARD=LVCMOS33;  # TP9_0
     74NET TP_A<10> LOC  = B12  | IOSTANDARD=LVCMOS33;  # TP10_0
     75NET TP_A<11> LOC  = A14  | IOSTANDARD=LVCMOS33;  # TP11_0
    7376
    7477
    75 # LVDS Inputs
     78# Rate counter LVDS Inputs
    7679######################################################
    77 LVDS0_P  LOC  = Y4 | IOSTANDARD=LVCMOS33; # Patch 0
    78 LVDS0_N  LOC  = Y5 | IOSTANDARD=LVCMOS33;
     80# logic signal from first trigger patch
     81NET patch_A_p  LOC  = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P
     82NET patch_A_n  LOC  = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N
    7983
    80 LVDS1_P  LOC  = Y6 | IOSTANDARD=LVCMOS33; # Patch 1
    81 LVDS1_N  LOC  = Y7 | IOSTANDARD=LVCMOS33;
     84# logic signal from second trigger patch
     85NET patch_B_p  LOC  = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P
     86NET patch_B_n  LOC  = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N
    8287
    83 LVDS2_P  LOC  = Y17 | IOSTANDARD=LVCMOS33; # Patch 2
    84 LVDS2_N  LOC  = Y18 | IOSTANDARD=LVCMOS33;
     88# logic signal from third trigger patch
     89NET patch_C_p  LOC  = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P
     90NET patch_C_n  LOC  = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N
    8591
    86 LVDS3_P  LOC  = Y16 | IOSTANDARD=LVCMOS33; # Patch 3
    87 LVDS3_N  LOC  = W16 | IOSTANDARD=LVCMOS33;
     92# logic signal from fourth trigger patch
     93NET patch_D_p  LOC  = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P
     94NET patch_D_n  LOC  = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N
    8895
    89 TRG_P+   LOC  = Y13 | IOSTANDARD=LVCMOS33; #The Trigger Primitive
    90 TRG_P-   LOC  = W13 | IOSTANDARD=LVCMOS33;
    91 
    92 
    93 
     96#The Trigger Primitive: logic signal from n-out-of-4 circuit
     97NET trig_prim_p   LOC  = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+
     98NET trig_prim_n   LOC  = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P-
    9499
    95100
     
    97102######################################################
    98103# Patch 0
    99 XEN0_0   LOC  = D2 | IOSTANDARD=LVCMOS33;
    100 XEN0_1   LOC  = B1 | IOSTANDARD=LVCMOS33;
    101 XEN0_2   LOC  = C2 | IOSTANDARD=LVCMOS33;
    102 XEN0_3   LOC  = D1 | IOSTANDARD=LVCMOS33;
    103 XEN0_4   LOC  = C1 | IOSTANDARD=LVCMOS33;
    104 XEN0_5   LOC  = D4 | IOSTANDARD=LVCMOS33;
    105 XEN0_6   LOC  = E1 | IOSTANDARD=LVCMOS33;
    106 XEN0_7   LOC  = D3 | IOSTANDARD=LVCMOS33;
    107 XEN0_8   LOC  = E3 | IOSTANDARD=LVCMOS33;
     104NET enables_A<0>  LOC  = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0
     105NET enables_A<1>  LOC  = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1
     106NET enables_A<2>  LOC  = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2
     107NET enables_A<3>  LOC  = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3
     108NET enables_A<4>  LOC  = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4
     109NET enables_A<5>  LOC  = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5
     110NET enables_A<6>  LOC  = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6
     111NET enables_A<7>  LOC  = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7
     112NET enables_A<8>  LOC  = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8 
    108113
    109 # Patch 1
    110 XEN1_0   LOC  = F2 | IOSTANDARD=LVCMOS33;
    111 XEN1_1   LOC  = F4 | IOSTANDARD=LVCMOS33;
    112 XEN1_2   LOC  = F3 | IOSTANDARD=LVCMOS33;
    113 XEN1_3   LOC  = F1 | IOSTANDARD=LVCMOS33;
    114 XEN1_4   LOC  = G3 | IOSTANDARD=LVCMOS33;
    115 XEN1_5   LOC  = G4 | IOSTANDARD=LVCMOS33;
    116 XEN1_6   LOC  = H2 | IOSTANDARD=LVCMOS33;
    117 XEN1_7   LOC  = H3 | IOSTANDARD=LVCMOS33;
    118 XEN1_8   LOC  = J3 | IOSTANDARD=LVCMOS33;
     114## Patch 1
     115NET enables_B<0>  LOC  = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0
     116NET enables_B<1>  LOC  = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1
     117NET enables_B<2>  LOC  = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2
     118NET enables_B<3>  LOC  = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3
     119NET enables_B<4>  LOC  = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4
     120NET enables_B<5>  LOC  = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5
     121NET enables_B<6>  LOC  = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6
     122NET enables_B<7>  LOC  = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7
     123NET enables_B<8>  LOC  = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8
    119124
    120125# Patch 2
    121 XEN2_0   LOC  = N1 | IOSTANDARD=LVCMOS33;
    122 XEN2_1   LOC  = R1 | IOSTANDARD=LVCMOS33;
    123 XEN2_2   LOC  = M3 | IOSTANDARD=LVCMOS33;
    124 XEN2_3   LOC  = N2 | IOSTANDARD=LVCMOS33;
    125 XEN2_4   LOC  = P1 | IOSTANDARD=LVCMOS33;
    126 XEN2_5   LOC  = N3 | IOSTANDARD=LVCMOS33;
    127 XEN2_6   LOC  = R2 | IOSTANDARD=LVCMOS33;
    128 XEN2_7   LOC  = P3 | IOSTANDARD=LVCMOS33;
    129 XEN2_8   LOC  = T2 | IOSTANDARD=LVCMOS33;
     126NET enables_C<0>   LOC  = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0
     127NET enables_C<1>   LOC  = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1
     128NET enables_C<2>   LOC  = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2
     129NET enables_C<3>   LOC  = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3
     130NET enables_C<4>   LOC  = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4
     131NET enables_C<5>   LOC  = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5
     132NET enables_C<6>   LOC  = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6
     133NET enables_C<7>   LOC  = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7
     134NET enables_C<8>   LOC  = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8
    130135
    131136# Patch 3
    132 XEN2_0   LOC  = R3 | IOSTANDARD=LVCMOS33;
    133 XEN2_1   LOC  = T4 | IOSTANDARD=LVCMOS33;
    134 XEN2_2   LOC  = T3 | IOSTANDARD=LVCMOS33;
    135 XEN2_3   LOC  = U1 | IOSTANDARD=LVCMOS33;
    136 XEN2_4   LOC  = U3 | IOSTANDARD=LVCMOS33;
    137 XEN2_5   LOC  = V1 | IOSTANDARD=LVCMOS33;
    138 XEN2_6   LOC  = V2 | IOSTANDARD=LVCMOS33;
    139 XEN2_7   LOC  = W1 | IOSTANDARD=LVCMOS33;
    140 XEN2_8   LOC  = W2 | IOSTANDARD=LVCMOS33;
     137NET enables_D<0>   LOC  = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
     138NET enables_D<1>   LOC  = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
     139NET enables_D<2>   LOC  = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
     140NET enables_D<3>   LOC  = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
     141NET enables_D<4>   LOC  = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
     142NET enables_D<5>   LOC  = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
     143NET enables_D<6>   LOC  = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
     144NET enables_D<7>   LOC  = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
     145NET enables_D<8>   LOC  = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
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