Changeset 234 for FPGA/FTU/test_firmware/FTU_test1

Timestamp:

07/01/10 10:31:43 (15 years ago)

Author:

qweitzel

Message:

ucf file for FTU updated

Location:

FPGA/FTU/test_firmware/FTU_test1

Files:

• FTU_test1.vhd (modified) (3 diffs)
• FTU_test1_tb.vhd (modified) (1 diff)
• ftu_board_test1.ucf (added)

FPGA/FTU/test_firmware/FTU_test1/FTU_test1.vhd

@@ -34 +34 @@
     ext_clk   : IN  STD_LOGIC;                      -- external clock from FTU board
     --reset     : in  STD_LOGIC;                      -- reset
-    brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- global board address (not local)
-
+    brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- geographic board/slot address
+    brd_id    : IN  STD_LOGIC_VECTOR(7 downto 0);   -- local solder-programmable board ID
+    
     -- rate counters LVDS inputs
     -- use IBUFDS differential input buffer
@@ -108 +109 @@
     );
 
+  enables_A(0) <= enable_sig;
+  enables_A(1) <= enable_sig;
+  enables_A(2) <= enable_sig;
+  enables_A(3) <= enable_sig;
+  enables_A(4) <= enable_sig;
+  enables_A(5) <= enable_sig;
+  enables_A(6) <= enable_sig;
+  enables_A(7) <= enable_sig;
   enables_A(8) <= enable_sig;
+
+  enables_B(0) <= enable_sig;
+  enables_B(1) <= enable_sig;
+  enables_B(2) <= enable_sig;
+  enables_B(3) <= enable_sig;
+  enables_B(4) <= enable_sig;
+  enables_B(5) <= enable_sig;
+  enables_B(6) <= enable_sig;
+  enables_B(7) <= enable_sig;
   enables_B(8) <= enable_sig;
+
+  enables_C(0) <= enable_sig;
+  enables_C(1) <= enable_sig;
+  enables_C(2) <= enable_sig;
+  enables_C(3) <= enable_sig;
+  enables_C(4) <= enable_sig;
+  enables_C(5) <= enable_sig;
+  enables_C(6) <= enable_sig;
+  enables_C(7) <= enable_sig;
   enables_C(8) <= enable_sig;
+
+  enables_D(0) <= enable_sig;
+  enables_D(1) <= enable_sig;
+  enables_D(2) <= enable_sig;
+  enables_D(3) <= enable_sig;
+  enables_D(4) <= enable_sig;
+  enables_D(5) <= enable_sig;
+  enables_D(6) <= enable_sig;
+  enables_D(7) <= enable_sig;
   enables_D(8) <= enable_sig;
-
+  
 end Behavioral;
 
@@ -130 +166 @@
 architecture RTL of Clock_Divider is
   
-  constant max_count   : integer := 5000000/1000000; -- for simulation
-  --constant max_count   : integer := 5000000/1;   -- for implementation
-  constant final_count : integer := 3;
+  --constant max_count   : integer := 5000000/1000000; -- for simulation
+  constant max_count   : integer := 5000000/1;   -- for implementation
+  constant final_count : integer := 10;
   
 begin

FPGA/FTU/test_firmware/FTU_test1/FTU_test1_tb.vhd

@@ -43 +43 @@
       ext_clk   : IN  STD_LOGIC;                      -- external clock from FTU board
       --reset     : in  STD_LOGIC;                      -- reset
-      brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- global board address (not local) 
+      brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- geographic board/slot address
+      brd_id    : IN  STD_LOGIC_VECTOR(7 downto 0);   -- local solder-programmable address
 
       -- rate counters LVDS inputs