Index: /FPGA/FTU/FTU_top.vhd
===================================================================
--- /FPGA/FTU/FTU_top.vhd	(revision 233)
+++ /FPGA/FTU/FTU_top.vhd	(revision 234)
@@ -33,6 +33,7 @@
     -- global control 
     ext_clk   : IN  STD_LOGIC;                      -- external clock from FTU board
-    brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- global board address
-
+    brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- geographic board/slot address
+    brd_id    : in  STD_LOGIC_VECTOR(7 downto 0);   -- local solder-programmable board ID
+    
     -- rate counters LVDS inputs
     -- use IBUFDS differential input buffer
Index: /FPGA/FTU/FTU_top_tb.vhd
===================================================================
--- /FPGA/FTU/FTU_top_tb.vhd	(revision 233)
+++ /FPGA/FTU/FTU_top_tb.vhd	(revision 234)
@@ -42,6 +42,7 @@
       -- global control
       ext_clk   : IN  STD_LOGIC;                      -- external clock from FTU board
-      brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- global board address
-
+      brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- geographic board/slot address
+      brd_id    : in  STD_LOGIC_VECTOR(7 downto 0);   -- local solder-programmable board ID
+      
       -- rate counters LVDS inputs
       -- use IBUFDS differential input buffer
@@ -83,4 +84,5 @@
   signal ext_clk     : STD_LOGIC := '0';
   signal brd_add     : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
+  signal brd_id      : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
   signal patch_A_p   : STD_LOGIC := '0';
   signal patch_A_n   : STD_LOGIC := '0';
@@ -119,4 +121,5 @@
       ext_clk     => ext_clk,
       brd_add     => brd_add,
+      brd_id      => brd_id,
       patch_A_p   => patch_A_p,
       patch_A_n   => patch_A_n,
Index: /FPGA/FTU/ftu_board.ucf
===================================================================
--- /FPGA/FTU/ftu_board.ucf	(revision 233)
+++ /FPGA/FTU/ftu_board.ucf	(revision 234)
@@ -5,5 +5,6 @@
 # Pin location constraints
 #
-# by Patrick Vogler
+# by Patrick Vogler, Quirin Weitzel
+# 01 July 2010
 ########################################################
 
@@ -11,43 +12,45 @@
 #Clock
 #######################################################
-NET Clk LOC = Y11 | IOSTANDARD=LVCMOS33;		
+NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk	
 
 
 # RS-485 Interface
 #######################################################
-NET 485_RE LOC  = T20 | IOSTANDARD=LVCMOS33;		
-NET 485_DE LOC  = U20 | IOSTANDARD=LVCMOS33;		
-NET 485_DO LOC  = U19 | IOSTANDARD=LVCMOS33;		
-NET 485_DI LOC  = R20 | IOSTANDARD=LVCMOS33;		
+NET rx_en LOC  = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver		
+NET tx_en LOC  = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter		
+NET tx    LOC  = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM		
+NET rx    LOC  = R20 | IOSTANDARD=LVCMOS33;               # 485_DI: serial data from FTM
 
 
-# Board ID  - inputs
+# Board ID - inputs 
+# local board-ID "solder programmable"
 #######################################################
-NET P0 LOC  = C4 | IOSTANDARD=LVCMOS33;		
-NET P1 LOC  = C5 | IOSTANDARD=LVCMOS33;		
-NET P2 LOC  = C6 | IOSTANDARD=LVCMOS33;		
-NET P3 LOC  = C7 | IOSTANDARD=LVCMOS33;		
-NET P4 LOC  = C8 | IOSTANDARD=LVCMOS33;		
-NET P5 LOC  = B8 | IOSTANDARD=LVCMOS33;		
-NET P6 LOC  = C9 | IOSTANDARD=LVCMOS33;	
-NET P7 LOC  = B9 | IOSTANDARD=LVCMOS33;	
+NET brd_id<0> LOC  = C4 | IOSTANDARD=LVCMOS33; # P0		
+NET brd_id<1> LOC  = C5 | IOSTANDARD=LVCMOS33; # P1		
+NET brd_id<2> LOC  = C6 | IOSTANDARD=LVCMOS33; # P2		
+NET brd_id<3> LOC  = C7 | IOSTANDARD=LVCMOS33; # P3		
+NET brd_id<4> LOC  = C8 | IOSTANDARD=LVCMOS33; # P4		
+NET brd_id<5> LOC  = B8 | IOSTANDARD=LVCMOS33; # P5		
+NET brd_id<6> LOC  = C9 | IOSTANDARD=LVCMOS33; # P6	
+NET brd_id<7> LOC  = B9 | IOSTANDARD=LVCMOS33; # P7	
 
 
 # Board Addresses
+# geographical slot address
 #######################################################
-NET ADDR0 LOC  = A15 | IOSTANDARD=LVCMOS33;
-NET ADDR1 LOC  = B15 | IOSTANDARD=LVCMOS33;
-NET ADDR2 LOC  = A16 | IOSTANDARD=LVCMOS33;
-NET ADDR3 LOC  = A17 | IOSTANDARD=LVCMOS33;
-NET ADDR4 LOC  = A18 | IOSTANDARD=LVCMOS33;
-NET ADDR5 LOC  = B18 | IOSTANDARD=LVCMOS33;
+NET brd_add<0> LOC  = A15 | IOSTANDARD=LVCMOS33; # ADDR0
+NET brd_add<1> LOC  = B15 | IOSTANDARD=LVCMOS33; # ADDR1
+NET brd_add<2> LOC  = A16 | IOSTANDARD=LVCMOS33; # ADDR2
+NET brd_add<3> LOC  = A17 | IOSTANDARD=LVCMOS33; # ADDR3
+NET brd_add<4> LOC  = A18 | IOSTANDARD=LVCMOS33; # ADDR4
+NET brd_add<5> LOC  = B18 | IOSTANDARD=LVCMOS33; # ADDR5
 
 
 # DAC SPI Interface
 #######################################################
-NET MOSI LOC  = E20 | IOSTANDARD=LVCMOS33;			
-NET SCK LOC  = E19 | IOSTANDARD=LVCMOS33;			
-NET DAC_CS LOC  = E18 | IOSTANDARD=LVCMOS33;			
-NET DAC_CRL LOC  = D20 | IOSTANDARD=LVCMOS33;			
+NET mosi   LOC  = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in 		
+NET sck    LOC  = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC			
+NET cs_ld  LOC  = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC			
+NET clr    LOC  = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC	
 
 
@@ -55,41 +58,43 @@
 ######################################################
 # on Connector J5
-NET TP0_0 LOC  = B3 | IOSTANDARD=LVCMOS33;
-NET TP1_0 LOC  = A3 | IOSTANDARD=LVCMOS33;
-NET TP2_0 LOC  = A4 | IOSTANDARD=LVCMOS33;
-NET TP3_0 LOC  = B5 | IOSTANDARD=LVCMOS33;
+NET TP_A<0> LOC  = B3 | IOSTANDARD=LVCMOS33;  # TP0_0
+NET TP_A<1> LOC  = A3 | IOSTANDARD=LVCMOS33;  # TP1_0
+NET TP_A<2> LOC  = A4 | IOSTANDARD=LVCMOS33;  # TP2_0
+NET TP_A<3> LOC  = B5 | IOSTANDARD=LVCMOS33;  # TP2_0
 
 # on Connector J6
-NET TP4_0 LOC  = A5 | IOSTANDARD=LVCMOS33;
-NET TP5_0 LOC  = A6 | IOSTANDARD=LVCMOS33;
-NET TP6_0 LOC  = B7 | IOSTANDARD=LVCMOS33;
-NET TP7_0 LOC  = A7 | IOSTANDARD=LVCMOS33;
+NET TP_A<4> LOC  = A5 | IOSTANDARD=LVCMOS33;  # TP4_0
+NET TP_A<5> LOC  = A6 | IOSTANDARD=LVCMOS33;  # TP5_0
+NET TP_A<6> LOC  = B7 | IOSTANDARD=LVCMOS33;  # TP6_0
+NET TP_A<7> LOC  = A7 | IOSTANDARD=LVCMOS33;  # TP7_0
 
 # on Connector J7
-NET TP8_0 LOC  = B11  | IOSTANDARD=LVCMOS33;
-NET TP9_0 LOC  = A12  | IOSTANDARD=LVCMOS33;
-NET TP10_0 LOC  = B12 | IOSTANDARD=LVCMOS33;
-NET TP11_0 LOC  = A14 | IOSTANDARD=LVCMOS33;
+NET TP_A<8>  LOC  = B11  | IOSTANDARD=LVCMOS33;  # TP8_0
+NET TP_A<9>  LOC  = A12  | IOSTANDARD=LVCMOS33;  # TP9_0
+NET TP_A<10> LOC  = B12  | IOSTANDARD=LVCMOS33;  # TP10_0
+NET TP_A<11> LOC  = A14  | IOSTANDARD=LVCMOS33;  # TP11_0
 
 
-# LVDS Inputs
+# Rate counter LVDS Inputs
 ######################################################
-LVDS0_P  LOC  = Y4 | IOSTANDARD=LVCMOS33; # Patch 0
-LVDS0_N  LOC  = Y5 | IOSTANDARD=LVCMOS33;
+# logic signal from first trigger patch
+NET patch_A_p  LOC  = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P
+NET patch_A_n  LOC  = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N
 
-LVDS1_P  LOC  = Y6 | IOSTANDARD=LVCMOS33; # Patch 1
-LVDS1_N  LOC  = Y7 | IOSTANDARD=LVCMOS33;
+# logic signal from second trigger patch
+NET patch_B_p  LOC  = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P
+NET patch_B_n  LOC  = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N
 
-LVDS2_P  LOC  = Y17 | IOSTANDARD=LVCMOS33; # Patch 2
-LVDS2_N  LOC  = Y18 | IOSTANDARD=LVCMOS33;
+# logic signal from third trigger patch
+NET patch_C_p  LOC  = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P
+NET patch_C_n  LOC  = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N
 
-LVDS3_P  LOC  = Y16 | IOSTANDARD=LVCMOS33; # Patch 3
-LVDS3_N  LOC  = W16 | IOSTANDARD=LVCMOS33;
+# logic signal from fourth trigger patch
+NET patch_D_p  LOC  = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P
+NET patch_D_n  LOC  = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N
 
-TRG_P+   LOC  = Y13 | IOSTANDARD=LVCMOS33; #The Trigger Primitive
-TRG_P-   LOC  = W13 | IOSTANDARD=LVCMOS33;
-
-
-
+#The Trigger Primitive: logic signal from n-out-of-4 circuit
+NET trig_prim_p   LOC  = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+
+NET trig_prim_n   LOC  = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P-
 
 
@@ -97,44 +102,44 @@
 ######################################################
 # Patch 0
-XEN0_0   LOC  = D2 | IOSTANDARD=LVCMOS33;
-XEN0_1   LOC  = B1 | IOSTANDARD=LVCMOS33;
-XEN0_2   LOC  = C2 | IOSTANDARD=LVCMOS33;
-XEN0_3   LOC  = D1 | IOSTANDARD=LVCMOS33;
-XEN0_4   LOC  = C1 | IOSTANDARD=LVCMOS33;
-XEN0_5   LOC  = D4 | IOSTANDARD=LVCMOS33;
-XEN0_6   LOC  = E1 | IOSTANDARD=LVCMOS33;
-XEN0_7   LOC  = D3 | IOSTANDARD=LVCMOS33;
-XEN0_8   LOC  = E3 | IOSTANDARD=LVCMOS33;
+NET enables_A<0>  LOC  = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 
+NET enables_A<1>  LOC  = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1
+NET enables_A<2>  LOC  = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2
+NET enables_A<3>  LOC  = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3
+NET enables_A<4>  LOC  = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4
+NET enables_A<5>  LOC  = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5
+NET enables_A<6>  LOC  = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6
+NET enables_A<7>  LOC  = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7 
+NET enables_A<8>  LOC  = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8  
 
-# Patch 1
-XEN1_0   LOC  = F2 | IOSTANDARD=LVCMOS33;
-XEN1_1   LOC  = F4 | IOSTANDARD=LVCMOS33;
-XEN1_2   LOC  = F3 | IOSTANDARD=LVCMOS33;
-XEN1_3   LOC  = F1 | IOSTANDARD=LVCMOS33;
-XEN1_4   LOC  = G3 | IOSTANDARD=LVCMOS33;
-XEN1_5   LOC  = G4 | IOSTANDARD=LVCMOS33;
-XEN1_6   LOC  = H2 | IOSTANDARD=LVCMOS33;
-XEN1_7   LOC  = H3 | IOSTANDARD=LVCMOS33;
-XEN1_8   LOC  = J3 | IOSTANDARD=LVCMOS33;
+## Patch 1
+NET enables_B<0>  LOC  = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0
+NET enables_B<1>  LOC  = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1
+NET enables_B<2>  LOC  = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2
+NET enables_B<3>  LOC  = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3
+NET enables_B<4>  LOC  = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4
+NET enables_B<5>  LOC  = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5
+NET enables_B<6>  LOC  = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6
+NET enables_B<7>  LOC  = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7
+NET enables_B<8>  LOC  = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8
 
 # Patch 2
-XEN2_0   LOC  = N1 | IOSTANDARD=LVCMOS33;
-XEN2_1   LOC  = R1 | IOSTANDARD=LVCMOS33;
-XEN2_2   LOC  = M3 | IOSTANDARD=LVCMOS33;
-XEN2_3   LOC  = N2 | IOSTANDARD=LVCMOS33;
-XEN2_4   LOC  = P1 | IOSTANDARD=LVCMOS33;
-XEN2_5   LOC  = N3 | IOSTANDARD=LVCMOS33;
-XEN2_6   LOC  = R2 | IOSTANDARD=LVCMOS33;
-XEN2_7   LOC  = P3 | IOSTANDARD=LVCMOS33;
-XEN2_8   LOC  = T2 | IOSTANDARD=LVCMOS33;
+NET enables_C<0>   LOC  = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0
+NET enables_C<1>   LOC  = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1
+NET enables_C<2>   LOC  = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2
+NET enables_C<3>   LOC  = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3
+NET enables_C<4>   LOC  = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4
+NET enables_C<5>   LOC  = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5
+NET enables_C<6>   LOC  = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6
+NET enables_C<7>   LOC  = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7
+NET enables_C<8>   LOC  = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8
 
 # Patch 3
-XEN2_0   LOC  = R3 | IOSTANDARD=LVCMOS33;
-XEN2_1   LOC  = T4 | IOSTANDARD=LVCMOS33;
-XEN2_2   LOC  = T3 | IOSTANDARD=LVCMOS33;
-XEN2_3   LOC  = U1 | IOSTANDARD=LVCMOS33;
-XEN2_4   LOC  = U3 | IOSTANDARD=LVCMOS33;
-XEN2_5   LOC  = V1 | IOSTANDARD=LVCMOS33;
-XEN2_6   LOC  = V2 | IOSTANDARD=LVCMOS33;
-XEN2_7   LOC  = W1 | IOSTANDARD=LVCMOS33;
-XEN2_8   LOC  = W2 | IOSTANDARD=LVCMOS33;
+NET enables_D<0>   LOC  = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<1>   LOC  = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<2>   LOC  = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<3>   LOC  = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<4>   LOC  = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<5>   LOC  = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<6>   LOC  = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<7>   LOC  = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<8>   LOC  = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
Index: /FPGA/FTU/test_firmware/FTU_test1/FTU_test1.vhd
===================================================================
--- /FPGA/FTU/test_firmware/FTU_test1/FTU_test1.vhd	(revision 233)
+++ /FPGA/FTU/test_firmware/FTU_test1/FTU_test1.vhd	(revision 234)
@@ -34,6 +34,7 @@
     ext_clk   : IN  STD_LOGIC;                      -- external clock from FTU board
     --reset     : in  STD_LOGIC;                      -- reset
-    brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- global board address (not local)
-
+    brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- geographic board/slot address
+    brd_id    : IN  STD_LOGIC_VECTOR(7 downto 0);   -- local solder-programmable board ID
+    
     -- rate counters LVDS inputs
     -- use IBUFDS differential input buffer
@@ -108,9 +109,44 @@
     );
 
+  enables_A(0) <= enable_sig;
+  enables_A(1) <= enable_sig;
+  enables_A(2) <= enable_sig;
+  enables_A(3) <= enable_sig;
+  enables_A(4) <= enable_sig;
+  enables_A(5) <= enable_sig;
+  enables_A(6) <= enable_sig;
+  enables_A(7) <= enable_sig;
   enables_A(8) <= enable_sig;
+
+  enables_B(0) <= enable_sig;
+  enables_B(1) <= enable_sig;
+  enables_B(2) <= enable_sig;
+  enables_B(3) <= enable_sig;
+  enables_B(4) <= enable_sig;
+  enables_B(5) <= enable_sig;
+  enables_B(6) <= enable_sig;
+  enables_B(7) <= enable_sig;
   enables_B(8) <= enable_sig;
+
+  enables_C(0) <= enable_sig;
+  enables_C(1) <= enable_sig;
+  enables_C(2) <= enable_sig;
+  enables_C(3) <= enable_sig;
+  enables_C(4) <= enable_sig;
+  enables_C(5) <= enable_sig;
+  enables_C(6) <= enable_sig;
+  enables_C(7) <= enable_sig;
   enables_C(8) <= enable_sig;
+
+  enables_D(0) <= enable_sig;
+  enables_D(1) <= enable_sig;
+  enables_D(2) <= enable_sig;
+  enables_D(3) <= enable_sig;
+  enables_D(4) <= enable_sig;
+  enables_D(5) <= enable_sig;
+  enables_D(6) <= enable_sig;
+  enables_D(7) <= enable_sig;
   enables_D(8) <= enable_sig;
-
+  
 end Behavioral;
 
@@ -130,7 +166,7 @@
 architecture RTL of Clock_Divider is
   
-  constant max_count   : integer := 5000000/1000000; -- for simulation
-  --constant max_count   : integer := 5000000/1;   -- for implementation
-  constant final_count : integer := 3;
+  --constant max_count   : integer := 5000000/1000000; -- for simulation
+  constant max_count   : integer := 5000000/1;   -- for implementation
+  constant final_count : integer := 10;
   
 begin
Index: /FPGA/FTU/test_firmware/FTU_test1/FTU_test1_tb.vhd
===================================================================
--- /FPGA/FTU/test_firmware/FTU_test1/FTU_test1_tb.vhd	(revision 233)
+++ /FPGA/FTU/test_firmware/FTU_test1/FTU_test1_tb.vhd	(revision 234)
@@ -43,5 +43,6 @@
       ext_clk   : IN  STD_LOGIC;                      -- external clock from FTU board
       --reset     : in  STD_LOGIC;                      -- reset
-      brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- global board address (not local) 
+      brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- geographic board/slot address
+      brd_id    : IN  STD_LOGIC_VECTOR(7 downto 0);   -- local solder-programmable address
 
       -- rate counters LVDS inputs
Index: /FPGA/FTU/test_firmware/FTU_test1/ftu_board_test1.ucf
===================================================================
--- /FPGA/FTU/test_firmware/FTU_test1/ftu_board_test1.ucf	(revision 234)
+++ /FPGA/FTU/test_firmware/FTU_test1/ftu_board_test1.ucf	(revision 234)
@@ -0,0 +1,145 @@
+########################################################
+# FTU Board 
+# FACT Trigger Unit
+#
+# Pin location constraints
+#
+# by Patrick Vogler, Quirin Weitzel
+# 01 July 2010
+########################################################
+
+
+#Clock
+#######################################################
+NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk	
+
+
+# RS-485 Interface
+#######################################################
+#NET rx_en LOC  = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver		
+#NET tx_en LOC  = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter		
+#NET tx    LOC  = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM		
+#NET rx    LOC  = R20 | IOSTANDARD=LVCMOS33;               # 485_DI: serial data from FTM
+
+
+# Board ID - inputs 
+# local board-ID "solder programmable"
+#######################################################
+#NET brd_id<0> LOC  = C4 | IOSTANDARD=LVCMOS33; # P0		
+#NET brd_id<1> LOC  = C5 | IOSTANDARD=LVCMOS33; # P1		
+#NET brd_id<2> LOC  = C6 | IOSTANDARD=LVCMOS33; # P2		
+#NET brd_id<3> LOC  = C7 | IOSTANDARD=LVCMOS33; # P3		
+#NET brd_id<4> LOC  = C8 | IOSTANDARD=LVCMOS33; # P4		
+#NET brd_id<5> LOC  = B8 | IOSTANDARD=LVCMOS33; # P5		
+#NET brd_id<6> LOC  = C9 | IOSTANDARD=LVCMOS33; # P6	
+#NET brd_id<7> LOC  = B9 | IOSTANDARD=LVCMOS33; # P7	
+
+
+# Board Addresses
+# geographical slot address
+#######################################################
+#NET brd_add<0> LOC  = A15 | IOSTANDARD=LVCMOS33; # ADDR0
+#NET brd_add<1> LOC  = B15 | IOSTANDARD=LVCMOS33; # ADDR1
+#NET brd_add<2> LOC  = A16 | IOSTANDARD=LVCMOS33; # ADDR2
+#NET brd_add<3> LOC  = A17 | IOSTANDARD=LVCMOS33; # ADDR3
+#NET brd_add<4> LOC  = A18 | IOSTANDARD=LVCMOS33; # ADDR4
+#NET brd_add<5> LOC  = B18 | IOSTANDARD=LVCMOS33; # ADDR5
+
+
+# DAC SPI Interface
+#######################################################
+#NET mosi   LOC  = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in 		
+#NET sck    LOC  = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC			
+#NET cs_ld  LOC  = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC			
+#NET clr    LOC  = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC	
+
+
+# Testpoints
+######################################################
+# on Connector J5
+#NET TP_A<0> LOC  = B3 | IOSTANDARD=LVCMOS33;  # TP0_0
+#NET TP_A<1> LOC  = A3 | IOSTANDARD=LVCMOS33;  # TP1_0
+#NET TP_A<2> LOC  = A4 | IOSTANDARD=LVCMOS33;  # TP2_0
+#NET TP_A<3> LOC  = B5 | IOSTANDARD=LVCMOS33;  # TP2_0
+
+# on Connector J6
+#NET TP_A<4> LOC  = A5 | IOSTANDARD=LVCMOS33;  # TP4_0
+#NET TP_A<5> LOC  = A6 | IOSTANDARD=LVCMOS33;  # TP5_0
+#NET TP_A<6> LOC  = B7 | IOSTANDARD=LVCMOS33;  # TP6_0
+#NET TP_A<7> LOC  = A7 | IOSTANDARD=LVCMOS33;  # TP7_0
+
+# on Connector J7
+#NET TP_A<8>  LOC  = B11  | IOSTANDARD=LVCMOS33;  # TP8_0
+#NET TP_A<9>  LOC  = A12  | IOSTANDARD=LVCMOS33;  # TP9_0
+#NET TP_A<10> LOC  = B12  | IOSTANDARD=LVCMOS33;  # TP10_0
+#NET TP_A<11> LOC  = A14  | IOSTANDARD=LVCMOS33;  # TP11_0
+
+
+# Rate counter LVDS Inputs
+######################################################
+# logic signal from first trigger patch
+#NET patch_A_p  LOC  = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P
+#NET patch_A_n  LOC  = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N
+
+# logic signal from second trigger patch
+#NET patch_B_p  LOC  = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P
+#NET patch_B_n  LOC  = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N
+
+# logic signal from third trigger patch
+#NET patch_C_p  LOC  = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P
+#NET patch_C_n  LOC  = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N
+
+# logic signal from fourth trigger patch
+#NET patch_D_p  LOC  = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P
+#NET patch_D_n  LOC  = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N
+
+#The Trigger Primitive: logic signal from n-out-of-4 circuit
+#NET trig_prim_p   LOC  = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+
+#NET trig_prim_n   LOC  = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P-
+
+
+# Enables 
+######################################################
+# Patch 0
+NET enables_A<0>  LOC  = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 
+NET enables_A<1>  LOC  = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1
+NET enables_A<2>  LOC  = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2
+NET enables_A<3>  LOC  = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3
+NET enables_A<4>  LOC  = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4
+NET enables_A<5>  LOC  = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5
+NET enables_A<6>  LOC  = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6
+NET enables_A<7>  LOC  = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7 
+NET enables_A<8>  LOC  = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8  
+
+## Patch 1
+NET enables_B<0>  LOC  = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0
+NET enables_B<1>  LOC  = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1
+NET enables_B<2>  LOC  = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2
+NET enables_B<3>  LOC  = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3
+NET enables_B<4>  LOC  = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4
+NET enables_B<5>  LOC  = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5
+NET enables_B<6>  LOC  = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6
+NET enables_B<7>  LOC  = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7
+NET enables_B<8>  LOC  = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8
+
+# Patch 2
+NET enables_C<0>   LOC  = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0
+NET enables_C<1>   LOC  = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1
+NET enables_C<2>   LOC  = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2
+NET enables_C<3>   LOC  = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3
+NET enables_C<4>   LOC  = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4
+NET enables_C<5>   LOC  = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5
+NET enables_C<6>   LOC  = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6
+NET enables_C<7>   LOC  = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7
+NET enables_C<8>   LOC  = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8
+
+# Patch 3
+NET enables_D<0>   LOC  = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<1>   LOC  = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<2>   LOC  = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<3>   LOC  = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<4>   LOC  = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<5>   LOC  = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<6>   LOC  = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<7>   LOC  = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<8>   LOC  = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0