- Timestamp:
- 07/02/10 17:47:20 (14 years ago)
- File:
-
- 1 edited
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FPGA/FTU/test_firmware/FTU_test1/FTU_test1_tb.vhd
r234 r235 87 87 --signal reset : STD_LOGIC := '0'; 88 88 signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); 89 signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 89 90 signal patch_A_p : STD_LOGIC := '0'; 90 91 signal patch_A_n : STD_LOGIC := '0'; … … 125 126 --reset => reset, 126 127 brd_add => brd_add, 128 brd_id => brd_id, 127 129 patch_A_p => patch_A_p, 128 130 patch_A_n => patch_A_n,
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