- Timestamp:
- 07/06/10 13:52:54 (14 years ago)
- File:
-
- 1 edited
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FPGA/FTU/test_firmware/FTU_test3/FTU_test3.vhd
r239 r240 91 91 Inst_FTU_test3_dcm : FTU_test3_dcm 92 92 port map( 93 CLKIN_IN => ext_clk ,93 CLKIN_IN => ext_clk_sig, 94 94 CLKFX_OUT => clk_5M_sig, 95 95 CLKIN_IBUFG_OUT => open … … 98 98 ext_clk_sig <= ext_clk; 99 99 100 sck <= ext_clk_sig;100 sck <= clk_5M_sig; 101 101 mosi <= clk_5M_sig; 102 102 cs_ld <= clk_5M_sig;
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