Index: FPGA/FTU/test_firmware/FTU_test2/FTU_test2.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test2/FTU_test2.vhd	(revision 237)
+++ FPGA/FTU/test_firmware/FTU_test2/FTU_test2.vhd	(revision 241)
@@ -92,5 +92,8 @@
       mosi     : OUT STD_LOGIC;
       sck      : OUT STD_LOGIC;
-      cs_ld    : OUT STD_LOGIC
+      cs_ld    : OUT STD_LOGIC;
+      enable1  : out STD_LOGIC;
+      enable2  : out STD_LOGIC;
+      enable3  : out STD_LOGIC
     );
   end component;
@@ -115,10 +118,13 @@
   Inst_FTU_test2_dac_control : FTU_test2_dac_control
     port map(
-      clk   => clk_50M_sig,
-      reset => reset_sig,
-      clr   => clr,
-      mosi  => mosi,
-      sck   => sck,
-      cs_ld => cs_ld
+      clk     => clk_50M_sig,
+      reset   => reset_sig,
+      clr     => clr,
+      mosi    => mosi,
+      sck     => sck,
+      cs_ld   => cs_ld,
+      enable1 => enables_A(1),
+      enable2 => enables_A(2),
+      enable3 => enables_A(3)
     );
 
@@ -138,4 +144,5 @@
       when Running =>
         reset_sig <= '0';
+        enables_A(0) <= '1';
     end case;
   end process FTU_test2_C_logic;