Index: FPGA/FTU/test_firmware/FTU_test2/FTU_test2.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test2/FTU_test2.vhd	(revision 240)
+++ FPGA/FTU/test_firmware/FTU_test2/FTU_test2.vhd	(revision 241)
@@ -92,5 +92,8 @@
       mosi     : OUT STD_LOGIC;
       sck      : OUT STD_LOGIC;
-      cs_ld    : OUT STD_LOGIC
+      cs_ld    : OUT STD_LOGIC;
+      enable1  : out STD_LOGIC;
+      enable2  : out STD_LOGIC;
+      enable3  : out STD_LOGIC
     );
   end component;
@@ -115,10 +118,13 @@
   Inst_FTU_test2_dac_control : FTU_test2_dac_control
     port map(
-      clk   => clk_50M_sig,
-      reset => reset_sig,
-      clr   => clr,
-      mosi  => mosi,
-      sck   => sck,
-      cs_ld => cs_ld
+      clk     => clk_50M_sig,
+      reset   => reset_sig,
+      clr     => clr,
+      mosi    => mosi,
+      sck     => sck,
+      cs_ld   => cs_ld,
+      enable1 => enables_A(1),
+      enable2 => enables_A(2),
+      enable3 => enables_A(3)
     );
 
@@ -138,4 +144,5 @@
       when Running =>
         reset_sig <= '0';
+        enables_A(0) <= '1';
     end case;
   end process FTU_test2_C_logic;
Index: FPGA/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd	(revision 240)
+++ FPGA/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd	(revision 241)
@@ -37,5 +37,8 @@
     mosi     : OUT    STD_LOGIC;
     sck      : OUT    STD_LOGIC;
-    cs_ld    : out    STD_LOGIC
+    cs_ld    : out    STD_LOGIC;
+    enable1  : out    STD_LOGIC;
+    enable2  : out    STD_LOGIC;
+    enable3  : out    STD_LOGIC
   );
 end FTU_test2_dac_control;
@@ -114,13 +117,22 @@
       when START =>
         config_start_sig <= '1';
-        next_state <= WAITING;
+        enable1 <= '1';
+        enable2 <= '0';
+        enable3 <= '0';
+        next_state <= WAITING;        
       when WAITING =>
-        if (config_ready_sig = '1') then
-          next_state <= STOP;
+        enable1 <= '0';
+        enable2 <= '1';
+        enable3 <= '0';
+        if (config_ready_sig = '1') then          
+          next_state <= STOP;          
         else
           next_state <= WAITING;
         end if;
       when STOP =>
-        config_start_sig <= '0';
+        enable1 <= '0';
+        enable2 <= '0';
+        enable3 <= '1';
+        config_start_sig <= '0';        
     end case;
   end process;
Index: FPGA/FTU/test_firmware/FTU_test2/ftu_board_test2.ucf
===================================================================
--- FPGA/FTU/test_firmware/FTU_test2/ftu_board_test2.ucf	(revision 240)
+++ FPGA/FTU/test_firmware/FTU_test2/ftu_board_test2.ucf	(revision 241)
@@ -102,8 +102,8 @@
 ######################################################
 # Patch 0
-#NET enables_A<0>  LOC  = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 
-#NET enables_A<1>  LOC  = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1
-#NET enables_A<2>  LOC  = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2
-#NET enables_A<3>  LOC  = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3
+NET enables_A<0>  LOC  = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 
+NET enables_A<1>  LOC  = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1
+NET enables_A<2>  LOC  = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2
+NET enables_A<3>  LOC  = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3
 #NET enables_A<4>  LOC  = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4
 #NET enables_A<5>  LOC  = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5