Index: FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_controller.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_controller.vhd	(revision 241)
+++ FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_controller.vhd	(revision 242)
@@ -19,5 +19,6 @@
       mosi         : OUT    std_logic := '0';
       dac_id       : IN     std_logic_vector (2 DOWNTO 0);
-      data         : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z');
+      --data         : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z');
+      data         : IN  std_logic_vector (15 DOWNTO 0) := (others => '0');
       dac_cs       : OUT    std_logic := '1';
       dac_start    : IN     std_logic;
@@ -43,5 +44,5 @@
       miso <= 'Z';
       mosi <= '0';
-      data <= (others => 'Z');
+      --data <= (others => 'Z');
       case spi_state is
         when SPI_IDLE =>
Index: FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_distributor.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_distributor.vhd	(revision 241)
+++ FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_distributor.vhd	(revision 242)
@@ -26,5 +26,6 @@
     dac_config_ready  : IN    std_logic;
     dac_id            : OUT   std_logic_vector(2 downto 0) := (others => '0');
-    data              : INOUT std_logic_vector(15 downto 0) := (others => 'Z')
+    --data              : INOUT std_logic_vector(15 downto 0) := (others => 'Z')
+    data              : OUT std_logic_vector(15 downto 0) := (others => '0')
   );
 END ENTITY FTU_test2_spi_distributor;
@@ -36,4 +37,5 @@
   signal spi_distr_state       : TYPE_SPI_DISTRIBUTION_STATE := INIT;
   signal dac_id_cnt            : integer range 0 to 4 := 0;
+  signal wait_cnt              : integer range 0 to 3 := 0;
   
 BEGIN
@@ -43,11 +45,19 @@
     
     if rising_edge(clk) then
-      data <= (others => 'Z');
+      --data <= (others => 'Z');
+      data <= (others => '0');
       case spi_distr_state is
         when INIT =>
-          data <= (others => 'Z');
-          spi_distr_state <= IDLE;
+          --data <= (others => 'Z');
+          data <= (others => '0');
+          if wait_cnt < 3 then
+            wait_cnt <= wait_cnt + 1;
+            spi_distr_state <= INIT;
+          else
+            spi_distr_state <= IDLE;
+          end if;
         when IDLE =>
-          data <= (others => 'Z');
+          --data <= (others => 'Z');
+          data <= (others => '0');
          -- start DAC configuration
           if (config_start = '1') then
@@ -56,5 +66,5 @@
             dac_config_start <= '1';
             dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length);
-            data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length);
+            data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length);          
             spi_distr_state <= CONFIG_DAC;
           end if;
Index: FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_interface.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_interface.vhd	(revision 241)
+++ FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_interface.vhd	(revision 242)
@@ -75,5 +75,6 @@
       dac_ready    : OUT    std_logic                      := '0';
       mosi         : OUT    std_logic                      := '0';
-      data         : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z');
+      --data         : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z');
+      data         : IN  std_logic_vector (15 DOWNTO 0) := (others => '0');
       miso         : INOUT  std_logic                      := 'Z'
    );
@@ -90,5 +91,6 @@
       dac_config_start  : OUT    std_logic                      := '0';
       dac_id            : OUT    std_logic_vector (2 DOWNTO 0)  := (others => '0');
-      data              : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z')
+      --data              : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z')
+      data              : OUT  std_logic_vector (15 DOWNTO 0) := (others => '0')
    );
    END COMPONENT;