Index: FPGA/FTU/test_firmware/FTU_test2/FTU_test2.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test2/FTU_test2.vhd	(revision 242)
+++ FPGA/FTU/test_firmware/FTU_test2/FTU_test2.vhd	(revision 243)
@@ -3,5 +3,5 @@
 -- Engineer:       P. Vogler, Q. Weitzel
 -- 
--- Create Date:    05/17/2010 
+-- Create Date:    05/07/2010 
 -- Design Name:    
 -- Module Name:    FTU_test2 - Behavioral 
Index: FPGA/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd	(revision 242)
+++ FPGA/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd	(revision 243)
@@ -3,5 +3,5 @@
 -- Engineer:       P. Vogler, Q. Weitzel
 -- 
--- Create Date:    05/17/2010 
+-- Create Date:    05/07/2010 
 -- Design Name: 
 -- Module Name:    FTU_test2_dac_control - Behavioral 
@@ -60,13 +60,4 @@
   end component;
 
-  --component FTU_test2_upcnt16
-  --  port(
-  --    full  : out STD_LOGIC;
-  --    clr   : in STD_LOGIC;
-  --    reset : in STD_Logic;
-  --    clk   : in STD_LOGIC
-  --  );
-  --end component;
-  
   signal clk_sig            : std_logic;
   signal reset_sig          : std_logic;
@@ -81,17 +72,13 @@
   signal config_started_sig : std_logic := '0';
   signal dac_array_sig      : dac_array_type := (100,200,300,400,500);
-    
-  --signal full_sig           : std_logic;
-  --signal clr_wcnt_sig       : std_logic;
-    
+ 
   -- Build an enumerated type for the state machine
   type state_type is (START, WAITING, STOP);
 
   -- Register to hold the current state
-  signal state, next_state: state_type;
+  signal state, next_state : state_type;
   
 begin
 
-  --to be checked
   reset_sig <= reset;
   clk_sig <= clk;
@@ -122,4 +109,5 @@
         next_state <= WAITING;        
       when WAITING =>
+        config_start_sig <= '1';
         enable1 <= '0';
         enable2 <= '1';
@@ -134,5 +122,5 @@
         enable2 <= '0';
         enable3 <= '1';
-        config_start_sig <= '0';        
+        config_start_sig <= '0';
     end case;
   end process;
@@ -151,12 +139,4 @@
     );
 
-  --Inst_FTU_test2_upcnt16: FTU_test2_upcnt16
-  --  port map(
-  --    full  => full_sig,
-  --    clr   => clr_wcnt_sig,
-  --    reset => reset_sig,
-  --    clk   => serial_clock_sig
-  --  );
-  
 end Behavioral;
 
Index: FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_controller.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_controller.vhd	(revision 242)
+++ FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_controller.vhd	(revision 243)
@@ -7,4 +7,6 @@
 --
 -- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
+--
+-- modified by Q. Weitzel
 --
 LIBRARY ieee;
@@ -55,5 +57,5 @@
           spi_cycle_cnt <= 0;   
             if (dac_start = '1') then
-              shift_reg <= "0011" & '0' & dac_id & data;
+              shift_reg <= "0011" & '0' & dac_id & data(11 downto 0) & "0000";
               spi_state <= SPI_LOAD_DAC;
             end if;
Index: FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_distributor.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_distributor.vhd	(revision 242)
+++ FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_distributor.vhd	(revision 243)
@@ -8,5 +8,6 @@
 -- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
 --
-
+-- modified by Q. Weitzel
+--
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;
@@ -37,5 +38,4 @@
   signal spi_distr_state       : TYPE_SPI_DISTRIBUTION_STATE := INIT;
   signal dac_id_cnt            : integer range 0 to 4 := 0;
-  signal wait_cnt              : integer range 0 to 3 := 0;
   
 BEGIN
@@ -51,10 +51,5 @@
           --data <= (others => 'Z');
           data <= (others => '0');
-          if wait_cnt < 3 then
-            wait_cnt <= wait_cnt + 1;
-            spi_distr_state <= INIT;
-          else
-            spi_distr_state <= IDLE;
-          end if;
+          spi_distr_state <= IDLE;
         when IDLE =>
           --data <= (others => 'Z');