Index: FPGA/FTU/old_design/ftu_board.ucf =================================================================== --- FPGA/FTU/old_design/ftu_board.ucf (revision 251) +++ FPGA/FTU/old_design/ftu_board.ucf (revision 251) @@ -0,0 +1,145 @@ +######################################################## +# FTU Board +# FACT Trigger Unit +# +# Pin location constraints +# +# by Patrick Vogler, Quirin Weitzel +# 01 July 2010 +######################################################## + + +#Clock +####################################################### +NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk + + +# RS-485 Interface +####################################################### +NET rx_en LOC = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver +NET tx_en LOC = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter +NET tx LOC = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM +NET rx LOC = R20 | IOSTANDARD=LVCMOS33; # 485_DI: serial data from FTM + + +# Board ID - inputs +# local board-ID "solder programmable" +####################################################### +NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0 +NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1 +NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2 +NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3 +NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4 +NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5 +NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6 +NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7 + + +# Board Addresses +# geographical slot address +####################################################### +NET brd_add<0> LOC = A15 | IOSTANDARD=LVCMOS33; # ADDR0 +NET brd_add<1> LOC = B15 | IOSTANDARD=LVCMOS33; # ADDR1 +NET brd_add<2> LOC = A16 | IOSTANDARD=LVCMOS33; # ADDR2 +NET brd_add<3> LOC = A17 | IOSTANDARD=LVCMOS33; # ADDR3 +NET brd_add<4> LOC = A18 | IOSTANDARD=LVCMOS33; # ADDR4 +NET brd_add<5> LOC = B18 | IOSTANDARD=LVCMOS33; # ADDR5 + + +# DAC SPI Interface +####################################################### +NET mosi LOC = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in +NET sck LOC = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC +NET cs_ld LOC = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC +NET clr LOC = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC + + +# Testpoints +###################################################### +# on Connector J5 +NET TP_A<0> LOC = B3 | IOSTANDARD=LVCMOS33; # TP0_0 +NET TP_A<1> LOC = A3 | IOSTANDARD=LVCMOS33; # TP1_0 +NET TP_A<2> LOC = A4 | IOSTANDARD=LVCMOS33; # TP2_0 +NET TP_A<3> LOC = B5 | IOSTANDARD=LVCMOS33; # TP2_0 + +# on Connector J6 +NET TP_A<4> LOC = A5 | IOSTANDARD=LVCMOS33; # TP4_0 +NET TP_A<5> LOC = A6 | IOSTANDARD=LVCMOS33; # TP5_0 +NET TP_A<6> LOC = B7 | IOSTANDARD=LVCMOS33; # TP6_0 +NET TP_A<7> LOC = A7 | IOSTANDARD=LVCMOS33; # TP7_0 + +# on Connector J7 +NET TP_A<8> LOC = B11 | IOSTANDARD=LVCMOS33; # TP8_0 +NET TP_A<9> LOC = A12 | IOSTANDARD=LVCMOS33; # TP9_0 +NET TP_A<10> LOC = B12 | IOSTANDARD=LVCMOS33; # TP10_0 +NET TP_A<11> LOC = A14 | IOSTANDARD=LVCMOS33; # TP11_0 + + +# Rate counter LVDS Inputs +###################################################### +# logic signal from first trigger patch +NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P +NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N + +# logic signal from second trigger patch +NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P +NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N + +# logic signal from third trigger patch +NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P +NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N + +# logic signal from fourth trigger patch +NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P +NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N + +#The Trigger Primitive: logic signal from n-out-of-4 circuit +NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+ +NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P- + + +# Enables +###################################################### +# Patch 0 +NET enables_A<0> LOC = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 +NET enables_A<1> LOC = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1 +NET enables_A<2> LOC = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2 +NET enables_A<3> LOC = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3 +NET enables_A<4> LOC = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4 +NET enables_A<5> LOC = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5 +NET enables_A<6> LOC = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6 +NET enables_A<7> LOC = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7 +NET enables_A<8> LOC = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8 + +## Patch 1 +NET enables_B<0> LOC = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0 +NET enables_B<1> LOC = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1 +NET enables_B<2> LOC = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2 +NET enables_B<3> LOC = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3 +NET enables_B<4> LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4 +NET enables_B<5> LOC = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5 +NET enables_B<6> LOC = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6 +NET enables_B<7> LOC = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7 +NET enables_B<8> LOC = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8 + +# Patch 2 +NET enables_C<0> LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0 +NET enables_C<1> LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1 +NET enables_C<2> LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2 +NET enables_C<3> LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3 +NET enables_C<4> LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4 +NET enables_C<5> LOC = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5 +NET enables_C<6> LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6 +NET enables_C<7> LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7 +NET enables_C<8> LOC = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8 + +# Patch 3 +NET enables_D<0> LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<1> LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<2> LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<3> LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<4> LOC = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<5> LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<6> LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<7> LOC = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<8> LOC = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0