Index: FPGA/FTU/FTU_top.vhd =================================================================== --- FPGA/FTU/FTU_top.vhd (revision 251) +++ FPGA/FTU/FTU_top.vhd (revision 251) @@ -0,0 +1,109 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 11:59:40 01/19/2010 +-- Design Name: +-- Module Name: FTU_top - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Top level entity of FACT FTU board +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Revision 0.02 - New design of FTU firmware, 12.07.2010, Q. Weitzel +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +entity FTU_top is + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : in STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); +end FTU_top; + + +architecture Behavioral of FTU_top is + + signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up + signal clk_5M_sig : STD_LOGIC; + + type FTU_top_StateType is (Init, Running, Reset); + signal FTU_top_State, FTU_top_NextState: FTU_top_StateType; + +begin + + --FTU main state machine (two-process implementation) + + FTU_top_Registers: process (ext_clk) + begin + if Rising_edge(ext_clk) then + FTU_top_State <= FTU_top_NextState; + end if; + end process FTU_top_Registers; + + FTU_top_C_logic: process (FTU_top_State) + begin + FTU_top_NextState <= FTU_top_State; + case FTU_top_State is + when Init => + reset_sig <= '0'; + FTU_top_NextState <= Running; + when Running => + when Reset => + reset_sig <= '1'; + FTU_top_NextState <= Init; + end case; + end process FTU_top_C_logic; + +end Behavioral; Index: FPGA/FTU/old_design/ftu_board.ucf =================================================================== --- FPGA/FTU/old_design/ftu_board.ucf (revision 251) +++ FPGA/FTU/old_design/ftu_board.ucf (revision 251) @@ -0,0 +1,145 @@ +######################################################## +# FTU Board +# FACT Trigger Unit +# +# Pin location constraints +# +# by Patrick Vogler, Quirin Weitzel +# 01 July 2010 +######################################################## + + +#Clock +####################################################### +NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk + + +# RS-485 Interface +####################################################### +NET rx_en LOC = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver +NET tx_en LOC = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter +NET tx LOC = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM +NET rx LOC = R20 | IOSTANDARD=LVCMOS33; # 485_DI: serial data from FTM + + +# Board ID - inputs +# local board-ID "solder programmable" +####################################################### +NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0 +NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1 +NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2 +NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3 +NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4 +NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5 +NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6 +NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7 + + +# Board Addresses +# geographical slot address +####################################################### +NET brd_add<0> LOC = A15 | IOSTANDARD=LVCMOS33; # ADDR0 +NET brd_add<1> LOC = B15 | IOSTANDARD=LVCMOS33; # ADDR1 +NET brd_add<2> LOC = A16 | IOSTANDARD=LVCMOS33; # ADDR2 +NET brd_add<3> LOC = A17 | IOSTANDARD=LVCMOS33; # ADDR3 +NET brd_add<4> LOC = A18 | IOSTANDARD=LVCMOS33; # ADDR4 +NET brd_add<5> LOC = B18 | IOSTANDARD=LVCMOS33; # ADDR5 + + +# DAC SPI Interface +####################################################### +NET mosi LOC = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in +NET sck LOC = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC +NET cs_ld LOC = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC +NET clr LOC = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC + + +# Testpoints +###################################################### +# on Connector J5 +NET TP_A<0> LOC = B3 | IOSTANDARD=LVCMOS33; # TP0_0 +NET TP_A<1> LOC = A3 | IOSTANDARD=LVCMOS33; # TP1_0 +NET TP_A<2> LOC = A4 | IOSTANDARD=LVCMOS33; # TP2_0 +NET TP_A<3> LOC = B5 | IOSTANDARD=LVCMOS33; # TP2_0 + +# on Connector J6 +NET TP_A<4> LOC = A5 | IOSTANDARD=LVCMOS33; # TP4_0 +NET TP_A<5> LOC = A6 | IOSTANDARD=LVCMOS33; # TP5_0 +NET TP_A<6> LOC = B7 | IOSTANDARD=LVCMOS33; # TP6_0 +NET TP_A<7> LOC = A7 | IOSTANDARD=LVCMOS33; # TP7_0 + +# on Connector J7 +NET TP_A<8> LOC = B11 | IOSTANDARD=LVCMOS33; # TP8_0 +NET TP_A<9> LOC = A12 | IOSTANDARD=LVCMOS33; # TP9_0 +NET TP_A<10> LOC = B12 | IOSTANDARD=LVCMOS33; # TP10_0 +NET TP_A<11> LOC = A14 | IOSTANDARD=LVCMOS33; # TP11_0 + + +# Rate counter LVDS Inputs +###################################################### +# logic signal from first trigger patch +NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P +NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N + +# logic signal from second trigger patch +NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P +NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N + +# logic signal from third trigger patch +NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P +NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N + +# logic signal from fourth trigger patch +NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P +NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N + +#The Trigger Primitive: logic signal from n-out-of-4 circuit +NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+ +NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P- + + +# Enables +###################################################### +# Patch 0 +NET enables_A<0> LOC = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 +NET enables_A<1> LOC = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1 +NET enables_A<2> LOC = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2 +NET enables_A<3> LOC = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3 +NET enables_A<4> LOC = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4 +NET enables_A<5> LOC = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5 +NET enables_A<6> LOC = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6 +NET enables_A<7> LOC = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7 +NET enables_A<8> LOC = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8 + +## Patch 1 +NET enables_B<0> LOC = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0 +NET enables_B<1> LOC = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1 +NET enables_B<2> LOC = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2 +NET enables_B<3> LOC = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3 +NET enables_B<4> LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4 +NET enables_B<5> LOC = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5 +NET enables_B<6> LOC = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6 +NET enables_B<7> LOC = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7 +NET enables_B<8> LOC = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8 + +# Patch 2 +NET enables_C<0> LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0 +NET enables_C<1> LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1 +NET enables_C<2> LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2 +NET enables_C<3> LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3 +NET enables_C<4> LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4 +NET enables_C<5> LOC = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5 +NET enables_C<6> LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6 +NET enables_C<7> LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7 +NET enables_C<8> LOC = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8 + +# Patch 3 +NET enables_D<0> LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<1> LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<2> LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<3> LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<4> LOC = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<5> LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<6> LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<7> LOC = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<8> LOC = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0