Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD.hdp =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD.hdp (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD.hdp (revision 252) @@ -1,6 +1,8 @@ +[DesignChecker] +FACT_FAD_lib = $HDS_PROJECT_DIR\FACT_FAD_lib\designcheck [ModelSim] FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/work FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/work -secureip = C:\FPGAdv82PS\Xilinx_Lib\secureip +secureip = C:/FPGAdv82PS/Xilinx_Lib/secureip simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro @@ -8,5 +10,5 @@ XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib [QuestaSim] -secureip = C:\FPGAdv82PS\Xilinx_Lib\secureip +secureip = C:/FPGAdv82PS/Xilinx_Lib/secureip simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd (revision 252) @@ -36,5 +36,7 @@ ram_write_en : OUT std_logic_vector (0 DOWNTO 0); dac_array : OUT dac_array_type; - roi_array : OUT roi_array_type + roi_array : OUT roi_array_type; + drs_address : OUT std_logic_vector (3 DOWNTO 0); + drs_address_mode : OUT std_logic ); @@ -53,4 +55,6 @@ signal int_dac_array : dac_array_type := DEFAULT_DAC; signal int_roi_array : roi_array_type := DEFAULT_ROI; + signal int_drs_address: std_logic_vector (3 DOWNTO 0) := DEFAULT_DRSADDR; + signal int_drs_address_mode: std_logic := DEFAULT_DRSADDR_MODE; BEGIN @@ -66,4 +70,5 @@ when CTRL_INIT => + -- WRITES DEFAULT VALUES IN config ram addr_cntr <= addr_cntr + 1; ram_addr <= conv_std_logic_vector(addr_cntr, ADDR_WIDTH); @@ -76,4 +81,8 @@ elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then ram_data_in <= conv_std_logic_vector(int_dac_array(addr_cntr - NO_OF_ROI), 16); + elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then + ram_data_in <= "0000" & "0000" + & "000" & conv_std_logic_vector(int_drs_address_mode, 1) + & int_drs_address; else ram_write_en <= "0"; @@ -82,4 +91,5 @@ when CTRL_IDLE => + -- addr_cntr <= 0; ram_write_en <= "0"; @@ -119,5 +129,9 @@ dac_array(addr_cntr - NO_OF_ROI) <= conv_integer(ram_data_out); ctrl_state <= CTRL_LOAD_ADDR; - else + elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then + drs_address <= ram_data_out(3 downto 0); + drs_address_mode <= ram_data_out(4); + ctrl_state <= CTRL_LOAD_ADDR; + else addr_cntr <= 0; config_started <= '0'; Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_unit_struct.vhd =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_unit_struct.vhd (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_unit_struct.vhd (revision 252) @@ -2,6 +2,6 @@ -- -- Created: --- by - Benjamin Krumm.UNKNOWN (EEPC8) --- at - 12:04:03 23.06.2010 +-- by - dneise.UNKNOWN (TU-CC4900F8C7D2) +-- at - 14:46:37 12.07.2010 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -25,4 +25,6 @@ config_started : OUT std_logic := '0'; dac_array : OUT dac_array_type; + drs_address : OUT std_logic_vector (3 DOWNTO 0); + drs_address_mode : OUT std_logic; roi_array : OUT roi_array_type; config_data : INOUT std_logic_vector (15 DOWNTO 0) @@ -37,6 +39,6 @@ -- -- Created: --- by - Benjamin Krumm.UNKNOWN (EEPC8) --- at - 12:04:03 23.06.2010 +-- by - dneise.UNKNOWN (TU-CC4900F8C7D2) +-- at - 14:46:37 12.07.2010 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -93,5 +95,7 @@ ram_write_en : OUT std_logic_vector (0 DOWNTO 0); dac_array : OUT dac_array_type ; - roi_array : OUT roi_array_type + roi_array : OUT roi_array_type ; + drs_address : OUT std_logic_vector (3 DOWNTO 0); + drs_address_mode : OUT std_logic ); END COMPONENT; @@ -137,5 +141,7 @@ ram_write_en => ram_wren, dac_array => dac_array, - roi_array => roi_array + roi_array => roi_array, + drs_address => drs_address, + drs_address_mode => drs_address_mode ); Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board.ucf =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board.ucf (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board.ucf (revision 252) @@ -10,6 +10,6 @@ #Test Trigger input on 'Testpoint near W5300' -#NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; #ok -NET TEST_TRG LOC = R19 | IOSTANDARD=LVCMOS33 | PULLUP; +#NET _TW<3> LOC = R19 | IOSTANDARD=LVCMOS33; #ok +NET TEST_TRG LOC = R19 | IOSTANDARD=LVCMOS33; @@ -229,5 +229,5 @@ NET A1_T<2> LOC = AC12 | IOSTANDARD=LVCMOS33; #ok NET A1_T<3> LOC = AC14 | IOSTANDARD=LVCMOS33; #ok -#NET A1_T<4> LOC = AC15 | IOSTANDARD=LVCMOS33; #ok +NET A1_T<4> LOC = AC15 | IOSTANDARD=LVCMOS33; #ok #NET A1_T<5> LOC = AB16 | IOSTANDARD=LVCMOS33; #ok #NET A1_T<6> LOC = AC16 | IOSTANDARD=LVCMOS33; #ok Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 252) @@ -2,6 +2,6 @@ -- -- Created: --- by - dneise.UNKNOWN (TU-CC4900F8C7D2) --- at - 12:42:19 02.07.2010 +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 15:25:14 14.07.2010 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -27,5 +27,5 @@ W_INT : IN std_logic; X_50M : IN STD_LOGIC; - A1_T : OUT std_logic_vector (3 DOWNTO 0); + A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); A_CLK : OUT std_logic_vector (3 DOWNTO 0); D0_SRCLK : OUT STD_LOGIC; @@ -72,6 +72,6 @@ -- -- Created: --- by - dneise.UNKNOWN (TU-CC4900F8C7D2) --- at - 12:42:20 02.07.2010 +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 15:25:14 14.07.2010 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -95,16 +95,12 @@ SIGNAL CLK_25_PS : std_logic; SIGNAL CLK_50 : std_logic; - SIGNAL SRCLK : std_logic := '0'; + SIGNAL SRCLK : std_logic := '0'; SIGNAL TRG_OR : std_logic; SIGNAL adc_data_array : adc_data_array_type; SIGNAL board_id : std_logic_vector(3 DOWNTO 0); SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); + SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL dummy : std_logic; - SIGNAL not_TEST_TRG : STD_LOGIC; SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); - SIGNAL trigger_out : STD_LOGIC := '0'; - - -- Implicit buffer signal declarations - SIGNAL RSRLOAD_internal : std_logic; @@ -148,20 +144,8 @@ ); END COMPONENT; - COMPONENT debouncer - GENERIC ( - WIDTH : INTEGER := 17 - ); - PORT ( - clk : IN STD_LOGIC ; - -- rst : in STD_LOGIC; - trigger_in : IN STD_LOGIC ; - trigger_out : OUT STD_LOGIC := '0' - ); - END COMPONENT; -- Optional embedded configurations -- pragma synthesis_off FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main; - FOR ALL : debouncer USE ENTITY FACT_FAD_lib.debouncer; -- pragma synthesis_on @@ -228,8 +212,7 @@ -- HDL Embedded Text Block 8 eb2 -- eb2 8 - A1_T(0) <= dummy; - A1_T(1) <= RSRLOAD_internal; - A1_T(2) <= D0_SROUT; - A1_T(3) <= D1_SROUT; + A1_T(3 downto 0) <= drs_channel_id; + D_A <= drs_channel_id; + A1_T(4) <= TRG_OR; @@ -237,9 +220,6 @@ DAC_CS <= dummy; - -- ModuleWare code(v1.9) for instance 'I1' of 'inv' - not_TEST_TRG <= NOT(TEST_TRG); - -- ModuleWare code(v1.9) for instance 'I2' of 'or' - TRG_OR <= TRG OR trigger_out; + TRG_OR <= TRG OR TEST_TRG; -- Instance port mappings. @@ -262,10 +242,10 @@ CLK_25_PS => CLK_25_PS, CLK_50 => CLK_50, - RSRLOAD => RSRLOAD_internal, + RSRLOAD => RSRLOAD, SRCLK => SRCLK, adc_oeb => OE_ADC, dac_cs => dummy, denable => DENABLE, - drs_channel_id => D_A, + drs_channel_id => drs_channel_id, drs_dwrite => DWRITE, led => D_T, @@ -281,16 +261,4 @@ wiz_data => W_D ); - I_debouncer : debouncer - GENERIC MAP ( - WIDTH => 17 - ) - PORT MAP ( - clk => CLK_50, - trigger_in => not_TEST_TRG, - trigger_out => trigger_out - ); - - -- Implicit buffered output assignments - RSRLOAD <= RSRLOAD_internal; END struct; Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 252) @@ -104,4 +104,9 @@ constant DEFAULT_DAC : dac_array_type := (20972, 34079, 20526, 0, 28836, 28836, 28836, 28836); --constant DEFAULT_DAC : dac_array_type := (others => 0); + + constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= "0000"; + constant DEFAULT_DRSADDR_MODE : std_logic := '0'; + + -- Commands Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd.bak =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd.bak (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd.bak (revision 252) @@ -51,4 +51,6 @@ constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14"; constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18"; + constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C"; + constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E"; constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20"; constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22"; @@ -80,5 +82,6 @@ constant LOG2_OF_RAM_SIZE_64B : integer := 15; - constant RAM_SIZE_64B : integer := 2**LOG2_OF_RAM_SIZE_64B; + --constant RAM_SIZE_64B : integer := 2**LOG2_OF_RAM_SIZE_64B; + constant RAM_SIZE_64B : integer := 24576; constant RAM_SIZE_16B : integer := RAM_SIZE_64B * 4; @@ -101,4 +104,9 @@ constant DEFAULT_DAC : dac_array_type := (20972, 34079, 20526, 0, 28836, 28836, 28836, 28836); --constant DEFAULT_DAC : dac_array_type := (others => 0); + + constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= X"0"; + constant DEFAULT_DRSADDR_MODE : std_logic := '0'; + + -- Commands Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 252) @@ -3,5 +3,5 @@ -- Created: -- by - dneise.UNKNOWN (TU-CC4900F8C7D2) --- at - 12:42:19 02.07.2010 +-- at - 14:46:38 12.07.2010 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -60,5 +60,5 @@ -- Created: -- by - dneise.UNKNOWN (TU-CC4900F8C7D2) --- at - 12:42:19 02.07.2010 +-- at - 14:46:38 12.07.2010 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -106,4 +106,7 @@ SIGNAL dac_array : dac_array_type; SIGNAL data_out : std_logic_vector(63 DOWNTO 0); + SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0'); + SIGNAL drs_address_mode : std_logic; + SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL drs_clk_en : std_logic := '0'; SIGNAL drs_read_s_cell : std_logic := '0'; @@ -170,4 +173,6 @@ config_started : OUT std_logic := '0'; dac_array : OUT dac_array_type ; + drs_address : OUT std_logic_vector (3 DOWNTO 0); + drs_address_mode : OUT std_logic ; roi_array : OUT roi_array_type ; config_data : INOUT std_logic_vector (15 DOWNTO 0) @@ -351,4 +356,15 @@ drs_dwrite <= dwrite AND dwrite_enable; + -- ModuleWare code(v1.9) for instance 'U_0' of 'mux' + u_0combo_proc: PROCESS(drs_channel_internal, drs_address, + drs_address_mode) + BEGIN + CASE drs_address_mode IS + WHEN '0' => drs_channel_id <= drs_channel_internal; + WHEN '1' => drs_channel_id <= drs_address; + WHEN OTHERS => drs_channel_id <= (OTHERS => 'X'); + END CASE; + END PROCESS u_0combo_proc; + -- Instance port mappings. I_main_adc_buffer : adc_buffer @@ -379,4 +395,6 @@ config_started => config_started_cu, dac_array => dac_array, + drs_address => drs_address, + drs_address_mode => drs_address_mode, roi_array => roi_array, config_data => config_data @@ -429,5 +447,5 @@ adc_oeb => adc_oeb, adc_otr => adc_otr, - drs_channel_id => drs_channel_id, + drs_channel_id => drs_channel_internal, drs_dwrite => dwrite, drs_clk_en => drs_clk_en, Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.xrf/control_unit_struct.xrf =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.xrf/control_unit_struct.xrf (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.xrf/control_unit_struct.xrf (revision 252) @@ -37,206 +37,224 @@ DESIGN control_unit VIEW symbol.sb -GRAPHIC 155,0 26 0 -DESIGN control_unit -VIEW symbol.sb -GRAPHIC 150,0 27 0 -DESIGN control_unit -VIEW symbol.sb -GRAPHIC 1,0 30 0 -DESIGN control_unit -VIEW symbol.sb -GRAPHIC 1,0 31 0 -DESIGN control_unit -VIEW struct.bd -NO_GRAPHIC 34 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 41,0 43 0 -DESIGN control_unit -VIEW struct.bd -NO_GRAPHIC 48 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 0,0 51 2 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 345,0 56 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 333,0 57 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 349,0 58 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 329,0 59 0 -DESIGN control_unit -VIEW struct.bd -NO_GRAPHIC 60 -DESIGN control_unit -VIEW struct.bd -NO_GRAPHIC 61 +GRAPHIC 521,0 26 0 +DESIGN control_unit +VIEW symbol.sb +GRAPHIC 526,0 27 0 +DESIGN control_unit +VIEW symbol.sb +GRAPHIC 155,0 28 0 +DESIGN control_unit +VIEW symbol.sb +GRAPHIC 150,0 29 0 +DESIGN control_unit +VIEW symbol.sb +GRAPHIC 1,0 32 0 +DESIGN control_unit +VIEW symbol.sb +GRAPHIC 1,0 33 0 +DESIGN control_unit +VIEW struct.bd +NO_GRAPHIC 36 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 41,0 45 0 +DESIGN control_unit +VIEW struct.bd +NO_GRAPHIC 50 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 0,0 53 2 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 345,0 58 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 333,0 59 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 349,0 60 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 329,0 61 0 +DESIGN control_unit +VIEW struct.bd +NO_GRAPHIC 62 +DESIGN control_unit +VIEW struct.bd +NO_GRAPHIC 63 LIBRARY FACT_FAD_lib DESIGN control@r@a@m_16bit_x256 VIEW control@r@a@m_16bit_x256_a -GRAPHIC 993,0 63 0 -DESIGN control@r@a@m_16bit_x256 -VIEW control@r@a@m_16bit_x256_a -GRAPHIC 48,0 65 0 -DESIGN control@r@a@m_16bit_x256 -VIEW control@r@a@m_16bit_x256_a -GRAPHIC 53,0 66 0 -DESIGN control@r@a@m_16bit_x256 -VIEW control@r@a@m_16bit_x256_a -GRAPHIC 58,0 67 0 -DESIGN control@r@a@m_16bit_x256 -VIEW control@r@a@m_16bit_x256_a -GRAPHIC 63,0 68 0 -DESIGN control@r@a@m_16bit_x256 -VIEW control@r@a@m_16bit_x256_a -GRAPHIC 68,0 69 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 960,0 72 0 -DESIGN control_manager -VIEW symbol.sb -GRAPHIC 14,0 73 1 -DESIGN control_manager -VIEW beha -GRAPHIC 48,0 79 0 -DESIGN control_manager -VIEW beha -GRAPHIC 310,0 80 0 -DESIGN control_manager -VIEW beha -GRAPHIC 58,0 81 0 -DESIGN control_manager -VIEW beha -GRAPHIC 492,0 82 0 -DESIGN control_manager -VIEW beha -GRAPHIC 63,0 83 0 -DESIGN control_manager -VIEW beha -GRAPHIC 68,0 84 0 -DESIGN control_manager -VIEW beha -GRAPHIC 73,0 85 0 -DESIGN control_manager -VIEW beha -GRAPHIC 78,0 86 0 -DESIGN control_manager -VIEW beha -GRAPHIC 83,0 87 0 -DESIGN control_manager -VIEW beha -GRAPHIC 88,0 88 0 -DESIGN control_manager -VIEW beha -GRAPHIC 93,0 89 0 -DESIGN control_manager -VIEW beha -GRAPHIC 346,0 90 0 -DESIGN control_manager -VIEW beha -GRAPHIC 263,0 91 0 -DESIGN control_manager -VIEW beha -GRAPHIC 268,0 92 0 -DESIGN control_manager -VIEW beha -GRAPHIC 118,0 93 0 -DESIGN control_manager -VIEW beha -GRAPHIC 123,0 94 0 +GRAPHIC 993,0 65 0 +DESIGN control@r@a@m_16bit_x256 +VIEW control@r@a@m_16bit_x256_a +GRAPHIC 48,0 67 0 +DESIGN control@r@a@m_16bit_x256 +VIEW control@r@a@m_16bit_x256_a +GRAPHIC 53,0 68 0 +DESIGN control@r@a@m_16bit_x256 +VIEW control@r@a@m_16bit_x256_a +GRAPHIC 58,0 69 0 +DESIGN control@r@a@m_16bit_x256 +VIEW control@r@a@m_16bit_x256_a +GRAPHIC 63,0 70 0 +DESIGN control@r@a@m_16bit_x256 +VIEW control@r@a@m_16bit_x256_a +GRAPHIC 68,0 71 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 960,0 74 0 +DESIGN control_manager +VIEW symbol.sb +GRAPHIC 14,0 75 1 +DESIGN control_manager +VIEW beha +GRAPHIC 48,0 81 0 +DESIGN control_manager +VIEW beha +GRAPHIC 310,0 82 0 +DESIGN control_manager +VIEW beha +GRAPHIC 58,0 83 0 +DESIGN control_manager +VIEW beha +GRAPHIC 492,0 84 0 +DESIGN control_manager +VIEW beha +GRAPHIC 63,0 85 0 +DESIGN control_manager +VIEW beha +GRAPHIC 68,0 86 0 +DESIGN control_manager +VIEW beha +GRAPHIC 73,0 87 0 +DESIGN control_manager +VIEW beha +GRAPHIC 78,0 88 0 +DESIGN control_manager +VIEW beha +GRAPHIC 83,0 89 0 +DESIGN control_manager +VIEW beha +GRAPHIC 88,0 90 0 +DESIGN control_manager +VIEW beha +GRAPHIC 93,0 91 0 +DESIGN control_manager +VIEW beha +GRAPHIC 346,0 92 0 +DESIGN control_manager +VIEW beha +GRAPHIC 263,0 93 0 +DESIGN control_manager +VIEW beha +GRAPHIC 268,0 94 0 +DESIGN control_manager +VIEW beha +GRAPHIC 118,0 95 0 +DESIGN control_manager +VIEW beha +GRAPHIC 123,0 96 0 +DESIGN control_manager +VIEW beha +GRAPHIC 528,0 97 0 +DESIGN control_manager +VIEW beha +GRAPHIC 533,0 98 0 LIBRARY FACT_FAD_lib DESIGN control_unit VIEW struct.bd -NO_GRAPHIC 97 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 993,0 100 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 960,0 101 0 -DESIGN control_unit -VIEW struct.bd -NO_GRAPHIC 104 -DESIGN control_unit -VIEW struct.bd -NO_GRAPHIC 106 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 993,0 108 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 279,0 110 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 237,0 111 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 285,0 112 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 233,0 113 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 301,0 114 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 960,0 116 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 967,0 117 1 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 241,0 123 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 301,0 124 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 321,0 125 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 1084,0 126 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 289,0 127 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 267,0 128 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 227,0 129 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 295,0 130 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 311,0 131 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 255,0 132 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 261,0 133 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 285,0 134 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 237,0 135 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 233,0 136 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 305,0 137 0 -DESIGN control_unit -VIEW struct.bd -GRAPHIC 273,0 138 0 -DESIGN control_unit -VIEW struct.bd -NO_GRAPHIC 141 +NO_GRAPHIC 101 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 993,0 104 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 960,0 105 0 +DESIGN control_unit +VIEW struct.bd +NO_GRAPHIC 108 +DESIGN control_unit +VIEW struct.bd +NO_GRAPHIC 110 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 993,0 112 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 279,0 114 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 237,0 115 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 285,0 116 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 233,0 117 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 301,0 118 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 960,0 120 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 967,0 121 1 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 241,0 127 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 301,0 128 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 321,0 129 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 1084,0 130 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 289,0 131 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 267,0 132 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 227,0 133 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 295,0 134 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 311,0 135 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 255,0 136 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 261,0 137 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 285,0 138 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 237,0 139 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 233,0 140 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 305,0 141 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 273,0 142 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 1208,0 143 0 +DESIGN control_unit +VIEW struct.bd +GRAPHIC 1222,0 144 0 +DESIGN control_unit +VIEW struct.bd +NO_GRAPHIC 147 Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf (revision 252) @@ -175,5 +175,5 @@ DESIGN @f@a@d_@board VIEW struct.bd -GRAPHIC 2267,0 95 0 +GRAPHIC 9500,0 95 0 DESIGN @f@a@d_@board VIEW struct.bd @@ -193,8 +193,8 @@ DESIGN @f@a@d_@board VIEW struct.bd -GRAPHIC 7485,0 101 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 6326,0 102 0 +GRAPHIC 8851,0 101 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 7485,0 102 0 DESIGN @f@a@d_@board VIEW struct.bd @@ -202,175 +202,172 @@ DESIGN @f@a@d_@board VIEW struct.bd -GRAPHIC 6278,0 104 0 +NO_GRAPHIC 104 DESIGN @f@a@d_@board VIEW struct.bd NO_GRAPHIC 105 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 7118,0 107 0 -DESIGN @f@a@d_@board -VIEW struct.bd -NO_GRAPHIC 109 LIBRARY FACT_FAD_lib DESIGN @f@a@d_main VIEW struct -GRAPHIC 169,0 111 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 14,0 112 1 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 1755,0 116 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 2710,0 117 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 2715,0 118 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 2720,0 119 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 2725,0 120 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 2282,0 121 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 1976,0 122 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 923,0 123 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 928,0 124 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 464,0 125 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 1062,0 126 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 1389,0 127 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 1725,0 128 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 2987,0 129 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 2992,0 130 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 833,0 131 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 3641,0 132 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 4144,0 133 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 2448,0 134 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 2453,0 135 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 163,0 136 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 4067,0 137 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 3631,0 138 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 3646,0 139 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 1037,0 140 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 1047,0 141 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 1057,0 142 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 135,0 143 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 1052,0 144 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 3636,0 145 0 -DESIGN @f@a@d_main -VIEW symbol.sb -GRAPHIC 1042,0 146 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 6250,0 149 0 -DESIGN debouncer -VIEW symbol.sb -GRAPHIC 14,0 150 1 -DESIGN debouncer -VIEW @behavioral -GRAPHIC 48,0 154 0 -DESIGN debouncer -VIEW @behavioral -GRAPHIC 53,0 155 0 -DESIGN debouncer -VIEW @behavioral -GRAPHIC 58,0 157 0 +GRAPHIC 169,0 107 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 14,0 108 1 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1755,0 112 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2710,0 113 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2715,0 114 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2720,0 115 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2725,0 116 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2282,0 117 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1976,0 118 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 923,0 119 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 928,0 120 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 464,0 121 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1062,0 122 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1389,0 123 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1725,0 124 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2987,0 125 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2992,0 126 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 833,0 127 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 3641,0 128 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 4144,0 129 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2448,0 130 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2453,0 131 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 163,0 132 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 4067,0 133 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 3631,0 134 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 3646,0 135 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1037,0 136 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1047,0 137 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1057,0 138 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 135,0 139 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1052,0 140 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 3636,0 141 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1042,0 142 0 LIBRARY FACT_FAD_lib DESIGN @f@a@d_@board VIEW struct.bd -NO_GRAPHIC 160 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 169,0 163 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 6250,0 164 0 -DESIGN @f@a@d_@board -VIEW struct.bd -NO_GRAPHIC 167 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 265,0 170 0 -DESIGN @f@a@d_@board -VIEW struct.bd -NO_GRAPHIC 174 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 3248,0 175 0 -DESIGN @f@a@d_@board -VIEW struct.bd -NO_GRAPHIC 181 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 3300,0 182 0 -DESIGN @f@a@d_@board -VIEW struct.bd -NO_GRAPHIC 188 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 3394,0 189 0 -DESIGN @f@a@d_@board -VIEW struct.bd -NO_GRAPHIC 195 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 3542,0 196 0 -DESIGN @f@a@d_@board -VIEW struct.bd -NO_GRAPHIC 202 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 3700,0 203 0 +NO_GRAPHIC 145 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 169,0 148 0 +DESIGN @f@a@d_@board +VIEW struct.bd +NO_GRAPHIC 151 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 265,0 154 0 +DESIGN @f@a@d_@board +VIEW struct.bd +NO_GRAPHIC 158 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 3248,0 159 0 +DESIGN @f@a@d_@board +VIEW struct.bd +NO_GRAPHIC 165 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 3300,0 166 0 +DESIGN @f@a@d_@board +VIEW struct.bd +NO_GRAPHIC 172 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 3394,0 173 0 +DESIGN @f@a@d_@board +VIEW struct.bd +NO_GRAPHIC 179 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 3542,0 180 0 +DESIGN @f@a@d_@board +VIEW struct.bd +NO_GRAPHIC 186 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 3700,0 187 0 +DESIGN @f@a@d_@board +VIEW struct.bd +NO_GRAPHIC 207 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 6888,0 208 0 +DESIGN @f@a@d_@board +VIEW struct.bd +NO_GRAPHIC 210 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 7092,0 211 0 +DESIGN @f@a@d_@board +VIEW struct.bd +NO_GRAPHIC 216 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 7652,0 217 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 6586,0 220 0 DESIGN @f@a@d_@board VIEW struct.bd @@ -378,144 +375,102 @@ DESIGN @f@a@d_@board VIEW struct.bd -GRAPHIC 6888,0 224 0 -DESIGN @f@a@d_@board -VIEW struct.bd -NO_GRAPHIC 226 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 7092,0 227 0 -DESIGN @f@a@d_@board -VIEW struct.bd -NO_GRAPHIC 233 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 7652,0 234 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 6539,0 237 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 6586,0 240 0 -DESIGN @f@a@d_@board -VIEW struct.bd -NO_GRAPHIC 243 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 169,0 245 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 176,0 246 1 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 245,0 250 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 1865,0 251 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 1873,0 252 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 1881,0 253 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 1889,0 254 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 1467,0 255 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 1730,0 256 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 277,0 257 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 285,0 258 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 6130,0 259 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 450,0 260 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 3270,0 261 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 2269,0 262 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 2409,0 263 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 2423,0 264 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 362,0 265 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 7477,0 266 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 6431,0 267 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 1833,0 268 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 1841,0 269 0 -DESIGN @f@a@d_@board -VIEW struct.bd -GRAPHIC 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struct.bd -NO_GRAPHIC 295 +GRAPHIC 169,0 225 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 176,0 226 1 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 245,0 230 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 1865,0 231 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 1873,0 232 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 1881,0 233 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 1889,0 234 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 1467,0 235 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 1730,0 236 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 277,0 237 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 285,0 238 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 6130,0 239 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 450,0 240 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 3270,0 241 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 9502,0 242 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 2409,0 243 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 2423,0 244 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 362,0 245 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 7477,0 246 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 6431,0 247 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 8853,0 248 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 1841,0 249 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 4942,0 250 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 3682,0 251 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 3009,0 252 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 3021,0 253 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 426,0 254 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 434,0 255 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 458,0 256 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 418,0 257 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 466,0 258 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 3015,0 259 0 +DESIGN @f@a@d_@board +VIEW struct.bd +GRAPHIC 442,0 260 0 +DESIGN @f@a@d_@board +VIEW struct.bd +NO_GRAPHIC 263 Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf (revision 252) @@ -187,553 +187,562 @@ DESIGN @f@a@d_main VIEW struct.bd -GRAPHIC 4399,0 107 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 4417,0 108 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 4741,0 109 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 4405,0 110 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 6544,0 111 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 6450,0 112 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 5948,0 113 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 2640,0 114 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 362,0 115 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 368,0 116 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 2297,0 117 0 -DESIGN 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5222,0 526 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 424,0 527 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 432,0 528 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 2482,0 529 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 2488,0 530 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 370,0 531 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 364,0 532 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 2476,0 533 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 8416,0 534 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 2470,0 535 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 2506,0 536 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 2500,0 537 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 2494,0 538 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 5281,0 539 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 5950,0 540 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 5962,0 541 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 5090,0 542 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 5114,0 543 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 5122,0 544 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 5130,0 545 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 5106,0 546 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 6362,0 547 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 6452,0 548 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 6276,0 552 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 3888,0 553 0 +DESIGN @f@a@d_main +VIEW struct.bd +NO_GRAPHIC 555 Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd (revision 252) @@ -40,27 +40,4 @@ ) (Instance -name "I_debouncer" -duLibraryName "FACT_FAD_LIB" -duName "debouncer" -elements [ -(GiElement -name "WIDTH" -type "INTEGER" -value "17" -) -] -mwi 0 -uid 6250,0 -) -(Instance -name "I1" -duLibraryName "moduleware" -duName "inv" -elements [ -] -mwi 1 -uid 6539,0 -) -(Instance name "I2" duLibraryName "moduleware" @@ -128,21 +105,21 @@ (vvPair variable "HDLDir" -value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hdl" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" ) (vvPair variable "HDSDir" -value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair variable "SideDataDesignDir" -value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info" ) (vvPair variable "SideDataUserDir" -value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user" ) (vvPair variable "SourceDir" -value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair @@ -156,29 +133,29 @@ (vvPair variable "config" -value "%(unit)_config" +value "%(unit)_%(view)_config" ) (vvPair variable "d" -value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board" ) (vvPair variable "d_logical" -value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board" ) (vvPair variable "date" -value "24.06.2010" +value "14.07.2010" ) (vvPair variable "day" -value "Do" +value "Mi" ) (vvPair variable "day_long" -value "Donnerstag" +value "Mittwoch" ) (vvPair variable "dd" -value "24" +value "14" ) (vvPair @@ -208,5 +185,5 @@ (vvPair variable "host" -value "EEPC8" +value "E5B-LABOR6" ) (vvPair @@ -219,4 +196,8 @@ ) (vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR\\FACT_FAD_lib\\designcheck" +) +(vvPair variable "library_downstream_ISEPARInvoke" value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" @@ -236,5 +217,5 @@ (vvPair variable "mm" -value "06" +value "07" ) (vvPair @@ -244,17 +225,17 @@ (vvPair variable "month" -value "Jun" +value "Jul" ) (vvPair variable "month_long" -value "Juni" +value "Juli" ) (vvPair variable "p" -value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd" ) (vvPair variable "p_logical" -value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd" ) (vvPair @@ -280,5 +261,5 @@ (vvPair variable "task_ModelSimPath" -value "$HDS_HOME/../Modeltech/win32" +value "" ) (vvPair @@ -288,5 +269,5 @@ (vvPair variable "task_PrecisionRTLPath" -value "$HDS_HOME/../Precision/Mgc_home/bin" +value "" ) (vvPair @@ -312,5 +293,5 @@ (vvPair variable "time" -value "14:18:44" +value "15:25:08" ) (vvPair @@ -320,5 +301,5 @@ (vvPair variable "user" -value "Benjamin Krumm" +value "dneise" ) (vvPair @@ -364,5 +345,5 @@ bg "0,0,32768" ) -xt "99200,4000,108700,5000" +xt "99200,4000,108500,5000" st " by %user on %dd %month %year @@ -2074,5 +2055,6 @@ ) xt "39000,48000,67000,48800" -st "SIGNAL board_id : std_logic_vector(3 downto 0)" +st "SIGNAL board_id : std_logic_vector(3 downto 0) +" ) ) @@ -2092,5 +2074,6 @@ ) xt "39000,48800,67000,49600" -st "SIGNAL crate_id : std_logic_vector(1 downto 0)" +st "SIGNAL crate_id : std_logic_vector(1 downto 0) +" ) ) @@ -2415,27 +2398,9 @@ ) xt "39000,47200,62500,48000" -st "SIGNAL adc_data_array : adc_data_array_type" +st "SIGNAL adc_data_array : adc_data_array_type +" ) ) *63 (Net -uid 2267,0 -decl (Decl -n "CLK_50" -t "std_logic" -preAdd 0 -posAdd 0 -o 51 -suid 54,0 -) -declText (MLText -uid 2268,0 -va (VaSet -font "Courier New,8,0" -) -xt "39000,44800,57000,45600" -st "SIGNAL CLK_50 : std_logic" -) -) -*64 (Net uid 2407,0 decl (Decl @@ -2452,8 +2417,9 @@ ) xt "39000,31000,68000,31800" -st "RSRLOAD : std_logic := '0'" -) -) -*65 (PortIoOut +st "RSRLOAD : std_logic := '0' +" +) +) +*64 (PortIoOut uid 2415,0 shape (CompositeShape @@ -2500,5 +2466,5 @@ ) ) -*66 (Net +*65 (Net uid 2421,0 decl (Decl @@ -2515,8 +2481,9 @@ ) xt "39000,45600,71500,46400" -st "SIGNAL SRCLK : std_logic := '0'" -) -) -*67 (Net +st "SIGNAL SRCLK : std_logic := '0' +" +) +) +*66 (Net uid 3019,0 decl (Decl @@ -2533,8 +2500,9 @@ ) xt "39000,51200,67000,52000" -st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" -) -) -*68 (Net +st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0) +" +) +) +*67 (Net uid 3025,0 decl (Decl @@ -2550,8 +2518,9 @@ ) xt "39000,19800,53500,20600" -st "DAC_CS : std_logic" -) -) -*69 (PortIoOut +st "DAC_CS : std_logic +" +) +) +*68 (PortIoOut uid 3153,0 shape (CompositeShape @@ -2598,5 +2567,5 @@ ) ) -*70 (Net +*69 (Net uid 3216,0 decl (Decl @@ -2614,8 +2583,9 @@ ) xt "39000,14200,53500,15000" -st "X_50M : STD_LOGIC" -) -) -*71 (Net +st "X_50M : STD_LOGIC +" +) +) +*70 (Net uid 3226,0 decl (Decl @@ -2631,11 +2601,12 @@ ) xt "39000,12600,53500,13400" -st "TRG : STD_LOGIC" -) -) -*72 (HdlText +st "TRG : STD_LOGIC +" +) +) +*71 (HdlText uid 3248,0 optionalChildren [ -*73 (EmbeddedText +*72 (EmbeddedText uid 3254,0 commentText (CommentText @@ -2689,5 +2660,5 @@ stg "VerticalLayoutStrategy" textVec [ -*74 (Text +*73 (Text uid 3251,0 va (VaSet @@ -2699,5 +2670,5 @@ tm "HdlTextNameMgr" ) -*75 (Text +*74 (Text uid 3252,0 va (VaSet @@ -2725,5 +2696,5 @@ viewiconposition 0 ) -*76 (Net +*75 (Net uid 3266,0 decl (Decl @@ -2740,8 +2711,9 @@ ) xt "39000,15800,63500,16600" -st "A_CLK : std_logic_vector(3 downto 0)" -) -) -*77 (Net +st "A_CLK : std_logic_vector(3 downto 0) +" +) +) +*76 (Net uid 3268,0 decl (Decl @@ -2757,8 +2729,9 @@ ) xt "39000,44000,57000,44800" -st "SIGNAL CLK_25_PS : std_logic" -) -) -*78 (PortIoOut +st "SIGNAL CLK_25_PS : std_logic +" +) +) +*77 (PortIoOut uid 3284,0 shape (CompositeShape @@ -2805,5 +2778,5 @@ ) ) -*79 (Net +*78 (Net uid 3290,0 decl (Decl @@ -2821,8 +2794,9 @@ ) xt "39000,27000,53500,27800" -st "OE_ADC : STD_LOGIC" -) -) -*80 (PortIoIn +st "OE_ADC : STD_LOGIC +" +) +) +*79 (PortIoIn uid 3292,0 shape (CompositeShape @@ -2869,5 +2843,5 @@ ) ) -*81 (Net +*80 (Net uid 3298,0 decl (Decl @@ -2884,11 +2858,12 @@ ) xt "39000,7000,63500,7800" -st "A_OTR : std_logic_vector(3 DOWNTO 0)" -) -) -*82 (HdlText +st "A_OTR : std_logic_vector(3 DOWNTO 0) +" +) +) +*81 (HdlText uid 3300,0 optionalChildren [ -*83 (EmbeddedText +*82 (EmbeddedText uid 3306,0 commentText (CommentText @@ -2942,5 +2917,5 @@ stg "VerticalLayoutStrategy" textVec [ -*84 (Text +*83 (Text uid 3303,0 va (VaSet @@ -2952,5 +2927,5 @@ tm "HdlTextNameMgr" ) -*85 (Text +*84 (Text uid 3304,0 va (VaSet @@ -2978,5 +2953,5 @@ viewiconposition 0 ) -*86 (PortIoIn +*85 (PortIoIn uid 3310,0 shape (CompositeShape @@ -3023,5 +2998,5 @@ ) ) -*87 (PortIoIn +*86 (PortIoIn uid 3332,0 shape (CompositeShape @@ -3068,5 +3043,5 @@ ) ) -*88 (PortIoIn +*87 (PortIoIn uid 3338,0 shape (CompositeShape @@ -3113,5 +3088,5 @@ ) ) -*89 (PortIoIn +*88 (PortIoIn uid 3344,0 shape (CompositeShape @@ -3158,5 +3133,5 @@ ) ) -*90 (Net +*89 (Net uid 3374,0 decl (Decl @@ -3173,8 +3148,9 @@ ) xt "39000,3800,64000,4600" -st "A0_D : std_logic_vector(11 DOWNTO 0)" -) -) -*91 (Net +st "A0_D : std_logic_vector(11 DOWNTO 0) +" +) +) +*90 (Net uid 3376,0 decl (Decl @@ -3191,8 +3167,9 @@ ) xt "39000,4600,64000,5400" -st "A1_D : std_logic_vector(11 DOWNTO 0)" -) -) -*92 (Net +st "A1_D : std_logic_vector(11 DOWNTO 0) +" +) +) +*91 (Net uid 3378,0 decl (Decl @@ -3209,8 +3186,9 @@ ) xt "39000,5400,64000,6200" -st "A2_D : std_logic_vector(11 DOWNTO 0)" -) -) -*93 (Net +st "A2_D : std_logic_vector(11 DOWNTO 0) +" +) +) +*92 (Net uid 3380,0 decl (Decl @@ -3227,11 +3205,12 @@ ) xt "39000,6200,64000,7000" -st "A3_D : std_logic_vector(11 DOWNTO 0)" -) -) -*94 (HdlText +st "A3_D : std_logic_vector(11 DOWNTO 0) +" +) +) +*93 (HdlText uid 3394,0 optionalChildren [ -*95 (EmbeddedText +*94 (EmbeddedText uid 3400,0 commentText (CommentText @@ -3285,5 +3264,5 @@ stg "VerticalLayoutStrategy" textVec [ -*96 (Text +*95 (Text uid 3397,0 va (VaSet @@ -3295,5 +3274,5 @@ tm "HdlTextNameMgr" ) -*97 (Text +*96 (Text uid 3398,0 va (VaSet @@ -3321,5 +3300,5 @@ viewiconposition 0 ) -*98 (Net +*97 (Net uid 3460,0 decl (Decl @@ -3335,8 +3314,9 @@ ) xt "39000,16600,53500,17400" -st "D0_SRCLK : STD_LOGIC" -) -) -*99 (Net +st "D0_SRCLK : STD_LOGIC +" +) +) +*98 (Net uid 3462,0 decl (Decl @@ -3352,8 +3332,9 @@ ) xt "39000,17400,53500,18200" -st "D1_SRCLK : STD_LOGIC" -) -) -*100 (Net +st "D1_SRCLK : STD_LOGIC +" +) +) +*99 (Net uid 3464,0 decl (Decl @@ -3369,8 +3350,9 @@ ) xt "39000,18200,53500,19000" -st "D2_SRCLK : STD_LOGIC" -) -) -*101 (Net +st "D2_SRCLK : STD_LOGIC +" +) +) +*100 (Net uid 3466,0 decl (Decl @@ -3386,8 +3368,9 @@ ) xt "39000,19000,53500,19800" -st "D3_SRCLK : STD_LOGIC" -) -) -*102 (PortIoIn +st "D3_SRCLK : STD_LOGIC +" +) +) +*101 (PortIoIn uid 3476,0 shape (CompositeShape @@ -3434,5 +3417,5 @@ ) ) -*103 (PortIoIn +*102 (PortIoIn uid 3482,0 shape (CompositeShape @@ -3479,5 +3462,5 @@ ) ) -*104 (PortIoIn +*103 (PortIoIn uid 3488,0 shape (CompositeShape @@ -3524,5 +3507,5 @@ ) ) -*105 (PortIoIn +*104 (PortIoIn uid 3494,0 shape (CompositeShape @@ -3569,5 +3552,5 @@ ) ) -*106 (Net +*105 (Net uid 3500,0 decl (Decl @@ -3583,8 +3566,9 @@ ) xt "39000,7800,53500,8600" -st "D0_SROUT : std_logic" -) -) -*107 (Net +st "D0_SROUT : std_logic +" +) +) +*106 (Net uid 3502,0 decl (Decl @@ -3600,8 +3584,9 @@ ) xt "39000,8600,53500,9400" -st "D1_SROUT : std_logic" -) -) -*108 (Net +st "D1_SROUT : std_logic +" +) +) +*107 (Net uid 3504,0 decl (Decl @@ -3617,8 +3602,9 @@ ) xt "39000,9400,53500,10200" -st "D2_SROUT : std_logic" -) -) -*109 (Net +st "D2_SROUT : std_logic +" +) +) +*108 (Net uid 3506,0 decl (Decl @@ -3634,8 +3620,9 @@ ) xt "39000,10200,53500,11000" -st "D3_SROUT : std_logic" -) -) -*110 (PortIoOut +st "D3_SROUT : std_logic +" +) +) +*109 (PortIoOut uid 3508,0 shape (CompositeShape @@ -3650,5 +3637,5 @@ sl 0 ro 90 -xt "19000,108625,20500,109375" +xt "4000,133625,5500,134375" ) (Line @@ -3656,8 +3643,8 @@ sl 0 ro 90 -xt "20500,109000,21000,109000" -pts [ -"21000,109000" -"20500,109000" +xt "5500,134000,6000,134000" +pts [ +"6000,134000" +"5500,134000" ] ) @@ -3674,13 +3661,13 @@ va (VaSet ) -xt "16100,108500,18000,109500" +xt "1100,133500,3000,134500" st "D_A" ju 2 -blo "18000,109300" +blo "3000,134300" tm "WireNameMgr" ) ) ) -*111 (Net +*110 (Net uid 3514,0 decl (Decl @@ -3698,8 +3685,9 @@ ) xt "39000,22200,74000,23000" -st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0')" -) -) -*112 (PortIoOut +st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0') +" +) +) +*111 (PortIoOut uid 3516,0 shape (CompositeShape @@ -3746,5 +3734,5 @@ ) ) -*113 (Net +*112 (Net uid 3522,0 decl (Decl @@ -3761,8 +3749,9 @@ ) xt "39000,21400,68000,22200" -st "DWRITE : std_logic := '0'" -) -) -*114 (PortIoOut +st "DWRITE : std_logic := '0' +" +) +) +*113 (PortIoOut uid 3536,0 shape (CompositeShape @@ -3808,8 +3797,8 @@ ) ) -*115 (HdlText +*114 (HdlText uid 3542,0 optionalChildren [ -*116 (EmbeddedText +*115 (EmbeddedText uid 3612,0 commentText (CommentText @@ -3863,5 +3852,5 @@ stg "VerticalLayoutStrategy" textVec [ -*117 (Text +*116 (Text uid 3545,0 va (VaSet @@ -3873,5 +3862,5 @@ tm "HdlTextNameMgr" ) -*118 (Text +*117 (Text uid 3546,0 va (VaSet @@ -3899,5 +3888,5 @@ viewiconposition 0 ) -*119 (PortIoOut +*118 (PortIoOut uid 3548,0 shape (CompositeShape @@ -3943,5 +3932,5 @@ ) ) -*120 (PortIoOut +*119 (PortIoOut uid 3554,0 shape (CompositeShape @@ -3987,5 +3976,5 @@ ) ) -*121 (PortIoOut +*120 (PortIoOut uid 3560,0 shape (CompositeShape @@ -4031,5 +4020,5 @@ ) ) -*122 (PortIoOut +*121 (PortIoOut uid 3566,0 shape (CompositeShape @@ -4075,5 +4064,5 @@ ) ) -*123 (Net +*122 (Net uid 3604,0 decl (Decl @@ -4089,8 +4078,9 @@ ) xt "39000,33400,53500,34200" -st "T0_CS : std_logic" -) -) -*124 (Net +st "T0_CS : std_logic +" +) +) +*123 (Net uid 3606,0 decl (Decl @@ -4106,8 +4096,9 @@ ) xt "39000,34200,53500,35000" -st "T1_CS : std_logic" -) -) -*125 (Net +st "T1_CS : std_logic +" +) +) +*124 (Net uid 3608,0 decl (Decl @@ -4123,8 +4114,9 @@ ) xt "39000,35000,53500,35800" -st "T2_CS : std_logic" -) -) -*126 (Net +st "T2_CS : std_logic +" +) +) +*125 (Net uid 3610,0 decl (Decl @@ -4140,8 +4132,9 @@ ) xt "39000,35800,53500,36600" -st "T3_CS : std_logic" -) -) -*127 (PortIoOut +st "T3_CS : std_logic +" +) +) +*126 (PortIoOut uid 3624,0 shape (CompositeShape @@ -4187,5 +4180,5 @@ ) ) -*128 (Net +*127 (Net uid 3630,0 decl (Decl @@ -4201,8 +4194,9 @@ ) xt "39000,32600,53500,33400" -st "S_CLK : std_logic" -) -) -*129 (Net +st "S_CLK : std_logic +" +) +) +*128 (Net uid 3632,0 decl (Decl @@ -4219,8 +4213,9 @@ ) xt "39000,37400,63500,38200" -st "W_A : std_logic_vector(9 DOWNTO 0)" -) -) -*130 (Net +st "W_A : std_logic_vector(9 DOWNTO 0) +" +) +) +*129 (Net uid 3634,0 decl (Decl @@ -4237,8 +4232,9 @@ ) xt "39000,42200,64000,43000" -st "W_D : std_logic_vector(15 DOWNTO 0)" -) -) -*131 (Net +st "W_D : std_logic_vector(15 DOWNTO 0) +" +) +) +*130 (Net uid 3636,0 decl (Decl @@ -4255,8 +4251,9 @@ ) xt "39000,39800,68000,40600" -st "W_RES : std_logic := '1'" -) -) -*132 (Net +st "W_RES : std_logic := '1' +" +) +) +*131 (Net uid 3638,0 decl (Decl @@ -4273,8 +4270,9 @@ ) xt "39000,39000,68000,39800" -st "W_RD : std_logic := '1'" -) -) -*133 (Net +st "W_RD : std_logic := '1' +" +) +) +*132 (Net uid 3640,0 decl (Decl @@ -4291,8 +4289,9 @@ ) xt "39000,40600,68000,41400" -st "W_WR : std_logic := '1'" -) -) -*134 (Net +st "W_WR : std_logic := '1' +" +) +) +*133 (Net uid 3642,0 decl (Decl @@ -4308,8 +4307,9 @@ ) xt "39000,13400,53500,14200" -st "W_INT : std_logic" -) -) -*135 (Net +st "W_INT : std_logic +" +) +) +*134 (Net uid 3644,0 decl (Decl @@ -4326,8 +4326,9 @@ ) xt "39000,38200,68000,39000" -st "W_CS : std_logic := '1'" -) -) -*136 (PortIoInOut +st "W_CS : std_logic := '1' +" +) +) +*135 (PortIoInOut uid 3674,0 shape (CompositeShape @@ -4371,5 +4372,5 @@ ) ) -*137 (Net +*136 (Net uid 3680,0 decl (Decl @@ -4386,8 +4387,9 @@ ) xt "39000,26200,68000,27000" -st "MOSI : std_logic := '0'" -) -) -*138 (PortIoOut +st "MOSI : std_logic := '0' +" +) +) +*137 (PortIoOut uid 3688,0 shape (CompositeShape @@ -4433,5 +4435,5 @@ ) ) -*139 (Net +*138 (Net uid 3694,0 decl (Decl @@ -4449,11 +4451,12 @@ ) xt "39000,41400,53500,42200" -st "MISO : std_logic" -) -) -*140 (HdlText +st "MISO : std_logic +" +) +) +*139 (HdlText uid 3700,0 optionalChildren [ -*141 (EmbeddedText +*140 (EmbeddedText uid 3706,0 commentText (CommentText @@ -4522,5 +4525,5 @@ stg "VerticalLayoutStrategy" textVec [ -*142 (Text +*141 (Text uid 3703,0 va (VaSet @@ -4532,5 +4535,5 @@ tm "HdlTextNameMgr" ) -*143 (Text +*142 (Text uid 3704,0 va (VaSet @@ -4558,5 +4561,5 @@ viewiconposition 0 ) -*144 (PortIoOut +*143 (PortIoOut uid 3710,0 shape (CompositeShape @@ -4602,5 +4605,5 @@ ) ) -*145 (PortIoOut +*144 (PortIoOut uid 3716,0 shape (CompositeShape @@ -4646,5 +4649,5 @@ ) ) -*146 (PortIoOut +*145 (PortIoOut uid 3722,0 shape (CompositeShape @@ -4690,5 +4693,5 @@ ) ) -*147 (PortIoOut +*146 (PortIoOut uid 3728,0 shape (CompositeShape @@ -4734,5 +4737,5 @@ ) ) -*148 (PortIoOut +*147 (PortIoOut uid 3734,0 shape (CompositeShape @@ -4778,5 +4781,5 @@ ) ) -*149 (PortIoOut +*148 (PortIoOut uid 3740,0 shape (CompositeShape @@ -4822,5 +4825,5 @@ ) ) -*150 (PortIoOut +*149 (PortIoOut uid 3746,0 shape (CompositeShape @@ -4866,5 +4869,5 @@ ) ) -*151 (PortIoOut +*150 (PortIoOut uid 3752,0 shape (CompositeShape @@ -4910,5 +4913,5 @@ ) ) -*152 (PortIoOut +*151 (PortIoOut uid 3758,0 shape (CompositeShape @@ -4954,5 +4957,5 @@ ) ) -*153 (Net +*152 (Net uid 3864,0 decl (Decl @@ -4968,8 +4971,9 @@ ) xt "39000,36600,53500,37400" -st "TRG_V : std_logic" -) -) -*154 (Net +st "TRG_V : std_logic +" +) +) +*153 (Net uid 3866,0 decl (Decl @@ -4985,8 +4989,9 @@ ) xt "39000,28600,53500,29400" -st "RS485_C_RE : std_logic" -) -) -*155 (Net +st "RS485_C_RE : std_logic +" +) +) +*154 (Net uid 3868,0 decl (Decl @@ -5002,8 +5007,9 @@ ) xt "39000,27800,53500,28600" -st "RS485_C_DE : std_logic" -) -) -*156 (Net +st "RS485_C_DE : std_logic +" +) +) +*155 (Net uid 3870,0 decl (Decl @@ -5019,8 +5025,9 @@ ) xt "39000,30200,53500,31000" -st "RS485_E_RE : std_logic" -) -) -*157 (Net +st "RS485_E_RE : std_logic +" +) +) +*156 (Net uid 3872,0 decl (Decl @@ -5036,8 +5043,9 @@ ) xt "39000,29400,53500,30200" -st "RS485_E_DE : std_logic" -) -) -*158 (Net +st "RS485_E_DE : std_logic +" +) +) +*157 (Net uid 3874,0 decl (Decl @@ -5054,8 +5062,9 @@ ) xt "39000,20600,68000,21400" -st "DENABLE : std_logic := '0'" -) -) -*159 (Net +st "DENABLE : std_logic := '0' +" +) +) +*158 (Net uid 3876,0 decl (Decl @@ -5071,8 +5080,9 @@ ) xt "39000,31800,53500,32600" -st "SRIN : std_logic" -) -) -*160 (Net +st "SRIN : std_logic +" +) +) +*159 (Net uid 3878,0 decl (Decl @@ -5088,8 +5098,9 @@ ) xt "39000,24600,53500,25400" -st "EE_CS : std_logic" -) -) -*161 (Net +st "EE_CS : std_logic +" +) +) +*160 (Net uid 3880,0 decl (Decl @@ -5107,8 +5118,9 @@ ) xt "39000,25400,74000,26200" -st "LED : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')" -) -) -*162 (PortIoOut +st "LED : std_logic_vector( 2 DOWNTO 0 ) := (others => '1') +" +) +) +*161 (PortIoOut uid 3995,0 shape (CompositeShape @@ -5155,5 +5167,5 @@ ) ) -*163 (PortIoOut +*162 (PortIoOut uid 4001,0 shape (CompositeShape @@ -5200,5 +5212,5 @@ ) ) -*164 (PortIoOut +*163 (PortIoOut uid 4007,0 shape (CompositeShape @@ -5245,5 +5257,5 @@ ) ) -*165 (PortIoOut +*164 (PortIoOut uid 4013,0 shape (CompositeShape @@ -5290,5 +5302,5 @@ ) ) -*166 (PortIoOut +*165 (PortIoOut uid 4916,0 shape (CompositeShape @@ -5334,5 +5346,5 @@ ) ) -*167 (Net +*166 (Net uid 5320,0 decl (Decl @@ -5350,8 +5362,9 @@ ) xt "39000,23000,74000,23800" -st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" -) -) -*168 (PortIoIn +st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') +" +) +) +*167 (PortIoIn uid 5650,0 shape (CompositeShape @@ -5366,5 +5379,5 @@ sl 0 ro 270 -xt "-30000,88625,-28500,89375" +xt "9000,78625,10500,79375" ) (Line @@ -5372,8 +5385,8 @@ sl 0 ro 270 -xt "-28500,89000,-28000,89000" -pts [ -"-28500,89000" -"-28000,89000" +xt "10500,79000,11000,79000" +pts [ +"10500,79000" +"11000,79000" ] ) @@ -5390,13 +5403,13 @@ va (VaSet ) -xt "-35500,88500,-31000,89500" +xt "3500,78500,8000,79500" st "TEST_TRG" ju 2 -blo "-31000,89300" +blo "8000,79300" tm "WireNameMgr" ) ) ) -*169 (Net +*168 (Net uid 5662,0 decl (Decl @@ -5412,8 +5425,9 @@ ) xt "39000,11800,53500,12600" -st "TEST_TRG : std_logic" -) -) -*170 (Net +st "TEST_TRG : std_logic +" +) +) +*169 (Net uid 6138,0 decl (Decl @@ -5429,502 +5443,15 @@ ) xt "39000,46400,57000,47200" -st "SIGNAL TRG_OR : std_logic" -) -) -*171 (SaComponent -uid 6250,0 -optionalChildren [ -*172 (CptPort -uid 6235,0 -ps "OnEdgeStrategy" -shape (Triangle -uid 6236,0 -ro 90 -va (VaSet -vasetType 1 -fg "0,65535,0" -) -xt "-11750,87625,-11000,88375" -) -tg (CPTG -uid 6237,0 -ps "CptPortTextPlaceStrategy" -stg "VerticalLayoutStrategy" -f (Text -uid 6238,0 -va (VaSet -) -xt "-10000,87500,-8700,88500" -st "clk" -blo "-10000,88300" -) -) -thePort (LogicalPort -decl (Decl -n "clk" -t "STD_LOGIC" -preAdd 0 -posAdd 0 -o 1 -suid 1,0 -) -) -) -*173 (CptPort -uid 6239,0 -ps "OnEdgeStrategy" -shape (Triangle -uid 6240,0 -ro 90 -va (VaSet -vasetType 1 -fg "0,65535,0" -) -xt "-11750,88625,-11000,89375" -) -tg (CPTG -uid 6241,0 -ps "CptPortTextPlaceStrategy" -stg "VerticalLayoutStrategy" -f (Text -uid 6242,0 -va (VaSet -) -xt "-10000,88500,-5800,89500" -st "trigger_in" -blo "-10000,89300" -) -) -thePort (LogicalPort -decl (Decl -n "trigger_in" -t "STD_LOGIC" -prec "-- rst : in STD_LOGIC;" -preAdd 0 -posAdd 0 -o 2 -suid 2,0 -) -) -) -*174 (CptPort -uid 6243,0 -ps "OnEdgeStrategy" -shape (Triangle -uid 6244,0 -ro 90 -va (VaSet -vasetType 1 -fg "0,65535,0" -) -xt "1000,88625,1750,89375" -) -tg (CPTG -uid 6245,0 -ps "CptPortTextPlaceStrategy" -stg "RightVerticalLayoutStrategy" -f (Text -uid 6246,0 -va (VaSet -) -xt "-4600,88500,0,89500" -st "trigger_out" -ju 2 -blo "0,89300" -) -) -thePort (LogicalPort -m 1 -decl (Decl -n "trigger_out" -t "STD_LOGIC" -preAdd 0 -posAdd 0 -o 3 -suid 3,0 -i "'0'" -) -) -) -] -shape (Rectangle -uid 6251,0 -va (VaSet -vasetType 1 -fg "0,65535,0" -lineColor "0,32896,0" -lineWidth 2 -) -xt "-11000,87000,1000,92000" -) -oxt "25000,13000,37000,18000" -ttg (MlTextGroup -uid 6252,0 -ps "CenterOffsetStrategy" -stg "VerticalLayoutStrategy" -textVec [ -*175 (Text -uid 6253,0 -va (VaSet -font "Arial,8,1" -) -xt "-10800,92000,-4200,93000" -st "FACT_FAD_LIB" -blo "-10800,92800" -tm "BdLibraryNameMgr" -) -*176 (Text -uid 6254,0 -va (VaSet -font "Arial,8,1" -) -xt "-10800,93000,-6400,94000" -st "debouncer" -blo "-10800,93800" -tm "CptNameMgr" -) -*177 (Text -uid 6255,0 -va (VaSet -font "Arial,8,1" -) -xt "-10800,94000,-5400,95000" -st "I_debouncer" -blo "-10800,94800" -tm "InstanceNameMgr" -) -] -) -ga (GenericAssociation -uid 6256,0 -ps "EdgeToEdgeStrategy" -matrix (Matrix -uid 6257,0 -text (MLText -uid 6258,0 -va (VaSet -font "Courier New,8,0" -) -xt "-11000,86200,4000,87000" -st "WIDTH = 17 ( INTEGER ) " -) -header "" -) -elements [ -(GiElement -name "WIDTH" -type "INTEGER" -value "17" -) -] -) -viewicon (ZoomableIcon -uid 6259,0 -sl 0 -va (VaSet -vasetType 1 -fg "49152,49152,49152" -) -xt "-10750,90250,-9250,91750" -iconName "VhdlFileViewIcon.png" -iconMaskName "VhdlFileViewIcon.msk" -ftype 10 -) -ordering 1 -viewiconposition 0 -portVis (PortSigDisplay -) -archFileType "UNKNOWN" -) -*178 (Net -uid 6278,0 -decl (Decl -n "trigger_out" -t "STD_LOGIC" -preAdd 0 -posAdd 0 -o 60 -suid 147,0 -i "'0'" -) -declText (MLText -uid 6279,0 -va (VaSet -font "Courier New,8,0" -) -xt "39000,52000,71500,52800" -st "SIGNAL trigger_out : STD_LOGIC := '0'" -) -) -*179 (Net -uid 6326,0 -decl (Decl -n "not_TEST_TRG" -t "STD_LOGIC" -o 58 -suid 148,0 -) -declText (MLText -uid 6327,0 -va (VaSet -font "Courier New,8,0" -) -xt "39000,50400,57000,51200" -st "SIGNAL not_TEST_TRG : STD_LOGIC" -) -) -*180 (MWC -uid 6539,0 -optionalChildren [ -*181 (CptPort -uid 6526,0 -optionalChildren [ -*182 (Line -uid 6530,0 -layer 5 -sl 0 -va (VaSet -vasetType 3 -) -xt "-22000,89000,-20999,89000" -pts [ -"-22000,89000" -"-20999,89000" -] -) -] -ps "OnEdgeStrategy" -shape (Triangle -uid 6527,0 -ro 90 -va (VaSet -vasetType 1 -isHidden 1 -fg "0,65535,65535" -) -xt "-22750,88625,-22000,89375" -) -tg (CPTG -uid 6528,0 -ps "CptPortTextPlaceStrategy" -stg "VerticalLayoutStrategy" -f (Text -uid 6529,0 -sl 0 -va (VaSet -isHidden 1 -font "arial,8,0" -) -xt "-25000,88500,-23600,89500" -st "din" -blo "-25000,89300" -) -s (Text -uid 6548,0 -sl 0 -va (VaSet -font "arial,8,0" -) -xt "-25000,89500,-25000,89500" -blo "-25000,89500" -) -) -thePort (LogicalPort -decl (Decl -n "din" -t "std_logic" -o 11 -suid 1,0 -) -) -) -*183 (CptPort -uid 6531,0 -optionalChildren [ -*184 (Line -uid 6535,0 -layer 5 -sl 0 -va (VaSet -vasetType 3 -) -xt "-17249,89000,-17000,89000" -pts [ -"-17000,89000" -"-17249,89000" -] -) -*185 (Circle -uid 6536,0 -va (VaSet -vasetType 1 -fg "65535,65535,65535" -lineColor "26368,26368,26368" -) -xt "-17999,88625,-17249,89375" -radius 375 -) -] -ps "OnEdgeStrategy" -shape (Triangle -uid 6532,0 -ro 90 -va (VaSet -vasetType 1 -isHidden 1 -fg "0,65535,65535" -) -xt "-17000,88625,-16250,89375" -) -tg (CPTG -uid 6533,0 -ps "CptPortTextPlaceStrategy" -stg "RightVerticalLayoutStrategy" -f (Text -uid 6534,0 -sl 0 -va (VaSet -isHidden 1 -font "arial,8,0" -) -xt "-15050,88500,-13250,89500" -st "dout" -ju 2 -blo "-13250,89300" -) -s (Text -uid 6549,0 -sl 0 -va (VaSet -font "arial,8,0" -) -xt "-13250,89500,-13250,89500" -ju 2 -blo "-13250,89500" -) -) -thePort (LogicalPort -m 1 -decl (Decl -n "dout" -t "STD_LOGIC" -o 58 -suid 2,0 -) -) -) -*186 (CommentGraphic -uid 6537,0 -shape (CustomPolygon -pts [ -"-21000,87000" -"-18000,89000" -"-21000,91000" -"-21000,87000" -] -uid 6538,0 -layer 0 -sl 0 -va (VaSet -vasetType 1 -fg "0,65535,65535" -bg "0,65535,65535" -lineColor "26368,26368,26368" -) -xt "-21000,87000,-18000,91000" -) -oxt "7000,6000,10000,10000" -) -] -shape (Rectangle -uid 6540,0 -va (VaSet -vasetType 1 -transparent 1 -fg "0,65535,0" -lineColor "65535,65535,65535" -lineWidth -1 -) -xt "-22000,87000,-17000,91000" -fos 1 -) -showPorts 0 -oxt "6000,6000,11000,10000" -ttg (MlTextGroup -uid 6541,0 -ps "CenterOffsetStrategy" -stg "VerticalLayoutStrategy" -textVec [ -*187 (Text -uid 6542,0 -va (VaSet -isHidden 1 -font "arial,8,0" -) -xt "-19650,89100,-14850,90100" -st "moduleware" -blo "-19650,89900" -) -*188 (Text -uid 6543,0 -va (VaSet -font "arial,8,0" -) -xt "-19650,90100,-18350,91100" -st "inv" -blo "-19650,90900" -) -*189 (Text -uid 6544,0 -va (VaSet -font "arial,8,0" -) -xt "-19650,91100,-18650,92100" -st "I1" -blo "-19650,91900" -tm "InstanceNameMgr" -) -] -) -ga (GenericAssociation -uid 6545,0 -ps "EdgeToEdgeStrategy" -matrix (Matrix -uid 6546,0 -text (MLText -uid 6547,0 -va (VaSet -font "arial,8,0" -) -xt "-25000,68400,-25000,68400" -) -header "" -) -elements [ -] -) -sed 1 -awe 1 -portVis (PortSigDisplay -disp 1 -sN 0 -sTC 0 -selT 0 -) -prms (Property -pclass "params" -pname "params" -ptn "String" -) -visOptions (mwParamsVisibilityOptions -) -) -*190 (MWC +st "SIGNAL TRG_OR : std_logic +" +) +) +*170 (MWC uid 6586,0 optionalChildren [ -*191 (CptPort +*171 (CptPort uid 6550,0 optionalChildren [ -*192 (Line +*172 (Line uid 6554,0 layer 5 @@ -5970,17 +5497,14 @@ decl (Decl n "din1" -t "STD_LOGIC" -preAdd 0 -posAdd 0 -o 60 +t "std_logic" +o 11 suid 1,0 -i "'0'" -) -) -) -*193 (CptPort +) +) +) +*173 (CptPort uid 6555,0 optionalChildren [ -*194 (Property +*174 (Property uid 6559,0 pclass "_MW_GEOM_" @@ -5988,5 +5512,5 @@ ptn "String" ) -*195 (Line +*175 (Line uid 6560,0 layer 5 @@ -6040,8 +5564,8 @@ ) ) -*196 (CptPort +*176 (CptPort uid 6561,0 optionalChildren [ -*197 (Line +*177 (Line uid 6565,0 layer 5 @@ -6093,5 +5617,5 @@ ) ) -*198 (CommentGraphic +*178 (CommentGraphic uid 6566,0 shape (Arc2D @@ -6114,5 +5638,5 @@ oxt "7000,6003,11000,8000" ) -*199 (CommentGraphic +*179 (CommentGraphic uid 6568,0 shape (Arc2D @@ -6135,11 +5659,11 @@ oxt "6996,8005,11000,10000" ) -*200 (Grouping +*180 (Grouping uid 6570,0 optionalChildren [ -*201 (CommentGraphic +*181 (CommentGraphic uid 6572,0 optionalChildren [ -*202 (Property +*182 (Property uid 6574,0 pclass "_MW_GEOM_" @@ -6172,8 +5696,8 @@ oxt "7000,6000,11000,9998" ) -*203 (CommentGraphic +*183 (CommentGraphic uid 6575,0 optionalChildren [ -*204 (Property +*184 (Property uid 6577,0 pclass "_MW_GEOM_" @@ -6217,5 +5741,5 @@ oxt "7000,6000,11000,10000" ) -*205 (CommentGraphic +*185 (CommentGraphic uid 6578,0 shape (PolyLine2D @@ -6236,8 +5760,8 @@ oxt "11000,8000,11000,8000" ) -*206 (CommentGraphic +*186 (CommentGraphic uid 6580,0 optionalChildren [ -*207 (Property +*187 (Property uid 6582,0 pclass "_MW_GEOM_" @@ -6263,8 +5787,8 @@ oxt "7000,6000,7000,6000" ) -*208 (CommentGraphic +*188 (CommentGraphic uid 6583,0 optionalChildren [ -*209 (Property +*189 (Property uid 6585,0 pclass "_MW_GEOM_" @@ -6309,5 +5833,5 @@ stg "VerticalLayoutStrategy" textVec [ -*210 (Text +*190 (Text uid 6589,0 va (VaSet @@ -6319,5 +5843,5 @@ blo "15500,77300" ) -*211 (Text +*191 (Text uid 6590,0 va (VaSet @@ -6328,5 +5852,5 @@ blo "15500,78300" ) -*212 (Text +*192 (Text uid 6591,0 va (VaSet @@ -6373,5 +5897,5 @@ ) ) -*213 (PortIoIn +*193 (PortIoIn uid 6781,0 shape (CompositeShape @@ -6418,5 +5942,5 @@ ) ) -*214 (Net +*194 (Net uid 6793,0 decl (Decl @@ -6433,8 +5957,9 @@ ) xt "39000,11000,63500,11800" -st "D_PLLLCK : std_logic_vector(3 DOWNTO 0)" -) -) -*215 (PortIoOut +st "D_PLLLCK : std_logic_vector(3 DOWNTO 0) +" +) +) +*195 (PortIoOut uid 6874,0 shape (CompositeShape @@ -6480,5 +6005,5 @@ ) ) -*216 (Net +*196 (Net uid 6886,0 decl (Decl @@ -6496,11 +6021,12 @@ ) xt "39000,23800,74000,24600" -st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0')" -) -) -*217 (HdlText +st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0') +" +) +) +*197 (HdlText uid 6888,0 optionalChildren [ -*218 (EmbeddedText +*198 (EmbeddedText uid 6894,0 commentText (CommentText @@ -6550,5 +6076,5 @@ stg "VerticalLayoutStrategy" textVec [ -*219 (Text +*199 (Text uid 6891,0 va (VaSet @@ -6560,5 +6086,5 @@ tm "HdlTextNameMgr" ) -*220 (Text +*200 (Text uid 6892,0 va (VaSet @@ -6586,8 +6112,8 @@ viewiconposition 0 ) -*221 (HdlText +*201 (HdlText uid 7092,0 optionalChildren [ -*222 (EmbeddedText +*202 (EmbeddedText uid 7098,0 commentText (CommentText @@ -6602,5 +6128,5 @@ lineWidth 2 ) -xt "27000,137000,45000,145000" +xt "26000,137000,46000,143000" ) oxt "0,0,18000,5000" @@ -6609,16 +6135,15 @@ va (VaSet ) -xt "27200,137200,39400,142200" +xt "26200,137200,40000,141200" st " -- eb2 8 -A1_T(0) <= dummy; -A1_T(1) <= RSRLOAD; -A1_T(2) <= D0_SROUT; -A1_T(3) <= D1_SROUT; +A1_T(3 downto 0) <= drs_channel_id; +D_A <= drs_channel_id; +A1_T(4) <= TRG_OR; " tm "HdlTextMgr" wrapOption 3 -visibleHeight 8000 -visibleWidth 18000 +visibleHeight 6000 +visibleWidth 20000 ) ) @@ -6641,5 +6166,5 @@ stg "VerticalLayoutStrategy" textVec [ -*223 (Text +*203 (Text uid 7095,0 va (VaSet @@ -6651,5 +6176,5 @@ tm "HdlTextNameMgr" ) -*224 (Text +*204 (Text uid 7096,0 va (VaSet @@ -6677,5 +6202,5 @@ viewiconposition 0 ) -*225 (PortIoOut +*205 (PortIoOut uid 7138,0 shape (CompositeShape @@ -6721,12 +6246,13 @@ ) ) -*226 (Net +*206 (Net uid 7150,0 decl (Decl n "A1_T" t "std_logic_vector" -b "(3 DOWNTO 0)" +b "(7 DOWNTO 0)" o 15 suid 155,0 +i "(OTHERS => '0')" ) declText (MLText @@ -6735,14 +6261,15 @@ font "Courier New,8,0" ) -xt "39000,15000,63500,15800" -st "A1_T : std_logic_vector(3 DOWNTO 0)" -) -) -*227 (Net +xt "39000,15000,74000,15800" +st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') +" +) +) +*207 (Net uid 7485,0 decl (Decl n "dummy" t "std_logic" -o 60 +o 58 suid 157,0 ) @@ -6752,15 +6279,16 @@ font "Courier New,8,0" ) -xt "39000,49600,57000,50400" -st "SIGNAL dummy : std_logic" -) -) -*228 (MWC +xt "39000,50400,57000,51200" +st "SIGNAL dummy : std_logic +" +) +) +*208 (MWC uid 7652,0 optionalChildren [ -*229 (CptPort +*209 (CptPort uid 7632,0 optionalChildren [ -*230 (Line +*210 (Line uid 7636,0 layer 5 @@ -6816,13 +6344,13 @@ n "s" t "std_logic" -o 60 +o 58 suid 1,0 ) ) ) -*231 (CptPort +*211 (CptPort uid 7637,0 optionalChildren [ -*232 (Line +*212 (Line uid 7641,0 layer 5 @@ -6886,5 +6414,5 @@ ) ) -*233 (CommentGraphic +*213 (CommentGraphic uid 7642,0 shape (PolyLine2D @@ -6907,5 +6435,5 @@ oxt "6000,6000,7000,7000" ) -*234 (CommentGraphic +*214 (CommentGraphic uid 7644,0 shape (PolyLine2D @@ -6928,5 +6456,5 @@ oxt "6000,7000,7000,8000" ) -*235 (CommentGraphic +*215 (CommentGraphic uid 7646,0 shape (PolyLine2D @@ -6949,5 +6477,5 @@ oxt "6988,7329,7988,7329" ) -*236 (CommentGraphic +*216 (CommentGraphic uid 7648,0 shape (PolyLine2D @@ -6968,5 +6496,5 @@ oxt "8000,7000,9000,7000" ) -*237 (CommentGraphic +*217 (CommentGraphic uid 7650,0 shape (PolyLine2D @@ -7009,5 +6537,5 @@ stg "VerticalLayoutStrategy" textVec [ -*238 (Text +*218 (Text uid 7655,0 va (VaSet @@ -7019,5 +6547,5 @@ blo "90350,83900" ) -*239 (Text +*219 (Text uid 7656,0 va (VaSet @@ -7028,5 +6556,5 @@ blo "90350,84900" ) -*240 (Text +*220 (Text uid 7657,0 va (VaSet @@ -7073,5 +6601,43 @@ ) ) -*241 (Wire +*221 (Net +uid 8851,0 +decl (Decl +n "drs_channel_id" +t "std_logic_vector" +b "(3 downto 0)" +o 57 +suid 159,0 +i "(others => '0')" +) +declText (MLText +uid 8852,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,49600,77500,50400" +st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') +" +) +) +*222 (Net +uid 9500,0 +decl (Decl +n "CLK_50" +t "std_logic" +o 51 +suid 163,0 +) +declText (MLText +uid 9501,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,44800,57000,45600" +st "SIGNAL CLK_50 : std_logic +" +) +) +*223 (Wire uid 245,0 shape (OrthoPolyLine @@ -7110,7 +6676,7 @@ ) ) -on &70 -) -*242 (Wire +on &69 +) +*224 (Wire uid 277,0 shape (OrthoPolyLine @@ -7150,5 +6716,5 @@ on &53 ) -*243 (Wire +*225 (Wire uid 285,0 shape (OrthoPolyLine @@ -7188,5 +6754,5 @@ on &54 ) -*244 (Wire +*226 (Wire uid 362,0 shape (OrthoPolyLine @@ -7201,5 +6767,5 @@ ] ) -start &78 +start &77 end &16 sat 32 @@ -7224,7 +6790,7 @@ ) ) -on &79 -) -*245 (Wire +on &78 +) +*227 (Wire uid 418,0 shape (OrthoPolyLine @@ -7262,7 +6828,7 @@ ) ) -on &131 -) -*246 (Wire +on &130 +) +*228 (Wire uid 426,0 shape (OrthoPolyLine @@ -7302,7 +6868,7 @@ ) ) -on &129 -) -*247 (Wire +on &128 +) +*229 (Wire uid 434,0 shape (OrthoPolyLine @@ -7340,7 +6906,7 @@ ) ) -on &135 -) -*248 (Wire +on &134 +) +*230 (Wire uid 442,0 shape (OrthoPolyLine @@ -7380,7 +6946,7 @@ ) ) -on &130 -) -*249 (Wire +on &129 +) +*231 (Wire uid 450,0 shape (OrthoPolyLine @@ -7418,7 +6984,7 @@ ) ) -on &134 -) -*250 (Wire +on &133 +) +*232 (Wire uid 458,0 shape (OrthoPolyLine @@ -7456,7 +7022,7 @@ ) ) -on &132 -) -*251 (Wire +on &131 +) +*233 (Wire uid 466,0 shape (OrthoPolyLine @@ -7494,7 +7060,7 @@ ) ) -on &133 -) -*252 (Wire +on &132 +) +*234 (Wire uid 1467,0 shape (OrthoPolyLine @@ -7509,5 +7075,5 @@ ] ) -start &82 +start &81 end &28 sat 2 @@ -7532,5 +7098,5 @@ on &62 ) -*253 (Wire +*235 (Wire uid 1730,0 shape (OrthoPolyLine @@ -7546,5 +7112,5 @@ ] ) -start &80 +start &79 end &29 sat 32 @@ -7570,7 +7136,7 @@ ) ) -on &81 -) -*254 (Wire +on &80 +) +*236 (Wire uid 1833,0 shape (OrthoPolyLine @@ -7580,13 +7146,13 @@ lineWidth 2 ) -xt "21000,109000,51250,109000" -pts [ -"51250,109000" -"21000,109000" -] -) -start &30 -end &110 -sat 32 +xt "6000,134000,31000,134000" +pts [ +"31000,134000" +"6000,134000" +] +) +start &201 +end &109 +sat 2 eat 32 sty 1 @@ -7604,13 +7170,13 @@ isHidden 1 ) -xt "22000,108000,23900,109000" +xt "7000,133000,8900,134000" st "D_A" -blo "22000,108800" +blo "7000,133800" tm "WireNameMgr" ) ) -on &111 -) -*255 (Wire +on &110 +) +*237 (Wire uid 1841,0 shape (OrthoPolyLine @@ -7626,5 +7192,5 @@ ) start &31 -end &112 +end &111 sat 32 eat 32 @@ -7648,7 +7214,7 @@ ) ) -on &113 -) -*256 (Wire +on &112 +) +*238 (Wire uid 1865,0 shape (OrthoPolyLine @@ -7663,5 +7229,5 @@ ] ) -start &102 +start &101 end &32 sat 32 @@ -7686,7 +7252,7 @@ ) ) -on &106 -) -*257 (Wire +on &105 +) +*239 (Wire uid 1873,0 shape (OrthoPolyLine @@ -7701,5 +7267,5 @@ ] ) -start &103 +start &102 end &33 sat 32 @@ -7724,7 +7290,7 @@ ) ) -on &107 -) -*258 (Wire +on &106 +) +*240 (Wire uid 1881,0 shape (OrthoPolyLine @@ -7739,5 +7305,5 @@ ] ) -start &104 +start &103 end &34 sat 32 @@ -7762,7 +7328,7 @@ ) ) -on &108 -) -*259 (Wire +on &107 +) +*241 (Wire uid 1889,0 shape (OrthoPolyLine @@ -7777,5 +7343,5 @@ ] ) -start &105 +start &104 end &35 sat 32 @@ -7800,47 +7366,7 @@ ) ) -on &109 -) -*260 (Wire -uid 2269,0 -shape (OrthoPolyLine -uid 2270,0 -va (VaSet -vasetType 3 -) -xt "-15000,69000,51250,88000" -pts [ -"51250,69000" -"-15000,69000" -"-15000,88000" -"-11750,88000" -] -) -start &26 -end &172 -sat 32 -eat 32 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 2273,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 2274,0 -va (VaSet -isHidden 1 -) -xt "50250,68000,53350,69000" -st "CLK_50" -blo "50250,68800" -tm "WireNameMgr" -) -) -on &63 -) -*261 (Wire +on &108 +) +*242 (Wire uid 2409,0 shape (OrthoPolyLine @@ -7856,5 +7382,5 @@ ) start &36 -end &65 +end &64 sat 32 eat 32 @@ -7878,7 +7404,7 @@ ) ) -on &64 -) -*262 (Wire +on &63 +) +*243 (Wire uid 2423,0 shape (OrthoPolyLine @@ -7894,5 +7420,5 @@ ) start &37 -end &94 +end &93 sat 32 eat 1 @@ -7916,7 +7442,7 @@ ) ) -on &66 -) -*263 (Wire +on &65 +) +*244 (Wire uid 3009,0 shape (OrthoPolyLine @@ -7932,5 +7458,5 @@ ) start &39 -end &127 +end &126 sat 32 eat 32 @@ -7954,7 +7480,7 @@ ) ) -on &128 -) -*264 (Wire +on &127 +) +*245 (Wire uid 3015,0 shape (OrthoPolyLine @@ -7970,5 +7496,5 @@ ) start &41 -end &136 +end &135 sat 32 eat 32 @@ -7992,7 +7518,7 @@ ) ) -on &139 -) -*265 (Wire +on &138 +) +*246 (Wire uid 3021,0 shape (OrthoPolyLine @@ -8009,5 +7535,5 @@ ) start &40 -end &115 +end &114 sat 32 eat 1 @@ -8030,7 +7556,7 @@ ) ) -on &67 -) -*266 (Wire +on &66 +) +*247 (Wire uid 3027,0 shape (OrthoPolyLine @@ -8045,6 +7571,6 @@ ] ) -start &231 -end &114 +start &211 +end &113 ss 0 sat 32 @@ -8069,7 +7595,7 @@ ) ) -on &68 -) -*267 (Wire +on &67 +) +*248 (Wire uid 3218,0 shape (OrthoPolyLine @@ -8085,5 +7611,5 @@ ) start &47 -end &196 +end &176 sat 32 eat 32 @@ -8107,7 +7633,7 @@ ) ) -on &71 -) -*268 (Wire +on &70 +) +*249 (Wire uid 3260,0 shape (OrthoPolyLine @@ -8123,6 +7649,6 @@ ] ) -start &69 -end &72 +start &68 +end &71 sat 32 eat 2 @@ -8147,7 +7673,7 @@ ) ) -on &76 -) -*269 (Wire +on &75 +) +*250 (Wire uid 3270,0 shape (OrthoPolyLine @@ -8163,5 +7689,5 @@ ) start &25 -end &72 +end &71 sat 32 eat 1 @@ -8183,7 +7709,7 @@ ) ) -on &77 -) -*270 (Wire +on &76 +) +*251 (Wire uid 3318,0 shape (OrthoPolyLine @@ -8199,6 +7725,6 @@ ] ) -start &86 -end &82 +start &85 +end &81 sat 32 eat 1 @@ -8223,7 +7749,7 @@ ) ) -on &90 -) -*271 (Wire +on &89 +) +*252 (Wire uid 3352,0 shape (OrthoPolyLine @@ -8239,6 +7765,6 @@ ] ) -start &87 -end &82 +start &86 +end &81 sat 32 eat 1 @@ -8263,7 +7789,7 @@ ) ) -on &91 -) -*272 (Wire +on &90 +) +*253 (Wire uid 3360,0 shape (OrthoPolyLine @@ -8279,6 +7805,6 @@ ] ) -start &88 -end &82 +start &87 +end &81 sat 32 eat 1 @@ -8303,7 +7829,7 @@ ) ) -on &92 -) -*273 (Wire +on &91 +) +*254 (Wire uid 3368,0 shape (OrthoPolyLine @@ -8319,6 +7845,6 @@ ] ) -start &89 -end &82 +start &88 +end &81 sat 32 eat 1 @@ -8343,7 +7869,7 @@ ) ) -on &93 -) -*274 (Wire +on &92 +) +*255 (Wire uid 3430,0 shape (OrthoPolyLine @@ -8358,6 +7884,6 @@ ] ) -start &162 -end &94 +start &161 +end &93 sat 32 eat 2 @@ -8381,7 +7907,7 @@ ) ) -on &98 -) -*275 (Wire +on &97 +) +*256 (Wire uid 3438,0 shape (OrthoPolyLine @@ -8396,6 +7922,6 @@ ] ) -start &163 -end &94 +start &162 +end &93 sat 32 eat 2 @@ -8419,7 +7945,7 @@ ) ) -on &99 -) -*276 (Wire +on &98 +) +*257 (Wire uid 3446,0 shape (OrthoPolyLine @@ -8434,6 +7960,6 @@ ] ) -start &164 -end &94 +start &163 +end &93 sat 32 eat 2 @@ -8457,7 +7983,7 @@ ) ) -on &100 -) -*277 (Wire +on &99 +) +*258 (Wire uid 3454,0 shape (OrthoPolyLine @@ -8472,6 +7998,6 @@ ] ) -start &165 -end &94 +start &164 +end &93 sat 32 eat 2 @@ -8495,7 +8021,7 @@ ) ) -on &101 -) -*278 (Wire +on &100 +) +*259 (Wire uid 3574,0 shape (OrthoPolyLine @@ -8510,6 +8036,6 @@ ] ) -start &119 -end &115 +start &118 +end &114 sat 32 eat 2 @@ -8533,7 +8059,7 @@ ) ) -on &123 -) -*279 (Wire +on &122 +) +*260 (Wire uid 3582,0 shape (OrthoPolyLine @@ -8548,6 +8074,6 @@ ] ) -start &120 -end &115 +start &119 +end &114 sat 32 eat 2 @@ -8571,7 +8097,7 @@ ) ) -on &124 -) -*280 (Wire +on &123 +) +*261 (Wire uid 3590,0 shape (OrthoPolyLine @@ -8586,6 +8112,6 @@ ] ) -start &121 -end &115 +start &120 +end &114 sat 32 eat 2 @@ -8609,7 +8135,7 @@ ) ) -on &125 -) -*281 (Wire +on &124 +) +*262 (Wire uid 3598,0 shape (OrthoPolyLine @@ -8624,6 +8150,6 @@ ] ) -start &122 -end &115 +start &121 +end &114 sat 32 eat 2 @@ -8647,7 +8173,7 @@ ) ) -on &126 -) -*282 (Wire +on &125 +) +*263 (Wire uid 3682,0 shape (OrthoPolyLine @@ -8663,5 +8189,5 @@ ) start &42 -end &138 +end &137 sat 32 eat 32 @@ -8685,7 +8211,7 @@ ) ) -on &137 -) -*283 (Wire +on &136 +) +*264 (Wire uid 3778,0 shape (OrthoPolyLine @@ -8700,6 +8226,6 @@ ] ) -start &144 -end &140 +start &143 +end &139 sat 32 eat 2 @@ -8723,7 +8249,7 @@ ) ) -on &153 -) -*284 (Wire +on &152 +) +*265 (Wire uid 3786,0 shape (OrthoPolyLine @@ -8738,6 +8264,6 @@ ] ) -start &145 -end &140 +start &144 +end &139 sat 32 eat 2 @@ -8761,7 +8287,7 @@ ) ) -on &154 -) -*285 (Wire +on &153 +) +*266 (Wire uid 3794,0 shape (OrthoPolyLine @@ -8776,6 +8302,6 @@ ] ) -start &146 -end &140 +start &145 +end &139 sat 32 eat 2 @@ -8799,7 +8325,7 @@ ) ) -on &155 -) -*286 (Wire +on &154 +) +*267 (Wire uid 3802,0 shape (OrthoPolyLine @@ -8814,6 +8340,6 @@ ] ) -start &147 -end &140 +start &146 +end &139 sat 32 eat 2 @@ -8837,7 +8363,7 @@ ) ) -on &156 -) -*287 (Wire +on &155 +) +*268 (Wire uid 3810,0 shape (OrthoPolyLine @@ -8852,6 +8378,6 @@ ] ) -start &148 -end &140 +start &147 +end &139 sat 32 eat 2 @@ -8875,7 +8401,7 @@ ) ) -on &157 -) -*288 (Wire +on &156 +) +*269 (Wire uid 3826,0 shape (OrthoPolyLine @@ -8890,6 +8416,6 @@ ] ) -start &150 -end &140 +start &149 +end &139 sat 32 eat 2 @@ -8913,7 +8439,7 @@ ) ) -on &159 -) -*289 (Wire +on &158 +) +*270 (Wire uid 3834,0 shape (OrthoPolyLine @@ -8928,6 +8454,6 @@ ] ) -start &151 -end &140 +start &150 +end &139 sat 32 eat 2 @@ -8951,7 +8477,7 @@ ) ) -on &160 -) -*290 (Wire +on &159 +) +*271 (Wire uid 3842,0 shape (OrthoPolyLine @@ -8967,6 +8493,6 @@ ] ) -start &152 -end &140 +start &151 +end &139 sat 32 eat 2 @@ -8991,7 +8517,7 @@ ) ) -on &161 -) -*291 (Wire +on &160 +) +*272 (Wire uid 4942,0 shape (OrthoPolyLine @@ -9008,5 +8534,5 @@ ) start &14 -end &166 +end &165 sat 32 eat 32 @@ -9031,7 +8557,7 @@ ) ) -on &167 -) -*292 (Wire +on &166 +) +*273 (Wire uid 6130,0 shape (OrthoPolyLine @@ -9046,5 +8572,5 @@ ] ) -start &193 +start &173 end &15 sat 32 @@ -9067,46 +8593,7 @@ ) ) -on &170 -) -*293 (Wire -uid 6288,0 -shape (OrthoPolyLine -uid 6289,0 -va (VaSet -vasetType 3 -) -xt "1750,79000,13000,89000" -pts [ -"1750,89000" -"9000,89000" -"9000,86000" -"9000,79000" -"13000,79000" -] -) -start &174 -end &191 -sat 32 -eat 32 -st 0 -sf 1 -si 0 -tg (WTG -uid 6294,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 6295,0 -va (VaSet -) -xt "4000,88000,8600,89000" -st "trigger_out" -blo "4000,88800" -tm "WireNameMgr" -) -) -on &178 -) -*294 (Wire +on &169 +) +*274 (Wire uid 6306,0 shape (OrthoPolyLine @@ -9115,15 +8602,15 @@ vasetType 3 ) -xt "-28000,89000,-22000,89000" -pts [ -"-28000,89000" -"-22000,89000" -] -) -start &168 -end &181 -es 0 +xt "11000,79000,13000,79000" +pts [ +"11000,79000" +"13000,79000" +] +) +start &167 +end &171 sat 32 eat 32 +stc 0 st 0 sf 1 @@ -9136,50 +8623,15 @@ uid 6313,0 va (VaSet -) -xt "-26000,88000,-21500,89000" +isHidden 1 +) +xt "13000,78000,17500,79000" st "TEST_TRG" -blo "-26000,88800" +blo "13000,78800" tm "WireNameMgr" ) ) -on &169 -) -*295 (Wire -uid 6328,0 -shape (OrthoPolyLine -uid 6329,0 -va (VaSet -vasetType 3 -) -xt "-17000,89000,-11750,89000" -pts [ -"-17000,89000" -"-11750,89000" -] -) -start &183 -end &173 -sat 32 -eat 32 -st 0 -sf 1 -si 0 -tg (WTG -uid 6334,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 6335,0 -va (VaSet -) -xt "-18000,92000,-11700,93000" -st "not_TEST_TRG" -blo "-18000,92800" -tm "WireNameMgr" -) -) -on &179 -) -*296 (Wire +on &168 +) +*275 (Wire uid 6431,0 shape (OrthoPolyLine @@ -9195,5 +8647,5 @@ ) start &43 -end &149 +end &148 sat 32 eat 32 @@ -9217,7 +8669,7 @@ ) ) -on &158 -) -*297 (Wire +on &157 +) +*276 (Wire uid 6787,0 shape (OrthoPolyLine @@ -9233,6 +8685,6 @@ ] ) -start &213 -end &217 +start &193 +end &197 sat 32 eat 1 @@ -9256,7 +8708,7 @@ ) ) -on &214 -) -*298 (Wire +on &194 +) +*277 (Wire uid 6880,0 shape (OrthoPolyLine @@ -9272,6 +8724,6 @@ ] ) -start &217 -end &215 +start &197 +end &195 sat 2 eat 32 @@ -9295,112 +8747,7 @@ ) ) -on &216 -) -*299 (Wire -uid 7102,0 -shape (OrthoPolyLine -uid 7103,0 -va (VaSet -vasetType 3 -) -xt "21000,132000,31000,132000" -pts [ -"21000,132000" -"31000,132000" -] -) -end &221 -sat 16 -eat 1 -st 0 -sf 1 -si 0 -tg (WTG -uid 7108,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 7109,0 -va (VaSet -) -xt "23000,131000,27600,132000" -st "D0_SROUT" -blo "23000,131800" -tm "WireNameMgr" -) -) -on &106 -) -*300 (Wire -uid 7110,0 -shape (OrthoPolyLine -uid 7111,0 -va (VaSet -vasetType 3 -) -xt "21000,133000,31000,133000" -pts [ -"21000,133000" -"31000,133000" -] -) -end &221 -sat 16 -eat 1 -st 0 -sf 1 -si 0 -tg (WTG -uid 7116,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 7117,0 -va (VaSet -) -xt "23000,132000,27600,133000" -st "D1_SROUT" -blo "23000,132800" -tm "WireNameMgr" -) -) -on &107 -) -*301 (Wire -uid 7118,0 -shape (OrthoPolyLine -uid 7119,0 -va (VaSet -vasetType 3 -) -xt "21000,134000,31000,134000" -pts [ -"21000,134000" -"31000,134000" -] -) -end &221 -sat 16 -eat 1 -st 0 -sf 1 -si 0 -tg (WTG -uid 7124,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 7125,0 -va (VaSet -) -xt "23000,133000,27200,134000" -st "RSRLOAD" -blo "23000,133800" -tm "WireNameMgr" -) -) -on &64 -) -*302 (Wire +on &196 +) +*278 (Wire uid 7144,0 shape (OrthoPolyLine @@ -9416,6 +8763,6 @@ ] ) -start &221 -end &225 +start &201 +end &205 sat 2 eat 32 @@ -9434,12 +8781,12 @@ ) xt "41000,131000,45800,132000" -st "A1_T : (3:0)" +st "A1_T : (7:0)" blo "41000,131800" tm "WireNameMgr" ) ) -on &226 -) -*303 (Wire +on &206 +) +*279 (Wire uid 7477,0 shape (OrthoPolyLine @@ -9455,5 +8802,5 @@ ) start &38 -end &229 +end &209 es 0 sat 32 @@ -9476,10 +8823,50 @@ ) ) -on &227 -) -*304 (Wire -uid 7487,0 +on &207 +) +*280 (Wire +uid 8853,0 shape (OrthoPolyLine -uid 7488,0 +uid 8854,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "10000,109000,51250,132000" +pts [ +"51250,109000" +"10000,109000" +"10000,132000" +"31000,132000" +] +) +start &30 +end &201 +sat 32 +eat 1 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 8857,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8858,0 +va (VaSet +) +xt "42000,108000,50500,109000" +st "drs_channel_id : (3:0)" +blo "42000,108800" +tm "WireNameMgr" +) +) +on &221 +) +*281 (Wire +uid 9492,0 +shape (OrthoPolyLine +uid 9493,0 va (VaSet vasetType 3 @@ -9491,5 +8878,5 @@ ] ) -end &221 +end &201 sat 16 eat 1 @@ -9498,18 +8885,53 @@ si 0 tg (WTG -uid 7493,0 +uid 9498,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text -uid 7494,0 -va (VaSet -) -xt "23000,134000,25700,135000" -st "dummy" +uid 9499,0 +va (VaSet +) +xt "23000,134000,26700,135000" +st "TRG_OR" blo "23000,134800" tm "WireNameMgr" ) ) -on &227 +on &169 +) +*282 (Wire +uid 9502,0 +shape (OrthoPolyLine +uid 9503,0 +va (VaSet +vasetType 3 +) +xt "46000,69000,51250,69000" +pts [ +"51250,69000" +"46000,69000" +] +) +start &26 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 9506,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 9507,0 +va (VaSet +) +xt "47000,68000,50100,69000" +st "CLK_50" +blo "47000,68800" +tm "WireNameMgr" +) +) +on &222 ) ] @@ -9525,9 +8947,9 @@ color "26368,26368,26368" ) -packageList *305 (PackageList +packageList *283 (PackageList uid 41,0 stg "VerticalLayoutStrategy" textVec [ -*306 (Text +*284 (Text uid 42,0 va (VaSet @@ -9538,5 +8960,5 @@ blo "0,800" ) -*307 (MLText +*285 (MLText uid 43,0 va (VaSet @@ -9559,5 +8981,5 @@ stg "VerticalLayoutStrategy" textVec [ -*308 (Text +*286 (Text uid 45,0 va (VaSet @@ -9569,5 +8991,5 @@ blo "20000,800" ) -*309 (Text +*287 (Text uid 46,0 va (VaSet @@ -9579,5 +9001,5 @@ blo "20000,1800" ) -*310 (MLText +*288 (MLText uid 47,0 va (VaSet @@ -9589,5 +9011,5 @@ tm "BdCompilerDirectivesTextMgr" ) -*311 (Text +*289 (Text uid 48,0 va (VaSet @@ -9599,5 +9021,5 @@ blo "20000,4800" ) -*312 (MLText +*290 (MLText uid 49,0 va (VaSet @@ -9607,5 +9029,5 @@ tm "BdCompilerDirectivesTextMgr" ) -*313 (Text +*291 (Text uid 50,0 va (VaSet @@ -9617,5 +9039,5 @@ blo "20000,5800" ) -*314 (MLText +*292 (MLText uid 51,0 va (VaSet @@ -9628,7 +9050,7 @@ associable 1 ) -windowSize "0,0,1281,1002" -viewArea "2340,64220,87220,128140" -cachedDiagramExtent "-35500,0,699000,450107" +windowSize "0,22,1281,1024" +viewArea "-13800,92200,71080,160280" +cachedDiagramExtent "0,0,699000,450107" pageSetupInfo (PageSetupInfo ptrCmd "" @@ -9641,6 +9063,6 @@ ) hasePageBreakOrigin 1 -pageBreakOrigin "-73000,0" -lastUid 8751,0 +pageBreakOrigin "0,0" +lastUid 9715,0 defaultCommentText (CommentText shape (Rectangle @@ -9704,5 +9126,5 @@ stg "VerticalLayoutStrategy" textVec [ -*315 (Text +*293 (Text va (VaSet font "Arial,8,1" @@ -9713,5 +9135,5 @@ tm "BdLibraryNameMgr" ) -*316 (Text +*294 (Text va (VaSet font "Arial,8,1" @@ -9722,5 +9144,5 @@ tm "BlkNameMgr" ) -*317 (Text +*295 (Text va (VaSet font "Arial,8,1" @@ -9773,5 +9195,5 @@ stg "VerticalLayoutStrategy" textVec [ -*318 (Text +*296 (Text va (VaSet font "Arial,8,1" @@ -9781,5 +9203,5 @@ blo "550,4300" ) -*319 (Text +*297 (Text va (VaSet font "Arial,8,1" @@ -9789,5 +9211,5 @@ blo "550,5300" ) -*320 (Text +*298 (Text va (VaSet font "Arial,8,1" @@ -9838,5 +9260,5 @@ stg "VerticalLayoutStrategy" textVec [ -*321 (Text +*299 (Text va (VaSet font "Arial,8,1" @@ -9847,5 +9269,5 @@ tm "BdLibraryNameMgr" ) -*322 (Text +*300 (Text va (VaSet font "Arial,8,1" @@ -9856,5 +9278,5 @@ tm "CptNameMgr" ) -*323 (Text +*301 (Text va (VaSet font "Arial,8,1" @@ -9910,5 +9332,5 @@ stg "VerticalLayoutStrategy" textVec [ -*324 (Text +*302 (Text va (VaSet font "Arial,8,1" @@ -9918,5 +9340,5 @@ blo "500,4300" ) -*325 (Text +*303 (Text va (VaSet font "Arial,8,1" @@ -9926,5 +9348,5 @@ blo "500,5300" ) -*326 (Text +*304 (Text va (VaSet font "Arial,8,1" @@ -9971,5 +9393,5 @@ stg "VerticalLayoutStrategy" textVec [ -*327 (Text +*305 (Text va (VaSet font "Arial,8,1" @@ -9979,5 +9401,5 @@ blo "50,4300" ) -*328 (Text +*306 (Text va (VaSet font "Arial,8,1" @@ -9987,5 +9409,5 @@ blo "50,5300" ) -*329 (Text +*307 (Text va (VaSet font "Arial,8,1" @@ -10028,5 +9450,5 @@ stg "VerticalLayoutStrategy" textVec [ -*330 (Text +*308 (Text va (VaSet font "Arial,8,1" @@ -10037,5 +9459,5 @@ tm "HdlTextNameMgr" ) -*331 (Text +*309 (Text va (VaSet font "Arial,8,1" @@ -10440,5 +9862,5 @@ stg "VerticalLayoutStrategy" textVec [ -*332 (Text +*310 (Text va (VaSet font "Arial,8,1" @@ -10448,5 +9870,5 @@ blo "14100,20800" ) -*333 (MLText +*311 (MLText va (VaSet ) @@ -10500,5 +9922,5 @@ stg "VerticalLayoutStrategy" textVec [ -*334 (Text +*312 (Text va (VaSet font "Arial,8,1" @@ -10508,5 +9930,5 @@ blo "14100,20800" ) -*335 (MLText +*313 (MLText va (VaSet ) @@ -10652,44 +10074,44 @@ commonDM (CommonDM ldm (LogicalDM -suid 158,0 +suid 163,0 usingSuid 1 -emptyRow *336 (LEmptyRow +emptyRow *314 (LEmptyRow ) uid 54,0 optionalChildren [ -*337 (RefLabelRowHdr -) -*338 (TitleRowHdr -) -*339 (FilterRowHdr -) -*340 (RefLabelColHdr +*315 (RefLabelRowHdr +) +*316 (TitleRowHdr +) +*317 (FilterRowHdr +) +*318 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*341 (RowExpandColHdr +*319 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*342 (GroupColHdr +*320 (GroupColHdr tm "GroupColHdrMgr" ) -*343 (NameColHdr +*321 (NameColHdr tm "BlockDiagramNameColHdrMgr" ) -*344 (ModeColHdr +*322 (ModeColHdr tm "BlockDiagramModeColHdrMgr" ) -*345 (TypeColHdr +*323 (TypeColHdr tm "BlockDiagramTypeColHdrMgr" ) -*346 (BoundsColHdr +*324 (BoundsColHdr tm "BlockDiagramBoundsColHdrMgr" ) -*347 (InitColHdr +*325 (InitColHdr tm "BlockDiagramInitColHdrMgr" ) -*348 (EolColHdr +*326 (EolColHdr tm "BlockDiagramEolColHdrMgr" ) -*349 (LeafLogPort +*327 (LeafLogPort port (LogicalPort m 4 @@ -10706,5 +10128,5 @@ uid 327,0 ) -*350 (LeafLogPort +*328 (LeafLogPort port (LogicalPort m 4 @@ -10719,5 +10141,5 @@ uid 329,0 ) -*351 (LeafLogPort +*329 (LeafLogPort port (LogicalPort m 4 @@ -10731,19 +10153,5 @@ uid 1491,0 ) -*352 (LeafLogPort -port (LogicalPort -m 4 -decl (Decl -n "CLK_50" -t "std_logic" -preAdd 0 -posAdd 0 -o 51 -suid 54,0 -) -) -uid 2275,0 -) -*353 (LeafLogPort +*330 (LeafLogPort port (LogicalPort m 1 @@ -10758,5 +10166,5 @@ uid 2435,0 ) -*354 (LeafLogPort +*331 (LeafLogPort port (LogicalPort m 4 @@ -10771,5 +10179,5 @@ uid 2437,0 ) -*355 (LeafLogPort +*332 (LeafLogPort port (LogicalPort m 4 @@ -10784,5 +10192,5 @@ uid 3037,0 ) -*356 (LeafLogPort +*333 (LeafLogPort port (LogicalPort m 1 @@ -10796,5 +10204,5 @@ uid 3039,0 ) -*357 (LeafLogPort +*334 (LeafLogPort port (LogicalPort decl (Decl @@ -10809,5 +10217,5 @@ uid 3276,0 ) -*358 (LeafLogPort +*335 (LeafLogPort port (LogicalPort decl (Decl @@ -10820,5 +10228,5 @@ uid 3278,0 ) -*359 (LeafLogPort +*336 (LeafLogPort port (LogicalPort m 1 @@ -10833,5 +10241,5 @@ uid 3280,0 ) -*360 (LeafLogPort +*337 (LeafLogPort port (LogicalPort m 4 @@ -10845,5 +10253,5 @@ uid 3282,0 ) -*361 (LeafLogPort +*338 (LeafLogPort port (LogicalPort m 1 @@ -10859,5 +10267,5 @@ uid 3382,0 ) -*362 (LeafLogPort +*339 (LeafLogPort port (LogicalPort decl (Decl @@ -10871,5 +10279,5 @@ uid 3384,0 ) -*363 (LeafLogPort +*340 (LeafLogPort port (LogicalPort decl (Decl @@ -10883,5 +10291,5 @@ uid 3386,0 ) -*364 (LeafLogPort +*341 (LeafLogPort port (LogicalPort decl (Decl @@ -10895,5 +10303,5 @@ uid 3388,0 ) -*365 (LeafLogPort +*342 (LeafLogPort port (LogicalPort decl (Decl @@ -10907,5 +10315,5 @@ uid 3390,0 ) -*366 (LeafLogPort +*343 (LeafLogPort port (LogicalPort decl (Decl @@ -10919,5 +10327,5 @@ uid 3392,0 ) -*367 (LeafLogPort +*344 (LeafLogPort port (LogicalPort m 1 @@ -10931,5 +10339,5 @@ uid 3468,0 ) -*368 (LeafLogPort +*345 (LeafLogPort port (LogicalPort m 1 @@ -10943,5 +10351,5 @@ uid 3470,0 ) -*369 (LeafLogPort +*346 (LeafLogPort port (LogicalPort m 1 @@ -10955,5 +10363,5 @@ uid 3472,0 ) -*370 (LeafLogPort +*347 (LeafLogPort port (LogicalPort m 1 @@ -10967,5 +10375,5 @@ uid 3474,0 ) -*371 (LeafLogPort +*348 (LeafLogPort port (LogicalPort decl (Decl @@ -10978,5 +10386,5 @@ uid 3524,0 ) -*372 (LeafLogPort +*349 (LeafLogPort port (LogicalPort decl (Decl @@ -10989,5 +10397,5 @@ uid 3526,0 ) -*373 (LeafLogPort +*350 (LeafLogPort port (LogicalPort decl (Decl @@ -11000,5 +10408,5 @@ uid 3528,0 ) -*374 (LeafLogPort +*351 (LeafLogPort port (LogicalPort decl (Decl @@ -11011,5 +10419,5 @@ uid 3530,0 ) -*375 (LeafLogPort +*352 (LeafLogPort port (LogicalPort m 1 @@ -11025,5 +10433,5 @@ uid 3532,0 ) -*376 (LeafLogPort +*353 (LeafLogPort port (LogicalPort m 1 @@ -11038,5 +10446,5 @@ uid 3534,0 ) -*377 (LeafLogPort +*354 (LeafLogPort port (LogicalPort m 1 @@ -11050,5 +10458,5 @@ uid 3646,0 ) -*378 (LeafLogPort +*355 (LeafLogPort port (LogicalPort m 1 @@ -11062,5 +10470,5 @@ uid 3648,0 ) -*379 (LeafLogPort +*356 (LeafLogPort port (LogicalPort m 1 @@ -11074,5 +10482,5 @@ uid 3650,0 ) -*380 (LeafLogPort +*357 (LeafLogPort port (LogicalPort m 1 @@ -11086,5 +10494,5 @@ uid 3652,0 ) -*381 (LeafLogPort +*358 (LeafLogPort port (LogicalPort m 1 @@ -11098,5 +10506,5 @@ uid 3654,0 ) -*382 (LeafLogPort +*359 (LeafLogPort port (LogicalPort m 1 @@ -11111,5 +10519,5 @@ uid 3656,0 ) -*383 (LeafLogPort +*360 (LeafLogPort port (LogicalPort m 2 @@ -11124,5 +10532,5 @@ uid 3658,0 ) -*384 (LeafLogPort +*361 (LeafLogPort port (LogicalPort m 1 @@ -11137,5 +10545,5 @@ uid 3660,0 ) -*385 (LeafLogPort +*362 (LeafLogPort port (LogicalPort m 1 @@ -11150,5 +10558,5 @@ uid 3662,0 ) -*386 (LeafLogPort +*363 (LeafLogPort port (LogicalPort m 1 @@ -11163,5 +10571,5 @@ uid 3664,0 ) -*387 (LeafLogPort +*364 (LeafLogPort port (LogicalPort decl (Decl @@ -11174,5 +10582,5 @@ uid 3666,0 ) -*388 (LeafLogPort +*365 (LeafLogPort port (LogicalPort m 1 @@ -11187,5 +10595,5 @@ uid 3668,0 ) -*389 (LeafLogPort +*366 (LeafLogPort port (LogicalPort m 1 @@ -11200,5 +10608,5 @@ uid 3696,0 ) -*390 (LeafLogPort +*367 (LeafLogPort port (LogicalPort m 2 @@ -11214,5 +10622,5 @@ uid 3698,0 ) -*391 (LeafLogPort +*368 (LeafLogPort port (LogicalPort m 1 @@ -11226,5 +10634,5 @@ uid 3886,0 ) -*392 (LeafLogPort +*369 (LeafLogPort port (LogicalPort m 1 @@ -11238,5 +10646,5 @@ uid 3888,0 ) -*393 (LeafLogPort +*370 (LeafLogPort port (LogicalPort m 1 @@ -11250,5 +10658,5 @@ uid 3890,0 ) -*394 (LeafLogPort +*371 (LeafLogPort port (LogicalPort m 1 @@ -11262,5 +10670,5 @@ uid 3892,0 ) -*395 (LeafLogPort +*372 (LeafLogPort port (LogicalPort m 1 @@ -11274,5 +10682,5 @@ uid 3894,0 ) -*396 (LeafLogPort +*373 (LeafLogPort port (LogicalPort m 1 @@ -11287,5 +10695,5 @@ uid 3896,0 ) -*397 (LeafLogPort +*374 (LeafLogPort port (LogicalPort m 1 @@ -11299,5 +10707,5 @@ uid 3898,0 ) -*398 (LeafLogPort +*375 (LeafLogPort port (LogicalPort m 1 @@ -11311,5 +10719,5 @@ uid 3900,0 ) -*399 (LeafLogPort +*376 (LeafLogPort port (LogicalPort m 1 @@ -11325,5 +10733,5 @@ uid 3902,0 ) -*400 (LeafLogPort +*377 (LeafLogPort port (LogicalPort m 1 @@ -11339,5 +10747,5 @@ uid 5322,0 ) -*401 (LeafLogPort +*378 (LeafLogPort port (LogicalPort decl (Decl @@ -11351,5 +10759,5 @@ scheme 0 ) -*402 (LeafLogPort +*379 (LeafLogPort port (LogicalPort m 4 @@ -11364,33 +10772,5 @@ scheme 0 ) -*403 (LeafLogPort -port (LogicalPort -m 4 -decl (Decl -n "trigger_out" -t "STD_LOGIC" -preAdd 0 -posAdd 0 -o 60 -suid 147,0 -i "'0'" -) -) -uid 6286,0 -) -*404 (LeafLogPort -port (LogicalPort -m 4 -decl (Decl -n "not_TEST_TRG" -t "STD_LOGIC" -o 58 -suid 148,0 -) -) -uid 6314,0 -scheme 0 -) -*405 (LeafLogPort +*380 (LeafLogPort port (LogicalPort decl (Decl @@ -11405,5 +10785,5 @@ scheme 0 ) -*406 (LeafLogPort +*381 (LeafLogPort port (LogicalPort m 1 @@ -11420,5 +10800,5 @@ scheme 0 ) -*407 (LeafLogPort +*382 (LeafLogPort port (LogicalPort m 1 @@ -11426,7 +10806,8 @@ n "A1_T" t "std_logic_vector" -b "(3 DOWNTO 0)" +b "(7 DOWNTO 0)" o 15 suid 155,0 +i "(OTHERS => '0')" ) ) @@ -11434,5 +10815,5 @@ scheme 0 ) -*408 (LeafLogPort +*383 (LeafLogPort port (LogicalPort m 4 @@ -11440,5 +10821,5 @@ n "dummy" t "std_logic" -o 60 +o 58 suid 157,0 ) @@ -11446,4 +10827,30 @@ uid 7473,0 scheme 0 +) +*384 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "drs_channel_id" +t "std_logic_vector" +b "(3 downto 0)" +o 57 +suid 159,0 +i "(others => '0')" +) +) +uid 8875,0 +) +*385 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "CLK_50" +t "std_logic" +o 51 +suid 163,0 +) +) +uid 9516,0 ) ] @@ -11454,5 +10861,5 @@ uid 67,0 optionalChildren [ -*409 (Sheet +*386 (Sheet sheetRow (SheetRow headerVa (MVa @@ -11471,25 +10878,25 @@ font "Tahoma,10,0" ) -emptyMRCItem *410 (MRCItem -litem &336 -pos 60 +emptyMRCItem *387 (MRCItem +litem &314 +pos 59 dimension 20 ) uid 69,0 optionalChildren [ -*411 (MRCItem -litem &337 +*388 (MRCItem +litem &315 pos 0 dimension 20 uid 70,0 ) -*412 (MRCItem -litem &338 +*389 (MRCItem +litem &316 pos 1 dimension 23 uid 71,0 ) -*413 (MRCItem -litem &339 +*390 (MRCItem +litem &317 pos 2 hidden 1 @@ -11497,363 +10904,357 @@ uid 72,0 ) -*414 (MRCItem -litem &349 -pos 44 +*391 (MRCItem +litem &327 +pos 49 dimension 20 uid 328,0 ) -*415 (MRCItem -litem &350 -pos 45 +*392 (MRCItem +litem &328 +pos 50 dimension 20 uid 330,0 ) -*416 (MRCItem -litem &351 -pos 46 +*393 (MRCItem +litem &329 +pos 51 dimension 20 uid 1492,0 ) -*417 (MRCItem -litem &352 -pos 47 -dimension 20 -uid 2276,0 -) -*418 (MRCItem -litem &353 +*394 (MRCItem +litem &330 pos 0 dimension 20 uid 2436,0 ) -*419 (MRCItem -litem &354 -pos 48 +*395 (MRCItem +litem &331 +pos 52 dimension 20 uid 2438,0 ) -*420 (MRCItem -litem &355 -pos 49 +*396 (MRCItem +litem &332 +pos 53 dimension 20 uid 3038,0 ) -*421 (MRCItem -litem &356 +*397 (MRCItem +litem &333 pos 1 dimension 20 uid 3040,0 ) -*422 (MRCItem -litem &357 +*398 (MRCItem +litem &334 pos 2 dimension 20 uid 3277,0 ) -*423 (MRCItem -litem &358 +*399 (MRCItem +litem &335 pos 3 dimension 20 uid 3279,0 ) -*424 (MRCItem -litem &359 +*400 (MRCItem +litem &336 pos 4 dimension 20 uid 3281,0 ) -*425 (MRCItem -litem &360 -pos 50 +*401 (MRCItem +litem &337 +pos 54 dimension 20 uid 3283,0 ) -*426 (MRCItem -litem &361 +*402 (MRCItem +litem &338 pos 5 dimension 20 uid 3383,0 ) -*427 (MRCItem -litem &362 +*403 (MRCItem +litem &339 pos 6 dimension 20 uid 3385,0 ) -*428 (MRCItem -litem &363 +*404 (MRCItem +litem &340 pos 7 dimension 20 uid 3387,0 ) -*429 (MRCItem -litem &364 +*405 (MRCItem +litem &341 pos 8 dimension 20 uid 3389,0 ) -*430 (MRCItem -litem &365 +*406 (MRCItem +litem &342 pos 9 dimension 20 uid 3391,0 ) -*431 (MRCItem -litem &366 +*407 (MRCItem +litem &343 pos 10 dimension 20 uid 3393,0 ) -*432 (MRCItem -litem &367 +*408 (MRCItem +litem &344 pos 11 dimension 20 uid 3469,0 ) -*433 (MRCItem -litem &368 +*409 (MRCItem +litem &345 pos 12 dimension 20 uid 3471,0 ) -*434 (MRCItem -litem &369 +*410 (MRCItem +litem &346 pos 13 dimension 20 uid 3473,0 ) -*435 (MRCItem -litem &370 +*411 (MRCItem +litem &347 pos 14 dimension 20 uid 3475,0 ) -*436 (MRCItem -litem &371 +*412 (MRCItem +litem &348 pos 15 dimension 20 uid 3525,0 ) -*437 (MRCItem -litem &372 +*413 (MRCItem +litem &349 pos 16 dimension 20 uid 3527,0 ) -*438 (MRCItem -litem &373 +*414 (MRCItem +litem &350 pos 17 dimension 20 uid 3529,0 ) -*439 (MRCItem -litem &374 +*415 (MRCItem +litem &351 pos 18 dimension 20 uid 3531,0 ) -*440 (MRCItem -litem &375 +*416 (MRCItem +litem &352 pos 19 dimension 20 uid 3533,0 ) -*441 (MRCItem -litem &376 +*417 (MRCItem +litem &353 pos 20 dimension 20 uid 3535,0 ) -*442 (MRCItem -litem &377 +*418 (MRCItem +litem &354 pos 21 dimension 20 uid 3647,0 ) -*443 (MRCItem -litem &378 +*419 (MRCItem +litem &355 pos 22 dimension 20 uid 3649,0 ) -*444 (MRCItem -litem &379 +*420 (MRCItem +litem &356 pos 23 dimension 20 uid 3651,0 ) -*445 (MRCItem -litem &380 +*421 (MRCItem +litem &357 pos 24 dimension 20 uid 3653,0 ) -*446 (MRCItem -litem &381 +*422 (MRCItem +litem &358 pos 25 dimension 20 uid 3655,0 ) -*447 (MRCItem -litem &382 +*423 (MRCItem +litem &359 pos 26 dimension 20 uid 3657,0 ) -*448 (MRCItem -litem &383 +*424 (MRCItem +litem &360 pos 27 dimension 20 uid 3659,0 ) -*449 (MRCItem -litem &384 +*425 (MRCItem +litem &361 pos 28 dimension 20 uid 3661,0 ) -*450 (MRCItem -litem &385 +*426 (MRCItem +litem &362 pos 29 dimension 20 uid 3663,0 ) -*451 (MRCItem -litem &386 +*427 (MRCItem +litem &363 pos 30 dimension 20 uid 3665,0 ) -*452 (MRCItem -litem &387 +*428 (MRCItem +litem &364 pos 31 dimension 20 uid 3667,0 ) -*453 (MRCItem -litem &388 +*429 (MRCItem +litem &365 pos 32 dimension 20 uid 3669,0 ) -*454 (MRCItem -litem &389 +*430 (MRCItem +litem &366 pos 33 dimension 20 uid 3697,0 ) -*455 (MRCItem -litem &390 +*431 (MRCItem +litem &367 pos 34 dimension 20 uid 3699,0 ) -*456 (MRCItem -litem &391 +*432 (MRCItem +litem &368 pos 35 dimension 20 uid 3887,0 ) -*457 (MRCItem -litem &392 +*433 (MRCItem +litem &369 pos 36 dimension 20 uid 3889,0 ) -*458 (MRCItem -litem &393 +*434 (MRCItem +litem &370 pos 37 dimension 20 uid 3891,0 ) -*459 (MRCItem -litem &394 +*435 (MRCItem +litem &371 pos 38 dimension 20 uid 3893,0 ) -*460 (MRCItem -litem &395 +*436 (MRCItem +litem &372 pos 39 dimension 20 uid 3895,0 ) -*461 (MRCItem -litem &396 +*437 (MRCItem +litem &373 pos 40 dimension 20 uid 3897,0 ) -*462 (MRCItem -litem &397 +*438 (MRCItem +litem &374 pos 41 dimension 20 uid 3899,0 ) -*463 (MRCItem -litem &398 +*439 (MRCItem +litem &375 pos 42 dimension 20 uid 3901,0 ) -*464 (MRCItem -litem &399 +*440 (MRCItem +litem &376 pos 43 dimension 20 uid 3903,0 ) -*465 (MRCItem -litem &400 -pos 51 +*441 (MRCItem +litem &377 +pos 44 dimension 20 uid 5323,0 ) -*466 (MRCItem -litem &401 -pos 52 +*442 (MRCItem +litem &378 +pos 45 dimension 20 uid 5649,0 ) -*467 (MRCItem -litem &402 -pos 53 +*443 (MRCItem +litem &379 +pos 55 dimension 20 uid 6129,0 ) -*468 (MRCItem -litem &403 -pos 54 +*444 (MRCItem +litem &380 +pos 46 dimension 20 -uid 6287,0 -) -*469 (MRCItem -litem &404 -pos 55 +uid 6778,0 +) +*445 (MRCItem +litem &381 +pos 47 dimension 20 -uid 6315,0 -) -*470 (MRCItem -litem &405 +uid 6873,0 +) +*446 (MRCItem +litem &382 +pos 48 +dimension 20 +uid 7135,0 +) +*447 (MRCItem +litem &383 pos 56 dimension 20 -uid 6778,0 -) -*471 (MRCItem -litem &406 +uid 7474,0 +) +*448 (MRCItem +litem &384 pos 57 dimension 20 -uid 6873,0 -) -*472 (MRCItem -litem &407 +uid 8876,0 +) +*449 (MRCItem +litem &385 pos 58 dimension 20 -uid 7135,0 -) -*473 (MRCItem -litem &408 -pos 59 -dimension 20 -uid 7474,0 +uid 9517,0 ) ] @@ -11868,48 +11269,48 @@ uid 73,0 optionalChildren [ -*474 (MRCItem -litem &340 +*450 (MRCItem +litem &318 pos 0 dimension 20 uid 74,0 ) -*475 (MRCItem -litem &342 +*451 (MRCItem +litem &320 pos 1 dimension 50 uid 75,0 ) -*476 (MRCItem -litem &343 +*452 (MRCItem +litem &321 pos 2 dimension 100 uid 76,0 ) -*477 (MRCItem -litem &344 +*453 (MRCItem +litem &322 pos 3 dimension 50 uid 77,0 ) -*478 (MRCItem -litem &345 +*454 (MRCItem +litem &323 pos 4 dimension 100 uid 78,0 ) -*479 (MRCItem -litem &346 +*455 (MRCItem +litem &324 pos 5 dimension 100 uid 79,0 ) -*480 (MRCItem -litem &347 +*456 (MRCItem +litem &325 pos 6 dimension 92 uid 80,0 ) -*481 (MRCItem -litem &348 +*457 (MRCItem +litem &326 pos 7 dimension 80 @@ -11931,36 +11332,36 @@ genericsCommonDM (CommonDM ldm (LogicalDM -emptyRow *482 (LEmptyRow +emptyRow *458 (LEmptyRow ) uid 83,0 optionalChildren [ -*483 (RefLabelRowHdr -) -*484 (TitleRowHdr -) -*485 (FilterRowHdr -) -*486 (RefLabelColHdr +*459 (RefLabelRowHdr +) +*460 (TitleRowHdr +) +*461 (FilterRowHdr +) +*462 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*487 (RowExpandColHdr +*463 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*488 (GroupColHdr +*464 (GroupColHdr tm "GroupColHdrMgr" ) -*489 (NameColHdr +*465 (NameColHdr tm "GenericNameColHdrMgr" ) -*490 (TypeColHdr +*466 (TypeColHdr tm "GenericTypeColHdrMgr" ) -*491 (InitColHdr +*467 (InitColHdr tm "GenericValueColHdrMgr" ) -*492 (PragmaColHdr +*468 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) -*493 (EolColHdr +*469 (EolColHdr tm "GenericEolColHdrMgr" ) @@ -11972,5 +11373,5 @@ uid 95,0 optionalChildren [ -*494 (Sheet +*470 (Sheet sheetRow (SheetRow headerVa (MVa @@ -11989,6 +11390,6 @@ font "Tahoma,10,0" ) -emptyMRCItem *495 (MRCItem -litem &482 +emptyMRCItem *471 (MRCItem +litem &458 pos 0 dimension 20 @@ -11996,18 +11397,18 @@ uid 97,0 optionalChildren [ -*496 (MRCItem -litem &483 +*472 (MRCItem +litem &459 pos 0 dimension 20 uid 98,0 ) -*497 (MRCItem -litem &484 +*473 (MRCItem +litem &460 pos 1 dimension 23 uid 99,0 ) -*498 (MRCItem -litem &485 +*474 (MRCItem +litem &461 pos 2 hidden 1 @@ -12026,42 +11427,42 @@ uid 101,0 optionalChildren [ -*499 (MRCItem -litem &486 +*475 (MRCItem +litem &462 pos 0 dimension 20 uid 102,0 ) -*500 (MRCItem -litem &488 +*476 (MRCItem +litem &464 pos 1 dimension 50 uid 103,0 ) -*501 (MRCItem -litem &489 +*477 (MRCItem +litem &465 pos 2 dimension 100 uid 104,0 ) -*502 (MRCItem -litem &490 +*478 (MRCItem +litem &466 pos 3 dimension 100 uid 105,0 ) -*503 (MRCItem -litem &491 +*479 (MRCItem +litem &467 pos 4 dimension 50 uid 106,0 ) -*504 (MRCItem -litem &492 +*480 (MRCItem +litem &468 pos 5 dimension 50 uid 107,0 ) -*505 (MRCItem -litem &493 +*481 (MRCItem +litem &469 pos 6 dimension 80 @@ -12082,4 +11483,4 @@ type 1 ) -activeModelName "BlockDiag" -) +activeModelName "BlockDiag:CDM" +) Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.bak =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.bak (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.bak (revision 252) @@ -26,5 +26,5 @@ instances [ (Instance -name "I_testboard_main" +name "I_board_main" duLibraryName "FACT_FAD_lib" duName "FAD_main" @@ -38,27 +38,4 @@ mwi 0 uid 169,0 -) -(Instance -name "I0" -duLibraryName "FACT_FAD_LIB" -duName "debouncer" -elements [ -(GiElement -name "WIDTH" -type "INTEGER" -value "17" -) -] -mwi 0 -uid 6250,0 -) -(Instance -name "I1" -duLibraryName "moduleware" -duName "inv" -elements [ -] -mwi 1 -uid 6539,0 ) (Instance @@ -128,21 +105,21 @@ (vvPair variable "HDLDir" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hdl" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" ) (vvPair variable "HDSDir" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair variable "SideDataDesignDir" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info" ) (vvPair variable "SideDataUserDir" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user" ) (vvPair variable "SourceDir" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair @@ -160,25 +137,25 @@ (vvPair variable "d" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board" ) (vvPair variable "d_logical" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\FAD_Board" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board" ) (vvPair variable "date" -value "22.06.2010" +value "14.07.2010" ) (vvPair variable "day" -value "Di" +value "Mi" ) (vvPair variable "day_long" -value "Dienstag" +value "Mittwoch" ) (vvPair variable "dd" -value "22" +value "14" ) (vvPair @@ -208,5 +185,5 @@ (vvPair variable "host" -value "TU-CC4900F8C7D2" +value "E5B-LABOR6" ) (vvPair @@ -219,4 +196,8 @@ ) (vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR\\FACT_FAD_lib\\designcheck" +) +(vvPair variable "library_downstream_ISEPARInvoke" value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" @@ -236,5 +217,5 @@ (vvPair variable "mm" -value "06" +value "07" ) (vvPair @@ -244,17 +225,17 @@ (vvPair variable "month" -value "Jun" +value "Jul" ) (vvPair variable "month_long" -value "Juni" +value "Juli" ) (vvPair variable "p" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd" ) (vvPair variable "p_logical" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd" ) (vvPair @@ -312,5 +293,5 @@ (vvPair variable "time" -value "11:16:21" +value "15:24:46" ) (vvPair @@ -364,5 +345,5 @@ bg "0,0,32768" ) -xt "99200,4000,108700,5000" +xt "99200,4000,108500,5000" st " by %user on %dd %month %year @@ -1831,6 +1812,6 @@ font "Arial,8,1" ) -xt "52200,125000,59400,126000" -st "I_testboard_main" +xt "52200,125000,58000,126000" +st "I_board_main" blo "52200,125800" tm "InstanceNameMgr" @@ -2065,5 +2046,5 @@ preAdd 0 posAdd 0 -o 55 +o 56 suid 5,0 ) @@ -2073,5 +2054,5 @@ font "Courier New,8,0" ) -xt "39000,48000,67000,48800" +xt "39000,48800,67000,49600" st "SIGNAL board_id : std_logic_vector(3 downto 0)" ) @@ -2083,5 +2064,5 @@ t "std_logic_vector" b "(1 downto 0)" -o 56 +o 57 suid 6,0 ) @@ -2091,5 +2072,5 @@ font "Courier New,8,0" ) -xt "39000,48800,67000,49600" +xt "39000,49600,67000,50400" st "SIGNAL crate_id : std_logic_vector(1 downto 0)" ) @@ -2406,5 +2387,5 @@ n "adc_data_array" t "adc_data_array_type" -o 54 +o 55 suid 29,0 ) @@ -2414,33 +2395,14 @@ font "Courier New,8,0" ) -xt "39000,47200,62500,48000" +xt "39000,48000,62500,48800" st "SIGNAL adc_data_array : adc_data_array_type" ) ) *63 (Net -uid 2267,0 -decl (Decl -n "CLK_50" -t "std_logic" -preAdd 0 -posAdd 0 -o 51 -suid 54,0 -) -declText (MLText -uid 2268,0 -va (VaSet -font "Courier New,8,0" -) -xt "39000,44800,57000,45600" -st "SIGNAL CLK_50 : std_logic" -) -) -*64 (Net uid 2407,0 decl (Decl n "RSRLOAD" t "std_logic" -o 35 +o 36 suid 57,0 i "'0'" @@ -2451,9 +2413,9 @@ font "Courier New,8,0" ) -xt "39000,31000,68000,31800" +xt "39000,31800,68000,32600" st "RSRLOAD : std_logic := '0'" ) ) -*65 (PortIoOut +*64 (PortIoOut uid 2415,0 shape (CompositeShape @@ -2500,10 +2462,10 @@ ) ) -*66 (Net +*65 (Net uid 2421,0 decl (Decl n "SRCLK" t "std_logic" -o 52 +o 53 suid 58,0 i "'0'" @@ -2514,9 +2476,9 @@ font "Courier New,8,0" ) -xt "39000,45600,71500,46400" +xt "39000,46400,71500,47200" st "SIGNAL SRCLK : std_logic := '0'" ) ) -*67 (Net +*66 (Net uid 3019,0 decl (Decl @@ -2524,5 +2486,5 @@ t "std_logic_vector" b "(3 DOWNTO 0)" -o 59 +o 60 suid 65,0 ) @@ -2532,14 +2494,14 @@ font "Courier New,8,0" ) -xt "39000,51200,67000,52000" +xt "39000,52000,67000,52800" st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" ) ) -*68 (Net +*67 (Net uid 3025,0 decl (Decl n "DAC_CS" t "std_logic" -o 21 +o 22 suid 66,0 ) @@ -2549,9 +2511,9 @@ font "Courier New,8,0" ) -xt "39000,19800,53500,20600" +xt "39000,20600,53500,21400" st "DAC_CS : std_logic" ) ) -*69 (PortIoOut +*68 (PortIoOut uid 3153,0 shape (CompositeShape @@ -2598,5 +2560,5 @@ ) ) -*70 (Net +*69 (Net uid 3216,0 decl (Decl @@ -2617,5 +2579,5 @@ ) ) -*71 (Net +*70 (Net uid 3226,0 decl (Decl @@ -2634,8 +2596,8 @@ ) ) -*72 (HdlText +*71 (HdlText uid 3248,0 optionalChildren [ -*73 (EmbeddedText +*72 (EmbeddedText uid 3254,0 commentText (CommentText @@ -2689,5 +2651,5 @@ stg "VerticalLayoutStrategy" textVec [ -*74 (Text +*73 (Text uid 3251,0 va (VaSet @@ -2699,5 +2661,5 @@ tm "HdlTextNameMgr" ) -*75 (Text +*74 (Text uid 3252,0 va (VaSet @@ -2725,5 +2687,5 @@ viewiconposition 0 ) -*76 (Net +*75 (Net uid 3266,0 decl (Decl @@ -2731,5 +2693,5 @@ t "std_logic_vector" b "(3 downto 0)" -o 16 +o 17 suid 71,0 ) @@ -2739,14 +2701,14 @@ font "Courier New,8,0" ) -xt "39000,15800,63500,16600" +xt "39000,16600,63500,17400" st "A_CLK : std_logic_vector(3 downto 0)" ) ) -*77 (Net +*76 (Net uid 3268,0 decl (Decl n "CLK_25_PS" t "std_logic" -o 50 +o 51 suid 72,0 ) @@ -2756,9 +2718,9 @@ font "Courier New,8,0" ) -xt "39000,44000,57000,44800" +xt "39000,44800,57000,45600" st "SIGNAL CLK_25_PS : std_logic" ) ) -*78 (PortIoOut +*77 (PortIoOut uid 3284,0 shape (CompositeShape @@ -2805,5 +2767,5 @@ ) ) -*79 (Net +*78 (Net uid 3290,0 decl (Decl @@ -2812,5 +2774,5 @@ preAdd 0 posAdd 0 -o 30 +o 31 suid 73,0 ) @@ -2820,9 +2782,9 @@ font "Courier New,8,0" ) -xt "39000,27000,53500,27800" +xt "39000,27800,53500,28600" st "OE_ADC : STD_LOGIC" ) ) -*80 (PortIoIn +*79 (PortIoIn uid 3292,0 shape (CompositeShape @@ -2869,5 +2831,5 @@ ) ) -*81 (Net +*80 (Net uid 3298,0 decl (Decl @@ -2887,8 +2849,8 @@ ) ) -*82 (HdlText +*81 (HdlText uid 3300,0 optionalChildren [ -*83 (EmbeddedText +*82 (EmbeddedText uid 3306,0 commentText (CommentText @@ -2942,5 +2904,5 @@ stg "VerticalLayoutStrategy" textVec [ -*84 (Text +*83 (Text uid 3303,0 va (VaSet @@ -2952,5 +2914,5 @@ tm "HdlTextNameMgr" ) -*85 (Text +*84 (Text uid 3304,0 va (VaSet @@ -2978,5 +2940,5 @@ viewiconposition 0 ) -*86 (PortIoIn +*85 (PortIoIn uid 3310,0 shape (CompositeShape @@ -3023,5 +2985,5 @@ ) ) -*87 (PortIoIn +*86 (PortIoIn uid 3332,0 shape (CompositeShape @@ -3068,5 +3030,5 @@ ) ) -*88 (PortIoIn +*87 (PortIoIn uid 3338,0 shape (CompositeShape @@ -3113,5 +3075,5 @@ ) ) -*89 (PortIoIn +*88 (PortIoIn uid 3344,0 shape (CompositeShape @@ -3158,5 +3120,5 @@ ) ) -*90 (Net +*89 (Net uid 3374,0 decl (Decl @@ -3176,5 +3138,5 @@ ) ) -*91 (Net +*90 (Net uid 3376,0 decl (Decl @@ -3194,5 +3156,5 @@ ) ) -*92 (Net +*91 (Net uid 3378,0 decl (Decl @@ -3212,5 +3174,5 @@ ) ) -*93 (Net +*92 (Net uid 3380,0 decl (Decl @@ -3230,8 +3192,8 @@ ) ) -*94 (HdlText +*93 (HdlText uid 3394,0 optionalChildren [ -*95 (EmbeddedText +*94 (EmbeddedText uid 3400,0 commentText (CommentText @@ -3285,5 +3247,5 @@ stg "VerticalLayoutStrategy" textVec [ -*96 (Text +*95 (Text uid 3397,0 va (VaSet @@ -3295,5 +3257,5 @@ tm "HdlTextNameMgr" ) -*97 (Text +*96 (Text uid 3398,0 va (VaSet @@ -3321,10 +3283,10 @@ viewiconposition 0 ) -*98 (Net +*97 (Net uid 3460,0 decl (Decl n "D0_SRCLK" t "STD_LOGIC" -o 17 +o 18 suid 87,0 ) @@ -3334,14 +3296,14 @@ font "Courier New,8,0" ) -xt "39000,16600,53500,17400" +xt "39000,17400,53500,18200" st "D0_SRCLK : STD_LOGIC" ) ) -*99 (Net +*98 (Net uid 3462,0 decl (Decl n "D1_SRCLK" t "STD_LOGIC" -o 18 +o 19 suid 88,0 ) @@ -3351,14 +3313,14 @@ font "Courier New,8,0" ) -xt "39000,17400,53500,18200" +xt "39000,18200,53500,19000" st "D1_SRCLK : STD_LOGIC" ) ) -*100 (Net +*99 (Net uid 3464,0 decl (Decl n "D2_SRCLK" t "STD_LOGIC" -o 19 +o 20 suid 89,0 ) @@ -3368,14 +3330,14 @@ font "Courier New,8,0" ) -xt "39000,18200,53500,19000" +xt "39000,19000,53500,19800" st "D2_SRCLK : STD_LOGIC" ) ) -*101 (Net +*100 (Net uid 3466,0 decl (Decl n "D3_SRCLK" t "STD_LOGIC" -o 20 +o 21 suid 90,0 ) @@ -3385,9 +3347,9 @@ font "Courier New,8,0" ) -xt "39000,19000,53500,19800" +xt "39000,19800,53500,20600" st "D3_SRCLK : STD_LOGIC" ) ) -*102 (PortIoIn +*101 (PortIoIn uid 3476,0 shape (CompositeShape @@ -3434,5 +3396,5 @@ ) ) -*103 (PortIoIn +*102 (PortIoIn uid 3482,0 shape (CompositeShape @@ -3479,5 +3441,5 @@ ) ) -*104 (PortIoIn +*103 (PortIoIn uid 3488,0 shape (CompositeShape @@ -3524,5 +3486,5 @@ ) ) -*105 (PortIoIn +*104 (PortIoIn uid 3494,0 shape (CompositeShape @@ -3569,5 +3531,5 @@ ) ) -*106 (Net +*105 (Net uid 3500,0 decl (Decl @@ -3586,5 +3548,5 @@ ) ) -*107 (Net +*106 (Net uid 3502,0 decl (Decl @@ -3603,5 +3565,5 @@ ) ) -*108 (Net +*107 (Net uid 3504,0 decl (Decl @@ -3620,5 +3582,5 @@ ) ) -*109 (Net +*108 (Net uid 3506,0 decl (Decl @@ -3637,5 +3599,5 @@ ) ) -*110 (PortIoOut +*109 (PortIoOut uid 3508,0 shape (CompositeShape @@ -3650,5 +3612,5 @@ sl 0 ro 90 -xt "19000,108625,20500,109375" +xt "4000,133625,5500,134375" ) (Line @@ -3656,8 +3618,8 @@ sl 0 ro 90 -xt "20500,109000,21000,109000" -pts [ -"21000,109000" -"20500,109000" +xt "5500,134000,6000,134000" +pts [ +"6000,134000" +"5500,134000" ] ) @@ -3674,13 +3636,13 @@ va (VaSet ) -xt "16100,108500,18000,109500" +xt "1100,133500,3000,134500" st "D_A" ju 2 -blo "18000,109300" -tm "WireNameMgr" -) -) -) -*111 (Net +blo "3000,134300" +tm "WireNameMgr" +) +) +) +*110 (Net uid 3514,0 decl (Decl @@ -3688,5 +3650,5 @@ t "std_logic_vector" b "(3 DOWNTO 0)" -o 24 +o 25 suid 95,0 i "(others => '0')" @@ -3697,9 +3659,9 @@ font "Courier New,8,0" ) -xt "39000,22200,74000,23000" +xt "39000,23000,74000,23800" st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0')" ) ) -*112 (PortIoOut +*111 (PortIoOut uid 3516,0 shape (CompositeShape @@ -3746,10 +3708,10 @@ ) ) -*113 (Net +*112 (Net uid 3522,0 decl (Decl n "DWRITE" t "std_logic" -o 23 +o 24 suid 96,0 i "'0'" @@ -3760,9 +3722,9 @@ font "Courier New,8,0" ) -xt "39000,21400,68000,22200" +xt "39000,22200,68000,23000" st "DWRITE : std_logic := '0'" ) ) -*114 (PortIoOut +*113 (PortIoOut uid 3536,0 shape (CompositeShape @@ -3808,8 +3770,8 @@ ) ) -*115 (HdlText +*114 (HdlText uid 3542,0 optionalChildren [ -*116 (EmbeddedText +*115 (EmbeddedText uid 3612,0 commentText (CommentText @@ -3863,5 +3825,5 @@ stg "VerticalLayoutStrategy" textVec [ -*117 (Text +*116 (Text uid 3545,0 va (VaSet @@ -3873,5 +3835,5 @@ tm "HdlTextNameMgr" ) -*118 (Text +*117 (Text uid 3546,0 va (VaSet @@ -3899,5 +3861,5 @@ viewiconposition 0 ) -*119 (PortIoOut +*118 (PortIoOut uid 3548,0 shape (CompositeShape @@ -3943,5 +3905,5 @@ ) ) -*120 (PortIoOut +*119 (PortIoOut uid 3554,0 shape (CompositeShape @@ -3987,5 +3949,5 @@ ) ) -*121 (PortIoOut +*120 (PortIoOut uid 3560,0 shape (CompositeShape @@ -4031,5 +3993,5 @@ ) ) -*122 (PortIoOut +*121 (PortIoOut uid 3566,0 shape (CompositeShape @@ -4075,10 +4037,10 @@ ) ) -*123 (Net +*122 (Net uid 3604,0 decl (Decl n "T0_CS" t "std_logic" -o 38 +o 39 suid 101,0 ) @@ -4088,14 +4050,14 @@ font "Courier New,8,0" ) -xt "39000,33400,53500,34200" +xt "39000,34200,53500,35000" st "T0_CS : std_logic" ) ) -*124 (Net +*123 (Net uid 3606,0 decl (Decl n "T1_CS" t "std_logic" -o 39 +o 40 suid 102,0 ) @@ -4105,14 +4067,14 @@ font "Courier New,8,0" ) -xt "39000,34200,53500,35000" +xt "39000,35000,53500,35800" st "T1_CS : std_logic" ) ) -*125 (Net +*124 (Net uid 3608,0 decl (Decl n "T2_CS" t "std_logic" -o 40 +o 41 suid 103,0 ) @@ -4122,14 +4084,14 @@ font "Courier New,8,0" ) -xt "39000,35000,53500,35800" +xt "39000,35800,53500,36600" st "T2_CS : std_logic" ) ) -*126 (Net +*125 (Net uid 3610,0 decl (Decl n "T3_CS" t "std_logic" -o 41 +o 42 suid 104,0 ) @@ -4139,9 +4101,9 @@ font "Courier New,8,0" ) -xt "39000,35800,53500,36600" +xt "39000,36600,53500,37400" st "T3_CS : std_logic" ) ) -*127 (PortIoOut +*126 (PortIoOut uid 3624,0 shape (CompositeShape @@ -4187,10 +4149,10 @@ ) ) -*128 (Net +*127 (Net uid 3630,0 decl (Decl n "S_CLK" t "std_logic" -o 37 +o 38 suid 105,0 ) @@ -4200,9 +4162,9 @@ font "Courier New,8,0" ) -xt "39000,32600,53500,33400" +xt "39000,33400,53500,34200" st "S_CLK : std_logic" ) ) -*129 (Net +*128 (Net uid 3632,0 decl (Decl @@ -4210,5 +4172,5 @@ t "std_logic_vector" b "(9 DOWNTO 0)" -o 43 +o 44 suid 106,0 ) @@ -4218,9 +4180,9 @@ font "Courier New,8,0" ) -xt "39000,37400,63500,38200" +xt "39000,38200,63500,39000" st "W_A : std_logic_vector(9 DOWNTO 0)" ) ) -*130 (Net +*129 (Net uid 3634,0 decl (Decl @@ -4228,5 +4190,5 @@ t "std_logic_vector" b "(15 DOWNTO 0)" -o 49 +o 50 suid 107,0 ) @@ -4236,14 +4198,14 @@ font "Courier New,8,0" ) -xt "39000,42200,64000,43000" +xt "39000,43000,64000,43800" st "W_D : std_logic_vector(15 DOWNTO 0)" ) ) -*131 (Net +*130 (Net uid 3636,0 decl (Decl n "W_RES" t "std_logic" -o 46 +o 47 suid 108,0 i "'1'" @@ -4254,14 +4216,14 @@ font "Courier New,8,0" ) -xt "39000,39800,68000,40600" +xt "39000,40600,68000,41400" st "W_RES : std_logic := '1'" ) ) -*132 (Net +*131 (Net uid 3638,0 decl (Decl n "W_RD" t "std_logic" -o 45 +o 46 suid 109,0 i "'1'" @@ -4272,14 +4234,14 @@ font "Courier New,8,0" ) -xt "39000,39000,68000,39800" +xt "39000,39800,68000,40600" st "W_RD : std_logic := '1'" ) ) -*133 (Net +*132 (Net uid 3640,0 decl (Decl n "W_WR" t "std_logic" -o 47 +o 48 suid 110,0 i "'1'" @@ -4290,9 +4252,9 @@ font "Courier New,8,0" ) -xt "39000,40600,68000,41400" +xt "39000,41400,68000,42200" st "W_WR : std_logic := '1'" ) ) -*134 (Net +*133 (Net uid 3642,0 decl (Decl @@ -4311,10 +4273,10 @@ ) ) -*135 (Net +*134 (Net uid 3644,0 decl (Decl n "W_CS" t "std_logic" -o 44 +o 45 suid 112,0 i "'1'" @@ -4325,9 +4287,9 @@ font "Courier New,8,0" ) -xt "39000,38200,68000,39000" +xt "39000,39000,68000,39800" st "W_CS : std_logic := '1'" ) ) -*136 (PortIoInOut +*135 (PortIoInOut uid 3674,0 shape (CompositeShape @@ -4371,10 +4333,10 @@ ) ) -*137 (Net +*136 (Net uid 3680,0 decl (Decl n "MOSI" t "std_logic" -o 29 +o 30 suid 113,0 i "'0'" @@ -4385,9 +4347,9 @@ font "Courier New,8,0" ) -xt "39000,26200,68000,27000" +xt "39000,27000,68000,27800" st "MOSI : std_logic := '0'" ) ) -*138 (PortIoOut +*137 (PortIoOut uid 3688,0 shape (CompositeShape @@ -4433,5 +4395,5 @@ ) ) -*139 (Net +*138 (Net uid 3694,0 decl (Decl @@ -4440,5 +4402,5 @@ preAdd 0 posAdd 0 -o 48 +o 49 suid 114,0 ) @@ -4448,12 +4410,12 @@ font "Courier New,8,0" ) -xt "39000,41400,53500,42200" +xt "39000,42200,53500,43000" st "MISO : std_logic" ) ) -*140 (HdlText +*139 (HdlText uid 3700,0 optionalChildren [ -*141 (EmbeddedText +*140 (EmbeddedText uid 3706,0 commentText (CommentText @@ -4522,5 +4484,5 @@ stg "VerticalLayoutStrategy" textVec [ -*142 (Text +*141 (Text uid 3703,0 va (VaSet @@ -4532,5 +4494,5 @@ tm "HdlTextNameMgr" ) -*143 (Text +*142 (Text uid 3704,0 va (VaSet @@ -4558,5 +4520,5 @@ viewiconposition 0 ) -*144 (PortIoOut +*143 (PortIoOut uid 3710,0 shape (CompositeShape @@ -4602,5 +4564,5 @@ ) ) -*145 (PortIoOut +*144 (PortIoOut uid 3716,0 shape (CompositeShape @@ -4646,5 +4608,5 @@ ) ) -*146 (PortIoOut +*145 (PortIoOut uid 3722,0 shape (CompositeShape @@ -4690,5 +4652,5 @@ ) ) -*147 (PortIoOut +*146 (PortIoOut uid 3728,0 shape (CompositeShape @@ -4734,5 +4696,5 @@ ) ) -*148 (PortIoOut +*147 (PortIoOut uid 3734,0 shape (CompositeShape @@ -4778,5 +4740,5 @@ ) ) -*149 (PortIoOut +*148 (PortIoOut uid 3740,0 shape (CompositeShape @@ -4822,5 +4784,5 @@ ) ) -*150 (PortIoOut +*149 (PortIoOut uid 3746,0 shape (CompositeShape @@ -4866,5 +4828,5 @@ ) ) -*151 (PortIoOut +*150 (PortIoOut uid 3752,0 shape (CompositeShape @@ -4910,5 +4872,5 @@ ) ) -*152 (PortIoOut +*151 (PortIoOut uid 3758,0 shape (CompositeShape @@ -4954,10 +4916,10 @@ ) ) -*153 (Net +*152 (Net uid 3864,0 decl (Decl n "TRG_V" t "std_logic" -o 42 +o 43 suid 126,0 ) @@ -4967,14 +4929,14 @@ font "Courier New,8,0" ) -xt "39000,36600,53500,37400" +xt "39000,37400,53500,38200" st "TRG_V : std_logic" ) ) -*154 (Net +*153 (Net uid 3866,0 decl (Decl n "RS485_C_RE" t "std_logic" -o 32 +o 33 suid 127,0 ) @@ -4984,14 +4946,14 @@ font "Courier New,8,0" ) -xt "39000,28600,53500,29400" +xt "39000,29400,53500,30200" st "RS485_C_RE : std_logic" ) ) -*155 (Net +*154 (Net uid 3868,0 decl (Decl n "RS485_C_DE" t "std_logic" -o 31 +o 32 suid 128,0 ) @@ -5001,14 +4963,14 @@ font "Courier New,8,0" ) -xt "39000,27800,53500,28600" +xt "39000,28600,53500,29400" st "RS485_C_DE : std_logic" ) ) -*156 (Net +*155 (Net uid 3870,0 decl (Decl n "RS485_E_RE" t "std_logic" -o 34 +o 35 suid 129,0 ) @@ -5018,14 +4980,14 @@ font "Courier New,8,0" ) -xt "39000,30200,53500,31000" +xt "39000,31000,53500,31800" st "RS485_E_RE : std_logic" ) ) -*157 (Net +*156 (Net uid 3872,0 decl (Decl n "RS485_E_DE" t "std_logic" -o 33 +o 34 suid 130,0 ) @@ -5035,14 +4997,14 @@ font "Courier New,8,0" ) -xt "39000,29400,53500,30200" +xt "39000,30200,53500,31000" st "RS485_E_DE : std_logic" ) ) -*158 (Net +*157 (Net uid 3874,0 decl (Decl n "DENABLE" t "std_logic" -o 22 +o 23 suid 131,0 i "'0'" @@ -5053,14 +5015,14 @@ font "Courier New,8,0" ) -xt "39000,20600,68000,21400" +xt "39000,21400,68000,22200" st "DENABLE : std_logic := '0'" ) ) -*159 (Net +*158 (Net uid 3876,0 decl (Decl n "SRIN" t "std_logic" -o 36 +o 37 suid 132,0 ) @@ -5070,14 +5032,14 @@ font "Courier New,8,0" ) -xt "39000,31800,53500,32600" +xt "39000,32600,53500,33400" st "SRIN : std_logic" ) ) -*160 (Net +*159 (Net uid 3878,0 decl (Decl n "EE_CS" t "std_logic" -o 27 +o 28 suid 133,0 ) @@ -5087,9 +5049,9 @@ font "Courier New,8,0" ) -xt "39000,24600,53500,25400" +xt "39000,25400,53500,26200" st "EE_CS : std_logic" ) ) -*161 (Net +*160 (Net uid 3880,0 decl (Decl @@ -5097,5 +5059,5 @@ t "std_logic_vector" b "( 2 DOWNTO 0 )" -o 28 +o 29 suid 134,0 i "(others => '1')" @@ -5106,9 +5068,9 @@ font "Courier New,8,0" ) -xt "39000,25400,74000,26200" +xt "39000,26200,74000,27000" st "LED : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')" ) ) -*162 (PortIoOut +*161 (PortIoOut uid 3995,0 shape (CompositeShape @@ -5155,5 +5117,5 @@ ) ) -*163 (PortIoOut +*162 (PortIoOut uid 4001,0 shape (CompositeShape @@ -5200,5 +5162,5 @@ ) ) -*164 (PortIoOut +*163 (PortIoOut uid 4007,0 shape (CompositeShape @@ -5245,5 +5207,5 @@ ) ) -*165 (PortIoOut +*164 (PortIoOut uid 4013,0 shape (CompositeShape @@ -5290,5 +5252,5 @@ ) ) -*166 (PortIoOut +*165 (PortIoOut uid 4916,0 shape (CompositeShape @@ -5334,5 +5296,5 @@ ) ) -*167 (Net +*166 (Net uid 5320,0 decl (Decl @@ -5340,5 +5302,5 @@ t "std_logic_vector" b "(7 DOWNTO 0)" -o 25 +o 26 suid 141,0 i "(OTHERS => '0')" @@ -5349,9 +5311,9 @@ font "Courier New,8,0" ) -xt "39000,23000,74000,23800" +xt "39000,23800,74000,24600" st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" ) ) -*168 (PortIoIn +*167 (PortIoIn uid 5650,0 shape (CompositeShape @@ -5366,5 +5328,5 @@ sl 0 ro 270 -xt "-30000,88625,-28500,89375" +xt "9000,78625,10500,79375" ) (Line @@ -5372,8 +5334,8 @@ sl 0 ro 270 -xt "-28500,89000,-28000,89000" -pts [ -"-28500,89000" -"-28000,89000" +xt "10500,79000,11000,79000" +pts [ +"10500,79000" +"11000,79000" ] ) @@ -5390,13 +5352,13 @@ va (VaSet ) -xt "-35500,88500,-31000,89500" +xt "3500,78500,8000,79500" st "TEST_TRG" ju 2 -blo "-31000,89300" -tm "WireNameMgr" -) -) -) -*169 (Net +blo "8000,79300" +tm "WireNameMgr" +) +) +) +*168 (Net uid 5662,0 decl (Decl @@ -5415,10 +5377,10 @@ ) ) -*170 (Net +*169 (Net uid 6138,0 decl (Decl n "TRG_OR" t "std_logic" -o 53 +o 54 suid 146,0 ) @@ -5428,503 +5390,15 @@ font "Courier New,8,0" ) -xt "39000,46400,57000,47200" +xt "39000,47200,57000,48000" st "SIGNAL TRG_OR : std_logic" ) ) -*171 (SaComponent -uid 6250,0 -optionalChildren [ -*172 (CptPort -uid 6235,0 -ps "OnEdgeStrategy" -shape (Triangle -uid 6236,0 -ro 90 -va (VaSet -vasetType 1 -fg "0,65535,0" -) -xt "-11750,87625,-11000,88375" -) -tg (CPTG -uid 6237,0 -ps "CptPortTextPlaceStrategy" -stg "VerticalLayoutStrategy" -f (Text -uid 6238,0 -va (VaSet -) -xt "-10000,87500,-8700,88500" -st "clk" -blo "-10000,88300" -) -) -thePort (LogicalPort -decl (Decl -n "clk" -t "STD_LOGIC" -preAdd 0 -posAdd 0 -o 1 -suid 1,0 -) -) -) -*173 (CptPort -uid 6239,0 -ps "OnEdgeStrategy" -shape (Triangle -uid 6240,0 -ro 90 -va (VaSet -vasetType 1 -fg "0,65535,0" -) -xt "-11750,88625,-11000,89375" -) -tg (CPTG -uid 6241,0 -ps "CptPortTextPlaceStrategy" -stg "VerticalLayoutStrategy" -f (Text -uid 6242,0 -va (VaSet -) -xt "-10000,88500,-5800,89500" -st "trigger_in" -blo "-10000,89300" -) -) -thePort (LogicalPort -decl (Decl -n "trigger_in" -t "STD_LOGIC" -prec "-- rst : in STD_LOGIC;" -preAdd 0 -posAdd 0 -o 2 -suid 2,0 -) -) -) -*174 (CptPort -uid 6243,0 -ps "OnEdgeStrategy" -shape (Triangle -uid 6244,0 -ro 90 -va (VaSet -vasetType 1 -fg "0,65535,0" -) -xt "1000,88625,1750,89375" -) -tg (CPTG -uid 6245,0 -ps "CptPortTextPlaceStrategy" -stg "RightVerticalLayoutStrategy" -f (Text -uid 6246,0 -va (VaSet -) -xt "-4600,88500,0,89500" -st "trigger_out" -ju 2 -blo "0,89300" -) -) -thePort (LogicalPort -m 1 -decl (Decl -n "trigger_out" -t "STD_LOGIC" -preAdd 0 -posAdd 0 -o 3 -suid 3,0 -i "'0'" -) -) -) -] -shape (Rectangle -uid 6251,0 -va (VaSet -vasetType 1 -fg "0,65535,0" -lineColor "0,32896,0" -lineWidth 2 -) -xt "-11000,87000,1000,92000" -) -oxt "25000,13000,37000,18000" -ttg (MlTextGroup -uid 6252,0 -ps "CenterOffsetStrategy" -stg "VerticalLayoutStrategy" -textVec [ -*175 (Text -uid 6253,0 -va (VaSet -font "Arial,8,1" -) -xt "-10800,92000,-4200,93000" -st "FACT_FAD_LIB" -blo "-10800,92800" -tm "BdLibraryNameMgr" -) -*176 (Text -uid 6254,0 -va (VaSet -font "Arial,8,1" -) -xt "-10800,93000,-6400,94000" -st "debouncer" -blo "-10800,93800" -tm "CptNameMgr" -) -*177 (Text -uid 6255,0 -va (VaSet -font "Arial,8,1" -) -xt "-10800,94000,-9800,95000" -st "I0" -blo "-10800,94800" -tm "InstanceNameMgr" -) -] -) -ga (GenericAssociation -uid 6256,0 -ps "EdgeToEdgeStrategy" -matrix (Matrix -uid 6257,0 -text (MLText -uid 6258,0 -va (VaSet -font "Courier New,8,0" -) -xt "-11000,86200,4000,87000" -st "WIDTH = 17 ( INTEGER ) " -) -header "" -) -elements [ -(GiElement -name "WIDTH" -type "INTEGER" -value "17" -) -] -) -viewicon (ZoomableIcon -uid 6259,0 -sl 0 -va (VaSet -vasetType 1 -fg "49152,49152,49152" -) -xt "-10750,90250,-9250,91750" -iconName "VhdlFileViewIcon.png" -iconMaskName "VhdlFileViewIcon.msk" -ftype 10 -) -ordering 1 -viewiconposition 0 -portVis (PortSigDisplay -) -archFileType "UNKNOWN" -) -*178 (Net -uid 6278,0 -decl (Decl -n "trigger_out" -t "STD_LOGIC" -preAdd 0 -posAdd 0 -o 60 -suid 147,0 -i "'0'" -) -declText (MLText -uid 6279,0 -va (VaSet -font "Courier New,8,0" -) -xt "39000,52000,71500,52800" -st "SIGNAL trigger_out : STD_LOGIC := '0'" -) -) -*179 (Net -uid 6326,0 -decl (Decl -n "not_TEST_TRG" -t "STD_LOGIC" -o 58 -suid 148,0 -) -declText (MLText -uid 6327,0 -va (VaSet -font "Courier New,8,0" -) -xt "39000,50400,57000,51200" -st "SIGNAL not_TEST_TRG : STD_LOGIC" -) -) -*180 (MWC -uid 6539,0 -optionalChildren [ -*181 (CptPort -uid 6526,0 -optionalChildren [ -*182 (Line -uid 6530,0 -layer 5 -sl 0 -va (VaSet -vasetType 3 -) -xt "-22000,89000,-20999,89000" -pts [ -"-22000,89000" -"-20999,89000" -] -) -] -ps "OnEdgeStrategy" -shape (Triangle -uid 6527,0 -ro 90 -va (VaSet -vasetType 1 -isHidden 1 -fg "0,65535,65535" -) -xt "-22750,88625,-22000,89375" -) -tg (CPTG -uid 6528,0 -ps "CptPortTextPlaceStrategy" -stg "VerticalLayoutStrategy" -f (Text -uid 6529,0 -sl 0 -va (VaSet -isHidden 1 -font "arial,8,0" -) -xt "-25000,88500,-23600,89500" -st "din" -blo "-25000,89300" -) -s (Text -uid 6548,0 -sl 0 -va (VaSet -font "arial,8,0" -) -xt "-25000,89500,-25000,89500" -blo "-25000,89500" -) -) -thePort (LogicalPort -decl (Decl -n "din" -t "std_logic" -o 11 -suid 1,0 -) -) -) -*183 (CptPort -uid 6531,0 -optionalChildren [ -*184 (Line -uid 6535,0 -layer 5 -sl 0 -va (VaSet -vasetType 3 -) -xt "-17249,89000,-17000,89000" -pts [ -"-17000,89000" -"-17249,89000" -] -) -*185 (Circle -uid 6536,0 -va (VaSet -vasetType 1 -fg "65535,65535,65535" -lineColor "26368,26368,26368" -) -xt "-17999,88625,-17249,89375" -radius 375 -) -] -ps "OnEdgeStrategy" -shape (Triangle -uid 6532,0 -ro 90 -va (VaSet -vasetType 1 -isHidden 1 -fg "0,65535,65535" -) -xt "-17000,88625,-16250,89375" -) -tg (CPTG -uid 6533,0 -ps "CptPortTextPlaceStrategy" -stg "RightVerticalLayoutStrategy" -f (Text -uid 6534,0 -sl 0 -va (VaSet -isHidden 1 -font "arial,8,0" -) -xt "-15050,88500,-13250,89500" -st "dout" -ju 2 -blo "-13250,89300" -) -s (Text -uid 6549,0 -sl 0 -va (VaSet -font "arial,8,0" -) -xt "-13250,89500,-13250,89500" -ju 2 -blo "-13250,89500" -) -) -thePort (LogicalPort -m 1 -decl (Decl -n "dout" -t "STD_LOGIC" -o 58 -suid 2,0 -) -) -) -*186 (CommentGraphic -uid 6537,0 -shape (CustomPolygon -pts [ -"-21000,87000" -"-18000,89000" -"-21000,91000" -"-21000,87000" -] -uid 6538,0 -layer 0 -sl 0 -va (VaSet -vasetType 1 -fg "0,65535,65535" -bg "0,65535,65535" -lineColor "26368,26368,26368" -) -xt "-21000,87000,-18000,91000" -) -oxt "7000,6000,10000,10000" -) -] -shape (Rectangle -uid 6540,0 -va (VaSet -vasetType 1 -transparent 1 -fg "0,65535,0" -lineColor "65535,65535,65535" -lineWidth -1 -) -xt "-22000,87000,-17000,91000" -fos 1 -) -showPorts 0 -oxt "6000,6000,11000,10000" -ttg (MlTextGroup -uid 6541,0 -ps "CenterOffsetStrategy" -stg "VerticalLayoutStrategy" -textVec [ -*187 (Text -uid 6542,0 -va (VaSet -isHidden 1 -font "arial,8,0" -) -xt "-19650,89100,-14850,90100" -st "moduleware" -blo "-19650,89900" -) -*188 (Text -uid 6543,0 -va (VaSet -font "arial,8,0" -) -xt "-19650,90100,-18350,91100" -st "inv" -blo "-19650,90900" -) -*189 (Text -uid 6544,0 -va (VaSet -font "arial,8,0" -) -xt "-19650,91100,-18650,92100" -st "I1" -blo "-19650,91900" -tm "InstanceNameMgr" -) -] -) -ga (GenericAssociation -uid 6545,0 -ps "EdgeToEdgeStrategy" -matrix (Matrix -uid 6546,0 -text (MLText -uid 6547,0 -va (VaSet -font "arial,8,0" -) -xt "-25000,68400,-25000,68400" -) -header "" -) -elements [ -] -) -sed 1 -awe 1 -portVis (PortSigDisplay -disp 1 -sN 0 -sTC 0 -selT 0 -) -prms (Property -pclass "params" -pname "params" -ptn "String" -) -visOptions (mwParamsVisibilityOptions -) -) -*190 (MWC +*170 (MWC uid 6586,0 optionalChildren [ -*191 (CptPort +*171 (CptPort uid 6550,0 optionalChildren [ -*192 (Line +*172 (Line uid 6554,0 layer 5 @@ -5970,17 +5444,14 @@ decl (Decl n "din1" -t "STD_LOGIC" -preAdd 0 -posAdd 0 -o 60 +t "std_logic" +o 11 suid 1,0 -i "'0'" -) -) -) -*193 (CptPort +) +) +) +*173 (CptPort uid 6555,0 optionalChildren [ -*194 (Property +*174 (Property uid 6559,0 pclass "_MW_GEOM_" @@ -5988,5 +5459,5 @@ ptn "String" ) -*195 (Line +*175 (Line uid 6560,0 layer 5 @@ -6035,13 +5506,13 @@ n "dout" t "std_logic" -o 53 +o 54 suid 2,0 ) ) ) -*196 (CptPort +*176 (CptPort uid 6561,0 optionalChildren [ -*197 (Line +*177 (Line uid 6565,0 layer 5 @@ -6093,5 +5564,5 @@ ) ) -*198 (CommentGraphic +*178 (CommentGraphic uid 6566,0 shape (Arc2D @@ -6114,5 +5585,5 @@ oxt "7000,6003,11000,8000" ) -*199 (CommentGraphic +*179 (CommentGraphic uid 6568,0 shape (Arc2D @@ -6135,11 +5606,11 @@ oxt "6996,8005,11000,10000" ) -*200 (Grouping +*180 (Grouping uid 6570,0 optionalChildren [ -*201 (CommentGraphic +*181 (CommentGraphic uid 6572,0 optionalChildren [ -*202 (Property +*182 (Property uid 6574,0 pclass "_MW_GEOM_" @@ -6172,8 +5643,8 @@ oxt "7000,6000,11000,9998" ) -*203 (CommentGraphic +*183 (CommentGraphic uid 6575,0 optionalChildren [ -*204 (Property +*184 (Property uid 6577,0 pclass "_MW_GEOM_" @@ -6217,5 +5688,5 @@ oxt "7000,6000,11000,10000" ) -*205 (CommentGraphic +*185 (CommentGraphic uid 6578,0 shape (PolyLine2D @@ -6236,8 +5707,8 @@ oxt "11000,8000,11000,8000" ) -*206 (CommentGraphic +*186 (CommentGraphic uid 6580,0 optionalChildren [ -*207 (Property +*187 (Property uid 6582,0 pclass "_MW_GEOM_" @@ -6263,8 +5734,8 @@ oxt "7000,6000,7000,6000" ) -*208 (CommentGraphic +*188 (CommentGraphic uid 6583,0 optionalChildren [ -*209 (Property +*189 (Property uid 6585,0 pclass "_MW_GEOM_" @@ -6309,5 +5780,5 @@ stg "VerticalLayoutStrategy" textVec [ -*210 (Text +*190 (Text uid 6589,0 va (VaSet @@ -6319,5 +5790,5 @@ blo "15500,77300" ) -*211 (Text +*191 (Text uid 6590,0 va (VaSet @@ -6328,5 +5799,5 @@ blo "15500,78300" ) -*212 (Text +*192 (Text uid 6591,0 va (VaSet @@ -6373,5 +5844,5 @@ ) ) -*213 (PortIoIn +*193 (PortIoIn uid 6781,0 shape (CompositeShape @@ -6418,5 +5889,5 @@ ) ) -*214 (Net +*194 (Net uid 6793,0 decl (Decl @@ -6436,5 +5907,5 @@ ) ) -*215 (PortIoOut +*195 (PortIoOut uid 6874,0 shape (CompositeShape @@ -6480,5 +5951,5 @@ ) ) -*216 (Net +*196 (Net uid 6886,0 decl (Decl @@ -6486,5 +5957,5 @@ t "std_logic_vector" b "(3 DOWNTO 0)" -o 26 +o 27 suid 154,0 i "(others => '0')" @@ -6495,12 +5966,12 @@ font "Courier New,8,0" ) -xt "39000,23800,74000,24600" +xt "39000,24600,74000,25400" st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0')" ) ) -*217 (HdlText +*197 (HdlText uid 6888,0 optionalChildren [ -*218 (EmbeddedText +*198 (EmbeddedText uid 6894,0 commentText (CommentText @@ -6550,5 +6021,5 @@ stg "VerticalLayoutStrategy" textVec [ -*219 (Text +*199 (Text uid 6891,0 va (VaSet @@ -6560,5 +6031,5 @@ tm "HdlTextNameMgr" ) -*220 (Text +*200 (Text uid 6892,0 va (VaSet @@ -6586,8 +6057,8 @@ viewiconposition 0 ) -*221 (HdlText +*201 (HdlText uid 7092,0 optionalChildren [ -*222 (EmbeddedText +*202 (EmbeddedText uid 7098,0 commentText (CommentText @@ -6602,5 +6073,5 @@ lineWidth 2 ) -xt "27000,137000,45000,145000" +xt "26000,137000,46000,143000" ) oxt "0,0,18000,5000" @@ -6609,16 +6080,15 @@ va (VaSet ) -xt "27200,137200,39400,142200" +xt "26200,137200,40000,141200" st " -- eb2 8 -A1_T(0) <= dummy; -A1_T(1) <= RSRLOAD; -A1_T(2) <= D0_SROUT; -A1_T(3) <= D1_SROUT; +A1_T(3 downto 0) <= drs_channel_id; +D_A <= drs_channel_id; +A1_T(4) <= TRG_OR; " tm "HdlTextMgr" wrapOption 3 -visibleHeight 8000 -visibleWidth 18000 +visibleHeight 6000 +visibleWidth 20000 ) ) @@ -6641,5 +6111,5 @@ stg "VerticalLayoutStrategy" textVec [ -*223 (Text +*203 (Text uid 7095,0 va (VaSet @@ -6651,5 +6121,5 @@ tm "HdlTextNameMgr" ) -*224 (Text +*204 (Text uid 7096,0 va (VaSet @@ -6677,5 +6147,5 @@ viewiconposition 0 ) -*225 (PortIoOut +*205 (PortIoOut uid 7138,0 shape (CompositeShape @@ -6721,12 +6191,13 @@ ) ) -*226 (Net +*206 (Net uid 7150,0 decl (Decl n "A1_T" t "std_logic_vector" -b "(3 DOWNTO 0)" -o 15 +b "(7 DOWNTO 0)" +o 16 suid 155,0 +i "(OTHERS => '0')" ) declText (MLText @@ -6735,14 +6206,14 @@ font "Courier New,8,0" ) -xt "39000,15000,63500,15800" -st "A1_T : std_logic_vector(3 DOWNTO 0)" -) -) -*227 (Net +xt "39000,15800,74000,16600" +st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" +) +) +*207 (Net uid 7485,0 decl (Decl n "dummy" t "std_logic" -o 60 +o 59 suid 157,0 ) @@ -6752,15 +6223,15 @@ font "Courier New,8,0" ) -xt "39000,49600,57000,50400" +xt "39000,51200,57000,52000" st "SIGNAL dummy : std_logic" ) ) -*228 (MWC +*208 (MWC uid 7652,0 optionalChildren [ -*229 (CptPort +*209 (CptPort uid 7632,0 optionalChildren [ -*230 (Line +*210 (Line uid 7636,0 layer 5 @@ -6816,13 +6287,13 @@ n "s" t "std_logic" -o 60 +o 59 suid 1,0 ) ) ) -*231 (CptPort +*211 (CptPort uid 7637,0 optionalChildren [ -*232 (Line +*212 (Line uid 7641,0 layer 5 @@ -6881,10 +6352,10 @@ n "t" t "std_logic" -o 21 +o 22 suid 2,0 ) ) ) -*233 (CommentGraphic +*213 (CommentGraphic uid 7642,0 shape (PolyLine2D @@ -6907,5 +6378,5 @@ oxt "6000,6000,7000,7000" ) -*234 (CommentGraphic +*214 (CommentGraphic uid 7644,0 shape (PolyLine2D @@ -6928,5 +6399,5 @@ oxt "6000,7000,7000,8000" ) -*235 (CommentGraphic +*215 (CommentGraphic uid 7646,0 shape (PolyLine2D @@ -6949,5 +6420,5 @@ oxt "6988,7329,7988,7329" ) -*236 (CommentGraphic +*216 (CommentGraphic uid 7648,0 shape (PolyLine2D @@ -6968,5 +6439,5 @@ oxt "8000,7000,9000,7000" ) -*237 (CommentGraphic +*217 (CommentGraphic uid 7650,0 shape (PolyLine2D @@ -7009,5 +6480,5 @@ stg "VerticalLayoutStrategy" textVec [ -*238 (Text +*218 (Text uid 7655,0 va (VaSet @@ -7019,5 +6490,5 @@ blo "90350,83900" ) -*239 (Text +*219 (Text uid 7656,0 va (VaSet @@ -7028,5 +6499,5 @@ blo "90350,84900" ) -*240 (Text +*220 (Text uid 7657,0 va (VaSet @@ -7073,5 +6544,104 @@ ) ) -*241 (Wire +*221 (Net +uid 8851,0 +decl (Decl +n "drs_channel_id" +t "std_logic_vector" +b "(3 downto 0)" +o 58 +suid 159,0 +i "(others => '0')" +) +declText (MLText +uid 8852,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,50400,77500,51200" +st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" +) +) +*222 (Net +uid 9201,0 +decl (Decl +n "A0_T" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 15 +suid 162,0 +i "(OTHERS => '0')" +) +declText (MLText +uid 9202,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,15000,74000,15800" +st "A0_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" +) +) +*223 (PortIoOut +uid 9294,0 +shape (CompositeShape +uid 9295,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 9296,0 +sl 0 +ro 270 +xt "64500,139625,66000,140375" +) +(Line +uid 9297,0 +sl 0 +ro 270 +xt "64000,140000,64500,140000" +pts [ +"64000,140000" +"64500,140000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 9298,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 9299,0 +va (VaSet +) +xt "67000,139500,69200,140500" +st "A0_T" +blo "67000,140300" +tm "WireNameMgr" +) +) +) +*224 (Net +uid 9500,0 +decl (Decl +n "CLK_50" +t "std_logic" +o 52 +suid 163,0 +) +declText (MLText +uid 9501,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,45600,57000,46400" +st "SIGNAL CLK_50 : std_logic" +) +) +*225 (Wire uid 245,0 shape (OrthoPolyLine @@ -7110,7 +6680,7 @@ ) ) -on &70 -) -*242 (Wire +on &69 +) +*226 (Wire uid 277,0 shape (OrthoPolyLine @@ -7150,5 +6720,5 @@ on &53 ) -*243 (Wire +*227 (Wire uid 285,0 shape (OrthoPolyLine @@ -7188,5 +6758,5 @@ on &54 ) -*244 (Wire +*228 (Wire uid 362,0 shape (OrthoPolyLine @@ -7201,5 +6771,5 @@ ] ) -start &78 +start &77 end &16 sat 32 @@ -7224,7 +6794,7 @@ ) ) -on &79 -) -*245 (Wire +on &78 +) +*229 (Wire uid 418,0 shape (OrthoPolyLine @@ -7262,7 +6832,7 @@ ) ) -on &131 -) -*246 (Wire +on &130 +) +*230 (Wire uid 426,0 shape (OrthoPolyLine @@ -7302,7 +6872,7 @@ ) ) -on &129 -) -*247 (Wire +on &128 +) +*231 (Wire uid 434,0 shape (OrthoPolyLine @@ -7340,7 +6910,7 @@ ) ) -on &135 -) -*248 (Wire +on &134 +) +*232 (Wire uid 442,0 shape (OrthoPolyLine @@ -7380,7 +6950,7 @@ ) ) -on &130 -) -*249 (Wire +on &129 +) +*233 (Wire uid 450,0 shape (OrthoPolyLine @@ -7418,7 +6988,7 @@ ) ) -on &134 -) -*250 (Wire +on &133 +) +*234 (Wire uid 458,0 shape (OrthoPolyLine @@ -7456,7 +7026,7 @@ ) ) -on &132 -) -*251 (Wire +on &131 +) +*235 (Wire uid 466,0 shape (OrthoPolyLine @@ -7494,7 +7064,7 @@ ) ) -on &133 -) -*252 (Wire +on &132 +) +*236 (Wire uid 1467,0 shape (OrthoPolyLine @@ -7509,5 +7079,5 @@ ] ) -start &82 +start &81 end &28 sat 2 @@ -7532,5 +7102,5 @@ on &62 ) -*253 (Wire +*237 (Wire uid 1730,0 shape (OrthoPolyLine @@ -7546,5 +7116,5 @@ ] ) -start &80 +start &79 end &29 sat 32 @@ -7570,7 +7140,7 @@ ) ) -on &81 -) -*254 (Wire +on &80 +) +*238 (Wire uid 1833,0 shape (OrthoPolyLine @@ -7580,12 +7150,1393 @@ lineWidth 2 ) -xt "21000,109000,51250,109000" -pts [ -"51250,109000" -"21000,109000" -] -) -start &30 -end &110 +xt "6000,134000,31000,134000" +pts [ +"31000,134000" +"6000,134000" +] +) +start &201 +end &109 +sat 2 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1837,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1838,0 +va (VaSet +isHidden 1 +) +xt "7000,133000,8900,134000" +st "D_A" +blo "7000,133800" +tm "WireNameMgr" +) +) +on &110 +) +*239 (Wire +uid 1841,0 +shape (OrthoPolyLine +uid 1842,0 +va (VaSet +vasetType 3 +) +xt "21000,110000,51250,110000" +pts [ +"51250,110000" +"21000,110000" +] +) +start &31 +end &111 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1845,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1846,0 +va (VaSet +isHidden 1 +) +xt "22000,109000,25500,110000" +st "DWRITE" +blo "22000,109800" +tm "WireNameMgr" +) +) +on &112 +) +*240 (Wire +uid 1865,0 +shape (OrthoPolyLine +uid 1866,0 +va (VaSet +vasetType 3 +) +xt "21000,105000,51250,105000" +pts [ +"21000,105000" +"51250,105000" +] +) +start &101 +end &32 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1869,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1870,0 +va (VaSet +isHidden 1 +) +xt "22000,104000,26600,105000" +st "D0_SROUT" +blo "22000,104800" +tm "WireNameMgr" +) +) +on &105 +) +*241 (Wire +uid 1873,0 +shape (OrthoPolyLine +uid 1874,0 +va (VaSet +vasetType 3 +) +xt "21000,106000,51250,106000" +pts [ +"21000,106000" +"51250,106000" +] +) +start &102 +end &33 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1877,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1878,0 +va (VaSet +isHidden 1 +) +xt "22000,105000,26600,106000" +st "D1_SROUT" +blo "22000,105800" +tm "WireNameMgr" +) +) +on &106 +) +*242 (Wire +uid 1881,0 +shape (OrthoPolyLine +uid 1882,0 +va (VaSet +vasetType 3 +) +xt "21000,107000,51250,107000" +pts [ +"21000,107000" +"51250,107000" +] +) +start &103 +end &34 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1885,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1886,0 +va (VaSet +isHidden 1 +) +xt "22000,106000,26600,107000" +st "D2_SROUT" +blo "22000,106800" +tm "WireNameMgr" +) +) +on &107 +) +*243 (Wire +uid 1889,0 +shape (OrthoPolyLine +uid 1890,0 +va (VaSet +vasetType 3 +) +xt "21000,108000,51250,108000" +pts [ +"21000,108000" +"51250,108000" +] +) +start &104 +end &35 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1893,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1894,0 +va (VaSet +isHidden 1 +) +xt "22000,107000,26600,108000" +st "D3_SROUT" +blo "22000,107800" +tm "WireNameMgr" +) +) +on &108 +) +*244 (Wire +uid 2409,0 +shape (OrthoPolyLine +uid 2410,0 +va (VaSet +vasetType 3 +) +xt "21000,111000,51250,111000" +pts [ +"51250,111000" +"21000,111000" +] +) +start &36 +end &64 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2413,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2414,0 +va (VaSet +isHidden 1 +) +xt "22000,110000,26200,111000" +st "RSRLOAD" +blo "22000,110800" +tm "WireNameMgr" +) +) +on &63 +) +*245 (Wire +uid 2423,0 +shape (OrthoPolyLine +uid 2424,0 +va (VaSet +vasetType 3 +) +xt "32000,113000,51250,113000" +pts [ +"51250,113000" +"32000,113000" +] +) +start &37 +end &93 +sat 32 +eat 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2427,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2428,0 +va (VaSet +isHidden 1 +) +xt "66250,109000,69250,110000" +st "SRCLK" +blo "66250,109800" +tm "WireNameMgr" +) +) +on &65 +) +*246 (Wire +uid 3009,0 +shape (OrthoPolyLine +uid 3010,0 +va (VaSet +vasetType 3 +) +xt "80750,98000,111000,98000" +pts [ +"80750,98000" +"111000,98000" +] +) +start &39 +end &126 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3011,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3012,0 +va (VaSet +isHidden 1 +) +xt "82000,97000,84800,98000" +st "S_CLK" +blo "82000,97800" +tm "WireNameMgr" +) +) +on &127 +) +*247 (Wire +uid 3015,0 +shape (OrthoPolyLine +uid 3016,0 +va (VaSet +vasetType 3 +) +xt "80750,99000,111000,99000" +pts [ +"80750,99000" +"111000,99000" +] +) +start &41 +end &135 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3017,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3018,0 +va (VaSet +isHidden 1 +) +xt "82750,98000,85150,99000" +st "MISO" +blo "82750,98800" +tm "WireNameMgr" +) +) +on &138 +) +*248 (Wire +uid 3021,0 +shape (OrthoPolyLine +uid 3022,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "80750,89000,100000,89000" +pts [ +"80750,89000" +"100000,89000" +] +) +start &40 +end &114 +sat 32 +eat 1 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 3023,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3024,0 +va (VaSet +) +xt "92000,88000,98500,89000" +st "sensor_cs : (3:0)" +blo "92000,88800" +tm "WireNameMgr" +) +) +on &66 +) +*249 (Wire +uid 3027,0 +shape (OrthoPolyLine +uid 3028,0 +va (VaSet +vasetType 3 +) +xt "94000,87000,111000,87000" +pts [ +"94000,87000" +"111000,87000" +] +) +start &211 +end &113 +ss 0 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3031,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3032,0 +va (VaSet +isHidden 1 +) +xt "95000,86000,98600,87000" +st "DAC_CS" +blo "95000,86800" +tm "WireNameMgr" +) +) +on &67 +) +*250 (Wire +uid 3218,0 +shape (OrthoPolyLine +uid 3219,0 +va (VaSet +vasetType 3 +) +xt "11000,77000,13000,77000" +pts [ +"11000,77000" +"13000,77000" +] +) +start &47 +end &176 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3220,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3221,0 +va (VaSet +isHidden 1 +) +xt "22000,76000,24100,77000" +st "TRG" +blo "22000,76800" +tm "WireNameMgr" +) +) +on &70 +) +*251 (Wire +uid 3260,0 +shape (OrthoPolyLine +uid 3261,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "21000,70000,24000,70000" +pts [ +"21000,70000" +"24000,70000" +] +) +start &68 +end &71 +sat 32 +eat 2 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3264,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3265,0 +va (VaSet +isHidden 1 +) +xt "23000,69000,25800,70000" +st "A_CLK" +blo "23000,69800" +tm "WireNameMgr" +) +) +on &75 +) +*252 (Wire +uid 3270,0 +shape (OrthoPolyLine +uid 3271,0 +va (VaSet +vasetType 3 +) +xt "32000,70000,51250,70000" +pts [ +"51250,70000" +"32000,70000" +] +) +start &25 +end &71 +sat 32 +eat 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 3274,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3275,0 +va (VaSet +) +xt "46000,69000,50500,70000" +st "CLK_25_PS" +blo "46000,69800" +tm "WireNameMgr" +) +) +on &76 +) +*253 (Wire +uid 3318,0 +shape (OrthoPolyLine +uid 3319,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "21000,95000,24000,95000" +pts [ +"21000,95000" +"24000,95000" +] +) +start &85 +end &81 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3322,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3323,0 +va (VaSet +isHidden 1 +) +xt "23000,94000,25300,95000" +st "A0_D" +blo "23000,94800" +tm "WireNameMgr" +) +) +on &89 +) +*254 (Wire +uid 3352,0 +shape (OrthoPolyLine +uid 3353,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "21000,96000,24000,96000" +pts [ +"21000,96000" +"24000,96000" +] +) +start &86 +end &81 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3356,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3357,0 +va (VaSet +isHidden 1 +) +xt "23000,95000,25300,96000" +st "A1_D" +blo "23000,95800" +tm "WireNameMgr" +) +) +on &90 +) +*255 (Wire +uid 3360,0 +shape (OrthoPolyLine +uid 3361,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "21000,97000,24000,97000" +pts [ +"21000,97000" +"24000,97000" +] +) +start &87 +end &81 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3364,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3365,0 +va (VaSet +isHidden 1 +) +xt "23000,96000,25300,97000" +st "A2_D" +blo "23000,96800" +tm "WireNameMgr" +) +) +on &91 +) +*256 (Wire +uid 3368,0 +shape (OrthoPolyLine +uid 3369,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "21000,98000,24000,98000" +pts [ +"21000,98000" +"24000,98000" +] +) +start &88 +end &81 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3372,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3373,0 +va (VaSet +isHidden 1 +) +xt "23000,97000,25300,98000" +st "A3_D" +blo "23000,97800" +tm "WireNameMgr" +) +) +on &92 +) +*257 (Wire +uid 3430,0 +shape (OrthoPolyLine +uid 3431,0 +va (VaSet +vasetType 3 +) +xt "21000,113000,24000,113000" +pts [ +"21000,113000" +"24000,113000" +] +) +start &161 +end &93 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3434,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3435,0 +va (VaSet +isHidden 1 +) +xt "23000,112000,27400,113000" +st "D0_SRCLK" +blo "23000,112800" +tm "WireNameMgr" +) +) +on &97 +) +*258 (Wire +uid 3438,0 +shape (OrthoPolyLine +uid 3439,0 +va (VaSet +vasetType 3 +) +xt "21000,114000,24000,114000" +pts [ +"21000,114000" +"24000,114000" +] +) +start &162 +end &93 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3442,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3443,0 +va (VaSet +isHidden 1 +) +xt "23000,113000,27400,114000" +st "D1_SRCLK" +blo "23000,113800" +tm "WireNameMgr" +) +) +on &98 +) +*259 (Wire +uid 3446,0 +shape (OrthoPolyLine +uid 3447,0 +va (VaSet +vasetType 3 +) +xt "21000,115000,24000,115000" +pts [ +"21000,115000" +"24000,115000" +] +) +start &163 +end &93 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3450,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3451,0 +va (VaSet +isHidden 1 +) +xt "23000,114000,27400,115000" +st "D2_SRCLK" +blo "23000,114800" +tm "WireNameMgr" +) +) +on &99 +) +*260 (Wire +uid 3454,0 +shape (OrthoPolyLine +uid 3455,0 +va (VaSet +vasetType 3 +) +xt "21000,116000,24000,116000" +pts [ +"21000,116000" +"24000,116000" +] +) +start &164 +end &93 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3458,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3459,0 +va (VaSet +isHidden 1 +) +xt "23000,115000,27400,116000" +st "D3_SRCLK" +blo "23000,115800" +tm "WireNameMgr" +) +) +on &100 +) +*261 (Wire +uid 3574,0 +shape (OrthoPolyLine +uid 3575,0 +va (VaSet +vasetType 3 +) +xt "108000,89000,111000,89000" +pts [ +"111000,89000" +"108000,89000" +] +) +start &118 +end &114 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3578,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3579,0 +va (VaSet +isHidden 1 +) +xt "108000,88000,110800,89000" +st "T0_CS" +blo "108000,88800" +tm "WireNameMgr" +) +) +on &122 +) +*262 (Wire +uid 3582,0 +shape (OrthoPolyLine +uid 3583,0 +va (VaSet +vasetType 3 +) +xt "108000,90000,111000,90000" +pts [ +"111000,90000" +"108000,90000" +] +) +start &119 +end &114 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3586,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3587,0 +va (VaSet +isHidden 1 +) +xt "108000,89000,110800,90000" +st "T1_CS" +blo "108000,89800" +tm "WireNameMgr" +) +) +on &123 +) +*263 (Wire +uid 3590,0 +shape (OrthoPolyLine +uid 3591,0 +va (VaSet +vasetType 3 +) +xt "108000,91000,111000,91000" +pts [ +"111000,91000" +"108000,91000" +] +) +start &120 +end &114 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3594,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3595,0 +va (VaSet +isHidden 1 +) +xt "108000,90000,110800,91000" +st "T2_CS" +blo "108000,90800" +tm "WireNameMgr" +) +) +on &124 +) +*264 (Wire +uid 3598,0 +shape (OrthoPolyLine +uid 3599,0 +va (VaSet +vasetType 3 +) +xt "108000,92000,111000,92000" +pts [ +"111000,92000" +"108000,92000" +] +) +start &121 +end &114 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3602,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3603,0 +va (VaSet +isHidden 1 +) +xt "108000,91000,110800,92000" +st "T3_CS" +blo "108000,91800" +tm "WireNameMgr" +) +) +on &125 +) +*265 (Wire +uid 3682,0 +shape (OrthoPolyLine +uid 3683,0 +va (VaSet +vasetType 3 +) +xt "80750,100000,111000,100000" +pts [ +"80750,100000" +"111000,100000" +] +) +start &42 +end &137 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3686,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3687,0 +va (VaSet +isHidden 1 +) +xt "82000,99000,84400,100000" +st "MOSI" +blo "82000,99800" +tm "WireNameMgr" +) +) +on &136 +) +*266 (Wire +uid 3778,0 +shape (OrthoPolyLine +uid 3779,0 +va (VaSet +vasetType 3 +) +xt "108000,103000,111000,103000" +pts [ +"111000,103000" +"108000,103000" +] +) +start &143 +end &139 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3782,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3783,0 +va (VaSet +isHidden 1 +) +xt "108000,102000,111000,103000" +st "TRG_V" +blo "108000,102800" +tm "WireNameMgr" +) +) +on &152 +) +*267 (Wire +uid 3786,0 +shape (OrthoPolyLine +uid 3787,0 +va (VaSet +vasetType 3 +) +xt "108000,104000,111000,104000" +pts [ +"111000,104000" +"108000,104000" +] +) +start &144 +end &139 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3790,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3791,0 +va (VaSet +isHidden 1 +) +xt "108000,103000,113600,104000" +st "RS485_C_RE" +blo "108000,103800" +tm "WireNameMgr" +) +) +on &153 +) +*268 (Wire +uid 3794,0 +shape (OrthoPolyLine +uid 3795,0 +va (VaSet +vasetType 3 +) +xt "108000,105000,111000,105000" +pts [ +"111000,105000" +"108000,105000" +] +) +start &145 +end &139 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3798,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3799,0 +va (VaSet +isHidden 1 +) +xt "108000,104000,113600,105000" +st "RS485_C_DE" +blo "108000,104800" +tm "WireNameMgr" +) +) +on &154 +) +*269 (Wire +uid 3802,0 +shape (OrthoPolyLine +uid 3803,0 +va (VaSet +vasetType 3 +) +xt "108000,106000,111000,106000" +pts [ +"111000,106000" +"108000,106000" +] +) +start &146 +end &139 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3806,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3807,0 +va (VaSet +isHidden 1 +) +xt "108000,105000,113500,106000" +st "RS485_E_RE" +blo "108000,105800" +tm "WireNameMgr" +) +) +on &155 +) +*270 (Wire +uid 3810,0 +shape (OrthoPolyLine +uid 3811,0 +va (VaSet +vasetType 3 +) +xt "108000,107000,111000,107000" +pts [ +"111000,107000" +"108000,107000" +] +) +start &147 +end &139 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3814,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3815,0 +va (VaSet +isHidden 1 +) +xt "108000,106000,113500,107000" +st "RS485_E_DE" +blo "108000,106800" +tm "WireNameMgr" +) +) +on &156 +) +*271 (Wire +uid 3826,0 +shape (OrthoPolyLine +uid 3827,0 +va (VaSet +vasetType 3 +) +xt "108000,109000,111000,109000" +pts [ +"111000,109000" +"108000,109000" +] +) +start &149 +end &139 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3830,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3831,0 +va (VaSet +isHidden 1 +) +xt "108000,108000,110300,109000" +st "SRIN" +blo "108000,108800" +tm "WireNameMgr" +) +) +on &158 +) +*272 (Wire +uid 3834,0 +shape (OrthoPolyLine +uid 3835,0 +va (VaSet +vasetType 3 +) +xt "108000,110000,111000,110000" +pts [ +"111000,110000" +"108000,110000" +] +) +start &150 +end &139 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3838,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3839,0 +va (VaSet +isHidden 1 +) +xt "108000,109000,110900,110000" +st "EE_CS" +blo "108000,109800" +tm "WireNameMgr" +) +) +on &159 +) +*273 (Wire +uid 3842,0 +shape (OrthoPolyLine +uid 3843,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "108000,111000,111000,111000" +pts [ +"111000,111000" +"108000,111000" +] +) +start &151 +end &139 +sat 32 +eat 2 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3846,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3847,0 +va (VaSet +isHidden 1 +) +xt "108000,110000,109900,111000" +st "LED" +blo "108000,110800" +tm "WireNameMgr" +) +) +on &160 +) +*274 (Wire +uid 4942,0 +shape (OrthoPolyLine +uid 4943,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "80750,120000,111000,120000" +pts [ +"80750,120000" +"111000,120000" +] +) +start &14 +end &165 sat 32 eat 32 @@ -7596,35 +8547,71 @@ si 0 tg (WTG -uid 1837,0 +uid 4948,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text -uid 1838,0 +uid 4949,0 va (VaSet isHidden 1 ) -xt "22000,108000,23900,109000" -st "D_A" -blo "22000,108800" -tm "WireNameMgr" -) -) -on &111 -) -*255 (Wire -uid 1841,0 +xt "82750,117000,84650,118000" +st "D_T" +blo "82750,117800" +tm "WireNameMgr" +) +) +on &166 +) +*275 (Wire +uid 6130,0 shape (OrthoPolyLine -uid 1842,0 +uid 6131,0 va (VaSet vasetType 3 ) -xt "21000,110000,51250,110000" -pts [ -"51250,110000" -"21000,110000" -] -) -start &31 -end &112 +xt "19000,78000,51250,78000" +pts [ +"19000,78000" +"51250,78000" +] +) +start &173 +end &15 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 6136,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6137,0 +va (VaSet +) +xt "21000,77000,24700,78000" +st "TRG_OR" +blo "21000,77800" +tm "WireNameMgr" +) +) +on &169 +) +*276 (Wire +uid 6306,0 +shape (OrthoPolyLine +uid 6307,0 +va (VaSet +vasetType 3 +) +xt "11000,79000,13000,79000" +pts [ +"11000,79000" +"13000,79000" +] +) +start &167 +end &171 sat 32 eat 32 @@ -7634,35 +8621,35 @@ si 0 tg (WTG -uid 1845,0 +uid 6312,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text -uid 1846,0 +uid 6313,0 va (VaSet isHidden 1 ) -xt "22000,109000,25500,110000" -st "DWRITE" -blo "22000,109800" -tm "WireNameMgr" -) -) -on &113 -) -*256 (Wire -uid 1865,0 +xt "13000,78000,17500,79000" +st "TEST_TRG" +blo "13000,78800" +tm "WireNameMgr" +) +) +on &168 +) +*277 (Wire +uid 6431,0 shape (OrthoPolyLine -uid 1866,0 +uid 6432,0 va (VaSet vasetType 3 ) -xt "21000,105000,51250,105000" -pts [ -"21000,105000" -"51250,105000" -] -) -start &102 -end &32 +xt "80750,121000,111000,121000" +pts [ +"80750,121000" +"111000,121000" +] +) +start &43 +end &148 sat 32 eat 32 @@ -7672,342 +8659,36 @@ si 0 tg (WTG -uid 1869,0 +uid 6435,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text -uid 1870,0 +uid 6436,0 va (VaSet isHidden 1 ) -xt "22000,104000,26600,105000" -st "D0_SROUT" -blo "22000,104800" -tm "WireNameMgr" -) -) -on &106 -) -*257 (Wire -uid 1873,0 +xt "92000,120000,96000,121000" +st "DENABLE" +blo "92000,120800" +tm "WireNameMgr" +) +) +on &157 +) +*278 (Wire +uid 6787,0 shape (OrthoPolyLine -uid 1874,0 -va (VaSet -vasetType 3 -) -xt "21000,106000,51250,106000" -pts [ -"21000,106000" -"51250,106000" -] -) -start &103 -end &33 -sat 32 -eat 32 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 1877,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 1878,0 -va (VaSet -isHidden 1 -) -xt "22000,105000,26600,106000" -st "D1_SROUT" -blo "22000,105800" -tm "WireNameMgr" -) -) -on &107 -) -*258 (Wire -uid 1881,0 -shape (OrthoPolyLine -uid 1882,0 -va (VaSet -vasetType 3 -) -xt "21000,107000,51250,107000" -pts [ -"21000,107000" -"51250,107000" -] -) -start &104 -end &34 -sat 32 -eat 32 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 1885,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 1886,0 -va (VaSet -isHidden 1 -) -xt "22000,106000,26600,107000" -st "D2_SROUT" -blo "22000,106800" -tm "WireNameMgr" -) -) -on &108 -) -*259 (Wire -uid 1889,0 -shape (OrthoPolyLine -uid 1890,0 -va (VaSet -vasetType 3 -) -xt "21000,108000,51250,108000" -pts [ -"21000,108000" -"51250,108000" -] -) -start &105 -end &35 -sat 32 -eat 32 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 1893,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 1894,0 -va (VaSet -isHidden 1 -) -xt "22000,107000,26600,108000" -st "D3_SROUT" -blo "22000,107800" -tm "WireNameMgr" -) -) -on &109 -) -*260 (Wire -uid 2269,0 -shape (OrthoPolyLine -uid 2270,0 -va (VaSet -vasetType 3 -) -xt "-15000,69000,51250,88000" -pts [ -"51250,69000" -"-15000,69000" -"-15000,88000" -"-11750,88000" -] -) -start &26 -end &172 -sat 32 -eat 32 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 2273,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 2274,0 -va (VaSet -isHidden 1 -) -xt "50250,68000,53350,69000" -st "CLK_50" -blo "50250,68800" -tm "WireNameMgr" -) -) -on &63 -) -*261 (Wire -uid 2409,0 -shape (OrthoPolyLine -uid 2410,0 -va (VaSet -vasetType 3 -) -xt "21000,111000,51250,111000" -pts [ -"51250,111000" -"21000,111000" -] -) -start &36 -end &65 -sat 32 -eat 32 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 2413,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 2414,0 -va (VaSet -isHidden 1 -) -xt "22000,110000,26200,111000" -st "RSRLOAD" -blo "22000,110800" -tm "WireNameMgr" -) -) -on &64 -) -*262 (Wire -uid 2423,0 -shape (OrthoPolyLine -uid 2424,0 -va (VaSet -vasetType 3 -) -xt "32000,113000,51250,113000" -pts [ -"51250,113000" -"32000,113000" -] -) -start &37 -end &94 -sat 32 -eat 1 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 2427,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 2428,0 -va (VaSet -isHidden 1 -) -xt "66250,109000,69250,110000" -st "SRCLK" -blo "66250,109800" -tm "WireNameMgr" -) -) -on &66 -) -*263 (Wire -uid 3009,0 -shape (OrthoPolyLine -uid 3010,0 -va (VaSet -vasetType 3 -) -xt "80750,98000,111000,98000" -pts [ -"80750,98000" -"111000,98000" -] -) -start &39 -end &127 -sat 32 -eat 32 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3011,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3012,0 -va (VaSet -isHidden 1 -) -xt "82000,97000,84800,98000" -st "S_CLK" -blo "82000,97800" -tm "WireNameMgr" -) -) -on &128 -) -*264 (Wire -uid 3015,0 -shape (OrthoPolyLine -uid 3016,0 -va (VaSet -vasetType 3 -) -xt "80750,99000,111000,99000" -pts [ -"80750,99000" -"111000,99000" -] -) -start &41 -end &136 -sat 32 -eat 32 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3017,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3018,0 -va (VaSet -isHidden 1 -) -xt "82750,98000,85150,99000" -st "MISO" -blo "82750,98800" -tm "WireNameMgr" -) -) -on &139 -) -*265 (Wire -uid 3021,0 -shape (OrthoPolyLine -uid 3022,0 +uid 6788,0 va (VaSet vasetType 3 lineWidth 2 ) -xt "80750,89000,100000,89000" -pts [ -"80750,89000" -"100000,89000" -] -) -start &40 -end &115 +xt "93000,132000,99000,132000" +pts [ +"93000,132000" +"99000,132000" +] +) +start &193 +end &197 sat 32 eat 1 @@ -8017,1110 +8698,113 @@ si 0 tg (WTG -uid 3023,0 +uid 6791,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text -uid 3024,0 -va (VaSet -) -xt "92000,88000,98500,89000" -st "sensor_cs : (3:0)" -blo "92000,88800" -tm "WireNameMgr" -) -) -on &67 -) -*266 (Wire -uid 3027,0 +uid 6792,0 +va (VaSet +isHidden 1 +) +xt "95000,131000,101800,132000" +st "D_PLLLCK : (3:0)" +blo "95000,131800" +tm "WireNameMgr" +) +) +on &194 +) +*279 (Wire +uid 6880,0 shape (OrthoPolyLine -uid 3028,0 -va (VaSet -vasetType 3 -) -xt "94000,87000,111000,87000" -pts [ -"94000,87000" -"111000,87000" -] -) -start &231 -end &114 -ss 0 -sat 32 -eat 32 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3031,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3032,0 -va (VaSet -isHidden 1 -) -xt "95000,86000,98600,87000" -st "DAC_CS" -blo "95000,86800" -tm "WireNameMgr" -) -) -on &68 -) -*267 (Wire -uid 3218,0 -shape (OrthoPolyLine -uid 3219,0 -va (VaSet -vasetType 3 -) -xt "11000,77000,13000,77000" -pts [ -"11000,77000" -"13000,77000" -] -) -start &47 -end &196 -sat 32 -eat 32 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3220,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3221,0 -va (VaSet -isHidden 1 -) -xt "22000,76000,24100,77000" -st "TRG" -blo "22000,76800" -tm "WireNameMgr" -) -) -on &71 -) -*268 (Wire -uid 3260,0 -shape (OrthoPolyLine -uid 3261,0 +uid 6881,0 va (VaSet vasetType 3 lineWidth 2 ) -xt "21000,70000,24000,70000" -pts [ -"21000,70000" -"24000,70000" -] -) -start &69 -end &72 -sat 32 -eat 2 +xt "102000,132000,109000,132000" +pts [ +"102000,132000" +"109000,132000" +] +) +start &197 +end &195 +sat 2 +eat 32 sty 1 -stc 0 st 0 sf 1 si 0 tg (WTG -uid 3264,0 +uid 6884,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text -uid 3265,0 +uid 6885,0 va (VaSet isHidden 1 ) -xt "23000,69000,25800,70000" -st "A_CLK" -blo "23000,69800" -tm "WireNameMgr" -) -) -on &76 -) -*269 (Wire -uid 3270,0 +xt "104000,131000,108900,132000" +st "D_T2 : (3:0)" +blo "104000,131800" +tm "WireNameMgr" +) +) +on &196 +) +*280 (Wire +uid 7144,0 shape (OrthoPolyLine -uid 3271,0 -va (VaSet -vasetType 3 -) -xt "32000,70000,51250,70000" -pts [ -"51250,70000" -"32000,70000" -] -) -start &25 -end &72 -sat 32 -eat 1 -st 0 -sf 1 -si 0 -tg (WTG -uid 3274,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3275,0 -va (VaSet -) -xt "46000,69000,50500,70000" -st "CLK_25_PS" -blo "46000,69800" -tm "WireNameMgr" -) -) -on &77 -) -*270 (Wire -uid 3318,0 -shape (OrthoPolyLine -uid 3319,0 +uid 7145,0 va (VaSet vasetType 3 lineWidth 2 ) -xt "21000,95000,24000,95000" -pts [ -"21000,95000" -"24000,95000" -] -) -start &86 -end &82 -sat 32 -eat 1 -sty 1 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3322,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3323,0 -va (VaSet -isHidden 1 -) -xt "23000,94000,25300,95000" -st "A0_D" -blo "23000,94800" -tm "WireNameMgr" -) -) -on &90 -) -*271 (Wire -uid 3352,0 -shape (OrthoPolyLine -uid 3353,0 -va (VaSet -vasetType 3 -lineWidth 2 -) -xt "21000,96000,24000,96000" -pts [ -"21000,96000" -"24000,96000" -] -) -start &87 -end &82 -sat 32 -eat 1 -sty 1 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3356,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3357,0 -va (VaSet -isHidden 1 -) -xt "23000,95000,25300,96000" -st "A1_D" -blo "23000,95800" -tm "WireNameMgr" -) -) -on &91 -) -*272 (Wire -uid 3360,0 -shape (OrthoPolyLine -uid 3361,0 -va (VaSet -vasetType 3 -lineWidth 2 -) -xt "21000,97000,24000,97000" -pts [ -"21000,97000" -"24000,97000" -] -) -start &88 -end &82 -sat 32 -eat 1 -sty 1 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3364,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3365,0 -va (VaSet -isHidden 1 -) -xt "23000,96000,25300,97000" -st "A2_D" -blo "23000,96800" -tm "WireNameMgr" -) -) -on &92 -) -*273 (Wire -uid 3368,0 -shape (OrthoPolyLine -uid 3369,0 -va (VaSet -vasetType 3 -lineWidth 2 -) -xt "21000,98000,24000,98000" -pts [ -"21000,98000" -"24000,98000" -] -) -start &89 -end &82 -sat 32 -eat 1 -sty 1 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3372,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3373,0 -va (VaSet -isHidden 1 -) -xt "23000,97000,25300,98000" -st "A3_D" -blo "23000,97800" -tm "WireNameMgr" -) -) -on &93 -) -*274 (Wire -uid 3430,0 -shape (OrthoPolyLine -uid 3431,0 -va (VaSet -vasetType 3 -) -xt "21000,113000,24000,113000" -pts [ -"21000,113000" -"24000,113000" -] -) -start &162 -end &94 -sat 32 -eat 2 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3434,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3435,0 -va (VaSet -isHidden 1 -) -xt "23000,112000,27400,113000" -st "D0_SRCLK" -blo "23000,112800" -tm "WireNameMgr" -) -) -on &98 -) -*275 (Wire -uid 3438,0 -shape (OrthoPolyLine -uid 3439,0 -va (VaSet -vasetType 3 -) -xt "21000,114000,24000,114000" -pts [ -"21000,114000" -"24000,114000" -] -) -start &163 -end &94 -sat 32 -eat 2 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3442,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3443,0 -va (VaSet -isHidden 1 -) -xt "23000,113000,27400,114000" -st "D1_SRCLK" -blo "23000,113800" -tm "WireNameMgr" -) -) -on &99 -) -*276 (Wire -uid 3446,0 -shape (OrthoPolyLine -uid 3447,0 -va (VaSet -vasetType 3 -) -xt "21000,115000,24000,115000" -pts [ -"21000,115000" -"24000,115000" -] -) -start &164 -end &94 -sat 32 -eat 2 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3450,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3451,0 -va (VaSet -isHidden 1 -) -xt "23000,114000,27400,115000" -st "D2_SRCLK" -blo "23000,114800" -tm "WireNameMgr" -) -) -on &100 -) -*277 (Wire -uid 3454,0 -shape (OrthoPolyLine -uid 3455,0 -va (VaSet -vasetType 3 -) -xt "21000,116000,24000,116000" -pts [ -"21000,116000" -"24000,116000" -] -) -start &165 -end &94 -sat 32 -eat 2 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3458,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3459,0 -va (VaSet -isHidden 1 -) -xt "23000,115000,27400,116000" -st "D3_SRCLK" -blo "23000,115800" -tm "WireNameMgr" -) -) -on &101 -) -*278 (Wire -uid 3574,0 -shape (OrthoPolyLine -uid 3575,0 -va (VaSet -vasetType 3 -) -xt "108000,89000,111000,89000" -pts [ -"111000,89000" -"108000,89000" -] -) -start &119 -end &115 -sat 32 -eat 2 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3578,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3579,0 -va (VaSet -isHidden 1 -) -xt "108000,88000,110800,89000" -st "T0_CS" -blo "108000,88800" -tm "WireNameMgr" -) -) -on &123 -) -*279 (Wire -uid 3582,0 -shape (OrthoPolyLine -uid 3583,0 -va (VaSet -vasetType 3 -) -xt "108000,90000,111000,90000" -pts [ -"111000,90000" -"108000,90000" -] -) -start &120 -end &115 -sat 32 -eat 2 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3586,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3587,0 -va (VaSet -isHidden 1 -) -xt "108000,89000,110800,90000" -st "T1_CS" -blo "108000,89800" -tm "WireNameMgr" -) -) -on &124 -) -*280 (Wire -uid 3590,0 -shape (OrthoPolyLine -uid 3591,0 -va (VaSet -vasetType 3 -) -xt "108000,91000,111000,91000" -pts [ -"111000,91000" -"108000,91000" -] -) -start &121 -end &115 -sat 32 -eat 2 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3594,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3595,0 -va (VaSet -isHidden 1 -) -xt "108000,90000,110800,91000" -st "T2_CS" -blo "108000,90800" -tm "WireNameMgr" -) -) -on &125 -) -*281 (Wire -uid 3598,0 -shape (OrthoPolyLine -uid 3599,0 -va (VaSet -vasetType 3 -) -xt "108000,92000,111000,92000" -pts [ -"111000,92000" -"108000,92000" -] -) -start &122 -end &115 -sat 32 -eat 2 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3602,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3603,0 -va (VaSet -isHidden 1 -) -xt "108000,91000,110800,92000" -st "T3_CS" -blo "108000,91800" -tm "WireNameMgr" -) -) -on &126 -) -*282 (Wire -uid 3682,0 -shape (OrthoPolyLine -uid 3683,0 -va (VaSet -vasetType 3 -) -xt "80750,100000,111000,100000" -pts [ -"80750,100000" -"111000,100000" -] -) -start &42 -end &138 -sat 32 -eat 32 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3686,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3687,0 -va (VaSet -isHidden 1 -) -xt "82000,99000,84400,100000" -st "MOSI" -blo "82000,99800" -tm "WireNameMgr" -) -) -on &137 -) -*283 (Wire -uid 3778,0 -shape (OrthoPolyLine -uid 3779,0 -va (VaSet -vasetType 3 -) -xt "108000,103000,111000,103000" -pts [ -"111000,103000" -"108000,103000" -] -) -start &144 -end &140 -sat 32 -eat 2 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3782,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3783,0 -va (VaSet -isHidden 1 -) -xt "108000,102000,111000,103000" -st "TRG_V" -blo "108000,102800" -tm "WireNameMgr" -) -) -on &153 -) -*284 (Wire -uid 3786,0 -shape (OrthoPolyLine -uid 3787,0 -va (VaSet -vasetType 3 -) -xt "108000,104000,111000,104000" -pts [ -"111000,104000" -"108000,104000" -] -) -start &145 -end &140 -sat 32 -eat 2 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3790,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3791,0 -va (VaSet -isHidden 1 -) -xt "108000,103000,113600,104000" -st "RS485_C_RE" -blo "108000,103800" -tm "WireNameMgr" -) -) -on &154 -) -*285 (Wire -uid 3794,0 -shape (OrthoPolyLine -uid 3795,0 -va (VaSet -vasetType 3 -) -xt "108000,105000,111000,105000" -pts [ -"111000,105000" -"108000,105000" -] -) -start &146 -end &140 -sat 32 -eat 2 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3798,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3799,0 -va (VaSet -isHidden 1 -) -xt "108000,104000,113600,105000" -st "RS485_C_DE" -blo "108000,104800" -tm "WireNameMgr" -) -) -on &155 -) -*286 (Wire -uid 3802,0 -shape (OrthoPolyLine -uid 3803,0 -va (VaSet -vasetType 3 -) -xt "108000,106000,111000,106000" -pts [ -"111000,106000" -"108000,106000" -] -) -start &147 -end &140 -sat 32 -eat 2 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3806,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3807,0 -va (VaSet -isHidden 1 -) -xt "108000,105000,113500,106000" -st "RS485_E_RE" -blo "108000,105800" -tm "WireNameMgr" -) -) -on &156 -) -*287 (Wire -uid 3810,0 -shape (OrthoPolyLine -uid 3811,0 -va (VaSet -vasetType 3 -) -xt "108000,107000,111000,107000" -pts [ -"111000,107000" -"108000,107000" -] -) -start &148 -end &140 -sat 32 -eat 2 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3814,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3815,0 -va (VaSet -isHidden 1 -) -xt "108000,106000,113500,107000" -st "RS485_E_DE" -blo "108000,106800" -tm "WireNameMgr" -) -) -on &157 -) -*288 (Wire -uid 3826,0 -shape (OrthoPolyLine -uid 3827,0 -va (VaSet -vasetType 3 -) -xt "108000,109000,111000,109000" -pts [ -"111000,109000" -"108000,109000" -] -) -start &150 -end &140 -sat 32 -eat 2 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3830,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3831,0 -va (VaSet -isHidden 1 -) -xt "108000,108000,110300,109000" -st "SRIN" -blo "108000,108800" -tm "WireNameMgr" -) -) -on &159 -) -*289 (Wire -uid 3834,0 -shape (OrthoPolyLine -uid 3835,0 -va (VaSet -vasetType 3 -) -xt "108000,110000,111000,110000" -pts [ -"111000,110000" -"108000,110000" -] -) -start &151 -end &140 -sat 32 -eat 2 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3838,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3839,0 -va (VaSet -isHidden 1 -) -xt "108000,109000,110900,110000" -st "EE_CS" -blo "108000,109800" -tm "WireNameMgr" -) -) -on &160 -) -*290 (Wire -uid 3842,0 -shape (OrthoPolyLine -uid 3843,0 -va (VaSet -vasetType 3 -lineWidth 2 -) -xt "108000,111000,111000,111000" -pts [ -"111000,111000" -"108000,111000" -] -) -start &152 -end &140 -sat 32 -eat 2 -sty 1 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 3846,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 3847,0 -va (VaSet -isHidden 1 -) -xt "108000,110000,109900,111000" -st "LED" -blo "108000,110800" -tm "WireNameMgr" -) -) -on &161 -) -*291 (Wire -uid 4942,0 -shape (OrthoPolyLine -uid 4943,0 -va (VaSet -vasetType 3 -lineWidth 2 -) -xt "80750,120000,111000,120000" -pts [ -"80750,120000" -"111000,120000" -] -) -start &14 -end &166 -sat 32 +xt "39000,132000,44000,132000" +pts [ +"39000,132000" +"44000,132000" +] +) +start &201 +end &205 +sat 2 eat 32 sty 1 -stc 0 st 0 sf 1 si 0 tg (WTG -uid 4948,0 +uid 7148,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text -uid 4949,0 +uid 7149,0 va (VaSet isHidden 1 ) -xt "82750,117000,84650,118000" -st "D_T" -blo "82750,117800" -tm "WireNameMgr" -) -) -on &167 -) -*292 (Wire -uid 6130,0 +xt "41000,131000,45800,132000" +st "A1_T : (7:0)" +blo "41000,131800" +tm "WireNameMgr" +) +) +on &206 +) +*281 (Wire +uid 7477,0 shape (OrthoPolyLine -uid 6131,0 +uid 7478,0 va (VaSet vasetType 3 ) -xt "19000,78000,51250,78000" -pts [ -"19000,78000" -"51250,78000" -] -) -start &193 -end &15 -sat 32 -eat 32 -st 0 -sf 1 -si 0 -tg (WTG -uid 6136,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 6137,0 -va (VaSet -) -xt "21000,77000,24700,78000" -st "TRG_OR" -blo "21000,77800" -tm "WireNameMgr" -) -) -on &170 -) -*293 (Wire -uid 6288,0 -shape (OrthoPolyLine -uid 6289,0 -va (VaSet -vasetType 3 -) -xt "1750,79000,13000,89000" -pts [ -"1750,89000" -"9000,89000" -"9000,86000" -"9000,79000" -"13000,79000" -] -) -start &174 -end &191 -sat 32 -eat 32 -st 0 -sf 1 -si 0 -tg (WTG -uid 6294,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 6295,0 -va (VaSet -) -xt "4000,88000,8600,89000" -st "trigger_out" -blo "4000,88800" -tm "WireNameMgr" -) -) -on &178 -) -*294 (Wire -uid 6306,0 -shape (OrthoPolyLine -uid 6307,0 -va (VaSet -vasetType 3 -) -xt "-28000,89000,-22000,89000" -pts [ -"-28000,89000" -"-22000,89000" -] -) -start &168 -end &181 +xt "80750,87000,91000,87000" +pts [ +"80750,87000" +"91000,87000" +] +) +start &38 +end &209 es 0 sat 32 @@ -9130,109 +8814,37 @@ si 0 tg (WTG -uid 6312,0 +uid 7483,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text -uid 6313,0 -va (VaSet -) -xt "-26000,88000,-21500,89000" -st "TEST_TRG" -blo "-26000,88800" -tm "WireNameMgr" -) -) -on &169 -) -*295 (Wire -uid 6328,0 +uid 7484,0 +va (VaSet +) +xt "83000,86000,85700,87000" +st "dummy" +blo "83000,86800" +tm "WireNameMgr" +) +) +on &207 +) +*282 (Wire +uid 8853,0 shape (OrthoPolyLine -uid 6329,0 -va (VaSet -vasetType 3 -) -xt "-17000,89000,-11750,89000" -pts [ -"-17000,89000" -"-11750,89000" -] -) -start &183 -end &173 -sat 32 -eat 32 -st 0 -sf 1 -si 0 -tg (WTG -uid 6334,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 6335,0 -va (VaSet -) -xt "-18000,92000,-11700,93000" -st "not_TEST_TRG" -blo "-18000,92800" -tm "WireNameMgr" -) -) -on &179 -) -*296 (Wire -uid 6431,0 -shape (OrthoPolyLine -uid 6432,0 -va (VaSet -vasetType 3 -) -xt "80750,121000,111000,121000" -pts [ -"80750,121000" -"111000,121000" -] -) -start &43 -end &149 -sat 32 -eat 32 -stc 0 -st 0 -sf 1 -si 0 -tg (WTG -uid 6435,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 6436,0 -va (VaSet -isHidden 1 -) -xt "92000,120000,96000,121000" -st "DENABLE" -blo "92000,120800" -tm "WireNameMgr" -) -) -on &158 -) -*297 (Wire -uid 6787,0 -shape (OrthoPolyLine -uid 6788,0 +uid 8854,0 va (VaSet vasetType 3 lineWidth 2 ) -xt "93000,132000,99000,132000" -pts [ -"93000,132000" -"99000,132000" -] -) -start &213 -end &217 +xt "10000,109000,51250,132000" +pts [ +"51250,109000" +"10000,109000" +"10000,132000" +"31000,132000" +] +) +start &30 +end &201 sat 32 eat 1 @@ -9242,37 +8854,71 @@ si 0 tg (WTG -uid 6791,0 +uid 8857,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text -uid 6792,0 -va (VaSet -isHidden 1 -) -xt "95000,131000,101800,132000" -st "D_PLLLCK : (3:0)" -blo "95000,131800" -tm "WireNameMgr" -) -) -on &214 -) -*298 (Wire -uid 6880,0 +uid 8858,0 +va (VaSet +) +xt "42000,108000,50500,109000" +st "drs_channel_id : (3:0)" +blo "42000,108800" +tm "WireNameMgr" +) +) +on &221 +) +*283 (Wire +uid 9193,0 shape (OrthoPolyLine -uid 6881,0 +uid 9194,0 va (VaSet vasetType 3 lineWidth 2 ) -xt "102000,132000,109000,132000" -pts [ -"102000,132000" -"109000,132000" -] -) -start &217 -end &215 -sat 2 +xt "93000,136000,103000,136000" +pts [ +"93000,136000" +"103000,136000" +] +) +sat 16 +eat 16 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 9199,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 9200,0 +va (VaSet +) +xt "95000,135000,99800,136000" +st "A0_T : (7:0)" +blo "95000,135800" +tm "WireNameMgr" +) +) +on &222 +) +*284 (Wire +uid 9300,0 +shape (OrthoPolyLine +uid 9301,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "54000,140000,64000,140000" +pts [ +"54000,140000" +"64000,140000" +] +) +end &223 +sat 16 eat 32 sty 1 @@ -9281,34 +8927,34 @@ si 0 tg (WTG -uid 6884,0 +uid 9304,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text -uid 6885,0 +uid 9305,0 va (VaSet isHidden 1 ) -xt "104000,131000,108900,132000" -st "D_T2 : (3:0)" -blo "104000,131800" -tm "WireNameMgr" -) -) -on &216 -) -*299 (Wire -uid 7102,0 +xt "56000,139000,60800,140000" +st "A0_T : (7:0)" +blo "56000,139800" +tm "WireNameMgr" +) +) +on &222 +) +*285 (Wire +uid 9492,0 shape (OrthoPolyLine -uid 7103,0 +uid 9493,0 va (VaSet vasetType 3 ) -xt "21000,132000,31000,132000" -pts [ -"21000,132000" -"31000,132000" -] -) -end &221 +xt "21000,135000,31000,135000" +pts [ +"21000,135000" +"31000,135000" +] +) +end &201 sat 16 eat 1 @@ -9317,199 +8963,53 @@ si 0 tg (WTG -uid 7108,0 +uid 9498,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text -uid 7109,0 -va (VaSet -) -xt "23000,131000,27600,132000" -st "D0_SROUT" -blo "23000,131800" -tm "WireNameMgr" -) -) -on &106 -) -*300 (Wire -uid 7110,0 +uid 9499,0 +va (VaSet +) +xt "23000,134000,26700,135000" +st "TRG_OR" +blo "23000,134800" +tm "WireNameMgr" +) +) +on &169 +) +*286 (Wire +uid 9502,0 shape (OrthoPolyLine -uid 7111,0 +uid 9503,0 va (VaSet vasetType 3 ) -xt "21000,133000,31000,133000" -pts [ -"21000,133000" -"31000,133000" -] -) -end &221 -sat 16 -eat 1 +xt "46000,69000,51250,69000" +pts [ +"51250,69000" +"46000,69000" +] +) +start &26 +sat 32 +eat 16 st 0 sf 1 si 0 tg (WTG -uid 7116,0 +uid 9506,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text -uid 7117,0 -va (VaSet -) -xt "23000,132000,27600,133000" -st "D1_SROUT" -blo "23000,132800" -tm "WireNameMgr" -) -) -on &107 -) -*301 (Wire -uid 7118,0 -shape (OrthoPolyLine -uid 7119,0 -va (VaSet -vasetType 3 -) -xt "21000,134000,31000,134000" -pts [ -"21000,134000" -"31000,134000" -] -) -end &221 -sat 16 -eat 1 -st 0 -sf 1 -si 0 -tg (WTG -uid 7124,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 7125,0 -va (VaSet -) -xt "23000,133000,27200,134000" -st "RSRLOAD" -blo "23000,133800" -tm "WireNameMgr" -) -) -on &64 -) -*302 (Wire -uid 7144,0 -shape (OrthoPolyLine -uid 7145,0 -va (VaSet -vasetType 3 -lineWidth 2 -) -xt "39000,132000,44000,132000" -pts [ -"39000,132000" -"44000,132000" -] -) -start &221 -end &225 -sat 2 -eat 32 -sty 1 -st 0 -sf 1 -si 0 -tg (WTG -uid 7148,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 7149,0 -va (VaSet -isHidden 1 -) -xt "41000,131000,45800,132000" -st "A1_T : (3:0)" -blo "41000,131800" -tm "WireNameMgr" -) -) -on &226 -) -*303 (Wire -uid 7477,0 -shape (OrthoPolyLine -uid 7478,0 -va (VaSet -vasetType 3 -) -xt "80750,87000,91000,87000" -pts [ -"80750,87000" -"91000,87000" -] -) -start &38 -end &229 -es 0 -sat 32 -eat 32 -st 0 -sf 1 -si 0 -tg (WTG -uid 7483,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 7484,0 -va (VaSet -) -xt "83000,86000,85700,87000" -st "dummy" -blo "83000,86800" -tm "WireNameMgr" -) -) -on &227 -) -*304 (Wire -uid 7487,0 -shape (OrthoPolyLine -uid 7488,0 -va (VaSet -vasetType 3 -) -xt "21000,135000,31000,135000" -pts [ -"21000,135000" -"31000,135000" -] -) -end &221 -sat 16 -eat 1 -st 0 -sf 1 -si 0 -tg (WTG -uid 7493,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 7494,0 -va (VaSet -) -xt "23000,134000,25700,135000" -st "dummy" -blo "23000,134800" -tm "WireNameMgr" -) -) -on &227 +uid 9507,0 +va (VaSet +) +xt "47000,68000,50100,69000" +st "CLK_50" +blo "47000,68800" +tm "WireNameMgr" +) +) +on &224 ) ] @@ -9525,9 +9025,9 @@ color "26368,26368,26368" ) -packageList *305 (PackageList +packageList *287 (PackageList uid 41,0 stg "VerticalLayoutStrategy" textVec [ -*306 (Text +*288 (Text uid 42,0 va (VaSet @@ -9538,5 +9038,5 @@ blo "0,800" ) -*307 (MLText +*289 (MLText uid 43,0 va (VaSet @@ -9559,5 +9059,5 @@ stg "VerticalLayoutStrategy" textVec [ -*308 (Text +*290 (Text uid 45,0 va (VaSet @@ -9569,5 +9069,5 @@ blo "20000,800" ) -*309 (Text +*291 (Text uid 46,0 va (VaSet @@ -9579,5 +9079,5 @@ blo "20000,1800" ) -*310 (MLText +*292 (MLText uid 47,0 va (VaSet @@ -9589,5 +9089,5 @@ tm "BdCompilerDirectivesTextMgr" ) -*311 (Text +*293 (Text uid 48,0 va (VaSet @@ -9599,5 +9099,5 @@ blo "20000,4800" ) -*312 (MLText +*294 (MLText uid 49,0 va (VaSet @@ -9607,5 +9107,5 @@ tm "BdCompilerDirectivesTextMgr" ) -*313 (Text +*295 (Text uid 50,0 va (VaSet @@ -9617,5 +9117,5 @@ blo "20000,5800" ) -*314 (MLText +*296 (MLText uid 51,0 va (VaSet @@ -9628,7 +9128,7 @@ associable 1 ) -windowSize "0,0,1281,1002" -viewArea "-23100,-5300,61780,62940" -cachedDiagramExtent "-35500,0,699000,450107" +windowSize "0,22,1281,1024" +viewArea "-13800,92200,71080,160440" +cachedDiagramExtent "0,0,699000,450107" pageSetupInfo (PageSetupInfo ptrCmd "" @@ -9641,6 +9141,6 @@ ) hasePageBreakOrigin 1 -pageBreakOrigin "-73000,0" -lastUid 8652,0 +pageBreakOrigin "0,0" +lastUid 9715,0 defaultCommentText (CommentText shape (Rectangle @@ -9704,5 +9204,5 @@ stg "VerticalLayoutStrategy" textVec [ -*315 (Text +*297 (Text va (VaSet font "Arial,8,1" @@ -9713,5 +9213,5 @@ tm "BdLibraryNameMgr" ) -*316 (Text +*298 (Text va (VaSet font "Arial,8,1" @@ -9722,5 +9222,5 @@ tm "BlkNameMgr" ) -*317 (Text +*299 (Text va (VaSet font "Arial,8,1" @@ -9773,5 +9273,5 @@ stg "VerticalLayoutStrategy" textVec [ -*318 (Text +*300 (Text va (VaSet font "Arial,8,1" @@ -9781,5 +9281,5 @@ blo "550,4300" ) -*319 (Text +*301 (Text va (VaSet font "Arial,8,1" @@ -9789,5 +9289,5 @@ blo "550,5300" ) -*320 (Text +*302 (Text va (VaSet font "Arial,8,1" @@ -9838,5 +9338,5 @@ stg "VerticalLayoutStrategy" textVec [ -*321 (Text +*303 (Text va (VaSet font "Arial,8,1" @@ -9847,5 +9347,5 @@ tm "BdLibraryNameMgr" ) -*322 (Text +*304 (Text va (VaSet font "Arial,8,1" @@ -9856,5 +9356,5 @@ tm "CptNameMgr" ) -*323 (Text +*305 (Text va (VaSet font "Arial,8,1" @@ -9910,5 +9410,5 @@ stg "VerticalLayoutStrategy" textVec [ -*324 (Text +*306 (Text va (VaSet font "Arial,8,1" @@ -9918,5 +9418,5 @@ blo "500,4300" ) -*325 (Text +*307 (Text va (VaSet font "Arial,8,1" @@ -9926,5 +9426,5 @@ blo "500,5300" ) -*326 (Text +*308 (Text va (VaSet font "Arial,8,1" @@ -9971,5 +9471,5 @@ stg "VerticalLayoutStrategy" textVec [ -*327 (Text +*309 (Text va (VaSet font "Arial,8,1" @@ -9979,5 +9479,5 @@ blo "50,4300" ) -*328 (Text +*310 (Text va (VaSet font "Arial,8,1" @@ -9987,5 +9487,5 @@ blo "50,5300" ) -*329 (Text +*311 (Text va (VaSet font "Arial,8,1" @@ -10028,5 +9528,5 @@ stg "VerticalLayoutStrategy" textVec [ -*330 (Text +*312 (Text va (VaSet font "Arial,8,1" @@ -10037,5 +9537,5 @@ tm "HdlTextNameMgr" ) -*331 (Text +*313 (Text va (VaSet font "Arial,8,1" @@ -10440,5 +9940,5 @@ stg "VerticalLayoutStrategy" textVec [ -*332 (Text +*314 (Text va (VaSet font "Arial,8,1" @@ -10448,5 +9948,5 @@ blo "14100,20800" ) -*333 (MLText +*315 (MLText va (VaSet ) @@ -10500,5 +10000,5 @@ stg "VerticalLayoutStrategy" textVec [ -*334 (Text +*316 (Text va (VaSet font "Arial,8,1" @@ -10508,5 +10008,5 @@ blo "14100,20800" ) -*335 (MLText +*317 (MLText va (VaSet ) @@ -10626,7 +10126,7 @@ font "Arial,8,1" ) -xt "37000,43000,44100,44000" +xt "37000,43800,44100,44800" st "Diagram Signals:" -blo "37000,43800" +blo "37000,44600" ) postUserLabel (Text @@ -10652,44 +10152,44 @@ commonDM (CommonDM ldm (LogicalDM -suid 158,0 +suid 163,0 usingSuid 1 -emptyRow *336 (LEmptyRow +emptyRow *318 (LEmptyRow ) uid 54,0 optionalChildren [ -*337 (RefLabelRowHdr -) -*338 (TitleRowHdr -) -*339 (FilterRowHdr -) -*340 (RefLabelColHdr +*319 (RefLabelRowHdr +) +*320 (TitleRowHdr +) +*321 (FilterRowHdr +) +*322 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*341 (RowExpandColHdr +*323 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*342 (GroupColHdr +*324 (GroupColHdr tm "GroupColHdrMgr" ) -*343 (NameColHdr +*325 (NameColHdr tm "BlockDiagramNameColHdrMgr" ) -*344 (ModeColHdr +*326 (ModeColHdr tm "BlockDiagramModeColHdrMgr" ) -*345 (TypeColHdr +*327 (TypeColHdr tm "BlockDiagramTypeColHdrMgr" ) -*346 (BoundsColHdr +*328 (BoundsColHdr tm "BlockDiagramBoundsColHdrMgr" ) -*347 (InitColHdr +*329 (InitColHdr tm "BlockDiagramInitColHdrMgr" ) -*348 (EolColHdr +*330 (EolColHdr tm "BlockDiagramEolColHdrMgr" ) -*349 (LeafLogPort +*331 (LeafLogPort port (LogicalPort m 4 @@ -10700,5 +10200,5 @@ preAdd 0 posAdd 0 -o 55 +o 56 suid 5,0 ) @@ -10706,5 +10206,5 @@ uid 327,0 ) -*350 (LeafLogPort +*332 (LeafLogPort port (LogicalPort m 4 @@ -10713,5 +10213,5 @@ t "std_logic_vector" b "(1 downto 0)" -o 56 +o 57 suid 6,0 ) @@ -10719,5 +10219,5 @@ uid 329,0 ) -*351 (LeafLogPort +*333 (LeafLogPort port (LogicalPort m 4 @@ -10725,5 +10225,5 @@ n "adc_data_array" t "adc_data_array_type" -o 54 +o 55 suid 29,0 ) @@ -10731,38 +10231,24 @@ uid 1491,0 ) -*352 (LeafLogPort +*334 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "RSRLOAD" +t "std_logic" +o 36 +suid 57,0 +i "'0'" +) +) +uid 2435,0 +) +*335 (LeafLogPort port (LogicalPort m 4 decl (Decl -n "CLK_50" -t "std_logic" -preAdd 0 -posAdd 0 -o 51 -suid 54,0 -) -) -uid 2275,0 -) -*353 (LeafLogPort -port (LogicalPort -m 1 -decl (Decl -n "RSRLOAD" -t "std_logic" -o 35 -suid 57,0 -i "'0'" -) -) -uid 2435,0 -) -*354 (LeafLogPort -port (LogicalPort -m 4 -decl (Decl n "SRCLK" t "std_logic" -o 52 +o 53 suid 58,0 i "'0'" @@ -10771,5 +10257,5 @@ uid 2437,0 ) -*355 (LeafLogPort +*336 (LeafLogPort port (LogicalPort m 4 @@ -10778,5 +10264,5 @@ t "std_logic_vector" b "(3 DOWNTO 0)" -o 59 +o 60 suid 65,0 ) @@ -10784,5 +10270,5 @@ uid 3037,0 ) -*356 (LeafLogPort +*337 (LeafLogPort port (LogicalPort m 1 @@ -10790,5 +10276,5 @@ n "DAC_CS" t "std_logic" -o 21 +o 22 suid 66,0 ) @@ -10796,5 +10282,5 @@ uid 3039,0 ) -*357 (LeafLogPort +*338 (LeafLogPort port (LogicalPort decl (Decl @@ -10809,5 +10295,5 @@ uid 3276,0 ) -*358 (LeafLogPort +*339 (LeafLogPort port (LogicalPort decl (Decl @@ -10820,5 +10306,5 @@ uid 3278,0 ) -*359 (LeafLogPort +*340 (LeafLogPort port (LogicalPort m 1 @@ -10827,5 +10313,5 @@ t "std_logic_vector" b "(3 downto 0)" -o 16 +o 17 suid 71,0 ) @@ -10833,5 +10319,5 @@ uid 3280,0 ) -*360 (LeafLogPort +*341 (LeafLogPort port (LogicalPort m 4 @@ -10839,5 +10325,5 @@ n "CLK_25_PS" t "std_logic" -o 50 +o 51 suid 72,0 ) @@ -10845,5 +10331,5 @@ uid 3282,0 ) -*361 (LeafLogPort +*342 (LeafLogPort port (LogicalPort m 1 @@ -10853,5 +10339,5 @@ preAdd 0 posAdd 0 -o 30 +o 31 suid 73,0 ) @@ -10859,5 +10345,5 @@ uid 3382,0 ) -*362 (LeafLogPort +*343 (LeafLogPort port (LogicalPort decl (Decl @@ -10871,5 +10357,5 @@ uid 3384,0 ) -*363 (LeafLogPort +*344 (LeafLogPort port (LogicalPort decl (Decl @@ -10883,5 +10369,5 @@ uid 3386,0 ) -*364 (LeafLogPort +*345 (LeafLogPort port (LogicalPort decl (Decl @@ -10895,5 +10381,5 @@ uid 3388,0 ) -*365 (LeafLogPort +*346 (LeafLogPort port (LogicalPort decl (Decl @@ -10907,5 +10393,5 @@ uid 3390,0 ) -*366 (LeafLogPort +*347 (LeafLogPort port (LogicalPort decl (Decl @@ -10919,5 +10405,5 @@ uid 3392,0 ) -*367 (LeafLogPort +*348 (LeafLogPort port (LogicalPort m 1 @@ -10925,5 +10411,5 @@ n "D0_SRCLK" t "STD_LOGIC" -o 17 +o 18 suid 87,0 ) @@ -10931,5 +10417,5 @@ uid 3468,0 ) -*368 (LeafLogPort +*349 (LeafLogPort port (LogicalPort m 1 @@ -10937,5 +10423,5 @@ n "D1_SRCLK" t "STD_LOGIC" -o 18 +o 19 suid 88,0 ) @@ -10943,5 +10429,5 @@ uid 3470,0 ) -*369 (LeafLogPort +*350 (LeafLogPort port (LogicalPort m 1 @@ -10949,5 +10435,5 @@ n "D2_SRCLK" t "STD_LOGIC" -o 19 +o 20 suid 89,0 ) @@ -10955,5 +10441,5 @@ uid 3472,0 ) -*370 (LeafLogPort +*351 (LeafLogPort port (LogicalPort m 1 @@ -10961,5 +10447,5 @@ n "D3_SRCLK" t "STD_LOGIC" -o 20 +o 21 suid 90,0 ) @@ -10967,5 +10453,5 @@ uid 3474,0 ) -*371 (LeafLogPort +*352 (LeafLogPort port (LogicalPort decl (Decl @@ -10978,5 +10464,5 @@ uid 3524,0 ) -*372 (LeafLogPort +*353 (LeafLogPort port (LogicalPort decl (Decl @@ -10989,5 +10475,5 @@ uid 3526,0 ) -*373 (LeafLogPort +*354 (LeafLogPort port (LogicalPort decl (Decl @@ -11000,5 +10486,5 @@ uid 3528,0 ) -*374 (LeafLogPort +*355 (LeafLogPort port (LogicalPort decl (Decl @@ -11011,5 +10497,5 @@ uid 3530,0 ) -*375 (LeafLogPort +*356 (LeafLogPort port (LogicalPort m 1 @@ -11018,5 +10504,5 @@ t "std_logic_vector" b "(3 DOWNTO 0)" -o 24 +o 25 suid 95,0 i "(others => '0')" @@ -11025,5 +10511,5 @@ uid 3532,0 ) -*376 (LeafLogPort +*357 (LeafLogPort port (LogicalPort m 1 @@ -11031,5 +10517,5 @@ n "DWRITE" t "std_logic" -o 23 +o 24 suid 96,0 i "'0'" @@ -11038,5 +10524,5 @@ uid 3534,0 ) -*377 (LeafLogPort +*358 (LeafLogPort port (LogicalPort m 1 @@ -11044,5 +10530,5 @@ n "T0_CS" t "std_logic" -o 38 +o 39 suid 101,0 ) @@ -11050,5 +10536,5 @@ uid 3646,0 ) -*378 (LeafLogPort +*359 (LeafLogPort port (LogicalPort m 1 @@ -11056,5 +10542,5 @@ n "T1_CS" t "std_logic" -o 39 +o 40 suid 102,0 ) @@ -11062,5 +10548,5 @@ uid 3648,0 ) -*379 (LeafLogPort +*360 (LeafLogPort port (LogicalPort m 1 @@ -11068,5 +10554,5 @@ n "T2_CS" t "std_logic" -o 40 +o 41 suid 103,0 ) @@ -11074,5 +10560,5 @@ uid 3650,0 ) -*380 (LeafLogPort +*361 (LeafLogPort port (LogicalPort m 1 @@ -11080,5 +10566,5 @@ n "T3_CS" t "std_logic" -o 41 +o 42 suid 104,0 ) @@ -11086,5 +10572,5 @@ uid 3652,0 ) -*381 (LeafLogPort +*362 (LeafLogPort port (LogicalPort m 1 @@ -11092,5 +10578,5 @@ n "S_CLK" t "std_logic" -o 37 +o 38 suid 105,0 ) @@ -11098,5 +10584,5 @@ uid 3654,0 ) -*382 (LeafLogPort +*363 (LeafLogPort port (LogicalPort m 1 @@ -11105,5 +10591,5 @@ t "std_logic_vector" b "(9 DOWNTO 0)" -o 43 +o 44 suid 106,0 ) @@ -11111,5 +10597,5 @@ uid 3656,0 ) -*383 (LeafLogPort +*364 (LeafLogPort port (LogicalPort m 2 @@ -11118,5 +10604,5 @@ t "std_logic_vector" b "(15 DOWNTO 0)" -o 49 +o 50 suid 107,0 ) @@ -11124,5 +10610,5 @@ uid 3658,0 ) -*384 (LeafLogPort +*365 (LeafLogPort port (LogicalPort m 1 @@ -11130,5 +10616,5 @@ n "W_RES" t "std_logic" -o 46 +o 47 suid 108,0 i "'1'" @@ -11137,5 +10623,5 @@ uid 3660,0 ) -*385 (LeafLogPort +*366 (LeafLogPort port (LogicalPort m 1 @@ -11143,5 +10629,5 @@ n "W_RD" t "std_logic" -o 45 +o 46 suid 109,0 i "'1'" @@ -11150,5 +10636,5 @@ uid 3662,0 ) -*386 (LeafLogPort +*367 (LeafLogPort port (LogicalPort m 1 @@ -11156,5 +10642,5 @@ n "W_WR" t "std_logic" -o 47 +o 48 suid 110,0 i "'1'" @@ -11163,5 +10649,5 @@ uid 3664,0 ) -*387 (LeafLogPort +*368 (LeafLogPort port (LogicalPort decl (Decl @@ -11174,5 +10660,5 @@ uid 3666,0 ) -*388 (LeafLogPort +*369 (LeafLogPort port (LogicalPort m 1 @@ -11180,5 +10666,5 @@ n "W_CS" t "std_logic" -o 44 +o 45 suid 112,0 i "'1'" @@ -11187,5 +10673,5 @@ uid 3668,0 ) -*389 (LeafLogPort +*370 (LeafLogPort port (LogicalPort m 1 @@ -11193,5 +10679,5 @@ n "MOSI" t "std_logic" -o 29 +o 30 suid 113,0 i "'0'" @@ -11200,5 +10686,5 @@ uid 3696,0 ) -*390 (LeafLogPort +*371 (LeafLogPort port (LogicalPort m 2 @@ -11208,5 +10694,5 @@ preAdd 0 posAdd 0 -o 48 +o 49 suid 114,0 ) @@ -11214,5 +10700,5 @@ uid 3698,0 ) -*391 (LeafLogPort +*372 (LeafLogPort port (LogicalPort m 1 @@ -11220,5 +10706,5 @@ n "TRG_V" t "std_logic" -o 42 +o 43 suid 126,0 ) @@ -11226,5 +10712,5 @@ uid 3886,0 ) -*392 (LeafLogPort +*373 (LeafLogPort port (LogicalPort m 1 @@ -11232,5 +10718,5 @@ n "RS485_C_RE" t "std_logic" -o 32 +o 33 suid 127,0 ) @@ -11238,5 +10724,5 @@ uid 3888,0 ) -*393 (LeafLogPort +*374 (LeafLogPort port (LogicalPort m 1 @@ -11244,5 +10730,5 @@ n "RS485_C_DE" t "std_logic" -o 31 +o 32 suid 128,0 ) @@ -11250,5 +10736,5 @@ uid 3890,0 ) -*394 (LeafLogPort +*375 (LeafLogPort port (LogicalPort m 1 @@ -11256,5 +10742,5 @@ n "RS485_E_RE" t "std_logic" -o 34 +o 35 suid 129,0 ) @@ -11262,5 +10748,5 @@ uid 3892,0 ) -*395 (LeafLogPort +*376 (LeafLogPort port (LogicalPort m 1 @@ -11268,5 +10754,5 @@ n "RS485_E_DE" t "std_logic" -o 33 +o 34 suid 130,0 ) @@ -11274,5 +10760,5 @@ uid 3894,0 ) -*396 (LeafLogPort +*377 (LeafLogPort port (LogicalPort m 1 @@ -11280,5 +10766,5 @@ n "DENABLE" t "std_logic" -o 22 +o 23 suid 131,0 i "'0'" @@ -11287,5 +10773,5 @@ uid 3896,0 ) -*397 (LeafLogPort +*378 (LeafLogPort port (LogicalPort m 1 @@ -11293,5 +10779,5 @@ n "SRIN" t "std_logic" -o 36 +o 37 suid 132,0 ) @@ -11299,5 +10785,5 @@ uid 3898,0 ) -*398 (LeafLogPort +*379 (LeafLogPort port (LogicalPort m 1 @@ -11305,5 +10791,5 @@ n "EE_CS" t "std_logic" -o 27 +o 28 suid 133,0 ) @@ -11311,5 +10797,5 @@ uid 3900,0 ) -*399 (LeafLogPort +*380 (LeafLogPort port (LogicalPort m 1 @@ -11318,5 +10804,5 @@ t "std_logic_vector" b "( 2 DOWNTO 0 )" -o 28 +o 29 suid 134,0 i "(others => '1')" @@ -11325,5 +10811,5 @@ uid 3902,0 ) -*400 (LeafLogPort +*381 (LeafLogPort port (LogicalPort m 1 @@ -11332,5 +10818,5 @@ t "std_logic_vector" b "(7 DOWNTO 0)" -o 25 +o 26 suid 141,0 i "(OTHERS => '0')" @@ -11339,5 +10825,5 @@ uid 5322,0 ) -*401 (LeafLogPort +*382 (LeafLogPort port (LogicalPort decl (Decl @@ -11351,5 +10837,5 @@ scheme 0 ) -*402 (LeafLogPort +*383 (LeafLogPort port (LogicalPort m 4 @@ -11357,5 +10843,5 @@ n "TRG_OR" t "std_logic" -o 53 +o 54 suid 146,0 ) @@ -11364,33 +10850,5 @@ scheme 0 ) -*403 (LeafLogPort -port (LogicalPort -m 4 -decl (Decl -n "trigger_out" -t "STD_LOGIC" -preAdd 0 -posAdd 0 -o 60 -suid 147,0 -i "'0'" -) -) -uid 6286,0 -) -*404 (LeafLogPort -port (LogicalPort -m 4 -decl (Decl -n "not_TEST_TRG" -t "STD_LOGIC" -o 58 -suid 148,0 -) -) -uid 6314,0 -scheme 0 -) -*405 (LeafLogPort +*384 (LeafLogPort port (LogicalPort decl (Decl @@ -11405,5 +10863,5 @@ scheme 0 ) -*406 (LeafLogPort +*385 (LeafLogPort port (LogicalPort m 1 @@ -11412,5 +10870,5 @@ t "std_logic_vector" b "(3 DOWNTO 0)" -o 26 +o 27 suid 154,0 i "(others => '0')" @@ -11420,5 +10878,5 @@ scheme 0 ) -*407 (LeafLogPort +*386 (LeafLogPort port (LogicalPort m 1 @@ -11426,7 +10884,8 @@ n "A1_T" t "std_logic_vector" -b "(3 DOWNTO 0)" -o 15 +b "(7 DOWNTO 0)" +o 16 suid 155,0 +i "(OTHERS => '0')" ) ) @@ -11434,5 +10893,5 @@ scheme 0 ) -*408 (LeafLogPort +*387 (LeafLogPort port (LogicalPort m 4 @@ -11440,5 +10899,5 @@ n "dummy" t "std_logic" -o 60 +o 59 suid 157,0 ) @@ -11446,4 +10905,45 @@ uid 7473,0 scheme 0 +) +*388 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "drs_channel_id" +t "std_logic_vector" +b "(3 downto 0)" +o 58 +suid 159,0 +i "(others => '0')" +) +) +uid 8875,0 +) +*389 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "A0_T" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 15 +suid 162,0 +i "(OTHERS => '0')" +) +) +uid 9191,0 +scheme 0 +) +*390 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "CLK_50" +t "std_logic" +o 52 +suid 163,0 +) +) +uid 9516,0 ) ] @@ -11454,5 +10954,5 @@ uid 67,0 optionalChildren [ -*409 (Sheet +*391 (Sheet sheetRow (SheetRow headerVa (MVa @@ -11471,6 +10971,6 @@ font "Tahoma,10,0" ) -emptyMRCItem *410 (MRCItem -litem &336 +emptyMRCItem *392 (MRCItem +litem &318 pos 60 dimension 20 @@ -11478,18 +10978,18 @@ uid 69,0 optionalChildren [ -*411 (MRCItem -litem &337 +*393 (MRCItem +litem &319 pos 0 dimension 20 uid 70,0 ) -*412 (MRCItem -litem &338 +*394 (MRCItem +litem &320 pos 1 dimension 23 uid 71,0 ) -*413 (MRCItem -litem &339 +*395 (MRCItem +litem &321 pos 2 hidden 1 @@ -11497,363 +10997,363 @@ uid 72,0 ) -*414 (MRCItem -litem &349 -pos 44 +*396 (MRCItem +litem &331 +pos 50 dimension 20 uid 328,0 ) -*415 (MRCItem -litem &350 -pos 45 +*397 (MRCItem +litem &332 +pos 51 dimension 20 uid 330,0 ) -*416 (MRCItem -litem &351 -pos 46 +*398 (MRCItem +litem &333 +pos 52 dimension 20 uid 1492,0 ) -*417 (MRCItem -litem &352 -pos 47 -dimension 20 -uid 2276,0 -) -*418 (MRCItem -litem &353 +*399 (MRCItem +litem &334 pos 0 dimension 20 uid 2436,0 ) -*419 (MRCItem -litem &354 -pos 48 +*400 (MRCItem +litem &335 +pos 53 dimension 20 uid 2438,0 ) -*420 (MRCItem -litem &355 -pos 49 +*401 (MRCItem +litem &336 +pos 54 dimension 20 uid 3038,0 ) -*421 (MRCItem -litem &356 +*402 (MRCItem +litem &337 pos 1 dimension 20 uid 3040,0 ) -*422 (MRCItem -litem &357 +*403 (MRCItem +litem &338 pos 2 dimension 20 uid 3277,0 ) -*423 (MRCItem -litem &358 +*404 (MRCItem +litem &339 pos 3 dimension 20 uid 3279,0 ) -*424 (MRCItem -litem &359 +*405 (MRCItem +litem &340 pos 4 dimension 20 uid 3281,0 ) -*425 (MRCItem -litem &360 -pos 50 +*406 (MRCItem +litem &341 +pos 55 dimension 20 uid 3283,0 ) -*426 (MRCItem -litem &361 +*407 (MRCItem +litem &342 pos 5 dimension 20 uid 3383,0 ) -*427 (MRCItem -litem &362 +*408 (MRCItem +litem &343 pos 6 dimension 20 uid 3385,0 ) -*428 (MRCItem -litem &363 +*409 (MRCItem +litem &344 pos 7 dimension 20 uid 3387,0 ) -*429 (MRCItem -litem &364 +*410 (MRCItem +litem &345 pos 8 dimension 20 uid 3389,0 ) -*430 (MRCItem -litem &365 +*411 (MRCItem +litem &346 pos 9 dimension 20 uid 3391,0 ) -*431 (MRCItem -litem &366 +*412 (MRCItem +litem &347 pos 10 dimension 20 uid 3393,0 ) -*432 (MRCItem -litem &367 +*413 (MRCItem +litem &348 pos 11 dimension 20 uid 3469,0 ) -*433 (MRCItem -litem &368 +*414 (MRCItem +litem &349 pos 12 dimension 20 uid 3471,0 ) -*434 (MRCItem -litem &369 +*415 (MRCItem +litem &350 pos 13 dimension 20 uid 3473,0 ) -*435 (MRCItem -litem &370 +*416 (MRCItem +litem &351 pos 14 dimension 20 uid 3475,0 ) -*436 (MRCItem -litem &371 +*417 (MRCItem +litem &352 pos 15 dimension 20 uid 3525,0 ) -*437 (MRCItem -litem &372 +*418 (MRCItem +litem &353 pos 16 dimension 20 uid 3527,0 ) -*438 (MRCItem -litem &373 +*419 (MRCItem +litem &354 pos 17 dimension 20 uid 3529,0 ) -*439 (MRCItem -litem &374 +*420 (MRCItem +litem &355 pos 18 dimension 20 uid 3531,0 ) -*440 (MRCItem -litem &375 +*421 (MRCItem +litem &356 pos 19 dimension 20 uid 3533,0 ) -*441 (MRCItem -litem &376 +*422 (MRCItem +litem &357 pos 20 dimension 20 uid 3535,0 ) -*442 (MRCItem -litem &377 +*423 (MRCItem +litem &358 pos 21 dimension 20 uid 3647,0 ) -*443 (MRCItem -litem &378 +*424 (MRCItem +litem &359 pos 22 dimension 20 uid 3649,0 ) -*444 (MRCItem -litem &379 +*425 (MRCItem +litem &360 pos 23 dimension 20 uid 3651,0 ) -*445 (MRCItem -litem &380 +*426 (MRCItem +litem &361 pos 24 dimension 20 uid 3653,0 ) -*446 (MRCItem -litem &381 +*427 (MRCItem +litem &362 pos 25 dimension 20 uid 3655,0 ) -*447 (MRCItem -litem &382 +*428 (MRCItem +litem &363 pos 26 dimension 20 uid 3657,0 ) -*448 (MRCItem -litem &383 +*429 (MRCItem +litem &364 pos 27 dimension 20 uid 3659,0 ) -*449 (MRCItem -litem &384 +*430 (MRCItem +litem &365 pos 28 dimension 20 uid 3661,0 ) -*450 (MRCItem -litem &385 +*431 (MRCItem +litem &366 pos 29 dimension 20 uid 3663,0 ) -*451 (MRCItem -litem &386 +*432 (MRCItem +litem &367 pos 30 dimension 20 uid 3665,0 ) -*452 (MRCItem -litem &387 +*433 (MRCItem +litem &368 pos 31 dimension 20 uid 3667,0 ) -*453 (MRCItem -litem &388 +*434 (MRCItem +litem &369 pos 32 dimension 20 uid 3669,0 ) -*454 (MRCItem -litem &389 +*435 (MRCItem +litem &370 pos 33 dimension 20 uid 3697,0 ) -*455 (MRCItem -litem &390 +*436 (MRCItem +litem &371 pos 34 dimension 20 uid 3699,0 ) -*456 (MRCItem -litem &391 +*437 (MRCItem +litem &372 pos 35 dimension 20 uid 3887,0 ) -*457 (MRCItem -litem &392 +*438 (MRCItem +litem &373 pos 36 dimension 20 uid 3889,0 ) -*458 (MRCItem -litem &393 +*439 (MRCItem +litem &374 pos 37 dimension 20 uid 3891,0 ) -*459 (MRCItem -litem &394 +*440 (MRCItem +litem &375 pos 38 dimension 20 uid 3893,0 ) -*460 (MRCItem -litem &395 +*441 (MRCItem +litem &376 pos 39 dimension 20 uid 3895,0 ) -*461 (MRCItem -litem &396 +*442 (MRCItem +litem &377 pos 40 dimension 20 uid 3897,0 ) -*462 (MRCItem -litem &397 +*443 (MRCItem +litem &378 pos 41 dimension 20 uid 3899,0 ) -*463 (MRCItem -litem &398 +*444 (MRCItem +litem &379 pos 42 dimension 20 uid 3901,0 ) -*464 (MRCItem -litem &399 +*445 (MRCItem +litem &380 pos 43 dimension 20 uid 3903,0 ) -*465 (MRCItem -litem &400 -pos 51 +*446 (MRCItem +litem &381 +pos 44 dimension 20 uid 5323,0 ) -*466 (MRCItem -litem &401 -pos 52 +*447 (MRCItem +litem &382 +pos 45 dimension 20 uid 5649,0 ) -*467 (MRCItem -litem &402 -pos 53 +*448 (MRCItem +litem &383 +pos 56 dimension 20 uid 6129,0 ) -*468 (MRCItem -litem &403 -pos 54 -dimension 20 -uid 6287,0 -) -*469 (MRCItem -litem &404 -pos 55 -dimension 20 -uid 6315,0 -) -*470 (MRCItem -litem &405 -pos 56 +*449 (MRCItem +litem &384 +pos 46 dimension 20 uid 6778,0 ) -*471 (MRCItem -litem &406 +*450 (MRCItem +litem &385 +pos 47 +dimension 20 +uid 6873,0 +) +*451 (MRCItem +litem &386 +pos 48 +dimension 20 +uid 7135,0 +) +*452 (MRCItem +litem &387 pos 57 dimension 20 -uid 6873,0 -) -*472 (MRCItem -litem &407 +uid 7474,0 +) +*453 (MRCItem +litem &388 pos 58 dimension 20 -uid 7135,0 -) -*473 (MRCItem -litem &408 +uid 8876,0 +) +*454 (MRCItem +litem &389 +pos 49 +dimension 20 +uid 9192,0 +) +*455 (MRCItem +litem &390 pos 59 dimension 20 -uid 7474,0 +uid 9517,0 ) ] @@ -11868,48 +11368,48 @@ uid 73,0 optionalChildren [ -*474 (MRCItem -litem &340 +*456 (MRCItem +litem &322 pos 0 dimension 20 uid 74,0 ) -*475 (MRCItem -litem &342 +*457 (MRCItem +litem &324 pos 1 dimension 50 uid 75,0 ) -*476 (MRCItem -litem &343 +*458 (MRCItem +litem &325 pos 2 dimension 100 uid 76,0 ) -*477 (MRCItem -litem &344 +*459 (MRCItem +litem &326 pos 3 dimension 50 uid 77,0 ) -*478 (MRCItem -litem &345 +*460 (MRCItem +litem &327 pos 4 dimension 100 uid 78,0 ) -*479 (MRCItem -litem &346 +*461 (MRCItem +litem &328 pos 5 dimension 100 uid 79,0 ) -*480 (MRCItem -litem &347 +*462 (MRCItem +litem &329 pos 6 dimension 92 uid 80,0 ) -*481 (MRCItem -litem &348 +*463 (MRCItem +litem &330 pos 7 dimension 80 @@ -11931,36 +11431,36 @@ genericsCommonDM (CommonDM ldm (LogicalDM -emptyRow *482 (LEmptyRow +emptyRow *464 (LEmptyRow ) uid 83,0 optionalChildren [ -*483 (RefLabelRowHdr -) -*484 (TitleRowHdr -) -*485 (FilterRowHdr -) -*486 (RefLabelColHdr +*465 (RefLabelRowHdr +) +*466 (TitleRowHdr +) +*467 (FilterRowHdr +) +*468 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*487 (RowExpandColHdr +*469 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*488 (GroupColHdr +*470 (GroupColHdr tm "GroupColHdrMgr" ) -*489 (NameColHdr +*471 (NameColHdr tm "GenericNameColHdrMgr" ) -*490 (TypeColHdr +*472 (TypeColHdr tm "GenericTypeColHdrMgr" ) -*491 (InitColHdr +*473 (InitColHdr tm "GenericValueColHdrMgr" ) -*492 (PragmaColHdr +*474 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) -*493 (EolColHdr +*475 (EolColHdr tm "GenericEolColHdrMgr" ) @@ -11972,5 +11472,5 @@ uid 95,0 optionalChildren [ -*494 (Sheet +*476 (Sheet sheetRow (SheetRow headerVa (MVa @@ -11989,6 +11489,6 @@ font "Tahoma,10,0" ) -emptyMRCItem *495 (MRCItem -litem &482 +emptyMRCItem *477 (MRCItem +litem &464 pos 0 dimension 20 @@ -11996,18 +11496,18 @@ uid 97,0 optionalChildren [ -*496 (MRCItem -litem &483 +*478 (MRCItem +litem &465 pos 0 dimension 20 uid 98,0 ) -*497 (MRCItem -litem &484 +*479 (MRCItem +litem &466 pos 1 dimension 23 uid 99,0 ) -*498 (MRCItem -litem &485 +*480 (MRCItem +litem &467 pos 2 hidden 1 @@ -12026,42 +11526,42 @@ uid 101,0 optionalChildren [ -*499 (MRCItem -litem &486 +*481 (MRCItem +litem &468 pos 0 dimension 20 uid 102,0 ) -*500 (MRCItem -litem &488 +*482 (MRCItem +litem &470 pos 1 dimension 50 uid 103,0 ) -*501 (MRCItem -litem &489 +*483 (MRCItem +litem &471 pos 2 dimension 100 uid 104,0 ) -*502 (MRCItem -litem &490 +*484 (MRCItem +litem &472 pos 3 dimension 100 uid 105,0 ) -*503 (MRCItem -litem &491 +*485 (MRCItem +litem &473 pos 4 dimension 50 uid 106,0 ) -*504 (MRCItem -litem &492 +*486 (MRCItem +litem &474 pos 5 dimension 50 uid 107,0 ) -*505 (MRCItem -litem &493 +*487 (MRCItem +litem &475 pos 6 dimension 80 Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb (revision 252) @@ -21,5 +21,5 @@ commonDM (CommonDM ldm (LogicalDM -suid 66,0 +suid 67,0 usingSuid 1 emptyRow *1 (LEmptyRow @@ -659,7 +659,8 @@ n "A1_T" t "std_logic_vector" -b "(3 DOWNTO 0)" +b "(7 DOWNTO 0)" o 15 suid 66,0 +i "(OTHERS => '0')" ) ) @@ -1239,21 +1240,21 @@ (vvPair variable "HDLDir" -value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hdl" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" ) (vvPair variable "HDSDir" -value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair variable "SideDataDesignDir" -value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info" ) (vvPair variable "SideDataUserDir" -value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user" ) (vvPair variable "SourceDir" -value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair @@ -1271,13 +1272,13 @@ (vvPair variable "d" -value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board" ) (vvPair variable "d_logical" -value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\FAD_Board" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board" ) (vvPair variable "date" -value "16.06.2010" +value "14.07.2010" ) (vvPair @@ -1291,5 +1292,5 @@ (vvPair variable "dd" -value "16" +value "14" ) (vvPair @@ -1319,5 +1320,5 @@ (vvPair variable "host" -value "TU-CC4900F8C7D2" +value "E5B-LABOR6" ) (vvPair @@ -1330,4 +1331,8 @@ ) (vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR\\FACT_FAD_lib\\designcheck" +) +(vvPair variable "library_downstream_ISEPARInvoke" value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" @@ -1347,5 +1352,5 @@ (vvPair variable "mm" -value "06" +value "07" ) (vvPair @@ -1355,17 +1360,17 @@ (vvPair variable "month" -value "Jun" +value "Jul" ) (vvPair variable "month_long" -value "Juni" +value "Juli" ) (vvPair variable "p" -value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb" ) (vvPair variable "p_logical" -value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb" ) (vvPair @@ -1423,5 +1428,5 @@ (vvPair variable "time" -value "15:30:04" +value "15:25:08" ) (vvPair @@ -1500,5 +1505,6 @@ ) xt "44000,29200,76000,30000" -st "RSRLOAD : OUT std_logic := '0' ;" +st "RSRLOAD : OUT std_logic := '0' ; +" ) thePort (LogicalPort @@ -1545,5 +1551,6 @@ ) xt "44000,12400,61500,13200" -st "X_50M : IN STD_LOGIC ;" +st "X_50M : IN STD_LOGIC ; +" ) thePort (LogicalPort @@ -1590,5 +1597,6 @@ ) xt "44000,10800,61500,11600" -st "TRG : IN STD_LOGIC ;" +st "TRG : IN STD_LOGIC ; +" ) thePort (LogicalPort @@ -1634,5 +1642,6 @@ ) xt "44000,14000,71500,14800" -st "A_CLK : OUT std_logic_vector (3 downto 0) ;" +st "A_CLK : OUT std_logic_vector (3 downto 0) ; +" ) thePort (LogicalPort @@ -1680,5 +1689,6 @@ ) xt "44000,25200,61500,26000" -st "OE_ADC : OUT STD_LOGIC ;" +st "OE_ADC : OUT STD_LOGIC ; +" ) thePort (LogicalPort @@ -1726,5 +1736,6 @@ ) xt "44000,5200,71500,6000" -st "A_OTR : IN std_logic_vector (3 DOWNTO 0) ;" +st "A_OTR : IN std_logic_vector (3 DOWNTO 0) ; +" ) thePort (LogicalPort @@ -1770,5 +1781,6 @@ ) xt "44000,2000,72000,2800" -st "A0_D : IN std_logic_vector (11 DOWNTO 0) ;" +st "A0_D : IN std_logic_vector (11 DOWNTO 0) ; +" ) thePort (LogicalPort @@ -1814,5 +1826,6 @@ ) xt "44000,2800,72000,3600" -st "A1_D : IN std_logic_vector (11 DOWNTO 0) ;" +st "A1_D : IN std_logic_vector (11 DOWNTO 0) ; +" ) thePort (LogicalPort @@ -1858,5 +1871,6 @@ ) xt "44000,3600,72000,4400" -st "A2_D : IN std_logic_vector (11 DOWNTO 0) ;" +st "A2_D : IN std_logic_vector (11 DOWNTO 0) ; +" ) thePort (LogicalPort @@ -1902,5 +1916,6 @@ ) xt "44000,4400,72000,5200" -st "A3_D : IN std_logic_vector (11 DOWNTO 0) ;" +st "A3_D : IN std_logic_vector (11 DOWNTO 0) ; +" ) thePort (LogicalPort @@ -1947,5 +1962,6 @@ ) xt "44000,14800,61500,15600" -st "D0_SRCLK : OUT STD_LOGIC ;" +st "D0_SRCLK : OUT STD_LOGIC ; +" ) thePort (LogicalPort @@ -1992,5 +2008,6 @@ ) xt "44000,15600,61500,16400" -st "D1_SRCLK : OUT STD_LOGIC ;" +st "D1_SRCLK : OUT STD_LOGIC ; +" ) thePort (LogicalPort @@ -2037,5 +2054,6 @@ ) xt "44000,16400,61500,17200" -st "D2_SRCLK : OUT STD_LOGIC ;" +st "D2_SRCLK : OUT STD_LOGIC ; +" ) thePort (LogicalPort @@ -2082,5 +2100,6 @@ ) xt "44000,17200,61500,18000" -st "D3_SRCLK : OUT STD_LOGIC ;" +st "D3_SRCLK : OUT STD_LOGIC ; +" ) thePort (LogicalPort @@ -2126,5 +2145,6 @@ ) xt "44000,6000,61500,6800" -st "D0_SROUT : IN std_logic ;" +st "D0_SROUT : IN std_logic ; +" ) thePort (LogicalPort @@ -2169,5 +2189,6 @@ ) xt "44000,6800,61500,7600" -st "D1_SROUT : IN std_logic ;" +st "D1_SROUT : IN std_logic ; +" ) thePort (LogicalPort @@ -2212,5 +2233,6 @@ ) xt "44000,7600,61500,8400" -st "D2_SROUT : IN std_logic ;" +st "D2_SROUT : IN std_logic ; +" ) thePort (LogicalPort @@ -2255,5 +2277,6 @@ ) xt "44000,8400,61500,9200" -st "D3_SROUT : IN std_logic ;" +st "D3_SROUT : IN std_logic ; +" ) thePort (LogicalPort @@ -2309,5 +2332,6 @@ ) xt "44000,20400,82000,21200" -st "D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ;" +st "D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ; +" ) thePort (LogicalPort @@ -2366,5 +2390,6 @@ ) xt "44000,19600,76000,20400" -st "DWRITE : OUT std_logic := '0' ;" +st "DWRITE : OUT std_logic := '0' ; +" ) thePort (LogicalPort @@ -2412,5 +2437,6 @@ ) xt "44000,18000,61500,18800" -st "DAC_CS : OUT std_logic ;" +st "DAC_CS : OUT std_logic ; +" ) thePort (LogicalPort @@ -2457,5 +2483,6 @@ ) xt "44000,31600,61500,32400" -st "T0_CS : OUT std_logic ;" +st "T0_CS : OUT std_logic ; +" ) thePort (LogicalPort @@ -2502,5 +2529,6 @@ ) xt "44000,32400,61500,33200" -st "T1_CS : OUT std_logic ;" +st "T1_CS : OUT std_logic ; +" ) thePort (LogicalPort @@ -2547,5 +2575,6 @@ ) xt "44000,33200,61500,34000" -st "T2_CS : OUT std_logic ;" +st "T2_CS : OUT std_logic ; +" ) thePort (LogicalPort @@ -2592,5 +2621,6 @@ ) xt "44000,34000,61500,34800" -st "T3_CS : OUT std_logic ;" +st "T3_CS : OUT std_logic ; +" ) thePort (LogicalPort @@ -2637,5 +2667,6 @@ ) xt "44000,30800,61500,31600" -st "S_CLK : OUT std_logic ;" +st "S_CLK : OUT std_logic ; +" ) thePort (LogicalPort @@ -2682,5 +2713,6 @@ ) xt "44000,35600,71500,36400" -st "W_A : OUT std_logic_vector (9 DOWNTO 0) ;" +st "W_A : OUT std_logic_vector (9 DOWNTO 0) ; +" ) thePort (LogicalPort @@ -2728,5 +2760,6 @@ ) xt "44000,40400,71000,41200" -st "W_D : INOUT std_logic_vector (15 DOWNTO 0)" +st "W_D : INOUT std_logic_vector (15 DOWNTO 0) +" ) thePort (LogicalPort @@ -2784,5 +2817,6 @@ ) xt "44000,38000,76000,38800" -st "W_RES : OUT std_logic := '1' ;" +st "W_RES : OUT std_logic := '1' ; +" ) thePort (LogicalPort @@ -2840,5 +2874,6 @@ ) xt "44000,37200,76000,38000" -st "W_RD : OUT std_logic := '1' ;" +st "W_RD : OUT std_logic := '1' ; +" ) thePort (LogicalPort @@ -2896,5 +2931,6 @@ ) xt "44000,38800,76000,39600" -st "W_WR : OUT std_logic := '1' ;" +st "W_WR : OUT std_logic := '1' ; +" ) thePort (LogicalPort @@ -2941,5 +2977,6 @@ ) xt "44000,11600,61500,12400" -st "W_INT : IN std_logic ;" +st "W_INT : IN std_logic ; +" ) thePort (LogicalPort @@ -2995,5 +3032,6 @@ ) xt "44000,36400,76000,37200" -st "W_CS : OUT std_logic := '1' ;" +st "W_CS : OUT std_logic := '1' ; +" ) thePort (LogicalPort @@ -3051,5 +3089,6 @@ ) xt "44000,24400,76000,25200" -st "MOSI : OUT std_logic := '0' ;" +st "MOSI : OUT std_logic := '0' ; +" ) thePort (LogicalPort @@ -3097,5 +3136,6 @@ ) xt "44000,39600,61500,40400" -st "MISO : INOUT std_logic ;" +st "MISO : INOUT std_logic ; +" ) thePort (LogicalPort @@ -3144,5 +3184,6 @@ ) xt "44000,34800,61500,35600" -st "TRG_V : OUT std_logic ;" +st "TRG_V : OUT std_logic ; +" ) thePort (LogicalPort @@ -3189,5 +3230,6 @@ ) xt "44000,26800,61500,27600" -st "RS485_C_RE : OUT std_logic ;" +st "RS485_C_RE : OUT std_logic ; +" ) thePort (LogicalPort @@ -3234,5 +3276,6 @@ ) xt "44000,26000,61500,26800" -st "RS485_C_DE : OUT std_logic ;" +st "RS485_C_DE : OUT std_logic ; +" ) thePort (LogicalPort @@ -3279,5 +3322,6 @@ ) xt "44000,28400,61500,29200" -st "RS485_E_RE : OUT std_logic ;" +st "RS485_E_RE : OUT std_logic ; +" ) thePort (LogicalPort @@ -3324,5 +3368,6 @@ ) xt "44000,27600,61500,28400" -st "RS485_E_DE : OUT std_logic ;" +st "RS485_E_DE : OUT std_logic ; +" ) thePort (LogicalPort @@ -3379,5 +3424,6 @@ ) xt "44000,18800,76000,19600" -st "DENABLE : OUT std_logic := '0' ;" +st "DENABLE : OUT std_logic := '0' ; +" ) thePort (LogicalPort @@ -3425,5 +3471,6 @@ ) xt "44000,30000,61500,30800" -st "SRIN : OUT std_logic ;" +st "SRIN : OUT std_logic ; +" ) thePort (LogicalPort @@ -3470,5 +3517,6 @@ ) xt "44000,22800,61500,23600" -st "EE_CS : OUT std_logic ;" +st "EE_CS : OUT std_logic ; +" ) thePort (LogicalPort @@ -3525,5 +3573,6 @@ ) xt "44000,21200,82000,22000" -st "D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ;" +st "D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ; +" ) thePort (LogicalPort @@ -3582,5 +3631,6 @@ ) xt "44000,23600,82000,24400" -st "LED : OUT std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ;" +st "LED : OUT std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ; +" ) thePort (LogicalPort @@ -3628,5 +3678,6 @@ ) xt "44000,10000,61500,10800" -st "TEST_TRG : IN std_logic ;" +st "TEST_TRG : IN std_logic ; +" ) thePort (LogicalPort @@ -3671,5 +3722,6 @@ ) xt "44000,9200,71500,10000" -st "D_PLLLCK : IN std_logic_vector (3 DOWNTO 0) ;" +st "D_PLLLCK : IN std_logic_vector (3 DOWNTO 0) ; +" ) thePort (LogicalPort @@ -3726,5 +3778,6 @@ ) xt "44000,22000,82000,22800" -st "D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ;" +st "D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ; +" ) thePort (LogicalPort @@ -3761,9 +3814,19 @@ ) xt "27200,97500,32000,98500" -st "A1_T : (3:0)" +st "A1_T : (7:0)" ju 2 blo "32000,98300" tm "CptPortNameMgr" ) +t (Text +uid 3123,0 +va (VaSet +) +xt "25100,98500,32000,99500" +st "(OTHERS => '0')" +ju 2 +blo "32000,99300" +tm "InitValueDelayMgr" +) ) dt (MLText @@ -3772,6 +3835,7 @@ font "Courier New,8,0" ) -xt "44000,13200,71500,14000" -st "A1_T : OUT std_logic_vector (3 DOWNTO 0) ;" +xt "44000,13200,82000,14000" +st "A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ; +" ) thePort (LogicalPort @@ -3780,7 +3844,8 @@ n "A1_T" t "std_logic_vector" -b "(3 DOWNTO 0)" +b "(7 DOWNTO 0)" o 15 suid 66,0 +i "(OTHERS => '0')" ) ) @@ -3795,5 +3860,5 @@ lineWidth 2 ) -xt "15000,6000,33000,99000" +xt "15000,6000,33000,101000" ) oxt "15000,6000,33000,26000" @@ -3869,5 +3934,5 @@ bg "0,0,32768" ) -xt "36200,48000,45700,49000" +xt "36200,48000,45500,49000" st " by %user on %dd %month %year @@ -4452,5 +4517,5 @@ ) ) -lastUid 3076,0 +lastUid 3292,0 activeModelName "Symbol:CDM" ) Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd (revision 252) @@ -152,4 +152,13 @@ uid 8277,0 ) +(Instance +name "U_0" +duLibraryName "moduleware" +duName "mux" +elements [ +] +mwi 1 +uid 8562,0 +) ] libraryRefs [ @@ -359,5 +368,5 @@ (vvPair variable "time" -value "11:42:03" +value "14:21:30" ) (vvPair @@ -450,6 +459,7 @@ font "Courier New,8,0" ) -xt "-85000,84200,-41500,85000" -st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\"" +xt "-85000,86600,-41500,87400" +st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\" +" ) ) @@ -469,5 +479,6 @@ ) xt "-85000,47400,-45000,48200" -st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" +st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) +" ) ) @@ -487,5 +498,6 @@ ) xt "-85000,61800,-52500,62600" -st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0)" +st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0) +" ) ) @@ -504,6 +516,7 @@ font "Courier New,8,0" ) -xt "-85000,69000,-45000,69800" -st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)" +xt "-85000,71400,-45000,72200" +st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) +" ) ) @@ -522,6 +535,7 @@ font "Courier New,8,0" ) -xt "-85000,69800,-52500,70600" -st "SIGNAL ram_data : std_logic_vector(15 downto 0)" +xt "-85000,72200,-52500,73000" +st "SIGNAL ram_data : std_logic_vector(15 downto 0) +" ) ) @@ -541,5 +555,6 @@ ) xt "-85000,39800,-45000,40600" -st "wiz_reset : std_logic := '1'" +st "wiz_reset : std_logic := '1' +" ) ) @@ -559,5 +574,6 @@ ) xt "-85000,37400,-56500,38200" -st "wiz_addr : std_logic_vector(9 DOWNTO 0)" +st "wiz_addr : std_logic_vector(9 DOWNTO 0) +" ) ) @@ -577,5 +593,6 @@ ) xt "-85000,42200,-56000,43000" -st "wiz_data : std_logic_vector(15 DOWNTO 0)" +st "wiz_data : std_logic_vector(15 DOWNTO 0) +" ) ) @@ -595,5 +612,6 @@ ) xt "-85000,38200,-45000,39000" -st "wiz_cs : std_logic := '1'" +st "wiz_cs : std_logic := '1' +" ) ) @@ -613,5 +631,6 @@ ) xt "-85000,40600,-45000,41400" -st "wiz_wr : std_logic := '1'" +st "wiz_wr : std_logic := '1' +" ) ) @@ -631,5 +650,6 @@ ) xt "-85000,39000,-45000,39800" -st "wiz_rd : std_logic := '1'" +st "wiz_rd : std_logic := '1' +" ) ) @@ -648,5 +668,6 @@ ) xt "-85000,26200,-66500,27000" -st "wiz_int : std_logic" +st "wiz_int : std_logic +" ) ) @@ -2473,5 +2494,6 @@ ) xt "-85000,23800,-56500,24600" -st "board_id : std_logic_vector(3 downto 0)" +st "board_id : std_logic_vector(3 downto 0) +" ) ) @@ -2492,5 +2514,6 @@ ) xt "-85000,25400,-66500,26200" -st "trigger : std_logic" +st "trigger : std_logic +" ) ) @@ -3720,5 +3743,6 @@ ) xt "-85000,24600,-56500,25400" -st "crate_id : std_logic_vector(1 downto 0)" +st "crate_id : std_logic_vector(1 downto 0) +" ) ) @@ -3940,6 +3964,7 @@ font "Courier New,8,0" ) -xt "-85000,77000,-52500,77800" -st "SIGNAL trigger_id : std_logic_vector(47 downto 0)" +xt "-85000,79400,-52500,80200" +st "SIGNAL trigger_id : std_logic_vector(47 downto 0) +" ) ) @@ -3960,6 +3985,7 @@ font "Courier New,8,0" ) -xt "-85000,70600,-45000,71400" -st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" +xt "-85000,73000,-45000,73800" +st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) +" ) ) @@ -4766,6 +4792,7 @@ font "Courier New,8,0" ) -xt "-85000,78600,-62500,79400" -st "SIGNAL wiz_busy : std_logic" +xt "-85000,81000,-62500,81800" +st "SIGNAL wiz_busy : std_logic +" ) ) @@ -4785,6 +4812,7 @@ font "Courier New,8,0" ) -xt "-85000,81000,-41500,81800" -st "SIGNAL wiz_write_ea : std_logic := '0'" +xt "-85000,83400,-41500,84200" +st "SIGNAL wiz_write_ea : std_logic := '0' +" ) ) @@ -4805,6 +4833,7 @@ font "Courier New,8,0" ) -xt "-85000,83400,-35500,84200" -st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0')" +xt "-85000,85800,-35500,86600" +st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0') +" ) ) @@ -4826,6 +4855,7 @@ font "Courier New,8,0" ) -xt "-85000,80200,-35500,81000" -st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')" +xt "-85000,82600,-35500,83400" +st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0') +" ) ) @@ -4846,6 +4876,7 @@ font "Courier New,8,0" ) -xt "-85000,79400,-35500,80200" -st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0')" +xt "-85000,81800,-35500,82600" +st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0') +" ) ) @@ -4865,6 +4896,7 @@ font "Courier New,8,0" ) -xt "-85000,81800,-41500,82600" -st "SIGNAL wiz_write_end : std_logic := '0'" +xt "-85000,84200,-41500,85000" +st "SIGNAL wiz_write_end : std_logic := '0' +" ) ) @@ -4884,6 +4916,7 @@ font "Courier New,8,0" ) -xt "-85000,82600,-41500,83400" -st "SIGNAL wiz_write_header : std_logic := '0'" +xt "-85000,85000,-41500,85800" +st "SIGNAL wiz_write_header : std_logic := '0' +" ) ) @@ -4901,6 +4934,7 @@ font "Courier New,8,0" ) -xt "-85000,71400,-62500,72200" -st "SIGNAL ram_write_ea : std_logic" +xt "-85000,73800,-62500,74600" +st "SIGNAL ram_write_ea : std_logic +" ) ) @@ -4919,6 +4953,7 @@ font "Courier New,8,0" ) -xt "-85000,72200,-41500,73000" -st "SIGNAL ram_write_ready : std_logic := '0'" +xt "-85000,74600,-41500,75400" +st "SIGNAL ram_write_ready : std_logic := '0' +" ) ) @@ -4938,5 +4973,6 @@ ) xt "-85000,54600,-41500,55400" -st "SIGNAL config_start : std_logic := '0'" +st "SIGNAL config_start : std_logic := '0' +" ) ) @@ -4955,5 +4991,6 @@ ) xt "-85000,52200,-62500,53000" -st "SIGNAL config_ready : std_logic" +st "SIGNAL config_ready : std_logic +" ) ) @@ -4971,6 +5008,7 @@ font "Courier New,8,0" ) -xt "-85000,73800,-61000,74600" -st "SIGNAL roi_max : roi_max_type" +xt "-85000,76200,-61000,77000" +st "SIGNAL roi_max : roi_max_type +" ) ) @@ -4989,6 +5027,7 @@ font "Courier New,8,0" ) -xt "-85000,68200,-52500,69000" -st "SIGNAL package_length : std_logic_vector(15 downto 0)" +xt "-85000,70600,-52500,71400" +st "SIGNAL package_length : std_logic_vector(15 downto 0) +" ) ) @@ -5008,5 +5047,6 @@ ) xt "-85000,30200,-45000,31000" -st "adc_oeb : std_logic := '1'" +st "adc_oeb : std_logic := '1' +" ) ) @@ -5114,6 +5154,7 @@ font "Courier New,8,0" ) -xt "-85000,73000,-60000,73800" -st "SIGNAL roi_array : roi_array_type" +xt "-85000,75400,-60000,76200" +st "SIGNAL roi_array : roi_array_type +" ) ) @@ -5548,5 +5589,6 @@ ) xt "-85000,27000,-66500,27800" -st "CLK_25_PS : std_logic" +st "CLK_25_PS : std_logic +" ) ) @@ -5610,5 +5652,6 @@ ) xt "-85000,27800,-66500,28600" -st "CLK_50 : std_logic" +st "CLK_50 : std_logic +" ) ) @@ -5860,5 +5903,6 @@ ) xt "-85000,45000,-62500,45800" -st "SIGNAL CLK_25 : std_logic" +st "SIGNAL CLK_25 : std_logic +" ) ) @@ -5922,5 +5966,6 @@ ) xt "-85000,18200,-66500,19000" -st "CLK : std_logic" +st "CLK : std_logic +" ) ) @@ -5940,5 +5985,6 @@ ) xt "-85000,23000,-56500,23800" -st "adc_otr_array : std_logic_vector(3 DOWNTO 0)" +st "adc_otr_array : std_logic_vector(3 DOWNTO 0) +" ) ) @@ -5957,5 +6003,6 @@ ) xt "-85000,22200,-61000,23000" -st "adc_data_array : adc_data_array_type" +st "adc_data_array : adc_data_array_type +" ) ) @@ -6019,6 +6066,7 @@ font "Courier New,8,0" ) -xt "-85000,62600,-41500,63400" -st "SIGNAL drs_clk_en : std_logic := '0'" +xt "-85000,65000,-41500,65800" +st "SIGNAL drs_clk_en : std_logic := '0' +" ) ) @@ -6036,6 +6084,7 @@ font "Courier New,8,0" ) -xt "-85000,65000,-56500,65800" -st "SIGNAL drs_s_cell_array : drs_s_cell_array_type" +xt "-85000,67400,-56500,68200" +st "SIGNAL drs_s_cell_array : drs_s_cell_array_type +" ) ) @@ -6054,6 +6103,7 @@ font "Courier New,8,0" ) -xt "-85000,63400,-41500,64200" -st "SIGNAL drs_read_s_cell : std_logic := '0'" +xt "-85000,65800,-41500,66600" +st "SIGNAL drs_read_s_cell : std_logic := '0' +" ) ) @@ -6074,5 +6124,6 @@ ) xt "-85000,32600,-39000,33400" -st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" +st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') +" ) ) @@ -6092,5 +6143,6 @@ ) xt "-85000,33400,-45000,34200" -st "drs_dwrite : std_logic := '1'" +st "drs_dwrite : std_logic := '1' +" ) ) @@ -6108,5 +6160,5 @@ sl 0 ro 90 -xt "-28000,56625,-26500,57375" +xt "-39000,99625,-37500,100375" ) (Line @@ -6114,8 +6166,8 @@ sl 0 ro 90 -xt "-26500,57000,-26000,57000" +xt "-37500,100000,-37000,100000" pts [ -"-26000,57000" -"-26500,57000" +"-37000,100000" +"-37500,100000" ] ) @@ -6132,8 +6184,8 @@ va (VaSet ) -xt "-34900,56500,-29000,57500" +xt "-45900,99500,-40000,100500" st "drs_channel_id" ju 2 -blo "-29000,57300" +blo "-40000,100300" tm "WireNameMgr" ) @@ -6199,5 +6251,6 @@ ) xt "-85000,19000,-66500,19800" -st "SROUT_in_0 : std_logic" +st "SROUT_in_0 : std_logic +" ) ) @@ -6216,5 +6269,6 @@ ) xt "-85000,19800,-66500,20600" -st "SROUT_in_1 : std_logic" +st "SROUT_in_1 : std_logic +" ) ) @@ -6233,5 +6287,6 @@ ) xt "-85000,20600,-66500,21400" -st "SROUT_in_2 : std_logic" +st "SROUT_in_2 : std_logic +" ) ) @@ -6250,5 +6305,6 @@ ) xt "-85000,21400,-66500,22200" -st "SROUT_in_3 : std_logic" +st "SROUT_in_3 : std_logic +" ) ) @@ -6446,6 +6502,7 @@ font "Courier New,8,0" ) -xt "-85000,64200,-62500,65000" -st "SIGNAL drs_read_s_cell_ready : std_logic" +xt "-85000,66600,-62500,67400" +st "SIGNAL drs_read_s_cell_ready : std_logic +" ) ) @@ -6926,5 +6983,6 @@ ) xt "-85000,28600,-45000,29400" -st "RSRLOAD : std_logic := '0'" +st "RSRLOAD : std_logic := '0' +" ) ) @@ -6989,5 +7047,6 @@ ) xt "-85000,29400,-45000,30200" -st "SRCLK : std_logic := '0'" +st "SRCLK : std_logic := '0' +" ) ) @@ -7214,5 +7273,5 @@ t "std_logic_vector" b "(15 DOWNTO 0)" -o 12 +o 14 suid 5,0 ) @@ -7249,5 +7308,5 @@ n "roi_array" t "roi_array_type" -o 11 +o 13 suid 6,0 ) @@ -7464,4 +7523,77 @@ ) ) +*227 (CptPort +uid 8500,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8501,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92000,109625,92750,110375" +) +tg (CPTG +uid 8502,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8503,0 +va (VaSet +) +xt "83800,109500,91000,110500" +st "drs_address : (3:0)" +ju 2 +blo "91000,110300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 11 +suid 13,0 +) +) +) +*228 (CptPort +uid 8504,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8505,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92000,110625,92750,111375" +) +tg (CPTG +uid 8506,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8507,0 +va (VaSet +) +xt "83800,110500,91000,111500" +st "drs_address_mode" +ju 2 +blo "91000,111300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 12 +suid 14,0 +) +) +) ] shape (Rectangle @@ -7481,5 +7613,5 @@ stg "VerticalLayoutStrategy" textVec [ -*227 (Text +*229 (Text uid 5075,0 va (VaSet @@ -7491,5 +7623,5 @@ tm "BdLibraryNameMgr" ) -*228 (Text +*230 (Text uid 5076,0 va (VaSet @@ -7501,5 +7633,5 @@ tm "CptNameMgr" ) -*229 (Text +*231 (Text uid 5077,0 va (VaSet @@ -7547,5 +7679,5 @@ archFileType "UNKNOWN" ) -*230 (Net +*232 (Net uid 5088,0 decl (Decl @@ -7562,8 +7694,9 @@ ) xt "-85000,48200,-53000,49000" -st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0)" -) -) -*231 (Net +st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0) +" +) +) +*233 (Net uid 5096,0 decl (Decl @@ -7579,8 +7712,9 @@ ) xt "-85000,50600,-62500,51400" -st "SIGNAL config_data_valid : std_logic" -) -) -*232 (Net +st "SIGNAL config_data_valid : std_logic +" +) +) +*234 (Net uid 5104,0 decl (Decl @@ -7596,8 +7730,9 @@ ) xt "-85000,49000,-62500,49800" -st "SIGNAL config_busy : std_logic" -) -) -*233 (Net +st "SIGNAL config_busy : std_logic +" +) +) +*235 (Net uid 5112,0 decl (Decl @@ -7614,8 +7749,9 @@ ) xt "-85000,49800,-52500,50600" -st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0)" -) -) -*234 (Net +st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0) +" +) +) +*236 (Net uid 5120,0 decl (Decl @@ -7631,8 +7767,9 @@ ) xt "-85000,60200,-62500,61000" -st "SIGNAL config_wr_en : std_logic" -) -) -*235 (Net +st "SIGNAL config_wr_en : std_logic +" +) +) +*237 (Net uid 5128,0 decl (Decl @@ -7648,8 +7785,9 @@ ) xt "-85000,51400,-62500,52200" -st "SIGNAL config_rd_en : std_logic" -) -) -*236 (Net +st "SIGNAL config_rd_en : std_logic +" +) +) +*238 (Net uid 5144,0 decl (Decl @@ -7665,8 +7803,9 @@ ) xt "-85000,61000,-60000,61800" -st "SIGNAL dac_array : dac_array_type" -) -) -*237 (Net +st "SIGNAL dac_array : dac_array_type +" +) +) +*239 (Net uid 5194,0 decl (Decl @@ -7682,8 +7821,9 @@ ) xt "-85000,55400,-62500,56200" -st "SIGNAL config_start_cm : std_logic" -) -) -*238 (Net +st "SIGNAL config_start_cm : std_logic +" +) +) +*240 (Net uid 5196,0 decl (Decl @@ -7699,8 +7839,9 @@ ) xt "-85000,53000,-62500,53800" -st "SIGNAL config_ready_cm : std_logic" -) -) -*239 (Net +st "SIGNAL config_ready_cm : std_logic +" +) +) +*241 (Net uid 5220,0 decl (Decl @@ -7719,8 +7860,9 @@ ) xt "-85000,34200,-39000,35000" -st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" -) -) -*240 (Net +st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') +" +) +) +*242 (Net uid 5279,0 decl (Decl @@ -7736,9 +7878,10 @@ font "Courier New,8,0" ) -xt "-85000,74600,-41500,75400" -st "SIGNAL s_trigger : std_logic := '0'" -) -) -*241 (Net +xt "-85000,77000,-41500,77800" +st "SIGNAL s_trigger : std_logic := '0' +" +) +) +*243 (Net uid 5472,0 decl (Decl @@ -7753,9 +7896,10 @@ font "Courier New,8,0" ) -xt "-85000,76200,-62500,77000" -st "SIGNAL sensor_ready : std_logic" -) -) -*242 (Net +xt "-85000,78600,-62500,79400" +st "SIGNAL sensor_ready : std_logic +" +) +) +*244 (Net uid 5478,0 decl (Decl @@ -7770,9 +7914,10 @@ font "Courier New,8,0" ) -xt "-85000,75400,-58500,76200" -st "SIGNAL sensor_array : sensor_array_type" -) -) -*243 (Net +xt "-85000,77800,-58500,78600" +st "SIGNAL sensor_array : sensor_array_type +" +) +) +*245 (Net uid 5588,0 decl (Decl @@ -7788,8 +7933,9 @@ ) xt "-85000,53800,-62500,54600" -st "SIGNAL config_ready_spi : std_logic" -) -) -*244 (Net +st "SIGNAL config_ready_spi : std_logic +" +) +) +*246 (Net uid 5632,0 lang 10 @@ -7807,8 +7953,9 @@ ) xt "-85000,46600,-53000,47400" -st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0)" -) -) -*245 (Net +st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0) +" +) +) +*247 (Net uid 5640,0 decl (Decl @@ -7824,11 +7971,12 @@ ) xt "-85000,45800,-57500,46600" -st "SIGNAL adc_data_array_int : adc_data_array_type" -) -) -*246 (SaComponent +st "SIGNAL adc_data_array_int : adc_data_array_type +" +) +) +*248 (SaComponent uid 5678,0 optionalChildren [ -*247 (CptPort +*249 (CptPort uid 5658,0 ps "OnEdgeStrategy" @@ -7865,5 +8013,5 @@ ) ) -*248 (CptPort +*250 (CptPort uid 5662,0 ps "OnEdgeStrategy" @@ -7902,5 +8050,5 @@ ) ) -*249 (CptPort +*251 (CptPort uid 5666,0 ps "OnEdgeStrategy" @@ -7941,5 +8089,5 @@ ) ) -*250 (CptPort +*252 (CptPort uid 5670,0 ps "OnEdgeStrategy" @@ -7977,5 +8125,5 @@ ) ) -*251 (CptPort +*253 (CptPort uid 5674,0 ps "OnEdgeStrategy" @@ -8030,5 +8178,5 @@ stg "VerticalLayoutStrategy" textVec [ -*252 (Text +*254 (Text uid 5681,0 va (VaSet @@ -8040,5 +8188,5 @@ tm "BdLibraryNameMgr" ) -*253 (Text +*255 (Text uid 5682,0 va (VaSet @@ -8050,5 +8198,5 @@ tm "CptNameMgr" ) -*254 (Text +*256 (Text uid 5683,0 va (VaSet @@ -8099,5 +8247,5 @@ archFileType "UNKNOWN" ) -*255 (Net +*257 (Net uid 5743,0 decl (Decl @@ -8114,11 +8262,12 @@ ) xt "-85000,56200,-41500,57000" -st "SIGNAL config_start_spi : std_logic := '0'" -) -) -*256 (SaComponent +st "SIGNAL config_start_spi : std_logic := '0' +" +) +) +*258 (SaComponent uid 5793,0 optionalChildren [ -*257 (CptPort +*259 (CptPort uid 5753,0 ps "OnEdgeStrategy" @@ -8155,5 +8304,5 @@ ) ) -*258 (CptPort +*260 (CptPort uid 5761,0 ps "OnEdgeStrategy" @@ -8190,5 +8339,5 @@ ) ) -*259 (CptPort +*261 (CptPort uid 5765,0 ps "OnEdgeStrategy" @@ -8226,5 +8375,5 @@ ) ) -*260 (CptPort +*262 (CptPort uid 5769,0 ps "OnEdgeStrategy" @@ -8261,5 +8410,5 @@ ) ) -*261 (CptPort +*263 (CptPort uid 5773,0 ps "OnEdgeStrategy" @@ -8297,5 +8446,5 @@ ) ) -*262 (CptPort +*264 (CptPort uid 5777,0 ps "OnEdgeStrategy" @@ -8333,5 +8482,5 @@ ) ) -*263 (CptPort +*265 (CptPort uid 5781,0 ps "OnEdgeStrategy" @@ -8368,5 +8517,5 @@ ) ) -*264 (CptPort +*266 (CptPort uid 5785,0 ps "OnEdgeStrategy" @@ -8404,5 +8553,5 @@ ) ) -*265 (CptPort +*267 (CptPort uid 5789,0 ps "OnEdgeStrategy" @@ -8440,5 +8589,5 @@ ) ) -*266 (CptPort +*268 (CptPort uid 5986,0 ps "OnEdgeStrategy" @@ -8477,5 +8626,5 @@ ) ) -*267 (CptPort +*269 (CptPort uid 6154,0 ps "OnEdgeStrategy" @@ -8513,5 +8662,5 @@ ) ) -*268 (CptPort +*270 (CptPort uid 6317,0 ps "OnEdgeStrategy" @@ -8567,5 +8716,5 @@ stg "VerticalLayoutStrategy" textVec [ -*269 (Text +*271 (Text uid 5796,0 va (VaSet @@ -8577,5 +8726,5 @@ tm "BdLibraryNameMgr" ) -*270 (Text +*272 (Text uid 5797,0 va (VaSet @@ -8587,5 +8736,5 @@ tm "CptNameMgr" ) -*271 (Text +*273 (Text uid 5798,0 va (VaSet @@ -8633,5 +8782,5 @@ archFileType "UNKNOWN" ) -*272 (Net +*274 (Net uid 5811,0 decl (Decl @@ -8647,8 +8796,9 @@ ) xt "-85000,35800,-66500,36600" -st "sclk : std_logic" -) -) -*273 (Net +st "sclk : std_logic +" +) +) +*275 (Net uid 5819,0 decl (Decl @@ -8666,8 +8816,9 @@ ) xt "-85000,41400,-66500,42200" -st "sio : std_logic" -) -) -*274 (Net +st "sio : std_logic +" +) +) +*276 (Net uid 5827,0 decl (Decl @@ -8683,8 +8834,9 @@ ) xt "-85000,31000,-66500,31800" -st "dac_cs : std_logic" -) -) -*275 (Net +st "dac_cs : std_logic +" +) +) +*277 (Net uid 5835,0 decl (Decl @@ -8701,8 +8853,9 @@ ) xt "-85000,36600,-56500,37400" -st "sensor_cs : std_logic_vector(3 DOWNTO 0)" -) -) -*276 (PortIoOut +st "sensor_cs : std_logic_vector(3 DOWNTO 0) +" +) +) +*278 (PortIoOut uid 5843,0 shape (CompositeShape @@ -8749,5 +8902,5 @@ ) ) -*277 (PortIoInOut +*279 (PortIoInOut uid 5849,0 shape (CompositeShape @@ -8794,5 +8947,5 @@ ) ) -*278 (PortIoOut +*280 (PortIoOut uid 5855,0 shape (CompositeShape @@ -8839,5 +8992,5 @@ ) ) -*279 (PortIoOut +*281 (PortIoOut uid 5861,0 shape (CompositeShape @@ -8884,5 +9037,5 @@ ) ) -*280 (Net +*282 (Net uid 5948,0 decl (Decl @@ -8898,9 +9051,10 @@ font "Courier New,8,0" ) -xt "-85000,67400,-41500,68200" -st "SIGNAL new_config : std_logic := '0'" -) -) -*281 (Net +xt "-85000,69800,-41500,70600" +st "SIGNAL new_config : std_logic := '0' +" +) +) +*283 (Net uid 5960,0 decl (Decl @@ -8916,8 +9070,9 @@ ) xt "-85000,57000,-62500,57800" -st "SIGNAL config_started : std_logic" -) -) -*282 (Net +st "SIGNAL config_started : std_logic +" +) +) +*284 (Net uid 6012,0 decl (Decl @@ -8934,8 +9089,9 @@ ) xt "-85000,59400,-41500,60200" -st "SIGNAL config_started_spi : std_logic := '0'" -) -) -*283 (Net +st "SIGNAL config_started_spi : std_logic := '0' +" +) +) +*285 (Net uid 6014,0 decl (Decl @@ -8952,8 +9108,9 @@ ) xt "-85000,57800,-41500,58600" -st "SIGNAL config_started_cu : std_logic := '0'" -) -) -*284 (Net +st "SIGNAL config_started_cu : std_logic := '0' +" +) +) +*286 (Net uid 6016,0 decl (Decl @@ -8969,8 +9126,9 @@ ) xt "-85000,58600,-62500,59400" -st "SIGNAL config_started_mm : std_logic" -) -) -*285 (Net +st "SIGNAL config_started_mm : std_logic +" +) +) +*287 (Net uid 6158,0 decl (Decl @@ -8987,8 +9145,9 @@ ) xt "-85000,35000,-45000,35800" -st "mosi : std_logic := '0'" -) -) -*286 (PortIoOut +st "mosi : std_logic := '0' +" +) +) +*288 (PortIoOut uid 6166,0 shape (CompositeShape @@ -9035,5 +9194,5 @@ ) ) -*287 (Net +*289 (Net uid 6360,0 decl (Decl @@ -9052,8 +9211,9 @@ ) xt "-85000,31800,-31500,32600" -st "denable : std_logic := '0' -- default domino wave off" -) -) -*288 (PortIoOut +st "denable : std_logic := '0' -- default domino wave off +" +) +) +*290 (PortIoOut uid 6368,0 shape (CompositeShape @@ -9099,5 +9259,5 @@ ) ) -*289 (Net +*291 (Net uid 6450,0 decl (Decl @@ -9113,15 +9273,16 @@ font "Courier New,8,0" ) -xt "-85000,66600,-41500,67400" -st "SIGNAL dwrite_enable : std_logic := '1'" -) -) -*290 (MWC +xt "-85000,69000,-41500,69800" +st "SIGNAL dwrite_enable : std_logic := '1' +" +) +) +*292 (MWC uid 6529,0 optionalChildren [ -*291 (CptPort +*293 (CptPort uid 6501,0 optionalChildren [ -*292 (Line +*294 (Line uid 6505,0 layer 5 @@ -9136,5 +9297,5 @@ ] ) -*293 (Property +*295 (Property uid 6506,0 pclass "_MW_GEOM_" @@ -9181,8 +9342,8 @@ ) ) -*294 (CptPort +*296 (CptPort uid 6507,0 optionalChildren [ -*295 (Line +*297 (Line uid 6511,0 layer 5 @@ -9236,8 +9397,8 @@ ) ) -*296 (CptPort +*298 (CptPort uid 6512,0 optionalChildren [ -*297 (Line +*299 (Line uid 6516,0 layer 5 @@ -9291,8 +9452,8 @@ ) ) -*298 (CommentGraphic +*300 (CommentGraphic uid 6517,0 optionalChildren [ -*299 (Property +*301 (Property uid 6519,0 pclass "_MW_GEOM_" @@ -9318,8 +9479,8 @@ oxt "11000,10000,11000,10000" ) -*300 (CommentGraphic +*302 (CommentGraphic uid 6520,0 optionalChildren [ -*301 (Property +*303 (Property uid 6522,0 pclass "_MW_GEOM_" @@ -9345,8 +9506,8 @@ oxt "11000,6000,11000,6000" ) -*302 (Grouping +*304 (Grouping uid 6523,0 optionalChildren [ -*303 (CommentGraphic +*305 (CommentGraphic uid 6525,0 shape (PolyLine2D @@ -9369,5 +9530,5 @@ oxt "9000,6000,11000,10000" ) -*304 (CommentGraphic +*306 (CommentGraphic uid 6527,0 shape (Arc2D @@ -9422,5 +9583,5 @@ stg "VerticalLayoutStrategy" textVec [ -*305 (Text +*307 (Text uid 6532,0 va (VaSet @@ -9432,5 +9593,5 @@ blo "3500,59300" ) -*306 (Text +*308 (Text uid 6533,0 va (VaSet @@ -9441,5 +9602,5 @@ blo "3500,60300" ) -*307 (Text +*309 (Text uid 6534,0 va (VaSet @@ -9486,5 +9647,5 @@ ) ) -*308 (Net +*310 (Net uid 6544,0 decl (Decl @@ -9500,12 +9661,13 @@ font "Courier New,8,0" ) -xt "-85000,65800,-41500,66600" -st "SIGNAL dwrite : std_logic := '1'" -) -) -*309 (SaComponent +xt "-85000,68200,-41500,69000" +st "SIGNAL dwrite : std_logic := '1' +" +) +) +*311 (SaComponent uid 8277,0 optionalChildren [ -*310 (CptPort +*312 (CptPort uid 8246,0 ps "OnEdgeStrategy" @@ -9544,5 +9706,5 @@ ) ) -*311 (CptPort +*313 (CptPort uid 8250,0 ps "OnEdgeStrategy" @@ -9582,5 +9744,5 @@ ) ) -*312 (CptPort +*314 (CptPort uid 8254,0 ps "OnEdgeStrategy" @@ -9620,5 +9782,5 @@ ) ) -*313 (CptPort +*315 (CptPort uid 8258,0 ps "OnEdgeStrategy" @@ -9658,5 +9820,5 @@ ) ) -*314 (CptPort +*316 (CptPort uid 8262,0 ps "OnEdgeStrategy" @@ -9696,5 +9858,5 @@ ) ) -*315 (CptPort +*317 (CptPort uid 8266,0 ps "OnEdgeStrategy" @@ -9735,5 +9897,5 @@ ) ) -*316 (CptPort +*318 (CptPort uid 8270,0 ps "OnEdgeStrategy" @@ -9792,5 +9954,5 @@ stg "VerticalLayoutStrategy" textVec [ -*317 (Text +*319 (Text uid 8280,0 va (VaSet @@ -9802,5 +9964,5 @@ tm "BdLibraryNameMgr" ) -*318 (Text +*320 (Text uid 8281,0 va (VaSet @@ -9812,5 +9974,5 @@ tm "CptNameMgr" ) -*319 (Text +*321 (Text uid 8282,0 va (VaSet @@ -9860,5 +10022,5 @@ archFileType "UNKNOWN" ) -*320 (Net +*322 (Net uid 8414,0 lang 2 @@ -9874,9 +10036,596 @@ font "Courier New,8,0" ) -xt "-85000,77800,-62500,78600" -st "SIGNAL wiz_ack : std_logic" -) -) -*321 (Wire +xt "-85000,80200,-62500,81000" +st "SIGNAL wiz_ack : std_logic +" +) +) +*323 (Net +uid 8508,0 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 82 +suid 184,0 +i "(others => '0')" +) +declText (MLText +uid 8509,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,62600,-35500,63400" +st "SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0') +" +) +) +*324 (Net +uid 8516,0 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 83 +suid 185,0 +) +declText (MLText +uid 8517,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,63400,-62500,64200" +st "SIGNAL drs_address_mode : std_logic +" +) +) +*325 (MWC +uid 8562,0 +optionalChildren [ +*326 (CptPort +uid 8524,0 +optionalChildren [ +*327 (Line +uid 8528,0 +layer 5 +sl 0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "-29999,101000,-29000,101000" +pts [ +"-29000,101000" +"-29999,101000" +] +) +] +ps "OnEdgeStrategy" +shape (Triangle +uid 8525,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,65535" +) +xt "-29000,100625,-28250,101375" +) +tg (CPTG +uid 8526,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8527,0 +sl 0 +va (VaSet +isHidden 1 +font "arial,8,0" +) +xt "-98971,288551,-97171,289551" +st "din0" +ju 2 +blo "-97171,289351" +) +s (Text +uid 8571,0 +sl 0 +va (VaSet +font "arial,8,0" +) +xt "-97171,289551,-97171,289551" +ju 2 +blo "-97171,289551" +) +) +thePort (LogicalPort +decl (Decl +n "din0" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 84 +suid 1,0 +i "(others => '0')" +) +) +) +*328 (CptPort +uid 8529,0 +optionalChildren [ +*329 (Line +uid 8533,0 +layer 5 +sl 0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "-33000,100000,-31999,100000" +pts [ +"-33000,100000" +"-31999,100000" +] +) +*330 (Property +uid 8534,0 +pclass "_MW_GEOM_" +pname "fixed" +ptn "String" +) +] +ps "OnEdgeStrategy" +shape (Triangle +uid 8530,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,65535" +) +xt "-33750,99625,-33000,100375" +) +tg (CPTG +uid 8531,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8532,0 +sl 0 +va (VaSet +isHidden 1 +font "arial,8,0" +) +xt "-100999,287527,-99199,288527" +st "dout" +blo "-100999,288327" +) +s (Text +uid 8572,0 +sl 0 +va (VaSet +font "arial,8,0" +) +xt "-100999,288527,-100999,288527" +blo "-100999,288527" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "dout" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 19 +suid 2,0 +i "(others => '0')" +) +) +) +*331 (CptPort +uid 8535,0 +optionalChildren [ +*332 (Line +uid 8539,0 +layer 5 +sl 0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "-29999,99000,-29000,99000" +pts [ +"-29000,99000" +"-29999,99000" +] +) +] +ps "OnEdgeStrategy" +shape (Triangle +uid 8536,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,65535" +) +xt "-29000,98625,-28250,99375" +) +tg (CPTG +uid 8537,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8538,0 +sl 0 +va (VaSet +isHidden 1 +font "arial,8,0" +) +xt "-98971,286503,-97171,287503" +st "din1" +ju 2 +blo "-97171,287303" +) +s (Text +uid 8573,0 +sl 0 +va (VaSet +font "arial,8,0" +) +xt "-97171,287503,-97171,287503" +ju 2 +blo "-97171,287503" +) +) +thePort (LogicalPort +decl (Decl +n "din1" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 82 +suid 3,0 +i "(others => '0')" +) +) +) +*333 (CptPort +uid 8540,0 +optionalChildren [ +*334 (Line +uid 8544,0 +layer 5 +sl 0 +va (VaSet +vasetType 3 +) +xt "-31000,101333,-31000,103000" +pts [ +"-31000,103000" +"-31000,101333" +] +) +] +ps "OnEdgeStrategy" +shape (Triangle +uid 8541,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,65535" +) +xt "-31375,103000,-30625,103750" +) +tg (CPTG +uid 8542,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8543,0 +sl 0 +ro 270 +va (VaSet +isHidden 1 +font "arial,8,0" +) +xt "-99473,289183,-98473,290583" +st "sel" +blo "-98673,290583" +) +s (Text +uid 8574,0 +sl 0 +ro 270 +va (VaSet +font "arial,8,0" +) +xt "-98473,290583,-98473,290583" +blo "-98473,290583" +) +) +thePort (LogicalPort +decl (Decl +n "sel" +t "std_logic" +o 83 +suid 4,0 +) +) +) +*335 (CommentGraphic +uid 8545,0 +shape (CustomPolygon +pts [ +"-30000,102000" +"-32000,100666" +"-32000,99334" +"-30000,98000" +"-30000,102000" +] +uid 8546,0 +layer 0 +sl 0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +bg "0,65535,65535" +lineColor "26368,26368,26368" +) +xt "-32000,98000,-30000,102000" +) +oxt "7000,7000,9000,11000" +) +*336 (CommentGraphic +uid 8547,0 +optionalChildren [ +*337 (Property +uid 8549,0 +pclass "_MW_GEOM_" +pname "expand" +ptn "String" +) +] +shape (PolyLine2D +pts [ +"-30000,98000" +"-30000,98000" +] +uid 8548,0 +layer 0 +sl 0 +va (VaSet +vasetType 1 +transparent 1 +fg "49152,49152,49152" +) +xt "-30000,98000,-30000,98000" +) +oxt "9000,7000,9000,7000" +) +*338 (CommentGraphic +uid 8550,0 +optionalChildren [ +*339 (Property +uid 8552,0 +pclass "_MW_GEOM_" +pname "expand" +ptn "String" +) +] +shape (PolyLine2D +pts [ +"-30000,102000" +"-30000,102000" +] +uid 8551,0 +layer 0 +sl 0 +va (VaSet +vasetType 1 +transparent 1 +fg "49152,49152,49152" +) +xt "-30000,102000,-30000,102000" +) +oxt "9000,11000,9000,11000" +) +*340 (CommentText +uid 8553,0 +shape (Rectangle +uid 8554,0 +sl 0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +lineColor "65535,65535,65535" +lineWidth -1 +) +xt "-32000,100000,-30000,101506" +) +oxt "7000,9000,9000,10506" +text (MLText +uid 8555,0 +sl 0 +va (VaSet +font "arial,8,0" +) +xt "-31800,100200,-30600,101200" +st " +Lo +" +tm "CommentText" +wrapOption 3 +visibleHeight 1506 +visibleWidth 2000 +) +) +*341 (CommentText +uid 8556,0 +shape (Rectangle +uid 8557,0 +layer 8 +sl 0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +lineColor "65535,65535,65535" +lineWidth -1 +) +xt "-32000,98000,-30002,99556" +) +oxt "7000,7000,8998,8556" +text (MLText +uid 8558,0 +sl 0 +va (VaSet +font "arial,8,0" +) +xt "-31800,98200,-30600,99200" +st " +Hi +" +tm "CommentText" +wrapOption 3 +visibleHeight 1556 +visibleWidth 1998 +) +) +*342 (CommentText +uid 8559,0 +shape (Rectangle +uid 8560,0 +layer 0 +sl 0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +lineColor "65535,65535,65535" +lineWidth -1 +) +xt "-32111,99517,-30111,100517" +) +oxt "6889,8517,8889,9517" +text (MLText +uid 8561,0 +sl 0 +va (VaSet +font "arial,8,0" +) +xt "-31911,99717,-30211,100717" +st " +mux +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 2000 +) +) +] +shape (Rectangle +uid 8563,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +lineWidth -1 +) +xt "-33000,97000,-29000,103000" +fos 1 +) +showPorts 0 +oxt "6000,6000,10000,12000" +ttg (MlTextGroup +uid 8564,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*343 (Text +uid 8565,0 +va (VaSet +isHidden 1 +font "arial,8,0" +) +xt "-30650,102100,-25850,103100" +st "moduleware" +blo "-30650,102900" +) +*344 (Text +uid 8566,0 +va (VaSet +font "arial,8,0" +) +xt "-30650,103100,-28950,104100" +st "mux" +blo "-30650,103900" +) +*345 (Text +uid 8567,0 +va (VaSet +font "arial,8,0" +) +xt "-30650,104100,-28850,105100" +st "U_0" +blo "-30650,104900" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 8568,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 8569,0 +text (MLText +uid 8570,0 +va (VaSet +font "arial,8,0" +) +xt "-36000,79400,-36000,79400" +) +header "" +) +elements [ +] +) +sed 1 +awe 1 +portVis (PortSigDisplay +disp 1 +sN 0 +sTC 0 +selT 0 +) +prms (Property +pclass "params" +pname "params" +ptn "String" +) +de 1 +visOptions (mwParamsVisibilityOptions +) +) +*346 (Net +uid 8583,0 +decl (Decl +n "drs_channel_internal" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 84 +suid 187,0 +i "(others => '0')" +) +declText (MLText +uid 8584,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,64200,-35500,65000" +st "SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0') +" +) +) +*347 (Wire uid 322,0 shape (OrthoPolyLine @@ -9894,5 +10643,5 @@ ) start &26 -end &313 +end &315 sat 32 eat 32 @@ -9917,5 +10666,5 @@ on &2 ) -*322 (Wire +*348 (Wire uid 328,0 shape (OrthoPolyLine @@ -9933,5 +10682,5 @@ ) start &25 -end &312 +end &314 sat 32 eat 32 @@ -9956,5 +10705,5 @@ on &3 ) -*323 (Wire +*349 (Wire uid 334,0 shape (OrthoPolyLine @@ -9972,5 +10721,5 @@ ) start &24 -end &311 +end &313 sat 32 eat 32 @@ -9995,5 +10744,5 @@ on &4 ) -*324 (Wire +*350 (Wire uid 364,0 shape (OrthoPolyLine @@ -10012,5 +10761,5 @@ ) start &79 -end &315 +end &317 sat 32 eat 32 @@ -10035,5 +10784,5 @@ on &5 ) -*325 (Wire +*351 (Wire uid 370,0 shape (OrthoPolyLine @@ -10052,5 +10801,5 @@ ) start &78 -end &316 +end &318 sat 32 eat 32 @@ -10075,5 +10824,5 @@ on &6 ) -*326 (Wire +*352 (Wire uid 376,0 shape (OrthoPolyLine @@ -10113,5 +10862,5 @@ on &7 ) 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(OrthoPolyLine @@ -10555,5 +11304,5 @@ on &109 ) -*339 (Wire +*365 (Wire uid 2470,0 shape (OrthoPolyLine @@ -10592,5 +11341,5 @@ on &132 ) -*340 (Wire +*366 (Wire uid 2476,0 shape (OrthoPolyLine @@ -10629,5 +11378,5 @@ on &133 ) -*341 (Wire +*367 (Wire uid 2482,0 shape (OrthoPolyLine @@ -10668,5 +11417,5 @@ on &134 ) -*342 (Wire +*368 (Wire uid 2488,0 shape (OrthoPolyLine @@ -10707,5 +11456,5 @@ on &135 ) -*343 (Wire +*369 (Wire uid 2494,0 shape (OrthoPolyLine @@ -10746,5 +11495,5 @@ on &136 ) -*344 (Wire +*370 (Wire uid 2500,0 shape (OrthoPolyLine @@ -10783,5 +11532,5 @@ on &137 ) -*345 (Wire +*371 (Wire uid 2506,0 shape (OrthoPolyLine @@ -10820,5 +11569,5 @@ on &138 ) -*346 (Wire +*372 (Wire uid 2576,0 shape (OrthoPolyLine @@ -10858,5 +11607,5 @@ on &139 ) -*347 (Wire +*373 (Wire uid 2582,0 shape (OrthoPolyLine @@ -10896,5 +11645,5 @@ on &140 ) -*348 (Wire +*374 (Wire uid 2588,0 shape (OrthoPolyLine @@ -10935,5 +11684,5 @@ on &141 ) -*349 (Wire +*375 (Wire uid 2594,0 shape (OrthoPolyLine @@ -10973,5 +11722,5 @@ on &142 ) -*350 (Wire +*376 (Wire uid 2600,0 shape (OrthoPolyLine @@ -11011,5 +11760,5 @@ on &143 ) -*351 (Wire +*377 (Wire uid 2642,0 shape (OrthoPolyLine @@ -11051,5 +11800,5 @@ on &144 ) -*352 (Wire +*378 (Wire uid 2778,0 shape (OrthoPolyLine @@ -11089,5 +11838,5 @@ on &145 ) -*353 (Wire +*379 (Wire uid 2786,0 shape (OrthoPolyLine @@ -11104,5 +11853,5 @@ ) start &147 -end &250 +end &252 sat 32 eat 32 @@ -11129,5 +11878,5 @@ on &176 ) -*354 (Wire +*380 (Wire uid 2876,0 shape (OrthoPolyLine @@ -11143,5 +11892,5 @@ ] ) -start &335 +start &361 end &103 es 0 @@ -11167,8 +11916,8 @@ on &65 ) -*355 (Wire +*381 (Wire uid 3888,0 optionalChildren [ -*356 (BdJunction +*382 (BdJunction uid 4230,0 ps "OnConnectorStrategy" @@ -11182,5 +11931,5 @@ ) ) -*357 (BdJunction +*383 (BdJunction uid 4244,0 ps "OnConnectorStrategy" @@ -11233,5 +11982,5 @@ on &164 ) -*358 (Wire +*384 (Wire uid 3984,0 shape (OrthoPolyLine @@ -11274,5 +12023,5 @@ on &162 ) -*359 (Wire +*385 (Wire uid 4042,0 shape (OrthoPolyLine @@ -11312,5 +12061,5 @@ on &175 ) -*360 (Wire +*386 (Wire uid 4226,0 shape (OrthoPolyLine @@ -11328,5 +12077,5 @@ ) start &174 -end &356 +end &382 sat 32 eat 32 @@ -11352,5 +12101,5 @@ on &164 ) -*361 (Wire +*387 (Wire uid 4240,0 shape (OrthoPolyLine @@ -11367,6 +12116,6 @@ ] ) -start &314 -end &357 +start &316 +end &383 sat 32 eat 32 @@ -11391,5 +12140,5 @@ on &164 ) -*362 (Wire +*388 (Wire uid 4272,0 shape (OrthoPolyLine @@ -11405,5 +12154,5 @@ ) start &178 -end &247 +end &249 sat 32 eat 32 @@ -11429,5 +12178,5 @@ on &177 ) -*363 (Wire +*389 (Wire uid 4401,0 shape (OrthoPolyLine @@ -11465,5 +12214,5 @@ on &179 ) -*364 (Wire +*390 (Wire uid 4407,0 shape (OrthoPolyLine @@ -11501,5 +12250,5 @@ on &180 ) -*365 (Wire +*391 (Wire uid 4419,0 shape (OrthoPolyLine @@ -11537,5 +12286,5 @@ on &181 ) -*366 (Wire +*392 (Wire uid 4537,0 shape (OrthoPolyLine @@ -11545,11 +12294,11 @@ lineWidth 2 ) -xt "-26000,57000,18250,57000" +xt "-37000,100000,-33000,100000" pts [ -"18250,57000" -"-26000,57000" -] -) -start &39 +"-33000,100000" +"-37000,100000" +] +) +start &328 end &184 sat 32 @@ -11569,7 +12318,7 @@ isHidden 1 ) -xt "-20000,56000,-14100,57000" +xt "-71000,99000,-65100,100000" st "drs_channel_id" -blo "-20000,56800" +blo "-71000,99800" tm "WireNameMgr" ) @@ -11577,5 +12326,5 @@ on &182 ) -*367 (Wire +*393 (Wire uid 4545,0 shape (OrthoPolyLine @@ -11590,5 +12339,5 @@ ] ) -start &291 +start &293 end &185 sat 32 @@ -11614,5 +12363,5 @@ on &183 ) -*368 (Wire +*394 (Wire uid 4671,0 shape (OrthoPolyLine @@ -11652,5 +12401,5 @@ on &186 ) -*369 (Wire +*395 (Wire uid 4679,0 shape (OrthoPolyLine @@ -11690,5 +12439,5 @@ on &187 ) -*370 (Wire +*396 (Wire uid 4687,0 shape (OrthoPolyLine @@ -11728,5 +12477,5 @@ on &188 ) -*371 (Wire +*397 (Wire uid 4695,0 shape (OrthoPolyLine @@ -11766,5 +12515,5 @@ on &189 ) -*372 (Wire +*398 (Wire uid 4743,0 shape (OrthoPolyLine @@ -11802,8 +12551,8 @@ on &194 ) -*373 (Wire +*399 (Wire uid 4757,0 optionalChildren [ -*374 (BdJunction +*400 (BdJunction uid 6076,0 ps "OnConnectorStrategy" @@ -11833,5 +12582,5 @@ ) start &196 -end *375 (BdJunction +end *401 (BdJunction uid 6080,0 ps "OnConnectorStrategy" @@ -11867,5 +12616,5 @@ on &173 ) -*376 (Wire +*402 (Wire uid 4948,0 shape (OrthoPolyLine @@ -11905,5 +12654,5 @@ on &210 ) -*377 (Wire +*403 (Wire uid 4962,0 shape (OrthoPolyLine @@ -11943,5 +12692,5 @@ on &212 ) -*378 (Wire +*404 (Wire uid 5090,0 shape (OrthoPolyLine @@ -11980,7 +12729,7 @@ ) ) -on &230 -) -*379 (Wire +on &232 +) +*405 (Wire uid 5098,0 shape (OrthoPolyLine @@ -12014,7 +12763,7 @@ ) ) -on &231 -) -*380 (Wire +on &233 +) +*406 (Wire uid 5106,0 shape (OrthoPolyLine @@ -12051,7 +12800,7 @@ ) ) -on &232 -) -*381 (Wire +on &234 +) +*407 (Wire uid 5114,0 shape (OrthoPolyLine @@ -12090,7 +12839,7 @@ ) ) -on &233 -) -*382 (Wire +on &235 +) +*408 (Wire uid 5122,0 shape (OrthoPolyLine @@ -12127,7 +12876,7 @@ ) ) -on &234 -) -*383 (Wire +on &236 +) +*409 (Wire uid 5130,0 shape (OrthoPolyLine @@ -12164,10 +12913,10 @@ ) ) -on &235 -) -*384 (Wire +on &237 +) +*410 (Wire uid 5138,0 optionalChildren [ -*385 (BdJunction +*411 (BdJunction uid 5400,0 ps "OnConnectorStrategy" @@ -12219,5 +12968,5 @@ on &148 ) -*386 (Wire +*412 (Wire uid 5146,0 shape (OrthoPolyLine @@ -12233,5 +12982,5 @@ ) start &222 -end &258 +end &260 es 0 sat 32 @@ -12253,7 +13002,7 @@ ) ) -on &236 -) -*387 (Wire +on &238 +) +*413 (Wire uid 5168,0 shape (OrthoPolyLine @@ -12268,5 +13017,5 @@ ] ) -start &385 +start &411 end &125 sat 32 @@ -12291,5 +13040,5 @@ on &148 ) -*388 (Wire +*414 (Wire uid 5184,0 shape (OrthoPolyLine @@ -12326,7 +13075,7 @@ ) ) -on &237 -) -*389 (Wire +on &239 +) +*415 (Wire uid 5190,0 shape (OrthoPolyLine @@ -12363,7 +13112,7 @@ ) ) -on &238 -) -*390 (Wire +on &240 +) +*416 (Wire uid 5222,0 shape (OrthoPolyLine @@ -12403,7 +13152,7 @@ ) ) -on &239 -) -*391 (Wire +on &241 +) +*417 (Wire uid 5281,0 shape (OrthoPolyLine @@ -12441,7 +13190,7 @@ ) ) -on &240 -) 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-12680,7 +13429,7 @@ ) ) -on &245 -) -*399 (Wire +on &247 +) +*425 (Wire uid 5634,0 shape (OrthoPolyLine @@ -12697,5 +13446,5 @@ ) start &38 -end &249 +end &251 sat 32 eat 32 @@ -12718,7 +13467,7 @@ ) ) -on &244 -) -*400 (Wire +on &246 +) +*426 (Wire uid 5646,0 shape (OrthoPolyLine @@ -12734,5 +13483,5 @@ ] ) -end &251 +end &253 sat 16 eat 32 @@ -12756,5 +13505,5 @@ on &162 ) -*401 (Wire +*427 (Wire uid 5745,0 shape (OrthoPolyLine @@ -12772,5 +13521,5 @@ ) start &54 -end &260 +end &262 sat 32 eat 32 @@ -12792,7 +13541,7 @@ ) ) -on &255 -) -*402 (Wire +on &257 +) +*428 (Wire uid 5805,0 shape (OrthoPolyLine @@ -12807,5 +13556,5 @@ ] ) -end &265 +end &267 sat 16 eat 32 @@ -12828,5 +13577,5 @@ on &164 ) -*403 (Wire +*429 (Wire uid 5813,0 shape (OrthoPolyLine @@ -12841,6 +13590,6 @@ ] ) -start &257 -end &276 +start &259 +end &278 sat 32 eat 32 @@ -12864,7 +13613,7 @@ ) ) -on &272 -) -*404 (Wire +on &274 +) +*430 (Wire uid 5821,0 shape (OrthoPolyLine @@ -12879,6 +13628,6 @@ ] ) -start &268 -end &277 +start &270 +end &279 sat 32 eat 32 @@ -12902,7 +13651,7 @@ ) ) -on &273 -) -*405 (Wire +on &275 +) +*431 (Wire uid 5829,0 shape (OrthoPolyLine @@ -12917,6 +13666,6 @@ ] ) -start &263 -end &278 +start &265 +end &280 sat 32 eat 32 @@ -12940,7 +13689,7 @@ ) ) -on &274 -) -*406 (Wire +on &276 +) +*432 (Wire uid 5837,0 shape (OrthoPolyLine @@ -12956,6 +13705,6 @@ ] ) -start &264 -end &279 +start &266 +end &281 sat 32 eat 32 @@ -12980,7 +13729,7 @@ ) ) -on &275 -) -*407 (Wire +on &277 +) +*433 (Wire uid 5950,0 shape (OrthoPolyLine @@ -13018,7 +13767,7 @@ ) ) -on &280 -) -*408 (Wire +on &282 +) +*434 (Wire uid 5962,0 shape (OrthoPolyLine @@ -13056,7 +13805,7 @@ ) ) -on &281 -) -*409 (Wire +on &283 +) +*435 (Wire uid 6002,0 shape (OrthoPolyLine @@ -13094,7 +13843,7 @@ ) ) -on &283 -) -*410 (Wire +on &285 +) +*436 (Wire uid 6008,0 shape (OrthoPolyLine @@ -13111,5 +13860,5 @@ ] ) -start &266 +start &268 end &59 sat 32 @@ -13132,7 +13881,7 @@ ) ) -on &282 -) -*411 (Wire +on &284 +) +*437 (Wire uid 6018,0 shape (OrthoPolyLine @@ -13170,7 +13919,7 @@ ) ) -on &284 -) -*412 (Wire +on &286 +) +*438 (Wire uid 6064,0 shape (OrthoPolyLine @@ -13205,7 +13954,7 @@ ) ) -on &236 -) -*413 (Wire +on &238 +) +*439 (Wire uid 6072,0 shape (OrthoPolyLine @@ -13223,5 +13972,5 @@ ) start &167 -end &374 +end &400 sat 32 eat 32 @@ -13246,5 +13995,5 @@ on &173 ) -*414 (Wire +*440 (Wire uid 6082,0 shape (OrthoPolyLine @@ -13262,5 +14011,5 @@ ) start &112 -end &397 +end &423 sat 32 eat 32 @@ -13285,5 +14034,5 @@ on &173 ) -*415 (Wire +*441 (Wire uid 6160,0 shape (OrthoPolyLine @@ -13298,6 +14047,6 @@ ] ) -start &267 -end &286 +start &269 +end &288 sat 32 eat 32 @@ -13321,7 +14070,7 @@ ) ) -on &285 -) -*416 (Wire +on &287 +) +*442 (Wire uid 6276,0 shape (OrthoPolyLine @@ -13357,5 +14106,5 @@ on &162 ) -*417 (Wire +*443 (Wire uid 6362,0 shape (OrthoPolyLine @@ -13371,5 +14120,5 @@ ) start &94 -end &288 +end &290 sat 32 eat 32 @@ -13393,7 +14142,7 @@ ) ) -on &287 -) -*418 (Wire +on &289 +) +*444 (Wire uid 6452,0 shape (OrthoPolyLine @@ -13430,7 +14179,7 @@ ) ) -on &289 -) -*419 (Wire +on &291 +) +*445 (Wire uid 6540,0 shape (OrthoPolyLine @@ -13445,5 +14194,5 @@ ] ) -start &294 +start &296 end &41 sat 32 @@ -13467,7 +14216,7 @@ ) ) -on &308 -) -*420 (Wire +on &310 +) +*446 (Wire uid 6548,0 shape (OrthoPolyLine @@ -13482,5 +14231,5 @@ ] ) -start &296 +start &298 sat 32 eat 16 @@ -13503,7 +14252,7 @@ ) ) -on &289 -) -*421 (Wire +on &291 +) +*447 (Wire uid 8416,0 shape (OrthoPolyLine @@ -13539,5 +14288,227 @@ ) ) -on &320 +on &322 +) +*448 (Wire +uid 8510,0 +shape (OrthoPolyLine +uid 8511,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "92750,110000,102000,110000" +pts [ +"92750,110000" +"102000,110000" +] +) +start &227 +sat 32 +eat 16 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 8514,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8515,0 +va (VaSet +) +xt "94000,109000,101200,110000" +st "drs_address : (3:0)" +blo "94000,109800" +tm "WireNameMgr" +) +) +on &323 +) +*449 (Wire +uid 8518,0 +shape (OrthoPolyLine +uid 8519,0 +va (VaSet +vasetType 3 +) +xt "92750,111000,102000,111000" +pts [ +"92750,111000" +"102000,111000" +] +) +start &228 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 8522,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8523,0 +va (VaSet +) +xt "94000,110000,101200,111000" +st "drs_address_mode" +blo "94000,110800" +tm "WireNameMgr" +) +) +on &324 +) +*450 (Wire +uid 8577,0 +shape (OrthoPolyLine +uid 8578,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "7000,57000,18250,57000" +pts [ +"18250,57000" +"7000,57000" +] +) +start &39 +sat 32 +eat 16 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 8581,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8582,0 +va (VaSet +) +xt "8000,56000,18400,57000" +st "drs_channel_internal : (3:0)" +blo "8000,56800" +tm "WireNameMgr" +) +) +on &346 +) +*451 (Wire +uid 8587,0 +shape (OrthoPolyLine +uid 8588,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "-29000,101000,-20000,101000" +pts [ +"-20000,101000" +"-29000,101000" +] +) +end &326 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 8591,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8592,0 +va (VaSet +) +xt "-29000,100000,-20800,101000" +st "drs_channel_internal" +blo "-29000,100800" +tm "WireNameMgr" +) +) +on &346 +) +*452 (Wire +uid 8595,0 +shape (OrthoPolyLine +uid 8596,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "-29000,99000,-20000,99000" +pts [ +"-20000,99000" +"-29000,99000" +] +) +end &331 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 8599,0 +ps "ConnStartEndStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8600,0 +va (VaSet +) +xt "-29000,98000,-24000,99000" +st "drs_address" +blo "-29000,98800" +tm "WireNameMgr" +) +) +on &323 +) +*453 (Wire +uid 8603,0 +shape (OrthoPolyLine +uid 8604,0 +va (VaSet +vasetType 3 +) +xt "-31000,103000,-20000,107000" +pts [ +"-20000,107000" +"-31000,107000" +"-31000,103000" +] +) +end &333 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 8607,0 +ps "ConnStartEndStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8608,0 +va (VaSet +) +xt "-29000,106000,-21800,107000" +st "drs_address_mode" +blo "-29000,106800" +tm "WireNameMgr" +) +) +on &324 ) ] @@ -13553,9 +14524,9 @@ color "26368,26368,26368" ) -packageList *422 (PackageList +packageList *454 (PackageList uid 41,0 stg "VerticalLayoutStrategy" textVec [ -*423 (Text +*455 (Text uid 42,0 va (VaSet @@ -13566,5 +14537,5 @@ blo "-87000,1800" ) -*424 (MLText +*456 (MLText uid 43,0 va (VaSet @@ -13591,5 +14562,5 @@ stg "VerticalLayoutStrategy" textVec [ -*425 (Text +*457 (Text uid 45,0 va (VaSet @@ -13601,5 +14572,5 @@ blo "20000,800" ) -*426 (Text +*458 (Text uid 46,0 va (VaSet @@ -13611,5 +14582,5 @@ blo "20000,1800" ) -*427 (MLText +*459 (MLText uid 47,0 va (VaSet @@ -13621,5 +14592,5 @@ tm "BdCompilerDirectivesTextMgr" ) -*428 (Text +*460 (Text uid 48,0 va (VaSet @@ -13631,5 +14602,5 @@ blo "20000,4800" ) -*429 (MLText +*461 (MLText uid 49,0 va (VaSet @@ -13639,5 +14610,5 @@ tm "BdCompilerDirectivesTextMgr" ) -*430 (Text +*462 (Text uid 50,0 va (VaSet @@ -13649,5 +14620,5 @@ blo "20000,5800" ) -*431 (MLText +*463 (MLText uid 51,0 va (VaSet @@ -13661,6 +14632,6 @@ ) windowSize "0,0,1281,1024" -viewArea "-62364,34906,23843,105999" -cachedDiagramExtent "-87000,0,162300,301700" +viewArea "-73966,37109,33461,125703" +cachedDiagramExtent "-100999,0,162300,301700" pageSetupInfo (PageSetupInfo ptrCmd "eDocPrintPro,winspool," @@ -13687,5 +14658,5 @@ hasePageBreakOrigin 1 pageBreakOrigin "-73000,0" -lastUid 8460,0 +lastUid 8614,0 defaultCommentText (CommentText shape (Rectangle @@ -13749,5 +14720,5 @@ stg "VerticalLayoutStrategy" textVec [ -*432 (Text +*464 (Text va (VaSet font "Arial,8,1" @@ -13758,5 +14729,5 @@ tm "BdLibraryNameMgr" ) -*433 (Text +*465 (Text va (VaSet font "Arial,8,1" @@ -13767,5 +14738,5 @@ tm "BlkNameMgr" ) -*434 (Text +*466 (Text va (VaSet font "Arial,8,1" @@ -13818,5 +14789,5 @@ stg "VerticalLayoutStrategy" textVec [ -*435 (Text +*467 (Text va (VaSet font "Arial,8,1" @@ -13826,5 +14797,5 @@ blo "550,4300" ) -*436 (Text +*468 (Text va (VaSet font "Arial,8,1" @@ -13834,5 +14805,5 @@ blo "550,5300" ) -*437 (Text +*469 (Text va (VaSet font "Arial,8,1" @@ -13883,5 +14854,5 @@ stg "VerticalLayoutStrategy" textVec [ -*438 (Text +*470 (Text va (VaSet font "Arial,8,1" @@ -13892,5 +14863,5 @@ tm "BdLibraryNameMgr" ) -*439 (Text +*471 (Text va (VaSet font "Arial,8,1" @@ -13901,5 +14872,5 @@ tm "CptNameMgr" ) -*440 (Text +*472 (Text va (VaSet font "Arial,8,1" @@ -13955,5 +14926,5 @@ stg "VerticalLayoutStrategy" textVec [ -*441 (Text +*473 (Text va (VaSet font "Arial,8,1" @@ -13963,5 +14934,5 @@ blo "500,4300" ) -*442 (Text +*474 (Text va (VaSet font "Arial,8,1" @@ -13971,5 +14942,5 @@ blo "500,5300" ) -*443 (Text +*475 (Text va (VaSet font "Arial,8,1" @@ -14016,5 +14987,5 @@ stg "VerticalLayoutStrategy" textVec [ -*444 (Text +*476 (Text va (VaSet font "Arial,8,1" @@ -14024,5 +14995,5 @@ blo "50,4300" ) -*445 (Text +*477 (Text va (VaSet font "Arial,8,1" @@ -14032,5 +15003,5 @@ blo "50,5300" ) -*446 (Text +*478 (Text va (VaSet font "Arial,8,1" @@ -14073,5 +15044,5 @@ stg "VerticalLayoutStrategy" textVec [ -*447 (Text +*479 (Text va (VaSet font "Arial,8,1" @@ -14082,5 +15053,5 @@ tm "HdlTextNameMgr" ) -*448 (Text +*480 (Text va (VaSet font "Arial,8,1" @@ -14485,5 +15456,5 @@ stg "VerticalLayoutStrategy" textVec [ -*449 (Text +*481 (Text va (VaSet font "Arial,8,1" @@ -14493,5 +15464,5 @@ blo "14100,20800" ) -*450 (MLText +*482 (MLText va (VaSet ) @@ -14545,5 +15516,5 @@ stg "VerticalLayoutStrategy" textVec [ -*451 (Text +*483 (Text va (VaSet font "Arial,8,1" @@ -14553,5 +15524,5 @@ blo "14100,20800" ) -*452 (MLText +*484 (MLText va (VaSet ) @@ -14678,7 +15649,7 @@ font "Arial,8,1" ) -xt "-87000,85000,-82300,86000" +xt "-87000,87400,-82300,88400" st "Post User:" -blo "-87000,85800" +blo "-87000,88200" ) postUserText (MLText @@ -14693,44 +15664,44 @@ commonDM (CommonDM ldm (LogicalDM -suid 183,0 +suid 190,0 usingSuid 1 -emptyRow *453 (LEmptyRow +emptyRow *485 (LEmptyRow ) uid 54,0 optionalChildren [ -*454 (RefLabelRowHdr -) -*455 (TitleRowHdr -) -*456 (FilterRowHdr -) -*457 (RefLabelColHdr +*486 (RefLabelRowHdr +) +*487 (TitleRowHdr +) +*488 (FilterRowHdr +) +*489 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*458 (RowExpandColHdr +*490 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*459 (GroupColHdr +*491 (GroupColHdr tm "GroupColHdrMgr" ) -*460 (NameColHdr +*492 (NameColHdr tm "BlockDiagramNameColHdrMgr" ) -*461 (ModeColHdr +*493 (ModeColHdr tm "BlockDiagramModeColHdrMgr" ) -*462 (TypeColHdr +*494 (TypeColHdr tm "BlockDiagramTypeColHdrMgr" ) -*463 (BoundsColHdr +*495 (BoundsColHdr tm "BlockDiagramBoundsColHdrMgr" ) -*464 (InitColHdr +*496 (InitColHdr tm "BlockDiagramInitColHdrMgr" ) -*465 (EolColHdr +*497 (EolColHdr tm "BlockDiagramEolColHdrMgr" ) -*466 (LeafLogPort +*498 (LeafLogPort port (LogicalPort m 4 @@ -14746,5 +15717,5 @@ uid 516,0 ) -*467 (LeafLogPort +*499 (LeafLogPort port (LogicalPort m 4 @@ -14759,5 +15730,5 @@ uid 518,0 ) -*468 (LeafLogPort +*500 (LeafLogPort port (LogicalPort m 4 @@ -14772,5 +15743,5 @@ uid 520,0 ) -*469 (LeafLogPort +*501 (LeafLogPort port (LogicalPort m 4 @@ -14785,5 +15756,5 @@ uid 530,0 ) -*470 (LeafLogPort +*502 (LeafLogPort port (LogicalPort m 4 @@ -14798,5 +15769,5 @@ uid 532,0 ) -*471 (LeafLogPort +*503 (LeafLogPort port (LogicalPort m 1 @@ -14811,5 +15782,5 @@ uid 534,0 ) -*472 (LeafLogPort +*504 (LeafLogPort port (LogicalPort m 1 @@ -14824,5 +15795,5 @@ uid 536,0 ) -*473 (LeafLogPort +*505 (LeafLogPort port (LogicalPort m 2 @@ -14837,5 +15808,5 @@ uid 538,0 ) -*474 (LeafLogPort +*506 (LeafLogPort port (LogicalPort m 1 @@ -14850,5 +15821,5 @@ uid 540,0 ) -*475 (LeafLogPort +*507 (LeafLogPort port (LogicalPort m 1 @@ -14863,5 +15834,5 @@ uid 542,0 ) -*476 (LeafLogPort +*508 (LeafLogPort port (LogicalPort m 1 @@ -14876,5 +15847,5 @@ uid 546,0 ) -*477 (LeafLogPort +*509 (LeafLogPort port (LogicalPort decl (Decl @@ -14887,5 +15858,5 @@ uid 548,0 ) -*478 (LeafLogPort +*510 (LeafLogPort port (LogicalPort decl (Decl @@ -14901,5 +15872,5 @@ uid 1455,0 ) -*479 (LeafLogPort +*511 (LeafLogPort port (LogicalPort decl (Decl @@ -14914,5 +15885,5 @@ uid 1457,0 ) -*480 (LeafLogPort +*512 (LeafLogPort port (LogicalPort decl (Decl @@ -14926,5 +15897,5 @@ uid 1694,0 ) -*481 (LeafLogPort +*513 (LeafLogPort port (LogicalPort lang 2 @@ -14942,5 +15913,5 @@ uid 1993,0 ) -*482 (LeafLogPort +*514 (LeafLogPort port (LogicalPort m 4 @@ -14957,5 +15928,5 @@ uid 2305,0 ) -*483 (LeafLogPort +*515 (LeafLogPort port (LogicalPort lang 2 @@ -14970,5 +15941,5 @@ uid 2510,0 ) -*484 (LeafLogPort +*516 (LeafLogPort port (LogicalPort lang 2 @@ -14984,5 +15955,5 @@ uid 2512,0 ) -*485 (LeafLogPort +*517 (LeafLogPort port (LogicalPort lang 2 @@ -14999,5 +15970,5 @@ uid 2514,0 ) -*486 (LeafLogPort +*518 (LeafLogPort port (LogicalPort lang 2 @@ -15015,5 +15986,5 @@ uid 2516,0 ) -*487 (LeafLogPort +*519 (LeafLogPort port (LogicalPort lang 2 @@ -15030,5 +16001,5 @@ uid 2518,0 ) -*488 (LeafLogPort +*520 (LeafLogPort port (LogicalPort lang 2 @@ -15044,5 +16015,5 @@ uid 2520,0 ) -*489 (LeafLogPort +*521 (LeafLogPort port (LogicalPort lang 2 @@ -15058,5 +16029,5 @@ uid 2522,0 ) -*490 (LeafLogPort +*522 (LeafLogPort port (LogicalPort m 4 @@ -15070,5 +16041,5 @@ uid 2604,0 ) -*491 (LeafLogPort +*523 (LeafLogPort port (LogicalPort m 4 @@ -15083,5 +16054,5 @@ uid 2606,0 ) -*492 (LeafLogPort +*524 (LeafLogPort port (LogicalPort m 4 @@ -15096,5 +16067,5 @@ uid 2608,0 ) -*493 (LeafLogPort +*525 (LeafLogPort port (LogicalPort m 4 @@ -15108,5 +16079,5 @@ uid 2610,0 ) -*494 (LeafLogPort +*526 (LeafLogPort port (LogicalPort m 4 @@ -15120,5 +16091,5 @@ uid 2612,0 ) -*495 (LeafLogPort +*527 (LeafLogPort port (LogicalPort m 4 @@ -15133,5 +16104,5 @@ uid 2646,0 ) -*496 (LeafLogPort +*528 (LeafLogPort port (LogicalPort m 1 @@ -15146,5 +16117,5 @@ uid 2812,0 ) -*497 (LeafLogPort +*529 (LeafLogPort port (LogicalPort m 4 @@ -15158,5 +16129,5 @@ uid 2962,0 ) -*498 (LeafLogPort +*530 (LeafLogPort port (LogicalPort m 1 @@ -15170,5 +16141,5 @@ uid 3902,0 ) -*499 (LeafLogPort +*531 (LeafLogPort port (LogicalPort m 1 @@ -15182,5 +16153,5 @@ uid 4070,0 ) -*500 (LeafLogPort +*532 (LeafLogPort port (LogicalPort m 4 @@ -15194,5 +16165,5 @@ uid 4212,0 ) -*501 (LeafLogPort +*533 (LeafLogPort port (LogicalPort decl (Decl @@ -15205,5 +16176,5 @@ uid 4234,0 ) -*502 (LeafLogPort +*534 (LeafLogPort port (LogicalPort decl (Decl @@ -15217,5 +16188,5 @@ uid 4262,0 ) -*503 (LeafLogPort +*535 (LeafLogPort port (LogicalPort decl (Decl @@ -15228,5 +16199,5 @@ uid 4276,0 ) -*504 (LeafLogPort +*536 (LeafLogPort port (LogicalPort m 4 @@ -15241,5 +16212,5 @@ uid 4563,0 ) -*505 (LeafLogPort +*537 (LeafLogPort port (LogicalPort m 4 @@ -15253,5 +16224,5 @@ uid 4565,0 ) -*506 (LeafLogPort +*538 (LeafLogPort port (LogicalPort m 4 @@ -15266,5 +16237,5 @@ uid 4569,0 ) -*507 (LeafLogPort +*539 (LeafLogPort port (LogicalPort m 1 @@ -15280,5 +16251,5 @@ uid 4585,0 ) -*508 (LeafLogPort +*540 (LeafLogPort port (LogicalPort m 1 @@ -15293,5 +16264,5 @@ uid 4587,0 ) -*509 (LeafLogPort +*541 (LeafLogPort port (LogicalPort decl (Decl @@ -15304,5 +16275,5 @@ uid 4733,0 ) -*510 (LeafLogPort +*542 (LeafLogPort port (LogicalPort decl (Decl @@ -15315,5 +16286,5 @@ uid 4735,0 ) -*511 (LeafLogPort +*543 (LeafLogPort port (LogicalPort decl (Decl @@ -15326,5 +16297,5 @@ uid 4737,0 ) -*512 (LeafLogPort +*544 (LeafLogPort port (LogicalPort decl (Decl @@ -15337,5 +16308,5 @@ uid 4739,0 ) -*513 (LeafLogPort +*545 (LeafLogPort port (LogicalPort m 4 @@ -15349,5 +16320,5 @@ uid 4749,0 ) -*514 (LeafLogPort +*546 (LeafLogPort port (LogicalPort m 1 @@ -15362,5 +16333,5 @@ uid 4974,0 ) -*515 (LeafLogPort +*547 (LeafLogPort port (LogicalPort m 1 @@ -15375,5 +16346,5 @@ uid 4976,0 ) -*516 (LeafLogPort +*548 (LeafLogPort port (LogicalPort m 4 @@ -15388,5 +16359,5 @@ uid 5198,0 ) -*517 (LeafLogPort +*549 (LeafLogPort port (LogicalPort m 4 @@ -15400,5 +16371,5 @@ uid 5200,0 ) -*518 (LeafLogPort +*550 (LeafLogPort port (LogicalPort m 4 @@ -15412,5 +16383,5 @@ uid 5202,0 ) -*519 (LeafLogPort +*551 (LeafLogPort port (LogicalPort m 4 @@ -15425,5 +16396,5 @@ uid 5204,0 ) -*520 (LeafLogPort +*552 (LeafLogPort port (LogicalPort m 4 @@ -15437,5 +16408,5 @@ uid 5206,0 ) -*521 (LeafLogPort +*553 (LeafLogPort port (LogicalPort m 4 @@ -15449,5 +16420,5 @@ uid 5208,0 ) -*522 (LeafLogPort +*554 (LeafLogPort port (LogicalPort m 4 @@ -15461,5 +16432,5 @@ uid 5210,0 ) -*523 (LeafLogPort +*555 (LeafLogPort port (LogicalPort m 4 @@ -15473,5 +16444,5 @@ uid 5212,0 ) -*524 (LeafLogPort +*556 (LeafLogPort port (LogicalPort m 4 @@ -15485,5 +16456,5 @@ uid 5214,0 ) -*525 (LeafLogPort +*557 (LeafLogPort port (LogicalPort m 1 @@ -15500,5 +16471,5 @@ uid 5226,0 ) -*526 (LeafLogPort +*558 (LeafLogPort port (LogicalPort m 4 @@ -15513,5 +16484,5 @@ uid 5285,0 ) -*527 (LeafLogPort +*559 (LeafLogPort port (LogicalPort m 4 @@ -15525,5 +16496,5 @@ uid 5502,0 ) -*528 (LeafLogPort +*560 (LeafLogPort port (LogicalPort m 4 @@ -15537,5 +16508,5 @@ uid 5504,0 ) -*529 (LeafLogPort +*561 (LeafLogPort port (LogicalPort m 4 @@ -15549,5 +16520,5 @@ uid 5600,0 ) -*530 (LeafLogPort +*562 (LeafLogPort port (LogicalPort lang 10 @@ -15563,5 +16534,5 @@ uid 5642,0 ) -*531 (LeafLogPort +*563 (LeafLogPort port (LogicalPort m 4 @@ -15575,5 +16546,5 @@ uid 5644,0 ) -*532 (LeafLogPort +*564 (LeafLogPort port (LogicalPort m 4 @@ -15588,5 +16559,5 @@ uid 5751,0 ) -*533 (LeafLogPort +*565 (LeafLogPort port (LogicalPort m 1 @@ -15600,5 +16571,5 @@ uid 5867,0 ) -*534 (LeafLogPort +*566 (LeafLogPort port (LogicalPort m 2 @@ -15614,5 +16585,5 @@ uid 5869,0 ) -*535 (LeafLogPort +*567 (LeafLogPort port (LogicalPort m 1 @@ -15626,5 +16597,5 @@ uid 5871,0 ) -*536 (LeafLogPort +*568 (LeafLogPort port (LogicalPort m 1 @@ -15639,5 +16610,5 @@ uid 5873,0 ) -*537 (LeafLogPort +*569 (LeafLogPort port (LogicalPort m 4 @@ -15652,5 +16623,5 @@ uid 5966,0 ) -*538 (LeafLogPort +*570 (LeafLogPort port (LogicalPort m 4 @@ -15664,5 +16635,5 @@ uid 5968,0 ) -*539 (LeafLogPort +*571 (LeafLogPort port (LogicalPort m 4 @@ -15677,5 +16648,5 @@ uid 6022,0 ) -*540 (LeafLogPort +*572 (LeafLogPort port (LogicalPort m 4 @@ -15690,5 +16661,5 @@ uid 6024,0 ) -*541 (LeafLogPort +*573 (LeafLogPort port (LogicalPort m 4 @@ -15702,5 +16673,5 @@ uid 6026,0 ) -*542 (LeafLogPort +*574 (LeafLogPort port (LogicalPort m 1 @@ -15715,5 +16686,5 @@ uid 6172,0 ) -*543 (LeafLogPort +*575 (LeafLogPort port (LogicalPort m 1 @@ -15730,5 +16701,5 @@ uid 6374,0 ) -*544 (LeafLogPort +*576 (LeafLogPort port (LogicalPort m 4 @@ -15743,5 +16714,5 @@ uid 6464,0 ) -*545 (LeafLogPort +*577 (LeafLogPort port (LogicalPort m 4 @@ -15756,5 +16727,5 @@ uid 6554,0 ) -*546 (LeafLogPort +*578 (LeafLogPort port (LogicalPort lang 2 @@ -15768,4 +16739,44 @@ ) uid 8420,0 +) +*579 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 82 +suid 184,0 +i "(others => '0')" +) +) +uid 8609,0 +) +*580 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 83 +suid 185,0 +) +) +uid 8611,0 +) +*581 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "drs_channel_internal" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 84 +suid 187,0 +i "(others => '0')" +) +) +uid 8613,0 ) ] @@ -15776,5 +16787,5 @@ uid 67,0 optionalChildren [ -*547 (Sheet +*582 (Sheet sheetRow (SheetRow headerVa (MVa @@ -15793,25 +16804,25 @@ font "Tahoma,10,0" ) -emptyMRCItem *548 (MRCItem -litem &453 -pos 81 +emptyMRCItem *583 (MRCItem +litem &485 +pos 84 dimension 20 ) uid 69,0 optionalChildren [ -*549 (MRCItem -litem &454 +*584 (MRCItem +litem &486 pos 0 dimension 20 uid 70,0 ) -*550 (MRCItem -litem &455 +*585 (MRCItem +litem &487 pos 1 dimension 23 uid 71,0 ) -*551 (MRCItem -litem &456 +*586 (MRCItem +litem &488 pos 2 hidden 1 @@ -15819,489 +16830,507 @@ uid 72,0 ) -*552 (MRCItem -litem &466 +*587 (MRCItem +litem &498 pos 31 dimension 20 uid 517,0 ) -*553 (MRCItem -litem &467 +*588 (MRCItem +litem &499 pos 32 dimension 20 uid 519,0 ) -*554 (MRCItem -litem &468 +*589 (MRCItem +litem &500 pos 33 dimension 20 uid 521,0 ) -*555 (MRCItem -litem &469 +*590 (MRCItem +litem &501 pos 34 dimension 20 uid 531,0 ) -*556 (MRCItem -litem &470 +*591 (MRCItem +litem &502 pos 35 dimension 20 uid 533,0 ) -*557 (MRCItem -litem &471 +*592 (MRCItem +litem &503 pos 0 dimension 20 uid 535,0 ) -*558 (MRCItem -litem &472 +*593 (MRCItem +litem &504 pos 1 dimension 20 uid 537,0 ) -*559 (MRCItem -litem &473 +*594 (MRCItem +litem &505 pos 2 dimension 20 uid 539,0 ) -*560 (MRCItem -litem &474 +*595 (MRCItem +litem &506 pos 3 dimension 20 uid 541,0 ) -*561 (MRCItem -litem &475 +*596 (MRCItem +litem &507 pos 4 dimension 20 uid 543,0 ) -*562 (MRCItem -litem &476 +*597 (MRCItem +litem &508 pos 5 dimension 20 uid 547,0 ) -*563 (MRCItem -litem &477 +*598 (MRCItem +litem &509 pos 6 dimension 20 uid 549,0 ) -*564 (MRCItem -litem &478 +*599 (MRCItem +litem &510 pos 8 dimension 20 uid 1456,0 ) -*565 (MRCItem -litem &479 +*600 (MRCItem +litem &511 pos 7 dimension 20 uid 1458,0 ) -*566 (MRCItem -litem &480 +*601 (MRCItem +litem &512 pos 9 dimension 20 uid 1695,0 ) -*567 (MRCItem -litem &481 +*602 (MRCItem +litem &513 pos 36 dimension 20 uid 1994,0 ) -*568 (MRCItem -litem &482 +*603 (MRCItem +litem &514 pos 37 dimension 20 uid 2306,0 ) -*569 (MRCItem -litem &483 +*604 (MRCItem +litem &515 pos 38 dimension 20 uid 2511,0 ) -*570 (MRCItem -litem &484 +*605 (MRCItem +litem &516 pos 39 dimension 20 uid 2513,0 ) -*571 (MRCItem -litem &485 +*606 (MRCItem +litem &517 pos 40 dimension 20 uid 2515,0 ) -*572 (MRCItem -litem &486 +*607 (MRCItem +litem &518 pos 41 dimension 20 uid 2517,0 ) -*573 (MRCItem -litem &487 +*608 (MRCItem +litem &519 pos 42 dimension 20 uid 2519,0 ) -*574 (MRCItem -litem &488 +*609 (MRCItem +litem &520 pos 43 dimension 20 uid 2521,0 ) -*575 (MRCItem -litem &489 +*610 (MRCItem +litem &521 pos 44 dimension 20 uid 2523,0 ) -*576 (MRCItem -litem &490 +*611 (MRCItem +litem &522 pos 45 dimension 20 uid 2605,0 ) -*577 (MRCItem -litem &491 +*612 (MRCItem +litem &523 pos 46 dimension 20 uid 2607,0 ) -*578 (MRCItem -litem &492 +*613 (MRCItem +litem &524 pos 47 dimension 20 uid 2609,0 ) -*579 (MRCItem -litem &493 +*614 (MRCItem +litem &525 pos 48 dimension 20 uid 2611,0 ) -*580 (MRCItem -litem &494 +*615 (MRCItem +litem &526 pos 49 dimension 20 uid 2613,0 ) -*581 (MRCItem -litem &495 +*616 (MRCItem +litem &527 pos 50 dimension 20 uid 2647,0 ) -*582 (MRCItem -litem &496 +*617 (MRCItem +litem &528 pos 10 dimension 20 uid 2813,0 ) -*583 (MRCItem -litem &497 +*618 (MRCItem +litem &529 pos 51 dimension 20 uid 2963,0 ) -*584 (MRCItem -litem &498 +*619 (MRCItem +litem &530 pos 11 dimension 20 uid 3903,0 ) -*585 (MRCItem -litem &499 +*620 (MRCItem +litem &531 pos 12 dimension 20 uid 4071,0 ) -*586 (MRCItem -litem &500 +*621 (MRCItem +litem &532 pos 52 dimension 20 uid 4213,0 ) -*587 (MRCItem -litem &501 +*622 (MRCItem +litem &533 pos 13 dimension 20 uid 4235,0 ) -*588 (MRCItem -litem &502 +*623 (MRCItem +litem &534 pos 14 dimension 20 uid 4263,0 ) -*589 (MRCItem -litem &503 +*624 (MRCItem +litem &535 pos 15 dimension 20 uid 4277,0 ) -*590 (MRCItem -litem &504 +*625 (MRCItem +litem &536 pos 53 dimension 20 uid 4564,0 ) -*591 (MRCItem -litem &505 +*626 (MRCItem +litem &537 pos 54 dimension 20 uid 4566,0 ) -*592 (MRCItem -litem &506 +*627 (MRCItem +litem &538 pos 55 dimension 20 uid 4570,0 ) -*593 (MRCItem -litem &507 +*628 (MRCItem +litem &539 pos 16 dimension 20 uid 4586,0 ) -*594 (MRCItem -litem &508 +*629 (MRCItem +litem &540 pos 17 dimension 20 uid 4588,0 ) -*595 (MRCItem -litem &509 +*630 (MRCItem +litem &541 pos 18 dimension 20 uid 4734,0 ) -*596 (MRCItem -litem &510 +*631 (MRCItem +litem &542 pos 19 dimension 20 uid 4736,0 ) -*597 (MRCItem -litem &511 +*632 (MRCItem +litem &543 pos 20 dimension 20 uid 4738,0 ) -*598 (MRCItem -litem &512 +*633 (MRCItem +litem &544 pos 21 dimension 20 uid 4740,0 ) -*599 (MRCItem -litem &513 +*634 (MRCItem +litem &545 pos 56 dimension 20 uid 4750,0 ) -*600 (MRCItem -litem &514 +*635 (MRCItem +litem &546 pos 22 dimension 20 uid 4975,0 ) -*601 (MRCItem -litem &515 +*636 (MRCItem +litem &547 pos 23 dimension 20 uid 4977,0 ) -*602 (MRCItem -litem &516 +*637 (MRCItem +litem &548 pos 57 dimension 20 uid 5199,0 ) -*603 (MRCItem -litem &517 +*638 (MRCItem +litem &549 pos 58 dimension 20 uid 5201,0 ) -*604 (MRCItem -litem &518 +*639 (MRCItem +litem &550 pos 59 dimension 20 uid 5203,0 ) -*605 (MRCItem -litem &519 +*640 (MRCItem +litem &551 pos 60 dimension 20 uid 5205,0 ) -*606 (MRCItem -litem &520 +*641 (MRCItem +litem &552 pos 61 dimension 20 uid 5207,0 ) -*607 (MRCItem -litem &521 +*642 (MRCItem +litem &553 pos 62 dimension 20 uid 5209,0 ) -*608 (MRCItem -litem &522 +*643 (MRCItem +litem &554 pos 63 dimension 20 uid 5211,0 ) -*609 (MRCItem -litem &523 +*644 (MRCItem +litem &555 pos 64 dimension 20 uid 5213,0 ) -*610 (MRCItem -litem &524 +*645 (MRCItem +litem &556 pos 65 dimension 20 uid 5215,0 ) -*611 (MRCItem -litem &525 +*646 (MRCItem +litem &557 pos 24 dimension 20 uid 5227,0 ) -*612 (MRCItem -litem &526 +*647 (MRCItem +litem &558 pos 66 dimension 20 uid 5286,0 ) -*613 (MRCItem -litem &527 +*648 (MRCItem +litem &559 pos 67 dimension 20 uid 5503,0 ) -*614 (MRCItem -litem &528 +*649 (MRCItem +litem &560 pos 68 dimension 20 uid 5505,0 ) -*615 (MRCItem -litem &529 +*650 (MRCItem +litem &561 pos 69 dimension 20 uid 5601,0 ) -*616 (MRCItem -litem &530 +*651 (MRCItem +litem &562 pos 70 dimension 20 uid 5643,0 ) -*617 (MRCItem -litem &531 +*652 (MRCItem +litem &563 pos 71 dimension 20 uid 5645,0 ) -*618 (MRCItem -litem &532 +*653 (MRCItem +litem &564 pos 72 dimension 20 uid 5752,0 ) -*619 (MRCItem -litem &533 +*654 (MRCItem +litem &565 pos 25 dimension 20 uid 5868,0 ) -*620 (MRCItem -litem &534 +*655 (MRCItem +litem &566 pos 26 dimension 20 uid 5870,0 ) -*621 (MRCItem -litem &535 +*656 (MRCItem +litem &567 pos 27 dimension 20 uid 5872,0 ) -*622 (MRCItem -litem &536 +*657 (MRCItem +litem &568 pos 28 dimension 20 uid 5874,0 ) -*623 (MRCItem -litem &537 +*658 (MRCItem +litem &569 pos 73 dimension 20 uid 5967,0 ) -*624 (MRCItem -litem &538 +*659 (MRCItem +litem &570 pos 74 dimension 20 uid 5969,0 ) -*625 (MRCItem -litem &539 +*660 (MRCItem +litem &571 pos 75 dimension 20 uid 6023,0 ) -*626 (MRCItem -litem &540 +*661 (MRCItem +litem &572 pos 76 dimension 20 uid 6025,0 ) -*627 (MRCItem -litem &541 +*662 (MRCItem +litem &573 pos 77 dimension 20 uid 6027,0 ) -*628 (MRCItem -litem &542 +*663 (MRCItem +litem &574 pos 29 dimension 20 uid 6173,0 ) -*629 (MRCItem -litem &543 +*664 (MRCItem +litem &575 pos 30 dimension 20 uid 6375,0 ) -*630 (MRCItem -litem &544 +*665 (MRCItem +litem &576 pos 78 dimension 20 uid 6465,0 ) -*631 (MRCItem -litem &545 +*666 (MRCItem +litem &577 pos 79 dimension 20 uid 6555,0 ) -*632 (MRCItem -litem &546 +*667 (MRCItem +litem &578 pos 80 dimension 20 uid 8421,0 +) +*668 (MRCItem +litem &579 +pos 81 +dimension 20 +uid 8610,0 +) +*669 (MRCItem +litem &580 +pos 82 +dimension 20 +uid 8612,0 +) +*670 (MRCItem +litem &581 +pos 83 +dimension 20 +uid 8614,0 ) ] @@ -16316,48 +17345,48 @@ uid 73,0 optionalChildren [ -*633 (MRCItem -litem &457 +*671 (MRCItem +litem &489 pos 0 dimension 20 uid 74,0 ) -*634 (MRCItem -litem &459 +*672 (MRCItem +litem &491 pos 1 dimension 50 uid 75,0 ) -*635 (MRCItem -litem &460 +*673 (MRCItem +litem &492 pos 2 dimension 100 uid 76,0 ) -*636 (MRCItem -litem &461 +*674 (MRCItem +litem &493 pos 3 dimension 50 uid 77,0 ) -*637 (MRCItem -litem &462 +*675 (MRCItem +litem &494 pos 4 dimension 100 uid 78,0 ) -*638 (MRCItem -litem &463 +*676 (MRCItem +litem &495 pos 5 dimension 100 uid 79,0 ) -*639 (MRCItem -litem &464 +*677 (MRCItem +litem &496 pos 6 dimension 50 uid 80,0 ) -*640 (MRCItem -litem &465 +*678 (MRCItem +litem &497 pos 7 dimension 80 @@ -16379,39 +17408,39 @@ genericsCommonDM (CommonDM ldm (LogicalDM -emptyRow *641 (LEmptyRow +emptyRow *679 (LEmptyRow ) uid 83,0 optionalChildren [ -*642 (RefLabelRowHdr -) -*643 (TitleRowHdr -) -*644 (FilterRowHdr -) -*645 (RefLabelColHdr +*680 (RefLabelRowHdr +) +*681 (TitleRowHdr +) +*682 (FilterRowHdr +) +*683 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*646 (RowExpandColHdr +*684 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*647 (GroupColHdr +*685 (GroupColHdr tm "GroupColHdrMgr" ) -*648 (NameColHdr +*686 (NameColHdr tm "GenericNameColHdrMgr" ) -*649 (TypeColHdr +*687 (TypeColHdr tm "GenericTypeColHdrMgr" ) -*650 (InitColHdr +*688 (InitColHdr tm "GenericValueColHdrMgr" ) -*651 (PragmaColHdr +*689 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) -*652 (EolColHdr +*690 (EolColHdr tm "GenericEolColHdrMgr" ) -*653 (LogGeneric +*691 (LogGeneric generic (GiElement name "RAMADDRWIDTH64b" @@ -16428,5 +17457,5 @@ uid 95,0 optionalChildren [ -*654 (Sheet +*692 (Sheet sheetRow (SheetRow headerVa (MVa @@ -16445,6 +17474,6 @@ font "Tahoma,10,0" ) -emptyMRCItem *655 (MRCItem -litem &641 +emptyMRCItem *693 (MRCItem +litem &679 pos 1 dimension 20 @@ -16452,18 +17481,18 @@ uid 97,0 optionalChildren [ -*656 (MRCItem -litem &642 +*694 (MRCItem +litem &680 pos 0 dimension 20 uid 98,0 ) -*657 (MRCItem -litem &643 +*695 (MRCItem +litem &681 pos 1 dimension 23 uid 99,0 ) -*658 (MRCItem -litem &644 +*696 (MRCItem +litem &682 pos 2 hidden 1 @@ -16471,6 +17500,6 @@ uid 100,0 ) -*659 (MRCItem -litem &653 +*697 (MRCItem +litem &691 pos 0 dimension 20 @@ -16488,42 +17517,42 @@ uid 101,0 optionalChildren [ -*660 (MRCItem -litem &645 +*698 (MRCItem +litem &683 pos 0 dimension 20 uid 102,0 ) -*661 (MRCItem -litem &647 +*699 (MRCItem +litem &685 pos 1 dimension 50 uid 103,0 ) -*662 (MRCItem -litem &648 +*700 (MRCItem +litem &686 pos 2 dimension 186 uid 104,0 ) -*663 (MRCItem -litem &649 +*701 (MRCItem +litem &687 pos 3 dimension 96 uid 105,0 ) -*664 (MRCItem -litem &650 +*702 (MRCItem +litem &688 pos 4 dimension 50 uid 106,0 ) -*665 (MRCItem -litem &651 +*703 (MRCItem +litem &689 pos 5 dimension 50 uid 107,0 ) -*666 (MRCItem -litem &652 +*704 (MRCItem +litem &690 pos 6 dimension 80 Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak (revision 252) @@ -167,21 +167,21 @@ (vvPair variable "HDLDir" -value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hdl" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" ) (vvPair variable "HDSDir" -value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair variable "SideDataDesignDir" -value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info" ) (vvPair variable "SideDataUserDir" -value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user" ) (vvPair variable "SourceDir" -value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair @@ -199,25 +199,25 @@ (vvPair variable "d" -value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main" ) (vvPair variable "d_logical" -value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main" ) (vvPair variable "date" -value "02.07.2010" +value "12.07.2010" ) (vvPair variable "day" -value "Fr" +value "Mo" ) (vvPair variable "day_long" -value "Freitag" +value "Montag" ) (vvPair variable "dd" -value "02" +value "12" ) (vvPair @@ -299,9 +299,9 @@ (vvPair variable "p" -value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd" ) (vvPair variable "p_logical" -value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd" ) (vvPair @@ -359,5 +359,5 @@ (vvPair variable "time" -value "10:38:34" +value "11:42:03" ) (vvPair @@ -12748,7 +12748,7 @@ va (VaSet ) -xt "-25000,74000,-20500,75000" +xt "-25000,73000,-20500,74000" st "CLK_25_PS" -blo "-25000,74800" +blo "-25000,73800" tm "WireNameMgr" ) @@ -13330,7 +13330,7 @@ vasetType 3 ) -xt "-23000,63000,-18750,63000" +xt "-27000,63000,-18750,63000" pts [ -"-23000,63000" +"-27000,63000" "-18750,63000" ] @@ -13349,7 +13349,7 @@ va (VaSet ) -xt "-22000,62000,-17500,63000" +xt "-24000,62000,-19500,63000" st "CLK_25_PS" -blo "-22000,62800" +blo "-24000,62800" tm "WireNameMgr" ) @@ -13661,5 +13661,5 @@ ) windowSize "0,0,1281,1024" -viewArea "63050,40700,132015,97575" +viewArea "-62364,34906,23843,105999" cachedDiagramExtent "-87000,0,162300,301700" pageSetupInfo (PageSetupInfo @@ -13687,5 +13687,5 @@ hasePageBreakOrigin 1 pageBreakOrigin "-73000,0" -lastUid 8421,0 +lastUid 8460,0 defaultCommentText (CommentText shape (Rectangle Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_manager/symbol.sb =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_manager/symbol.sb (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_manager/symbol.sb (revision 252) @@ -30,10 +30,10 @@ ) version "24.1" -appVersion "2009.1 (Build 12)" +appVersion "2009.2 (Build 10)" model (Symbol commonDM (CommonDM ldm (LogicalDM ordering 1 -suid 23,0 +suid 25,0 usingSuid 1 emptyRow *1 (LEmptyRow @@ -293,4 +293,29 @@ uid 497,0 ) +*30 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 17 +suid 24,0 +) +) +uid 538,0 +) +*31 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 18 +suid 25,0 +) +) +uid 540,0 +) ] ) @@ -300,5 +325,5 @@ uid 187,0 optionalChildren [ -*30 (Sheet +*32 (Sheet sheetRow (SheetRow headerVa (MVa @@ -317,5 +342,5 @@ font "Tahoma,10,0" ) -emptyMRCItem *31 (MRCItem +emptyMRCItem *33 (MRCItem litem &1 pos 3 @@ -324,5 +349,5 @@ uid 189,0 optionalChildren [ -*32 (MRCItem +*34 (MRCItem litem &2 pos 0 @@ -330,5 +355,5 @@ uid 190,0 ) -*33 (MRCItem +*35 (MRCItem litem &3 pos 1 @@ -336,5 +361,5 @@ uid 191,0 ) -*34 (MRCItem +*36 (MRCItem litem &4 pos 2 @@ -343,5 +368,5 @@ uid 192,0 ) -*35 (MRCItem +*37 (MRCItem litem &14 pos 0 @@ -349,5 +374,5 @@ uid 138,0 ) -*36 (MRCItem +*38 (MRCItem litem &15 pos 1 @@ -355,5 +380,5 @@ uid 142,0 ) -*37 (MRCItem +*39 (MRCItem litem &16 pos 2 @@ -361,5 +386,5 @@ uid 144,0 ) -*38 (MRCItem +*40 (MRCItem litem &17 pos 3 @@ -367,5 +392,5 @@ uid 146,0 ) -*39 (MRCItem +*41 (MRCItem litem &18 pos 4 @@ -373,5 +398,5 @@ uid 148,0 ) -*40 (MRCItem +*42 (MRCItem litem &19 pos 5 @@ -379,5 +404,5 @@ uid 150,0 ) -*41 (MRCItem +*43 (MRCItem litem &20 pos 6 @@ -385,5 +410,5 @@ uid 152,0 ) -*42 (MRCItem +*44 (MRCItem litem &21 pos 7 @@ -391,5 +416,5 @@ uid 154,0 ) -*43 (MRCItem +*45 (MRCItem litem &22 pos 8 @@ -397,5 +422,5 @@ uid 156,0 ) -*44 (MRCItem +*46 (MRCItem litem &23 pos 9 @@ -403,5 +428,5 @@ uid 166,0 ) -*45 (MRCItem +*47 (MRCItem litem &24 pos 10 @@ -409,5 +434,5 @@ uid 168,0 ) -*46 (MRCItem +*48 (MRCItem litem &25 pos 11 @@ -415,5 +440,5 @@ uid 278,0 ) -*47 (MRCItem +*49 (MRCItem litem &26 pos 12 @@ -421,5 +446,5 @@ uid 280,0 ) -*48 (MRCItem +*50 (MRCItem litem &27 pos 13 @@ -427,5 +452,5 @@ uid 316,0 ) -*49 (MRCItem +*51 (MRCItem litem &28 pos 14 @@ -433,9 +458,21 @@ uid 352,0 ) -*50 (MRCItem +*52 (MRCItem litem &29 pos 15 dimension 20 uid 498,0 +) +*53 (MRCItem +litem &30 +pos 16 +dimension 20 +uid 539,0 +) +*54 (MRCItem +litem &31 +pos 17 +dimension 20 +uid 541,0 ) ] @@ -450,5 +487,5 @@ uid 193,0 optionalChildren [ -*51 (MRCItem +*55 (MRCItem litem &5 pos 0 @@ -456,5 +493,5 @@ uid 194,0 ) -*52 (MRCItem +*56 (MRCItem litem &7 pos 1 @@ -462,5 +499,5 @@ uid 195,0 ) -*53 (MRCItem +*57 (MRCItem litem &8 pos 2 @@ -468,5 +505,5 @@ uid 196,0 ) -*54 (MRCItem +*58 (MRCItem litem &9 pos 3 @@ -474,5 +511,5 @@ uid 197,0 ) -*55 (MRCItem +*59 (MRCItem litem &10 pos 4 @@ -480,5 +517,5 @@ uid 198,0 ) -*56 (MRCItem +*60 (MRCItem litem &11 pos 5 @@ -486,5 +523,5 @@ uid 199,0 ) -*57 (MRCItem +*61 (MRCItem litem &12 pos 6 @@ -492,5 +529,5 @@ uid 200,0 ) -*58 (MRCItem +*62 (MRCItem litem &13 pos 7 @@ -513,39 +550,39 @@ genericsCommonDM (CommonDM ldm (LogicalDM -emptyRow *59 (LEmptyRow +emptyRow *63 (LEmptyRow ) uid 203,0 optionalChildren [ -*60 (RefLabelRowHdr -) -*61 (TitleRowHdr -) -*62 (FilterRowHdr -) -*63 (RefLabelColHdr +*64 (RefLabelRowHdr +) +*65 (TitleRowHdr +) +*66 (FilterRowHdr +) +*67 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*64 (RowExpandColHdr +*68 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*65 (GroupColHdr +*69 (GroupColHdr tm "GroupColHdrMgr" ) -*66 (NameColHdr +*70 (NameColHdr tm "GenericNameColHdrMgr" ) -*67 (TypeColHdr +*71 (TypeColHdr tm "GenericTypeColHdrMgr" ) -*68 (InitColHdr +*72 (InitColHdr tm "GenericValueColHdrMgr" ) -*69 (PragmaColHdr +*73 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) -*70 (EolColHdr +*74 (EolColHdr tm "GenericEolColHdrMgr" ) -*71 (LogGeneric +*75 (LogGeneric generic (GiElement name "NO_OF_ROI" @@ -553,7 +590,7 @@ value "36" ) -uid 499,0 -) -*72 (LogGeneric +uid 542,0 +) +*76 (LogGeneric generic (GiElement name "NO_OF_DAC" @@ -561,7 +598,7 @@ value "8" ) -uid 501,0 -) -*73 (LogGeneric +uid 544,0 +) +*77 (LogGeneric generic (GiElement name "ADDR_WIDTH" @@ -569,5 +606,5 @@ value "8" ) -uid 503,0 +uid 546,0 ) ] @@ -578,5 +615,5 @@ uid 215,0 optionalChildren [ -*74 (Sheet +*78 (Sheet sheetRow (SheetRow headerVa (MVa @@ -595,6 +632,6 @@ font "Tahoma,10,0" ) -emptyMRCItem *75 (MRCItem -litem &59 +emptyMRCItem *79 (MRCItem +litem &63 pos 3 dimension 20 @@ -602,18 +639,18 @@ uid 217,0 optionalChildren [ -*76 (MRCItem -litem &60 +*80 (MRCItem +litem &64 pos 0 dimension 20 uid 218,0 ) -*77 (MRCItem -litem &61 +*81 (MRCItem +litem &65 pos 1 dimension 23 uid 219,0 ) -*78 (MRCItem -litem &62 +*82 (MRCItem +litem &66 pos 2 hidden 1 @@ -621,21 +658,21 @@ uid 220,0 ) -*79 (MRCItem -litem &71 +*83 (MRCItem +litem &75 pos 0 dimension 20 -uid 500,0 -) -*80 (MRCItem -litem &72 +uid 543,0 +) +*84 (MRCItem +litem &76 pos 1 dimension 20 -uid 502,0 -) -*81 (MRCItem -litem &73 +uid 545,0 +) +*85 (MRCItem +litem &77 pos 2 dimension 20 -uid 504,0 +uid 547,0 ) ] @@ -650,42 +687,42 @@ uid 221,0 optionalChildren [ -*82 (MRCItem -litem &63 +*86 (MRCItem +litem &67 pos 0 dimension 20 uid 222,0 ) -*83 (MRCItem -litem &65 +*87 (MRCItem +litem &69 pos 1 dimension 50 uid 223,0 ) -*84 (MRCItem -litem &66 +*88 (MRCItem +litem &70 pos 2 dimension 100 uid 224,0 ) -*85 (MRCItem -litem &67 +*89 (MRCItem +litem &71 pos 3 dimension 100 uid 225,0 ) -*86 (MRCItem -litem &68 +*90 (MRCItem +litem &72 pos 4 dimension 50 uid 226,0 ) -*87 (MRCItem -litem &69 +*91 (MRCItem +litem &73 pos 5 dimension 50 uid 227,0 ) -*88 (MRCItem -litem &70 +*92 (MRCItem +litem &74 pos 6 dimension 80 @@ -710,21 +747,21 @@ (vvPair variable "HDLDir" -value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hdl" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" ) (vvPair variable "HDSDir" -value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair variable "SideDataDesignDir" -value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.info" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.info" ) (vvPair variable "SideDataUserDir" -value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.user" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.user" ) (vvPair variable "SourceDir" -value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair @@ -742,25 +779,25 @@ (vvPair variable "d" -value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager" ) (vvPair variable "d_logical" -value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager" ) (vvPair variable "date" -value "07.05.2010" +value "12.07.2010" ) (vvPair variable "day" -value "Fr" +value "Mo" ) (vvPair variable "day_long" -value "Freitag" +value "Montag" ) (vvPair variable "dd" -value "07" +value "12" ) (vvPair @@ -790,5 +827,5 @@ (vvPair variable "host" -value "E5PCXX" +value "TU-CC4900F8C7D2" ) (vvPair @@ -818,5 +855,5 @@ (vvPair variable "mm" -value "05" +value "07" ) (vvPair @@ -826,17 +863,17 @@ (vvPair variable "month" -value "Mai" +value "Jul" ) (vvPair variable "month_long" -value "Mai" +value "Juli" ) (vvPair variable "p" -value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb" ) (vvPair variable "p_logical" -value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb" ) (vvPair @@ -858,9 +895,9 @@ (vvPair variable "task_LeonardoPath" -value "$HDS_HOME/../Exemplar/bin/win32" +value "" ) (vvPair variable "task_ModelSimPath" -value "D:\\Programme\\FPGAdv82LSPS\\Modeltech\\win32" +value "" ) (vvPair @@ -870,5 +907,5 @@ (vvPair variable "task_PrecisionRTLPath" -value "$HDS_HOME/../Precision/Mgc_home/bin" +value "" ) (vvPair @@ -894,5 +931,5 @@ (vvPair variable "time" -value "12:45:37" +value "14:11:44" ) (vvPair @@ -902,9 +939,9 @@ (vvPair variable "user" -value "kai" +value "dneise" ) (vvPair variable "version" -value "2009.1 (Build 12)" +value "2009.2 (Build 10)" ) (vvPair @@ -925,8 +962,8 @@ uid 172,0 optionalChildren [ -*89 (SymbolBody +*93 (SymbolBody uid 8,0 optionalChildren [ -*90 (CptPort +*94 (CptPort uid 48,0 ps "OnEdgeStrategy" @@ -974,5 +1011,5 @@ ) ) -*91 (CptPort +*95 (CptPort uid 58,0 ps "OnEdgeStrategy" @@ -1023,5 +1060,5 @@ ) ) -*92 (CptPort +*96 (CptPort uid 63,0 ps "OnEdgeStrategy" @@ -1070,5 +1107,5 @@ ) ) -*93 (CptPort +*97 (CptPort uid 68,0 ps "OnEdgeStrategy" @@ -1120,5 +1157,5 @@ ) ) -*94 (CptPort +*98 (CptPort uid 73,0 ps "OnEdgeStrategy" @@ -1168,5 +1205,5 @@ ) ) -*95 (CptPort +*99 (CptPort uid 78,0 ps "OnEdgeStrategy" @@ -1215,5 +1252,5 @@ ) ) -*96 (CptPort +*100 (CptPort uid 83,0 ps "OnEdgeStrategy" @@ -1262,5 +1299,5 @@ ) ) -*97 (CptPort +*101 (CptPort uid 88,0 ps "OnEdgeStrategy" @@ -1311,5 +1348,5 @@ ) ) -*98 (CptPort +*102 (CptPort uid 93,0 ps "OnEdgeStrategy" @@ -1360,5 +1397,5 @@ ) ) -*99 (CptPort +*103 (CptPort uid 118,0 ps "OnEdgeStrategy" @@ -1408,5 +1445,5 @@ ) ) -*100 (CptPort +*104 (CptPort uid 123,0 ps "OnEdgeStrategy" @@ -1440,6 +1477,6 @@ font "Courier New,8,0" ) -xt "2000,23000,25000,23800" -st "roi_array : OUT roi_array_type +xt "2000,23000,26000,23800" +st "roi_array : OUT roi_array_type ; " ) @@ -1456,5 +1493,5 @@ ) ) -*101 (CptPort +*105 (CptPort uid 263,0 ps "OnEdgeStrategy" @@ -1503,5 +1540,5 @@ ) ) -*102 (CptPort +*106 (CptPort uid 268,0 ps "OnEdgeStrategy" @@ -1550,5 +1587,5 @@ ) ) -*103 (CptPort +*107 (CptPort uid 310,0 ps "OnEdgeStrategy" @@ -1595,5 +1632,5 @@ ) ) -*104 (CptPort +*108 (CptPort uid 346,0 ps "OnEdgeStrategy" @@ -1642,5 +1679,5 @@ ) ) -*105 (CptPort +*109 (CptPort uid 492,0 ps "OnEdgeStrategy" @@ -1689,4 +1726,97 @@ ) ) +*110 (CptPort +uid 528,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 529,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,32625,67750,33375" +) +tg (CPTG +uid 530,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 531,0 +va (VaSet +) +xt "58800,32500,66000,33500" +st "drs_address : (3:0)" +ju 2 +blo "66000,33300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 532,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,23800,33000,24600" +st "drs_address : OUT std_logic_vector (3 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 17 +suid 24,0 +) +) +) +*111 (CptPort +uid 533,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 534,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,33625,67750,34375" +) +tg (CPTG +uid 535,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 536,0 +va (VaSet +) +xt "58800,33500,66000,34500" +st "drs_address_mode" +ju 2 +blo "66000,34300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 537,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,24600,22000,25400" +st "drs_address_mode : OUT std_logic +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 18 +suid 25,0 +) +) +) ] shape (Rectangle @@ -1698,5 +1828,5 @@ lineWidth 2 ) -xt "42000,14000,67000,33000" +xt "42000,14000,67000,35000" ) oxt "42000,14000,66000,27000" @@ -1724,5 +1854,5 @@ ) ) -gi *106 (GenericInterface +gi *112 (GenericInterface uid 13,0 ps "CenterOffsetStrategy" @@ -1769,8 +1899,8 @@ ) ) -*107 (Grouping +*113 (Grouping uid 16,0 optionalChildren [ -*108 (CommentText +*114 (CommentText uid 18,0 shape (Rectangle @@ -1803,5 +1933,5 @@ titleBlock 1 ) -*109 (CommentText +*115 (CommentText uid 21,0 shape (Rectangle @@ -1834,5 +1964,5 @@ titleBlock 1 ) -*110 (CommentText +*116 (CommentText uid 24,0 shape (Rectangle @@ -1865,5 +1995,5 @@ titleBlock 1 ) -*111 (CommentText +*117 (CommentText uid 27,0 shape (Rectangle @@ -1896,5 +2026,5 @@ titleBlock 1 ) -*112 (CommentText +*118 (CommentText uid 30,0 shape (Rectangle @@ -1926,5 +2056,5 @@ titleBlock 1 ) -*113 (CommentText +*119 (CommentText uid 33,0 shape (Rectangle @@ -1957,5 +2087,5 @@ titleBlock 1 ) -*114 (CommentText +*120 (CommentText uid 36,0 shape (Rectangle @@ -1989,5 +2119,5 @@ titleBlock 1 ) -*115 (CommentText +*121 (CommentText uid 39,0 shape (Rectangle @@ -2020,5 +2150,5 @@ titleBlock 1 ) -*116 (CommentText +*122 (CommentText uid 42,0 shape (Rectangle @@ -2051,5 +2181,5 @@ titleBlock 1 ) -*117 (CommentText +*123 (CommentText uid 45,0 shape (Rectangle @@ -2095,5 +2225,5 @@ oxt "14000,66000,55000,71000" ) -*118 (CommentText +*124 (CommentText uid 134,0 shape (Rectangle @@ -2138,9 +2268,9 @@ color "26368,26368,26368" ) -packageList *119 (PackageList +packageList *125 (PackageList uid 169,0 stg "VerticalLayoutStrategy" textVec [ -*120 (Text +*126 (Text uid 170,0 va (VaSet @@ -2151,5 +2281,5 @@ blo "0,1800" ) -*121 (MLText +*127 (MLText uid 171,0 va (VaSet @@ -2252,5 +2382,5 @@ ) ) -gi *122 (GenericInterface +gi *128 (GenericInterface ps "CenterOffsetStrategy" matrix (Matrix @@ -2349,5 +2479,5 @@ ) ) -DeclarativeBlock *123 (SymDeclBlock +DeclarativeBlock *129 (SymDeclBlock uid 1,0 stg "SymDeclLayoutStrategy" @@ -2375,7 +2505,7 @@ font "Arial,8,1" ) -xt "0,23800,2400,24800" +xt "0,25400,2400,26400" st "User:" -blo "0,24600" +blo "0,26200" ) internalLabel (Text @@ -2394,5 +2524,5 @@ font "Courier New,8,0" ) -xt "2000,24800,2000,24800" +xt "2000,26400,2000,26400" tm "SyDeclarativeTextMgr" ) @@ -2407,5 +2537,5 @@ ) ) -lastUid 504,0 +lastUid 547,0 activeModelName "Symbol:CDM" ) Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd (revision 252) @@ -60,5 +60,5 @@ ) version "29.1" -appVersion "2009.1 (Build 12)" +appVersion "2009.2 (Build 10)" noEmbeddedEditors 1 model (BlockDiag @@ -67,21 +67,21 @@ (vvPair variable "HDLDir" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hdl" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" ) (vvPair variable "HDSDir" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair variable "SideDataDesignDir" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info" ) (vvPair variable "SideDataUserDir" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user" ) (vvPair variable "SourceDir" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair @@ -99,25 +99,25 @@ (vvPair variable "d" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" ) (vvPair variable "d_logical" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" ) (vvPair variable "date" -value "27.05.2010" +value "12.07.2010" ) (vvPair variable "day" -value "Do" +value "Mo" ) (vvPair variable "day_long" -value "Donnerstag" +value "Montag" ) (vvPair variable "dd" -value "27" +value "12" ) (vvPair @@ -147,5 +147,5 @@ (vvPair variable "host" -value "IHP110" +value "TU-CC4900F8C7D2" ) (vvPair @@ -175,5 +175,5 @@ (vvPair variable "mm" -value "05" +value "07" ) (vvPair @@ -183,17 +183,17 @@ (vvPair variable "month" -value "Mai" +value "Jul" ) (vvPair variable "month_long" -value "Mai" +value "Juli" ) (vvPair variable "p" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd" ) (vvPair variable "p_logical" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd" ) (vvPair @@ -219,5 +219,5 @@ (vvPair variable "task_ModelSimPath" -value "D:\\modeltech_6.5e\\win32" +value "" ) (vvPair @@ -251,5 +251,5 @@ (vvPair variable "time" -value "10:24:05" +value "14:13:34" ) (vvPair @@ -259,9 +259,9 @@ (vvPair variable "user" -value "daqct3" +value "dneise" ) (vvPair variable "version" -value "2009.1 (Build 12)" +value "2009.2 (Build 10)" ) (vvPair @@ -303,5 +303,5 @@ bg "0,0,32768" ) -xt "16200,76000,25900,77000" +xt "16200,76000,25500,77000" st " by %user on %dd %month %year @@ -621,6 +621,7 @@ font "Courier New,8,0" ) -xt "22000,2000,38000,2800" -st "clk : STD_LOGIC" +xt "29000,2200,45000,3000" +st "clk : STD_LOGIC +" ) ) @@ -639,6 +640,7 @@ font "Courier New,8,0" ) -xt "22000,15000,51500,15800" -st "SIGNAL ram_wren : std_logic_VECTOR(0 DOWNTO 0)" +xt "29000,16800,58500,17600" +st "SIGNAL ram_wren : std_logic_VECTOR(0 DOWNTO 0) +" ) ) @@ -657,6 +659,7 @@ font "Courier New,8,0" ) -xt "22000,2800,48000,3600" -st "config_addr : std_logic_vector(7 DOWNTO 0)" +xt "29000,3000,55000,3800" +st "config_addr : std_logic_vector(7 DOWNTO 0) +" ) ) @@ -675,6 +678,7 @@ font "Courier New,8,0" ) -xt "22000,13400,52000,14200" -st "SIGNAL ram_data_in : std_logic_VECTOR(15 DOWNTO 0)" +xt "29000,15200,59000,16000" +st "SIGNAL ram_data_in : std_logic_VECTOR(15 DOWNTO 0) +" ) ) @@ -692,6 +696,7 @@ font "Courier New,8,0" ) -xt "22000,6800,38000,7600" -st "config_data_valid : std_logic" +xt "29000,7000,45000,7800" +st "config_data_valid : std_logic +" ) ) @@ -709,6 +714,7 @@ font "Courier New,8,0" ) -xt "22000,6000,38000,6800" -st "config_busy : std_logic" +xt "29000,6200,45000,7000" +st "config_busy : std_logic +" ) ) @@ -727,6 +733,7 @@ font "Courier New,8,0" ) -xt "22000,10800,48500,11600" -st "config_data : std_logic_vector(15 DOWNTO 0)" +xt "29000,12600,55500,13400" +st "config_data : std_logic_vector(15 DOWNTO 0) +" ) ) @@ -744,6 +751,7 @@ font "Courier New,8,0" ) -xt "22000,10000,40500,10800" -st "roi_array : roi_array_type" +xt "29000,11800,47500,12600" +st "roi_array : roi_array_type +" ) ) @@ -762,6 +770,7 @@ font "Courier New,8,0" ) -xt "22000,12600,51500,13400" -st "SIGNAL ram_addr : std_logic_VECTOR(7 DOWNTO 0)" +xt "29000,14400,58500,15200" +st "SIGNAL ram_addr : std_logic_VECTOR(7 DOWNTO 0) +" ) ) @@ -779,6 +788,7 @@ font "Courier New,8,0" ) -xt "22000,5200,38000,6000" -st "config_wr_en : std_logic" +xt "29000,5400,45000,6200" +st "config_wr_en : std_logic +" ) ) @@ -797,6 +807,7 @@ font "Courier New,8,0" ) -xt "22000,14200,52000,15000" -st "SIGNAL ram_data_out : std_logic_VECTOR(15 DOWNTO 0)" +xt "29000,16000,59000,16800" +st "SIGNAL ram_data_out : std_logic_VECTOR(15 DOWNTO 0) +" ) ) @@ -814,6 +825,7 @@ font "Courier New,8,0" ) -xt "22000,9200,40500,10000" -st "dac_array : dac_array_type" +xt "29000,9400,47500,10200" +st "dac_array : dac_array_type +" ) ) @@ -831,6 +843,7 @@ font "Courier New,8,0" ) -xt "22000,3600,38000,4400" -st "config_rd_en : std_logic" +xt "29000,3800,45000,4600" +st "config_rd_en : std_logic +" ) ) @@ -848,6 +861,7 @@ font "Courier New,8,0" ) -xt "22000,4400,38000,5200" -st "config_start : std_logic" +xt "29000,4600,45000,5400" +st "config_start : std_logic +" ) ) @@ -865,6 +879,7 @@ font "Courier New,8,0" ) -xt "22000,7600,38000,8400" -st "config_ready : std_logic" +xt "29000,7800,45000,8600" +st "config_ready : std_logic +" ) ) @@ -882,5 +897,5 @@ sl 0 ro 270 -xt "3000,23625,4500,24375" +xt "2000,19625,3500,20375" ) (Line @@ -888,8 +903,8 @@ sl 0 ro 270 -xt "4500,24000,5000,24000" +xt "3500,20000,4000,20000" pts [ -"4500,24000" -"5000,24000" +"3500,20000" +"4000,20000" ] ) @@ -906,8 +921,8 @@ va (VaSet ) -xt "700,23500,2000,24500" +xt "700,19500,2000,20500" st "clk" ju 2 -blo "2000,24300" +blo "2000,20300" tm "WireNameMgr" ) @@ -927,5 +942,5 @@ sl 0 ro 270 -xt "42500,28625,44000,29375" +xt "36500,28625,38000,29375" ) (Line @@ -933,8 +948,8 @@ sl 0 ro 270 -xt "42000,29000,42500,29000" +xt "36000,29000,36500,29000" pts [ -"42000,29000" -"42500,29000" +"36000,29000" +"36500,29000" ] ) @@ -951,7 +966,7 @@ va (VaSet ) -xt "45000,28500,50100,29500" +xt "39000,28500,44100,29500" st "config_ready" -blo "45000,29300" +blo "39000,29300" tm "WireNameMgr" ) @@ -971,5 +986,5 @@ sl 0 ro 90 -xt "42500,29625,44000,30375" +xt "36500,29625,38000,30375" ) (Line @@ -977,8 +992,8 @@ sl 0 ro 90 -xt "42000,30000,42500,30000" +xt "36000,30000,36500,30000" pts [ -"42500,30000" -"42000,30000" +"36500,30000" +"36000,30000" ] ) @@ -995,7 +1010,7 @@ va (VaSet ) -xt "45000,29500,49800,30500" +xt "39000,29500,43800,30500" st "config_start" -blo "45000,30300" +blo "39000,30300" tm "WireNameMgr" ) @@ -1014,13 +1029,13 @@ uid 381,0 sl 0 -xt "42500,24625,44000,25375" +xt "36500,24625,38000,25375" ) (Line uid 382,0 sl 0 -xt "42000,25000,42500,25000" +xt "36000,25000,36500,25000" pts [ -"42000,25000" -"42500,25000" +"36000,25000" +"36500,25000" ] ) @@ -1037,7 +1052,7 @@ va (VaSet ) -xt "45000,24500,49700,25500" +xt "39000,24500,43700,25500" st "config_data" -blo "45000,25300" +blo "39000,25300" tm "WireNameMgr" ) @@ -1057,5 +1072,5 @@ sl 0 ro 90 -xt "42500,23625,44000,24375" +xt "36500,23625,38000,24375" ) (Line @@ -1063,8 +1078,8 @@ sl 0 ro 90 -xt "42000,24000,42500,24000" +xt "36000,24000,36500,24000" pts [ -"42500,24000" -"42000,24000" +"36500,24000" +"36000,24000" ] ) @@ -1081,7 +1096,7 @@ va (VaSet ) -xt "45000,23500,49800,24500" +xt "39000,23500,43800,24500" st "config_addr" -blo "45000,24300" +blo "39000,24300" tm "WireNameMgr" ) @@ -1101,5 +1116,5 @@ sl 0 ro 90 -xt "42500,26625,44000,27375" +xt "36500,26625,38000,27375" ) (Line @@ -1107,8 +1122,8 @@ sl 0 ro 90 -xt "42000,27000,42500,27000" +xt "36000,27000,36500,27000" pts [ -"42500,27000" -"42000,27000" +"36500,27000" +"36000,27000" ] ) @@ -1125,7 +1140,7 @@ va (VaSet ) -xt "45000,26500,50300,27500" +xt "39000,26500,44300,27500" st "config_wr_en" -blo "45000,27300" +blo "39000,27300" tm "WireNameMgr" ) @@ -1145,5 +1160,5 @@ sl 0 ro 90 -xt "42500,27625,44000,28375" +xt "36500,27625,38000,28375" ) (Line @@ -1151,8 +1166,8 @@ sl 0 ro 90 -xt "42000,28000,42500,28000" +xt "36000,28000,36500,28000" pts [ -"42500,28000" -"42000,28000" +"36500,28000" +"36000,28000" ] ) @@ -1169,7 +1184,7 @@ va (VaSet ) -xt "45000,27500,50200,28500" +xt "39000,27500,44200,28500" st "config_rd_en" -blo "45000,28300" +blo "39000,28300" tm "WireNameMgr" ) @@ -1189,5 +1204,5 @@ sl 0 ro 270 -xt "42500,33625,44000,34375" +xt "36500,33625,38000,34375" ) (Line @@ -1195,8 +1210,8 @@ sl 0 ro 270 -xt "42000,34000,42500,34000" +xt "36000,34000,36500,34000" pts [ -"42000,34000" -"42500,34000" +"36000,34000" +"36500,34000" ] ) @@ -1213,7 +1228,7 @@ va (VaSet ) -xt "45000,33500,48700,34500" +xt "39000,33500,42700,34500" st "dac_array" -blo "45000,34300" +blo "39000,34300" tm "WireNameMgr" ) @@ -1233,5 +1248,5 @@ sl 0 ro 270 -xt "42500,34625,44000,35375" +xt "36500,34625,38000,35375" ) (Line @@ -1239,8 +1254,8 @@ sl 0 ro 270 -xt "42000,35000,42500,35000" +xt "36000,35000,36500,35000" pts [ -"42000,35000" -"42500,35000" +"36000,35000" +"36500,35000" ] ) @@ -1257,7 +1272,7 @@ va (VaSet ) -xt "45000,34500,48400,35500" +xt "39000,34500,42400,35500" st "roi_array" -blo "45000,35300" +blo "39000,35300" tm "WireNameMgr" ) @@ -1277,5 +1292,5 @@ sl 0 ro 270 -xt "42500,31625,44000,32375" +xt "36500,31625,38000,32375" ) (Line @@ -1283,8 +1298,8 @@ sl 0 ro 270 -xt "42000,32000,42500,32000" +xt "36000,32000,36500,32000" pts [ -"42000,32000" -"42500,32000" +"36000,32000" +"36500,32000" ] ) @@ -1301,7 +1316,7 @@ va (VaSet ) -xt "45000,31500,51600,32500" +xt "39000,31500,45600,32500" st "config_data_valid" -blo "45000,32300" +blo "39000,32300" tm "WireNameMgr" ) @@ -1321,5 +1336,5 @@ sl 0 ro 270 -xt "42500,32625,44000,33375" +xt "36500,32625,38000,33375" ) (Line @@ -1327,8 +1342,8 @@ sl 0 ro 270 -xt "42000,33000,42500,33000" +xt "36000,33000,36500,33000" pts [ -"42000,33000" -"42500,33000" +"36000,33000" +"36500,33000" ] ) @@ -1345,7 +1360,7 @@ va (VaSet ) -xt "45000,32500,49800,33500" +xt "39000,32500,43800,33500" st "config_busy" -blo "45000,33300" +blo "39000,33300" tm "WireNameMgr" ) @@ -1365,5 +1380,5 @@ fg "0,65535,0" ) -xt "12250,23625,13000,24375" +xt "6250,23625,7000,24375" ) tg (CPTG @@ -1375,7 +1390,7 @@ va (VaSet ) -xt "14000,23500,15300,24500" +xt "8000,23500,9300,24500" st "clk" -blo "14000,24300" +blo "8000,24300" ) ) @@ -1401,5 +1416,5 @@ fg "0,65535,0" ) -xt "38000,28625,38750,29375" +xt "32000,28625,32750,29375" ) tg (CPTG @@ -1411,8 +1426,8 @@ va (VaSet ) -xt "31900,28500,37000,29500" +xt "25900,28500,31000,29500" st "config_ready" ju 2 -blo "37000,29300" +blo "31000,29300" ) ) @@ -1440,5 +1455,5 @@ fg "0,65535,0" ) -xt "38000,29625,38750,30375" +xt "32000,29625,32750,30375" ) tg (CPTG @@ -1450,8 +1465,8 @@ va (VaSet ) -xt "32200,29500,37000,30500" +xt "26200,29500,31000,30500" st "config_start" ju 2 -blo "37000,30300" +blo "31000,30300" ) ) @@ -1477,5 +1492,5 @@ fg "0,65535,0" ) -xt "38000,24625,38750,25375" +xt "32000,24625,32750,25375" ) tg (CPTG @@ -1487,8 +1502,8 @@ va (VaSet ) -xt "29300,24500,37000,25500" +xt "23300,24500,31000,25500" st "config_data : (15:0)" ju 2 -blo "37000,25300" +blo "31000,25300" ) ) @@ -1517,5 +1532,5 @@ fg "0,65535,0" ) -xt "38000,23625,38750,24375" +xt "32000,23625,32750,24375" ) tg (CPTG @@ -1527,8 +1542,8 @@ va (VaSet ) -xt "23600,23500,37000,24500" +xt "17600,23500,31000,24500" st "config_addr : (ADDR_WIDTH - 1:0)" ju 2 -blo "37000,24300" +blo "31000,24300" ) ) @@ -1555,5 +1570,5 @@ fg "0,65535,0" ) -xt "38000,26625,38750,27375" +xt "32000,26625,32750,27375" ) tg (CPTG @@ -1565,8 +1580,8 @@ va (VaSet ) -xt "31700,26500,37000,27500" +xt "25700,26500,31000,27500" st "config_wr_en" ju 2 -blo "37000,27300" +blo "31000,27300" ) ) @@ -1592,5 +1607,5 @@ fg "0,65535,0" ) -xt "38000,27625,38750,28375" +xt "32000,27625,32750,28375" ) tg (CPTG @@ -1602,8 +1617,8 @@ va (VaSet ) -xt "31800,27500,37000,28500" +xt "25800,27500,31000,28500" st "config_rd_en" ju 2 -blo "37000,28300" +blo "31000,28300" ) ) @@ -1629,5 +1644,5 @@ fg "0,65535,0" ) -xt "38000,31625,38750,32375" +xt "32000,31625,32750,32375" ) tg (CPTG @@ -1639,8 +1654,8 @@ va (VaSet ) -xt "30400,31500,37000,32500" +xt "24400,31500,31000,32500" st "config_data_valid" ju 2 -blo "37000,32300" +blo "31000,32300" ) ) @@ -1668,5 +1683,5 @@ fg "0,65535,0" ) -xt "38000,32625,38750,33375" +xt "32000,32625,32750,33375" ) tg (CPTG @@ -1678,8 +1693,8 @@ va (VaSet ) -xt "32200,32500,37000,33500" +xt "26200,32500,31000,33500" st "config_busy" ju 2 -blo "37000,33300" +blo "31000,33300" ) ) @@ -1707,5 +1722,5 @@ fg "0,65535,0" ) -xt "38000,33625,38750,34375" +xt "32000,33625,32750,34375" ) tg (CPTG @@ -1717,8 +1732,8 @@ va (VaSet ) -xt "33300,33500,37000,34500" +xt "27300,33500,31000,34500" st "dac_array" ju 2 -blo "37000,34300" +blo "31000,34300" ) ) @@ -1745,5 +1760,5 @@ fg "0,65535,0" ) -xt "38000,34625,38750,35375" +xt "32000,34625,32750,35375" ) tg (CPTG @@ -1755,8 +1770,8 @@ va (VaSet ) -xt "33600,34500,37000,35500" +xt "27600,34500,31000,35500" st "roi_array" ju 2 -blo "37000,35300" +blo "31000,35300" ) ) @@ -1783,5 +1798,5 @@ fg "0,65535,0" ) -xt "38000,37625,38750,38375" +xt "32000,37625,32750,38375" ) tg (CPTG @@ -1793,8 +1808,8 @@ va (VaSet ) -xt "29100,37500,37000,38500" +xt "23100,37500,31000,38500" st "ram_data_in : (15:0)" ju 2 -blo "37000,38300" +blo "31000,38300" ) ) @@ -1820,5 +1835,5 @@ fg "0,65535,0" ) -xt "38000,38625,38750,39375" +xt "32000,38625,32750,39375" ) tg (CPTG @@ -1830,8 +1845,8 @@ va (VaSet ) -xt "29100,38500,37000,39500" +xt "23100,38500,31000,39500" st "ram_write_en : (0:0)" ju 2 -blo "37000,39300" +blo "31000,39300" ) ) @@ -1857,5 +1872,5 @@ fg "0,65535,0" ) -xt "12250,24625,13000,25375" +xt "6250,38625,7000,39375" ) tg (CPTG @@ -1867,7 +1882,7 @@ va (VaSet ) -xt "14000,24500,22300,25500" +xt "8000,38500,16300,39500" st "ram_data_out : (15:0)" -blo "14000,25300" +blo "8000,39300" ) ) @@ -1892,5 +1907,5 @@ fg "0,65535,0" ) -xt "38000,39625,38750,40375" +xt "32000,39625,32750,40375" ) tg (CPTG @@ -1902,8 +1917,8 @@ va (VaSet ) -xt "24400,39500,37000,40500" +xt "18400,39500,31000,40500" st "ram_addr : (ADDR_WIDTH - 1:0)" ju 2 -blo "37000,40300" +blo "31000,40300" ) ) @@ -1929,5 +1944,5 @@ fg "0,65535,0" ) -xt "38000,30625,38750,31375" +xt "32000,30625,32750,31375" ) tg (CPTG @@ -1939,8 +1954,8 @@ va (VaSet ) -xt "31400,30500,37000,31500" +xt "25400,30500,31000,31500" st "config_started" ju 2 -blo "37000,31300" +blo "31000,31300" ) ) @@ -1956,4 +1971,77 @@ ) ) +*55 (CptPort +uid 1198,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1199,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,21625,32750,22375" +) +tg (CPTG +uid 1200,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1201,0 +va (VaSet +) +xt "23800,21500,31000,22500" +st "drs_address : (3:0)" +ju 2 +blo "31000,22300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 17 +suid 24,0 +) +) +) +*56 (CptPort +uid 1202,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1203,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,20625,32750,21375" +) +tg (CPTG +uid 1204,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1205,0 +va (VaSet +) +xt "23800,20500,31000,21500" +st "drs_address_mode" +ju 2 +blo "31000,21300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 18 +suid 25,0 +) +) +) ] shape (Rectangle @@ -1965,5 +2053,5 @@ lineWidth 2 ) -xt "13000,23000,38000,42000" +xt "7000,20000,32000,41000" ) oxt "42000,14000,67000,32000" @@ -1973,32 +2061,32 @@ stg "VerticalLayoutStrategy" textVec [ -*55 (Text +*57 (Text uid 963,0 va (VaSet font "Arial,8,1" ) -xt "12950,42000,19150,43000" +xt "6950,42000,13150,43000" st "FACT_FAD_lib" -blo "12950,42800" +blo "6950,42800" tm "BdLibraryNameMgr" ) -*56 (Text +*58 (Text uid 964,0 va (VaSet font "Arial,8,1" ) -xt "12950,43000,20050,44000" +xt "6950,43000,14050,44000" st "control_manager" -blo "12950,43800" +blo "6950,43800" tm "CptNameMgr" ) -*57 (Text +*59 (Text uid 965,0 va (VaSet font "Arial,8,1" ) -xt "12950,44000,20650,45000" +xt "6950,44000,14650,45000" st "I_control_manager" -blo "12950,44800" +blo "6950,44800" tm "InstanceNameMgr" ) @@ -2015,5 +2103,5 @@ font "Courier New,8,0" ) -xt "12500,10600,30000,13000" +xt "10000,17600,27500,20000" st "NO_OF_ROI = 36 ( integer ) NO_OF_DAC = 8 ( integer ) @@ -2047,5 +2135,5 @@ fg "49152,49152,49152" ) -xt "13250,40250,14750,41750" +xt "7250,39250,8750,40750" iconName "VhdlFileViewIcon.png" iconMaskName "VhdlFileViewIcon.msk" @@ -2058,30 +2146,32 @@ archFileType "UNKNOWN" ) -*58 (SaComponent +*60 (SaComponent uid 993,0 optionalChildren [ -*59 (CptPort +*61 (CptPort uid 970,0 ps "OnEdgeStrategy" shape (Triangle uid 971,0 -ro 90 +ro 180 va (VaSet vasetType 1 fg "0,65535,0" ) -xt "19250,50625,20000,51375" +xt "42625,41250,43375,42000" ) tg (CPTG uid 972,0 ps "CptPortTextPlaceStrategy" -stg "VerticalLayoutStrategy" +stg "RightVerticalLayoutStrategy" f (Text uid 973,0 -va (VaSet -) -xt "21000,50500,22700,51500" +ro 270 +va (VaSet +) +xt "42500,43000,43500,44700" st "clka" -blo "21000,51300" +ju 2 +blo "43300,43000" ) ) @@ -2097,5 +2187,5 @@ ) ) -*60 (CptPort +*62 (CptPort uid 974,0 ps "OnEdgeStrategy" @@ -2107,5 +2197,5 @@ fg "0,65535,0" ) -xt "19250,52625,20000,53375" +xt "39250,45625,40000,46375" ) tg (CPTG @@ -2117,7 +2207,7 @@ va (VaSet ) -xt "21000,52500,25800,53500" +xt "41000,45500,45800,46500" st "dina : (15:0)" -blo "21000,53300" +blo "41000,46300" ) ) @@ -2134,5 +2224,5 @@ ) ) -*61 (CptPort +*63 (CptPort uid 978,0 ps "OnEdgeStrategy" @@ -2144,5 +2234,5 @@ fg "0,65535,0" ) -xt "19250,54625,20000,55375" +xt "39250,47625,40000,48375" ) tg (CPTG @@ -2154,7 +2244,7 @@ va (VaSet ) -xt "21000,54500,25900,55500" +xt "41000,47500,45900,48500" st "addra : (7:0)" -blo "21000,55300" +blo "41000,48300" ) ) @@ -2171,5 +2261,5 @@ ) ) -*62 (CptPort +*64 (CptPort uid 982,0 ps "OnEdgeStrategy" @@ -2181,5 +2271,5 @@ fg "0,65535,0" ) -xt "19250,53625,20000,54375" +xt "39250,46625,40000,47375" ) tg (CPTG @@ -2191,7 +2281,7 @@ va (VaSet ) -xt "21000,53500,25300,54500" +xt "41000,46500,45300,47500" st "wea : (0:0)" -blo "21000,54300" +blo "41000,47300" ) ) @@ -2208,5 +2298,5 @@ ) ) -*63 (CptPort +*65 (CptPort uid 986,0 ps "OnEdgeStrategy" @@ -2218,5 +2308,5 @@ fg "0,65535,0" ) -xt "30000,50625,30750,51375" +xt "50000,43625,50750,44375" ) tg (CPTG @@ -2228,8 +2318,8 @@ va (VaSet ) -xt "23800,50500,29000,51500" +xt "43800,43500,49000,44500" st "douta : (15:0)" ju 2 -blo "29000,51300" +blo "49000,44300" ) ) @@ -2256,5 +2346,5 @@ lineWidth 2 ) -xt "20000,49000,30000,59000" +xt "40000,42000,50000,52000" ) oxt "30000,7000,40000,17000" @@ -2264,32 +2354,32 @@ stg "VerticalLayoutStrategy" textVec [ -*64 (Text +*66 (Text uid 996,0 va (VaSet font "Arial,8,1" ) -xt "20200,59000,26400,60000" +xt "40200,52000,46400,53000" st "FACT_FAD_lib" -blo "20200,59800" +blo "40200,52800" tm "BdLibraryNameMgr" ) -*65 (Text +*67 (Text uid 997,0 va (VaSet font "Arial,8,1" ) -xt "20200,60000,30100,61000" +xt "40200,53000,50100,54000" st "controlRAM_16bit_x256" -blo "20200,60800" +blo "40200,53800" tm "CptNameMgr" ) -*66 (Text +*68 (Text uid 998,0 va (VaSet font "Arial,8,1" ) -xt "20200,61000,26100,62000" +xt "40200,54000,46100,55000" st "I_control_ram" -blo "20200,61800" +blo "40200,54800" tm "InstanceNameMgr" ) @@ -2306,5 +2396,5 @@ font "Courier New,8,0" ) -xt "19500,48000,19500,48000" +xt "39500,41000,39500,41000" ) header "" @@ -2320,5 +2410,5 @@ fg "49152,49152,49152" ) -xt "20250,57250,21750,58750" +xt "40250,50250,41750,51750" iconName "VhdlFileViewIcon.png" iconMaskName "VhdlFileViewIcon.msk" @@ -2332,5 +2422,5 @@ archFileType "UNKNOWN" ) -*67 (Net +*69 (Net uid 1082,0 decl (Decl @@ -2346,9 +2436,10 @@ font "Courier New,8,0" ) -xt "22000,8400,41500,9200" -st "config_started : std_logic := '0'" -) -) -*68 (PortIoOut +xt "29000,8600,48500,9400" +st "config_started : std_logic := '0' +" +) +) +*70 (PortIoOut uid 1090,0 shape (CompositeShape @@ -2363,5 +2454,5 @@ sl 0 ro 270 -xt "42500,30625,44000,31375" +xt "36500,30625,38000,31375" ) (Line @@ -2369,8 +2460,8 @@ sl 0 ro 270 -xt "42000,31000,42500,31000" +xt "36000,31000,36500,31000" pts [ -"42000,31000" -"42500,31000" +"36000,31000" +"36500,31000" ] ) @@ -2387,12 +2478,137 @@ va (VaSet ) -xt "45000,30500,50600,31500" +xt "39000,30500,44600,31500" st "config_started" -blo "45000,31300" +blo "39000,31300" tm "WireNameMgr" ) ) ) -*69 (Wire +*71 (Net +uid 1206,0 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 17 +suid 19,0 +) +declText (MLText +uid 1207,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,10200,55000,11000" +st "drs_address : std_logic_vector(3 DOWNTO 0) +" +) +) +*72 (PortIoOut +uid 1214,0 +shape (CompositeShape +uid 1215,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 1216,0 +sl 0 +ro 270 +xt "36500,21625,38000,22375" +) +(Line +uid 1217,0 +sl 0 +ro 270 +xt "36000,22000,36500,22000" +pts [ +"36000,22000" +"36500,22000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 1218,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1219,0 +va (VaSet +) +xt "39000,21500,44000,22500" +st "drs_address" +blo "39000,22300" +tm "WireNameMgr" +) +) +) +*73 (Net +uid 1220,0 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 18 +suid 20,0 +) +declText (MLText +uid 1221,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,11000,45000,11800" +st "drs_address_mode : std_logic +" +) +) +*74 (PortIoOut +uid 1228,0 +shape (CompositeShape +uid 1229,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 1230,0 +sl 0 +ro 270 +xt "36500,20625,38000,21375" +) +(Line +uid 1231,0 +sl 0 +ro 270 +xt "36000,21000,36500,21000" +pts [ +"36000,21000" +"36500,21000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 1232,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1233,0 +va (VaSet +) +xt "39000,20500,46200,21500" +st "drs_address_mode" +blo "39000,21300" +tm "WireNameMgr" +) +) +) +*75 (Wire uid 227,0 shape (OrthoPolyLine @@ -2402,9 +2618,8 @@ lineWidth 2 ) -xt "38750,24000,42000,24000" +xt "32750,24000,36000,24000" pts [ -"42000,24000" -"40000,24000" -"38750,24000" +"36000,24000" +"32750,24000" ] ) @@ -2427,7 +2642,7 @@ isHidden 1 ) -xt "45000,23000,49800,24000" +xt "39000,23000,43800,24000" st "config_addr" -blo "45000,23800" +blo "39000,23800" tm "WireNameMgr" ) @@ -2435,5 +2650,5 @@ on &14 ) -*70 (Wire +*76 (Wire uid 233,0 shape (OrthoPolyLine @@ -2443,15 +2658,13 @@ lineWidth 2 ) -xt "13000,39000,43000,54000" +xt "32750,39000,39250,47000" pts [ -"19250,54000" -"13000,54000" -"13000,47000" -"43000,47000" -"43000,39000" -"38750,39000" -] -) -start &62 +"39250,47000" +"34000,47000" +"34000,39000" +"32750,39000" +] +) +start &64 end &51 sat 32 @@ -2469,7 +2682,7 @@ va (VaSet ) -xt "23000,46000,29300,47000" +xt "34000,46000,40300,47000" st "ram_wren : (0:0)" -blo "23000,46800" +blo "34000,46800" tm "WireNameMgr" ) @@ -2477,5 +2690,5 @@ on &13 ) -*71 (Wire +*77 (Wire uid 237,0 shape (OrthoPolyLine @@ -2485,15 +2698,13 @@ lineWidth 2 ) -xt "14000,38000,44000,53000" +xt "32750,38000,39250,46000" pts [ -"19250,53000" -"14000,53000" -"14000,48000" -"44000,48000" -"44000,38000" -"38750,38000" -] -) -start &60 +"39250,46000" +"35000,46000" +"35000,38000" +"32750,38000" +] +) +start &62 end &50 sat 32 @@ -2511,7 +2722,7 @@ va (VaSet ) -xt "23000,47000,30900,48000" +xt "33000,37000,40900,38000" st "ram_data_in : (15:0)" -blo "23000,47800" +blo "33000,37800" tm "WireNameMgr" ) @@ -2519,5 +2730,5 @@ on &15 ) -*72 (Wire +*78 (Wire uid 241,0 shape (OrthoPolyLine @@ -2526,8 +2737,10 @@ vasetType 3 ) -xt "5000,24000,12250,24000" +xt "4000,20000,6250,24000" pts [ +"4000,20000" +"5000,20000" "5000,24000" -"12250,24000" +"6250,24000" ] ) @@ -2549,7 +2762,7 @@ isHidden 1 ) -xt "7000,23000,8300,24000" +xt "6000,19000,7300,20000" st "clk" -blo "7000,23800" +blo "6000,19800" tm "WireNameMgr" ) @@ -2557,5 +2770,5 @@ on &12 ) -*73 (Wire +*79 (Wire uid 255,0 shape (OrthoPolyLine @@ -2564,8 +2777,8 @@ vasetType 3 ) -xt "38750,32000,42000,32000" +xt "32750,32000,36000,32000" pts [ -"38750,32000" -"42000,32000" +"32750,32000" +"36000,32000" ] ) @@ -2587,7 +2800,7 @@ isHidden 1 ) -xt "45000,30000,51600,31000" +xt "39000,30000,45600,31000" st "config_data_valid" -blo "45000,30800" +blo "39000,30800" tm "WireNameMgr" ) @@ -2595,5 +2808,5 @@ on &16 ) -*74 (Wire +*80 (Wire uid 261,0 shape (OrthoPolyLine @@ -2602,8 +2815,8 @@ vasetType 3 ) -xt "38750,33000,42000,33000" +xt "32750,33000,36000,33000" pts [ -"38750,33000" -"42000,33000" +"32750,33000" +"36000,33000" ] ) @@ -2625,7 +2838,7 @@ isHidden 1 ) -xt "45000,31000,49800,32000" +xt "39000,31000,43800,32000" st "config_busy" -blo "45000,31800" +blo "39000,31800" tm "WireNameMgr" ) @@ -2633,5 +2846,5 @@ on &17 ) -*75 (Wire +*81 (Wire uid 267,0 shape (OrthoPolyLine @@ -2641,9 +2854,8 @@ lineWidth 2 ) -xt "38750,25000,42000,25000" +xt "32750,25000,36000,25000" pts [ -"42000,25000" -"40000,25000" -"38750,25000" +"36000,25000" +"32750,25000" ] ) @@ -2666,7 +2878,7 @@ isHidden 1 ) -xt "45000,24000,49700,25000" +xt "39000,24000,43700,25000" st "config_data" -blo "45000,24800" +blo "39000,24800" tm "WireNameMgr" ) @@ -2674,5 +2886,5 @@ on &18 ) -*76 (Wire +*82 (Wire uid 273,0 shape (OrthoPolyLine @@ -2681,9 +2893,8 @@ vasetType 3 ) -xt "38750,35000,42000,35000" +xt "32750,35000,36000,35000" pts [ -"38750,35000" -"40000,35000" -"42000,35000" +"32750,35000" +"36000,35000" ] ) @@ -2705,7 +2916,7 @@ isHidden 1 ) -xt "45000,34000,48400,35000" +xt "39000,34000,42400,35000" st "roi_array" -blo "45000,34800" +blo "39000,34800" tm "WireNameMgr" ) @@ -2713,5 +2924,5 @@ on &19 ) -*77 (Wire +*83 (Wire uid 279,0 shape (OrthoPolyLine @@ -2720,11 +2931,11 @@ vasetType 3 ) -xt "17000,51000,19250,51000" +xt "43000,38000,43000,41250" pts [ -"17000,51000" -"19250,51000" -] -) -end &59 +"43000,38000" +"43000,41250" +] +) +end &61 sat 16 eat 32 @@ -2740,7 +2951,7 @@ va (VaSet ) -xt "18000,50000,19300,51000" +xt "44000,37000,45300,38000" st "clk" -blo "18000,50800" +blo "44000,37800" tm "WireNameMgr" ) @@ -2748,5 +2959,5 @@ on &12 ) -*78 (Wire +*84 (Wire uid 285,0 shape (OrthoPolyLine @@ -2756,16 +2967,14 @@ lineWidth 2 ) -xt "12000,40000,42000,55000" +xt "32750,40000,39250,48000" pts [ -"38750,40000" -"42000,40000" -"42000,46000" -"12000,46000" -"12000,55000" -"19250,55000" +"32750,40000" +"33000,40000" +"33000,48000" +"39250,48000" ] ) start &53 -end &61 +end &63 sat 32 eat 32 @@ -2782,7 +2991,7 @@ va (VaSet ) -xt "23000,45000,29200,46000" +xt "33000,47000,39200,48000" st "ram_addr : (7:0)" -blo "23000,45800" +blo "33000,47800" tm "WireNameMgr" ) @@ -2790,5 +2999,5 @@ on &20 ) -*79 (Wire +*85 (Wire uid 289,0 shape (OrthoPolyLine @@ -2797,9 +3006,8 @@ vasetType 3 ) -xt "38750,30000,42000,30000" +xt "32750,30000,36000,30000" pts [ -"42000,30000" -"40000,30000" -"38750,30000" +"36000,30000" +"32750,30000" ] ) @@ -2821,7 +3029,7 @@ isHidden 1 ) -xt "45000,29000,49800,30000" +xt "39000,29000,43800,30000" st "config_start" -blo "45000,29800" +blo "39000,29800" tm "WireNameMgr" ) @@ -2829,5 +3037,5 @@ on &25 ) -*80 (Wire +*86 (Wire uid 295,0 shape (OrthoPolyLine @@ -2836,9 +3044,8 @@ vasetType 3 ) -xt "38750,27000,42000,27000" +xt "32750,27000,36000,27000" pts [ -"42000,27000" -"40000,27000" -"38750,27000" +"36000,27000" +"32750,27000" ] ) @@ -2860,7 +3067,7 @@ isHidden 1 ) -xt "45000,26000,50300,27000" +xt "39000,26000,44300,27000" st "config_wr_en" -blo "45000,26800" +blo "39000,26800" tm "WireNameMgr" ) @@ -2868,5 +3075,5 @@ on &21 ) -*81 (Wire +*87 (Wire uid 301,0 shape (OrthoPolyLine @@ -2876,16 +3083,16 @@ lineWidth 2 ) -xt "9000,25000,34000,64000" +xt "3000,39000,52000,56000" pts [ -"12250,25000" -"9000,25000" -"9000,64000" -"34000,64000" -"34000,51000" -"30750,51000" +"6250,39000" +"3000,39000" +"3000,56000" +"52000,56000" +"52000,44000" +"50750,44000" ] ) start &52 -end &63 +end &65 sat 32 eat 32 @@ -2902,7 +3109,7 @@ va (VaSet ) -xt "20000,63000,28300,64000" +xt "33000,55000,41300,56000" st "ram_data_out : (15:0)" -blo "20000,63800" +blo "33000,55800" tm "WireNameMgr" ) @@ -2910,5 +3117,5 @@ on &22 ) -*82 (Wire +*88 (Wire uid 305,0 shape (OrthoPolyLine @@ -2917,9 +3124,8 @@ vasetType 3 ) -xt "38750,34000,42000,34000" +xt "32750,34000,36000,34000" pts [ -"38750,34000" -"40000,34000" -"42000,34000" +"32750,34000" +"36000,34000" ] ) @@ -2941,7 +3147,7 @@ isHidden 1 ) -xt "45000,33000,48700,34000" +xt "39000,33000,42700,34000" st "dac_array" -blo "45000,33800" +blo "39000,33800" tm "WireNameMgr" ) @@ -2949,5 +3155,5 @@ on &23 ) -*83 (Wire +*89 (Wire uid 311,0 shape (OrthoPolyLine @@ -2956,9 +3162,8 @@ vasetType 3 ) -xt "38750,28000,42000,28000" +xt "32750,28000,36000,28000" pts [ -"42000,28000" -"40000,28000" -"38750,28000" +"36000,28000" +"32750,28000" ] ) @@ -2980,7 +3185,7 @@ isHidden 1 ) -xt "45000,27000,50200,28000" +xt "39000,27000,44200,28000" st "config_rd_en" -blo "45000,27800" +blo "39000,27800" tm "WireNameMgr" ) @@ -2988,5 +3193,5 @@ on &24 ) -*84 (Wire +*90 (Wire uid 321,0 shape (OrthoPolyLine @@ -2995,9 +3200,8 @@ vasetType 3 ) -xt "38750,29000,42000,29000" +xt "32750,29000,36000,29000" pts [ -"38750,29000" -"40000,29000" -"42000,29000" +"32750,29000" +"36000,29000" ] ) @@ -3019,7 +3223,7 @@ isHidden 1 ) -xt "45000,28000,50100,29000" +xt "39000,28000,44100,29000" st "config_ready" -blo "45000,28800" +blo "39000,28800" tm "WireNameMgr" ) @@ -3027,5 +3231,5 @@ on &26 ) -*85 (Wire +*91 (Wire uid 1084,0 shape (OrthoPolyLine @@ -3034,12 +3238,12 @@ vasetType 3 ) -xt "38750,31000,42000,31000" +xt "32750,31000,36000,31000" pts [ -"38750,31000" -"42000,31000" +"32750,31000" +"36000,31000" ] ) start &54 -end &68 +end &70 sat 32 eat 32 @@ -3057,11 +3261,89 @@ isHidden 1 ) -xt "40000,30000,45600,31000" +xt "34000,30000,39600,31000" st "config_started" -blo "40000,30800" +blo "34000,30800" tm "WireNameMgr" ) ) -on &67 +on &69 +) +*92 (Wire +uid 1208,0 +shape (OrthoPolyLine +uid 1209,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "32750,22000,36000,22000" +pts [ +"32750,22000" +"36000,22000" +] +) +start &55 +end &72 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1212,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1213,0 +va (VaSet +isHidden 1 +) +xt "34000,21000,39000,22000" +st "drs_address" +blo "34000,21800" +tm "WireNameMgr" +) +) +on &71 +) +*93 (Wire +uid 1222,0 +shape (OrthoPolyLine +uid 1223,0 +va (VaSet +vasetType 3 +) +xt "32750,21000,36000,21000" +pts [ +"32750,21000" +"36000,21000" +] +) +start &56 +end &74 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1226,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1227,0 +va (VaSet +isHidden 1 +) +xt "34000,20000,41200,21000" +st "drs_address_mode" +blo "34000,20800" +tm "WireNameMgr" +) +) +on &73 ) ] @@ -3077,22 +3359,22 @@ color "26368,26368,26368" ) -packageList *86 (PackageList +packageList *94 (PackageList uid 41,0 stg "VerticalLayoutStrategy" textVec [ -*87 (Text +*95 (Text uid 42,0 va (VaSet font "arial,8,1" ) -xt "0,0,5400,1000" +xt "1000,1000,6400,2000" st "Package List" -blo "0,800" -) -*88 (MLText +blo "1000,1800" +) +*96 (MLText uid 43,0 va (VaSet ) -xt "0,1000,15300,6000" +xt "1000,2000,16300,7000" st "LIBRARY ieee; USE ieee.std_logic_1164.ALL; @@ -3108,5 +3390,5 @@ stg "VerticalLayoutStrategy" textVec [ -*89 (Text +*97 (Text uid 45,0 va (VaSet @@ -3118,5 +3400,5 @@ blo "20000,800" ) -*90 (Text +*98 (Text uid 46,0 va (VaSet @@ -3128,5 +3410,5 @@ blo "20000,1800" ) -*91 (MLText +*99 (MLText uid 47,0 va (VaSet @@ -3138,5 +3420,5 @@ tm "BdCompilerDirectivesTextMgr" ) -*92 (Text +*100 (Text uid 48,0 va (VaSet @@ -3148,5 +3430,5 @@ blo "20000,4800" ) -*93 (MLText +*101 (MLText uid 49,0 va (VaSet @@ -3156,5 +3438,5 @@ tm "BdCompilerDirectivesTextMgr" ) -*94 (Text +*102 (Text uid 50,0 va (VaSet @@ -3166,5 +3448,5 @@ blo "20000,5800" ) -*95 (MLText +*103 (MLText uid 51,0 va (VaSet @@ -3177,7 +3459,7 @@ associable 1 ) -windowSize "0,22,1286,1024" -viewArea "834,29654,54098,72685" -cachedDiagramExtent "0,0,53000,77000" +windowSize "0,0,1281,1002" +viewArea "-6400,12000,60443,65739" +cachedDiagramExtent "700,0,59000,77000" pageSetupInfo (PageSetupInfo ptrCmd "Brother HL-5270DN series,winspool," @@ -3205,5 +3487,5 @@ hasePageBreakOrigin 1 pageBreakOrigin "0,0" -lastUid 1122,0 +lastUid 1237,0 defaultCommentText (CommentText shape (Rectangle @@ -3267,5 +3549,5 @@ stg "VerticalLayoutStrategy" textVec [ -*96 (Text +*104 (Text va (VaSet font "Arial,8,1" @@ -3276,5 +3558,5 @@ tm "BdLibraryNameMgr" ) -*97 (Text +*105 (Text va (VaSet font "Arial,8,1" @@ -3285,5 +3567,5 @@ tm "BlkNameMgr" ) -*98 (Text +*106 (Text va (VaSet font "Arial,8,1" @@ -3336,5 +3618,5 @@ stg "VerticalLayoutStrategy" textVec [ -*99 (Text +*107 (Text va (VaSet font "Arial,8,1" @@ -3344,5 +3626,5 @@ blo "550,4300" ) -*100 (Text +*108 (Text va (VaSet font "Arial,8,1" @@ -3352,5 +3634,5 @@ blo "550,5300" ) -*101 (Text +*109 (Text va (VaSet font "Arial,8,1" @@ -3401,5 +3683,5 @@ stg "VerticalLayoutStrategy" textVec [ -*102 (Text +*110 (Text va (VaSet font "Arial,8,1" @@ -3410,5 +3692,5 @@ tm "BdLibraryNameMgr" ) -*103 (Text +*111 (Text va (VaSet font "Arial,8,1" @@ -3419,5 +3701,5 @@ tm "CptNameMgr" ) -*104 (Text +*112 (Text va (VaSet font "Arial,8,1" @@ -3473,5 +3755,5 @@ stg "VerticalLayoutStrategy" textVec [ -*105 (Text +*113 (Text va (VaSet font "Arial,8,1" @@ -3481,5 +3763,5 @@ blo "500,4300" ) -*106 (Text +*114 (Text va (VaSet font "Arial,8,1" @@ -3489,5 +3771,5 @@ blo "500,5300" ) -*107 (Text +*115 (Text va (VaSet font "Arial,8,1" @@ -3534,5 +3816,5 @@ stg "VerticalLayoutStrategy" textVec [ -*108 (Text +*116 (Text va (VaSet font "Arial,8,1" @@ -3542,5 +3824,5 @@ blo "50,4300" ) -*109 (Text +*117 (Text va (VaSet font "Arial,8,1" @@ -3550,5 +3832,5 @@ blo "50,5300" ) -*110 (Text +*118 (Text va (VaSet font "Arial,8,1" @@ -3591,5 +3873,5 @@ stg "VerticalLayoutStrategy" textVec [ -*111 (Text +*119 (Text va (VaSet font "Arial,8,1" @@ -3600,5 +3882,5 @@ tm "HdlTextNameMgr" ) -*112 (Text +*120 (Text va (VaSet font "Arial,8,1" @@ -4003,5 +4285,5 @@ stg "VerticalLayoutStrategy" textVec [ -*113 (Text +*121 (Text va (VaSet font "Arial,8,1" @@ -4011,5 +4293,5 @@ blo "14100,20800" ) -*114 (MLText +*122 (MLText va (VaSet ) @@ -4063,5 +4345,5 @@ stg "VerticalLayoutStrategy" textVec [ -*115 (Text +*123 (Text va (VaSet font "Arial,8,1" @@ -4071,5 +4353,5 @@ blo "14100,20800" ) -*116 (MLText +*124 (MLText va (VaSet ) @@ -4152,7 +4434,7 @@ font "Arial,8,1" ) -xt "20000,0,25400,1000" +xt "27000,200,32400,1200" st "Declarations" -blo "20000,800" +blo "27000,1000" ) portLabel (Text @@ -4161,7 +4443,7 @@ font "Arial,8,1" ) -xt "20000,1000,22700,2000" +xt "27000,1200,29700,2200" st "Ports:" -blo "20000,1800" +blo "27000,2000" ) preUserLabel (Text @@ -4171,7 +4453,7 @@ font "Arial,8,1" ) -xt "20000,0,23800,1000" +xt "27000,200,30800,1200" st "Pre User:" -blo "20000,800" +blo "27000,1000" ) preUserText (MLText @@ -4181,5 +4463,5 @@ font "Courier New,8,0" ) -xt "20000,0,20000,0" +xt "27000,200,27000,200" tm "BdDeclarativeTextMgr" ) @@ -4189,7 +4471,7 @@ font "Arial,8,1" ) -xt "20000,11600,27100,12600" +xt "27000,13400,34100,14400" st "Diagram Signals:" -blo "20000,12400" +blo "27000,14200" ) postUserLabel (Text @@ -4199,7 +4481,7 @@ font "Arial,8,1" ) -xt "20000,0,24700,1000" +xt "27000,200,31700,1200" st "Post User:" -blo "20000,800" +blo "27000,1000" ) postUserText (MLText @@ -4209,5 +4491,5 @@ font "Courier New,8,0" ) -xt "20000,0,20000,0" +xt "27000,200,27000,200" tm "BdDeclarativeTextMgr" ) @@ -4215,44 +4497,44 @@ commonDM (CommonDM ldm (LogicalDM -suid 18,0 +suid 20,0 usingSuid 1 -emptyRow *117 (LEmptyRow +emptyRow *125 (LEmptyRow ) uid 54,0 optionalChildren [ -*118 (RefLabelRowHdr -) -*119 (TitleRowHdr -) -*120 (FilterRowHdr -) -*121 (RefLabelColHdr +*126 (RefLabelRowHdr +) +*127 (TitleRowHdr +) +*128 (FilterRowHdr +) +*129 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*122 (RowExpandColHdr +*130 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*123 (GroupColHdr +*131 (GroupColHdr tm "GroupColHdrMgr" ) -*124 (NameColHdr +*132 (NameColHdr tm "BlockDiagramNameColHdrMgr" ) -*125 (ModeColHdr +*133 (ModeColHdr tm "BlockDiagramModeColHdrMgr" ) -*126 (TypeColHdr +*134 (TypeColHdr tm "BlockDiagramTypeColHdrMgr" ) -*127 (BoundsColHdr +*135 (BoundsColHdr tm "BlockDiagramBoundsColHdrMgr" ) -*128 (InitColHdr +*136 (InitColHdr tm "BlockDiagramInitColHdrMgr" ) -*129 (EolColHdr +*137 (EolColHdr tm "BlockDiagramEolColHdrMgr" ) -*130 (LeafLogPort +*138 (LeafLogPort port (LogicalPort decl (Decl @@ -4265,5 +4547,5 @@ uid 427,0 ) -*131 (LeafLogPort +*139 (LeafLogPort port (LogicalPort m 4 @@ -4278,5 +4560,5 @@ uid 429,0 ) -*132 (LeafLogPort +*140 (LeafLogPort port (LogicalPort decl (Decl @@ -4290,5 +4572,5 @@ uid 431,0 ) -*133 (LeafLogPort +*141 (LeafLogPort port (LogicalPort m 4 @@ -4303,5 +4585,5 @@ uid 433,0 ) -*134 (LeafLogPort +*142 (LeafLogPort port (LogicalPort m 1 @@ -4315,5 +4597,5 @@ uid 435,0 ) -*135 (LeafLogPort +*143 (LeafLogPort port (LogicalPort m 1 @@ -4327,5 +4609,5 @@ uid 437,0 ) -*136 (LeafLogPort +*144 (LeafLogPort port (LogicalPort m 2 @@ -4340,5 +4622,5 @@ uid 439,0 ) -*137 (LeafLogPort +*145 (LeafLogPort port (LogicalPort m 1 @@ -4352,5 +4634,5 @@ uid 441,0 ) -*138 (LeafLogPort +*146 (LeafLogPort port (LogicalPort m 4 @@ -4365,5 +4647,5 @@ uid 443,0 ) -*139 (LeafLogPort +*147 (LeafLogPort port (LogicalPort decl (Decl @@ -4376,5 +4658,5 @@ uid 445,0 ) -*140 (LeafLogPort +*148 (LeafLogPort port (LogicalPort m 4 @@ -4389,5 +4671,5 @@ uid 447,0 ) -*141 (LeafLogPort +*149 (LeafLogPort port (LogicalPort m 1 @@ -4401,5 +4683,5 @@ uid 449,0 ) -*142 (LeafLogPort +*150 (LeafLogPort port (LogicalPort decl (Decl @@ -4412,5 +4694,5 @@ uid 451,0 ) -*143 (LeafLogPort +*151 (LeafLogPort port (LogicalPort decl (Decl @@ -4423,5 +4705,5 @@ uid 453,0 ) -*144 (LeafLogPort +*152 (LeafLogPort port (LogicalPort m 1 @@ -4435,5 +4717,5 @@ uid 457,0 ) -*145 (LeafLogPort +*153 (LeafLogPort port (LogicalPort m 1 @@ -4448,4 +4730,29 @@ uid 1096,0 ) +*154 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 17 +suid 19,0 +) +) +uid 1234,0 +) +*155 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 18 +suid 20,0 +) +) +uid 1236,0 +) ] ) @@ -4455,5 +4762,5 @@ uid 67,0 optionalChildren [ -*146 (Sheet +*156 (Sheet sheetRow (SheetRow headerVa (MVa @@ -4472,25 +4779,25 @@ font "Tahoma,10,0" ) -emptyMRCItem *147 (MRCItem -litem &117 -pos 16 +emptyMRCItem *157 (MRCItem +litem &125 +pos 18 dimension 20 ) uid 69,0 optionalChildren [ -*148 (MRCItem -litem &118 +*158 (MRCItem +litem &126 pos 0 dimension 20 uid 70,0 ) -*149 (MRCItem -litem &119 +*159 (MRCItem +litem &127 pos 1 dimension 23 uid 71,0 ) -*150 (MRCItem -litem &120 +*160 (MRCItem +litem &128 pos 2 hidden 1 @@ -4498,99 +4805,111 @@ uid 72,0 ) -*151 (MRCItem -litem &130 +*161 (MRCItem +litem &138 pos 0 dimension 20 uid 428,0 ) -*152 (MRCItem -litem &131 +*162 (MRCItem +litem &139 pos 11 dimension 20 uid 430,0 ) -*153 (MRCItem -litem &132 +*163 (MRCItem +litem &140 pos 1 dimension 20 uid 432,0 ) -*154 (MRCItem -litem &133 +*164 (MRCItem +litem &141 pos 12 dimension 20 uid 434,0 ) -*155 (MRCItem -litem &134 +*165 (MRCItem +litem &142 pos 2 dimension 20 uid 436,0 ) -*156 (MRCItem -litem &135 +*166 (MRCItem +litem &143 pos 3 dimension 20 uid 438,0 ) -*157 (MRCItem -litem &136 +*167 (MRCItem +litem &144 pos 4 dimension 20 uid 440,0 ) -*158 (MRCItem -litem &137 +*168 (MRCItem +litem &145 pos 5 dimension 20 uid 442,0 ) -*159 (MRCItem -litem &138 +*169 (MRCItem +litem &146 pos 13 dimension 20 uid 444,0 ) -*160 (MRCItem -litem &139 +*170 (MRCItem +litem &147 pos 6 dimension 20 uid 446,0 ) -*161 (MRCItem -litem &140 +*171 (MRCItem +litem &148 pos 14 dimension 20 uid 448,0 ) -*162 (MRCItem -litem &141 +*172 (MRCItem +litem &149 pos 7 dimension 20 uid 450,0 ) -*163 (MRCItem -litem &142 +*173 (MRCItem +litem &150 pos 8 dimension 20 uid 452,0 ) -*164 (MRCItem -litem &143 +*174 (MRCItem +litem &151 pos 9 dimension 20 uid 454,0 ) -*165 (MRCItem -litem &144 +*175 (MRCItem +litem &152 pos 10 dimension 20 uid 458,0 ) -*166 (MRCItem -litem &145 +*176 (MRCItem +litem &153 pos 15 dimension 20 uid 1097,0 +) +*177 (MRCItem +litem &154 +pos 16 +dimension 20 +uid 1235,0 +) +*178 (MRCItem +litem &155 +pos 17 +dimension 20 +uid 1237,0 ) ] @@ -4605,48 +4924,48 @@ uid 73,0 optionalChildren [ -*167 (MRCItem -litem &121 +*179 (MRCItem +litem &129 pos 0 dimension 20 uid 74,0 ) -*168 (MRCItem -litem &123 +*180 (MRCItem +litem &131 pos 1 dimension 50 uid 75,0 ) -*169 (MRCItem -litem &124 +*181 (MRCItem +litem &132 pos 2 dimension 100 uid 76,0 ) -*170 (MRCItem -litem &125 +*182 (MRCItem +litem &133 pos 3 dimension 50 uid 77,0 ) -*171 (MRCItem -litem &126 +*183 (MRCItem +litem &134 pos 4 dimension 100 uid 78,0 ) -*172 (MRCItem -litem &127 +*184 (MRCItem +litem &135 pos 5 dimension 100 uid 79,0 ) -*173 (MRCItem -litem &128 +*185 (MRCItem +litem &136 pos 6 dimension 50 uid 80,0 ) -*174 (MRCItem -litem &129 +*186 (MRCItem +litem &137 pos 7 dimension 80 @@ -4668,36 +4987,36 @@ genericsCommonDM (CommonDM ldm (LogicalDM -emptyRow *175 (LEmptyRow +emptyRow *187 (LEmptyRow ) uid 83,0 optionalChildren [ -*176 (RefLabelRowHdr -) -*177 (TitleRowHdr -) -*178 (FilterRowHdr -) -*179 (RefLabelColHdr +*188 (RefLabelRowHdr +) +*189 (TitleRowHdr +) +*190 (FilterRowHdr +) +*191 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*180 (RowExpandColHdr +*192 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*181 (GroupColHdr +*193 (GroupColHdr tm "GroupColHdrMgr" ) -*182 (NameColHdr +*194 (NameColHdr tm "GenericNameColHdrMgr" ) -*183 (TypeColHdr +*195 (TypeColHdr tm "GenericTypeColHdrMgr" ) -*184 (InitColHdr +*196 (InitColHdr tm "GenericValueColHdrMgr" ) -*185 (PragmaColHdr +*197 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) -*186 (EolColHdr +*198 (EolColHdr tm "GenericEolColHdrMgr" ) @@ -4709,5 +5028,5 @@ uid 95,0 optionalChildren [ -*187 (Sheet +*199 (Sheet sheetRow (SheetRow headerVa (MVa @@ -4726,6 +5045,6 @@ font "Tahoma,10,0" ) -emptyMRCItem *188 (MRCItem -litem &175 +emptyMRCItem *200 (MRCItem +litem &187 pos 0 dimension 20 @@ -4733,18 +5052,18 @@ uid 97,0 optionalChildren [ -*189 (MRCItem -litem &176 +*201 (MRCItem +litem &188 pos 0 dimension 20 uid 98,0 ) -*190 (MRCItem -litem &177 +*202 (MRCItem +litem &189 pos 1 dimension 23 uid 99,0 ) -*191 (MRCItem -litem &178 +*203 (MRCItem +litem &190 pos 2 hidden 1 @@ -4763,42 +5082,42 @@ uid 101,0 optionalChildren [ -*192 (MRCItem -litem &179 +*204 (MRCItem +litem &191 pos 0 dimension 20 uid 102,0 ) -*193 (MRCItem -litem &181 +*205 (MRCItem +litem &193 pos 1 dimension 50 uid 103,0 ) -*194 (MRCItem -litem &182 +*206 (MRCItem +litem &194 pos 2 dimension 100 uid 104,0 ) -*195 (MRCItem -litem &183 +*207 (MRCItem +litem &195 pos 3 dimension 100 uid 105,0 ) -*196 (MRCItem -litem &184 +*208 (MRCItem +litem &196 pos 4 dimension 50 uid 106,0 ) -*197 (MRCItem -litem &185 +*209 (MRCItem +litem &197 pos 5 dimension 50 uid 107,0 ) -*198 (MRCItem -litem &186 +*210 (MRCItem +litem &198 pos 6 dimension 80 Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.bak =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.bak (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.bak (revision 252) @@ -60,5 +60,5 @@ ) version "29.1" -appVersion "2009.1 (Build 12)" +appVersion "2009.2 (Build 10)" noEmbeddedEditors 1 model (BlockDiag @@ -67,21 +67,21 @@ (vvPair variable "HDLDir" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hdl" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" ) (vvPair variable "HDSDir" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair variable "SideDataDesignDir" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info" ) (vvPair variable "SideDataUserDir" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user" ) (vvPair variable "SourceDir" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair @@ -99,25 +99,25 @@ (vvPair variable "d" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" ) (vvPair variable "d_logical" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" ) (vvPair variable "date" -value "27.05.2010" +value "12.07.2010" ) (vvPair variable "day" -value "Do" +value "Mo" ) (vvPair variable "day_long" -value "Donnerstag" +value "Montag" ) (vvPair variable "dd" -value "27" +value "12" ) (vvPair @@ -147,5 +147,5 @@ (vvPair variable "host" -value "IHP110" +value "TU-CC4900F8C7D2" ) (vvPair @@ -175,5 +175,5 @@ (vvPair variable "mm" -value "05" +value "07" ) (vvPair @@ -183,17 +183,17 @@ (vvPair variable "month" -value "Mai" +value "Jul" ) (vvPair variable "month_long" -value "Mai" +value "Juli" ) (vvPair variable "p" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd" ) (vvPair variable "p_logical" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd" ) (vvPair @@ -219,5 +219,5 @@ (vvPair variable "task_ModelSimPath" -value "D:\\modeltech_6.5e\\win32" +value "" ) (vvPair @@ -251,5 +251,5 @@ (vvPair variable "time" -value "10:24:01" +value "13:47:38" ) (vvPair @@ -259,9 +259,9 @@ (vvPair variable "user" -value "daqct3" +value "dneise" ) (vvPair variable "version" -value "2009.1 (Build 12)" +value "2009.2 (Build 10)" ) (vvPair @@ -303,5 +303,5 @@ bg "0,0,32768" ) -xt "16200,76000,24500,77000" +xt "16200,76000,25500,77000" st " by %user on %dd %month %year @@ -621,7 +621,6 @@ font "Courier New,8,0" ) -xt "22000,2000,38000,2800" -st "clk : STD_LOGIC -" +xt "29000,2200,45000,3000" +st "clk : STD_LOGIC" ) ) @@ -640,7 +639,6 @@ font "Courier New,8,0" ) -xt "22000,15000,51500,15800" -st "SIGNAL ram_wren : std_logic_VECTOR(0 DOWNTO 0) -" +xt "29000,15200,58500,16000" +st "SIGNAL ram_wren : std_logic_VECTOR(0 DOWNTO 0)" ) ) @@ -659,7 +657,6 @@ font "Courier New,8,0" ) -xt "22000,2800,48000,3600" -st "config_addr : std_logic_vector(7 DOWNTO 0) -" +xt "29000,3000,55000,3800" +st "config_addr : std_logic_vector(7 DOWNTO 0)" ) ) @@ -678,7 +675,6 @@ font "Courier New,8,0" ) -xt "22000,13400,52000,14200" -st "SIGNAL ram_data_in : std_logic_VECTOR(15 DOWNTO 0) -" +xt "29000,13600,59000,14400" +st "SIGNAL ram_data_in : std_logic_VECTOR(15 DOWNTO 0)" ) ) @@ -696,7 +692,6 @@ font "Courier New,8,0" ) -xt "22000,6800,38000,7600" -st "config_data_valid : std_logic -" +xt "29000,7000,45000,7800" +st "config_data_valid : std_logic" ) ) @@ -714,7 +709,6 @@ font "Courier New,8,0" ) -xt "22000,6000,38000,6800" -st "config_busy : std_logic -" +xt "29000,6200,45000,7000" +st "config_busy : std_logic" ) ) @@ -733,7 +727,6 @@ font "Courier New,8,0" ) -xt "22000,10800,48500,11600" -st "config_data : std_logic_vector(15 DOWNTO 0) -" +xt "29000,11000,55500,11800" +st "config_data : std_logic_vector(15 DOWNTO 0)" ) ) @@ -751,7 +744,6 @@ font "Courier New,8,0" ) -xt "22000,10000,40500,10800" -st "roi_array : roi_array_type -" +xt "29000,10200,47500,11000" +st "roi_array : roi_array_type" ) ) @@ -770,7 +762,6 @@ font "Courier New,8,0" ) -xt "22000,12600,51500,13400" -st "SIGNAL ram_addr : std_logic_VECTOR(7 DOWNTO 0) -" +xt "29000,12800,58500,13600" +st "SIGNAL ram_addr : std_logic_VECTOR(7 DOWNTO 0)" ) ) @@ -788,7 +779,6 @@ font "Courier New,8,0" ) -xt "22000,5200,38000,6000" -st "config_wr_en : std_logic -" +xt "29000,5400,45000,6200" +st "config_wr_en : std_logic" ) ) @@ -807,7 +797,6 @@ font "Courier New,8,0" ) -xt "22000,14200,52000,15000" -st "SIGNAL ram_data_out : std_logic_VECTOR(15 DOWNTO 0) -" +xt "29000,14400,59000,15200" +st "SIGNAL ram_data_out : std_logic_VECTOR(15 DOWNTO 0)" ) ) @@ -825,7 +814,6 @@ font "Courier New,8,0" ) -xt "22000,9200,40500,10000" -st "dac_array : dac_array_type -" +xt "29000,9400,47500,10200" +st "dac_array : dac_array_type" ) ) @@ -843,7 +831,6 @@ font "Courier New,8,0" ) -xt "22000,3600,38000,4400" -st "config_rd_en : std_logic -" +xt "29000,3800,45000,4600" +st "config_rd_en : std_logic" ) ) @@ -861,7 +848,6 @@ font "Courier New,8,0" ) -xt "22000,4400,38000,5200" -st "config_start : std_logic -" +xt "29000,4600,45000,5400" +st "config_start : std_logic" ) ) @@ -879,7 +865,6 @@ font "Courier New,8,0" ) -xt "22000,7600,38000,8400" -st "config_ready : std_logic -" +xt "29000,7800,45000,8600" +st "config_ready : std_logic" ) ) @@ -897,5 +882,5 @@ sl 0 ro 270 -xt "3000,23625,4500,24375" +xt "2000,19625,3500,20375" ) (Line @@ -903,8 +888,8 @@ sl 0 ro 270 -xt "4500,24000,5000,24000" +xt "3500,20000,4000,20000" pts [ -"4500,24000" -"5000,24000" +"3500,20000" +"4000,20000" ] ) @@ -921,8 +906,8 @@ va (VaSet ) -xt "700,23500,2000,24500" +xt "700,19500,2000,20500" st "clk" ju 2 -blo "2000,24300" +blo "2000,20300" tm "WireNameMgr" ) @@ -942,5 +927,5 @@ sl 0 ro 270 -xt "42500,28625,44000,29375" +xt "36500,28625,38000,29375" ) (Line @@ -948,8 +933,8 @@ sl 0 ro 270 -xt "42000,29000,42500,29000" +xt "36000,29000,36500,29000" pts [ -"42000,29000" -"42500,29000" +"36000,29000" +"36500,29000" ] ) @@ -966,7 +951,7 @@ va (VaSet ) -xt "45000,28500,50100,29500" +xt "39000,28500,44100,29500" st "config_ready" -blo "45000,29300" +blo "39000,29300" tm "WireNameMgr" ) @@ -986,5 +971,5 @@ sl 0 ro 90 -xt "42500,29625,44000,30375" +xt "36500,29625,38000,30375" ) (Line @@ -992,8 +977,8 @@ sl 0 ro 90 -xt "42000,30000,42500,30000" +xt "36000,30000,36500,30000" pts [ -"42500,30000" -"42000,30000" +"36500,30000" +"36000,30000" ] ) @@ -1010,7 +995,7 @@ va (VaSet ) -xt "45000,29500,49800,30500" +xt "39000,29500,43800,30500" st "config_start" -blo "45000,30300" +blo "39000,30300" tm "WireNameMgr" ) @@ -1029,13 +1014,13 @@ uid 381,0 sl 0 -xt "42500,24625,44000,25375" +xt "36500,24625,38000,25375" ) (Line uid 382,0 sl 0 -xt "42000,25000,42500,25000" +xt "36000,25000,36500,25000" pts [ -"42000,25000" -"42500,25000" +"36000,25000" +"36500,25000" ] ) @@ -1052,7 +1037,7 @@ va (VaSet ) -xt "45000,24500,49700,25500" +xt "39000,24500,43700,25500" st "config_data" -blo "45000,25300" +blo "39000,25300" tm "WireNameMgr" ) @@ -1072,5 +1057,5 @@ sl 0 ro 90 -xt "42500,23625,44000,24375" +xt "36500,23625,38000,24375" ) (Line @@ -1078,8 +1063,8 @@ sl 0 ro 90 -xt "42000,24000,42500,24000" +xt "36000,24000,36500,24000" pts [ -"42500,24000" -"42000,24000" +"36500,24000" +"36000,24000" ] ) @@ -1096,7 +1081,7 @@ va (VaSet ) -xt "45000,23500,49800,24500" +xt "39000,23500,43800,24500" st "config_addr" -blo "45000,24300" +blo "39000,24300" tm "WireNameMgr" ) @@ -1116,5 +1101,5 @@ sl 0 ro 90 -xt "42500,26625,44000,27375" +xt "36500,26625,38000,27375" ) (Line @@ -1122,8 +1107,8 @@ sl 0 ro 90 -xt "42000,27000,42500,27000" +xt "36000,27000,36500,27000" pts [ -"42500,27000" -"42000,27000" +"36500,27000" +"36000,27000" ] ) @@ -1140,7 +1125,7 @@ va (VaSet ) -xt "45000,26500,50300,27500" +xt "39000,26500,44300,27500" st "config_wr_en" -blo "45000,27300" +blo "39000,27300" tm "WireNameMgr" ) @@ -1160,5 +1145,5 @@ sl 0 ro 90 -xt "42500,27625,44000,28375" +xt "36500,27625,38000,28375" ) (Line @@ -1166,8 +1151,8 @@ sl 0 ro 90 -xt "42000,28000,42500,28000" +xt "36000,28000,36500,28000" pts [ -"42500,28000" -"42000,28000" +"36500,28000" +"36000,28000" ] ) @@ -1184,7 +1169,7 @@ va (VaSet ) -xt "45000,27500,50200,28500" +xt "39000,27500,44200,28500" st "config_rd_en" -blo "45000,28300" +blo "39000,28300" tm "WireNameMgr" ) @@ -1204,5 +1189,5 @@ sl 0 ro 270 -xt "42500,33625,44000,34375" +xt "36500,33625,38000,34375" ) (Line @@ -1210,8 +1195,8 @@ sl 0 ro 270 -xt "42000,34000,42500,34000" +xt "36000,34000,36500,34000" pts [ -"42000,34000" -"42500,34000" +"36000,34000" +"36500,34000" ] ) @@ -1228,7 +1213,7 @@ va (VaSet ) -xt "45000,33500,48700,34500" +xt "39000,33500,42700,34500" st "dac_array" -blo "45000,34300" +blo "39000,34300" tm "WireNameMgr" ) @@ -1248,5 +1233,5 @@ sl 0 ro 270 -xt "42500,34625,44000,35375" +xt "36500,34625,38000,35375" ) (Line @@ -1254,8 +1239,8 @@ sl 0 ro 270 -xt "42000,35000,42500,35000" +xt "36000,35000,36500,35000" pts [ -"42000,35000" -"42500,35000" +"36000,35000" +"36500,35000" ] ) @@ -1272,7 +1257,7 @@ va (VaSet ) -xt "45000,34500,48400,35500" +xt "39000,34500,42400,35500" st "roi_array" -blo "45000,35300" +blo "39000,35300" tm "WireNameMgr" ) @@ -1292,5 +1277,5 @@ sl 0 ro 270 -xt "42500,31625,44000,32375" +xt "36500,31625,38000,32375" ) (Line @@ -1298,8 +1283,8 @@ sl 0 ro 270 -xt "42000,32000,42500,32000" +xt "36000,32000,36500,32000" pts [ -"42000,32000" -"42500,32000" +"36000,32000" +"36500,32000" ] ) @@ -1316,7 +1301,7 @@ va (VaSet ) -xt "45000,31500,51600,32500" +xt "39000,31500,45600,32500" st "config_data_valid" -blo "45000,32300" +blo "39000,32300" tm "WireNameMgr" ) @@ -1336,5 +1321,5 @@ sl 0 ro 270 -xt "42500,32625,44000,33375" +xt "36500,32625,38000,33375" ) (Line @@ -1342,8 +1327,8 @@ sl 0 ro 270 -xt "42000,33000,42500,33000" +xt "36000,33000,36500,33000" pts [ -"42000,33000" -"42500,33000" +"36000,33000" +"36500,33000" ] ) @@ -1360,7 +1345,7 @@ va (VaSet ) -xt "45000,32500,49800,33500" +xt "39000,32500,43800,33500" st "config_busy" -blo "45000,33300" +blo "39000,33300" tm "WireNameMgr" ) @@ -1380,5 +1365,5 @@ fg "0,65535,0" ) -xt "12250,23625,13000,24375" +xt "6250,23625,7000,24375" ) tg (CPTG @@ -1390,7 +1375,7 @@ va (VaSet ) -xt "14000,23500,15300,24500" +xt "8000,23500,9300,24500" st "clk" -blo "14000,24300" +blo "8000,24300" ) ) @@ -1416,5 +1401,5 @@ fg "0,65535,0" ) -xt "38000,28625,38750,29375" +xt "32000,28625,32750,29375" ) tg (CPTG @@ -1426,8 +1411,8 @@ va (VaSet ) -xt "31900,28500,37000,29500" +xt "25900,28500,31000,29500" st "config_ready" ju 2 -blo "37000,29300" +blo "31000,29300" ) ) @@ -1455,5 +1440,5 @@ fg "0,65535,0" ) -xt "38000,29625,38750,30375" +xt "32000,29625,32750,30375" ) tg (CPTG @@ -1465,8 +1450,8 @@ va (VaSet ) -xt "32200,29500,37000,30500" +xt "26200,29500,31000,30500" st "config_start" ju 2 -blo "37000,30300" +blo "31000,30300" ) ) @@ -1492,5 +1477,5 @@ fg "0,65535,0" ) -xt "38000,24625,38750,25375" +xt "32000,24625,32750,25375" ) tg (CPTG @@ -1502,8 +1487,8 @@ va (VaSet ) -xt "29300,24500,37000,25500" +xt "23300,24500,31000,25500" st "config_data : (15:0)" ju 2 -blo "37000,25300" +blo "31000,25300" ) ) @@ -1532,5 +1517,5 @@ fg "0,65535,0" ) -xt "38000,23625,38750,24375" +xt "32000,23625,32750,24375" ) tg (CPTG @@ -1542,8 +1527,8 @@ va (VaSet ) -xt "23600,23500,37000,24500" +xt "17600,23500,31000,24500" st "config_addr : (ADDR_WIDTH - 1:0)" ju 2 -blo "37000,24300" +blo "31000,24300" ) ) @@ -1570,5 +1555,5 @@ fg "0,65535,0" ) -xt "38000,26625,38750,27375" +xt "32000,26625,32750,27375" ) tg (CPTG @@ -1580,8 +1565,8 @@ va (VaSet ) -xt "31700,26500,37000,27500" +xt "25700,26500,31000,27500" st "config_wr_en" ju 2 -blo "37000,27300" +blo "31000,27300" ) ) @@ -1607,5 +1592,5 @@ fg "0,65535,0" ) -xt "38000,27625,38750,28375" +xt "32000,27625,32750,28375" ) tg (CPTG @@ -1617,8 +1602,8 @@ va (VaSet ) -xt "31800,27500,37000,28500" +xt "25800,27500,31000,28500" st "config_rd_en" ju 2 -blo "37000,28300" +blo "31000,28300" ) ) @@ -1644,5 +1629,5 @@ fg "0,65535,0" ) -xt "38000,31625,38750,32375" +xt "32000,31625,32750,32375" ) tg (CPTG @@ -1654,8 +1639,8 @@ va (VaSet ) -xt "30400,31500,37000,32500" +xt "24400,31500,31000,32500" st "config_data_valid" ju 2 -blo "37000,32300" +blo "31000,32300" ) ) @@ -1683,5 +1668,5 @@ fg "0,65535,0" ) -xt "38000,32625,38750,33375" +xt "32000,32625,32750,33375" ) tg (CPTG @@ -1693,8 +1678,8 @@ va (VaSet ) -xt "32200,32500,37000,33500" +xt "26200,32500,31000,33500" st "config_busy" ju 2 -blo "37000,33300" +blo "31000,33300" ) ) @@ -1722,5 +1707,5 @@ fg "0,65535,0" ) -xt "38000,33625,38750,34375" +xt "32000,33625,32750,34375" ) tg (CPTG @@ -1732,8 +1717,8 @@ va (VaSet ) -xt "33300,33500,37000,34500" +xt "27300,33500,31000,34500" st "dac_array" ju 2 -blo "37000,34300" +blo "31000,34300" ) ) @@ -1760,5 +1745,5 @@ fg "0,65535,0" ) -xt "38000,34625,38750,35375" +xt "32000,34625,32750,35375" ) tg (CPTG @@ -1770,8 +1755,8 @@ va (VaSet ) -xt "33600,34500,37000,35500" +xt "27600,34500,31000,35500" st "roi_array" ju 2 -blo "37000,35300" +blo "31000,35300" ) ) @@ -1798,5 +1783,5 @@ fg "0,65535,0" ) -xt "38000,37625,38750,38375" +xt "32000,37625,32750,38375" ) tg (CPTG @@ -1808,8 +1793,8 @@ va (VaSet ) -xt "29100,37500,37000,38500" +xt "23100,37500,31000,38500" st "ram_data_in : (15:0)" ju 2 -blo "37000,38300" +blo "31000,38300" ) ) @@ -1835,5 +1820,5 @@ fg "0,65535,0" ) -xt "38000,38625,38750,39375" +xt "32000,38625,32750,39375" ) tg (CPTG @@ -1845,8 +1830,8 @@ va (VaSet ) -xt "29100,38500,37000,39500" +xt "23100,38500,31000,39500" st "ram_write_en : (0:0)" ju 2 -blo "37000,39300" +blo "31000,39300" ) ) @@ -1872,5 +1857,5 @@ fg "0,65535,0" ) -xt "12250,24625,13000,25375" +xt "6250,38625,7000,39375" ) tg (CPTG @@ -1882,7 +1867,7 @@ va (VaSet ) -xt "14000,24500,22300,25500" +xt "8000,38500,16300,39500" st "ram_data_out : (15:0)" -blo "14000,25300" +blo "8000,39300" ) ) @@ -1907,5 +1892,5 @@ fg "0,65535,0" ) -xt "38000,39625,38750,40375" +xt "32000,39625,32750,40375" ) tg (CPTG @@ -1917,8 +1902,8 @@ va (VaSet ) -xt "24400,39500,37000,40500" +xt "18400,39500,31000,40500" st "ram_addr : (ADDR_WIDTH - 1:0)" ju 2 -blo "37000,40300" +blo "31000,40300" ) ) @@ -1944,5 +1929,5 @@ fg "0,65535,0" ) -xt "38000,30625,38750,31375" +xt "32000,30625,32750,31375" ) tg (CPTG @@ -1954,8 +1939,8 @@ va (VaSet ) -xt "31400,30500,37000,31500" +xt "25400,30500,31000,31500" st "config_started" ju 2 -blo "37000,31300" +blo "31000,31300" ) ) @@ -1980,5 +1965,5 @@ lineWidth 2 ) -xt "13000,23000,38000,42000" +xt "7000,23000,32000,42000" ) oxt "42000,14000,67000,32000" @@ -1993,7 +1978,7 @@ font "Arial,8,1" ) -xt "12950,42000,19150,43000" +xt "6950,42000,13150,43000" st "FACT_FAD_lib" -blo "12950,42800" +blo "6950,42800" tm "BdLibraryNameMgr" ) @@ -2003,7 +1988,7 @@ font "Arial,8,1" ) -xt "12950,43000,20050,44000" +xt "6950,43000,14050,44000" st "control_manager" -blo "12950,43800" +blo "6950,43800" tm "CptNameMgr" ) @@ -2013,7 +1998,7 @@ font "Arial,8,1" ) -xt "12950,44000,20650,45000" +xt "6950,44000,14650,45000" st "I_control_manager" -blo "12950,44800" +blo "6950,44800" tm "InstanceNameMgr" ) @@ -2030,5 +2015,5 @@ font "Courier New,8,0" ) -xt "12500,10600,30000,13000" +xt "10000,20600,27500,23000" st "NO_OF_ROI = 36 ( integer ) NO_OF_DAC = 8 ( integer ) @@ -2062,5 +2047,5 @@ fg "49152,49152,49152" ) -xt "13250,40250,14750,41750" +xt "7250,40250,8750,41750" iconName "VhdlFileViewIcon.png" iconMaskName "VhdlFileViewIcon.msk" @@ -2081,22 +2066,24 @@ shape (Triangle uid 971,0 -ro 90 +ro 180 va (VaSet vasetType 1 fg "0,65535,0" ) -xt "19250,50625,20000,51375" +xt "42625,41250,43375,42000" ) tg (CPTG uid 972,0 ps "CptPortTextPlaceStrategy" -stg "VerticalLayoutStrategy" +stg "RightVerticalLayoutStrategy" f (Text uid 973,0 -va (VaSet -) -xt "21000,50500,22700,51500" +ro 270 +va (VaSet +) +xt "42500,43000,43500,44700" st "clka" -blo "21000,51300" +ju 2 +blo "43300,43000" ) ) @@ -2122,5 +2109,5 @@ fg "0,65535,0" ) -xt "19250,52625,20000,53375" +xt "39250,45625,40000,46375" ) tg (CPTG @@ -2132,7 +2119,7 @@ va (VaSet ) -xt "21000,52500,25800,53500" +xt "41000,45500,45800,46500" st "dina : (15:0)" -blo "21000,53300" +blo "41000,46300" ) ) @@ -2159,5 +2146,5 @@ fg "0,65535,0" ) -xt "19250,54625,20000,55375" +xt "39250,47625,40000,48375" ) tg (CPTG @@ -2169,7 +2156,7 @@ va (VaSet ) -xt "21000,54500,25900,55500" +xt "41000,47500,45900,48500" st "addra : (7:0)" -blo "21000,55300" +blo "41000,48300" ) ) @@ -2196,5 +2183,5 @@ fg "0,65535,0" ) -xt "19250,53625,20000,54375" +xt "39250,46625,40000,47375" ) tg (CPTG @@ -2206,7 +2193,7 @@ va (VaSet ) -xt "21000,53500,25300,54500" +xt "41000,46500,45300,47500" st "wea : (0:0)" -blo "21000,54300" +blo "41000,47300" ) ) @@ -2233,5 +2220,5 @@ fg "0,65535,0" ) -xt "30000,50625,30750,51375" +xt "50000,43625,50750,44375" ) tg (CPTG @@ -2243,8 +2230,8 @@ va (VaSet ) -xt "23800,50500,29000,51500" +xt "43800,43500,49000,44500" st "douta : (15:0)" ju 2 -blo "29000,51300" +blo "49000,44300" ) ) @@ -2271,5 +2258,5 @@ lineWidth 2 ) -xt "20000,49000,30000,59000" +xt "40000,42000,50000,52000" ) oxt "30000,7000,40000,17000" @@ -2284,7 +2271,7 @@ font "Arial,8,1" ) -xt "20200,59000,26400,60000" +xt "40200,52000,46400,53000" st "FACT_FAD_lib" -blo "20200,59800" +blo "40200,52800" tm "BdLibraryNameMgr" ) @@ -2294,7 +2281,7 @@ font "Arial,8,1" ) -xt "20200,60000,30100,61000" +xt "40200,53000,50100,54000" st "controlRAM_16bit_x256" -blo "20200,60800" +blo "40200,53800" tm "CptNameMgr" ) @@ -2304,7 +2291,7 @@ font "Arial,8,1" ) -xt "20200,61000,26100,62000" +xt "40200,54000,46100,55000" st "I_control_ram" -blo "20200,61800" +blo "40200,54800" tm "InstanceNameMgr" ) @@ -2321,5 +2308,5 @@ font "Courier New,8,0" ) -xt "19500,48000,19500,48000" +xt "39500,41000,39500,41000" ) header "" @@ -2335,7 +2322,8 @@ fg "49152,49152,49152" ) -xt "20250,57250,21750,58750" -iconName "UnknownFile.png" -iconMaskName "UnknownFile.msk" +xt "40250,50250,41750,51750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 ) ordering 1 @@ -2360,7 +2348,6 @@ font "Courier New,8,0" ) -xt "22000,8400,41500,9200" -st "config_started : std_logic := '0' -" +xt "29000,8600,48500,9400" +st "config_started : std_logic := '0'" ) ) @@ -2378,5 +2365,5 @@ sl 0 ro 270 -xt "42500,30625,44000,31375" +xt "36500,30625,38000,31375" ) (Line @@ -2384,8 +2371,8 @@ sl 0 ro 270 -xt "42000,31000,42500,31000" +xt "36000,31000,36500,31000" pts [ -"42000,31000" -"42500,31000" +"36000,31000" +"36500,31000" ] ) @@ -2402,7 +2389,7 @@ va (VaSet ) -xt "45000,30500,50600,31500" +xt "39000,30500,44600,31500" st "config_started" -blo "45000,31300" +blo "39000,31300" tm "WireNameMgr" ) @@ -2417,9 +2404,8 @@ lineWidth 2 ) -xt "38750,24000,42000,24000" +xt "32750,24000,36000,24000" pts [ -"42000,24000" -"40000,24000" -"38750,24000" +"36000,24000" +"32750,24000" ] ) @@ -2442,7 +2428,7 @@ isHidden 1 ) -xt "45000,23000,49800,24000" +xt "39000,23000,43800,24000" st "config_addr" -blo "45000,23800" +blo "39000,23800" tm "WireNameMgr" ) @@ -2458,12 +2444,10 @@ lineWidth 2 ) -xt "13000,39000,43000,54000" +xt "32750,39000,39250,47000" pts [ -"19250,54000" -"13000,54000" -"13000,47000" -"43000,47000" -"43000,39000" -"38750,39000" +"39250,47000" +"34000,47000" +"34000,39000" +"32750,39000" ] ) @@ -2484,7 +2468,7 @@ va (VaSet ) -xt "23000,46000,29300,47000" +xt "34000,46000,40300,47000" st "ram_wren : (0:0)" -blo "23000,46800" +blo "34000,46800" tm "WireNameMgr" ) @@ -2500,12 +2484,10 @@ lineWidth 2 ) -xt "14000,38000,44000,53000" +xt "32750,38000,39250,46000" pts [ -"19250,53000" -"14000,53000" -"14000,48000" -"44000,48000" -"44000,38000" -"38750,38000" +"39250,46000" +"35000,46000" +"35000,38000" +"32750,38000" ] ) @@ -2526,7 +2508,7 @@ va (VaSet ) -xt "23000,47000,30900,48000" +xt "33000,37000,40900,38000" st "ram_data_in : (15:0)" -blo "23000,47800" +blo "33000,37800" tm "WireNameMgr" ) @@ -2541,8 +2523,10 @@ vasetType 3 ) -xt "5000,24000,12250,24000" +xt "4000,20000,6250,24000" pts [ +"4000,20000" +"5000,20000" "5000,24000" -"12250,24000" +"6250,24000" ] ) @@ -2564,7 +2548,7 @@ isHidden 1 ) -xt "7000,23000,8300,24000" +xt "6000,19000,7300,20000" st "clk" -blo "7000,23800" +blo "6000,19800" tm "WireNameMgr" ) @@ -2579,8 +2563,8 @@ vasetType 3 ) -xt "38750,32000,42000,32000" +xt "32750,32000,36000,32000" pts [ -"38750,32000" -"42000,32000" +"32750,32000" +"36000,32000" ] ) @@ -2602,7 +2586,7 @@ isHidden 1 ) -xt "45000,30000,51600,31000" +xt "39000,30000,45600,31000" st "config_data_valid" -blo "45000,30800" +blo "39000,30800" tm "WireNameMgr" ) @@ -2617,8 +2601,8 @@ vasetType 3 ) -xt "38750,33000,42000,33000" +xt "32750,33000,36000,33000" pts [ -"38750,33000" -"42000,33000" +"32750,33000" +"36000,33000" ] ) @@ -2640,7 +2624,7 @@ isHidden 1 ) -xt "45000,31000,49800,32000" +xt "39000,31000,43800,32000" st "config_busy" -blo "45000,31800" +blo "39000,31800" tm "WireNameMgr" ) @@ -2656,9 +2640,8 @@ lineWidth 2 ) -xt "38750,25000,42000,25000" +xt "32750,25000,36000,25000" pts [ -"42000,25000" -"40000,25000" -"38750,25000" +"36000,25000" +"32750,25000" ] ) @@ -2681,7 +2664,7 @@ isHidden 1 ) -xt "45000,24000,49700,25000" +xt "39000,24000,43700,25000" st "config_data" -blo "45000,24800" +blo "39000,24800" tm "WireNameMgr" ) @@ -2696,9 +2679,8 @@ vasetType 3 ) -xt "38750,35000,42000,35000" +xt "32750,35000,36000,35000" pts [ -"38750,35000" -"40000,35000" -"42000,35000" +"32750,35000" +"36000,35000" ] ) @@ -2720,7 +2702,7 @@ isHidden 1 ) -xt "45000,34000,48400,35000" +xt "39000,34000,42400,35000" st "roi_array" -blo "45000,34800" +blo "39000,34800" tm "WireNameMgr" ) @@ -2735,8 +2717,8 @@ vasetType 3 ) -xt "17000,51000,19250,51000" +xt "43000,38000,43000,41250" pts [ -"17000,51000" -"19250,51000" +"43000,38000" +"43000,41250" ] ) @@ -2755,7 +2737,7 @@ va (VaSet ) -xt "18000,50000,19300,51000" +xt "44000,37000,45300,38000" st "clk" -blo "18000,50800" +blo "44000,37800" tm "WireNameMgr" ) @@ -2771,12 +2753,10 @@ lineWidth 2 ) -xt "12000,40000,42000,55000" +xt "32750,40000,39250,48000" pts [ -"38750,40000" -"42000,40000" -"42000,46000" -"12000,46000" -"12000,55000" -"19250,55000" +"32750,40000" +"33000,40000" +"33000,48000" +"39250,48000" ] ) @@ -2797,7 +2777,7 @@ va (VaSet ) -xt "23000,45000,29200,46000" +xt "33000,47000,39200,48000" st "ram_addr : (7:0)" -blo "23000,45800" +blo "33000,47800" tm "WireNameMgr" ) @@ -2812,9 +2792,8 @@ vasetType 3 ) -xt "38750,30000,42000,30000" +xt "32750,30000,36000,30000" pts [ -"42000,30000" -"40000,30000" -"38750,30000" +"36000,30000" +"32750,30000" ] ) @@ -2836,7 +2815,7 @@ isHidden 1 ) -xt "45000,29000,49800,30000" +xt "39000,29000,43800,30000" st "config_start" -blo "45000,29800" +blo "39000,29800" tm "WireNameMgr" ) @@ -2851,9 +2830,8 @@ vasetType 3 ) -xt "38750,27000,42000,27000" +xt "32750,27000,36000,27000" pts [ -"42000,27000" -"40000,27000" -"38750,27000" +"36000,27000" +"32750,27000" ] ) @@ -2875,7 +2853,7 @@ isHidden 1 ) -xt "45000,26000,50300,27000" +xt "39000,26000,44300,27000" st "config_wr_en" -blo "45000,26800" +blo "39000,26800" tm "WireNameMgr" ) @@ -2891,12 +2869,12 @@ lineWidth 2 ) -xt "9000,25000,34000,64000" +xt "3000,39000,52000,56000" pts [ -"12250,25000" -"9000,25000" -"9000,64000" -"34000,64000" -"34000,51000" -"30750,51000" +"6250,39000" +"3000,39000" +"3000,56000" +"52000,56000" +"52000,44000" +"50750,44000" ] ) @@ -2917,7 +2895,7 @@ va (VaSet ) -xt "20000,63000,28300,64000" +xt "33000,55000,41300,56000" st "ram_data_out : (15:0)" -blo "20000,63800" +blo "33000,55800" tm "WireNameMgr" ) @@ -2932,9 +2910,8 @@ vasetType 3 ) -xt "38750,34000,42000,34000" +xt "32750,34000,36000,34000" pts [ -"38750,34000" -"40000,34000" -"42000,34000" +"32750,34000" +"36000,34000" ] ) @@ -2956,7 +2933,7 @@ isHidden 1 ) -xt "45000,33000,48700,34000" +xt "39000,33000,42700,34000" st "dac_array" -blo "45000,33800" +blo "39000,33800" tm "WireNameMgr" ) @@ -2971,9 +2948,8 @@ vasetType 3 ) -xt "38750,28000,42000,28000" +xt "32750,28000,36000,28000" pts [ -"42000,28000" -"40000,28000" -"38750,28000" +"36000,28000" +"32750,28000" ] ) @@ -2995,7 +2971,7 @@ isHidden 1 ) -xt "45000,27000,50200,28000" +xt "39000,27000,44200,28000" st "config_rd_en" -blo "45000,27800" +blo "39000,27800" tm "WireNameMgr" ) @@ -3010,9 +2986,8 @@ vasetType 3 ) -xt "38750,29000,42000,29000" +xt "32750,29000,36000,29000" pts [ -"38750,29000" -"40000,29000" -"42000,29000" +"32750,29000" +"36000,29000" ] ) @@ -3034,7 +3009,7 @@ isHidden 1 ) -xt "45000,28000,50100,29000" +xt "39000,28000,44100,29000" st "config_ready" -blo "45000,28800" +blo "39000,28800" tm "WireNameMgr" ) @@ -3049,8 +3024,8 @@ vasetType 3 ) -xt "38750,31000,42000,31000" +xt "32750,31000,36000,31000" pts [ -"38750,31000" -"42000,31000" +"32750,31000" +"36000,31000" ] ) @@ -3072,7 +3047,7 @@ isHidden 1 ) -xt "40000,30000,45600,31000" +xt "34000,30000,39600,31000" st "config_started" -blo "40000,30800" +blo "34000,30800" tm "WireNameMgr" ) @@ -3101,7 +3076,7 @@ font "arial,8,1" ) -xt "0,0,5400,1000" +xt "1000,1000,6400,2000" st "Package List" -blo "0,800" +blo "1000,1800" ) *88 (MLText @@ -3109,5 +3084,5 @@ va (VaSet ) -xt "0,1000,15300,6000" +xt "1000,2000,16300,7000" st "LIBRARY ieee; USE ieee.std_logic_1164.ALL; @@ -3192,7 +3167,7 @@ associable 1 ) -windowSize "0,22,1286,1024" -viewArea "834,16774,54098,59806" -cachedDiagramExtent "0,0,53000,77000" +windowSize "0,0,1281,1002" +viewArea "-6400,12035,60443,65774" +cachedDiagramExtent "700,0,59000,77000" pageSetupInfo (PageSetupInfo ptrCmd "Brother HL-5270DN series,winspool," @@ -3220,5 +3195,5 @@ hasePageBreakOrigin 1 pageBreakOrigin "0,0" -lastUid 1122,0 +lastUid 1172,0 defaultCommentText (CommentText shape (Rectangle @@ -4167,7 +4142,7 @@ font "Arial,8,1" ) -xt "20000,0,25400,1000" +xt "27000,200,32400,1200" st "Declarations" -blo "20000,800" +blo "27000,1000" ) portLabel (Text @@ -4176,7 +4151,7 @@ font "Arial,8,1" ) -xt "20000,1000,22700,2000" +xt "27000,1200,29700,2200" st "Ports:" -blo "20000,1800" +blo "27000,2000" ) preUserLabel (Text @@ -4186,7 +4161,7 @@ font "Arial,8,1" ) -xt "20000,0,23800,1000" +xt "27000,200,30800,1200" st "Pre User:" -blo "20000,800" +blo "27000,1000" ) preUserText (MLText @@ -4196,5 +4171,5 @@ font "Courier New,8,0" ) -xt "20000,0,20000,0" +xt "27000,200,27000,200" tm "BdDeclarativeTextMgr" ) @@ -4204,7 +4179,7 @@ font "Arial,8,1" ) -xt "20000,11600,27100,12600" +xt "27000,11800,34100,12800" st "Diagram Signals:" -blo "20000,12400" +blo "27000,12600" ) postUserLabel (Text @@ -4214,7 +4189,7 @@ font "Arial,8,1" ) -xt "20000,0,24700,1000" +xt "27000,200,31700,1200" st "Post User:" -blo "20000,800" +blo "27000,1000" ) postUserText (MLText @@ -4224,5 +4199,5 @@ font "Courier New,8,0" ) -xt "20000,0,20000,0" +xt "27000,200,27000,200" tm "BdDeclarativeTextMgr" ) Index: /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/symbol.sb =================================================================== --- /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/symbol.sb (revision 251) +++ /FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/symbol.sb (revision 252) @@ -25,9 +25,9 @@ ) version "24.1" -appVersion "2009.1 (Build 12)" +appVersion "2009.2 (Build 10)" model (Symbol commonDM (CommonDM ldm (LogicalDM -suid 12,0 +suid 14,0 usingSuid 1 emptyRow *1 (LEmptyRow @@ -122,5 +122,5 @@ t "std_logic_vector" b "(15 DOWNTO 0)" -o 12 +o 14 suid 5,0 ) @@ -134,5 +134,5 @@ n "roi_array" t "roi_array_type" -o 11 +o 13 suid 6,0 ) @@ -210,4 +210,29 @@ uid 349,0 ) +*26 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 11 +suid 13,0 +) +) +uid 518,0 +) +*27 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 12 +suid 14,0 +) +) +uid 520,0 +) ] ) @@ -217,5 +242,5 @@ uid 66,0 optionalChildren [ -*26 (Sheet +*28 (Sheet sheetRow (SheetRow headerVa (MVa @@ -234,5 +259,5 @@ font "Tahoma,10,0" ) -emptyMRCItem *27 (MRCItem +emptyMRCItem *29 (MRCItem litem &1 pos 11 @@ -241,5 +266,5 @@ uid 68,0 optionalChildren [ -*28 (MRCItem +*30 (MRCItem litem &2 pos 0 @@ -247,5 +272,5 @@ uid 69,0 ) -*29 (MRCItem +*31 (MRCItem litem &3 pos 1 @@ -253,5 +278,5 @@ uid 70,0 ) -*30 (MRCItem +*32 (MRCItem litem &4 pos 2 @@ -260,5 +285,5 @@ uid 71,0 ) -*31 (MRCItem +*33 (MRCItem litem &14 pos 0 @@ -266,5 +291,5 @@ uid 108,0 ) -*32 (MRCItem +*34 (MRCItem litem &15 pos 1 @@ -272,5 +297,5 @@ uid 110,0 ) -*33 (MRCItem +*35 (MRCItem litem &16 pos 2 @@ -278,5 +303,5 @@ uid 112,0 ) -*34 (MRCItem +*36 (MRCItem litem &17 pos 3 @@ -284,5 +309,5 @@ uid 114,0 ) -*35 (MRCItem +*37 (MRCItem litem &18 pos 4 @@ -290,5 +315,5 @@ uid 116,0 ) -*36 (MRCItem +*38 (MRCItem litem &19 pos 5 @@ -296,5 +321,5 @@ uid 118,0 ) -*37 (MRCItem +*39 (MRCItem litem &20 pos 6 @@ -302,5 +327,5 @@ uid 120,0 ) -*38 (MRCItem +*40 (MRCItem litem &21 pos 7 @@ -308,5 +333,5 @@ uid 122,0 ) -*39 (MRCItem +*41 (MRCItem litem &22 pos 8 @@ -314,5 +339,5 @@ uid 124,0 ) -*40 (MRCItem +*42 (MRCItem litem &23 pos 9 @@ -320,5 +345,5 @@ uid 126,0 ) -*41 (MRCItem +*43 (MRCItem litem &24 pos 10 @@ -326,9 +351,21 @@ uid 128,0 ) -*42 (MRCItem +*44 (MRCItem litem &25 pos 11 dimension 20 uid 348,0 +) +*45 (MRCItem +litem &26 +pos 12 +dimension 20 +uid 517,0 +) +*46 (MRCItem +litem &27 +pos 13 +dimension 20 +uid 519,0 ) ] @@ -343,5 +380,5 @@ uid 72,0 optionalChildren [ -*43 (MRCItem +*47 (MRCItem litem &5 pos 0 @@ -349,5 +386,5 @@ uid 73,0 ) -*44 (MRCItem +*48 (MRCItem litem &7 pos 1 @@ -355,5 +392,5 @@ uid 74,0 ) -*45 (MRCItem +*49 (MRCItem litem &8 pos 2 @@ -361,5 +398,5 @@ uid 75,0 ) -*46 (MRCItem +*50 (MRCItem litem &9 pos 3 @@ -367,5 +404,5 @@ uid 76,0 ) -*47 (MRCItem +*51 (MRCItem litem &10 pos 4 @@ -373,5 +410,5 @@ uid 77,0 ) -*48 (MRCItem +*52 (MRCItem litem &11 pos 5 @@ -379,5 +416,5 @@ uid 78,0 ) -*49 (MRCItem +*53 (MRCItem litem &12 pos 6 @@ -385,5 +422,5 @@ uid 79,0 ) -*50 (MRCItem +*54 (MRCItem litem &13 pos 7 @@ -406,36 +443,36 @@ genericsCommonDM (CommonDM ldm (LogicalDM -emptyRow *51 (LEmptyRow +emptyRow *55 (LEmptyRow ) uid 82,0 optionalChildren [ -*52 (RefLabelRowHdr -) -*53 (TitleRowHdr -) -*54 (FilterRowHdr -) -*55 (RefLabelColHdr +*56 (RefLabelRowHdr +) +*57 (TitleRowHdr +) +*58 (FilterRowHdr +) +*59 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*56 (RowExpandColHdr +*60 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*57 (GroupColHdr +*61 (GroupColHdr tm "GroupColHdrMgr" ) -*58 (NameColHdr +*62 (NameColHdr tm "GenericNameColHdrMgr" ) -*59 (TypeColHdr +*63 (TypeColHdr tm "GenericTypeColHdrMgr" ) -*60 (InitColHdr +*64 (InitColHdr tm "GenericValueColHdrMgr" ) -*61 (PragmaColHdr +*65 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) -*62 (EolColHdr +*66 (EolColHdr tm "GenericEolColHdrMgr" ) @@ -447,5 +484,5 @@ uid 94,0 optionalChildren [ -*63 (Sheet +*67 (Sheet sheetRow (SheetRow headerVa (MVa @@ -464,6 +501,6 @@ font "Tahoma,10,0" ) -emptyMRCItem *64 (MRCItem -litem &51 +emptyMRCItem *68 (MRCItem +litem &55 pos 0 dimension 20 @@ -471,18 +508,18 @@ uid 96,0 optionalChildren [ -*65 (MRCItem -litem &52 +*69 (MRCItem +litem &56 pos 0 dimension 20 uid 97,0 ) -*66 (MRCItem -litem &53 +*70 (MRCItem +litem &57 pos 1 dimension 23 uid 98,0 ) -*67 (MRCItem -litem &54 +*71 (MRCItem +litem &58 pos 2 hidden 1 @@ -501,42 +538,42 @@ uid 100,0 optionalChildren [ -*68 (MRCItem -litem &55 +*72 (MRCItem +litem &59 pos 0 dimension 20 uid 101,0 ) -*69 (MRCItem -litem &57 +*73 (MRCItem +litem &61 pos 1 dimension 50 uid 102,0 ) -*70 (MRCItem -litem &58 +*74 (MRCItem +litem &62 pos 2 dimension 100 uid 103,0 ) -*71 (MRCItem -litem &59 +*75 (MRCItem +litem &63 pos 3 dimension 100 uid 104,0 ) -*72 (MRCItem -litem &60 +*76 (MRCItem +litem &64 pos 4 dimension 50 uid 105,0 ) -*73 (MRCItem -litem &61 +*77 (MRCItem +litem &65 pos 5 dimension 50 uid 106,0 ) -*74 (MRCItem -litem &62 +*78 (MRCItem +litem &66 pos 6 dimension 80 @@ -561,21 +598,21 @@ (vvPair variable "HDLDir" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hdl" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" ) (vvPair variable "HDSDir" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair variable "SideDataDesignDir" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.info" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.info" ) (vvPair variable "SideDataUserDir" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.user" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.user" ) (vvPair variable "SourceDir" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair @@ -593,25 +630,25 @@ (vvPair variable "d" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" ) (vvPair variable "d_logical" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" ) (vvPair variable "date" -value "27.05.2010" +value "12.07.2010" ) (vvPair variable "day" -value "Do" +value "Mo" ) (vvPair variable "day_long" -value "Donnerstag" +value "Montag" ) (vvPair variable "dd" -value "27" +value "12" ) (vvPair @@ -641,5 +678,5 @@ (vvPair variable "host" -value "IHP110" +value "TU-CC4900F8C7D2" ) (vvPair @@ -669,5 +706,5 @@ (vvPair variable "mm" -value "05" +value "07" ) (vvPair @@ -677,17 +714,17 @@ (vvPair variable "month" -value "Mai" +value "Jul" ) (vvPair variable "month_long" -value "Mai" +value "Juli" ) (vvPair variable "p" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb" ) (vvPair variable "p_logical" -value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb" ) (vvPair @@ -713,5 +750,5 @@ (vvPair variable "task_ModelSimPath" -value "D:\\modeltech_6.5e\\win32" +value "" ) (vvPair @@ -745,5 +782,5 @@ (vvPair variable "time" -value "10:24:05" +value "14:13:34" ) (vvPair @@ -753,9 +790,9 @@ (vvPair variable "user" -value "daqct3" +value "dneise" ) (vvPair variable "version" -value "2009.1 (Build 12)" +value "2009.2 (Build 10)" ) (vvPair @@ -776,8 +813,8 @@ uid 51,0 optionalChildren [ -*75 (SymbolBody +*79 (SymbolBody uid 8,0 optionalChildren [ -*76 (CptPort +*80 (CptPort uid 130,0 ps "OnEdgeStrategy" @@ -811,5 +848,6 @@ ) xt "44000,2000,65000,2800" -st "clk : IN STD_LOGIC ;" +st "clk : IN STD_LOGIC ; +" ) thePort (LogicalPort @@ -822,5 +860,5 @@ ) ) -*77 (CptPort +*81 (CptPort uid 135,0 ps "OnEdgeStrategy" @@ -855,5 +893,6 @@ ) xt "44000,2800,75000,3600" -st "config_addr : IN std_logic_vector (7 DOWNTO 0) ;" +st "config_addr : IN std_logic_vector (7 DOWNTO 0) ; +" ) thePort (LogicalPort @@ -867,5 +906,5 @@ ) ) -*78 (CptPort +*82 (CptPort uid 140,0 ps "OnEdgeStrategy" @@ -900,5 +939,6 @@ ) xt "44000,6800,65000,7600" -st "config_data_valid : OUT std_logic ;" +st "config_data_valid : OUT std_logic ; +" ) thePort (LogicalPort @@ -912,5 +952,5 @@ ) ) -*79 (CptPort +*83 (CptPort uid 145,0 ps "OnEdgeStrategy" @@ -945,5 +985,6 @@ ) xt "44000,6000,65000,6800" -st "config_busy : OUT std_logic ;" +st "config_busy : OUT std_logic ; +" ) thePort (LogicalPort @@ -957,5 +998,5 @@ ) ) -*80 (CptPort +*84 (CptPort uid 150,0 ps "OnEdgeStrategy" @@ -989,6 +1030,7 @@ font "Courier New,8,0" ) -xt "44000,10800,74500,11600" -st "config_data : INOUT std_logic_vector (15 DOWNTO 0)" +xt "44000,12400,74500,13200" +st "config_data : INOUT std_logic_vector (15 DOWNTO 0) +" ) thePort (LogicalPort @@ -998,10 +1040,10 @@ t "std_logic_vector" b "(15 DOWNTO 0)" -o 12 +o 14 suid 5,0 ) ) ) -*81 (CptPort +*85 (CptPort uid 155,0 ps "OnEdgeStrategy" @@ -1035,6 +1077,7 @@ font "Courier New,8,0" ) -xt "44000,10000,68000,10800" -st "roi_array : OUT roi_array_type ;" +xt "44000,11600,68000,12400" +st "roi_array : OUT roi_array_type ; +" ) thePort (LogicalPort @@ -1043,10 +1086,10 @@ n "roi_array" t "roi_array_type" -o 11 +o 13 suid 6,0 ) ) ) -*82 (CptPort +*86 (CptPort uid 160,0 ps "OnEdgeStrategy" @@ -1081,5 +1124,6 @@ ) xt "44000,5200,65000,6000" -st "config_wr_en : IN std_logic ;" +st "config_wr_en : IN std_logic ; +" ) thePort (LogicalPort @@ -1092,5 +1136,5 @@ ) ) -*83 (CptPort +*87 (CptPort uid 165,0 ps "OnEdgeStrategy" @@ -1125,5 +1169,6 @@ ) xt "44000,9200,68000,10000" -st "dac_array : OUT dac_array_type ;" +st "dac_array : OUT dac_array_type ; +" ) thePort (LogicalPort @@ -1137,5 +1182,5 @@ ) ) -*84 (CptPort +*88 (CptPort uid 170,0 ps "OnEdgeStrategy" @@ -1170,5 +1215,6 @@ ) xt "44000,3600,65000,4400" -st "config_rd_en : IN std_logic ;" +st "config_rd_en : IN std_logic ; +" ) thePort (LogicalPort @@ -1181,5 +1227,5 @@ ) ) -*85 (CptPort +*89 (CptPort uid 175,0 ps "OnEdgeStrategy" @@ -1214,5 +1260,6 @@ ) xt "44000,4400,65000,5200" -st "config_start : IN std_logic ;" +st "config_start : IN std_logic ; +" ) thePort (LogicalPort @@ -1225,5 +1272,5 @@ ) ) -*86 (CptPort +*90 (CptPort uid 180,0 ps "OnEdgeStrategy" @@ -1258,5 +1305,6 @@ ) xt "44000,7600,65000,8400" -st "config_ready : OUT std_logic ;" +st "config_ready : OUT std_logic ; +" ) thePort (LogicalPort @@ -1270,5 +1318,5 @@ ) ) -*87 (CptPort +*91 (CptPort uid 350,0 ps "OnEdgeStrategy" @@ -1313,5 +1361,6 @@ ) xt "44000,8400,69000,9200" -st "config_started : OUT std_logic := '0' ;" +st "config_started : OUT std_logic := '0' ; +" ) thePort (LogicalPort @@ -1326,4 +1375,97 @@ ) ) +*92 (CptPort +uid 521,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 522,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,28625,33750,29375" +) +tg (CPTG +uid 523,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 524,0 +va (VaSet +) +xt "24800,28500,32000,29500" +st "drs_address : (3:0)" +ju 2 +blo "32000,29300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 525,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10000,75000,10800" +st "drs_address : OUT std_logic_vector (3 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 11 +suid 13,0 +) +) +) +*93 (CptPort +uid 526,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 527,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,30625,33750,31375" +) +tg (CPTG +uid 528,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 529,0 +va (VaSet +) +xt "24800,30500,32000,31500" +st "drs_address_mode" +ju 2 +blo "32000,31300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 530,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10800,65000,11600" +st "drs_address_mode : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 12 +suid 14,0 +) +) +) ] shape (Rectangle @@ -1335,5 +1477,5 @@ lineWidth 2 ) -xt "15000,13000,33000,28000" +xt "15000,13000,33000,32000" ) oxt "15000,13000,33000,26000" @@ -1361,5 +1503,5 @@ ) ) -gi *88 (GenericInterface +gi *94 (GenericInterface uid 13,0 ps "CenterOffsetStrategy" @@ -1388,8 +1530,8 @@ ) ) -*89 (Grouping +*95 (Grouping uid 16,0 optionalChildren [ -*90 (CommentText +*96 (CommentText uid 18,0 shape (Rectangle @@ -1409,5 +1551,5 @@ bg "0,0,32768" ) -xt "36200,48000,45900,49000" +xt "36200,48000,45500,49000" st " by %user on %dd %month %year @@ -1422,5 +1564,5 @@ titleBlock 1 ) -*91 (CommentText +*97 (CommentText uid 21,0 shape (Rectangle @@ -1453,5 +1595,5 @@ titleBlock 1 ) -*92 (CommentText +*98 (CommentText uid 24,0 shape (Rectangle @@ -1484,5 +1626,5 @@ titleBlock 1 ) -*93 (CommentText +*99 (CommentText uid 27,0 shape (Rectangle @@ -1515,5 +1657,5 @@ titleBlock 1 ) -*94 (CommentText +*100 (CommentText uid 30,0 shape (Rectangle @@ -1545,5 +1687,5 @@ titleBlock 1 ) -*95 (CommentText +*101 (CommentText uid 33,0 shape (Rectangle @@ -1576,5 +1718,5 @@ titleBlock 1 ) -*96 (CommentText +*102 (CommentText uid 36,0 shape (Rectangle @@ -1608,5 +1750,5 @@ titleBlock 1 ) -*97 (CommentText +*103 (CommentText uid 39,0 shape (Rectangle @@ -1639,5 +1781,5 @@ titleBlock 1 ) -*98 (CommentText +*104 (CommentText uid 42,0 shape (Rectangle @@ -1670,5 +1812,5 @@ titleBlock 1 ) -*99 (CommentText +*105 (CommentText uid 45,0 shape (Rectangle @@ -1726,9 +1868,9 @@ color "26368,26368,26368" ) -packageList *100 (PackageList +packageList *106 (PackageList uid 48,0 stg "VerticalLayoutStrategy" textVec [ -*101 (Text +*107 (Text uid 49,0 va (VaSet @@ -1739,5 +1881,5 @@ blo "0,800" ) -*102 (MLText +*108 (MLText uid 50,0 va (VaSet @@ -1840,5 +1982,5 @@ ) ) -gi *103 (GenericInterface +gi *109 (GenericInterface ps "CenterOffsetStrategy" matrix (Matrix @@ -1937,5 +2079,5 @@ ) ) -DeclarativeBlock *104 (SymDeclBlock +DeclarativeBlock *110 (SymDeclBlock uid 1,0 stg "SymDeclLayoutStrategy" @@ -1963,7 +2105,7 @@ font "Arial,8,1" ) -xt "42000,11600,44400,12600" +xt "42000,13200,44400,14200" st "User:" -blo "42000,12400" +blo "42000,14000" ) internalLabel (Text @@ -1982,5 +2124,5 @@ font "Courier New,8,0" ) -xt "44000,12600,44000,12600" +xt "44000,14200,44000,14200" tm "SyDeclarativeTextMgr" ) @@ -1995,5 +2137,5 @@ ) ) -lastUid 401,0 +lastUid 530,0 okToSyncOnLoad 1 OkToSyncGenericsOnLoad 1