Ignore:
Timestamp:
07/16/10 16:25:44 (15 years ago)
Author:
dneise
Message:
DRS addresses may not be set via
sa 44 0 .. 31
Location:
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd

    r246 r252  
    4040)
    4141(Instance
    42 name "I_debouncer"
    43 duLibraryName "FACT_FAD_LIB"
    44 duName "debouncer"
    45 elements [
    46 (GiElement
    47 name "WIDTH"
    48 type "INTEGER"
    49 value "17"
    50 )
    51 ]
    52 mwi 0
    53 uid 6250,0
    54 )
    55 (Instance
    56 name "I1"
    57 duLibraryName "moduleware"
    58 duName "inv"
    59 elements [
    60 ]
    61 mwi 1
    62 uid 6539,0
    63 )
    64 (Instance
    6542name "I2"
    6643duLibraryName "moduleware"
     
    128105(vvPair
    129106variable "HDLDir"
    130 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hdl"
     107value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
    131108)
    132109(vvPair
    133110variable "HDSDir"
    134 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds"
     111value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    135112)
    136113(vvPair
    137114variable "SideDataDesignDir"
    138 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
     115value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
    139116)
    140117(vvPair
    141118variable "SideDataUserDir"
    142 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
     119value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
    143120)
    144121(vvPair
    145122variable "SourceDir"
    146 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds"
     123value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    147124)
    148125(vvPair
     
    156133(vvPair
    157134variable "config"
    158 value "%(unit)_config"
     135value "%(unit)_%(view)_config"
    159136)
    160137(vvPair
    161138variable "d"
    162 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board"
     139value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board"
    163140)
    164141(vvPair
    165142variable "d_logical"
    166 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board"
     143value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board"
    167144)
    168145(vvPair
    169146variable "date"
    170 value "24.06.2010"
     147value "14.07.2010"
    171148)
    172149(vvPair
    173150variable "day"
    174 value "Do"
     151value "Mi"
    175152)
    176153(vvPair
    177154variable "day_long"
    178 value "Donnerstag"
     155value "Mittwoch"
    179156)
    180157(vvPair
    181158variable "dd"
    182 value "24"
     159value "14"
    183160)
    184161(vvPair
     
    208185(vvPair
    209186variable "host"
    210 value "EEPC8"
     187value "E5B-LABOR6"
    211188)
    212189(vvPair
     
    219196)
    220197(vvPair
     198variable "library_downstream_HdsLintPlugin"
     199value "$HDS_PROJECT_DIR\\FACT_FAD_lib\\designcheck"
     200)
     201(vvPair
    221202variable "library_downstream_ISEPARInvoke"
    222203value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
     
    236217(vvPair
    237218variable "mm"
    238 value "06"
     219value "07"
    239220)
    240221(vvPair
     
    244225(vvPair
    245226variable "month"
    246 value "Jun"
     227value "Jul"
    247228)
    248229(vvPair
    249230variable "month_long"
    250 value "Juni"
     231value "Juli"
    251232)
    252233(vvPair
    253234variable "p"
    254 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
     235value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
    255236)
    256237(vvPair
    257238variable "p_logical"
    258 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
     239value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
    259240)
    260241(vvPair
     
    280261(vvPair
    281262variable "task_ModelSimPath"
    282 value "$HDS_HOME/../Modeltech/win32"
     263value "<TBD>"
    283264)
    284265(vvPair
     
    288269(vvPair
    289270variable "task_PrecisionRTLPath"
    290 value "$HDS_HOME/../Precision/Mgc_home/bin"
     271value "<TBD>"
    291272)
    292273(vvPair
     
    312293(vvPair
    313294variable "time"
    314 value "14:18:44"
     295value "15:25:08"
    315296)
    316297(vvPair
     
    320301(vvPair
    321302variable "user"
    322 value "Benjamin Krumm"
     303value "dneise"
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    41124103uid 3608,0
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     4219*129 (Net
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    4241 )
    4242 *131 (Net
     4234st "W_D            : std_logic_vector(15 DOWNTO 0)
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     4236)
     4237)
     4238*130 (Net
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    4259 )
    4260 *132 (Net
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    4277 )
    4278 *133 (Net
     4272st "W_RD           : std_logic                      := '1'
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     4275)
     4276*132 (Net
    42794277uid 3640,0
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    4294 )
    4295 )
    4296 *134 (Net
     4291st "W_WR           : std_logic                      := '1'
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     4293)
     4294)
     4295*133 (Net
    42974296uid 3642,0
    42984297decl (Decl
     
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    4312 )
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     4309st "W_INT          : std_logic
     4310"
     4311)
     4312)
     4313*134 (Net
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    43154315decl (Decl
     
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    4328 st "W_CS           : std_logic                      := '1'"
    4329 )
    4330 )
    4331 *136 (PortIoInOut
     4328st "W_CS           : std_logic                      := '1'
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     4330)
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     4332*135 (PortIoInOut
    43324333uid 3674,0
    43334334shape (CompositeShape
     
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     4374*136 (Net
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    4388 st "MOSI           : std_logic                      := '0'"
    4389 )
    4390 )
    4391 *138 (PortIoOut
     4389st "MOSI           : std_logic                      := '0'
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     4391)
     4392)
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    4451 st "MISO           : std_logic"
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    4453 )
    4454 *140 (HdlText
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    49694972xt "39000,36600,53500,37400"
    4970 st "TRG_V          : std_logic"
    4971 )
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    4973 *154 (Net
     4973st "TRG_V          : std_logic
     4974"
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    49744978uid 3866,0
    49754979decl (Decl
     
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    49864990xt "39000,28600,53500,29400"
    4987 st "RS485_C_RE     : std_logic"
    4988 )
    4989 )
    4990 *155 (Net
     4991st "RS485_C_RE     : std_logic
     4992"
     4993)
     4994)
     4995*154 (Net
    49914996uid 3868,0
    49924997decl (Decl
     
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    50035008xt "39000,27800,53500,28600"
    5004 st "RS485_C_DE     : std_logic"
    5005 )
    5006 )
    5007 *156 (Net
     5009st "RS485_C_DE     : std_logic
     5010"
     5011)
     5012)
     5013*155 (Net
    50085014uid 3870,0
    50095015decl (Decl
     
    50195025)
    50205026xt "39000,30200,53500,31000"
    5021 st "RS485_E_RE     : std_logic"
    5022 )
    5023 )
    5024 *157 (Net
     5027st "RS485_E_RE     : std_logic
     5028"
     5029)
     5030)
     5031*156 (Net
    50255032uid 3872,0
    50265033decl (Decl
     
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    50375044xt "39000,29400,53500,30200"
    5038 st "RS485_E_DE     : std_logic"
    5039 )
    5040 )
    5041 *158 (Net
     5045st "RS485_E_DE     : std_logic
     5046"
     5047)
     5048)
     5049*157 (Net
    50425050uid 3874,0
    50435051decl (Decl
     
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    50555063xt "39000,20600,68000,21400"
    5056 st "DENABLE        : std_logic                      := '0'"
    5057 )
    5058 )
    5059 *159 (Net
     5064st "DENABLE        : std_logic                      := '0'
     5065"
     5066)
     5067)
     5068*158 (Net
    50605069uid 3876,0
    50615070decl (Decl
     
    50715080)
    50725081xt "39000,31800,53500,32600"
    5073 st "SRIN           : std_logic"
    5074 )
    5075 )
    5076 *160 (Net
     5082st "SRIN           : std_logic
     5083"
     5084)
     5085)
     5086*159 (Net
    50775087uid 3878,0
    50785088decl (Decl
     
    50885098)
    50895099xt "39000,24600,53500,25400"
    5090 st "EE_CS          : std_logic"
    5091 )
    5092 )
    5093 *161 (Net
     5100st "EE_CS          : std_logic
     5101"
     5102)
     5103)
     5104*160 (Net
    50945105uid 3880,0
    50955106decl (Decl
     
    51075118)
    51085119xt "39000,25400,74000,26200"
    5109 st "LED            : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')"
    5110 )
    5111 )
    5112 *162 (PortIoOut
     5120st "LED            : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')
     5121"
     5122)
     5123)
     5124*161 (PortIoOut
    51135125uid 3995,0
    51145126shape (CompositeShape
     
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    51565168)
    5157 *163 (PortIoOut
     5169*162 (PortIoOut
    51585170uid 4001,0
    51595171shape (CompositeShape
     
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    52015213)
    5202 *164 (PortIoOut
     5214*163 (PortIoOut
    52035215uid 4007,0
    52045216shape (CompositeShape
     
    52455257)
    52465258)
    5247 *165 (PortIoOut
     5259*164 (PortIoOut
    52485260uid 4013,0
    52495261shape (CompositeShape
     
    52905302)
    52915303)
    5292 *166 (PortIoOut
     5304*165 (PortIoOut
    52935305uid 4916,0
    52945306shape (CompositeShape
     
    53345346)
    53355347)
    5336 *167 (Net
     5348*166 (Net
    53375349uid 5320,0
    53385350decl (Decl
     
    53505362)
    53515363xt "39000,23000,74000,23800"
    5352 st "D_T            : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')"
    5353 )
    5354 )
    5355 *168 (PortIoIn
     5364st "D_T            : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')
     5365"
     5366)
     5367)
     5368*167 (PortIoIn
    53565369uid 5650,0
    53575370shape (CompositeShape
     
    53665379sl 0
    53675380ro 270
    5368 xt "-30000,88625,-28500,89375"
     5381xt "9000,78625,10500,79375"
    53695382)
    53705383(Line
     
    53725385sl 0
    53735386ro 270
    5374 xt "-28500,89000,-28000,89000"
    5375 pts [
    5376 "-28500,89000"
    5377 "-28000,89000"
     5387xt "10500,79000,11000,79000"
     5388pts [
     5389"10500,79000"
     5390"11000,79000"
    53785391]
    53795392)
     
    53905403va (VaSet
    53915404)
    5392 xt "-35500,88500,-31000,89500"
     5405xt "3500,78500,8000,79500"
    53935406st "TEST_TRG"
    53945407ju 2
    5395 blo "-31000,89300"
     5408blo "8000,79300"
    53965409tm "WireNameMgr"
    53975410)
    53985411)
    53995412)
    5400 *169 (Net
     5413*168 (Net
    54015414uid 5662,0
    54025415decl (Decl
     
    54125425)
    54135426xt "39000,11800,53500,12600"
    5414 st "TEST_TRG       : std_logic"
    5415 )
    5416 )
    5417 *170 (Net
     5427st "TEST_TRG       : std_logic
     5428"
     5429)
     5430)
     5431*169 (Net
    54185432uid 6138,0
    54195433decl (Decl
     
    54295443)
    54305444xt "39000,46400,57000,47200"
    5431 st "SIGNAL TRG_OR         : std_logic"
    5432 )
    5433 )
    5434 *171 (SaComponent
    5435 uid 6250,0
    5436 optionalChildren [
    5437 *172 (CptPort
    5438 uid 6235,0
    5439 ps "OnEdgeStrategy"
    5440 shape (Triangle
    5441 uid 6236,0
    5442 ro 90
    5443 va (VaSet
    5444 vasetType 1
    5445 fg "0,65535,0"
    5446 )
    5447 xt "-11750,87625,-11000,88375"
    5448 )
    5449 tg (CPTG
    5450 uid 6237,0
    5451 ps "CptPortTextPlaceStrategy"
    5452 stg "VerticalLayoutStrategy"
    5453 f (Text
    5454 uid 6238,0
    5455 va (VaSet
    5456 )
    5457 xt "-10000,87500,-8700,88500"
    5458 st "clk"
    5459 blo "-10000,88300"
    5460 )
    5461 )
    5462 thePort (LogicalPort
    5463 decl (Decl
    5464 n "clk"
    5465 t "STD_LOGIC"
    5466 preAdd 0
    5467 posAdd 0
    5468 o 1
    5469 suid 1,0
    5470 )
    5471 )
    5472 )
    5473 *173 (CptPort
    5474 uid 6239,0
    5475 ps "OnEdgeStrategy"
    5476 shape (Triangle
    5477 uid 6240,0
    5478 ro 90
    5479 va (VaSet
    5480 vasetType 1
    5481 fg "0,65535,0"
    5482 )
    5483 xt "-11750,88625,-11000,89375"
    5484 )
    5485 tg (CPTG
    5486 uid 6241,0
    5487 ps "CptPortTextPlaceStrategy"
    5488 stg "VerticalLayoutStrategy"
    5489 f (Text
    5490 uid 6242,0
    5491 va (VaSet
    5492 )
    5493 xt "-10000,88500,-5800,89500"
    5494 st "trigger_in"
    5495 blo "-10000,89300"
    5496 )
    5497 )
    5498 thePort (LogicalPort
    5499 decl (Decl
    5500 n "trigger_in"
    5501 t "STD_LOGIC"
    5502 prec "--           rst : in  STD_LOGIC;"
    5503 preAdd 0
    5504 posAdd 0
    5505 o 2
    5506 suid 2,0
    5507 )
    5508 )
    5509 )
    5510 *174 (CptPort
    5511 uid 6243,0
    5512 ps "OnEdgeStrategy"
    5513 shape (Triangle
    5514 uid 6244,0
    5515 ro 90
    5516 va (VaSet
    5517 vasetType 1
    5518 fg "0,65535,0"
    5519 )
    5520 xt "1000,88625,1750,89375"
    5521 )
    5522 tg (CPTG
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    1143210813)
     
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     10843)
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     11229)
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     11235)
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     11241)
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     11247)
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     11253)
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    1186811269uid 73,0
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    1193211333ldm (LogicalDM
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    1195411355)
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     11356*466 (TypeColHdr
    1195611357tm "GenericTypeColHdrMgr"
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     11359*467 (InitColHdr
    1195911360tm "GenericValueColHdrMgr"
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     11362*468 (PragmaColHdr
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    1196311364)
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     11365*469 (EolColHdr
    1196511366tm "GenericEolColHdrMgr"
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     11486)
  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.bak

    r246 r252  
    2626instances [
    2727(Instance
    28 name "I_testboard_main"
     28name "I_board_main"
    2929duLibraryName "FACT_FAD_lib"
    3030duName "FAD_main"
     
    3838mwi 0
    3939uid 169,0
    40 )
    41 (Instance
    42 name "I0"
    43 duLibraryName "FACT_FAD_LIB"
    44 duName "debouncer"
    45 elements [
    46 (GiElement
    47 name "WIDTH"
    48 type "INTEGER"
    49 value "17"
    50 )
    51 ]
    52 mwi 0
    53 uid 6250,0
    54 )
    55 (Instance
    56 name "I1"
    57 duLibraryName "moduleware"
    58 duName "inv"
    59 elements [
    60 ]
    61 mwi 1
    62 uid 6539,0
    6340)
    6441(Instance
     
    128105(vvPair
    129106variable "HDLDir"
    130 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hdl"
     107value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
    131108)
    132109(vvPair
    133110variable "HDSDir"
    134 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds"
     111value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    135112)
    136113(vvPair
    137114variable "SideDataDesignDir"
    138 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
     115value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
    139116)
    140117(vvPair
    141118variable "SideDataUserDir"
    142 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
     119value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
    143120)
    144121(vvPair
    145122variable "SourceDir"
    146 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds"
     123value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    147124)
    148125(vvPair
     
    160137(vvPair
    161138variable "d"
    162 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board"
     139value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board"
    163140)
    164141(vvPair
    165142variable "d_logical"
    166 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\FAD_Board"
     143value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board"
    167144)
    168145(vvPair
    169146variable "date"
    170 value "22.06.2010"
     147value "14.07.2010"
    171148)
    172149(vvPair
    173150variable "day"
    174 value "Di"
     151value "Mi"
    175152)
    176153(vvPair
    177154variable "day_long"
    178 value "Dienstag"
     155value "Mittwoch"
    179156)
    180157(vvPair
    181158variable "dd"
    182 value "22"
     159value "14"
    183160)
    184161(vvPair
     
    208185(vvPair
    209186variable "host"
    210 value "TU-CC4900F8C7D2"
     187value "E5B-LABOR6"
    211188)
    212189(vvPair
     
    219196)
    220197(vvPair
     198variable "library_downstream_HdsLintPlugin"
     199value "$HDS_PROJECT_DIR\\FACT_FAD_lib\\designcheck"
     200)
     201(vvPair
    221202variable "library_downstream_ISEPARInvoke"
    222203value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
     
    236217(vvPair
    237218variable "mm"
    238 value "06"
     219value "07"
    239220)
    240221(vvPair
     
    244225(vvPair
    245226variable "month"
    246 value "Jun"
     227value "Jul"
    247228)
    248229(vvPair
    249230variable "month_long"
    250 value "Juni"
     231value "Juli"
    251232)
    252233(vvPair
    253234variable "p"
    254 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
     235value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
    255236)
    256237(vvPair
    257238variable "p_logical"
    258 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
     239value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
    259240)
    260241(vvPair
     
    312293(vvPair
    313294variable "time"
    314 value "11:16:21"
     295value "15:24:46"
    315296)
    316297(vvPair
     
    364345bg "0,0,32768"
    365346)
    366 xt "99200,4000,108700,5000"
     347xt "99200,4000,108500,5000"
    367348st "
    368349by %user on %dd %month %year
     
    18311812font "Arial,8,1"
    18321813)
    1833 xt "52200,125000,59400,126000"
    1834 st "I_testboard_main"
     1814xt "52200,125000,58000,126000"
     1815st "I_board_main"
    18351816blo "52200,125800"
    18361817tm "InstanceNameMgr"
     
    20652046preAdd 0
    20662047posAdd 0
    2067 o 55
     2048o 56
    20682049suid 5,0
    20692050)
     
    20732054font "Courier New,8,0"
    20742055)
    2075 xt "39000,48000,67000,48800"
     2056xt "39000,48800,67000,49600"
    20762057st "SIGNAL board_id       : std_logic_vector(3 downto 0)"
    20772058)
     
    20832064t "std_logic_vector"
    20842065b "(1 downto 0)"
    2085 o 56
     2066o 57
    20862067suid 6,0
    20872068)
     
    20912072font "Courier New,8,0"
    20922073)
    2093 xt "39000,48800,67000,49600"
     2074xt "39000,49600,67000,50400"
    20942075st "SIGNAL crate_id       : std_logic_vector(1 downto 0)"
    20952076)
     
    24062387n "adc_data_array"
    24072388t "adc_data_array_type"
    2408 o 54
     2389o 55
    24092390suid 29,0
    24102391)
     
    24142395font "Courier New,8,0"
    24152396)
    2416 xt "39000,47200,62500,48000"
     2397xt "39000,48000,62500,48800"
    24172398st "SIGNAL adc_data_array : adc_data_array_type"
    24182399)
    24192400)
    24202401*63 (Net
    2421 uid 2267,0
    2422 decl (Decl
    2423 n "CLK_50"
    2424 t "std_logic"
    2425 preAdd 0
    2426 posAdd 0
    2427 o 51
    2428 suid 54,0
    2429 )
    2430 declText (MLText
    2431 uid 2268,0
    2432 va (VaSet
    2433 font "Courier New,8,0"
    2434 )
    2435 xt "39000,44800,57000,45600"
    2436 st "SIGNAL CLK_50         : std_logic"
    2437 )
    2438 )
    2439 *64 (Net
    24402402uid 2407,0
    24412403decl (Decl
    24422404n "RSRLOAD"
    24432405t "std_logic"
    2444 o 35
     2406o 36
    24452407suid 57,0
    24462408i "'0'"
     
    24512413font "Courier New,8,0"
    24522414)
    2453 xt "39000,31000,68000,31800"
     2415xt "39000,31800,68000,32600"
    24542416st "RSRLOAD        : std_logic                      := '0'"
    24552417)
    24562418)
    2457 *65 (PortIoOut
     2419*64 (PortIoOut
    24582420uid 2415,0
    24592421shape (CompositeShape
     
    25002462)
    25012463)
    2502 *66 (Net
     2464*65 (Net
    25032465uid 2421,0
    25042466decl (Decl
    25052467n "SRCLK"
    25062468t "std_logic"
    2507 o 52
     2469o 53
    25082470suid 58,0
    25092471i "'0'"
     
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     4335*136 (Net
    43744336uid 3680,0
    43754337decl (Decl
    43764338n "MOSI"
    43774339t "std_logic"
    4378 o 29
     4340o 30
    43794341suid 113,0
    43804342i "'0'"
     
    43854347font "Courier New,8,0"
    43864348)
    4387 xt "39000,26200,68000,27000"
     4349xt "39000,27000,68000,27800"
    43884350st "MOSI           : std_logic                      := '0'"
    43894351)
    43904352)
    4391 *138 (PortIoOut
     4353*137 (PortIoOut
    43924354uid 3688,0
    43934355shape (CompositeShape
     
    44334395)
    44344396)
    4435 *139 (Net
     4397*138 (Net
    44364398uid 3694,0
    44374399decl (Decl
     
    44404402preAdd 0
    44414403posAdd 0
    4442 o 48
     4404o 49
    44434405suid 114,0
    44444406)
     
    44484410font "Courier New,8,0"
    44494411)
    4450 xt "39000,41400,53500,42200"
     4412xt "39000,42200,53500,43000"
    44514413st "MISO           : std_logic"
    44524414)
    44534415)
    4454 *140 (HdlText
     4416*139 (HdlText
    44554417uid 3700,0
    44564418optionalChildren [
    4457 *141 (EmbeddedText
     4419*140 (EmbeddedText
    44584420uid 3706,0
    44594421commentText (CommentText
     
    45224484stg "VerticalLayoutStrategy"
    45234485textVec [
    4524 *142 (Text
     4486*141 (Text
    45254487uid 3703,0
    45264488va (VaSet
     
    45324494tm "HdlTextNameMgr"
    45334495)
    4534 *143 (Text
     4496*142 (Text
    45354497uid 3704,0
    45364498va (VaSet
     
    45584520viewiconposition 0
    45594521)
    4560 *144 (PortIoOut
     4522*143 (PortIoOut
    45614523uid 3710,0
    45624524shape (CompositeShape
     
    46024564)
    46034565)
    4604 *145 (PortIoOut
     4566*144 (PortIoOut
    46054567uid 3716,0
    46064568shape (CompositeShape
     
    46464608)
    46474609)
    4648 *146 (PortIoOut
     4610*145 (PortIoOut
    46494611uid 3722,0
    46504612shape (CompositeShape
     
    46904652)
    46914653)
    4692 *147 (PortIoOut
     4654*146 (PortIoOut
    46934655uid 3728,0
    46944656shape (CompositeShape
     
    47344696)
    47354697)
    4736 *148 (PortIoOut
     4698*147 (PortIoOut
    47374699uid 3734,0
    47384700shape (CompositeShape
     
    47784740)
    47794741)
    4780 *149 (PortIoOut
     4742*148 (PortIoOut
    47814743uid 3740,0
    47824744shape (CompositeShape
     
    48224784)
    48234785)
    4824 *150 (PortIoOut
     4786*149 (PortIoOut
    48254787uid 3746,0
    48264788shape (CompositeShape
     
    48664828)
    48674829)
    4868 *151 (PortIoOut
     4830*150 (PortIoOut
    48694831uid 3752,0
    48704832shape (CompositeShape
     
    49104872)
    49114873)
    4912 *152 (PortIoOut
     4874*151 (PortIoOut
    49134875uid 3758,0
    49144876shape (CompositeShape
     
    49544916)
    49554917)
    4956 *153 (Net
     4918*152 (Net
    49574919uid 3864,0
    49584920decl (Decl
    49594921n "TRG_V"
    49604922t "std_logic"
    4961 o 42
     4923o 43
    49624924suid 126,0
    49634925)
     
    49674929font "Courier New,8,0"
    49684930)
    4969 xt "39000,36600,53500,37400"
     4931xt "39000,37400,53500,38200"
    49704932st "TRG_V          : std_logic"
    49714933)
    49724934)
    4973 *154 (Net
     4935*153 (Net
    49744936uid 3866,0
    49754937decl (Decl
    49764938n "RS485_C_RE"
    49774939t "std_logic"
    4978 o 32
     4940o 33
    49794941suid 127,0
    49804942)
     
    49844946font "Courier New,8,0"
    49854947)
    4986 xt "39000,28600,53500,29400"
     4948xt "39000,29400,53500,30200"
    49874949st "RS485_C_RE     : std_logic"
    49884950)
    49894951)
    4990 *155 (Net
     4952*154 (Net
    49914953uid 3868,0
    49924954decl (Decl
    49934955n "RS485_C_DE"
    49944956t "std_logic"
    4995 o 31
     4957o 32
    49964958suid 128,0
    49974959)
     
    50014963font "Courier New,8,0"
    50024964)
    5003 xt "39000,27800,53500,28600"
     4965xt "39000,28600,53500,29400"
    50044966st "RS485_C_DE     : std_logic"
    50054967)
    50064968)
    5007 *156 (Net
     4969*155 (Net
    50084970uid 3870,0
    50094971decl (Decl
    50104972n "RS485_E_RE"
    50114973t "std_logic"
    5012 o 34
     4974o 35
    50134975suid 129,0
    50144976)
     
    50184980font "Courier New,8,0"
    50194981)
    5020 xt "39000,30200,53500,31000"
     4982xt "39000,31000,53500,31800"
    50214983st "RS485_E_RE     : std_logic"
    50224984)
    50234985)
    5024 *157 (Net
     4986*156 (Net
    50254987uid 3872,0
    50264988decl (Decl
    50274989n "RS485_E_DE"
    50284990t "std_logic"
    5029 o 33
     4991o 34
    50304992suid 130,0
    50314993)
     
    50354997font "Courier New,8,0"
    50364998)
    5037 xt "39000,29400,53500,30200"
     4999xt "39000,30200,53500,31000"
    50385000st "RS485_E_DE     : std_logic"
    50395001)
    50405002)
    5041 *158 (Net
     5003*157 (Net
    50425004uid 3874,0
    50435005decl (Decl
    50445006n "DENABLE"
    50455007t "std_logic"
    5046 o 22
     5008o 23
    50475009suid 131,0
    50485010i "'0'"
     
    50535015font "Courier New,8,0"
    50545016)
    5055 xt "39000,20600,68000,21400"
     5017xt "39000,21400,68000,22200"
    50565018st "DENABLE        : std_logic                      := '0'"
    50575019)
    50585020)
    5059 *159 (Net
     5021*158 (Net
    50605022uid 3876,0
    50615023decl (Decl
    50625024n "SRIN"
    50635025t "std_logic"
    5064 o 36
     5026o 37
    50655027suid 132,0
    50665028)
     
    50705032font "Courier New,8,0"
    50715033)
    5072 xt "39000,31800,53500,32600"
     5034xt "39000,32600,53500,33400"
    50735035st "SRIN           : std_logic"
    50745036)
    50755037)
    5076 *160 (Net
     5038*159 (Net
    50775039uid 3878,0
    50785040decl (Decl
    50795041n "EE_CS"
    50805042t "std_logic"
    5081 o 27
     5043o 28
    50825044suid 133,0
    50835045)
     
    50875049font "Courier New,8,0"
    50885050)
    5089 xt "39000,24600,53500,25400"
     5051xt "39000,25400,53500,26200"
    50905052st "EE_CS          : std_logic"
    50915053)
    50925054)
    5093 *161 (Net
     5055*160 (Net
    50945056uid 3880,0
    50955057decl (Decl
     
    50975059t "std_logic_vector"
    50985060b "( 2 DOWNTO 0 )"
    5099 o 28
     5061o 29
    51005062suid 134,0
    51015063i "(others => '1')"
     
    51065068font "Courier New,8,0"
    51075069)
    5108 xt "39000,25400,74000,26200"
     5070xt "39000,26200,74000,27000"
    51095071st "LED            : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')"
    51105072)
    51115073)
    5112 *162 (PortIoOut
     5074*161 (PortIoOut
    51135075uid 3995,0
    51145076shape (CompositeShape
     
    51555117)
    51565118)
    5157 *163 (PortIoOut
     5119*162 (PortIoOut
    51585120uid 4001,0
    51595121shape (CompositeShape
     
    52005162)
    52015163)
    5202 *164 (PortIoOut
     5164*163 (PortIoOut
    52035165uid 4007,0
    52045166shape (CompositeShape
     
    52455207)
    52465208)
    5247 *165 (PortIoOut
     5209*164 (PortIoOut
    52485210uid 4013,0
    52495211shape (CompositeShape
     
    52905252)
    52915253)
    5292 *166 (PortIoOut
     5254*165 (PortIoOut
    52935255uid 4916,0
    52945256shape (CompositeShape
     
    53345296)
    53355297)
    5336 *167 (Net
     5298*166 (Net
    53375299uid 5320,0
    53385300decl (Decl
     
    53405302t "std_logic_vector"
    53415303b "(7 DOWNTO 0)"
    5342 o 25
     5304o 26
    53435305suid 141,0
    53445306i "(OTHERS => '0')"
     
    53495311font "Courier New,8,0"
    53505312)
    5351 xt "39000,23000,74000,23800"
     5313xt "39000,23800,74000,24600"
    53525314st "D_T            : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')"
    53535315)
    53545316)
    5355 *168 (PortIoIn
     5317*167 (PortIoIn
    53565318uid 5650,0
    53575319shape (CompositeShape
     
    53665328sl 0
    53675329ro 270
    5368 xt "-30000,88625,-28500,89375"
     5330xt "9000,78625,10500,79375"
    53695331)
    53705332(Line
     
    53725334sl 0
    53735335ro 270
    5374 xt "-28500,89000,-28000,89000"
    5375 pts [
    5376 "-28500,89000"
    5377 "-28000,89000"
     5336xt "10500,79000,11000,79000"
     5337pts [
     5338"10500,79000"
     5339"11000,79000"
    53785340]
    53795341)
     
    53905352va (VaSet
    53915353)
    5392 xt "-35500,88500,-31000,89500"
     5354xt "3500,78500,8000,79500"
    53935355st "TEST_TRG"
    53945356ju 2
    5395 blo "-31000,89300"
    5396 tm "WireNameMgr"
    5397 )
    5398 )
    5399 )
    5400 *169 (Net
     5357blo "8000,79300"
     5358tm "WireNameMgr"
     5359)
     5360)
     5361)
     5362*168 (Net
    54015363uid 5662,0
    54025364decl (Decl
     
    54155377)
    54165378)
    5417 *170 (Net
     5379*169 (Net
    54185380uid 6138,0
    54195381decl (Decl
    54205382n "TRG_OR"
    54215383t "std_logic"
    5422 o 53
     5384o 54
    54235385suid 146,0
    54245386)
     
    54285390font "Courier New,8,0"
    54295391)
    5430 xt "39000,46400,57000,47200"
     5392xt "39000,47200,57000,48000"
    54315393st "SIGNAL TRG_OR         : std_logic"
    54325394)
    54335395)
    5434 *171 (SaComponent
    5435 uid 6250,0
    5436 optionalChildren [
    5437 *172 (CptPort
    5438 uid 6235,0
    5439 ps "OnEdgeStrategy"
    5440 shape (Triangle
    5441 uid 6236,0
    5442 ro 90
    5443 va (VaSet
    5444 vasetType 1
    5445 fg "0,65535,0"
    5446 )
    5447 xt "-11750,87625,-11000,88375"
    5448 )
    5449 tg (CPTG
    5450 uid 6237,0
    5451 ps "CptPortTextPlaceStrategy"
    5452 stg "VerticalLayoutStrategy"
    5453 f (Text
    5454 uid 6238,0
    5455 va (VaSet
    5456 )
    5457 xt "-10000,87500,-8700,88500"
    5458 st "clk"
    5459 blo "-10000,88300"
    5460 )
    5461 )
    5462 thePort (LogicalPort
    5463 decl (Decl
    5464 n "clk"
    5465 t "STD_LOGIC"
    5466 preAdd 0
    5467 posAdd 0
    5468 o 1
    5469 suid 1,0
    5470 )
    5471 )
    5472 )
    5473 *173 (CptPort
    5474 uid 6239,0
    5475 ps "OnEdgeStrategy"
    5476 shape (Triangle
    5477 uid 6240,0
    5478 ro 90
    5479 va (VaSet
    5480 vasetType 1
    5481 fg "0,65535,0"
    5482 )
    5483 xt "-11750,88625,-11000,89375"
    5484 )
    5485 tg (CPTG
    5486 uid 6241,0
    5487 ps "CptPortTextPlaceStrategy"
    5488 stg "VerticalLayoutStrategy"
    5489 f (Text
    5490 uid 6242,0
    5491 va (VaSet
    5492 )
    5493 xt "-10000,88500,-5800,89500"
    5494 st "trigger_in"
    5495 blo "-10000,89300"
    5496 )
    5497 )
    5498 thePort (LogicalPort
    5499 decl (Decl
    5500 n "trigger_in"
    5501 t "STD_LOGIC"
    5502 prec "--           rst : in  STD_LOGIC;"
    5503 preAdd 0
    5504 posAdd 0
    5505 o 2
    5506 suid 2,0
    5507 )
    5508 )
    5509 )
    5510 *174 (CptPort
    5511 uid 6243,0
    5512 ps "OnEdgeStrategy"
    5513 shape (Triangle
    5514 uid 6244,0
    5515 ro 90
    5516 va (VaSet
    5517 vasetType 1
    5518 fg "0,65535,0"
    5519 )
    5520 xt "1000,88625,1750,89375"
    5521 )
    5522 tg (CPTG
    5523 uid 6245,0
    5524 ps "CptPortTextPlaceStrategy"
    5525 stg "RightVerticalLayoutStrategy"
    5526 f (Text
    5527 uid 6246,0
    5528 va (VaSet
    5529 )
    5530 xt "-4600,88500,0,89500"
    5531 st "trigger_out"
    5532 ju 2
    5533 blo "0,89300"
    5534 )
    5535 )
    5536 thePort (LogicalPort
    5537 m 1
    5538 decl (Decl
    5539 n "trigger_out"
    5540 t "STD_LOGIC"
    5541 preAdd 0
    5542 posAdd 0
    5543 o 3
    5544 suid 3,0
    5545 i "'0'"
    5546 )
    5547 )
    5548 )
    5549 ]
    5550 shape (Rectangle
    5551 uid 6251,0
    5552 va (VaSet
    5553 vasetType 1
    5554 fg "0,65535,0"
    5555 lineColor "0,32896,0"
    5556 lineWidth 2
    5557 )
    5558 xt "-11000,87000,1000,92000"
    5559 )
    5560 oxt "25000,13000,37000,18000"
    5561 ttg (MlTextGroup
    5562 uid 6252,0
    5563 ps "CenterOffsetStrategy"
    5564 stg "VerticalLayoutStrategy"
    5565 textVec [
    5566 *175 (Text
    5567 uid 6253,0
    5568 va (VaSet
    5569 font "Arial,8,1"
    5570 )
    5571 xt "-10800,92000,-4200,93000"
    5572 st "FACT_FAD_LIB"
    5573 blo "-10800,92800"
    5574 tm "BdLibraryNameMgr"
    5575 )
    5576 *176 (Text
    5577 uid 6254,0
    5578 va (VaSet
    5579 font "Arial,8,1"
    5580 )
    5581 xt "-10800,93000,-6400,94000"
    5582 st "debouncer"
    5583 blo "-10800,93800"
    5584 tm "CptNameMgr"
    5585 )
    5586 *177 (Text
    5587 uid 6255,0
    5588 va (VaSet
    5589 font "Arial,8,1"
    5590 )
    5591 xt "-10800,94000,-9800,95000"
    5592 st "I0"
    5593 blo "-10800,94800"
    5594 tm "InstanceNameMgr"
    5595 )
    5596 ]
    5597 )
    5598 ga (GenericAssociation
    5599 uid 6256,0
    5600 ps "EdgeToEdgeStrategy"
    5601 matrix (Matrix
    5602 uid 6257,0
    5603 text (MLText
    5604 uid 6258,0
    5605 va (VaSet
    5606 font "Courier New,8,0"
    5607 )
    5608 xt "-11000,86200,4000,87000"
    5609 st "WIDTH = 17    ( INTEGER )  "
    5610 )
    5611 header ""
    5612 )
    5613 elements [
    5614 (GiElement
    5615 name "WIDTH"
    5616 type "INTEGER"
    5617 value "17"
    5618 )
    5619 ]
    5620 )
    5621 viewicon (ZoomableIcon
    5622 uid 6259,0
    5623 sl 0
    5624 va (VaSet
    5625 vasetType 1
    5626 fg "49152,49152,49152"
    5627 )
    5628 xt "-10750,90250,-9250,91750"
    5629 iconName "VhdlFileViewIcon.png"
    5630 iconMaskName "VhdlFileViewIcon.msk"
    5631 ftype 10
    5632 )
    5633 ordering 1
    5634 viewiconposition 0
    5635 portVis (PortSigDisplay
    5636 )
    5637 archFileType "UNKNOWN"
    5638 )
    5639 *178 (Net
    5640 uid 6278,0
    5641 decl (Decl
    5642 n "trigger_out"
    5643 t "STD_LOGIC"
    5644 preAdd 0
    5645 posAdd 0
    5646 o 60
    5647 suid 147,0
    5648 i "'0'"
    5649 )
    5650 declText (MLText
    5651 uid 6279,0
    5652 va (VaSet
    5653 font "Courier New,8,0"
    5654 )
    5655 xt "39000,52000,71500,52800"
    5656 st "SIGNAL trigger_out    : STD_LOGIC                      := '0'"
    5657 )
    5658 )
    5659 *179 (Net
    5660 uid 6326,0
    5661 decl (Decl
    5662 n "not_TEST_TRG"
    5663 t "STD_LOGIC"
    5664 o 58
    5665 suid 148,0
    5666 )
    5667 declText (MLText
    5668 uid 6327,0
    5669 va (VaSet
    5670 font "Courier New,8,0"
    5671 )
    5672 xt "39000,50400,57000,51200"
    5673 st "SIGNAL not_TEST_TRG   : STD_LOGIC"
    5674 )
    5675 )
    5676 *180 (MWC
    5677 uid 6539,0
    5678 optionalChildren [
    5679 *181 (CptPort
    5680 uid 6526,0
    5681 optionalChildren [
    5682 *182 (Line
    5683 uid 6530,0
    5684 layer 5
    5685 sl 0
    5686 va (VaSet
    5687 vasetType 3
    5688 )
    5689 xt "-22000,89000,-20999,89000"
    5690 pts [
    5691 "-22000,89000"
    5692 "-20999,89000"
    5693 ]
    5694 )
    5695 ]
    5696 ps "OnEdgeStrategy"
    5697 shape (Triangle
    5698 uid 6527,0
    5699 ro 90
    5700 va (VaSet
    5701 vasetType 1
    5702 isHidden 1
    5703 fg "0,65535,65535"
    5704 )
    5705 xt "-22750,88625,-22000,89375"
    5706 )
    5707 tg (CPTG
    5708 uid 6528,0
    5709 ps "CptPortTextPlaceStrategy"
    5710 stg "VerticalLayoutStrategy"
    5711 f (Text
    5712 uid 6529,0
    5713 sl 0
    5714 va (VaSet
    5715 isHidden 1
    5716 font "arial,8,0"
    5717 )
    5718 xt "-25000,88500,-23600,89500"
    5719 st "din"
    5720 blo "-25000,89300"
    5721 )
    5722 s (Text
    5723 uid 6548,0
    5724 sl 0
    5725 va (VaSet
    5726 font "arial,8,0"
    5727 )
    5728 xt "-25000,89500,-25000,89500"
    5729 blo "-25000,89500"
    5730 )
    5731 )
    5732 thePort (LogicalPort
    5733 decl (Decl
    5734 n "din"
    5735 t "std_logic"
    5736 o 11
    5737 suid 1,0
    5738 )
    5739 )
    5740 )
    5741 *183 (CptPort
    5742 uid 6531,0
    5743 optionalChildren [
    5744 *184 (Line
    5745 uid 6535,0
    5746 layer 5
    5747 sl 0
    5748 va (VaSet
    5749 vasetType 3
    5750 )
    5751 xt "-17249,89000,-17000,89000"
    5752 pts [
    5753 "-17000,89000"
    5754 "-17249,89000"
    5755 ]
    5756 )
    5757 *185 (Circle
    5758 uid 6536,0
    5759 va (VaSet
    5760 vasetType 1
    5761 fg "65535,65535,65535"
    5762 lineColor "26368,26368,26368"
    5763 )
    5764 xt "-17999,88625,-17249,89375"
    5765 radius 375
    5766 )
    5767 ]
    5768 ps "OnEdgeStrategy"
    5769 shape (Triangle
    5770 uid 6532,0
    5771 ro 90
    5772 va (VaSet
    5773 vasetType 1
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     7346"51250,108000"
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     7422"32000,113000"
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     7537"100000,89000"
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     7573"94000,87000"
     7574"111000,87000"
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     7576)
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     7612"11000,77000"
     7613"13000,77000"
     7614]
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     7617end &176
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     7651"21000,70000"
     7652"24000,70000"
     7653]
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     7656end &71
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     7690"51250,70000"
     7691"32000,70000"
     7692]
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     7727"21000,95000"
     7728"24000,95000"
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     7730)
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     7732end &81
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     7765xt "21000,96000,24000,96000"
     7766pts [
     7767"21000,96000"
     7768"24000,96000"
     7769]
     7770)
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     7772end &81
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     7792tm "WireNameMgr"
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     7806pts [
     7807"21000,97000"
     7808"24000,97000"
     7809]
     7810)
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     7812end &81
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     7845xt "21000,98000,24000,98000"
     7846pts [
     7847"21000,98000"
     7848"24000,98000"
     7849]
     7850)
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     7852end &81
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     7872tm "WireNameMgr"
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     7884xt "21000,113000,24000,113000"
     7885pts [
     7886"21000,113000"
     7887"24000,113000"
     7888]
     7889)
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     7909blo "23000,112800"
     7910tm "WireNameMgr"
     7911)
     7912)
     7913on &97
     7914)
     7915*258 (Wire
     7916uid 3438,0
     7917shape (OrthoPolyLine
     7918uid 3439,0
     7919va (VaSet
     7920vasetType 3
     7921)
     7922xt "21000,114000,24000,114000"
     7923pts [
     7924"21000,114000"
     7925"24000,114000"
     7926]
     7927)
     7928start &162
     7929end &93
     7930sat 32
     7931eat 2
     7932stc 0
     7933st 0
     7934sf 1
     7935si 0
     7936tg (WTG
     7937uid 3442,0
     7938ps "ConnStartEndStrategy"
     7939stg "STSignalDisplayStrategy"
     7940f (Text
     7941uid 3443,0
     7942va (VaSet
     7943isHidden 1
     7944)
     7945xt "23000,113000,27400,114000"
     7946st "D1_SRCLK"
     7947blo "23000,113800"
     7948tm "WireNameMgr"
     7949)
     7950)
     7951on &98
     7952)
     7953*259 (Wire
     7954uid 3446,0
     7955shape (OrthoPolyLine
     7956uid 3447,0
     7957va (VaSet
     7958vasetType 3
     7959)
     7960xt "21000,115000,24000,115000"
     7961pts [
     7962"21000,115000"
     7963"24000,115000"
     7964]
     7965)
     7966start &163
     7967end &93
     7968sat 32
     7969eat 2
     7970stc 0
     7971st 0
     7972sf 1
     7973si 0
     7974tg (WTG
     7975uid 3450,0
     7976ps "ConnStartEndStrategy"
     7977stg "STSignalDisplayStrategy"
     7978f (Text
     7979uid 3451,0
     7980va (VaSet
     7981isHidden 1
     7982)
     7983xt "23000,114000,27400,115000"
     7984st "D2_SRCLK"
     7985blo "23000,114800"
     7986tm "WireNameMgr"
     7987)
     7988)
     7989on &99
     7990)
     7991*260 (Wire
     7992uid 3454,0
     7993shape (OrthoPolyLine
     7994uid 3455,0
     7995va (VaSet
     7996vasetType 3
     7997)
     7998xt "21000,116000,24000,116000"
     7999pts [
     8000"21000,116000"
     8001"24000,116000"
     8002]
     8003)
     8004start &164
     8005end &93
     8006sat 32
     8007eat 2
     8008stc 0
     8009st 0
     8010sf 1
     8011si 0
     8012tg (WTG
     8013uid 3458,0
     8014ps "ConnStartEndStrategy"
     8015stg "STSignalDisplayStrategy"
     8016f (Text
     8017uid 3459,0
     8018va (VaSet
     8019isHidden 1
     8020)
     8021xt "23000,115000,27400,116000"
     8022st "D3_SRCLK"
     8023blo "23000,115800"
     8024tm "WireNameMgr"
     8025)
     8026)
     8027on &100
     8028)
     8029*261 (Wire
     8030uid 3574,0
     8031shape (OrthoPolyLine
     8032uid 3575,0
     8033va (VaSet
     8034vasetType 3
     8035)
     8036xt "108000,89000,111000,89000"
     8037pts [
     8038"111000,89000"
     8039"108000,89000"
     8040]
     8041)
     8042start &118
     8043end &114
     8044sat 32
     8045eat 2
     8046stc 0
     8047st 0
     8048sf 1
     8049si 0
     8050tg (WTG
     8051uid 3578,0
     8052ps "ConnStartEndStrategy"
     8053stg "STSignalDisplayStrategy"
     8054f (Text
     8055uid 3579,0
     8056va (VaSet
     8057isHidden 1
     8058)
     8059xt "108000,88000,110800,89000"
     8060st "T0_CS"
     8061blo "108000,88800"
     8062tm "WireNameMgr"
     8063)
     8064)
     8065on &122
     8066)
     8067*262 (Wire
     8068uid 3582,0
     8069shape (OrthoPolyLine
     8070uid 3583,0
     8071va (VaSet
     8072vasetType 3
     8073)
     8074xt "108000,90000,111000,90000"
     8075pts [
     8076"111000,90000"
     8077"108000,90000"
     8078]
     8079)
     8080start &119
     8081end &114
     8082sat 32
     8083eat 2
     8084stc 0
     8085st 0
     8086sf 1
     8087si 0
     8088tg (WTG
     8089uid 3586,0
     8090ps "ConnStartEndStrategy"
     8091stg "STSignalDisplayStrategy"
     8092f (Text
     8093uid 3587,0
     8094va (VaSet
     8095isHidden 1
     8096)
     8097xt "108000,89000,110800,90000"
     8098st "T1_CS"
     8099blo "108000,89800"
     8100tm "WireNameMgr"
     8101)
     8102)
     8103on &123
     8104)
     8105*263 (Wire
     8106uid 3590,0
     8107shape (OrthoPolyLine
     8108uid 3591,0
     8109va (VaSet
     8110vasetType 3
     8111)
     8112xt "108000,91000,111000,91000"
     8113pts [
     8114"111000,91000"
     8115"108000,91000"
     8116]
     8117)
     8118start &120
     8119end &114
     8120sat 32
     8121eat 2
     8122stc 0
     8123st 0
     8124sf 1
     8125si 0
     8126tg (WTG
     8127uid 3594,0
     8128ps "ConnStartEndStrategy"
     8129stg "STSignalDisplayStrategy"
     8130f (Text
     8131uid 3595,0
     8132va (VaSet
     8133isHidden 1
     8134)
     8135xt "108000,90000,110800,91000"
     8136st "T2_CS"
     8137blo "108000,90800"
     8138tm "WireNameMgr"
     8139)
     8140)
     8141on &124
     8142)
     8143*264 (Wire
     8144uid 3598,0
     8145shape (OrthoPolyLine
     8146uid 3599,0
     8147va (VaSet
     8148vasetType 3
     8149)
     8150xt "108000,92000,111000,92000"
     8151pts [
     8152"111000,92000"
     8153"108000,92000"
     8154]
     8155)
     8156start &121
     8157end &114
     8158sat 32
     8159eat 2
     8160stc 0
     8161st 0
     8162sf 1
     8163si 0
     8164tg (WTG
     8165uid 3602,0
     8166ps "ConnStartEndStrategy"
     8167stg "STSignalDisplayStrategy"
     8168f (Text
     8169uid 3603,0
     8170va (VaSet
     8171isHidden 1
     8172)
     8173xt "108000,91000,110800,92000"
     8174st "T3_CS"
     8175blo "108000,91800"
     8176tm "WireNameMgr"
     8177)
     8178)
     8179on &125
     8180)
     8181*265 (Wire
     8182uid 3682,0
     8183shape (OrthoPolyLine
     8184uid 3683,0
     8185va (VaSet
     8186vasetType 3
     8187)
     8188xt "80750,100000,111000,100000"
     8189pts [
     8190"80750,100000"
     8191"111000,100000"
     8192]
     8193)
     8194start &42
     8195end &137
     8196sat 32
     8197eat 32
     8198stc 0
     8199st 0
     8200sf 1
     8201si 0
     8202tg (WTG
     8203uid 3686,0
     8204ps "ConnStartEndStrategy"
     8205stg "STSignalDisplayStrategy"
     8206f (Text
     8207uid 3687,0
     8208va (VaSet
     8209isHidden 1
     8210)
     8211xt "82000,99000,84400,100000"
     8212st "MOSI"
     8213blo "82000,99800"
     8214tm "WireNameMgr"
     8215)
     8216)
     8217on &136
     8218)
     8219*266 (Wire
     8220uid 3778,0
     8221shape (OrthoPolyLine
     8222uid 3779,0
     8223va (VaSet
     8224vasetType 3
     8225)
     8226xt "108000,103000,111000,103000"
     8227pts [
     8228"111000,103000"
     8229"108000,103000"
     8230]
     8231)
     8232start &143
     8233end &139
     8234sat 32
     8235eat 2
     8236stc 0
     8237st 0
     8238sf 1
     8239si 0
     8240tg (WTG
     8241uid 3782,0
     8242ps "ConnStartEndStrategy"
     8243stg "STSignalDisplayStrategy"
     8244f (Text
     8245uid 3783,0
     8246va (VaSet
     8247isHidden 1
     8248)
     8249xt "108000,102000,111000,103000"
     8250st "TRG_V"
     8251blo "108000,102800"
     8252tm "WireNameMgr"
     8253)
     8254)
     8255on &152
     8256)
     8257*267 (Wire
     8258uid 3786,0
     8259shape (OrthoPolyLine
     8260uid 3787,0
     8261va (VaSet
     8262vasetType 3
     8263)
     8264xt "108000,104000,111000,104000"
     8265pts [
     8266"111000,104000"
     8267"108000,104000"
     8268]
     8269)
     8270start &144
     8271end &139
     8272sat 32
     8273eat 2
     8274stc 0
     8275st 0
     8276sf 1
     8277si 0
     8278tg (WTG
     8279uid 3790,0
     8280ps "ConnStartEndStrategy"
     8281stg "STSignalDisplayStrategy"
     8282f (Text
     8283uid 3791,0
     8284va (VaSet
     8285isHidden 1
     8286)
     8287xt "108000,103000,113600,104000"
     8288st "RS485_C_RE"
     8289blo "108000,103800"
     8290tm "WireNameMgr"
     8291)
     8292)
     8293on &153
     8294)
     8295*268 (Wire
     8296uid 3794,0
     8297shape (OrthoPolyLine
     8298uid 3795,0
     8299va (VaSet
     8300vasetType 3
     8301)
     8302xt "108000,105000,111000,105000"
     8303pts [
     8304"111000,105000"
     8305"108000,105000"
     8306]
     8307)
     8308start &145
     8309end &139
     8310sat 32
     8311eat 2
     8312stc 0
     8313st 0
     8314sf 1
     8315si 0
     8316tg (WTG
     8317uid 3798,0
     8318ps "ConnStartEndStrategy"
     8319stg "STSignalDisplayStrategy"
     8320f (Text
     8321uid 3799,0
     8322va (VaSet
     8323isHidden 1
     8324)
     8325xt "108000,104000,113600,105000"
     8326st "RS485_C_DE"
     8327blo "108000,104800"
     8328tm "WireNameMgr"
     8329)
     8330)
     8331on &154
     8332)
     8333*269 (Wire
     8334uid 3802,0
     8335shape (OrthoPolyLine
     8336uid 3803,0
     8337va (VaSet
     8338vasetType 3
     8339)
     8340xt "108000,106000,111000,106000"
     8341pts [
     8342"111000,106000"
     8343"108000,106000"
     8344]
     8345)
     8346start &146
     8347end &139
     8348sat 32
     8349eat 2
     8350stc 0
     8351st 0
     8352sf 1
     8353si 0
     8354tg (WTG
     8355uid 3806,0
     8356ps "ConnStartEndStrategy"
     8357stg "STSignalDisplayStrategy"
     8358f (Text
     8359uid 3807,0
     8360va (VaSet
     8361isHidden 1
     8362)
     8363xt "108000,105000,113500,106000"
     8364st "RS485_E_RE"
     8365blo "108000,105800"
     8366tm "WireNameMgr"
     8367)
     8368)
     8369on &155
     8370)
     8371*270 (Wire
     8372uid 3810,0
     8373shape (OrthoPolyLine
     8374uid 3811,0
     8375va (VaSet
     8376vasetType 3
     8377)
     8378xt "108000,107000,111000,107000"
     8379pts [
     8380"111000,107000"
     8381"108000,107000"
     8382]
     8383)
     8384start &147
     8385end &139
     8386sat 32
     8387eat 2
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     8389st 0
     8390sf 1
     8391si 0
     8392tg (WTG
     8393uid 3814,0
     8394ps "ConnStartEndStrategy"
     8395stg "STSignalDisplayStrategy"
     8396f (Text
     8397uid 3815,0
     8398va (VaSet
     8399isHidden 1
     8400)
     8401xt "108000,106000,113500,107000"
     8402st "RS485_E_DE"
     8403blo "108000,106800"
     8404tm "WireNameMgr"
     8405)
     8406)
     8407on &156
     8408)
     8409*271 (Wire
     8410uid 3826,0
     8411shape (OrthoPolyLine
     8412uid 3827,0
     8413va (VaSet
     8414vasetType 3
     8415)
     8416xt "108000,109000,111000,109000"
     8417pts [
     8418"111000,109000"
     8419"108000,109000"
     8420]
     8421)
     8422start &149
     8423end &139
     8424sat 32
     8425eat 2
     8426stc 0
     8427st 0
     8428sf 1
     8429si 0
     8430tg (WTG
     8431uid 3830,0
     8432ps "ConnStartEndStrategy"
     8433stg "STSignalDisplayStrategy"
     8434f (Text
     8435uid 3831,0
     8436va (VaSet
     8437isHidden 1
     8438)
     8439xt "108000,108000,110300,109000"
     8440st "SRIN"
     8441blo "108000,108800"
     8442tm "WireNameMgr"
     8443)
     8444)
     8445on &158
     8446)
     8447*272 (Wire
     8448uid 3834,0
     8449shape (OrthoPolyLine
     8450uid 3835,0
     8451va (VaSet
     8452vasetType 3
     8453)
     8454xt "108000,110000,111000,110000"
     8455pts [
     8456"111000,110000"
     8457"108000,110000"
     8458]
     8459)
     8460start &150
     8461end &139
     8462sat 32
     8463eat 2
     8464stc 0
     8465st 0
     8466sf 1
     8467si 0
     8468tg (WTG
     8469uid 3838,0
     8470ps "ConnStartEndStrategy"
     8471stg "STSignalDisplayStrategy"
     8472f (Text
     8473uid 3839,0
     8474va (VaSet
     8475isHidden 1
     8476)
     8477xt "108000,109000,110900,110000"
     8478st "EE_CS"
     8479blo "108000,109800"
     8480tm "WireNameMgr"
     8481)
     8482)
     8483on &159
     8484)
     8485*273 (Wire
     8486uid 3842,0
     8487shape (OrthoPolyLine
     8488uid 3843,0
     8489va (VaSet
     8490vasetType 3
     8491lineWidth 2
     8492)
     8493xt "108000,111000,111000,111000"
     8494pts [
     8495"111000,111000"
     8496"108000,111000"
     8497]
     8498)
     8499start &151
     8500end &139
     8501sat 32
     8502eat 2
     8503sty 1
     8504stc 0
     8505st 0
     8506sf 1
     8507si 0
     8508tg (WTG
     8509uid 3846,0
     8510ps "ConnStartEndStrategy"
     8511stg "STSignalDisplayStrategy"
     8512f (Text
     8513uid 3847,0
     8514va (VaSet
     8515isHidden 1
     8516)
     8517xt "108000,110000,109900,111000"
     8518st "LED"
     8519blo "108000,110800"
     8520tm "WireNameMgr"
     8521)
     8522)
     8523on &160
     8524)
     8525*274 (Wire
     8526uid 4942,0
     8527shape (OrthoPolyLine
     8528uid 4943,0
     8529va (VaSet
     8530vasetType 3
     8531lineWidth 2
     8532)
     8533xt "80750,120000,111000,120000"
     8534pts [
     8535"80750,120000"
     8536"111000,120000"
     8537]
     8538)
     8539start &14
     8540end &165
    75908541sat 32
    75918542eat 32
     
    75968547si 0
    75978548tg (WTG
    7598 uid 1837,0
     8549uid 4948,0
    75998550ps "ConnStartEndStrategy"
    76008551stg "STSignalDisplayStrategy"
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    7602 uid 1838,0
     8553uid 4949,0
    76038554va (VaSet
    76048555isHidden 1
    76058556)
    7606 xt "22000,108000,23900,109000"
    7607 st "D_A"
    7608 blo "22000,108800"
    7609 tm "WireNameMgr"
    7610 )
    7611 )
    7612 on &111
    7613 )
    7614 *255 (Wire
    7615 uid 1841,0
     8557xt "82750,117000,84650,118000"
     8558st "D_T"
     8559blo "82750,117800"
     8560tm "WireNameMgr"
     8561)
     8562)
     8563on &166
     8564)
     8565*275 (Wire
     8566uid 6130,0
    76168567shape (OrthoPolyLine
    7617 uid 1842,0
     8568uid 6131,0
    76188569va (VaSet
    76198570vasetType 3
    76208571)
    7621 xt "21000,110000,51250,110000"
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    7623 "51250,110000"
    7624 "21000,110000"
    7625 ]
    7626 )
    7627 start &31
    7628 end &112
     8572xt "19000,78000,51250,78000"
     8573pts [
     8574"19000,78000"
     8575"51250,78000"
     8576]
     8577)
     8578start &173
     8579end &15
     8580sat 32
     8581eat 32
     8582st 0
     8583sf 1
     8584si 0
     8585tg (WTG
     8586uid 6136,0
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     8588stg "STSignalDisplayStrategy"
     8589f (Text
     8590uid 6137,0
     8591va (VaSet
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     8593xt "21000,77000,24700,78000"
     8594st "TRG_OR"
     8595blo "21000,77800"
     8596tm "WireNameMgr"
     8597)
     8598)
     8599on &169
     8600)
     8601*276 (Wire
     8602uid 6306,0
     8603shape (OrthoPolyLine
     8604uid 6307,0
     8605va (VaSet
     8606vasetType 3
     8607)
     8608xt "11000,79000,13000,79000"
     8609pts [
     8610"11000,79000"
     8611"13000,79000"
     8612]
     8613)
     8614start &167
     8615end &171
    76298616sat 32
    76308617eat 32
     
    76348621si 0
    76358622tg (WTG
    7636 uid 1845,0
     8623uid 6312,0
    76378624ps "ConnStartEndStrategy"
    76388625stg "STSignalDisplayStrategy"
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    7640 uid 1846,0
     8627uid 6313,0
    76418628va (VaSet
    76428629isHidden 1
    76438630)
    7644 xt "22000,109000,25500,110000"
    7645 st "DWRITE"
    7646 blo "22000,109800"
    7647 tm "WireNameMgr"
    7648 )
    7649 )
    7650 on &113
    7651 )
    7652 *256 (Wire
    7653 uid 1865,0
     8631xt "13000,78000,17500,79000"
     8632st "TEST_TRG"
     8633blo "13000,78800"
     8634tm "WireNameMgr"
     8635)
     8636)
     8637on &168
     8638)
     8639*277 (Wire
     8640uid 6431,0
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    7655 uid 1866,0
     8642uid 6432,0
    76568643va (VaSet
    76578644vasetType 3
    76588645)
    7659 xt "21000,105000,51250,105000"
    7660 pts [
    7661 "21000,105000"
    7662 "51250,105000"
    7663 ]
    7664 )
    7665 start &102
    7666 end &32
     8646xt "80750,121000,111000,121000"
     8647pts [
     8648"80750,121000"
     8649"111000,121000"
     8650]
     8651)
     8652start &43
     8653end &148
    76678654sat 32
    76688655eat 32
     
    76728659si 0
    76738660tg (WTG
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     8661uid 6435,0
    76758662ps "ConnStartEndStrategy"
    76768663stg "STSignalDisplayStrategy"
    76778664f (Text
    7678 uid 1870,0
     8665uid 6436,0
    76798666va (VaSet
    76808667isHidden 1
    76818668)
    7682 xt "22000,104000,26600,105000"
    7683 st "D0_SROUT"
    7684 blo "22000,104800"
    7685 tm "WireNameMgr"
    7686 )
    7687 )
    7688 on &106
    7689 )
    7690 *257 (Wire
    7691 uid 1873,0
     8669xt "92000,120000,96000,121000"
     8670st "DENABLE"
     8671blo "92000,120800"
     8672tm "WireNameMgr"
     8673)
     8674)
     8675on &157
     8676)
     8677*278 (Wire
     8678uid 6787,0
    76928679shape (OrthoPolyLine
    7693 uid 1874,0
    7694 va (VaSet
    7695 vasetType 3
    7696 )
    7697 xt "21000,106000,51250,106000"
    7698 pts [
    7699 "21000,106000"
    7700 "51250,106000"
    7701 ]
    7702 )
    7703 start &103
    7704 end &33
    7705 sat 32
    7706 eat 32
    7707 stc 0
    7708 st 0
    7709 sf 1
    7710 si 0
    7711 tg (WTG
    7712 uid 1877,0
    7713 ps "ConnStartEndStrategy"
    7714 stg "STSignalDisplayStrategy"
    7715 f (Text
    7716 uid 1878,0
    7717 va (VaSet
    7718 isHidden 1
    7719 )
    7720 xt "22000,105000,26600,106000"
    7721 st "D1_SROUT"
    7722 blo "22000,105800"
    7723 tm "WireNameMgr"
    7724 )
    7725 )
    7726 on &107
    7727 )
    7728 *258 (Wire
    7729 uid 1881,0
    7730 shape (OrthoPolyLine
    7731 uid 1882,0
    7732 va (VaSet
    7733 vasetType 3
    7734 )
    7735 xt "21000,107000,51250,107000"
    7736 pts [
    7737 "21000,107000"
    7738 "51250,107000"
    7739 ]
    7740 )
    7741 start &104
    7742 end &34
    7743 sat 32
    7744 eat 32
    7745 stc 0
    7746 st 0
    7747 sf 1
    7748 si 0
    7749 tg (WTG
    7750 uid 1885,0
    7751 ps "ConnStartEndStrategy"
    7752 stg "STSignalDisplayStrategy"
    7753 f (Text
    7754 uid 1886,0
    7755 va (VaSet
    7756 isHidden 1
    7757 )
    7758 xt "22000,106000,26600,107000"
    7759 st "D2_SROUT"
    7760 blo "22000,106800"
    7761 tm "WireNameMgr"
    7762 )
    7763 )
    7764 on &108
    7765 )
    7766 *259 (Wire
    7767 uid 1889,0
    7768 shape (OrthoPolyLine
    7769 uid 1890,0
    7770 va (VaSet
    7771 vasetType 3
    7772 )
    7773 xt "21000,108000,51250,108000"
    7774 pts [
    7775 "21000,108000"
    7776 "51250,108000"
    7777 ]
    7778 )
    7779 start &105
    7780 end &35
    7781 sat 32
    7782 eat 32
    7783 stc 0
    7784 st 0
    7785 sf 1
    7786 si 0
    7787 tg (WTG
    7788 uid 1893,0
    7789 ps "ConnStartEndStrategy"
    7790 stg "STSignalDisplayStrategy"
    7791 f (Text
    7792 uid 1894,0
    7793 va (VaSet
    7794 isHidden 1
    7795 )
    7796 xt "22000,107000,26600,108000"
    7797 st "D3_SROUT"
    7798 blo "22000,107800"
    7799 tm "WireNameMgr"
    7800 )
    7801 )
    7802 on &109
    7803 )
    7804 *260 (Wire
    7805 uid 2269,0
    7806 shape (OrthoPolyLine
    7807 uid 2270,0
    7808 va (VaSet
    7809 vasetType 3
    7810 )
    7811 xt "-15000,69000,51250,88000"
    7812 pts [
    7813 "51250,69000"
    7814 "-15000,69000"
    7815 "-15000,88000"
    7816 "-11750,88000"
    7817 ]
    7818 )
    7819 start &26
    7820 end &172
    7821 sat 32
    7822 eat 32
    7823 stc 0
    7824 st 0
    7825 sf 1
    7826 si 0
    7827 tg (WTG
    7828 uid 2273,0
    7829 ps "ConnStartEndStrategy"
    7830 stg "STSignalDisplayStrategy"
    7831 f (Text
    7832 uid 2274,0
    7833 va (VaSet
    7834 isHidden 1
    7835 )
    7836 xt "50250,68000,53350,69000"
    7837 st "CLK_50"
    7838 blo "50250,68800"
    7839 tm "WireNameMgr"
    7840 )
    7841 )
    7842 on &63
    7843 )
    7844 *261 (Wire
    7845 uid 2409,0
    7846 shape (OrthoPolyLine
    7847 uid 2410,0
    7848 va (VaSet
    7849 vasetType 3
    7850 )
    7851 xt "21000,111000,51250,111000"
    7852 pts [
    7853 "51250,111000"
    7854 "21000,111000"
    7855 ]
    7856 )
    7857 start &36
    7858 end &65
    7859 sat 32
    7860 eat 32
    7861 stc 0
    7862 st 0
    7863 sf 1
    7864 si 0
    7865 tg (WTG
    7866 uid 2413,0
    7867 ps "ConnStartEndStrategy"
    7868 stg "STSignalDisplayStrategy"
    7869 f (Text
    7870 uid 2414,0
    7871 va (VaSet
    7872 isHidden 1
    7873 )
    7874 xt "22000,110000,26200,111000"
    7875 st "RSRLOAD"
    7876 blo "22000,110800"
    7877 tm "WireNameMgr"
    7878 )
    7879 )
    7880 on &64
    7881 )
    7882 *262 (Wire
    7883 uid 2423,0
    7884 shape (OrthoPolyLine
    7885 uid 2424,0
    7886 va (VaSet
    7887 vasetType 3
    7888 )
    7889 xt "32000,113000,51250,113000"
    7890 pts [
    7891 "51250,113000"
    7892 "32000,113000"
    7893 ]
    7894 )
    7895 start &37
    7896 end &94
    7897 sat 32
    7898 eat 1
    7899 stc 0
    7900 st 0
    7901 sf 1
    7902 si 0
    7903 tg (WTG
    7904 uid 2427,0
    7905 ps "ConnStartEndStrategy"
    7906 stg "STSignalDisplayStrategy"
    7907 f (Text
    7908 uid 2428,0
    7909 va (VaSet
    7910 isHidden 1
    7911 )
    7912 xt "66250,109000,69250,110000"
    7913 st "SRCLK"
    7914 blo "66250,109800"
    7915 tm "WireNameMgr"
    7916 )
    7917 )
    7918 on &66
    7919 )
    7920 *263 (Wire
    7921 uid 3009,0
    7922 shape (OrthoPolyLine
    7923 uid 3010,0
    7924 va (VaSet
    7925 vasetType 3
    7926 )
    7927 xt "80750,98000,111000,98000"
    7928 pts [
    7929 "80750,98000"
    7930 "111000,98000"
    7931 ]
    7932 )
    7933 start &39
    7934 end &127
    7935 sat 32
    7936 eat 32
    7937 stc 0
    7938 st 0
    7939 sf 1
    7940 si 0
    7941 tg (WTG
    7942 uid 3011,0
    7943 ps "ConnStartEndStrategy"
    7944 stg "STSignalDisplayStrategy"
    7945 f (Text
    7946 uid 3012,0
    7947 va (VaSet
    7948 isHidden 1
    7949 )
    7950 xt "82000,97000,84800,98000"
    7951 st "S_CLK"
    7952 blo "82000,97800"
    7953 tm "WireNameMgr"
    7954 )
    7955 )
    7956 on &128
    7957 )
    7958 *264 (Wire
    7959 uid 3015,0
    7960 shape (OrthoPolyLine
    7961 uid 3016,0
    7962 va (VaSet
    7963 vasetType 3
    7964 )
    7965 xt "80750,99000,111000,99000"
    7966 pts [
    7967 "80750,99000"
    7968 "111000,99000"
    7969 ]
    7970 )
    7971 start &41
    7972 end &136
    7973 sat 32
    7974 eat 32
    7975 stc 0
    7976 st 0
    7977 sf 1
    7978 si 0
    7979 tg (WTG
    7980 uid 3017,0
    7981 ps "ConnStartEndStrategy"
    7982 stg "STSignalDisplayStrategy"
    7983 f (Text
    7984 uid 3018,0
    7985 va (VaSet
    7986 isHidden 1
    7987 )
    7988 xt "82750,98000,85150,99000"
    7989 st "MISO"
    7990 blo "82750,98800"
    7991 tm "WireNameMgr"
    7992 )
    7993 )
    7994 on &139
    7995 )
    7996 *265 (Wire
    7997 uid 3021,0
    7998 shape (OrthoPolyLine
    7999 uid 3022,0
     8680uid 6788,0
    80008681va (VaSet
    80018682vasetType 3
    80028683lineWidth 2
    80038684)
    8004 xt "80750,89000,100000,89000"
    8005 pts [
    8006 "80750,89000"
    8007 "100000,89000"
    8008 ]
    8009 )
    8010 start &40
    8011 end &115
     8685xt "93000,132000,99000,132000"
     8686pts [
     8687"93000,132000"
     8688"99000,132000"
     8689]
     8690)
     8691start &193
     8692end &197
    80128693sat 32
    80138694eat 1
     
    80178698si 0
    80188699tg (WTG
    8019 uid 3023,0
     8700uid 6791,0
    80208701ps "ConnStartEndStrategy"
    80218702stg "STSignalDisplayStrategy"
    80228703f (Text
    8023 uid 3024,0
    8024 va (VaSet
    8025 )
    8026 xt "92000,88000,98500,89000"
    8027 st "sensor_cs : (3:0)"
    8028 blo "92000,88800"
    8029 tm "WireNameMgr"
    8030 )
    8031 )
    8032 on &67
    8033 )
    8034 *266 (Wire
    8035 uid 3027,0
     8704uid 6792,0
     8705va (VaSet
     8706isHidden 1
     8707)
     8708xt "95000,131000,101800,132000"
     8709st "D_PLLLCK : (3:0)"
     8710blo "95000,131800"
     8711tm "WireNameMgr"
     8712)
     8713)
     8714on &194
     8715)
     8716*279 (Wire
     8717uid 6880,0
    80368718shape (OrthoPolyLine
    8037 uid 3028,0
    8038 va (VaSet
    8039 vasetType 3
    8040 )
    8041 xt "94000,87000,111000,87000"
    8042 pts [
    8043 "94000,87000"
    8044 "111000,87000"
    8045 ]
    8046 )
    8047 start &231
    8048 end &114
    8049 ss 0
    8050 sat 32
    8051 eat 32
    8052 stc 0
    8053 st 0
    8054 sf 1
    8055 si 0
    8056 tg (WTG
    8057 uid 3031,0
    8058 ps "ConnStartEndStrategy"
    8059 stg "STSignalDisplayStrategy"
    8060 f (Text
    8061 uid 3032,0
    8062 va (VaSet
    8063 isHidden 1
    8064 )
    8065 xt "95000,86000,98600,87000"
    8066 st "DAC_CS"
    8067 blo "95000,86800"
    8068 tm "WireNameMgr"
    8069 )
    8070 )
    8071 on &68
    8072 )
    8073 *267 (Wire
    8074 uid 3218,0
    8075 shape (OrthoPolyLine
    8076 uid 3219,0
    8077 va (VaSet
    8078 vasetType 3
    8079 )
    8080 xt "11000,77000,13000,77000"
    8081 pts [
    8082 "11000,77000"
    8083 "13000,77000"
    8084 ]
    8085 )
    8086 start &47
    8087 end &196
    8088 sat 32
    8089 eat 32
    8090 stc 0
    8091 st 0
    8092 sf 1
    8093 si 0
    8094 tg (WTG
    8095 uid 3220,0
    8096 ps "ConnStartEndStrategy"
    8097 stg "STSignalDisplayStrategy"
    8098 f (Text
    8099 uid 3221,0
    8100 va (VaSet
    8101 isHidden 1
    8102 )
    8103 xt "22000,76000,24100,77000"
    8104 st "TRG"
    8105 blo "22000,76800"
    8106 tm "WireNameMgr"
    8107 )
    8108 )
    8109 on &71
    8110 )
    8111 *268 (Wire
    8112 uid 3260,0
    8113 shape (OrthoPolyLine
    8114 uid 3261,0
     8719uid 6881,0
    81158720va (VaSet
    81168721vasetType 3
    81178722lineWidth 2
    81188723)
    8119 xt "21000,70000,24000,70000"
    8120 pts [
    8121 "21000,70000"
    8122 "24000,70000"
    8123 ]
    8124 )
    8125 start &69
    8126 end &72
    8127 sat 32
    8128 eat 2
     8724xt "102000,132000,109000,132000"
     8725pts [
     8726"102000,132000"
     8727"109000,132000"
     8728]
     8729)
     8730start &197
     8731end &195
     8732sat 2
     8733eat 32
    81298734sty 1
    8130 stc 0
    81318735st 0
    81328736sf 1
    81338737si 0
    81348738tg (WTG
    8135 uid 3264,0
     8739uid 6884,0
    81368740ps "ConnStartEndStrategy"
    81378741stg "STSignalDisplayStrategy"
    81388742f (Text
    8139 uid 3265,0
     8743uid 6885,0
    81408744va (VaSet
    81418745isHidden 1
    81428746)
    8143 xt "23000,69000,25800,70000"
    8144 st "A_CLK"
    8145 blo "23000,69800"
    8146 tm "WireNameMgr"
    8147 )
    8148 )
    8149 on &76
    8150 )
    8151 *269 (Wire
    8152 uid 3270,0
     8747xt "104000,131000,108900,132000"
     8748st "D_T2 : (3:0)"
     8749blo "104000,131800"
     8750tm "WireNameMgr"
     8751)
     8752)
     8753on &196
     8754)
     8755*280 (Wire
     8756uid 7144,0
    81538757shape (OrthoPolyLine
    8154 uid 3271,0
    8155 va (VaSet
    8156 vasetType 3
    8157 )
    8158 xt "32000,70000,51250,70000"
    8159 pts [
    8160 "51250,70000"
    8161 "32000,70000"
    8162 ]
    8163 )
    8164 start &25
    8165 end &72
    8166 sat 32
    8167 eat 1
    8168 st 0
    8169 sf 1
    8170 si 0
    8171 tg (WTG
    8172 uid 3274,0
    8173 ps "ConnStartEndStrategy"
    8174 stg "STSignalDisplayStrategy"
    8175 f (Text
    8176 uid 3275,0
    8177 va (VaSet
    8178 )
    8179 xt "46000,69000,50500,70000"
    8180 st "CLK_25_PS"
    8181 blo "46000,69800"
    8182 tm "WireNameMgr"
    8183 )
    8184 )
    8185 on &77
    8186 )
    8187 *270 (Wire
    8188 uid 3318,0
    8189 shape (OrthoPolyLine
    8190 uid 3319,0
     8758uid 7145,0
    81918759va (VaSet
    81928760vasetType 3
    81938761lineWidth 2
    81948762)
    8195 xt "21000,95000,24000,95000"
    8196 pts [
    8197 "21000,95000"
    8198 "24000,95000"
    8199 ]
    8200 )
    8201 start &86
    8202 end &82
    8203 sat 32
    8204 eat 1
    8205 sty 1
    8206 stc 0
    8207 st 0
    8208 sf 1
    8209 si 0
    8210 tg (WTG
    8211 uid 3322,0
    8212 ps "ConnStartEndStrategy"
    8213 stg "STSignalDisplayStrategy"
    8214 f (Text
    8215 uid 3323,0
    8216 va (VaSet
    8217 isHidden 1
    8218 )
    8219 xt "23000,94000,25300,95000"
    8220 st "A0_D"
    8221 blo "23000,94800"
    8222 tm "WireNameMgr"
    8223 )
    8224 )
    8225 on &90
    8226 )
    8227 *271 (Wire
    8228 uid 3352,0
    8229 shape (OrthoPolyLine
    8230 uid 3353,0
    8231 va (VaSet
    8232 vasetType 3
    8233 lineWidth 2
    8234 )
    8235 xt "21000,96000,24000,96000"
    8236 pts [
    8237 "21000,96000"
    8238 "24000,96000"
    8239 ]
    8240 )
    8241 start &87
    8242 end &82
    8243 sat 32
    8244 eat 1
    8245 sty 1
    8246 stc 0
    8247 st 0
    8248 sf 1
    8249 si 0
    8250 tg (WTG
    8251 uid 3356,0
    8252 ps "ConnStartEndStrategy"
    8253 stg "STSignalDisplayStrategy"
    8254 f (Text
    8255 uid 3357,0
    8256 va (VaSet
    8257 isHidden 1
    8258 )
    8259 xt "23000,95000,25300,96000"
    8260 st "A1_D"
    8261 blo "23000,95800"
    8262 tm "WireNameMgr"
    8263 )
    8264 )
    8265 on &91
    8266 )
    8267 *272 (Wire
    8268 uid 3360,0
    8269 shape (OrthoPolyLine
    8270 uid 3361,0
    8271 va (VaSet
    8272 vasetType 3
    8273 lineWidth 2
    8274 )
    8275 xt "21000,97000,24000,97000"
    8276 pts [
    8277 "21000,97000"
    8278 "24000,97000"
    8279 ]
    8280 )
    8281 start &88
    8282 end &82
    8283 sat 32
    8284 eat 1
    8285 sty 1
    8286 stc 0
    8287 st 0
    8288 sf 1
    8289 si 0
    8290 tg (WTG
    8291 uid 3364,0
    8292 ps "ConnStartEndStrategy"
    8293 stg "STSignalDisplayStrategy"
    8294 f (Text
    8295 uid 3365,0
    8296 va (VaSet
    8297 isHidden 1
    8298 )
    8299 xt "23000,96000,25300,97000"
    8300 st "A2_D"
    8301 blo "23000,96800"
    8302 tm "WireNameMgr"
    8303 )
    8304 )
    8305 on &92
    8306 )
    8307 *273 (Wire
    8308 uid 3368,0
    8309 shape (OrthoPolyLine
    8310 uid 3369,0
    8311 va (VaSet
    8312 vasetType 3
    8313 lineWidth 2
    8314 )
    8315 xt "21000,98000,24000,98000"
    8316 pts [
    8317 "21000,98000"
    8318 "24000,98000"
    8319 ]
    8320 )
    8321 start &89
    8322 end &82
    8323 sat 32
    8324 eat 1
    8325 sty 1
    8326 stc 0
    8327 st 0
    8328 sf 1
    8329 si 0
    8330 tg (WTG
    8331 uid 3372,0
    8332 ps "ConnStartEndStrategy"
    8333 stg "STSignalDisplayStrategy"
    8334 f (Text
    8335 uid 3373,0
    8336 va (VaSet
    8337 isHidden 1
    8338 )
    8339 xt "23000,97000,25300,98000"
    8340 st "A3_D"
    8341 blo "23000,97800"
    8342 tm "WireNameMgr"
    8343 )
    8344 )
    8345 on &93
    8346 )
    8347 *274 (Wire
    8348 uid 3430,0
    8349 shape (OrthoPolyLine
    8350 uid 3431,0
    8351 va (VaSet
    8352 vasetType 3
    8353 )
    8354 xt "21000,113000,24000,113000"
    8355 pts [
    8356 "21000,113000"
    8357 "24000,113000"
    8358 ]
    8359 )
    8360 start &162
    8361 end &94
    8362 sat 32
    8363 eat 2
    8364 stc 0
    8365 st 0
    8366 sf 1
    8367 si 0
    8368 tg (WTG
    8369 uid 3434,0
    8370 ps "ConnStartEndStrategy"
    8371 stg "STSignalDisplayStrategy"
    8372 f (Text
    8373 uid 3435,0
    8374 va (VaSet
    8375 isHidden 1
    8376 )
    8377 xt "23000,112000,27400,113000"
    8378 st "D0_SRCLK"
    8379 blo "23000,112800"
    8380 tm "WireNameMgr"
    8381 )
    8382 )
    8383 on &98
    8384 )
    8385 *275 (Wire
    8386 uid 3438,0
    8387 shape (OrthoPolyLine
    8388 uid 3439,0
    8389 va (VaSet
    8390 vasetType 3
    8391 )
    8392 xt "21000,114000,24000,114000"
    8393 pts [
    8394 "21000,114000"
    8395 "24000,114000"
    8396 ]
    8397 )
    8398 start &163
    8399 end &94
    8400 sat 32
    8401 eat 2
    8402 stc 0
    8403 st 0
    8404 sf 1
    8405 si 0
    8406 tg (WTG
    8407 uid 3442,0
    8408 ps "ConnStartEndStrategy"
    8409 stg "STSignalDisplayStrategy"
    8410 f (Text
    8411 uid 3443,0
    8412 va (VaSet
    8413 isHidden 1
    8414 )
    8415 xt "23000,113000,27400,114000"
    8416 st "D1_SRCLK"
    8417 blo "23000,113800"
    8418 tm "WireNameMgr"
    8419 )
    8420 )
    8421 on &99
    8422 )
    8423 *276 (Wire
    8424 uid 3446,0
    8425 shape (OrthoPolyLine
    8426 uid 3447,0
    8427 va (VaSet
    8428 vasetType 3
    8429 )
    8430 xt "21000,115000,24000,115000"
    8431 pts [
    8432 "21000,115000"
    8433 "24000,115000"
    8434 ]
    8435 )
    8436 start &164
    8437 end &94
    8438 sat 32
    8439 eat 2
    8440 stc 0
    8441 st 0
    8442 sf 1
    8443 si 0
    8444 tg (WTG
    8445 uid 3450,0
    8446 ps "ConnStartEndStrategy"
    8447 stg "STSignalDisplayStrategy"
    8448 f (Text
    8449 uid 3451,0
    8450 va (VaSet
    8451 isHidden 1
    8452 )
    8453 xt "23000,114000,27400,115000"
    8454 st "D2_SRCLK"
    8455 blo "23000,114800"
    8456 tm "WireNameMgr"
    8457 )
    8458 )
    8459 on &100
    8460 )
    8461 *277 (Wire
    8462 uid 3454,0
    8463 shape (OrthoPolyLine
    8464 uid 3455,0
    8465 va (VaSet
    8466 vasetType 3
    8467 )
    8468 xt "21000,116000,24000,116000"
    8469 pts [
    8470 "21000,116000"
    8471 "24000,116000"
    8472 ]
    8473 )
    8474 start &165
    8475 end &94
    8476 sat 32
    8477 eat 2
    8478 stc 0
    8479 st 0
    8480 sf 1
    8481 si 0
    8482 tg (WTG
    8483 uid 3458,0
    8484 ps "ConnStartEndStrategy"
    8485 stg "STSignalDisplayStrategy"
    8486 f (Text
    8487 uid 3459,0
    8488 va (VaSet
    8489 isHidden 1
    8490 )
    8491 xt "23000,115000,27400,116000"
    8492 st "D3_SRCLK"
    8493 blo "23000,115800"
    8494 tm "WireNameMgr"
    8495 )
    8496 )
    8497 on &101
    8498 )
    8499 *278 (Wire
    8500 uid 3574,0
    8501 shape (OrthoPolyLine
    8502 uid 3575,0
    8503 va (VaSet
    8504 vasetType 3
    8505 )
    8506 xt "108000,89000,111000,89000"
    8507 pts [
    8508 "111000,89000"
    8509 "108000,89000"
    8510 ]
    8511 )
    8512 start &119
    8513 end &115
    8514 sat 32
    8515 eat 2
    8516 stc 0
    8517 st 0
    8518 sf 1
    8519 si 0
    8520 tg (WTG
    8521 uid 3578,0
    8522 ps "ConnStartEndStrategy"
    8523 stg "STSignalDisplayStrategy"
    8524 f (Text
    8525 uid 3579,0
    8526 va (VaSet
    8527 isHidden 1
    8528 )
    8529 xt "108000,88000,110800,89000"
    8530 st "T0_CS"
    8531 blo "108000,88800"
    8532 tm "WireNameMgr"
    8533 )
    8534 )
    8535 on &123
    8536 )
    8537 *279 (Wire
    8538 uid 3582,0
    8539 shape (OrthoPolyLine
    8540 uid 3583,0
    8541 va (VaSet
    8542 vasetType 3
    8543 )
    8544 xt "108000,90000,111000,90000"
    8545 pts [
    8546 "111000,90000"
    8547 "108000,90000"
    8548 ]
    8549 )
    8550 start &120
    8551 end &115
    8552 sat 32
    8553 eat 2
    8554 stc 0
    8555 st 0
    8556 sf 1
    8557 si 0
    8558 tg (WTG
    8559 uid 3586,0
    8560 ps "ConnStartEndStrategy"
    8561 stg "STSignalDisplayStrategy"
    8562 f (Text
    8563 uid 3587,0
    8564 va (VaSet
    8565 isHidden 1
    8566 )
    8567 xt "108000,89000,110800,90000"
    8568 st "T1_CS"
    8569 blo "108000,89800"
    8570 tm "WireNameMgr"
    8571 )
    8572 )
    8573 on &124
    8574 )
    8575 *280 (Wire
    8576 uid 3590,0
    8577 shape (OrthoPolyLine
    8578 uid 3591,0
    8579 va (VaSet
    8580 vasetType 3
    8581 )
    8582 xt "108000,91000,111000,91000"
    8583 pts [
    8584 "111000,91000"
    8585 "108000,91000"
    8586 ]
    8587 )
    8588 start &121
    8589 end &115
    8590 sat 32
    8591 eat 2
    8592 stc 0
    8593 st 0
    8594 sf 1
    8595 si 0
    8596 tg (WTG
    8597 uid 3594,0
    8598 ps "ConnStartEndStrategy"
    8599 stg "STSignalDisplayStrategy"
    8600 f (Text
    8601 uid 3595,0
    8602 va (VaSet
    8603 isHidden 1
    8604 )
    8605 xt "108000,90000,110800,91000"
    8606 st "T2_CS"
    8607 blo "108000,90800"
    8608 tm "WireNameMgr"
    8609 )
    8610 )
    8611 on &125
    8612 )
    8613 *281 (Wire
    8614 uid 3598,0
    8615 shape (OrthoPolyLine
    8616 uid 3599,0
    8617 va (VaSet
    8618 vasetType 3
    8619 )
    8620 xt "108000,92000,111000,92000"
    8621 pts [
    8622 "111000,92000"
    8623 "108000,92000"
    8624 ]
    8625 )
    8626 start &122
    8627 end &115
    8628 sat 32
    8629 eat 2
    8630 stc 0
    8631 st 0
    8632 sf 1
    8633 si 0
    8634 tg (WTG
    8635 uid 3602,0
    8636 ps "ConnStartEndStrategy"
    8637 stg "STSignalDisplayStrategy"
    8638 f (Text
    8639 uid 3603,0
    8640 va (VaSet
    8641 isHidden 1
    8642 )
    8643 xt "108000,91000,110800,92000"
    8644 st "T3_CS"
    8645 blo "108000,91800"
    8646 tm "WireNameMgr"
    8647 )
    8648 )
    8649 on &126
    8650 )
    8651 *282 (Wire
    8652 uid 3682,0
    8653 shape (OrthoPolyLine
    8654 uid 3683,0
    8655 va (VaSet
    8656 vasetType 3
    8657 )
    8658 xt "80750,100000,111000,100000"
    8659 pts [
    8660 "80750,100000"
    8661 "111000,100000"
    8662 ]
    8663 )
    8664 start &42
    8665 end &138
    8666 sat 32
    8667 eat 32
    8668 stc 0
    8669 st 0
    8670 sf 1
    8671 si 0
    8672 tg (WTG
    8673 uid 3686,0
    8674 ps "ConnStartEndStrategy"
    8675 stg "STSignalDisplayStrategy"
    8676 f (Text
    8677 uid 3687,0
    8678 va (VaSet
    8679 isHidden 1
    8680 )
    8681 xt "82000,99000,84400,100000"
    8682 st "MOSI"
    8683 blo "82000,99800"
    8684 tm "WireNameMgr"
    8685 )
    8686 )
    8687 on &137
    8688 )
    8689 *283 (Wire
    8690 uid 3778,0
    8691 shape (OrthoPolyLine
    8692 uid 3779,0
    8693 va (VaSet
    8694 vasetType 3
    8695 )
    8696 xt "108000,103000,111000,103000"
    8697 pts [
    8698 "111000,103000"
    8699 "108000,103000"
    8700 ]
    8701 )
    8702 start &144
    8703 end &140
    8704 sat 32
    8705 eat 2
    8706 stc 0
    8707 st 0
    8708 sf 1
    8709 si 0
    8710 tg (WTG
    8711 uid 3782,0
    8712 ps "ConnStartEndStrategy"
    8713 stg "STSignalDisplayStrategy"
    8714 f (Text
    8715 uid 3783,0
    8716 va (VaSet
    8717 isHidden 1
    8718 )
    8719 xt "108000,102000,111000,103000"
    8720 st "TRG_V"
    8721 blo "108000,102800"
    8722 tm "WireNameMgr"
    8723 )
    8724 )
    8725 on &153
    8726 )
    8727 *284 (Wire
    8728 uid 3786,0
    8729 shape (OrthoPolyLine
    8730 uid 3787,0
    8731 va (VaSet
    8732 vasetType 3
    8733 )
    8734 xt "108000,104000,111000,104000"
    8735 pts [
    8736 "111000,104000"
    8737 "108000,104000"
    8738 ]
    8739 )
    8740 start &145
    8741 end &140
    8742 sat 32
    8743 eat 2
    8744 stc 0
    8745 st 0
    8746 sf 1
    8747 si 0
    8748 tg (WTG
    8749 uid 3790,0
    8750 ps "ConnStartEndStrategy"
    8751 stg "STSignalDisplayStrategy"
    8752 f (Text
    8753 uid 3791,0
    8754 va (VaSet
    8755 isHidden 1
    8756 )
    8757 xt "108000,103000,113600,104000"
    8758 st "RS485_C_RE"
    8759 blo "108000,103800"
    8760 tm "WireNameMgr"
    8761 )
    8762 )
    8763 on &154
    8764 )
    8765 *285 (Wire
    8766 uid 3794,0
    8767 shape (OrthoPolyLine
    8768 uid 3795,0
    8769 va (VaSet
    8770 vasetType 3
    8771 )
    8772 xt "108000,105000,111000,105000"
    8773 pts [
    8774 "111000,105000"
    8775 "108000,105000"
    8776 ]
    8777 )
    8778 start &146
    8779 end &140
    8780 sat 32
    8781 eat 2
    8782 stc 0
    8783 st 0
    8784 sf 1
    8785 si 0
    8786 tg (WTG
    8787 uid 3798,0
    8788 ps "ConnStartEndStrategy"
    8789 stg "STSignalDisplayStrategy"
    8790 f (Text
    8791 uid 3799,0
    8792 va (VaSet
    8793 isHidden 1
    8794 )
    8795 xt "108000,104000,113600,105000"
    8796 st "RS485_C_DE"
    8797 blo "108000,104800"
    8798 tm "WireNameMgr"
    8799 )
    8800 )
    8801 on &155
    8802 )
    8803 *286 (Wire
    8804 uid 3802,0
    8805 shape (OrthoPolyLine
    8806 uid 3803,0
    8807 va (VaSet
    8808 vasetType 3
    8809 )
    8810 xt "108000,106000,111000,106000"
    8811 pts [
    8812 "111000,106000"
    8813 "108000,106000"
    8814 ]
    8815 )
    8816 start &147
    8817 end &140
    8818 sat 32
    8819 eat 2
    8820 stc 0
    8821 st 0
    8822 sf 1
    8823 si 0
    8824 tg (WTG
    8825 uid 3806,0
    8826 ps "ConnStartEndStrategy"
    8827 stg "STSignalDisplayStrategy"
    8828 f (Text
    8829 uid 3807,0
    8830 va (VaSet
    8831 isHidden 1
    8832 )
    8833 xt "108000,105000,113500,106000"
    8834 st "RS485_E_RE"
    8835 blo "108000,105800"
    8836 tm "WireNameMgr"
    8837 )
    8838 )
    8839 on &156
    8840 )
    8841 *287 (Wire
    8842 uid 3810,0
    8843 shape (OrthoPolyLine
    8844 uid 3811,0
    8845 va (VaSet
    8846 vasetType 3
    8847 )
    8848 xt "108000,107000,111000,107000"
    8849 pts [
    8850 "111000,107000"
    8851 "108000,107000"
    8852 ]
    8853 )
    8854 start &148
    8855 end &140
    8856 sat 32
    8857 eat 2
    8858 stc 0
    8859 st 0
    8860 sf 1
    8861 si 0
    8862 tg (WTG
    8863 uid 3814,0
    8864 ps "ConnStartEndStrategy"
    8865 stg "STSignalDisplayStrategy"
    8866 f (Text
    8867 uid 3815,0
    8868 va (VaSet
    8869 isHidden 1
    8870 )
    8871 xt "108000,106000,113500,107000"
    8872 st "RS485_E_DE"
    8873 blo "108000,106800"
    8874 tm "WireNameMgr"
    8875 )
    8876 )
    8877 on &157
    8878 )
    8879 *288 (Wire
    8880 uid 3826,0
    8881 shape (OrthoPolyLine
    8882 uid 3827,0
    8883 va (VaSet
    8884 vasetType 3
    8885 )
    8886 xt "108000,109000,111000,109000"
    8887 pts [
    8888 "111000,109000"
    8889 "108000,109000"
    8890 ]
    8891 )
    8892 start &150
    8893 end &140
    8894 sat 32
    8895 eat 2
    8896 stc 0
    8897 st 0
    8898 sf 1
    8899 si 0
    8900 tg (WTG
    8901 uid 3830,0
    8902 ps "ConnStartEndStrategy"
    8903 stg "STSignalDisplayStrategy"
    8904 f (Text
    8905 uid 3831,0
    8906 va (VaSet
    8907 isHidden 1
    8908 )
    8909 xt "108000,108000,110300,109000"
    8910 st "SRIN"
    8911 blo "108000,108800"
    8912 tm "WireNameMgr"
    8913 )
    8914 )
    8915 on &159
    8916 )
    8917 *289 (Wire
    8918 uid 3834,0
    8919 shape (OrthoPolyLine
    8920 uid 3835,0
    8921 va (VaSet
    8922 vasetType 3
    8923 )
    8924 xt "108000,110000,111000,110000"
    8925 pts [
    8926 "111000,110000"
    8927 "108000,110000"
    8928 ]
    8929 )
    8930 start &151
    8931 end &140
    8932 sat 32
    8933 eat 2
    8934 stc 0
    8935 st 0
    8936 sf 1
    8937 si 0
    8938 tg (WTG
    8939 uid 3838,0
    8940 ps "ConnStartEndStrategy"
    8941 stg "STSignalDisplayStrategy"
    8942 f (Text
    8943 uid 3839,0
    8944 va (VaSet
    8945 isHidden 1
    8946 )
    8947 xt "108000,109000,110900,110000"
    8948 st "EE_CS"
    8949 blo "108000,109800"
    8950 tm "WireNameMgr"
    8951 )
    8952 )
    8953 on &160
    8954 )
    8955 *290 (Wire
    8956 uid 3842,0
    8957 shape (OrthoPolyLine
    8958 uid 3843,0
    8959 va (VaSet
    8960 vasetType 3
    8961 lineWidth 2
    8962 )
    8963 xt "108000,111000,111000,111000"
    8964 pts [
    8965 "111000,111000"
    8966 "108000,111000"
    8967 ]
    8968 )
    8969 start &152
    8970 end &140
    8971 sat 32
    8972 eat 2
    8973 sty 1
    8974 stc 0
    8975 st 0
    8976 sf 1
    8977 si 0
    8978 tg (WTG
    8979 uid 3846,0
    8980 ps "ConnStartEndStrategy"
    8981 stg "STSignalDisplayStrategy"
    8982 f (Text
    8983 uid 3847,0
    8984 va (VaSet
    8985 isHidden 1
    8986 )
    8987 xt "108000,110000,109900,111000"
    8988 st "LED"
    8989 blo "108000,110800"
    8990 tm "WireNameMgr"
    8991 )
    8992 )
    8993 on &161
    8994 )
    8995 *291 (Wire
    8996 uid 4942,0
    8997 shape (OrthoPolyLine
    8998 uid 4943,0
    8999 va (VaSet
    9000 vasetType 3
    9001 lineWidth 2
    9002 )
    9003 xt "80750,120000,111000,120000"
    9004 pts [
    9005 "80750,120000"
    9006 "111000,120000"
    9007 ]
    9008 )
    9009 start &14
    9010 end &166
    9011 sat 32
     8763xt "39000,132000,44000,132000"
     8764pts [
     8765"39000,132000"
     8766"44000,132000"
     8767]
     8768)
     8769start &201
     8770end &205
     8771sat 2
    90128772eat 32
    90138773sty 1
    9014 stc 0
    90158774st 0
    90168775sf 1
    90178776si 0
    90188777tg (WTG
    9019 uid 4948,0
     8778uid 7148,0
    90208779ps "ConnStartEndStrategy"
    90218780stg "STSignalDisplayStrategy"
    90228781f (Text
    9023 uid 4949,0
     8782uid 7149,0
    90248783va (VaSet
    90258784isHidden 1
    90268785)
    9027 xt "82750,117000,84650,118000"
    9028 st "D_T"
    9029 blo "82750,117800"
    9030 tm "WireNameMgr"
    9031 )
    9032 )
    9033 on &167
    9034 )
    9035 *292 (Wire
    9036 uid 6130,0
     8786xt "41000,131000,45800,132000"
     8787st "A1_T : (7:0)"
     8788blo "41000,131800"
     8789tm "WireNameMgr"
     8790)
     8791)
     8792on &206
     8793)
     8794*281 (Wire
     8795uid 7477,0
    90378796shape (OrthoPolyLine
    9038 uid 6131,0
     8797uid 7478,0
    90398798va (VaSet
    90408799vasetType 3
    90418800)
    9042 xt "19000,78000,51250,78000"
    9043 pts [
    9044 "19000,78000"
    9045 "51250,78000"
    9046 ]
    9047 )
    9048 start &193
    9049 end &15
    9050 sat 32
    9051 eat 32
    9052 st 0
    9053 sf 1
    9054 si 0
    9055 tg (WTG
    9056 uid 6136,0
    9057 ps "ConnStartEndStrategy"
    9058 stg "STSignalDisplayStrategy"
    9059 f (Text
    9060 uid 6137,0
    9061 va (VaSet
    9062 )
    9063 xt "21000,77000,24700,78000"
    9064 st "TRG_OR"
    9065 blo "21000,77800"
    9066 tm "WireNameMgr"
    9067 )
    9068 )
    9069 on &170
    9070 )
    9071 *293 (Wire
    9072 uid 6288,0
    9073 shape (OrthoPolyLine
    9074 uid 6289,0
    9075 va (VaSet
    9076 vasetType 3
    9077 )
    9078 xt "1750,79000,13000,89000"
    9079 pts [
    9080 "1750,89000"
    9081 "9000,89000"
    9082 "9000,86000"
    9083 "9000,79000"
    9084 "13000,79000"
    9085 ]
    9086 )
    9087 start &174
    9088 end &191
    9089 sat 32
    9090 eat 32
    9091 st 0
    9092 sf 1
    9093 si 0
    9094 tg (WTG
    9095 uid 6294,0
    9096 ps "ConnStartEndStrategy"
    9097 stg "STSignalDisplayStrategy"
    9098 f (Text
    9099 uid 6295,0
    9100 va (VaSet
    9101 )
    9102 xt "4000,88000,8600,89000"
    9103 st "trigger_out"
    9104 blo "4000,88800"
    9105 tm "WireNameMgr"
    9106 )
    9107 )
    9108 on &178
    9109 )
    9110 *294 (Wire
    9111 uid 6306,0
    9112 shape (OrthoPolyLine
    9113 uid 6307,0
    9114 va (VaSet
    9115 vasetType 3
    9116 )
    9117 xt "-28000,89000,-22000,89000"
    9118 pts [
    9119 "-28000,89000"
    9120 "-22000,89000"
    9121 ]
    9122 )
    9123 start &168
    9124 end &181
     8801xt "80750,87000,91000,87000"
     8802pts [
     8803"80750,87000"
     8804"91000,87000"
     8805]
     8806)
     8807start &38
     8808end &209
    91258809es 0
    91268810sat 32
     
    91308814si 0
    91318815tg (WTG
    9132 uid 6312,0
     8816uid 7483,0
    91338817ps "ConnStartEndStrategy"
    91348818stg "STSignalDisplayStrategy"
    91358819f (Text
    9136 uid 6313,0
    9137 va (VaSet
    9138 )
    9139 xt "-26000,88000,-21500,89000"
    9140 st "TEST_TRG"
    9141 blo "-26000,88800"
    9142 tm "WireNameMgr"
    9143 )
    9144 )
    9145 on &169
    9146 )
    9147 *295 (Wire
    9148 uid 6328,0
     8820uid 7484,0
     8821va (VaSet
     8822)
     8823xt "83000,86000,85700,87000"
     8824st "dummy"
     8825blo "83000,86800"
     8826tm "WireNameMgr"
     8827)
     8828)
     8829on &207
     8830)
     8831*282 (Wire
     8832uid 8853,0
    91498833shape (OrthoPolyLine
    9150 uid 6329,0
    9151 va (VaSet
    9152 vasetType 3
    9153 )
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    10681 *345 (TypeColHdr
     10181*327 (TypeColHdr
    1068210182tm "BlockDiagramTypeColHdrMgr"
    1068310183)
    10684 *346 (BoundsColHdr
     10184*328 (BoundsColHdr
    1068510185tm "BlockDiagramBoundsColHdrMgr"
    1068610186)
    10687 *347 (InitColHdr
     10187*329 (InitColHdr
    1068810188tm "BlockDiagramInitColHdrMgr"
    1068910189)
    10690 *348 (EolColHdr
     10190*330 (EolColHdr
    1069110191tm "BlockDiagramEolColHdrMgr"
    1069210192)
    10693 *349 (LeafLogPort
     10193*331 (LeafLogPort
    1069410194port (LogicalPort
    1069510195m 4
     
    1070010200preAdd 0
    1070110201posAdd 0
    10702 o 55
     10202o 56
    1070310203suid 5,0
    1070410204)
     
    1070610206uid 327,0
    1070710207)
    10708 *350 (LeafLogPort
     10208*332 (LeafLogPort
    1070910209port (LogicalPort
    1071010210m 4
     
    1071310213t "std_logic_vector"
    1071410214b "(1 downto 0)"
    10715 o 56
     10215o 57
    1071610216suid 6,0
    1071710217)
     
    1071910219uid 329,0
    1072010220)
    10721 *351 (LeafLogPort
     10221*333 (LeafLogPort
    1072210222port (LogicalPort
    1072310223m 4
     
    1072510225n "adc_data_array"
    1072610226t "adc_data_array_type"
    10727 o 54
     10227o 55
    1072810228suid 29,0
    1072910229)
     
    1073110231uid 1491,0
    1073210232)
    10733 *352 (LeafLogPort
     10233*334 (LeafLogPort
     10234port (LogicalPort
     10235m 1
     10236decl (Decl
     10237n "RSRLOAD"
     10238t "std_logic"
     10239o 36
     10240suid 57,0
     10241i "'0'"
     10242)
     10243)
     10244uid 2435,0
     10245)
     10246*335 (LeafLogPort
    1073410247port (LogicalPort
    1073510248m 4
    1073610249decl (Decl
    10737 n "CLK_50"
    10738 t "std_logic"
    10739 preAdd 0
    10740 posAdd 0
    10741 o 51
    10742 suid 54,0
    10743 )
    10744 )
    10745 uid 2275,0
    10746 )
    10747 *353 (LeafLogPort
    10748 port (LogicalPort
    10749 m 1
    10750 decl (Decl
    10751 n "RSRLOAD"
    10752 t "std_logic"
    10753 o 35
    10754 suid 57,0
    10755 i "'0'"
    10756 )
    10757 )
    10758 uid 2435,0
    10759 )
    10760 *354 (LeafLogPort
    10761 port (LogicalPort
    10762 m 4
    10763 decl (Decl
    1076410250n "SRCLK"
    1076510251t "std_logic"
    10766 o 52
     10252o 53
    1076710253suid 58,0
    1076810254i "'0'"
     
    1077110257uid 2437,0
    1077210258)
    10773 *355 (LeafLogPort
     10259*336 (LeafLogPort
    1077410260port (LogicalPort
    1077510261m 4
     
    1077810264t "std_logic_vector"
    1077910265b "(3 DOWNTO 0)"
    10780 o 59
     10266o 60
    1078110267suid 65,0
    1078210268)
     
    1078410270uid 3037,0
    1078510271)
    10786 *356 (LeafLogPort
     10272*337 (LeafLogPort
    1078710273port (LogicalPort
    1078810274m 1
     
    1079010276n "DAC_CS"
    1079110277t "std_logic"
    10792 o 21
     10278o 22
    1079310279suid 66,0
    1079410280)
     
    1079610282uid 3039,0
    1079710283)
    10798 *357 (LeafLogPort
     10284*338 (LeafLogPort
    1079910285port (LogicalPort
    1080010286decl (Decl
     
    1080910295uid 3276,0
    1081010296)
    10811 *358 (LeafLogPort
     10297*339 (LeafLogPort
    1081210298port (LogicalPort
    1081310299decl (Decl
     
    1082010306uid 3278,0
    1082110307)
    10822 *359 (LeafLogPort
     10308*340 (LeafLogPort
    1082310309port (LogicalPort
    1082410310m 1
     
    1082710313t "std_logic_vector"
    1082810314b "(3 downto 0)"
    10829 o 16
     10315o 17
    1083010316suid 71,0
    1083110317)
     
    1083310319uid 3280,0
    1083410320)
    10835 *360 (LeafLogPort
     10321*341 (LeafLogPort
    1083610322port (LogicalPort
    1083710323m 4
     
    1083910325n "CLK_25_PS"
    1084010326t "std_logic"
    10841 o 50
     10327o 51
    1084210328suid 72,0
    1084310329)
     
    1084510331uid 3282,0
    1084610332)
    10847 *361 (LeafLogPort
     10333*342 (LeafLogPort
    1084810334port (LogicalPort
    1084910335m 1
     
    1085310339preAdd 0
    1085410340posAdd 0
    10855 o 30
     10341o 31
    1085610342suid 73,0
    1085710343)
     
    1085910345uid 3382,0
    1086010346)
    10861 *362 (LeafLogPort
     10347*343 (LeafLogPort
    1086210348port (LogicalPort
    1086310349decl (Decl
     
    1087110357uid 3384,0
    1087210358)
    10873 *363 (LeafLogPort
     10359*344 (LeafLogPort
    1087410360port (LogicalPort
    1087510361decl (Decl
     
    1088310369uid 3386,0
    1088410370)
    10885 *364 (LeafLogPort
     10371*345 (LeafLogPort
    1088610372port (LogicalPort
    1088710373decl (Decl
     
    1089510381uid 3388,0
    1089610382)
    10897 *365 (LeafLogPort
     10383*346 (LeafLogPort
    1089810384port (LogicalPort
    1089910385decl (Decl
     
    1090710393uid 3390,0
    1090810394)
    10909 *366 (LeafLogPort
     10395*347 (LeafLogPort
    1091010396port (LogicalPort
    1091110397decl (Decl
     
    1091910405uid 3392,0
    1092010406)
    10921 *367 (LeafLogPort
     10407*348 (LeafLogPort
    1092210408port (LogicalPort
    1092310409m 1
     
    1092510411n "D0_SRCLK"
    1092610412t "STD_LOGIC"
    10927 o 17
     10413o 18
    1092810414suid 87,0
    1092910415)
     
    1093110417uid 3468,0
    1093210418)
    10933 *368 (LeafLogPort
     10419*349 (LeafLogPort
    1093410420port (LogicalPort
    1093510421m 1
     
    1093710423n "D1_SRCLK"
    1093810424t "STD_LOGIC"
    10939 o 18
     10425o 19
    1094010426suid 88,0
    1094110427)
     
    1094310429uid 3470,0
    1094410430)
    10945 *369 (LeafLogPort
     10431*350 (LeafLogPort
    1094610432port (LogicalPort
    1094710433m 1
     
    1094910435n "D2_SRCLK"
    1095010436t "STD_LOGIC"
    10951 o 19
     10437o 20
    1095210438suid 89,0
    1095310439)
     
    1095510441uid 3472,0
    1095610442)
    10957 *370 (LeafLogPort
     10443*351 (LeafLogPort
    1095810444port (LogicalPort
    1095910445m 1
     
    1096110447n "D3_SRCLK"
    1096210448t "STD_LOGIC"
    10963 o 20
     10449o 21
    1096410450suid 90,0
    1096510451)
     
    1096710453uid 3474,0
    1096810454)
    10969 *371 (LeafLogPort
     10455*352 (LeafLogPort
    1097010456port (LogicalPort
    1097110457decl (Decl
     
    1097810464uid 3524,0
    1097910465)
    10980 *372 (LeafLogPort
     10466*353 (LeafLogPort
    1098110467port (LogicalPort
    1098210468decl (Decl
     
    1098910475uid 3526,0
    1099010476)
    10991 *373 (LeafLogPort
     10477*354 (LeafLogPort
    1099210478port (LogicalPort
    1099310479decl (Decl
     
    1100010486uid 3528,0
    1100110487)
    11002 *374 (LeafLogPort
     10488*355 (LeafLogPort
    1100310489port (LogicalPort
    1100410490decl (Decl
     
    1101110497uid 3530,0
    1101210498)
    11013 *375 (LeafLogPort
     10499*356 (LeafLogPort
    1101410500port (LogicalPort
    1101510501m 1
     
    1101810504t "std_logic_vector"
    1101910505b "(3 DOWNTO 0)"
    11020 o 24
     10506o 25
    1102110507suid 95,0
    1102210508i "(others => '0')"
     
    1102510511uid 3532,0
    1102610512)
    11027 *376 (LeafLogPort
     10513*357 (LeafLogPort
    1102810514port (LogicalPort
    1102910515m 1
     
    1103110517n "DWRITE"
    1103210518t "std_logic"
    11033 o 23
     10519o 24
    1103410520suid 96,0
    1103510521i "'0'"
     
    1103810524uid 3534,0
    1103910525)
    11040 *377 (LeafLogPort
     10526*358 (LeafLogPort
    1104110527port (LogicalPort
    1104210528m 1
     
    1104410530n "T0_CS"
    1104510531t "std_logic"
    11046 o 38
     10532o 39
    1104710533suid 101,0
    1104810534)
     
    1105010536uid 3646,0
    1105110537)
    11052 *378 (LeafLogPort
     10538*359 (LeafLogPort
    1105310539port (LogicalPort
    1105410540m 1
     
    1105610542n "T1_CS"
    1105710543t "std_logic"
    11058 o 39
     10544o 40
    1105910545suid 102,0
    1106010546)
     
    1106210548uid 3648,0
    1106310549)
    11064 *379 (LeafLogPort
     10550*360 (LeafLogPort
    1106510551port (LogicalPort
    1106610552m 1
     
    1106810554n "T2_CS"
    1106910555t "std_logic"
    11070 o 40
     10556o 41
    1107110557suid 103,0
    1107210558)
     
    1107410560uid 3650,0
    1107510561)
    11076 *380 (LeafLogPort
     10562*361 (LeafLogPort
    1107710563port (LogicalPort
    1107810564m 1
     
    1108010566n "T3_CS"
    1108110567t "std_logic"
    11082 o 41
     10568o 42
    1108310569suid 104,0
    1108410570)
     
    1108610572uid 3652,0
    1108710573)
    11088 *381 (LeafLogPort
     10574*362 (LeafLogPort
    1108910575port (LogicalPort
    1109010576m 1
     
    1109210578n "S_CLK"
    1109310579t "std_logic"
    11094 o 37
     10580o 38
    1109510581suid 105,0
    1109610582)
     
    1109810584uid 3654,0
    1109910585)
    11100 *382 (LeafLogPort
     10586*363 (LeafLogPort
    1110110587port (LogicalPort
    1110210588m 1
     
    1110510591t "std_logic_vector"
    1110610592b "(9 DOWNTO 0)"
    11107 o 43
     10593o 44
    1110810594suid 106,0
    1110910595)
     
    1111110597uid 3656,0
    1111210598)
    11113 *383 (LeafLogPort
     10599*364 (LeafLogPort
    1111410600port (LogicalPort
    1111510601m 2
     
    1111810604t "std_logic_vector"
    1111910605b "(15 DOWNTO 0)"
    11120 o 49
     10606o 50
    1112110607suid 107,0
    1112210608)
     
    1112410610uid 3658,0
    1112510611)
    11126 *384 (LeafLogPort
     10612*365 (LeafLogPort
    1112710613port (LogicalPort
    1112810614m 1
     
    1113010616n "W_RES"
    1113110617t "std_logic"
    11132 o 46
     10618o 47
    1113310619suid 108,0
    1113410620i "'1'"
     
    1113710623uid 3660,0
    1113810624)
    11139 *385 (LeafLogPort
     10625*366 (LeafLogPort
    1114010626port (LogicalPort
    1114110627m 1
     
    1114310629n "W_RD"
    1114410630t "std_logic"
    11145 o 45
     10631o 46
    1114610632suid 109,0
    1114710633i "'1'"
     
    1115010636uid 3662,0
    1115110637)
    11152 *386 (LeafLogPort
     10638*367 (LeafLogPort
    1115310639port (LogicalPort
    1115410640m 1
     
    1115610642n "W_WR"
    1115710643t "std_logic"
    11158 o 47
     10644o 48
    1115910645suid 110,0
    1116010646i "'1'"
     
    1116310649uid 3664,0
    1116410650)
    11165 *387 (LeafLogPort
     10651*368 (LeafLogPort
    1116610652port (LogicalPort
    1116710653decl (Decl
     
    1117410660uid 3666,0
    1117510661)
    11176 *388 (LeafLogPort
     10662*369 (LeafLogPort
    1117710663port (LogicalPort
    1117810664m 1
     
    1118010666n "W_CS"
    1118110667t "std_logic"
    11182 o 44
     10668o 45
    1118310669suid 112,0
    1118410670i "'1'"
     
    1118710673uid 3668,0
    1118810674)
    11189 *389 (LeafLogPort
     10675*370 (LeafLogPort
    1119010676port (LogicalPort
    1119110677m 1
     
    1119310679n "MOSI"
    1119410680t "std_logic"
    11195 o 29
     10681o 30
    1119610682suid 113,0
    1119710683i "'0'"
     
    1120010686uid 3696,0
    1120110687)
    11202 *390 (LeafLogPort
     10688*371 (LeafLogPort
    1120310689port (LogicalPort
    1120410690m 2
     
    1120810694preAdd 0
    1120910695posAdd 0
    11210 o 48
     10696o 49
    1121110697suid 114,0
    1121210698)
     
    1121410700uid 3698,0
    1121510701)
    11216 *391 (LeafLogPort
     10702*372 (LeafLogPort
    1121710703port (LogicalPort
    1121810704m 1
     
    1122010706n "TRG_V"
    1122110707t "std_logic"
    11222 o 42
     10708o 43
    1122310709suid 126,0
    1122410710)
     
    1122610712uid 3886,0
    1122710713)
    11228 *392 (LeafLogPort
     10714*373 (LeafLogPort
    1122910715port (LogicalPort
    1123010716m 1
     
    1123210718n "RS485_C_RE"
    1123310719t "std_logic"
    11234 o 32
     10720o 33
    1123510721suid 127,0
    1123610722)
     
    1123810724uid 3888,0
    1123910725)
    11240 *393 (LeafLogPort
     10726*374 (LeafLogPort
    1124110727port (LogicalPort
    1124210728m 1
     
    1124410730n "RS485_C_DE"
    1124510731t "std_logic"
    11246 o 31
     10732o 32
    1124710733suid 128,0
    1124810734)
     
    1125010736uid 3890,0
    1125110737)
    11252 *394 (LeafLogPort
     10738*375 (LeafLogPort
    1125310739port (LogicalPort
    1125410740m 1
     
    1125610742n "RS485_E_RE"
    1125710743t "std_logic"
    11258 o 34
     10744o 35
    1125910745suid 129,0
    1126010746)
     
    1126210748uid 3892,0
    1126310749)
    11264 *395 (LeafLogPort
     10750*376 (LeafLogPort
    1126510751port (LogicalPort
    1126610752m 1
     
    1126810754n "RS485_E_DE"
    1126910755t "std_logic"
    11270 o 33
     10756o 34
    1127110757suid 130,0
    1127210758)
     
    1127410760uid 3894,0
    1127510761)
    11276 *396 (LeafLogPort
     10762*377 (LeafLogPort
    1127710763port (LogicalPort
    1127810764m 1
     
    1128010766n "DENABLE"
    1128110767t "std_logic"
    11282 o 22
     10768o 23
    1128310769suid 131,0
    1128410770i "'0'"
     
    1128710773uid 3896,0
    1128810774)
    11289 *397 (LeafLogPort
     10775*378 (LeafLogPort
    1129010776port (LogicalPort
    1129110777m 1
     
    1129310779n "SRIN"
    1129410780t "std_logic"
    11295 o 36
     10781o 37
    1129610782suid 132,0
    1129710783)
     
    1129910785uid 3898,0
    1130010786)
    11301 *398 (LeafLogPort
     10787*379 (LeafLogPort
    1130210788port (LogicalPort
    1130310789m 1
     
    1130510791n "EE_CS"
    1130610792t "std_logic"
    11307 o 27
     10793o 28
    1130810794suid 133,0
    1130910795)
     
    1131110797uid 3900,0
    1131210798)
    11313 *399 (LeafLogPort
     10799*380 (LeafLogPort
    1131410800port (LogicalPort
    1131510801m 1
     
    1131810804t "std_logic_vector"
    1131910805b "( 2 DOWNTO 0 )"
    11320 o 28
     10806o 29
    1132110807suid 134,0
    1132210808i "(others => '1')"
     
    1132510811uid 3902,0
    1132610812)
    11327 *400 (LeafLogPort
     10813*381 (LeafLogPort
    1132810814port (LogicalPort
    1132910815m 1
     
    1133210818t "std_logic_vector"
    1133310819b "(7 DOWNTO 0)"
    11334 o 25
     10820o 26
    1133510821suid 141,0
    1133610822i "(OTHERS => '0')"
     
    1133910825uid 5322,0
    1134010826)
    11341 *401 (LeafLogPort
     10827*382 (LeafLogPort
    1134210828port (LogicalPort
    1134310829decl (Decl
     
    1135110837scheme 0
    1135210838)
    11353 *402 (LeafLogPort
     10839*383 (LeafLogPort
    1135410840port (LogicalPort
    1135510841m 4
     
    1135710843n "TRG_OR"
    1135810844t "std_logic"
    11359 o 53
     10845o 54
    1136010846suid 146,0
    1136110847)
     
    1136410850scheme 0
    1136510851)
    11366 *403 (LeafLogPort
    11367 port (LogicalPort
    11368 m 4
    11369 decl (Decl
    11370 n "trigger_out"
    11371 t "STD_LOGIC"
    11372 preAdd 0
    11373 posAdd 0
    11374 o 60
    11375 suid 147,0
    11376 i "'0'"
    11377 )
    11378 )
    11379 uid 6286,0
    11380 )
    11381 *404 (LeafLogPort
    11382 port (LogicalPort
    11383 m 4
    11384 decl (Decl
    11385 n "not_TEST_TRG"
    11386 t "STD_LOGIC"
    11387 o 58
    11388 suid 148,0
    11389 )
    11390 )
    11391 uid 6314,0
    11392 scheme 0
    11393 )
    11394 *405 (LeafLogPort
     10852*384 (LeafLogPort
    1139510853port (LogicalPort
    1139610854decl (Decl
     
    1140510863scheme 0
    1140610864)
    11407 *406 (LeafLogPort
     10865*385 (LeafLogPort
    1140810866port (LogicalPort
    1140910867m 1
     
    1141210870t "std_logic_vector"
    1141310871b "(3 DOWNTO 0)"
    11414 o 26
     10872o 27
    1141510873suid 154,0
    1141610874i "(others => '0')"
     
    1142010878scheme 0
    1142110879)
    11422 *407 (LeafLogPort
     10880*386 (LeafLogPort
    1142310881port (LogicalPort
    1142410882m 1
     
    1142610884n "A1_T"
    1142710885t "std_logic_vector"
    11428 b "(3 DOWNTO 0)"
    11429 o 15
     10886b "(7 DOWNTO 0)"
     10887o 16
    1143010888suid 155,0
     10889i "(OTHERS => '0')"
    1143110890)
    1143210891)
     
    1143410893scheme 0
    1143510894)
    11436 *408 (LeafLogPort
     10895*387 (LeafLogPort
    1143710896port (LogicalPort
    1143810897m 4
     
    1144010899n "dummy"
    1144110900t "std_logic"
    11442 o 60
     10901o 59
    1144310902suid 157,0
    1144410903)
     
    1144610905uid 7473,0
    1144710906scheme 0
     10907)
     10908*388 (LeafLogPort
     10909port (LogicalPort
     10910m 4
     10911decl (Decl
     10912n "drs_channel_id"
     10913t "std_logic_vector"
     10914b "(3 downto 0)"
     10915o 58
     10916suid 159,0
     10917i "(others => '0')"
     10918)
     10919)
     10920uid 8875,0
     10921)
     10922*389 (LeafLogPort
     10923port (LogicalPort
     10924m 1
     10925decl (Decl
     10926n "A0_T"
     10927t "std_logic_vector"
     10928b "(7 DOWNTO 0)"
     10929o 15
     10930suid 162,0
     10931i "(OTHERS => '0')"
     10932)
     10933)
     10934uid 9191,0
     10935scheme 0
     10936)
     10937*390 (LeafLogPort
     10938port (LogicalPort
     10939m 4
     10940decl (Decl
     10941n "CLK_50"
     10942t "std_logic"
     10943o 52
     10944suid 163,0
     10945)
     10946)
     10947uid 9516,0
    1144810948)
    1144910949]
     
    1145410954uid 67,0
    1145510955optionalChildren [
    11456 *409 (Sheet
     10956*391 (Sheet
    1145710957sheetRow (SheetRow
    1145810958headerVa (MVa
     
    1147110971font "Tahoma,10,0"
    1147210972)
    11473 emptyMRCItem *410 (MRCItem
    11474 litem &336
     10973emptyMRCItem *392 (MRCItem
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    1193111431genericsCommonDM (CommonDM
    1193211432ldm (LogicalDM
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     11437*465 (RefLabelRowHdr
     11438)
     11439*466 (TitleRowHdr
     11440)
     11441*467 (FilterRowHdr
     11442)
     11443*468 (RefLabelColHdr
    1194411444tm "RefLabelColHdrMgr"
    1194511445)
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     11446*469 (RowExpandColHdr
    1194711447tm "RowExpandColHdrMgr"
    1194811448)
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     11449*470 (GroupColHdr
    1195011450tm "GroupColHdrMgr"
    1195111451)
    11952 *489 (NameColHdr
     11452*471 (NameColHdr
    1195311453tm "GenericNameColHdrMgr"
    1195411454)
    11955 *490 (TypeColHdr
     11455*472 (TypeColHdr
    1195611456tm "GenericTypeColHdrMgr"
    1195711457)
    11958 *491 (InitColHdr
     11458*473 (InitColHdr
    1195911459tm "GenericValueColHdrMgr"
    1196011460)
    11961 *492 (PragmaColHdr
     11461*474 (PragmaColHdr
    1196211462tm "GenericPragmaColHdrMgr"
    1196311463)
    11964 *493 (EolColHdr
     11464*475 (EolColHdr
    1196511465tm "GenericEolColHdrMgr"
    1196611466)
     
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    1197311473optionalChildren [
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    1201311513hidden 1
     
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  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb

    r246 r252  
    2121commonDM (CommonDM
    2222ldm (LogicalDM
    23 suid 66,0
     23suid 67,0
    2424usingSuid 1
    2525emptyRow *1 (LEmptyRow
     
    659659n "A1_T"
    660660t "std_logic_vector"
    661 b "(3 DOWNTO 0)"
     661b "(7 DOWNTO 0)"
    662662o 15
    663663suid 66,0
     664i "(OTHERS => '0')"
    664665)
    665666)
     
    12391240(vvPair
    12401241variable "HDLDir"
    1241 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hdl"
     1242value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
    12421243)
    12431244(vvPair
    12441245variable "HDSDir"
    1245 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds"
     1246value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    12461247)
    12471248(vvPair
    12481249variable "SideDataDesignDir"
    1249 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info"
     1250value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info"
    12501251)
    12511252(vvPair
    12521253variable "SideDataUserDir"
    1253 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user"
     1254value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user"
    12541255)
    12551256(vvPair
    12561257variable "SourceDir"
    1257 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds"
     1258value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    12581259)
    12591260(vvPair
     
    12711272(vvPair
    12721273variable "d"
    1273 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board"
     1274value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board"
    12741275)
    12751276(vvPair
    12761277variable "d_logical"
    1277 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\FAD_Board"
     1278value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board"
    12781279)
    12791280(vvPair
    12801281variable "date"
    1281 value "16.06.2010"
     1282value "14.07.2010"
    12821283)
    12831284(vvPair
     
    12911292(vvPair
    12921293variable "dd"
    1293 value "16"
     1294value "14"
    12941295)
    12951296(vvPair
     
    13191320(vvPair
    13201321variable "host"
    1321 value "TU-CC4900F8C7D2"
     1322value "E5B-LABOR6"
    13221323)
    13231324(vvPair
     
    13301331)
    13311332(vvPair
     1333variable "library_downstream_HdsLintPlugin"
     1334value "$HDS_PROJECT_DIR\\FACT_FAD_lib\\designcheck"
     1335)
     1336(vvPair
    13321337variable "library_downstream_ISEPARInvoke"
    13331338value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
     
    13471352(vvPair
    13481353variable "mm"
    1349 value "06"
     1354value "07"
    13501355)
    13511356(vvPair
     
    13551360(vvPair
    13561361variable "month"
    1357 value "Jun"
     1362value "Jul"
    13581363)
    13591364(vvPair
    13601365variable "month_long"
    1361 value "Juni"
     1366value "Juli"
    13621367)
    13631368(vvPair
    13641369variable "p"
    1365 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb"
     1370value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb"
    13661371)
    13671372(vvPair
    13681373variable "p_logical"
    1369 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb"
     1374value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb"
    13701375)
    13711376(vvPair
     
    14231428(vvPair
    14241429variable "time"
    1425 value "15:30:04"
     1430value "15:25:08"
    14261431)
    14271432(vvPair
     
    15001505)
    15011506xt "44000,29200,76000,30000"
    1502 st "RSRLOAD    : OUT    std_logic                       := '0' ;"
     1507st "RSRLOAD    : OUT    std_logic                       := '0' ;
     1508"
    15031509)
    15041510thePort (LogicalPort
     
    15451551)
    15461552xt "44000,12400,61500,13200"
    1547 st "X_50M      : IN     STD_LOGIC  ;"
     1553st "X_50M      : IN     STD_LOGIC  ;
     1554"
    15481555)
    15491556thePort (LogicalPort
     
    15901597)
    15911598xt "44000,10800,61500,11600"
    1592 st "TRG        : IN     STD_LOGIC  ;"
     1599st "TRG        : IN     STD_LOGIC  ;
     1600"
    15931601)
    15941602thePort (LogicalPort
     
    16341642)
    16351643xt "44000,14000,71500,14800"
    1636 st "A_CLK      : OUT    std_logic_vector (3 downto 0) ;"
     1644st "A_CLK      : OUT    std_logic_vector (3 downto 0) ;
     1645"
    16371646)
    16381647thePort (LogicalPort
     
    16801689)
    16811690xt "44000,25200,61500,26000"
    1682 st "OE_ADC     : OUT    STD_LOGIC  ;"
     1691st "OE_ADC     : OUT    STD_LOGIC  ;
     1692"
    16831693)
    16841694thePort (LogicalPort
     
    17261736)
    17271737xt "44000,5200,71500,6000"
    1728 st "A_OTR      : IN     std_logic_vector (3 DOWNTO 0) ;"
     1738st "A_OTR      : IN     std_logic_vector (3 DOWNTO 0) ;
     1739"
    17291740)
    17301741thePort (LogicalPort
     
    17701781)
    17711782xt "44000,2000,72000,2800"
    1772 st "A0_D       : IN     std_logic_vector (11 DOWNTO 0) ;"
     1783st "A0_D       : IN     std_logic_vector (11 DOWNTO 0) ;
     1784"
    17731785)
    17741786thePort (LogicalPort
     
    18141826)
    18151827xt "44000,2800,72000,3600"
    1816 st "A1_D       : IN     std_logic_vector (11 DOWNTO 0) ;"
     1828st "A1_D       : IN     std_logic_vector (11 DOWNTO 0) ;
     1829"
    18171830)
    18181831thePort (LogicalPort
     
    18581871)
    18591872xt "44000,3600,72000,4400"
    1860 st "A2_D       : IN     std_logic_vector (11 DOWNTO 0) ;"
     1873st "A2_D       : IN     std_logic_vector (11 DOWNTO 0) ;
     1874"
    18611875)
    18621876thePort (LogicalPort
     
    19021916)
    19031917xt "44000,4400,72000,5200"
    1904 st "A3_D       : IN     std_logic_vector (11 DOWNTO 0) ;"
     1918st "A3_D       : IN     std_logic_vector (11 DOWNTO 0) ;
     1919"
    19051920)
    19061921thePort (LogicalPort
     
    19471962)
    19481963xt "44000,14800,61500,15600"
    1949 st "D0_SRCLK   : OUT    STD_LOGIC  ;"
     1964st "D0_SRCLK   : OUT    STD_LOGIC  ;
     1965"
    19501966)
    19511967thePort (LogicalPort
     
    19922008)
    19932009xt "44000,15600,61500,16400"
    1994 st "D1_SRCLK   : OUT    STD_LOGIC  ;"
     2010st "D1_SRCLK   : OUT    STD_LOGIC  ;
     2011"
    19952012)
    19962013thePort (LogicalPort
     
    20372054)
    20382055xt "44000,16400,61500,17200"
    2039 st "D2_SRCLK   : OUT    STD_LOGIC  ;"
     2056st "D2_SRCLK   : OUT    STD_LOGIC  ;
     2057"
    20402058)
    20412059thePort (LogicalPort
     
    20822100)
    20832101xt "44000,17200,61500,18000"
    2084 st "D3_SRCLK   : OUT    STD_LOGIC  ;"
     2102st "D3_SRCLK   : OUT    STD_LOGIC  ;
     2103"
    20852104)
    20862105thePort (LogicalPort
     
    21262145)
    21272146xt "44000,6000,61500,6800"
    2128 st "D0_SROUT   : IN     std_logic  ;"
     2147st "D0_SROUT   : IN     std_logic  ;
     2148"
    21292149)
    21302150thePort (LogicalPort
     
    21692189)
    21702190xt "44000,6800,61500,7600"
    2171 st "D1_SROUT   : IN     std_logic  ;"
     2191st "D1_SROUT   : IN     std_logic  ;
     2192"
    21722193)
    21732194thePort (LogicalPort
     
    22122233)
    22132234xt "44000,7600,61500,8400"
    2214 st "D2_SROUT   : IN     std_logic  ;"
     2235st "D2_SROUT   : IN     std_logic  ;
     2236"
    22152237)
    22162238thePort (LogicalPort
     
    22552277)
    22562278xt "44000,8400,61500,9200"
    2257 st "D3_SROUT   : IN     std_logic  ;"
     2279st "D3_SROUT   : IN     std_logic  ;
     2280"
    22582281)
    22592282thePort (LogicalPort
     
    23092332)
    23102333xt "44000,20400,82000,21200"
    2311 st "D_A        : OUT    std_logic_vector (3 DOWNTO 0)   := (others => '0') ;"
     2334st "D_A        : OUT    std_logic_vector (3 DOWNTO 0)   := (others => '0') ;
     2335"
    23122336)
    23132337thePort (LogicalPort
     
    23662390)
    23672391xt "44000,19600,76000,20400"
    2368 st "DWRITE     : OUT    std_logic                       := '0' ;"
     2392st "DWRITE     : OUT    std_logic                       := '0' ;
     2393"
    23692394)
    23702395thePort (LogicalPort
     
    24122437)
    24132438xt "44000,18000,61500,18800"
    2414 st "DAC_CS     : OUT    std_logic  ;"
     2439st "DAC_CS     : OUT    std_logic  ;
     2440"
    24152441)
    24162442thePort (LogicalPort
     
    24572483)
    24582484xt "44000,31600,61500,32400"
    2459 st "T0_CS      : OUT    std_logic  ;"
     2485st "T0_CS      : OUT    std_logic  ;
     2486"
    24602487)
    24612488thePort (LogicalPort
     
    25022529)
    25032530xt "44000,32400,61500,33200"
    2504 st "T1_CS      : OUT    std_logic  ;"
     2531st "T1_CS      : OUT    std_logic  ;
     2532"
    25052533)
    25062534thePort (LogicalPort
     
    25472575)
    25482576xt "44000,33200,61500,34000"
    2549 st "T2_CS      : OUT    std_logic  ;"
     2577st "T2_CS      : OUT    std_logic  ;
     2578"
    25502579)
    25512580thePort (LogicalPort
     
    25922621)
    25932622xt "44000,34000,61500,34800"
    2594 st "T3_CS      : OUT    std_logic  ;"
     2623st "T3_CS      : OUT    std_logic  ;
     2624"
    25952625)
    25962626thePort (LogicalPort
     
    26372667)
    26382668xt "44000,30800,61500,31600"
    2639 st "S_CLK      : OUT    std_logic  ;"
     2669st "S_CLK      : OUT    std_logic  ;
     2670"
    26402671)
    26412672thePort (LogicalPort
     
    26822713)
    26832714xt "44000,35600,71500,36400"
    2684 st "W_A        : OUT    std_logic_vector (9 DOWNTO 0) ;"
     2715st "W_A        : OUT    std_logic_vector (9 DOWNTO 0) ;
     2716"
    26852717)
    26862718thePort (LogicalPort
     
    27282760)
    27292761xt "44000,40400,71000,41200"
    2730 st "W_D        : INOUT  std_logic_vector (15 DOWNTO 0)"
     2762st "W_D        : INOUT  std_logic_vector (15 DOWNTO 0)
     2763"
    27312764)
    27322765thePort (LogicalPort
     
    27842817)
    27852818xt "44000,38000,76000,38800"
    2786 st "W_RES      : OUT    std_logic                       := '1' ;"
     2819st "W_RES      : OUT    std_logic                       := '1' ;
     2820"
    27872821)
    27882822thePort (LogicalPort
     
    28402874)
    28412875xt "44000,37200,76000,38000"
    2842 st "W_RD       : OUT    std_logic                       := '1' ;"
     2876st "W_RD       : OUT    std_logic                       := '1' ;
     2877"
    28432878)
    28442879thePort (LogicalPort
     
    28962931)
    28972932xt "44000,38800,76000,39600"
    2898 st "W_WR       : OUT    std_logic                       := '1' ;"
     2933st "W_WR       : OUT    std_logic                       := '1' ;
     2934"
    28992935)
    29002936thePort (LogicalPort
     
    29412977)
    29422978xt "44000,11600,61500,12400"
    2943 st "W_INT      : IN     std_logic  ;"
     2979st "W_INT      : IN     std_logic  ;
     2980"
    29442981)
    29452982thePort (LogicalPort
     
    29953032)
    29963033xt "44000,36400,76000,37200"
    2997 st "W_CS       : OUT    std_logic                       := '1' ;"
     3034st "W_CS       : OUT    std_logic                       := '1' ;
     3035"
    29983036)
    29993037thePort (LogicalPort
     
    30513089)
    30523090xt "44000,24400,76000,25200"
    3053 st "MOSI       : OUT    std_logic                       := '0' ;"
     3091st "MOSI       : OUT    std_logic                       := '0' ;
     3092"
    30543093)
    30553094thePort (LogicalPort
     
    30973136)
    30983137xt "44000,39600,61500,40400"
    3099 st "MISO       : INOUT  std_logic  ;"
     3138st "MISO       : INOUT  std_logic  ;
     3139"
    31003140)
    31013141thePort (LogicalPort
     
    31443184)
    31453185xt "44000,34800,61500,35600"
    3146 st "TRG_V      : OUT    std_logic  ;"
     3186st "TRG_V      : OUT    std_logic  ;
     3187"
    31473188)
    31483189thePort (LogicalPort
     
    31893230)
    31903231xt "44000,26800,61500,27600"
    3191 st "RS485_C_RE : OUT    std_logic  ;"
     3232st "RS485_C_RE : OUT    std_logic  ;
     3233"
    31923234)
    31933235thePort (LogicalPort
     
    32343276)
    32353277xt "44000,26000,61500,26800"
    3236 st "RS485_C_DE : OUT    std_logic  ;"
     3278st "RS485_C_DE : OUT    std_logic  ;
     3279"
    32373280)
    32383281thePort (LogicalPort
     
    32793322)
    32803323xt "44000,28400,61500,29200"
    3281 st "RS485_E_RE : OUT    std_logic  ;"
     3324st "RS485_E_RE : OUT    std_logic  ;
     3325"
    32823326)
    32833327thePort (LogicalPort
     
    33243368)
    33253369xt "44000,27600,61500,28400"
    3326 st "RS485_E_DE : OUT    std_logic  ;"
     3370st "RS485_E_DE : OUT    std_logic  ;
     3371"
    33273372)
    33283373thePort (LogicalPort
     
    33793424)
    33803425xt "44000,18800,76000,19600"
    3381 st "DENABLE    : OUT    std_logic                       := '0' ;"
     3426st "DENABLE    : OUT    std_logic                       := '0' ;
     3427"
    33823428)
    33833429thePort (LogicalPort
     
    34253471)
    34263472xt "44000,30000,61500,30800"
    3427 st "SRIN       : OUT    std_logic  ;"
     3473st "SRIN       : OUT    std_logic  ;
     3474"
    34283475)
    34293476thePort (LogicalPort
     
    34703517)
    34713518xt "44000,22800,61500,23600"
    3472 st "EE_CS      : OUT    std_logic  ;"
     3519st "EE_CS      : OUT    std_logic  ;
     3520"
    34733521)
    34743522thePort (LogicalPort
     
    35253573)
    35263574xt "44000,21200,82000,22000"
    3527 st "D_T        : OUT    std_logic_vector (7 DOWNTO 0)   := (OTHERS => '0') ;"
     3575st "D_T        : OUT    std_logic_vector (7 DOWNTO 0)   := (OTHERS => '0') ;
     3576"
    35283577)
    35293578thePort (LogicalPort
     
    35823631)
    35833632xt "44000,23600,82000,24400"
    3584 st "LED        : OUT    std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ;"
     3633st "LED        : OUT    std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ;
     3634"
    35853635)
    35863636thePort (LogicalPort
     
    36283678)
    36293679xt "44000,10000,61500,10800"
    3630 st "TEST_TRG   : IN     std_logic  ;"
     3680st "TEST_TRG   : IN     std_logic  ;
     3681"
    36313682)
    36323683thePort (LogicalPort
     
    36713722)
    36723723xt "44000,9200,71500,10000"
    3673 st "D_PLLLCK   : IN     std_logic_vector (3 DOWNTO 0) ;"
     3724st "D_PLLLCK   : IN     std_logic_vector (3 DOWNTO 0) ;
     3725"
    36743726)
    36753727thePort (LogicalPort
     
    37263778)
    37273779xt "44000,22000,82000,22800"
    3728 st "D_T2       : OUT    std_logic_vector (3 DOWNTO 0)   := (others => '0') ;"
     3780st "D_T2       : OUT    std_logic_vector (3 DOWNTO 0)   := (others => '0') ;
     3781"
    37293782)
    37303783thePort (LogicalPort
     
    37613814)
    37623815xt "27200,97500,32000,98500"
    3763 st "A1_T : (3:0)"
     3816st "A1_T : (7:0)"
    37643817ju 2
    37653818blo "32000,98300"
    37663819tm "CptPortNameMgr"
    37673820)
     3821t (Text
     3822uid 3123,0
     3823va (VaSet
     3824)
     3825xt "25100,98500,32000,99500"
     3826st "(OTHERS => '0')"
     3827ju 2
     3828blo "32000,99300"
     3829tm "InitValueDelayMgr"
     3830)
    37683831)
    37693832dt (MLText
     
    37723835font "Courier New,8,0"
    37733836)
    3774 xt "44000,13200,71500,14000"
    3775 st "A1_T       : OUT    std_logic_vector (3 DOWNTO 0) ;"
     3837xt "44000,13200,82000,14000"
     3838st "A1_T       : OUT    std_logic_vector (7 DOWNTO 0)   := (OTHERS => '0') ;
     3839"
    37763840)
    37773841thePort (LogicalPort
     
    37803844n "A1_T"
    37813845t "std_logic_vector"
    3782 b "(3 DOWNTO 0)"
     3846b "(7 DOWNTO 0)"
    37833847o 15
    37843848suid 66,0
     3849i "(OTHERS => '0')"
    37853850)
    37863851)
     
    37953860lineWidth 2
    37963861)
    3797 xt "15000,6000,33000,99000"
     3862xt "15000,6000,33000,101000"
    37983863)
    37993864oxt "15000,6000,33000,26000"
     
    38693934bg "0,0,32768"
    38703935)
    3871 xt "36200,48000,45700,49000"
     3936xt "36200,48000,45500,49000"
    38723937st "
    38733938by %user on %dd %month %year
     
    44524517)
    44534518)
    4454 lastUid 3076,0
     4519lastUid 3292,0
    44554520activeModelName "Symbol:CDM"
    44564521)
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