Changeset 252 for FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board
- Timestamp:
- 07/16/10 16:25:44 (15 years ago)
- Location:
- FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd
r246 r252 40 40 ) 41 41 (Instance 42 name "I_debouncer"43 duLibraryName "FACT_FAD_LIB"44 duName "debouncer"45 elements [46 (GiElement47 name "WIDTH"48 type "INTEGER"49 value "17"50 )51 ]52 mwi 053 uid 6250,054 )55 (Instance56 name "I1"57 duLibraryName "moduleware"58 duName "inv"59 elements [60 ]61 mwi 162 uid 6539,063 )64 (Instance65 42 name "I2" 66 43 duLibraryName "moduleware" … … 128 105 (vvPair 129 106 variable "HDLDir" 130 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hdl"107 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" 131 108 ) 132 109 (vvPair 133 110 variable "HDSDir" 134 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds"111 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 135 112 ) 136 113 (vvPair 137 114 variable "SideDataDesignDir" 138 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"115 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info" 139 116 ) 140 117 (vvPair 141 118 variable "SideDataUserDir" 142 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"119 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user" 143 120 ) 144 121 (vvPair 145 122 variable "SourceDir" 146 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds"123 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 147 124 ) 148 125 (vvPair … … 156 133 (vvPair 157 134 variable "config" 158 value "%(unit)_ config"135 value "%(unit)_%(view)_config" 159 136 ) 160 137 (vvPair 161 138 variable "d" 162 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board"139 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board" 163 140 ) 164 141 (vvPair 165 142 variable "d_logical" 166 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board"143 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board" 167 144 ) 168 145 (vvPair 169 146 variable "date" 170 value " 24.06.2010"147 value "14.07.2010" 171 148 ) 172 149 (vvPair 173 150 variable "day" 174 value " Do"151 value "Mi" 175 152 ) 176 153 (vvPair 177 154 variable "day_long" 178 value " Donnerstag"155 value "Mittwoch" 179 156 ) 180 157 (vvPair 181 158 variable "dd" 182 value " 24"159 value "14" 183 160 ) 184 161 (vvPair … … 208 185 (vvPair 209 186 variable "host" 210 value "E EPC8"187 value "E5B-LABOR6" 211 188 ) 212 189 (vvPair … … 219 196 ) 220 197 (vvPair 198 variable "library_downstream_HdsLintPlugin" 199 value "$HDS_PROJECT_DIR\\FACT_FAD_lib\\designcheck" 200 ) 201 (vvPair 221 202 variable "library_downstream_ISEPARInvoke" 222 203 value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" … … 236 217 (vvPair 237 218 variable "mm" 238 value "0 6"219 value "07" 239 220 ) 240 221 (vvPair … … 244 225 (vvPair 245 226 variable "month" 246 value "Ju n"227 value "Jul" 247 228 ) 248 229 (vvPair 249 230 variable "month_long" 250 value "Ju ni"231 value "Juli" 251 232 ) 252 233 (vvPair 253 234 variable "p" 254 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"235 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd" 255 236 ) 256 237 (vvPair 257 238 variable "p_logical" 258 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"239 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd" 259 240 ) 260 241 (vvPair … … 280 261 (vvPair 281 262 variable "task_ModelSimPath" 282 value " $HDS_HOME/../Modeltech/win32"263 value "<TBD>" 283 264 ) 284 265 (vvPair … … 288 269 (vvPair 289 270 variable "task_PrecisionRTLPath" 290 value " $HDS_HOME/../Precision/Mgc_home/bin"271 value "<TBD>" 291 272 ) 292 273 (vvPair … … 312 293 (vvPair 313 294 variable "time" 314 value "1 4:18:44"295 value "15:25:08" 315 296 ) 316 297 (vvPair … … 320 301 (vvPair 321 302 variable "user" 322 value " Benjamin Krumm"303 value "dneise" 323 304 ) 324 305 (vvPair … … 364 345 bg "0,0,32768" 365 346 ) 366 xt "99200,4000,108 700,5000"347 xt "99200,4000,108500,5000" 367 348 st " 368 349 by %user on %dd %month %year … … 2074 2055 ) 2075 2056 xt "39000,48000,67000,48800" 2076 st "SIGNAL board_id : std_logic_vector(3 downto 0)" 2057 st "SIGNAL board_id : std_logic_vector(3 downto 0) 2058 " 2077 2059 ) 2078 2060 ) … … 2092 2074 ) 2093 2075 xt "39000,48800,67000,49600" 2094 st "SIGNAL crate_id : std_logic_vector(1 downto 0)" 2076 st "SIGNAL crate_id : std_logic_vector(1 downto 0) 2077 " 2095 2078 ) 2096 2079 ) … … 2415 2398 ) 2416 2399 xt "39000,47200,62500,48000" 2417 st "SIGNAL adc_data_array : adc_data_array_type" 2400 st "SIGNAL adc_data_array : adc_data_array_type 2401 " 2418 2402 ) 2419 2403 ) 2420 2404 *63 (Net 2421 uid 2267,02422 decl (Decl2423 n "CLK_50"2424 t "std_logic"2425 preAdd 02426 posAdd 02427 o 512428 suid 54,02429 )2430 declText (MLText2431 uid 2268,02432 va (VaSet2433 font "Courier New,8,0"2434 )2435 xt "39000,44800,57000,45600"2436 st "SIGNAL CLK_50 : std_logic"2437 )2438 )2439 *64 (Net2440 2405 uid 2407,0 2441 2406 decl (Decl … … 2452 2417 ) 2453 2418 xt "39000,31000,68000,31800" 2454 st "RSRLOAD : std_logic := '0'" 2455 ) 2456 ) 2457 *65 (PortIoOut 2419 st "RSRLOAD : std_logic := '0' 2420 " 2421 ) 2422 ) 2423 *64 (PortIoOut 2458 2424 uid 2415,0 2459 2425 shape (CompositeShape … … 2500 2466 ) 2501 2467 ) 2502 *6 6(Net2468 *65 (Net 2503 2469 uid 2421,0 2504 2470 decl (Decl … … 2515 2481 ) 2516 2482 xt "39000,45600,71500,46400" 2517 st "SIGNAL SRCLK : std_logic := '0'" 2518 ) 2519 ) 2520 *67 (Net 2483 st "SIGNAL SRCLK : std_logic := '0' 2484 " 2485 ) 2486 ) 2487 *66 (Net 2521 2488 uid 3019,0 2522 2489 decl (Decl … … 2533 2500 ) 2534 2501 xt "39000,51200,67000,52000" 2535 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" 2536 ) 2537 ) 2538 *68 (Net 2502 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0) 2503 " 2504 ) 2505 ) 2506 *67 (Net 2539 2507 uid 3025,0 2540 2508 decl (Decl … … 2550 2518 ) 2551 2519 xt "39000,19800,53500,20600" 2552 st "DAC_CS : std_logic" 2553 ) 2554 ) 2555 *69 (PortIoOut 2520 st "DAC_CS : std_logic 2521 " 2522 ) 2523 ) 2524 *68 (PortIoOut 2556 2525 uid 3153,0 2557 2526 shape (CompositeShape … … 2598 2567 ) 2599 2568 ) 2600 * 70(Net2569 *69 (Net 2601 2570 uid 3216,0 2602 2571 decl (Decl … … 2614 2583 ) 2615 2584 xt "39000,14200,53500,15000" 2616 st "X_50M : STD_LOGIC" 2617 ) 2618 ) 2619 *71 (Net 2585 st "X_50M : STD_LOGIC 2586 " 2587 ) 2588 ) 2589 *70 (Net 2620 2590 uid 3226,0 2621 2591 decl (Decl … … 2631 2601 ) 2632 2602 xt "39000,12600,53500,13400" 2633 st "TRG : STD_LOGIC" 2634 ) 2635 ) 2636 *72 (HdlText 2603 st "TRG : STD_LOGIC 2604 " 2605 ) 2606 ) 2607 *71 (HdlText 2637 2608 uid 3248,0 2638 2609 optionalChildren [ 2639 *7 3(EmbeddedText2610 *72 (EmbeddedText 2640 2611 uid 3254,0 2641 2612 commentText (CommentText … … 2689 2660 stg "VerticalLayoutStrategy" 2690 2661 textVec [ 2691 *7 4(Text2662 *73 (Text 2692 2663 uid 3251,0 2693 2664 va (VaSet … … 2699 2670 tm "HdlTextNameMgr" 2700 2671 ) 2701 *7 5(Text2672 *74 (Text 2702 2673 uid 3252,0 2703 2674 va (VaSet … … 2725 2696 viewiconposition 0 2726 2697 ) 2727 *7 6(Net2698 *75 (Net 2728 2699 uid 3266,0 2729 2700 decl (Decl … … 2740 2711 ) 2741 2712 xt "39000,15800,63500,16600" 2742 st "A_CLK : std_logic_vector(3 downto 0)" 2743 ) 2744 ) 2745 *77 (Net 2713 st "A_CLK : std_logic_vector(3 downto 0) 2714 " 2715 ) 2716 ) 2717 *76 (Net 2746 2718 uid 3268,0 2747 2719 decl (Decl … … 2757 2729 ) 2758 2730 xt "39000,44000,57000,44800" 2759 st "SIGNAL CLK_25_PS : std_logic" 2760 ) 2761 ) 2762 *78 (PortIoOut 2731 st "SIGNAL CLK_25_PS : std_logic 2732 " 2733 ) 2734 ) 2735 *77 (PortIoOut 2763 2736 uid 3284,0 2764 2737 shape (CompositeShape … … 2805 2778 ) 2806 2779 ) 2807 *7 9(Net2780 *78 (Net 2808 2781 uid 3290,0 2809 2782 decl (Decl … … 2821 2794 ) 2822 2795 xt "39000,27000,53500,27800" 2823 st "OE_ADC : STD_LOGIC" 2824 ) 2825 ) 2826 *80 (PortIoIn 2796 st "OE_ADC : STD_LOGIC 2797 " 2798 ) 2799 ) 2800 *79 (PortIoIn 2827 2801 uid 3292,0 2828 2802 shape (CompositeShape … … 2869 2843 ) 2870 2844 ) 2871 *8 1(Net2845 *80 (Net 2872 2846 uid 3298,0 2873 2847 decl (Decl … … 2884 2858 ) 2885 2859 xt "39000,7000,63500,7800" 2886 st "A_OTR : std_logic_vector(3 DOWNTO 0)" 2887 ) 2888 ) 2889 *82 (HdlText 2860 st "A_OTR : std_logic_vector(3 DOWNTO 0) 2861 " 2862 ) 2863 ) 2864 *81 (HdlText 2890 2865 uid 3300,0 2891 2866 optionalChildren [ 2892 *8 3(EmbeddedText2867 *82 (EmbeddedText 2893 2868 uid 3306,0 2894 2869 commentText (CommentText … … 2942 2917 stg "VerticalLayoutStrategy" 2943 2918 textVec [ 2944 *8 4(Text2919 *83 (Text 2945 2920 uid 3303,0 2946 2921 va (VaSet … … 2952 2927 tm "HdlTextNameMgr" 2953 2928 ) 2954 *8 5(Text2929 *84 (Text 2955 2930 uid 3304,0 2956 2931 va (VaSet … … 2978 2953 viewiconposition 0 2979 2954 ) 2980 *8 6(PortIoIn2955 *85 (PortIoIn 2981 2956 uid 3310,0 2982 2957 shape (CompositeShape … … 3023 2998 ) 3024 2999 ) 3025 *8 7(PortIoIn3000 *86 (PortIoIn 3026 3001 uid 3332,0 3027 3002 shape (CompositeShape … … 3068 3043 ) 3069 3044 ) 3070 *8 8(PortIoIn3045 *87 (PortIoIn 3071 3046 uid 3338,0 3072 3047 shape (CompositeShape … … 3113 3088 ) 3114 3089 ) 3115 *8 9(PortIoIn3090 *88 (PortIoIn 3116 3091 uid 3344,0 3117 3092 shape (CompositeShape … … 3158 3133 ) 3159 3134 ) 3160 * 90(Net3135 *89 (Net 3161 3136 uid 3374,0 3162 3137 decl (Decl … … 3173 3148 ) 3174 3149 xt "39000,3800,64000,4600" 3175 st "A0_D : std_logic_vector(11 DOWNTO 0)" 3176 ) 3177 ) 3178 *91 (Net 3150 st "A0_D : std_logic_vector(11 DOWNTO 0) 3151 " 3152 ) 3153 ) 3154 *90 (Net 3179 3155 uid 3376,0 3180 3156 decl (Decl … … 3191 3167 ) 3192 3168 xt "39000,4600,64000,5400" 3193 st "A1_D : std_logic_vector(11 DOWNTO 0)" 3194 ) 3195 ) 3196 *92 (Net 3169 st "A1_D : std_logic_vector(11 DOWNTO 0) 3170 " 3171 ) 3172 ) 3173 *91 (Net 3197 3174 uid 3378,0 3198 3175 decl (Decl … … 3209 3186 ) 3210 3187 xt "39000,5400,64000,6200" 3211 st "A2_D : std_logic_vector(11 DOWNTO 0)" 3212 ) 3213 ) 3214 *93 (Net 3188 st "A2_D : std_logic_vector(11 DOWNTO 0) 3189 " 3190 ) 3191 ) 3192 *92 (Net 3215 3193 uid 3380,0 3216 3194 decl (Decl … … 3227 3205 ) 3228 3206 xt "39000,6200,64000,7000" 3229 st "A3_D : std_logic_vector(11 DOWNTO 0)" 3230 ) 3231 ) 3232 *94 (HdlText 3207 st "A3_D : std_logic_vector(11 DOWNTO 0) 3208 " 3209 ) 3210 ) 3211 *93 (HdlText 3233 3212 uid 3394,0 3234 3213 optionalChildren [ 3235 *9 5(EmbeddedText3214 *94 (EmbeddedText 3236 3215 uid 3400,0 3237 3216 commentText (CommentText … … 3285 3264 stg "VerticalLayoutStrategy" 3286 3265 textVec [ 3287 *9 6(Text3266 *95 (Text 3288 3267 uid 3397,0 3289 3268 va (VaSet … … 3295 3274 tm "HdlTextNameMgr" 3296 3275 ) 3297 *9 7(Text3276 *96 (Text 3298 3277 uid 3398,0 3299 3278 va (VaSet … … 3321 3300 viewiconposition 0 3322 3301 ) 3323 *9 8(Net3302 *97 (Net 3324 3303 uid 3460,0 3325 3304 decl (Decl … … 3335 3314 ) 3336 3315 xt "39000,16600,53500,17400" 3337 st "D0_SRCLK : STD_LOGIC" 3338 ) 3339 ) 3340 *99 (Net 3316 st "D0_SRCLK : STD_LOGIC 3317 " 3318 ) 3319 ) 3320 *98 (Net 3341 3321 uid 3462,0 3342 3322 decl (Decl … … 3352 3332 ) 3353 3333 xt "39000,17400,53500,18200" 3354 st "D1_SRCLK : STD_LOGIC" 3355 ) 3356 ) 3357 *100 (Net 3334 st "D1_SRCLK : STD_LOGIC 3335 " 3336 ) 3337 ) 3338 *99 (Net 3358 3339 uid 3464,0 3359 3340 decl (Decl … … 3369 3350 ) 3370 3351 xt "39000,18200,53500,19000" 3371 st "D2_SRCLK : STD_LOGIC" 3372 ) 3373 ) 3374 *101 (Net 3352 st "D2_SRCLK : STD_LOGIC 3353 " 3354 ) 3355 ) 3356 *100 (Net 3375 3357 uid 3466,0 3376 3358 decl (Decl … … 3386 3368 ) 3387 3369 xt "39000,19000,53500,19800" 3388 st "D3_SRCLK : STD_LOGIC" 3389 ) 3390 ) 3391 *102 (PortIoIn 3370 st "D3_SRCLK : STD_LOGIC 3371 " 3372 ) 3373 ) 3374 *101 (PortIoIn 3392 3375 uid 3476,0 3393 3376 shape (CompositeShape … … 3434 3417 ) 3435 3418 ) 3436 *10 3(PortIoIn3419 *102 (PortIoIn 3437 3420 uid 3482,0 3438 3421 shape (CompositeShape … … 3479 3462 ) 3480 3463 ) 3481 *10 4(PortIoIn3464 *103 (PortIoIn 3482 3465 uid 3488,0 3483 3466 shape (CompositeShape … … 3524 3507 ) 3525 3508 ) 3526 *10 5(PortIoIn3509 *104 (PortIoIn 3527 3510 uid 3494,0 3528 3511 shape (CompositeShape … … 3569 3552 ) 3570 3553 ) 3571 *10 6(Net3554 *105 (Net 3572 3555 uid 3500,0 3573 3556 decl (Decl … … 3583 3566 ) 3584 3567 xt "39000,7800,53500,8600" 3585 st "D0_SROUT : std_logic" 3586 ) 3587 ) 3588 *107 (Net 3568 st "D0_SROUT : std_logic 3569 " 3570 ) 3571 ) 3572 *106 (Net 3589 3573 uid 3502,0 3590 3574 decl (Decl … … 3600 3584 ) 3601 3585 xt "39000,8600,53500,9400" 3602 st "D1_SROUT : std_logic" 3603 ) 3604 ) 3605 *108 (Net 3586 st "D1_SROUT : std_logic 3587 " 3588 ) 3589 ) 3590 *107 (Net 3606 3591 uid 3504,0 3607 3592 decl (Decl … … 3617 3602 ) 3618 3603 xt "39000,9400,53500,10200" 3619 st "D2_SROUT : std_logic" 3620 ) 3621 ) 3622 *109 (Net 3604 st "D2_SROUT : std_logic 3605 " 3606 ) 3607 ) 3608 *108 (Net 3623 3609 uid 3506,0 3624 3610 decl (Decl … … 3634 3620 ) 3635 3621 xt "39000,10200,53500,11000" 3636 st "D3_SROUT : std_logic" 3637 ) 3638 ) 3639 *110 (PortIoOut 3622 st "D3_SROUT : std_logic 3623 " 3624 ) 3625 ) 3626 *109 (PortIoOut 3640 3627 uid 3508,0 3641 3628 shape (CompositeShape … … 3650 3637 sl 0 3651 3638 ro 90 3652 xt " 19000,108625,20500,109375"3639 xt "4000,133625,5500,134375" 3653 3640 ) 3654 3641 (Line … … 3656 3643 sl 0 3657 3644 ro 90 3658 xt " 20500,109000,21000,109000"3659 pts [ 3660 " 21000,109000"3661 " 20500,109000"3645 xt "5500,134000,6000,134000" 3646 pts [ 3647 "6000,134000" 3648 "5500,134000" 3662 3649 ] 3663 3650 ) … … 3674 3661 va (VaSet 3675 3662 ) 3676 xt "1 6100,108500,18000,109500"3663 xt "1100,133500,3000,134500" 3677 3664 st "D_A" 3678 3665 ju 2 3679 blo " 18000,109300"3666 blo "3000,134300" 3680 3667 tm "WireNameMgr" 3681 3668 ) 3682 3669 ) 3683 3670 ) 3684 *11 1(Net3671 *110 (Net 3685 3672 uid 3514,0 3686 3673 decl (Decl … … 3698 3685 ) 3699 3686 xt "39000,22200,74000,23000" 3700 st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0')" 3701 ) 3702 ) 3703 *112 (PortIoOut 3687 st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0') 3688 " 3689 ) 3690 ) 3691 *111 (PortIoOut 3704 3692 uid 3516,0 3705 3693 shape (CompositeShape … … 3746 3734 ) 3747 3735 ) 3748 *11 3(Net3736 *112 (Net 3749 3737 uid 3522,0 3750 3738 decl (Decl … … 3761 3749 ) 3762 3750 xt "39000,21400,68000,22200" 3763 st "DWRITE : std_logic := '0'" 3764 ) 3765 ) 3766 *114 (PortIoOut 3751 st "DWRITE : std_logic := '0' 3752 " 3753 ) 3754 ) 3755 *113 (PortIoOut 3767 3756 uid 3536,0 3768 3757 shape (CompositeShape … … 3808 3797 ) 3809 3798 ) 3810 *11 5(HdlText3799 *114 (HdlText 3811 3800 uid 3542,0 3812 3801 optionalChildren [ 3813 *11 6(EmbeddedText3802 *115 (EmbeddedText 3814 3803 uid 3612,0 3815 3804 commentText (CommentText … … 3863 3852 stg "VerticalLayoutStrategy" 3864 3853 textVec [ 3865 *11 7(Text3854 *116 (Text 3866 3855 uid 3545,0 3867 3856 va (VaSet … … 3873 3862 tm "HdlTextNameMgr" 3874 3863 ) 3875 *11 8(Text3864 *117 (Text 3876 3865 uid 3546,0 3877 3866 va (VaSet … … 3899 3888 viewiconposition 0 3900 3889 ) 3901 *11 9(PortIoOut3890 *118 (PortIoOut 3902 3891 uid 3548,0 3903 3892 shape (CompositeShape … … 3943 3932 ) 3944 3933 ) 3945 *1 20(PortIoOut3934 *119 (PortIoOut 3946 3935 uid 3554,0 3947 3936 shape (CompositeShape … … 3987 3976 ) 3988 3977 ) 3989 *12 1(PortIoOut3978 *120 (PortIoOut 3990 3979 uid 3560,0 3991 3980 shape (CompositeShape … … 4031 4020 ) 4032 4021 ) 4033 *12 2(PortIoOut4022 *121 (PortIoOut 4034 4023 uid 3566,0 4035 4024 shape (CompositeShape … … 4075 4064 ) 4076 4065 ) 4077 *12 3(Net4066 *122 (Net 4078 4067 uid 3604,0 4079 4068 decl (Decl … … 4089 4078 ) 4090 4079 xt "39000,33400,53500,34200" 4091 st "T0_CS : std_logic" 4092 ) 4093 ) 4094 *124 (Net 4080 st "T0_CS : std_logic 4081 " 4082 ) 4083 ) 4084 *123 (Net 4095 4085 uid 3606,0 4096 4086 decl (Decl … … 4106 4096 ) 4107 4097 xt "39000,34200,53500,35000" 4108 st "T1_CS : std_logic" 4109 ) 4110 ) 4111 *125 (Net 4098 st "T1_CS : std_logic 4099 " 4100 ) 4101 ) 4102 *124 (Net 4112 4103 uid 3608,0 4113 4104 decl (Decl … … 4123 4114 ) 4124 4115 xt "39000,35000,53500,35800" 4125 st "T2_CS : std_logic" 4126 ) 4127 ) 4128 *126 (Net 4116 st "T2_CS : std_logic 4117 " 4118 ) 4119 ) 4120 *125 (Net 4129 4121 uid 3610,0 4130 4122 decl (Decl … … 4140 4132 ) 4141 4133 xt "39000,35800,53500,36600" 4142 st "T3_CS : std_logic" 4143 ) 4144 ) 4145 *127 (PortIoOut 4134 st "T3_CS : std_logic 4135 " 4136 ) 4137 ) 4138 *126 (PortIoOut 4146 4139 uid 3624,0 4147 4140 shape (CompositeShape … … 4187 4180 ) 4188 4181 ) 4189 *12 8(Net4182 *127 (Net 4190 4183 uid 3630,0 4191 4184 decl (Decl … … 4201 4194 ) 4202 4195 xt "39000,32600,53500,33400" 4203 st "S_CLK : std_logic" 4204 ) 4205 ) 4206 *129 (Net 4196 st "S_CLK : std_logic 4197 " 4198 ) 4199 ) 4200 *128 (Net 4207 4201 uid 3632,0 4208 4202 decl (Decl … … 4219 4213 ) 4220 4214 xt "39000,37400,63500,38200" 4221 st "W_A : std_logic_vector(9 DOWNTO 0)" 4222 ) 4223 ) 4224 *130 (Net 4215 st "W_A : std_logic_vector(9 DOWNTO 0) 4216 " 4217 ) 4218 ) 4219 *129 (Net 4225 4220 uid 3634,0 4226 4221 decl (Decl … … 4237 4232 ) 4238 4233 xt "39000,42200,64000,43000" 4239 st "W_D : std_logic_vector(15 DOWNTO 0)" 4240 ) 4241 ) 4242 *131 (Net 4234 st "W_D : std_logic_vector(15 DOWNTO 0) 4235 " 4236 ) 4237 ) 4238 *130 (Net 4243 4239 uid 3636,0 4244 4240 decl (Decl … … 4255 4251 ) 4256 4252 xt "39000,39800,68000,40600" 4257 st "W_RES : std_logic := '1'" 4258 ) 4259 ) 4260 *132 (Net 4253 st "W_RES : std_logic := '1' 4254 " 4255 ) 4256 ) 4257 *131 (Net 4261 4258 uid 3638,0 4262 4259 decl (Decl … … 4273 4270 ) 4274 4271 xt "39000,39000,68000,39800" 4275 st "W_RD : std_logic := '1'" 4276 ) 4277 ) 4278 *133 (Net 4272 st "W_RD : std_logic := '1' 4273 " 4274 ) 4275 ) 4276 *132 (Net 4279 4277 uid 3640,0 4280 4278 decl (Decl … … 4291 4289 ) 4292 4290 xt "39000,40600,68000,41400" 4293 st "W_WR : std_logic := '1'" 4294 ) 4295 ) 4296 *134 (Net 4291 st "W_WR : std_logic := '1' 4292 " 4293 ) 4294 ) 4295 *133 (Net 4297 4296 uid 3642,0 4298 4297 decl (Decl … … 4308 4307 ) 4309 4308 xt "39000,13400,53500,14200" 4310 st "W_INT : std_logic" 4311 ) 4312 ) 4313 *135 (Net 4309 st "W_INT : std_logic 4310 " 4311 ) 4312 ) 4313 *134 (Net 4314 4314 uid 3644,0 4315 4315 decl (Decl … … 4326 4326 ) 4327 4327 xt "39000,38200,68000,39000" 4328 st "W_CS : std_logic := '1'" 4329 ) 4330 ) 4331 *136 (PortIoInOut 4328 st "W_CS : std_logic := '1' 4329 " 4330 ) 4331 ) 4332 *135 (PortIoInOut 4332 4333 uid 3674,0 4333 4334 shape (CompositeShape … … 4371 4372 ) 4372 4373 ) 4373 *13 7(Net4374 *136 (Net 4374 4375 uid 3680,0 4375 4376 decl (Decl … … 4386 4387 ) 4387 4388 xt "39000,26200,68000,27000" 4388 st "MOSI : std_logic := '0'" 4389 ) 4390 ) 4391 *138 (PortIoOut 4389 st "MOSI : std_logic := '0' 4390 " 4391 ) 4392 ) 4393 *137 (PortIoOut 4392 4394 uid 3688,0 4393 4395 shape (CompositeShape … … 4433 4435 ) 4434 4436 ) 4435 *13 9(Net4437 *138 (Net 4436 4438 uid 3694,0 4437 4439 decl (Decl … … 4449 4451 ) 4450 4452 xt "39000,41400,53500,42200" 4451 st "MISO : std_logic" 4452 ) 4453 ) 4454 *140 (HdlText 4453 st "MISO : std_logic 4454 " 4455 ) 4456 ) 4457 *139 (HdlText 4455 4458 uid 3700,0 4456 4459 optionalChildren [ 4457 *14 1(EmbeddedText4460 *140 (EmbeddedText 4458 4461 uid 3706,0 4459 4462 commentText (CommentText … … 4522 4525 stg "VerticalLayoutStrategy" 4523 4526 textVec [ 4524 *14 2(Text4527 *141 (Text 4525 4528 uid 3703,0 4526 4529 va (VaSet … … 4532 4535 tm "HdlTextNameMgr" 4533 4536 ) 4534 *14 3(Text4537 *142 (Text 4535 4538 uid 3704,0 4536 4539 va (VaSet … … 4558 4561 viewiconposition 0 4559 4562 ) 4560 *14 4(PortIoOut4563 *143 (PortIoOut 4561 4564 uid 3710,0 4562 4565 shape (CompositeShape … … 4602 4605 ) 4603 4606 ) 4604 *14 5(PortIoOut4607 *144 (PortIoOut 4605 4608 uid 3716,0 4606 4609 shape (CompositeShape … … 4646 4649 ) 4647 4650 ) 4648 *14 6(PortIoOut4651 *145 (PortIoOut 4649 4652 uid 3722,0 4650 4653 shape (CompositeShape … … 4690 4693 ) 4691 4694 ) 4692 *14 7(PortIoOut4695 *146 (PortIoOut 4693 4696 uid 3728,0 4694 4697 shape (CompositeShape … … 4734 4737 ) 4735 4738 ) 4736 *14 8(PortIoOut4739 *147 (PortIoOut 4737 4740 uid 3734,0 4738 4741 shape (CompositeShape … … 4778 4781 ) 4779 4782 ) 4780 *14 9(PortIoOut4783 *148 (PortIoOut 4781 4784 uid 3740,0 4782 4785 shape (CompositeShape … … 4822 4825 ) 4823 4826 ) 4824 *1 50(PortIoOut4827 *149 (PortIoOut 4825 4828 uid 3746,0 4826 4829 shape (CompositeShape … … 4866 4869 ) 4867 4870 ) 4868 *15 1(PortIoOut4871 *150 (PortIoOut 4869 4872 uid 3752,0 4870 4873 shape (CompositeShape … … 4910 4913 ) 4911 4914 ) 4912 *15 2(PortIoOut4915 *151 (PortIoOut 4913 4916 uid 3758,0 4914 4917 shape (CompositeShape … … 4954 4957 ) 4955 4958 ) 4956 *15 3(Net4959 *152 (Net 4957 4960 uid 3864,0 4958 4961 decl (Decl … … 4968 4971 ) 4969 4972 xt "39000,36600,53500,37400" 4970 st "TRG_V : std_logic" 4971 ) 4972 ) 4973 *154 (Net 4973 st "TRG_V : std_logic 4974 " 4975 ) 4976 ) 4977 *153 (Net 4974 4978 uid 3866,0 4975 4979 decl (Decl … … 4985 4989 ) 4986 4990 xt "39000,28600,53500,29400" 4987 st "RS485_C_RE : std_logic" 4988 ) 4989 ) 4990 *155 (Net 4991 st "RS485_C_RE : std_logic 4992 " 4993 ) 4994 ) 4995 *154 (Net 4991 4996 uid 3868,0 4992 4997 decl (Decl … … 5002 5007 ) 5003 5008 xt "39000,27800,53500,28600" 5004 st "RS485_C_DE : std_logic" 5005 ) 5006 ) 5007 *156 (Net 5009 st "RS485_C_DE : std_logic 5010 " 5011 ) 5012 ) 5013 *155 (Net 5008 5014 uid 3870,0 5009 5015 decl (Decl … … 5019 5025 ) 5020 5026 xt "39000,30200,53500,31000" 5021 st "RS485_E_RE : std_logic" 5022 ) 5023 ) 5024 *157 (Net 5027 st "RS485_E_RE : std_logic 5028 " 5029 ) 5030 ) 5031 *156 (Net 5025 5032 uid 3872,0 5026 5033 decl (Decl … … 5036 5043 ) 5037 5044 xt "39000,29400,53500,30200" 5038 st "RS485_E_DE : std_logic" 5039 ) 5040 ) 5041 *158 (Net 5045 st "RS485_E_DE : std_logic 5046 " 5047 ) 5048 ) 5049 *157 (Net 5042 5050 uid 3874,0 5043 5051 decl (Decl … … 5054 5062 ) 5055 5063 xt "39000,20600,68000,21400" 5056 st "DENABLE : std_logic := '0'" 5057 ) 5058 ) 5059 *159 (Net 5064 st "DENABLE : std_logic := '0' 5065 " 5066 ) 5067 ) 5068 *158 (Net 5060 5069 uid 3876,0 5061 5070 decl (Decl … … 5071 5080 ) 5072 5081 xt "39000,31800,53500,32600" 5073 st "SRIN : std_logic" 5074 ) 5075 ) 5076 *160 (Net 5082 st "SRIN : std_logic 5083 " 5084 ) 5085 ) 5086 *159 (Net 5077 5087 uid 3878,0 5078 5088 decl (Decl … … 5088 5098 ) 5089 5099 xt "39000,24600,53500,25400" 5090 st "EE_CS : std_logic" 5091 ) 5092 ) 5093 *161 (Net 5100 st "EE_CS : std_logic 5101 " 5102 ) 5103 ) 5104 *160 (Net 5094 5105 uid 3880,0 5095 5106 decl (Decl … … 5107 5118 ) 5108 5119 xt "39000,25400,74000,26200" 5109 st "LED : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')" 5110 ) 5111 ) 5112 *162 (PortIoOut 5120 st "LED : std_logic_vector( 2 DOWNTO 0 ) := (others => '1') 5121 " 5122 ) 5123 ) 5124 *161 (PortIoOut 5113 5125 uid 3995,0 5114 5126 shape (CompositeShape … … 5155 5167 ) 5156 5168 ) 5157 *16 3(PortIoOut5169 *162 (PortIoOut 5158 5170 uid 4001,0 5159 5171 shape (CompositeShape … … 5200 5212 ) 5201 5213 ) 5202 *16 4(PortIoOut5214 *163 (PortIoOut 5203 5215 uid 4007,0 5204 5216 shape (CompositeShape … … 5245 5257 ) 5246 5258 ) 5247 *16 5(PortIoOut5259 *164 (PortIoOut 5248 5260 uid 4013,0 5249 5261 shape (CompositeShape … … 5290 5302 ) 5291 5303 ) 5292 *16 6(PortIoOut5304 *165 (PortIoOut 5293 5305 uid 4916,0 5294 5306 shape (CompositeShape … … 5334 5346 ) 5335 5347 ) 5336 *16 7(Net5348 *166 (Net 5337 5349 uid 5320,0 5338 5350 decl (Decl … … 5350 5362 ) 5351 5363 xt "39000,23000,74000,23800" 5352 st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 5353 ) 5354 ) 5355 *168 (PortIoIn 5364 st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 5365 " 5366 ) 5367 ) 5368 *167 (PortIoIn 5356 5369 uid 5650,0 5357 5370 shape (CompositeShape … … 5366 5379 sl 0 5367 5380 ro 270 5368 xt " -30000,88625,-28500,89375"5381 xt "9000,78625,10500,79375" 5369 5382 ) 5370 5383 (Line … … 5372 5385 sl 0 5373 5386 ro 270 5374 xt " -28500,89000,-28000,89000"5375 pts [ 5376 " -28500,89000"5377 " -28000,89000"5387 xt "10500,79000,11000,79000" 5388 pts [ 5389 "10500,79000" 5390 "11000,79000" 5378 5391 ] 5379 5392 ) … … 5390 5403 va (VaSet 5391 5404 ) 5392 xt " -35500,88500,-31000,89500"5405 xt "3500,78500,8000,79500" 5393 5406 st "TEST_TRG" 5394 5407 ju 2 5395 blo " -31000,89300"5408 blo "8000,79300" 5396 5409 tm "WireNameMgr" 5397 5410 ) 5398 5411 ) 5399 5412 ) 5400 *16 9(Net5413 *168 (Net 5401 5414 uid 5662,0 5402 5415 decl (Decl … … 5412 5425 ) 5413 5426 xt "39000,11800,53500,12600" 5414 st "TEST_TRG : std_logic" 5415 ) 5416 ) 5417 *170 (Net 5427 st "TEST_TRG : std_logic 5428 " 5429 ) 5430 ) 5431 *169 (Net 5418 5432 uid 6138,0 5419 5433 decl (Decl … … 5429 5443 ) 5430 5444 xt "39000,46400,57000,47200" 5431 st "SIGNAL TRG_OR : std_logic" 5432 ) 5433 ) 5434 *171 (SaComponent 5435 uid 6250,0 5436 optionalChildren [ 5437 *172 (CptPort 5438 uid 6235,0 5439 ps "OnEdgeStrategy" 5440 shape (Triangle 5441 uid 6236,0 5442 ro 90 5443 va (VaSet 5444 vasetType 1 5445 fg "0,65535,0" 5446 ) 5447 xt "-11750,87625,-11000,88375" 5448 ) 5449 tg (CPTG 5450 uid 6237,0 5451 ps "CptPortTextPlaceStrategy" 5452 stg "VerticalLayoutStrategy" 5453 f (Text 5454 uid 6238,0 5455 va (VaSet 5456 ) 5457 xt "-10000,87500,-8700,88500" 5458 st "clk" 5459 blo "-10000,88300" 5460 ) 5461 ) 5462 thePort (LogicalPort 5463 decl (Decl 5464 n "clk" 5465 t "STD_LOGIC" 5466 preAdd 0 5467 posAdd 0 5468 o 1 5469 suid 1,0 5470 ) 5471 ) 5472 ) 5473 *173 (CptPort 5474 uid 6239,0 5475 ps "OnEdgeStrategy" 5476 shape (Triangle 5477 uid 6240,0 5478 ro 90 5479 va (VaSet 5480 vasetType 1 5481 fg "0,65535,0" 5482 ) 5483 xt "-11750,88625,-11000,89375" 5484 ) 5485 tg (CPTG 5486 uid 6241,0 5487 ps "CptPortTextPlaceStrategy" 5488 stg "VerticalLayoutStrategy" 5489 f (Text 5490 uid 6242,0 5491 va (VaSet 5492 ) 5493 xt "-10000,88500,-5800,89500" 5494 st "trigger_in" 5495 blo "-10000,89300" 5496 ) 5497 ) 5498 thePort (LogicalPort 5499 decl (Decl 5500 n "trigger_in" 5501 t "STD_LOGIC" 5502 prec "-- rst : in STD_LOGIC;" 5503 preAdd 0 5504 posAdd 0 5505 o 2 5506 suid 2,0 5507 ) 5508 ) 5509 ) 5510 *174 (CptPort 5511 uid 6243,0 5512 ps "OnEdgeStrategy" 5513 shape (Triangle 5514 uid 6244,0 5515 ro 90 5516 va (VaSet 5517 vasetType 1 5518 fg "0,65535,0" 5519 ) 5520 xt "1000,88625,1750,89375" 5521 ) 5522 tg (CPTG 5523 uid 6245,0 5524 ps "CptPortTextPlaceStrategy" 5525 stg "RightVerticalLayoutStrategy" 5526 f (Text 5527 uid 6246,0 5528 va (VaSet 5529 ) 5530 xt "-4600,88500,0,89500" 5531 st "trigger_out" 5532 ju 2 5533 blo "0,89300" 5534 ) 5535 ) 5536 thePort (LogicalPort 5537 m 1 5538 decl (Decl 5539 n "trigger_out" 5540 t "STD_LOGIC" 5541 preAdd 0 5542 posAdd 0 5543 o 3 5544 suid 3,0 5545 i "'0'" 5546 ) 5547 ) 5548 ) 5549 ] 5550 shape (Rectangle 5551 uid 6251,0 5552 va (VaSet 5553 vasetType 1 5554 fg "0,65535,0" 5555 lineColor "0,32896,0" 5556 lineWidth 2 5557 ) 5558 xt "-11000,87000,1000,92000" 5559 ) 5560 oxt "25000,13000,37000,18000" 5561 ttg (MlTextGroup 5562 uid 6252,0 5563 ps "CenterOffsetStrategy" 5564 stg "VerticalLayoutStrategy" 5565 textVec [ 5566 *175 (Text 5567 uid 6253,0 5568 va (VaSet 5569 font "Arial,8,1" 5570 ) 5571 xt "-10800,92000,-4200,93000" 5572 st "FACT_FAD_LIB" 5573 blo "-10800,92800" 5574 tm "BdLibraryNameMgr" 5575 ) 5576 *176 (Text 5577 uid 6254,0 5578 va (VaSet 5579 font "Arial,8,1" 5580 ) 5581 xt "-10800,93000,-6400,94000" 5582 st "debouncer" 5583 blo "-10800,93800" 5584 tm "CptNameMgr" 5585 ) 5586 *177 (Text 5587 uid 6255,0 5588 va (VaSet 5589 font "Arial,8,1" 5590 ) 5591 xt "-10800,94000,-5400,95000" 5592 st "I_debouncer" 5593 blo "-10800,94800" 5594 tm "InstanceNameMgr" 5595 ) 5596 ] 5597 ) 5598 ga (GenericAssociation 5599 uid 6256,0 5600 ps "EdgeToEdgeStrategy" 5601 matrix (Matrix 5602 uid 6257,0 5603 text (MLText 5604 uid 6258,0 5605 va (VaSet 5606 font "Courier New,8,0" 5607 ) 5608 xt "-11000,86200,4000,87000" 5609 st "WIDTH = 17 ( INTEGER ) " 5610 ) 5611 header "" 5612 ) 5613 elements [ 5614 (GiElement 5615 name "WIDTH" 5616 type "INTEGER" 5617 value "17" 5618 ) 5619 ] 5620 ) 5621 viewicon (ZoomableIcon 5622 uid 6259,0 5623 sl 0 5624 va (VaSet 5625 vasetType 1 5626 fg "49152,49152,49152" 5627 ) 5628 xt "-10750,90250,-9250,91750" 5629 iconName "VhdlFileViewIcon.png" 5630 iconMaskName "VhdlFileViewIcon.msk" 5631 ftype 10 5632 ) 5633 ordering 1 5634 viewiconposition 0 5635 portVis (PortSigDisplay 5636 ) 5637 archFileType "UNKNOWN" 5638 ) 5639 *178 (Net 5640 uid 6278,0 5641 decl (Decl 5642 n "trigger_out" 5643 t "STD_LOGIC" 5644 preAdd 0 5645 posAdd 0 5646 o 60 5647 suid 147,0 5648 i "'0'" 5649 ) 5650 declText (MLText 5651 uid 6279,0 5652 va (VaSet 5653 font "Courier New,8,0" 5654 ) 5655 xt "39000,52000,71500,52800" 5656 st "SIGNAL trigger_out : STD_LOGIC := '0'" 5657 ) 5658 ) 5659 *179 (Net 5660 uid 6326,0 5661 decl (Decl 5662 n "not_TEST_TRG" 5663 t "STD_LOGIC" 5664 o 58 5665 suid 148,0 5666 ) 5667 declText (MLText 5668 uid 6327,0 5669 va (VaSet 5670 font "Courier New,8,0" 5671 ) 5672 xt "39000,50400,57000,51200" 5673 st "SIGNAL not_TEST_TRG : STD_LOGIC" 5674 ) 5675 ) 5676 *180 (MWC 5677 uid 6539,0 5678 optionalChildren [ 5679 *181 (CptPort 5680 uid 6526,0 5681 optionalChildren [ 5682 *182 (Line 5683 uid 6530,0 5684 layer 5 5685 sl 0 5686 va (VaSet 5687 vasetType 3 5688 ) 5689 xt "-22000,89000,-20999,89000" 5690 pts [ 5691 "-22000,89000" 5692 "-20999,89000" 5693 ] 5694 ) 5695 ] 5696 ps "OnEdgeStrategy" 5697 shape (Triangle 5698 uid 6527,0 5699 ro 90 5700 va (VaSet 5701 vasetType 1 5702 isHidden 1 5703 fg "0,65535,65535" 5704 ) 5705 xt "-22750,88625,-22000,89375" 5706 ) 5707 tg (CPTG 5708 uid 6528,0 5709 ps "CptPortTextPlaceStrategy" 5710 stg "VerticalLayoutStrategy" 5711 f (Text 5712 uid 6529,0 5713 sl 0 5714 va (VaSet 5715 isHidden 1 5716 font "arial,8,0" 5717 ) 5718 xt "-25000,88500,-23600,89500" 5719 st "din" 5720 blo "-25000,89300" 5721 ) 5722 s (Text 5723 uid 6548,0 5724 sl 0 5725 va (VaSet 5726 font "arial,8,0" 5727 ) 5728 xt "-25000,89500,-25000,89500" 5729 blo "-25000,89500" 5730 ) 5731 ) 5732 thePort (LogicalPort 5733 decl (Decl 5734 n "din" 5735 t "std_logic" 5736 o 11 5737 suid 1,0 5738 ) 5739 ) 5740 ) 5741 *183 (CptPort 5742 uid 6531,0 5743 optionalChildren [ 5744 *184 (Line 5745 uid 6535,0 5746 layer 5 5747 sl 0 5748 va (VaSet 5749 vasetType 3 5750 ) 5751 xt "-17249,89000,-17000,89000" 5752 pts [ 5753 "-17000,89000" 5754 "-17249,89000" 5755 ] 5756 ) 5757 *185 (Circle 5758 uid 6536,0 5759 va (VaSet 5760 vasetType 1 5761 fg "65535,65535,65535" 5762 lineColor "26368,26368,26368" 5763 ) 5764 xt "-17999,88625,-17249,89375" 5765 radius 375 5766 ) 5767 ] 5768 ps "OnEdgeStrategy" 5769 shape (Triangle 5770 uid 6532,0 5771 ro 90 5772 va (VaSet 5773 vasetType 1 5774 isHidden 1 5775 fg "0,65535,65535" 5776 ) 5777 xt "-17000,88625,-16250,89375" 5778 ) 5779 tg (CPTG 5780 uid 6533,0 5781 ps "CptPortTextPlaceStrategy" 5782 stg "RightVerticalLayoutStrategy" 5783 f (Text 5784 uid 6534,0 5785 sl 0 5786 va (VaSet 5787 isHidden 1 5788 font "arial,8,0" 5789 ) 5790 xt "-15050,88500,-13250,89500" 5791 st "dout" 5792 ju 2 5793 blo "-13250,89300" 5794 ) 5795 s (Text 5796 uid 6549,0 5797 sl 0 5798 va (VaSet 5799 font "arial,8,0" 5800 ) 5801 xt "-13250,89500,-13250,89500" 5802 ju 2 5803 blo "-13250,89500" 5804 ) 5805 ) 5806 thePort (LogicalPort 5807 m 1 5808 decl (Decl 5809 n "dout" 5810 t "STD_LOGIC" 5811 o 58 5812 suid 2,0 5813 ) 5814 ) 5815 ) 5816 *186 (CommentGraphic 5817 uid 6537,0 5818 shape (CustomPolygon 5819 pts [ 5820 "-21000,87000" 5821 "-18000,89000" 5822 "-21000,91000" 5823 "-21000,87000" 5824 ] 5825 uid 6538,0 5826 layer 0 5827 sl 0 5828 va (VaSet 5829 vasetType 1 5830 fg "0,65535,65535" 5831 bg "0,65535,65535" 5832 lineColor "26368,26368,26368" 5833 ) 5834 xt "-21000,87000,-18000,91000" 5835 ) 5836 oxt "7000,6000,10000,10000" 5837 ) 5838 ] 5839 shape (Rectangle 5840 uid 6540,0 5841 va (VaSet 5842 vasetType 1 5843 transparent 1 5844 fg "0,65535,0" 5845 lineColor "65535,65535,65535" 5846 lineWidth -1 5847 ) 5848 xt "-22000,87000,-17000,91000" 5849 fos 1 5850 ) 5851 showPorts 0 5852 oxt "6000,6000,11000,10000" 5853 ttg (MlTextGroup 5854 uid 6541,0 5855 ps "CenterOffsetStrategy" 5856 stg "VerticalLayoutStrategy" 5857 textVec [ 5858 *187 (Text 5859 uid 6542,0 5860 va (VaSet 5861 isHidden 1 5862 font "arial,8,0" 5863 ) 5864 xt "-19650,89100,-14850,90100" 5865 st "moduleware" 5866 blo "-19650,89900" 5867 ) 5868 *188 (Text 5869 uid 6543,0 5870 va (VaSet 5871 font "arial,8,0" 5872 ) 5873 xt "-19650,90100,-18350,91100" 5874 st "inv" 5875 blo "-19650,90900" 5876 ) 5877 *189 (Text 5878 uid 6544,0 5879 va (VaSet 5880 font "arial,8,0" 5881 ) 5882 xt "-19650,91100,-18650,92100" 5883 st "I1" 5884 blo "-19650,91900" 5885 tm "InstanceNameMgr" 5886 ) 5887 ] 5888 ) 5889 ga (GenericAssociation 5890 uid 6545,0 5891 ps "EdgeToEdgeStrategy" 5892 matrix (Matrix 5893 uid 6546,0 5894 text (MLText 5895 uid 6547,0 5896 va (VaSet 5897 font "arial,8,0" 5898 ) 5899 xt "-25000,68400,-25000,68400" 5900 ) 5901 header "" 5902 ) 5903 elements [ 5904 ] 5905 ) 5906 sed 1 5907 awe 1 5908 portVis (PortSigDisplay 5909 disp 1 5910 sN 0 5911 sTC 0 5912 selT 0 5913 ) 5914 prms (Property 5915 pclass "params" 5916 pname "params" 5917 ptn "String" 5918 ) 5919 visOptions (mwParamsVisibilityOptions 5920 ) 5921 ) 5922 *190 (MWC 5445 st "SIGNAL TRG_OR : std_logic 5446 " 5447 ) 5448 ) 5449 *170 (MWC 5923 5450 uid 6586,0 5924 5451 optionalChildren [ 5925 *1 91 (CptPort5452 *171 (CptPort 5926 5453 uid 6550,0 5927 5454 optionalChildren [ 5928 *1 92 (Line5455 *172 (Line 5929 5456 uid 6554,0 5930 5457 layer 5 … … 5970 5497 decl (Decl 5971 5498 n "din1" 5972 t "STD_LOGIC" 5973 preAdd 0 5974 posAdd 0 5975 o 60 5499 t "std_logic" 5500 o 11 5976 5501 suid 1,0 5977 i "'0'" 5978 ) 5979 ) 5980 ) 5981 *193 (CptPort 5502 ) 5503 ) 5504 ) 5505 *173 (CptPort 5982 5506 uid 6555,0 5983 5507 optionalChildren [ 5984 *1 94 (Property5508 *174 (Property 5985 5509 uid 6559,0 5986 5510 pclass "_MW_GEOM_" … … 5988 5512 ptn "String" 5989 5513 ) 5990 *1 95 (Line5514 *175 (Line 5991 5515 uid 6560,0 5992 5516 layer 5 … … 6040 5564 ) 6041 5565 ) 6042 *1 96 (CptPort5566 *176 (CptPort 6043 5567 uid 6561,0 6044 5568 optionalChildren [ 6045 *1 97 (Line5569 *177 (Line 6046 5570 uid 6565,0 6047 5571 layer 5 … … 6093 5617 ) 6094 5618 ) 6095 *1 98 (CommentGraphic5619 *178 (CommentGraphic 6096 5620 uid 6566,0 6097 5621 shape (Arc2D … … 6114 5638 oxt "7000,6003,11000,8000" 6115 5639 ) 6116 *1 99 (CommentGraphic5640 *179 (CommentGraphic 6117 5641 uid 6568,0 6118 5642 shape (Arc2D … … 6135 5659 oxt "6996,8005,11000,10000" 6136 5660 ) 6137 * 200 (Grouping5661 *180 (Grouping 6138 5662 uid 6570,0 6139 5663 optionalChildren [ 6140 * 201 (CommentGraphic5664 *181 (CommentGraphic 6141 5665 uid 6572,0 6142 5666 optionalChildren [ 6143 * 202 (Property5667 *182 (Property 6144 5668 uid 6574,0 6145 5669 pclass "_MW_GEOM_" … … 6172 5696 oxt "7000,6000,11000,9998" 6173 5697 ) 6174 * 203 (CommentGraphic5698 *183 (CommentGraphic 6175 5699 uid 6575,0 6176 5700 optionalChildren [ 6177 * 204 (Property5701 *184 (Property 6178 5702 uid 6577,0 6179 5703 pclass "_MW_GEOM_" … … 6217 5741 oxt "7000,6000,11000,10000" 6218 5742 ) 6219 * 205 (CommentGraphic5743 *185 (CommentGraphic 6220 5744 uid 6578,0 6221 5745 shape (PolyLine2D … … 6236 5760 oxt "11000,8000,11000,8000" 6237 5761 ) 6238 * 206 (CommentGraphic5762 *186 (CommentGraphic 6239 5763 uid 6580,0 6240 5764 optionalChildren [ 6241 * 207 (Property5765 *187 (Property 6242 5766 uid 6582,0 6243 5767 pclass "_MW_GEOM_" … … 6263 5787 oxt "7000,6000,7000,6000" 6264 5788 ) 6265 * 208 (CommentGraphic5789 *188 (CommentGraphic 6266 5790 uid 6583,0 6267 5791 optionalChildren [ 6268 * 209 (Property5792 *189 (Property 6269 5793 uid 6585,0 6270 5794 pclass "_MW_GEOM_" … … 6309 5833 stg "VerticalLayoutStrategy" 6310 5834 textVec [ 6311 * 210 (Text5835 *190 (Text 6312 5836 uid 6589,0 6313 5837 va (VaSet … … 6319 5843 blo "15500,77300" 6320 5844 ) 6321 * 211 (Text5845 *191 (Text 6322 5846 uid 6590,0 6323 5847 va (VaSet … … 6328 5852 blo "15500,78300" 6329 5853 ) 6330 * 212 (Text5854 *192 (Text 6331 5855 uid 6591,0 6332 5856 va (VaSet … … 6373 5897 ) 6374 5898 ) 6375 * 213 (PortIoIn5899 *193 (PortIoIn 6376 5900 uid 6781,0 6377 5901 shape (CompositeShape … … 6418 5942 ) 6419 5943 ) 6420 * 214 (Net5944 *194 (Net 6421 5945 uid 6793,0 6422 5946 decl (Decl … … 6433 5957 ) 6434 5958 xt "39000,11000,63500,11800" 6435 st "D_PLLLCK : std_logic_vector(3 DOWNTO 0)" 6436 ) 6437 ) 6438 *215 (PortIoOut 5959 st "D_PLLLCK : std_logic_vector(3 DOWNTO 0) 5960 " 5961 ) 5962 ) 5963 *195 (PortIoOut 6439 5964 uid 6874,0 6440 5965 shape (CompositeShape … … 6480 6005 ) 6481 6006 ) 6482 * 216 (Net6007 *196 (Net 6483 6008 uid 6886,0 6484 6009 decl (Decl … … 6496 6021 ) 6497 6022 xt "39000,23800,74000,24600" 6498 st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0')" 6499 ) 6500 ) 6501 *217 (HdlText 6023 st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0') 6024 " 6025 ) 6026 ) 6027 *197 (HdlText 6502 6028 uid 6888,0 6503 6029 optionalChildren [ 6504 * 218 (EmbeddedText6030 *198 (EmbeddedText 6505 6031 uid 6894,0 6506 6032 commentText (CommentText … … 6550 6076 stg "VerticalLayoutStrategy" 6551 6077 textVec [ 6552 * 219 (Text6078 *199 (Text 6553 6079 uid 6891,0 6554 6080 va (VaSet … … 6560 6086 tm "HdlTextNameMgr" 6561 6087 ) 6562 *2 20 (Text6088 *200 (Text 6563 6089 uid 6892,0 6564 6090 va (VaSet … … 6586 6112 viewiconposition 0 6587 6113 ) 6588 *2 21 (HdlText6114 *201 (HdlText 6589 6115 uid 7092,0 6590 6116 optionalChildren [ 6591 *2 22 (EmbeddedText6117 *202 (EmbeddedText 6592 6118 uid 7098,0 6593 6119 commentText (CommentText … … 6602 6128 lineWidth 2 6603 6129 ) 6604 xt "2 7000,137000,45000,145000"6130 xt "26000,137000,46000,143000" 6605 6131 ) 6606 6132 oxt "0,0,18000,5000" … … 6609 6135 va (VaSet 6610 6136 ) 6611 xt "2 7200,137200,39400,142200"6137 xt "26200,137200,40000,141200" 6612 6138 st " 6613 6139 -- eb2 8 6614 A1_T(0) <= dummy; 6615 A1_T(1) <= RSRLOAD; 6616 A1_T(2) <= D0_SROUT; 6617 A1_T(3) <= D1_SROUT; 6140 A1_T(3 downto 0) <= drs_channel_id; 6141 D_A <= drs_channel_id; 6142 A1_T(4) <= TRG_OR; 6618 6143 " 6619 6144 tm "HdlTextMgr" 6620 6145 wrapOption 3 6621 visibleHeight 80006622 visibleWidth 180006146 visibleHeight 6000 6147 visibleWidth 20000 6623 6148 ) 6624 6149 ) … … 6641 6166 stg "VerticalLayoutStrategy" 6642 6167 textVec [ 6643 *2 23 (Text6168 *203 (Text 6644 6169 uid 7095,0 6645 6170 va (VaSet … … 6651 6176 tm "HdlTextNameMgr" 6652 6177 ) 6653 *2 24 (Text6178 *204 (Text 6654 6179 uid 7096,0 6655 6180 va (VaSet … … 6677 6202 viewiconposition 0 6678 6203 ) 6679 *2 25 (PortIoOut6204 *205 (PortIoOut 6680 6205 uid 7138,0 6681 6206 shape (CompositeShape … … 6721 6246 ) 6722 6247 ) 6723 *2 26 (Net6248 *206 (Net 6724 6249 uid 7150,0 6725 6250 decl (Decl 6726 6251 n "A1_T" 6727 6252 t "std_logic_vector" 6728 b "( 3DOWNTO 0)"6253 b "(7 DOWNTO 0)" 6729 6254 o 15 6730 6255 suid 155,0 6256 i "(OTHERS => '0')" 6731 6257 ) 6732 6258 declText (MLText … … 6735 6261 font "Courier New,8,0" 6736 6262 ) 6737 xt "39000,15000,63500,15800" 6738 st "A1_T : std_logic_vector(3 DOWNTO 0)" 6739 ) 6740 ) 6741 *227 (Net 6263 xt "39000,15000,74000,15800" 6264 st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 6265 " 6266 ) 6267 ) 6268 *207 (Net 6742 6269 uid 7485,0 6743 6270 decl (Decl 6744 6271 n "dummy" 6745 6272 t "std_logic" 6746 o 606273 o 58 6747 6274 suid 157,0 6748 6275 ) … … 6752 6279 font "Courier New,8,0" 6753 6280 ) 6754 xt "39000,49600,57000,50400" 6755 st "SIGNAL dummy : std_logic" 6756 ) 6757 ) 6758 *228 (MWC 6281 xt "39000,50400,57000,51200" 6282 st "SIGNAL dummy : std_logic 6283 " 6284 ) 6285 ) 6286 *208 (MWC 6759 6287 uid 7652,0 6760 6288 optionalChildren [ 6761 *2 29 (CptPort6289 *209 (CptPort 6762 6290 uid 7632,0 6763 6291 optionalChildren [ 6764 *2 30 (Line6292 *210 (Line 6765 6293 uid 7636,0 6766 6294 layer 5 … … 6816 6344 n "s" 6817 6345 t "std_logic" 6818 o 606346 o 58 6819 6347 suid 1,0 6820 6348 ) 6821 6349 ) 6822 6350 ) 6823 *2 31 (CptPort6351 *211 (CptPort 6824 6352 uid 7637,0 6825 6353 optionalChildren [ 6826 *2 32 (Line6354 *212 (Line 6827 6355 uid 7641,0 6828 6356 layer 5 … … 6886 6414 ) 6887 6415 ) 6888 *2 33 (CommentGraphic6416 *213 (CommentGraphic 6889 6417 uid 7642,0 6890 6418 shape (PolyLine2D … … 6907 6435 oxt "6000,6000,7000,7000" 6908 6436 ) 6909 *2 34 (CommentGraphic6437 *214 (CommentGraphic 6910 6438 uid 7644,0 6911 6439 shape (PolyLine2D … … 6928 6456 oxt "6000,7000,7000,8000" 6929 6457 ) 6930 *2 35 (CommentGraphic6458 *215 (CommentGraphic 6931 6459 uid 7646,0 6932 6460 shape (PolyLine2D … … 6949 6477 oxt "6988,7329,7988,7329" 6950 6478 ) 6951 *2 36 (CommentGraphic6479 *216 (CommentGraphic 6952 6480 uid 7648,0 6953 6481 shape (PolyLine2D … … 6968 6496 oxt "8000,7000,9000,7000" 6969 6497 ) 6970 *2 37 (CommentGraphic6498 *217 (CommentGraphic 6971 6499 uid 7650,0 6972 6500 shape (PolyLine2D … … 7009 6537 stg "VerticalLayoutStrategy" 7010 6538 textVec [ 7011 *2 38 (Text6539 *218 (Text 7012 6540 uid 7655,0 7013 6541 va (VaSet … … 7019 6547 blo "90350,83900" 7020 6548 ) 7021 *2 39 (Text6549 *219 (Text 7022 6550 uid 7656,0 7023 6551 va (VaSet … … 7028 6556 blo "90350,84900" 7029 6557 ) 7030 *2 40 (Text6558 *220 (Text 7031 6559 uid 7657,0 7032 6560 va (VaSet … … 7073 6601 ) 7074 6602 ) 7075 *241 (Wire 6603 *221 (Net 6604 uid 8851,0 6605 decl (Decl 6606 n "drs_channel_id" 6607 t "std_logic_vector" 6608 b "(3 downto 0)" 6609 o 57 6610 suid 159,0 6611 i "(others => '0')" 6612 ) 6613 declText (MLText 6614 uid 8852,0 6615 va (VaSet 6616 font "Courier New,8,0" 6617 ) 6618 xt "39000,49600,77500,50400" 6619 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 6620 " 6621 ) 6622 ) 6623 *222 (Net 6624 uid 9500,0 6625 decl (Decl 6626 n "CLK_50" 6627 t "std_logic" 6628 o 51 6629 suid 163,0 6630 ) 6631 declText (MLText 6632 uid 9501,0 6633 va (VaSet 6634 font "Courier New,8,0" 6635 ) 6636 xt "39000,44800,57000,45600" 6637 st "SIGNAL CLK_50 : std_logic 6638 " 6639 ) 6640 ) 6641 *223 (Wire 7076 6642 uid 245,0 7077 6643 shape (OrthoPolyLine … … 7110 6676 ) 7111 6677 ) 7112 on & 707113 ) 7114 *2 42(Wire6678 on &69 6679 ) 6680 *224 (Wire 7115 6681 uid 277,0 7116 6682 shape (OrthoPolyLine … … 7150 6716 on &53 7151 6717 ) 7152 *2 43(Wire6718 *225 (Wire 7153 6719 uid 285,0 7154 6720 shape (OrthoPolyLine … … 7188 6754 on &54 7189 6755 ) 7190 *2 44(Wire6756 *226 (Wire 7191 6757 uid 362,0 7192 6758 shape (OrthoPolyLine … … 7201 6767 ] 7202 6768 ) 7203 start &7 86769 start &77 7204 6770 end &16 7205 6771 sat 32 … … 7224 6790 ) 7225 6791 ) 7226 on &7 97227 ) 7228 *2 45(Wire6792 on &78 6793 ) 6794 *227 (Wire 7229 6795 uid 418,0 7230 6796 shape (OrthoPolyLine … … 7262 6828 ) 7263 6829 ) 7264 on &13 17265 ) 7266 *2 46(Wire6830 on &130 6831 ) 6832 *228 (Wire 7267 6833 uid 426,0 7268 6834 shape (OrthoPolyLine … … 7302 6868 ) 7303 6869 ) 7304 on &12 97305 ) 7306 *2 47(Wire6870 on &128 6871 ) 6872 *229 (Wire 7307 6873 uid 434,0 7308 6874 shape (OrthoPolyLine … … 7340 6906 ) 7341 6907 ) 7342 on &13 57343 ) 7344 *2 48(Wire6908 on &134 6909 ) 6910 *230 (Wire 7345 6911 uid 442,0 7346 6912 shape (OrthoPolyLine … … 7380 6946 ) 7381 6947 ) 7382 on &1 307383 ) 7384 *2 49(Wire6948 on &129 6949 ) 6950 *231 (Wire 7385 6951 uid 450,0 7386 6952 shape (OrthoPolyLine … … 7418 6984 ) 7419 6985 ) 7420 on &13 47421 ) 7422 *2 50(Wire6986 on &133 6987 ) 6988 *232 (Wire 7423 6989 uid 458,0 7424 6990 shape (OrthoPolyLine … … 7456 7022 ) 7457 7023 ) 7458 on &13 27459 ) 7460 *2 51(Wire7024 on &131 7025 ) 7026 *233 (Wire 7461 7027 uid 466,0 7462 7028 shape (OrthoPolyLine … … 7494 7060 ) 7495 7061 ) 7496 on &13 37497 ) 7498 *2 52(Wire7062 on &132 7063 ) 7064 *234 (Wire 7499 7065 uid 1467,0 7500 7066 shape (OrthoPolyLine … … 7509 7075 ] 7510 7076 ) 7511 start &8 27077 start &81 7512 7078 end &28 7513 7079 sat 2 … … 7532 7098 on &62 7533 7099 ) 7534 *2 53(Wire7100 *235 (Wire 7535 7101 uid 1730,0 7536 7102 shape (OrthoPolyLine … … 7546 7112 ] 7547 7113 ) 7548 start & 807114 start &79 7549 7115 end &29 7550 7116 sat 32 … … 7570 7136 ) 7571 7137 ) 7572 on &8 17573 ) 7574 *2 54(Wire7138 on &80 7139 ) 7140 *236 (Wire 7575 7141 uid 1833,0 7576 7142 shape (OrthoPolyLine … … 7580 7146 lineWidth 2 7581 7147 ) 7582 xt " 21000,109000,51250,109000"7583 pts [ 7584 " 51250,109000"7585 " 21000,109000"7586 ] 7587 ) 7588 start & 307589 end &1 107590 sat 327148 xt "6000,134000,31000,134000" 7149 pts [ 7150 "31000,134000" 7151 "6000,134000" 7152 ] 7153 ) 7154 start &201 7155 end &109 7156 sat 2 7591 7157 eat 32 7592 7158 sty 1 … … 7604 7170 isHidden 1 7605 7171 ) 7606 xt " 22000,108000,23900,109000"7172 xt "7000,133000,8900,134000" 7607 7173 st "D_A" 7608 blo " 22000,108800"7174 blo "7000,133800" 7609 7175 tm "WireNameMgr" 7610 7176 ) 7611 7177 ) 7612 on &11 17613 ) 7614 *2 55(Wire7178 on &110 7179 ) 7180 *237 (Wire 7615 7181 uid 1841,0 7616 7182 shape (OrthoPolyLine … … 7626 7192 ) 7627 7193 start &31 7628 end &11 27194 end &111 7629 7195 sat 32 7630 7196 eat 32 … … 7648 7214 ) 7649 7215 ) 7650 on &11 37651 ) 7652 *2 56(Wire7216 on &112 7217 ) 7218 *238 (Wire 7653 7219 uid 1865,0 7654 7220 shape (OrthoPolyLine … … 7663 7229 ] 7664 7230 ) 7665 start &10 27231 start &101 7666 7232 end &32 7667 7233 sat 32 … … 7686 7252 ) 7687 7253 ) 7688 on &10 67689 ) 7690 *2 57(Wire7254 on &105 7255 ) 7256 *239 (Wire 7691 7257 uid 1873,0 7692 7258 shape (OrthoPolyLine … … 7701 7267 ] 7702 7268 ) 7703 start &10 37269 start &102 7704 7270 end &33 7705 7271 sat 32 … … 7724 7290 ) 7725 7291 ) 7726 on &10 77727 ) 7728 *2 58(Wire7292 on &106 7293 ) 7294 *240 (Wire 7729 7295 uid 1881,0 7730 7296 shape (OrthoPolyLine … … 7739 7305 ] 7740 7306 ) 7741 start &10 47307 start &103 7742 7308 end &34 7743 7309 sat 32 … … 7762 7328 ) 7763 7329 ) 7764 on &10 87765 ) 7766 *2 59(Wire7330 on &107 7331 ) 7332 *241 (Wire 7767 7333 uid 1889,0 7768 7334 shape (OrthoPolyLine … … 7777 7343 ] 7778 7344 ) 7779 start &10 57345 start &104 7780 7346 end &35 7781 7347 sat 32 … … 7800 7366 ) 7801 7367 ) 7802 on &109 7803 ) 7804 *260 (Wire 7805 uid 2269,0 7806 shape (OrthoPolyLine 7807 uid 2270,0 7808 va (VaSet 7809 vasetType 3 7810 ) 7811 xt "-15000,69000,51250,88000" 7812 pts [ 7813 "51250,69000" 7814 "-15000,69000" 7815 "-15000,88000" 7816 "-11750,88000" 7817 ] 7818 ) 7819 start &26 7820 end &172 7821 sat 32 7822 eat 32 7823 stc 0 7824 st 0 7825 sf 1 7826 si 0 7827 tg (WTG 7828 uid 2273,0 7829 ps "ConnStartEndStrategy" 7830 stg "STSignalDisplayStrategy" 7831 f (Text 7832 uid 2274,0 7833 va (VaSet 7834 isHidden 1 7835 ) 7836 xt "50250,68000,53350,69000" 7837 st "CLK_50" 7838 blo "50250,68800" 7839 tm "WireNameMgr" 7840 ) 7841 ) 7842 on &63 7843 ) 7844 *261 (Wire 7368 on &108 7369 ) 7370 *242 (Wire 7845 7371 uid 2409,0 7846 7372 shape (OrthoPolyLine … … 7856 7382 ) 7857 7383 start &36 7858 end &6 57384 end &64 7859 7385 sat 32 7860 7386 eat 32 … … 7878 7404 ) 7879 7405 ) 7880 on &6 47881 ) 7882 *2 62(Wire7406 on &63 7407 ) 7408 *243 (Wire 7883 7409 uid 2423,0 7884 7410 shape (OrthoPolyLine … … 7894 7420 ) 7895 7421 start &37 7896 end &9 47422 end &93 7897 7423 sat 32 7898 7424 eat 1 … … 7916 7442 ) 7917 7443 ) 7918 on &6 67919 ) 7920 *2 63(Wire7444 on &65 7445 ) 7446 *244 (Wire 7921 7447 uid 3009,0 7922 7448 shape (OrthoPolyLine … … 7932 7458 ) 7933 7459 start &39 7934 end &12 77460 end &126 7935 7461 sat 32 7936 7462 eat 32 … … 7954 7480 ) 7955 7481 ) 7956 on &12 87957 ) 7958 *2 64(Wire7482 on &127 7483 ) 7484 *245 (Wire 7959 7485 uid 3015,0 7960 7486 shape (OrthoPolyLine … … 7970 7496 ) 7971 7497 start &41 7972 end &13 67498 end &135 7973 7499 sat 32 7974 7500 eat 32 … … 7992 7518 ) 7993 7519 ) 7994 on &13 97995 ) 7996 *2 65(Wire7520 on &138 7521 ) 7522 *246 (Wire 7997 7523 uid 3021,0 7998 7524 shape (OrthoPolyLine … … 8009 7535 ) 8010 7536 start &40 8011 end &11 57537 end &114 8012 7538 sat 32 8013 7539 eat 1 … … 8030 7556 ) 8031 7557 ) 8032 on &6 78033 ) 8034 *2 66(Wire7558 on &66 7559 ) 7560 *247 (Wire 8035 7561 uid 3027,0 8036 7562 shape (OrthoPolyLine … … 8045 7571 ] 8046 7572 ) 8047 start &2 318048 end &11 47573 start &211 7574 end &113 8049 7575 ss 0 8050 7576 sat 32 … … 8069 7595 ) 8070 7596 ) 8071 on &6 88072 ) 8073 *2 67(Wire7597 on &67 7598 ) 7599 *248 (Wire 8074 7600 uid 3218,0 8075 7601 shape (OrthoPolyLine … … 8085 7611 ) 8086 7612 start &47 8087 end &1 967613 end &176 8088 7614 sat 32 8089 7615 eat 32 … … 8107 7633 ) 8108 7634 ) 8109 on &7 18110 ) 8111 *2 68(Wire7635 on &70 7636 ) 7637 *249 (Wire 8112 7638 uid 3260,0 8113 7639 shape (OrthoPolyLine … … 8123 7649 ] 8124 7650 ) 8125 start &6 98126 end &7 27651 start &68 7652 end &71 8127 7653 sat 32 8128 7654 eat 2 … … 8147 7673 ) 8148 7674 ) 8149 on &7 68150 ) 8151 *2 69(Wire7675 on &75 7676 ) 7677 *250 (Wire 8152 7678 uid 3270,0 8153 7679 shape (OrthoPolyLine … … 8163 7689 ) 8164 7690 start &25 8165 end &7 27691 end &71 8166 7692 sat 32 8167 7693 eat 1 … … 8183 7709 ) 8184 7710 ) 8185 on &7 78186 ) 8187 *2 70(Wire7711 on &76 7712 ) 7713 *251 (Wire 8188 7714 uid 3318,0 8189 7715 shape (OrthoPolyLine … … 8199 7725 ] 8200 7726 ) 8201 start &8 68202 end &8 27727 start &85 7728 end &81 8203 7729 sat 32 8204 7730 eat 1 … … 8223 7749 ) 8224 7750 ) 8225 on & 908226 ) 8227 *2 71(Wire7751 on &89 7752 ) 7753 *252 (Wire 8228 7754 uid 3352,0 8229 7755 shape (OrthoPolyLine … … 8239 7765 ] 8240 7766 ) 8241 start &8 78242 end &8 27767 start &86 7768 end &81 8243 7769 sat 32 8244 7770 eat 1 … … 8263 7789 ) 8264 7790 ) 8265 on &9 18266 ) 8267 *2 72(Wire7791 on &90 7792 ) 7793 *253 (Wire 8268 7794 uid 3360,0 8269 7795 shape (OrthoPolyLine … … 8279 7805 ] 8280 7806 ) 8281 start &8 88282 end &8 27807 start &87 7808 end &81 8283 7809 sat 32 8284 7810 eat 1 … … 8303 7829 ) 8304 7830 ) 8305 on &9 28306 ) 8307 *2 73(Wire7831 on &91 7832 ) 7833 *254 (Wire 8308 7834 uid 3368,0 8309 7835 shape (OrthoPolyLine … … 8319 7845 ] 8320 7846 ) 8321 start &8 98322 end &8 27847 start &88 7848 end &81 8323 7849 sat 32 8324 7850 eat 1 … … 8343 7869 ) 8344 7870 ) 8345 on &9 38346 ) 8347 *2 74(Wire7871 on &92 7872 ) 7873 *255 (Wire 8348 7874 uid 3430,0 8349 7875 shape (OrthoPolyLine … … 8358 7884 ] 8359 7885 ) 8360 start &16 28361 end &9 47886 start &161 7887 end &93 8362 7888 sat 32 8363 7889 eat 2 … … 8381 7907 ) 8382 7908 ) 8383 on &9 88384 ) 8385 *2 75(Wire7909 on &97 7910 ) 7911 *256 (Wire 8386 7912 uid 3438,0 8387 7913 shape (OrthoPolyLine … … 8396 7922 ] 8397 7923 ) 8398 start &16 38399 end &9 47924 start &162 7925 end &93 8400 7926 sat 32 8401 7927 eat 2 … … 8419 7945 ) 8420 7946 ) 8421 on &9 98422 ) 8423 *2 76(Wire7947 on &98 7948 ) 7949 *257 (Wire 8424 7950 uid 3446,0 8425 7951 shape (OrthoPolyLine … … 8434 7960 ] 8435 7961 ) 8436 start &16 48437 end &9 47962 start &163 7963 end &93 8438 7964 sat 32 8439 7965 eat 2 … … 8457 7983 ) 8458 7984 ) 8459 on & 1008460 ) 8461 *2 77(Wire7985 on &99 7986 ) 7987 *258 (Wire 8462 7988 uid 3454,0 8463 7989 shape (OrthoPolyLine … … 8472 7998 ] 8473 7999 ) 8474 start &16 58475 end &9 48000 start &164 8001 end &93 8476 8002 sat 32 8477 8003 eat 2 … … 8495 8021 ) 8496 8022 ) 8497 on &10 18498 ) 8499 *2 78(Wire8023 on &100 8024 ) 8025 *259 (Wire 8500 8026 uid 3574,0 8501 8027 shape (OrthoPolyLine … … 8510 8036 ] 8511 8037 ) 8512 start &11 98513 end &11 58038 start &118 8039 end &114 8514 8040 sat 32 8515 8041 eat 2 … … 8533 8059 ) 8534 8060 ) 8535 on &12 38536 ) 8537 *2 79(Wire8061 on &122 8062 ) 8063 *260 (Wire 8538 8064 uid 3582,0 8539 8065 shape (OrthoPolyLine … … 8548 8074 ] 8549 8075 ) 8550 start &1 208551 end &11 58076 start &119 8077 end &114 8552 8078 sat 32 8553 8079 eat 2 … … 8571 8097 ) 8572 8098 ) 8573 on &12 48574 ) 8575 *2 80(Wire8099 on &123 8100 ) 8101 *261 (Wire 8576 8102 uid 3590,0 8577 8103 shape (OrthoPolyLine … … 8586 8112 ] 8587 8113 ) 8588 start &12 18589 end &11 58114 start &120 8115 end &114 8590 8116 sat 32 8591 8117 eat 2 … … 8609 8135 ) 8610 8136 ) 8611 on &12 58612 ) 8613 *2 81(Wire8137 on &124 8138 ) 8139 *262 (Wire 8614 8140 uid 3598,0 8615 8141 shape (OrthoPolyLine … … 8624 8150 ] 8625 8151 ) 8626 start &12 28627 end &11 58152 start &121 8153 end &114 8628 8154 sat 32 8629 8155 eat 2 … … 8647 8173 ) 8648 8174 ) 8649 on &12 68650 ) 8651 *2 82(Wire8175 on &125 8176 ) 8177 *263 (Wire 8652 8178 uid 3682,0 8653 8179 shape (OrthoPolyLine … … 8663 8189 ) 8664 8190 start &42 8665 end &13 88191 end &137 8666 8192 sat 32 8667 8193 eat 32 … … 8685 8211 ) 8686 8212 ) 8687 on &13 78688 ) 8689 *2 83(Wire8213 on &136 8214 ) 8215 *264 (Wire 8690 8216 uid 3778,0 8691 8217 shape (OrthoPolyLine … … 8700 8226 ] 8701 8227 ) 8702 start &14 48703 end &1 408228 start &143 8229 end &139 8704 8230 sat 32 8705 8231 eat 2 … … 8723 8249 ) 8724 8250 ) 8725 on &15 38726 ) 8727 *2 84(Wire8251 on &152 8252 ) 8253 *265 (Wire 8728 8254 uid 3786,0 8729 8255 shape (OrthoPolyLine … … 8738 8264 ] 8739 8265 ) 8740 start &14 58741 end &1 408266 start &144 8267 end &139 8742 8268 sat 32 8743 8269 eat 2 … … 8761 8287 ) 8762 8288 ) 8763 on &15 48764 ) 8765 *2 85(Wire8289 on &153 8290 ) 8291 *266 (Wire 8766 8292 uid 3794,0 8767 8293 shape (OrthoPolyLine … … 8776 8302 ] 8777 8303 ) 8778 start &14 68779 end &1 408304 start &145 8305 end &139 8780 8306 sat 32 8781 8307 eat 2 … … 8799 8325 ) 8800 8326 ) 8801 on &15 58802 ) 8803 *2 86(Wire8327 on &154 8328 ) 8329 *267 (Wire 8804 8330 uid 3802,0 8805 8331 shape (OrthoPolyLine … … 8814 8340 ] 8815 8341 ) 8816 start &14 78817 end &1 408342 start &146 8343 end &139 8818 8344 sat 32 8819 8345 eat 2 … … 8837 8363 ) 8838 8364 ) 8839 on &15 68840 ) 8841 *2 87(Wire8365 on &155 8366 ) 8367 *268 (Wire 8842 8368 uid 3810,0 8843 8369 shape (OrthoPolyLine … … 8852 8378 ] 8853 8379 ) 8854 start &14 88855 end &1 408380 start &147 8381 end &139 8856 8382 sat 32 8857 8383 eat 2 … … 8875 8401 ) 8876 8402 ) 8877 on &15 78878 ) 8879 *2 88(Wire8403 on &156 8404 ) 8405 *269 (Wire 8880 8406 uid 3826,0 8881 8407 shape (OrthoPolyLine … … 8890 8416 ] 8891 8417 ) 8892 start &1 508893 end &1 408418 start &149 8419 end &139 8894 8420 sat 32 8895 8421 eat 2 … … 8913 8439 ) 8914 8440 ) 8915 on &15 98916 ) 8917 *2 89(Wire8441 on &158 8442 ) 8443 *270 (Wire 8918 8444 uid 3834,0 8919 8445 shape (OrthoPolyLine … … 8928 8454 ] 8929 8455 ) 8930 start &15 18931 end &1 408456 start &150 8457 end &139 8932 8458 sat 32 8933 8459 eat 2 … … 8951 8477 ) 8952 8478 ) 8953 on &1 608954 ) 8955 *2 90(Wire8479 on &159 8480 ) 8481 *271 (Wire 8956 8482 uid 3842,0 8957 8483 shape (OrthoPolyLine … … 8967 8493 ] 8968 8494 ) 8969 start &15 28970 end &1 408495 start &151 8496 end &139 8971 8497 sat 32 8972 8498 eat 2 … … 8991 8517 ) 8992 8518 ) 8993 on &16 18994 ) 8995 *2 91(Wire8519 on &160 8520 ) 8521 *272 (Wire 8996 8522 uid 4942,0 8997 8523 shape (OrthoPolyLine … … 9008 8534 ) 9009 8535 start &14 9010 end &16 68536 end &165 9011 8537 sat 32 9012 8538 eat 32 … … 9031 8557 ) 9032 8558 ) 9033 on &16 79034 ) 9035 *2 92(Wire8559 on &166 8560 ) 8561 *273 (Wire 9036 8562 uid 6130,0 9037 8563 shape (OrthoPolyLine … … 9046 8572 ] 9047 8573 ) 9048 start &1 938574 start &173 9049 8575 end &15 9050 8576 sat 32 … … 9067 8593 ) 9068 8594 ) 9069 on &170 9070 ) 9071 *293 (Wire 9072 uid 6288,0 9073 shape (OrthoPolyLine 9074 uid 6289,0 9075 va (VaSet 9076 vasetType 3 9077 ) 9078 xt "1750,79000,13000,89000" 9079 pts [ 9080 "1750,89000" 9081 "9000,89000" 9082 "9000,86000" 9083 "9000,79000" 9084 "13000,79000" 9085 ] 9086 ) 9087 start &174 9088 end &191 9089 sat 32 9090 eat 32 9091 st 0 9092 sf 1 9093 si 0 9094 tg (WTG 9095 uid 6294,0 9096 ps "ConnStartEndStrategy" 9097 stg "STSignalDisplayStrategy" 9098 f (Text 9099 uid 6295,0 9100 va (VaSet 9101 ) 9102 xt "4000,88000,8600,89000" 9103 st "trigger_out" 9104 blo "4000,88800" 9105 tm "WireNameMgr" 9106 ) 9107 ) 9108 on &178 9109 ) 9110 *294 (Wire 8595 on &169 8596 ) 8597 *274 (Wire 9111 8598 uid 6306,0 9112 8599 shape (OrthoPolyLine … … 9115 8602 vasetType 3 9116 8603 ) 9117 xt "-28000,89000,-22000,89000" 9118 pts [ 9119 "-28000,89000" 9120 "-22000,89000" 9121 ] 9122 ) 9123 start &168 9124 end &181 9125 es 0 8604 xt "11000,79000,13000,79000" 8605 pts [ 8606 "11000,79000" 8607 "13000,79000" 8608 ] 8609 ) 8610 start &167 8611 end &171 9126 8612 sat 32 9127 8613 eat 32 8614 stc 0 9128 8615 st 0 9129 8616 sf 1 … … 9136 8623 uid 6313,0 9137 8624 va (VaSet 9138 ) 9139 xt "-26000,88000,-21500,89000" 8625 isHidden 1 8626 ) 8627 xt "13000,78000,17500,79000" 9140 8628 st "TEST_TRG" 9141 blo " -26000,88800"8629 blo "13000,78800" 9142 8630 tm "WireNameMgr" 9143 8631 ) 9144 8632 ) 9145 on &169 9146 ) 9147 *295 (Wire 9148 uid 6328,0 9149 shape (OrthoPolyLine 9150 uid 6329,0 9151 va (VaSet 9152 vasetType 3 9153 ) 9154 xt "-17000,89000,-11750,89000" 9155 pts [ 9156 "-17000,89000" 9157 "-11750,89000" 9158 ] 9159 ) 9160 start &183 9161 end &173 9162 sat 32 9163 eat 32 9164 st 0 9165 sf 1 9166 si 0 9167 tg (WTG 9168 uid 6334,0 9169 ps "ConnStartEndStrategy" 9170 stg "STSignalDisplayStrategy" 9171 f (Text 9172 uid 6335,0 9173 va (VaSet 9174 ) 9175 xt "-18000,92000,-11700,93000" 9176 st "not_TEST_TRG" 9177 blo "-18000,92800" 9178 tm "WireNameMgr" 9179 ) 9180 ) 9181 on &179 9182 ) 9183 *296 (Wire 8633 on &168 8634 ) 8635 *275 (Wire 9184 8636 uid 6431,0 9185 8637 shape (OrthoPolyLine … … 9195 8647 ) 9196 8648 start &43 9197 end &14 98649 end &148 9198 8650 sat 32 9199 8651 eat 32 … … 9217 8669 ) 9218 8670 ) 9219 on &15 89220 ) 9221 *2 97(Wire8671 on &157 8672 ) 8673 *276 (Wire 9222 8674 uid 6787,0 9223 8675 shape (OrthoPolyLine … … 9233 8685 ] 9234 8686 ) 9235 start & 2139236 end & 2178687 start &193 8688 end &197 9237 8689 sat 32 9238 8690 eat 1 … … 9256 8708 ) 9257 8709 ) 9258 on & 2149259 ) 9260 *2 98(Wire8710 on &194 8711 ) 8712 *277 (Wire 9261 8713 uid 6880,0 9262 8714 shape (OrthoPolyLine … … 9272 8724 ] 9273 8725 ) 9274 start & 2179275 end & 2158726 start &197 8727 end &195 9276 8728 sat 2 9277 8729 eat 32 … … 9295 8747 ) 9296 8748 ) 9297 on &216 9298 ) 9299 *299 (Wire 9300 uid 7102,0 9301 shape (OrthoPolyLine 9302 uid 7103,0 9303 va (VaSet 9304 vasetType 3 9305 ) 9306 xt "21000,132000,31000,132000" 9307 pts [ 9308 "21000,132000" 9309 "31000,132000" 9310 ] 9311 ) 9312 end &221 9313 sat 16 9314 eat 1 9315 st 0 9316 sf 1 9317 si 0 9318 tg (WTG 9319 uid 7108,0 9320 ps "ConnStartEndStrategy" 9321 stg "STSignalDisplayStrategy" 9322 f (Text 9323 uid 7109,0 9324 va (VaSet 9325 ) 9326 xt "23000,131000,27600,132000" 9327 st "D0_SROUT" 9328 blo "23000,131800" 9329 tm "WireNameMgr" 9330 ) 9331 ) 9332 on &106 9333 ) 9334 *300 (Wire 9335 uid 7110,0 9336 shape (OrthoPolyLine 9337 uid 7111,0 9338 va (VaSet 9339 vasetType 3 9340 ) 9341 xt "21000,133000,31000,133000" 9342 pts [ 9343 "21000,133000" 9344 "31000,133000" 9345 ] 9346 ) 9347 end &221 9348 sat 16 9349 eat 1 9350 st 0 9351 sf 1 9352 si 0 9353 tg (WTG 9354 uid 7116,0 9355 ps "ConnStartEndStrategy" 9356 stg "STSignalDisplayStrategy" 9357 f (Text 9358 uid 7117,0 9359 va (VaSet 9360 ) 9361 xt "23000,132000,27600,133000" 9362 st "D1_SROUT" 9363 blo "23000,132800" 9364 tm "WireNameMgr" 9365 ) 9366 ) 9367 on &107 9368 ) 9369 *301 (Wire 9370 uid 7118,0 9371 shape (OrthoPolyLine 9372 uid 7119,0 9373 va (VaSet 9374 vasetType 3 9375 ) 9376 xt "21000,134000,31000,134000" 9377 pts [ 9378 "21000,134000" 9379 "31000,134000" 9380 ] 9381 ) 9382 end &221 9383 sat 16 9384 eat 1 9385 st 0 9386 sf 1 9387 si 0 9388 tg (WTG 9389 uid 7124,0 9390 ps "ConnStartEndStrategy" 9391 stg "STSignalDisplayStrategy" 9392 f (Text 9393 uid 7125,0 9394 va (VaSet 9395 ) 9396 xt "23000,133000,27200,134000" 9397 st "RSRLOAD" 9398 blo "23000,133800" 9399 tm "WireNameMgr" 9400 ) 9401 ) 9402 on &64 9403 ) 9404 *302 (Wire 8749 on &196 8750 ) 8751 *278 (Wire 9405 8752 uid 7144,0 9406 8753 shape (OrthoPolyLine … … 9416 8763 ] 9417 8764 ) 9418 start &2 219419 end &2 258765 start &201 8766 end &205 9420 8767 sat 2 9421 8768 eat 32 … … 9434 8781 ) 9435 8782 xt "41000,131000,45800,132000" 9436 st "A1_T : ( 3:0)"8783 st "A1_T : (7:0)" 9437 8784 blo "41000,131800" 9438 8785 tm "WireNameMgr" 9439 8786 ) 9440 8787 ) 9441 on &2 269442 ) 9443 * 303(Wire8788 on &206 8789 ) 8790 *279 (Wire 9444 8791 uid 7477,0 9445 8792 shape (OrthoPolyLine … … 9455 8802 ) 9456 8803 start &38 9457 end &2 298804 end &209 9458 8805 es 0 9459 8806 sat 32 … … 9476 8823 ) 9477 8824 ) 9478 on &2 279479 ) 9480 * 304(Wire9481 uid 7487,08825 on &207 8826 ) 8827 *280 (Wire 8828 uid 8853,0 9482 8829 shape (OrthoPolyLine 9483 uid 7488,0 8830 uid 8854,0 8831 va (VaSet 8832 vasetType 3 8833 lineWidth 2 8834 ) 8835 xt "10000,109000,51250,132000" 8836 pts [ 8837 "51250,109000" 8838 "10000,109000" 8839 "10000,132000" 8840 "31000,132000" 8841 ] 8842 ) 8843 start &30 8844 end &201 8845 sat 32 8846 eat 1 8847 sty 1 8848 st 0 8849 sf 1 8850 si 0 8851 tg (WTG 8852 uid 8857,0 8853 ps "ConnStartEndStrategy" 8854 stg "STSignalDisplayStrategy" 8855 f (Text 8856 uid 8858,0 8857 va (VaSet 8858 ) 8859 xt "42000,108000,50500,109000" 8860 st "drs_channel_id : (3:0)" 8861 blo "42000,108800" 8862 tm "WireNameMgr" 8863 ) 8864 ) 8865 on &221 8866 ) 8867 *281 (Wire 8868 uid 9492,0 8869 shape (OrthoPolyLine 8870 uid 9493,0 9484 8871 va (VaSet 9485 8872 vasetType 3 … … 9491 8878 ] 9492 8879 ) 9493 end &2 218880 end &201 9494 8881 sat 16 9495 8882 eat 1 … … 9498 8885 si 0 9499 8886 tg (WTG 9500 uid 7493,08887 uid 9498,0 9501 8888 ps "ConnStartEndStrategy" 9502 8889 stg "STSignalDisplayStrategy" 9503 8890 f (Text 9504 uid 7494,09505 va (VaSet 9506 ) 9507 xt "23000,134000,2 5700,135000"9508 st " dummy"8891 uid 9499,0 8892 va (VaSet 8893 ) 8894 xt "23000,134000,26700,135000" 8895 st "TRG_OR" 9509 8896 blo "23000,134800" 9510 8897 tm "WireNameMgr" 9511 8898 ) 9512 8899 ) 9513 on &227 8900 on &169 8901 ) 8902 *282 (Wire 8903 uid 9502,0 8904 shape (OrthoPolyLine 8905 uid 9503,0 8906 va (VaSet 8907 vasetType 3 8908 ) 8909 xt "46000,69000,51250,69000" 8910 pts [ 8911 "51250,69000" 8912 "46000,69000" 8913 ] 8914 ) 8915 start &26 8916 sat 32 8917 eat 16 8918 st 0 8919 sf 1 8920 si 0 8921 tg (WTG 8922 uid 9506,0 8923 ps "ConnStartEndStrategy" 8924 stg "STSignalDisplayStrategy" 8925 f (Text 8926 uid 9507,0 8927 va (VaSet 8928 ) 8929 xt "47000,68000,50100,69000" 8930 st "CLK_50" 8931 blo "47000,68800" 8932 tm "WireNameMgr" 8933 ) 8934 ) 8935 on &222 9514 8936 ) 9515 8937 ] … … 9525 8947 color "26368,26368,26368" 9526 8948 ) 9527 packageList * 305(PackageList8949 packageList *283 (PackageList 9528 8950 uid 41,0 9529 8951 stg "VerticalLayoutStrategy" 9530 8952 textVec [ 9531 * 306(Text8953 *284 (Text 9532 8954 uid 42,0 9533 8955 va (VaSet … … 9538 8960 blo "0,800" 9539 8961 ) 9540 * 307(MLText8962 *285 (MLText 9541 8963 uid 43,0 9542 8964 va (VaSet … … 9559 8981 stg "VerticalLayoutStrategy" 9560 8982 textVec [ 9561 * 308(Text8983 *286 (Text 9562 8984 uid 45,0 9563 8985 va (VaSet … … 9569 8991 blo "20000,800" 9570 8992 ) 9571 * 309(Text8993 *287 (Text 9572 8994 uid 46,0 9573 8995 va (VaSet … … 9579 9001 blo "20000,1800" 9580 9002 ) 9581 * 310(MLText9003 *288 (MLText 9582 9004 uid 47,0 9583 9005 va (VaSet … … 9589 9011 tm "BdCompilerDirectivesTextMgr" 9590 9012 ) 9591 * 311(Text9013 *289 (Text 9592 9014 uid 48,0 9593 9015 va (VaSet … … 9599 9021 blo "20000,4800" 9600 9022 ) 9601 * 312(MLText9023 *290 (MLText 9602 9024 uid 49,0 9603 9025 va (VaSet … … 9607 9029 tm "BdCompilerDirectivesTextMgr" 9608 9030 ) 9609 * 313(Text9031 *291 (Text 9610 9032 uid 50,0 9611 9033 va (VaSet … … 9617 9039 blo "20000,5800" 9618 9040 ) 9619 * 314(MLText9041 *292 (MLText 9620 9042 uid 51,0 9621 9043 va (VaSet … … 9628 9050 associable 1 9629 9051 ) 9630 windowSize "0, 0,1281,1002"9631 viewArea " 2340,64220,87220,128140"9632 cachedDiagramExtent " -35500,0,699000,450107"9052 windowSize "0,22,1281,1024" 9053 viewArea "-13800,92200,71080,160280" 9054 cachedDiagramExtent "0,0,699000,450107" 9633 9055 pageSetupInfo (PageSetupInfo 9634 9056 ptrCmd "" … … 9641 9063 ) 9642 9064 hasePageBreakOrigin 1 9643 pageBreakOrigin " -73000,0"9644 lastUid 8751,09065 pageBreakOrigin "0,0" 9066 lastUid 9715,0 9645 9067 defaultCommentText (CommentText 9646 9068 shape (Rectangle … … 9704 9126 stg "VerticalLayoutStrategy" 9705 9127 textVec [ 9706 * 315(Text9128 *293 (Text 9707 9129 va (VaSet 9708 9130 font "Arial,8,1" … … 9713 9135 tm "BdLibraryNameMgr" 9714 9136 ) 9715 * 316(Text9137 *294 (Text 9716 9138 va (VaSet 9717 9139 font "Arial,8,1" … … 9722 9144 tm "BlkNameMgr" 9723 9145 ) 9724 * 317(Text9146 *295 (Text 9725 9147 va (VaSet 9726 9148 font "Arial,8,1" … … 9773 9195 stg "VerticalLayoutStrategy" 9774 9196 textVec [ 9775 * 318(Text9197 *296 (Text 9776 9198 va (VaSet 9777 9199 font "Arial,8,1" … … 9781 9203 blo "550,4300" 9782 9204 ) 9783 * 319(Text9205 *297 (Text 9784 9206 va (VaSet 9785 9207 font "Arial,8,1" … … 9789 9211 blo "550,5300" 9790 9212 ) 9791 * 320(Text9213 *298 (Text 9792 9214 va (VaSet 9793 9215 font "Arial,8,1" … … 9838 9260 stg "VerticalLayoutStrategy" 9839 9261 textVec [ 9840 * 321(Text9262 *299 (Text 9841 9263 va (VaSet 9842 9264 font "Arial,8,1" … … 9847 9269 tm "BdLibraryNameMgr" 9848 9270 ) 9849 *3 22(Text9271 *300 (Text 9850 9272 va (VaSet 9851 9273 font "Arial,8,1" … … 9856 9278 tm "CptNameMgr" 9857 9279 ) 9858 *3 23(Text9280 *301 (Text 9859 9281 va (VaSet 9860 9282 font "Arial,8,1" … … 9910 9332 stg "VerticalLayoutStrategy" 9911 9333 textVec [ 9912 *3 24(Text9334 *302 (Text 9913 9335 va (VaSet 9914 9336 font "Arial,8,1" … … 9918 9340 blo "500,4300" 9919 9341 ) 9920 *3 25(Text9342 *303 (Text 9921 9343 va (VaSet 9922 9344 font "Arial,8,1" … … 9926 9348 blo "500,5300" 9927 9349 ) 9928 *3 26(Text9350 *304 (Text 9929 9351 va (VaSet 9930 9352 font "Arial,8,1" … … 9971 9393 stg "VerticalLayoutStrategy" 9972 9394 textVec [ 9973 *3 27(Text9395 *305 (Text 9974 9396 va (VaSet 9975 9397 font "Arial,8,1" … … 9979 9401 blo "50,4300" 9980 9402 ) 9981 *3 28(Text9403 *306 (Text 9982 9404 va (VaSet 9983 9405 font "Arial,8,1" … … 9987 9409 blo "50,5300" 9988 9410 ) 9989 *3 29(Text9411 *307 (Text 9990 9412 va (VaSet 9991 9413 font "Arial,8,1" … … 10028 9450 stg "VerticalLayoutStrategy" 10029 9451 textVec [ 10030 *3 30(Text9452 *308 (Text 10031 9453 va (VaSet 10032 9454 font "Arial,8,1" … … 10037 9459 tm "HdlTextNameMgr" 10038 9460 ) 10039 *3 31(Text9461 *309 (Text 10040 9462 va (VaSet 10041 9463 font "Arial,8,1" … … 10440 9862 stg "VerticalLayoutStrategy" 10441 9863 textVec [ 10442 *3 32(Text9864 *310 (Text 10443 9865 va (VaSet 10444 9866 font "Arial,8,1" … … 10448 9870 blo "14100,20800" 10449 9871 ) 10450 *3 33(MLText9872 *311 (MLText 10451 9873 va (VaSet 10452 9874 ) … … 10500 9922 stg "VerticalLayoutStrategy" 10501 9923 textVec [ 10502 *3 34(Text9924 *312 (Text 10503 9925 va (VaSet 10504 9926 font "Arial,8,1" … … 10508 9930 blo "14100,20800" 10509 9931 ) 10510 *3 35(MLText9932 *313 (MLText 10511 9933 va (VaSet 10512 9934 ) … … 10652 10074 commonDM (CommonDM 10653 10075 ldm (LogicalDM 10654 suid 1 58,010076 suid 163,0 10655 10077 usingSuid 1 10656 emptyRow *3 36(LEmptyRow10078 emptyRow *314 (LEmptyRow 10657 10079 ) 10658 10080 uid 54,0 10659 10081 optionalChildren [ 10660 *3 37(RefLabelRowHdr10661 ) 10662 *3 38(TitleRowHdr10663 ) 10664 *3 39(FilterRowHdr10665 ) 10666 *3 40(RefLabelColHdr10082 *315 (RefLabelRowHdr 10083 ) 10084 *316 (TitleRowHdr 10085 ) 10086 *317 (FilterRowHdr 10087 ) 10088 *318 (RefLabelColHdr 10667 10089 tm "RefLabelColHdrMgr" 10668 10090 ) 10669 *3 41(RowExpandColHdr10091 *319 (RowExpandColHdr 10670 10092 tm "RowExpandColHdrMgr" 10671 10093 ) 10672 *3 42(GroupColHdr10094 *320 (GroupColHdr 10673 10095 tm "GroupColHdrMgr" 10674 10096 ) 10675 *3 43(NameColHdr10097 *321 (NameColHdr 10676 10098 tm "BlockDiagramNameColHdrMgr" 10677 10099 ) 10678 *3 44(ModeColHdr10100 *322 (ModeColHdr 10679 10101 tm "BlockDiagramModeColHdrMgr" 10680 10102 ) 10681 *3 45(TypeColHdr10103 *323 (TypeColHdr 10682 10104 tm "BlockDiagramTypeColHdrMgr" 10683 10105 ) 10684 *3 46(BoundsColHdr10106 *324 (BoundsColHdr 10685 10107 tm "BlockDiagramBoundsColHdrMgr" 10686 10108 ) 10687 *3 47(InitColHdr10109 *325 (InitColHdr 10688 10110 tm "BlockDiagramInitColHdrMgr" 10689 10111 ) 10690 *3 48(EolColHdr10112 *326 (EolColHdr 10691 10113 tm "BlockDiagramEolColHdrMgr" 10692 10114 ) 10693 *3 49(LeafLogPort10115 *327 (LeafLogPort 10694 10116 port (LogicalPort 10695 10117 m 4 … … 10706 10128 uid 327,0 10707 10129 ) 10708 *3 50(LeafLogPort10130 *328 (LeafLogPort 10709 10131 port (LogicalPort 10710 10132 m 4 … … 10719 10141 uid 329,0 10720 10142 ) 10721 *3 51(LeafLogPort10143 *329 (LeafLogPort 10722 10144 port (LogicalPort 10723 10145 m 4 … … 10731 10153 uid 1491,0 10732 10154 ) 10733 *352 (LeafLogPort 10734 port (LogicalPort 10735 m 4 10736 decl (Decl 10737 n "CLK_50" 10738 t "std_logic" 10739 preAdd 0 10740 posAdd 0 10741 o 51 10742 suid 54,0 10743 ) 10744 ) 10745 uid 2275,0 10746 ) 10747 *353 (LeafLogPort 10155 *330 (LeafLogPort 10748 10156 port (LogicalPort 10749 10157 m 1 … … 10758 10166 uid 2435,0 10759 10167 ) 10760 *3 54(LeafLogPort10168 *331 (LeafLogPort 10761 10169 port (LogicalPort 10762 10170 m 4 … … 10771 10179 uid 2437,0 10772 10180 ) 10773 *3 55(LeafLogPort10181 *332 (LeafLogPort 10774 10182 port (LogicalPort 10775 10183 m 4 … … 10784 10192 uid 3037,0 10785 10193 ) 10786 *3 56(LeafLogPort10194 *333 (LeafLogPort 10787 10195 port (LogicalPort 10788 10196 m 1 … … 10796 10204 uid 3039,0 10797 10205 ) 10798 *3 57(LeafLogPort10206 *334 (LeafLogPort 10799 10207 port (LogicalPort 10800 10208 decl (Decl … … 10809 10217 uid 3276,0 10810 10218 ) 10811 *3 58(LeafLogPort10219 *335 (LeafLogPort 10812 10220 port (LogicalPort 10813 10221 decl (Decl … … 10820 10228 uid 3278,0 10821 10229 ) 10822 *3 59(LeafLogPort10230 *336 (LeafLogPort 10823 10231 port (LogicalPort 10824 10232 m 1 … … 10833 10241 uid 3280,0 10834 10242 ) 10835 *3 60(LeafLogPort10243 *337 (LeafLogPort 10836 10244 port (LogicalPort 10837 10245 m 4 … … 10845 10253 uid 3282,0 10846 10254 ) 10847 *3 61(LeafLogPort10255 *338 (LeafLogPort 10848 10256 port (LogicalPort 10849 10257 m 1 … … 10859 10267 uid 3382,0 10860 10268 ) 10861 *3 62(LeafLogPort10269 *339 (LeafLogPort 10862 10270 port (LogicalPort 10863 10271 decl (Decl … … 10871 10279 uid 3384,0 10872 10280 ) 10873 *3 63(LeafLogPort10281 *340 (LeafLogPort 10874 10282 port (LogicalPort 10875 10283 decl (Decl … … 10883 10291 uid 3386,0 10884 10292 ) 10885 *3 64(LeafLogPort10293 *341 (LeafLogPort 10886 10294 port (LogicalPort 10887 10295 decl (Decl … … 10895 10303 uid 3388,0 10896 10304 ) 10897 *3 65(LeafLogPort10305 *342 (LeafLogPort 10898 10306 port (LogicalPort 10899 10307 decl (Decl … … 10907 10315 uid 3390,0 10908 10316 ) 10909 *3 66(LeafLogPort10317 *343 (LeafLogPort 10910 10318 port (LogicalPort 10911 10319 decl (Decl … … 10919 10327 uid 3392,0 10920 10328 ) 10921 *3 67(LeafLogPort10329 *344 (LeafLogPort 10922 10330 port (LogicalPort 10923 10331 m 1 … … 10931 10339 uid 3468,0 10932 10340 ) 10933 *3 68(LeafLogPort10341 *345 (LeafLogPort 10934 10342 port (LogicalPort 10935 10343 m 1 … … 10943 10351 uid 3470,0 10944 10352 ) 10945 *3 69(LeafLogPort10353 *346 (LeafLogPort 10946 10354 port (LogicalPort 10947 10355 m 1 … … 10955 10363 uid 3472,0 10956 10364 ) 10957 *3 70(LeafLogPort10365 *347 (LeafLogPort 10958 10366 port (LogicalPort 10959 10367 m 1 … … 10967 10375 uid 3474,0 10968 10376 ) 10969 *3 71(LeafLogPort10377 *348 (LeafLogPort 10970 10378 port (LogicalPort 10971 10379 decl (Decl … … 10978 10386 uid 3524,0 10979 10387 ) 10980 *3 72(LeafLogPort10388 *349 (LeafLogPort 10981 10389 port (LogicalPort 10982 10390 decl (Decl … … 10989 10397 uid 3526,0 10990 10398 ) 10991 *3 73(LeafLogPort10399 *350 (LeafLogPort 10992 10400 port (LogicalPort 10993 10401 decl (Decl … … 11000 10408 uid 3528,0 11001 10409 ) 11002 *3 74(LeafLogPort10410 *351 (LeafLogPort 11003 10411 port (LogicalPort 11004 10412 decl (Decl … … 11011 10419 uid 3530,0 11012 10420 ) 11013 *3 75(LeafLogPort10421 *352 (LeafLogPort 11014 10422 port (LogicalPort 11015 10423 m 1 … … 11025 10433 uid 3532,0 11026 10434 ) 11027 *3 76(LeafLogPort10435 *353 (LeafLogPort 11028 10436 port (LogicalPort 11029 10437 m 1 … … 11038 10446 uid 3534,0 11039 10447 ) 11040 *3 77(LeafLogPort10448 *354 (LeafLogPort 11041 10449 port (LogicalPort 11042 10450 m 1 … … 11050 10458 uid 3646,0 11051 10459 ) 11052 *3 78(LeafLogPort10460 *355 (LeafLogPort 11053 10461 port (LogicalPort 11054 10462 m 1 … … 11062 10470 uid 3648,0 11063 10471 ) 11064 *3 79(LeafLogPort10472 *356 (LeafLogPort 11065 10473 port (LogicalPort 11066 10474 m 1 … … 11074 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10662 m 1 … … 11262 10670 uid 3892,0 11263 10671 ) 11264 *3 95(LeafLogPort10672 *372 (LeafLogPort 11265 10673 port (LogicalPort 11266 10674 m 1 … … 11274 10682 uid 3894,0 11275 10683 ) 11276 *3 96(LeafLogPort10684 *373 (LeafLogPort 11277 10685 port (LogicalPort 11278 10686 m 1 … … 11287 10695 uid 3896,0 11288 10696 ) 11289 *3 97(LeafLogPort10697 *374 (LeafLogPort 11290 10698 port (LogicalPort 11291 10699 m 1 … … 11299 10707 uid 3898,0 11300 10708 ) 11301 *3 98(LeafLogPort10709 *375 (LeafLogPort 11302 10710 port (LogicalPort 11303 10711 m 1 … … 11311 10719 uid 3900,0 11312 10720 ) 11313 *3 99(LeafLogPort10721 *376 (LeafLogPort 11314 10722 port (LogicalPort 11315 10723 m 1 … … 11325 10733 uid 3902,0 11326 10734 ) 11327 * 400(LeafLogPort10735 *377 (LeafLogPort 11328 10736 port (LogicalPort 11329 10737 m 1 … … 11339 10747 uid 5322,0 11340 10748 ) 11341 * 401(LeafLogPort10749 *378 (LeafLogPort 11342 10750 port (LogicalPort 11343 10751 decl (Decl … … 11351 10759 scheme 0 11352 10760 ) 11353 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"GroupColHdrMgr" 11951 11352 ) 11952 *4 89(NameColHdr11353 *465 (NameColHdr 11953 11354 tm "GenericNameColHdrMgr" 11954 11355 ) 11955 *4 90(TypeColHdr11356 *466 (TypeColHdr 11956 11357 tm "GenericTypeColHdrMgr" 11957 11358 ) 11958 *4 91(InitColHdr11359 *467 (InitColHdr 11959 11360 tm "GenericValueColHdrMgr" 11960 11361 ) 11961 *4 92(PragmaColHdr11362 *468 (PragmaColHdr 11962 11363 tm "GenericPragmaColHdrMgr" 11963 11364 ) 11964 *4 93(EolColHdr11365 *469 (EolColHdr 11965 11366 tm "GenericEolColHdrMgr" 11966 11367 ) … … 11972 11373 uid 95,0 11973 11374 optionalChildren [ 11974 *4 94(Sheet11375 *470 (Sheet 11975 11376 sheetRow (SheetRow 11976 11377 headerVa (MVa … … 11989 11390 font "Tahoma,10,0" 11990 11391 ) 11991 emptyMRCItem *4 95(MRCItem11992 litem &4 8211392 emptyMRCItem *471 (MRCItem 11393 litem &458 11993 11394 pos 0 11994 11395 dimension 20 … … 11996 11397 uid 97,0 11997 11398 optionalChildren [ 11998 *4 96(MRCItem11999 litem &4 8311399 *472 (MRCItem 11400 litem &459 12000 11401 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FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.bak
r246 r252 26 26 instances [ 27 27 (Instance 28 name "I_ testboard_main"28 name "I_board_main" 29 29 duLibraryName "FACT_FAD_lib" 30 30 duName "FAD_main" … … 38 38 mwi 0 39 39 uid 169,0 40 )41 (Instance42 name "I0"43 duLibraryName "FACT_FAD_LIB"44 duName "debouncer"45 elements [46 (GiElement47 name "WIDTH"48 type "INTEGER"49 value "17"50 )51 ]52 mwi 053 uid 6250,054 )55 (Instance56 name "I1"57 duLibraryName "moduleware"58 duName "inv"59 elements [60 ]61 mwi 162 uid 6539,063 40 ) 64 41 (Instance … … 128 105 (vvPair 129 106 variable "HDLDir" 130 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hdl"107 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" 131 108 ) 132 109 (vvPair 133 110 variable "HDSDir" 134 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hds"111 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 135 112 ) 136 113 (vvPair 137 114 variable "SideDataDesignDir" 138 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"115 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info" 139 116 ) 140 117 (vvPair 141 118 variable "SideDataUserDir" 142 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"119 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user" 143 120 ) 144 121 (vvPair 145 122 variable "SourceDir" 146 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hds"123 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 147 124 ) 148 125 (vvPair … … 160 137 (vvPair 161 138 variable "d" 162 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board"139 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board" 163 140 ) 164 141 (vvPair 165 142 variable "d_logical" 166 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hds\\FAD_Board"143 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board" 167 144 ) 168 145 (vvPair 169 146 variable "date" 170 value " 22.06.2010"147 value "14.07.2010" 171 148 ) 172 149 (vvPair 173 150 variable "day" 174 value " Di"151 value "Mi" 175 152 ) 176 153 (vvPair 177 154 variable "day_long" 178 value " Dienstag"155 value "Mittwoch" 179 156 ) 180 157 (vvPair 181 158 variable "dd" 182 value " 22"159 value "14" 183 160 ) 184 161 (vvPair … … 208 185 (vvPair 209 186 variable "host" 210 value " TU-CC4900F8C7D2"187 value "E5B-LABOR6" 211 188 ) 212 189 (vvPair … … 219 196 ) 220 197 (vvPair 198 variable "library_downstream_HdsLintPlugin" 199 value "$HDS_PROJECT_DIR\\FACT_FAD_lib\\designcheck" 200 ) 201 (vvPair 221 202 variable "library_downstream_ISEPARInvoke" 222 203 value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" … … 236 217 (vvPair 237 218 variable "mm" 238 value "0 6"219 value "07" 239 220 ) 240 221 (vvPair … … 244 225 (vvPair 245 226 variable "month" 246 value "Ju n"227 value "Jul" 247 228 ) 248 229 (vvPair 249 230 variable "month_long" 250 value "Ju ni"231 value "Juli" 251 232 ) 252 233 (vvPair 253 234 variable "p" 254 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"235 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd" 255 236 ) 256 237 (vvPair 257 238 variable "p_logical" 258 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"239 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd" 259 240 ) 260 241 (vvPair … … 312 293 (vvPair 313 294 variable "time" 314 value "1 1:16:21"295 value "15:24:46" 315 296 ) 316 297 (vvPair … … 364 345 bg "0,0,32768" 365 346 ) 366 xt "99200,4000,108 700,5000"347 xt "99200,4000,108500,5000" 367 348 st " 368 349 by %user on %dd %month %year … … 1831 1812 font "Arial,8,1" 1832 1813 ) 1833 xt "52200,125000,5 9400,126000"1834 st "I_ testboard_main"1814 xt "52200,125000,58000,126000" 1815 st "I_board_main" 1835 1816 blo "52200,125800" 1836 1817 tm "InstanceNameMgr" … … 2065 2046 preAdd 0 2066 2047 posAdd 0 2067 o 5 52048 o 56 2068 2049 suid 5,0 2069 2050 ) … … 2073 2054 font "Courier New,8,0" 2074 2055 ) 2075 xt "39000,48 000,67000,48800"2056 xt "39000,48800,67000,49600" 2076 2057 st "SIGNAL board_id : std_logic_vector(3 downto 0)" 2077 2058 ) … … 2083 2064 t "std_logic_vector" 2084 2065 b "(1 downto 0)" 2085 o 5 62066 o 57 2086 2067 suid 6,0 2087 2068 ) … … 2091 2072 font "Courier New,8,0" 2092 2073 ) 2093 xt "39000,4 8800,67000,49600"2074 xt "39000,49600,67000,50400" 2094 2075 st "SIGNAL crate_id : std_logic_vector(1 downto 0)" 2095 2076 ) … … 2406 2387 n "adc_data_array" 2407 2388 t "adc_data_array_type" 2408 o 5 42389 o 55 2409 2390 suid 29,0 2410 2391 ) … … 2414 2395 font "Courier New,8,0" 2415 2396 ) 2416 xt "39000,4 7200,62500,48000"2397 xt "39000,48000,62500,48800" 2417 2398 st "SIGNAL adc_data_array : adc_data_array_type" 2418 2399 ) 2419 2400 ) 2420 2401 *63 (Net 2421 uid 2267,02422 decl (Decl2423 n "CLK_50"2424 t "std_logic"2425 preAdd 02426 posAdd 02427 o 512428 suid 54,02429 )2430 declText (MLText2431 uid 2268,02432 va (VaSet2433 font "Courier New,8,0"2434 )2435 xt "39000,44800,57000,45600"2436 st "SIGNAL CLK_50 : std_logic"2437 )2438 )2439 *64 (Net2440 2402 uid 2407,0 2441 2403 decl (Decl 2442 2404 n "RSRLOAD" 2443 2405 t "std_logic" 2444 o 3 52406 o 36 2445 2407 suid 57,0 2446 2408 i "'0'" … … 2451 2413 font "Courier New,8,0" 2452 2414 ) 2453 xt "39000,31 000,68000,31800"2415 xt "39000,31800,68000,32600" 2454 2416 st "RSRLOAD : std_logic := '0'" 2455 2417 ) 2456 2418 ) 2457 *6 5(PortIoOut2419 *64 (PortIoOut 2458 2420 uid 2415,0 2459 2421 shape (CompositeShape … … 2500 2462 ) 2501 2463 ) 2502 *6 6(Net2464 *65 (Net 2503 2465 uid 2421,0 2504 2466 decl (Decl 2505 2467 n "SRCLK" 2506 2468 t "std_logic" 2507 o 5 22469 o 53 2508 2470 suid 58,0 2509 2471 i "'0'" … … 2514 2476 font "Courier New,8,0" 2515 2477 ) 2516 xt "39000,4 5600,71500,46400"2478 xt "39000,46400,71500,47200" 2517 2479 st "SIGNAL SRCLK : std_logic := '0'" 2518 2480 ) 2519 2481 ) 2520 *6 7(Net2482 *66 (Net 2521 2483 uid 3019,0 2522 2484 decl (Decl … … 2524 2486 t "std_logic_vector" 2525 2487 b "(3 DOWNTO 0)" 2526 o 592488 o 60 2527 2489 suid 65,0 2528 2490 ) … … 2532 2494 font "Courier New,8,0" 2533 2495 ) 2534 xt "39000,5 1200,67000,52000"2496 xt "39000,52000,67000,52800" 2535 2497 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" 2536 2498 ) 2537 2499 ) 2538 *6 8(Net2500 *67 (Net 2539 2501 uid 3025,0 2540 2502 decl (Decl 2541 2503 n "DAC_CS" 2542 2504 t "std_logic" 2543 o 2 12505 o 22 2544 2506 suid 66,0 2545 2507 ) … … 2549 2511 font "Courier New,8,0" 2550 2512 ) 2551 xt "39000, 19800,53500,20600"2513 xt "39000,20600,53500,21400" 2552 2514 st "DAC_CS : std_logic" 2553 2515 ) 2554 2516 ) 2555 *6 9(PortIoOut2517 *68 (PortIoOut 2556 2518 uid 3153,0 2557 2519 shape (CompositeShape … … 2598 2560 ) 2599 2561 ) 2600 * 70(Net2562 *69 (Net 2601 2563 uid 3216,0 2602 2564 decl (Decl … … 2617 2579 ) 2618 2580 ) 2619 *7 1(Net2581 *70 (Net 2620 2582 uid 3226,0 2621 2583 decl (Decl … … 2634 2596 ) 2635 2597 ) 2636 *7 2(HdlText2598 *71 (HdlText 2637 2599 uid 3248,0 2638 2600 optionalChildren [ 2639 *7 3(EmbeddedText2601 *72 (EmbeddedText 2640 2602 uid 3254,0 2641 2603 commentText (CommentText … … 2689 2651 stg "VerticalLayoutStrategy" 2690 2652 textVec [ 2691 *7 4(Text2653 *73 (Text 2692 2654 uid 3251,0 2693 2655 va (VaSet … … 2699 2661 tm "HdlTextNameMgr" 2700 2662 ) 2701 *7 5(Text2663 *74 (Text 2702 2664 uid 3252,0 2703 2665 va (VaSet … … 2725 2687 viewiconposition 0 2726 2688 ) 2727 *7 6(Net2689 *75 (Net 2728 2690 uid 3266,0 2729 2691 decl (Decl … … 2731 2693 t "std_logic_vector" 2732 2694 b "(3 downto 0)" 2733 o 1 62695 o 17 2734 2696 suid 71,0 2735 2697 ) … … 2739 2701 font "Courier New,8,0" 2740 2702 ) 2741 xt "39000,1 5800,63500,16600"2703 xt "39000,16600,63500,17400" 2742 2704 st "A_CLK : std_logic_vector(3 downto 0)" 2743 2705 ) 2744 2706 ) 2745 *7 7(Net2707 *76 (Net 2746 2708 uid 3268,0 2747 2709 decl (Decl 2748 2710 n "CLK_25_PS" 2749 2711 t "std_logic" 2750 o 5 02712 o 51 2751 2713 suid 72,0 2752 2714 ) … … 2756 2718 font "Courier New,8,0" 2757 2719 ) 2758 xt "39000,44 000,57000,44800"2720 xt "39000,44800,57000,45600" 2759 2721 st "SIGNAL CLK_25_PS : std_logic" 2760 2722 ) 2761 2723 ) 2762 *7 8(PortIoOut2724 *77 (PortIoOut 2763 2725 uid 3284,0 2764 2726 shape (CompositeShape … … 2805 2767 ) 2806 2768 ) 2807 *7 9(Net2769 *78 (Net 2808 2770 uid 3290,0 2809 2771 decl (Decl … … 2812 2774 preAdd 0 2813 2775 posAdd 0 2814 o 3 02776 o 31 2815 2777 suid 73,0 2816 2778 ) … … 2820 2782 font "Courier New,8,0" 2821 2783 ) 2822 xt "39000,27 000,53500,27800"2784 xt "39000,27800,53500,28600" 2823 2785 st "OE_ADC : STD_LOGIC" 2824 2786 ) 2825 2787 ) 2826 * 80(PortIoIn2788 *79 (PortIoIn 2827 2789 uid 3292,0 2828 2790 shape (CompositeShape … … 2869 2831 ) 2870 2832 ) 2871 *8 1(Net2833 *80 (Net 2872 2834 uid 3298,0 2873 2835 decl (Decl … … 2887 2849 ) 2888 2850 ) 2889 *8 2(HdlText2851 *81 (HdlText 2890 2852 uid 3300,0 2891 2853 optionalChildren [ 2892 *8 3(EmbeddedText2854 *82 (EmbeddedText 2893 2855 uid 3306,0 2894 2856 commentText (CommentText … … 2942 2904 stg "VerticalLayoutStrategy" 2943 2905 textVec [ 2944 *8 4(Text2906 *83 (Text 2945 2907 uid 3303,0 2946 2908 va (VaSet … … 2952 2914 tm "HdlTextNameMgr" 2953 2915 ) 2954 *8 5(Text2916 *84 (Text 2955 2917 uid 3304,0 2956 2918 va (VaSet … … 2978 2940 viewiconposition 0 2979 2941 ) 2980 *8 6(PortIoIn2942 *85 (PortIoIn 2981 2943 uid 3310,0 2982 2944 shape (CompositeShape … … 3023 2985 ) 3024 2986 ) 3025 *8 7(PortIoIn2987 *86 (PortIoIn 3026 2988 uid 3332,0 3027 2989 shape (CompositeShape … … 3068 3030 ) 3069 3031 ) 3070 *8 8(PortIoIn3032 *87 (PortIoIn 3071 3033 uid 3338,0 3072 3034 shape (CompositeShape … … 3113 3075 ) 3114 3076 ) 3115 *8 9(PortIoIn3077 *88 (PortIoIn 3116 3078 uid 3344,0 3117 3079 shape (CompositeShape … … 3158 3120 ) 3159 3121 ) 3160 * 90(Net3122 *89 (Net 3161 3123 uid 3374,0 3162 3124 decl (Decl … … 3176 3138 ) 3177 3139 ) 3178 *9 1(Net3140 *90 (Net 3179 3141 uid 3376,0 3180 3142 decl (Decl … … 3194 3156 ) 3195 3157 ) 3196 *9 2(Net3158 *91 (Net 3197 3159 uid 3378,0 3198 3160 decl (Decl … … 3212 3174 ) 3213 3175 ) 3214 *9 3(Net3176 *92 (Net 3215 3177 uid 3380,0 3216 3178 decl (Decl … … 3230 3192 ) 3231 3193 ) 3232 *9 4(HdlText3194 *93 (HdlText 3233 3195 uid 3394,0 3234 3196 optionalChildren [ 3235 *9 5(EmbeddedText3197 *94 (EmbeddedText 3236 3198 uid 3400,0 3237 3199 commentText (CommentText … … 3285 3247 stg "VerticalLayoutStrategy" 3286 3248 textVec [ 3287 *9 6(Text3249 *95 (Text 3288 3250 uid 3397,0 3289 3251 va (VaSet … … 3295 3257 tm "HdlTextNameMgr" 3296 3258 ) 3297 *9 7(Text3259 *96 (Text 3298 3260 uid 3398,0 3299 3261 va (VaSet … … 3321 3283 viewiconposition 0 3322 3284 ) 3323 *9 8(Net3285 *97 (Net 3324 3286 uid 3460,0 3325 3287 decl (Decl 3326 3288 n "D0_SRCLK" 3327 3289 t "STD_LOGIC" 3328 o 1 73290 o 18 3329 3291 suid 87,0 3330 3292 ) … … 3334 3296 font "Courier New,8,0" 3335 3297 ) 3336 xt "39000,1 6600,53500,17400"3298 xt "39000,17400,53500,18200" 3337 3299 st "D0_SRCLK : STD_LOGIC" 3338 3300 ) 3339 3301 ) 3340 *9 9(Net3302 *98 (Net 3341 3303 uid 3462,0 3342 3304 decl (Decl 3343 3305 n "D1_SRCLK" 3344 3306 t "STD_LOGIC" 3345 o 1 83307 o 19 3346 3308 suid 88,0 3347 3309 ) … … 3351 3313 font "Courier New,8,0" 3352 3314 ) 3353 xt "39000,1 7400,53500,18200"3315 xt "39000,18200,53500,19000" 3354 3316 st "D1_SRCLK : STD_LOGIC" 3355 3317 ) 3356 3318 ) 3357 * 100(Net3319 *99 (Net 3358 3320 uid 3464,0 3359 3321 decl (Decl 3360 3322 n "D2_SRCLK" 3361 3323 t "STD_LOGIC" 3362 o 193324 o 20 3363 3325 suid 89,0 3364 3326 ) … … 3368 3330 font "Courier New,8,0" 3369 3331 ) 3370 xt "39000,1 8200,53500,19000"3332 xt "39000,19000,53500,19800" 3371 3333 st "D2_SRCLK : STD_LOGIC" 3372 3334 ) 3373 3335 ) 3374 *10 1(Net3336 *100 (Net 3375 3337 uid 3466,0 3376 3338 decl (Decl 3377 3339 n "D3_SRCLK" 3378 3340 t "STD_LOGIC" 3379 o 2 03341 o 21 3380 3342 suid 90,0 3381 3343 ) … … 3385 3347 font "Courier New,8,0" 3386 3348 ) 3387 xt "39000,19 000,53500,19800"3349 xt "39000,19800,53500,20600" 3388 3350 st "D3_SRCLK : STD_LOGIC" 3389 3351 ) 3390 3352 ) 3391 *10 2(PortIoIn3353 *101 (PortIoIn 3392 3354 uid 3476,0 3393 3355 shape (CompositeShape … … 3434 3396 ) 3435 3397 ) 3436 *10 3(PortIoIn3398 *102 (PortIoIn 3437 3399 uid 3482,0 3438 3400 shape (CompositeShape … … 3479 3441 ) 3480 3442 ) 3481 *10 4(PortIoIn3443 *103 (PortIoIn 3482 3444 uid 3488,0 3483 3445 shape (CompositeShape … … 3524 3486 ) 3525 3487 ) 3526 *10 5(PortIoIn3488 *104 (PortIoIn 3527 3489 uid 3494,0 3528 3490 shape (CompositeShape … … 3569 3531 ) 3570 3532 ) 3571 *10 6(Net3533 *105 (Net 3572 3534 uid 3500,0 3573 3535 decl (Decl … … 3586 3548 ) 3587 3549 ) 3588 *10 7(Net3550 *106 (Net 3589 3551 uid 3502,0 3590 3552 decl (Decl … … 3603 3565 ) 3604 3566 ) 3605 *10 8(Net3567 *107 (Net 3606 3568 uid 3504,0 3607 3569 decl (Decl … … 3620 3582 ) 3621 3583 ) 3622 *10 9(Net3584 *108 (Net 3623 3585 uid 3506,0 3624 3586 decl (Decl … … 3637 3599 ) 3638 3600 ) 3639 *1 10(PortIoOut3601 *109 (PortIoOut 3640 3602 uid 3508,0 3641 3603 shape (CompositeShape … … 3650 3612 sl 0 3651 3613 ro 90 3652 xt " 19000,108625,20500,109375"3614 xt "4000,133625,5500,134375" 3653 3615 ) 3654 3616 (Line … … 3656 3618 sl 0 3657 3619 ro 90 3658 xt " 20500,109000,21000,109000"3659 pts [ 3660 " 21000,109000"3661 " 20500,109000"3620 xt "5500,134000,6000,134000" 3621 pts [ 3622 "6000,134000" 3623 "5500,134000" 3662 3624 ] 3663 3625 ) … … 3674 3636 va (VaSet 3675 3637 ) 3676 xt "1 6100,108500,18000,109500"3638 xt "1100,133500,3000,134500" 3677 3639 st "D_A" 3678 3640 ju 2 3679 blo " 18000,109300"3680 tm "WireNameMgr" 3681 ) 3682 ) 3683 ) 3684 *11 1(Net3641 blo "3000,134300" 3642 tm "WireNameMgr" 3643 ) 3644 ) 3645 ) 3646 *110 (Net 3685 3647 uid 3514,0 3686 3648 decl (Decl … … 3688 3650 t "std_logic_vector" 3689 3651 b "(3 DOWNTO 0)" 3690 o 2 43652 o 25 3691 3653 suid 95,0 3692 3654 i "(others => '0')" … … 3697 3659 font "Courier New,8,0" 3698 3660 ) 3699 xt "39000,2 2200,74000,23000"3661 xt "39000,23000,74000,23800" 3700 3662 st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0')" 3701 3663 ) 3702 3664 ) 3703 *11 2(PortIoOut3665 *111 (PortIoOut 3704 3666 uid 3516,0 3705 3667 shape (CompositeShape … … 3746 3708 ) 3747 3709 ) 3748 *11 3(Net3710 *112 (Net 3749 3711 uid 3522,0 3750 3712 decl (Decl 3751 3713 n "DWRITE" 3752 3714 t "std_logic" 3753 o 2 33715 o 24 3754 3716 suid 96,0 3755 3717 i "'0'" … … 3760 3722 font "Courier New,8,0" 3761 3723 ) 3762 xt "39000,2 1400,68000,22200"3724 xt "39000,22200,68000,23000" 3763 3725 st "DWRITE : std_logic := '0'" 3764 3726 ) 3765 3727 ) 3766 *11 4(PortIoOut3728 *113 (PortIoOut 3767 3729 uid 3536,0 3768 3730 shape (CompositeShape … … 3808 3770 ) 3809 3771 ) 3810 *11 5(HdlText3772 *114 (HdlText 3811 3773 uid 3542,0 3812 3774 optionalChildren [ 3813 *11 6(EmbeddedText3775 *115 (EmbeddedText 3814 3776 uid 3612,0 3815 3777 commentText (CommentText … … 3863 3825 stg "VerticalLayoutStrategy" 3864 3826 textVec [ 3865 *11 7(Text3827 *116 (Text 3866 3828 uid 3545,0 3867 3829 va (VaSet … … 3873 3835 tm "HdlTextNameMgr" 3874 3836 ) 3875 *11 8(Text3837 *117 (Text 3876 3838 uid 3546,0 3877 3839 va (VaSet … … 3899 3861 viewiconposition 0 3900 3862 ) 3901 *11 9(PortIoOut3863 *118 (PortIoOut 3902 3864 uid 3548,0 3903 3865 shape (CompositeShape … … 3943 3905 ) 3944 3906 ) 3945 *1 20(PortIoOut3907 *119 (PortIoOut 3946 3908 uid 3554,0 3947 3909 shape (CompositeShape … … 3987 3949 ) 3988 3950 ) 3989 *12 1(PortIoOut3951 *120 (PortIoOut 3990 3952 uid 3560,0 3991 3953 shape (CompositeShape … … 4031 3993 ) 4032 3994 ) 4033 *12 2(PortIoOut3995 *121 (PortIoOut 4034 3996 uid 3566,0 4035 3997 shape (CompositeShape … … 4075 4037 ) 4076 4038 ) 4077 *12 3(Net4039 *122 (Net 4078 4040 uid 3604,0 4079 4041 decl (Decl 4080 4042 n "T0_CS" 4081 4043 t "std_logic" 4082 o 3 84044 o 39 4083 4045 suid 101,0 4084 4046 ) … … 4088 4050 font "Courier New,8,0" 4089 4051 ) 4090 xt "39000,3 3400,53500,34200"4052 xt "39000,34200,53500,35000" 4091 4053 st "T0_CS : std_logic" 4092 4054 ) 4093 4055 ) 4094 *12 4(Net4056 *123 (Net 4095 4057 uid 3606,0 4096 4058 decl (Decl 4097 4059 n "T1_CS" 4098 4060 t "std_logic" 4099 o 394061 o 40 4100 4062 suid 102,0 4101 4063 ) … … 4105 4067 font "Courier New,8,0" 4106 4068 ) 4107 xt "39000,3 4200,53500,35000"4069 xt "39000,35000,53500,35800" 4108 4070 st "T1_CS : std_logic" 4109 4071 ) 4110 4072 ) 4111 *12 5(Net4073 *124 (Net 4112 4074 uid 3608,0 4113 4075 decl (Decl 4114 4076 n "T2_CS" 4115 4077 t "std_logic" 4116 o 4 04078 o 41 4117 4079 suid 103,0 4118 4080 ) … … 4122 4084 font "Courier New,8,0" 4123 4085 ) 4124 xt "39000,35 000,53500,35800"4086 xt "39000,35800,53500,36600" 4125 4087 st "T2_CS : std_logic" 4126 4088 ) 4127 4089 ) 4128 *12 6(Net4090 *125 (Net 4129 4091 uid 3610,0 4130 4092 decl (Decl 4131 4093 n "T3_CS" 4132 4094 t "std_logic" 4133 o 4 14095 o 42 4134 4096 suid 104,0 4135 4097 ) … … 4139 4101 font "Courier New,8,0" 4140 4102 ) 4141 xt "39000,3 5800,53500,36600"4103 xt "39000,36600,53500,37400" 4142 4104 st "T3_CS : std_logic" 4143 4105 ) 4144 4106 ) 4145 *12 7(PortIoOut4107 *126 (PortIoOut 4146 4108 uid 3624,0 4147 4109 shape (CompositeShape … … 4187 4149 ) 4188 4150 ) 4189 *12 8(Net4151 *127 (Net 4190 4152 uid 3630,0 4191 4153 decl (Decl 4192 4154 n "S_CLK" 4193 4155 t "std_logic" 4194 o 3 74156 o 38 4195 4157 suid 105,0 4196 4158 ) … … 4200 4162 font "Courier New,8,0" 4201 4163 ) 4202 xt "39000,3 2600,53500,33400"4164 xt "39000,33400,53500,34200" 4203 4165 st "S_CLK : std_logic" 4204 4166 ) 4205 4167 ) 4206 *12 9(Net4168 *128 (Net 4207 4169 uid 3632,0 4208 4170 decl (Decl … … 4210 4172 t "std_logic_vector" 4211 4173 b "(9 DOWNTO 0)" 4212 o 4 34174 o 44 4213 4175 suid 106,0 4214 4176 ) … … 4218 4180 font "Courier New,8,0" 4219 4181 ) 4220 xt "39000,3 7400,63500,38200"4182 xt "39000,38200,63500,39000" 4221 4183 st "W_A : std_logic_vector(9 DOWNTO 0)" 4222 4184 ) 4223 4185 ) 4224 *1 30(Net4186 *129 (Net 4225 4187 uid 3634,0 4226 4188 decl (Decl … … 4228 4190 t "std_logic_vector" 4229 4191 b "(15 DOWNTO 0)" 4230 o 494192 o 50 4231 4193 suid 107,0 4232 4194 ) … … 4236 4198 font "Courier New,8,0" 4237 4199 ) 4238 xt "39000,4 2200,64000,43000"4200 xt "39000,43000,64000,43800" 4239 4201 st "W_D : std_logic_vector(15 DOWNTO 0)" 4240 4202 ) 4241 4203 ) 4242 *13 1(Net4204 *130 (Net 4243 4205 uid 3636,0 4244 4206 decl (Decl 4245 4207 n "W_RES" 4246 4208 t "std_logic" 4247 o 4 64209 o 47 4248 4210 suid 108,0 4249 4211 i "'1'" … … 4254 4216 font "Courier New,8,0" 4255 4217 ) 4256 xt "39000, 39800,68000,40600"4218 xt "39000,40600,68000,41400" 4257 4219 st "W_RES : std_logic := '1'" 4258 4220 ) 4259 4221 ) 4260 *13 2(Net4222 *131 (Net 4261 4223 uid 3638,0 4262 4224 decl (Decl 4263 4225 n "W_RD" 4264 4226 t "std_logic" 4265 o 4 54227 o 46 4266 4228 suid 109,0 4267 4229 i "'1'" … … 4272 4234 font "Courier New,8,0" 4273 4235 ) 4274 xt "39000,39 000,68000,39800"4236 xt "39000,39800,68000,40600" 4275 4237 st "W_RD : std_logic := '1'" 4276 4238 ) 4277 4239 ) 4278 *13 3(Net4240 *132 (Net 4279 4241 uid 3640,0 4280 4242 decl (Decl 4281 4243 n "W_WR" 4282 4244 t "std_logic" 4283 o 4 74245 o 48 4284 4246 suid 110,0 4285 4247 i "'1'" … … 4290 4252 font "Courier New,8,0" 4291 4253 ) 4292 xt "39000,4 0600,68000,41400"4254 xt "39000,41400,68000,42200" 4293 4255 st "W_WR : std_logic := '1'" 4294 4256 ) 4295 4257 ) 4296 *13 4(Net4258 *133 (Net 4297 4259 uid 3642,0 4298 4260 decl (Decl … … 4311 4273 ) 4312 4274 ) 4313 *13 5(Net4275 *134 (Net 4314 4276 uid 3644,0 4315 4277 decl (Decl 4316 4278 n "W_CS" 4317 4279 t "std_logic" 4318 o 4 44280 o 45 4319 4281 suid 112,0 4320 4282 i "'1'" … … 4325 4287 font "Courier New,8,0" 4326 4288 ) 4327 xt "39000,3 8200,68000,39000"4289 xt "39000,39000,68000,39800" 4328 4290 st "W_CS : std_logic := '1'" 4329 4291 ) 4330 4292 ) 4331 *13 6(PortIoInOut4293 *135 (PortIoInOut 4332 4294 uid 3674,0 4333 4295 shape (CompositeShape … … 4371 4333 ) 4372 4334 ) 4373 *13 7(Net4335 *136 (Net 4374 4336 uid 3680,0 4375 4337 decl (Decl 4376 4338 n "MOSI" 4377 4339 t "std_logic" 4378 o 294340 o 30 4379 4341 suid 113,0 4380 4342 i "'0'" … … 4385 4347 font "Courier New,8,0" 4386 4348 ) 4387 xt "39000,2 6200,68000,27000"4349 xt "39000,27000,68000,27800" 4388 4350 st "MOSI : std_logic := '0'" 4389 4351 ) 4390 4352 ) 4391 *13 8(PortIoOut4353 *137 (PortIoOut 4392 4354 uid 3688,0 4393 4355 shape (CompositeShape … … 4433 4395 ) 4434 4396 ) 4435 *13 9(Net4397 *138 (Net 4436 4398 uid 3694,0 4437 4399 decl (Decl … … 4440 4402 preAdd 0 4441 4403 posAdd 0 4442 o 4 84404 o 49 4443 4405 suid 114,0 4444 4406 ) … … 4448 4410 font "Courier New,8,0" 4449 4411 ) 4450 xt "39000,4 1400,53500,42200"4412 xt "39000,42200,53500,43000" 4451 4413 st "MISO : std_logic" 4452 4414 ) 4453 4415 ) 4454 *1 40(HdlText4416 *139 (HdlText 4455 4417 uid 3700,0 4456 4418 optionalChildren [ 4457 *14 1(EmbeddedText4419 *140 (EmbeddedText 4458 4420 uid 3706,0 4459 4421 commentText (CommentText … … 4522 4484 stg "VerticalLayoutStrategy" 4523 4485 textVec [ 4524 *14 2(Text4486 *141 (Text 4525 4487 uid 3703,0 4526 4488 va (VaSet … … 4532 4494 tm "HdlTextNameMgr" 4533 4495 ) 4534 *14 3(Text4496 *142 (Text 4535 4497 uid 3704,0 4536 4498 va (VaSet … … 4558 4520 viewiconposition 0 4559 4521 ) 4560 *14 4(PortIoOut4522 *143 (PortIoOut 4561 4523 uid 3710,0 4562 4524 shape (CompositeShape … … 4602 4564 ) 4603 4565 ) 4604 *14 5(PortIoOut4566 *144 (PortIoOut 4605 4567 uid 3716,0 4606 4568 shape (CompositeShape … … 4646 4608 ) 4647 4609 ) 4648 *14 6(PortIoOut4610 *145 (PortIoOut 4649 4611 uid 3722,0 4650 4612 shape (CompositeShape … … 4690 4652 ) 4691 4653 ) 4692 *14 7(PortIoOut4654 *146 (PortIoOut 4693 4655 uid 3728,0 4694 4656 shape (CompositeShape … … 4734 4696 ) 4735 4697 ) 4736 *14 8(PortIoOut4698 *147 (PortIoOut 4737 4699 uid 3734,0 4738 4700 shape (CompositeShape … … 4778 4740 ) 4779 4741 ) 4780 *14 9(PortIoOut4742 *148 (PortIoOut 4781 4743 uid 3740,0 4782 4744 shape (CompositeShape … … 4822 4784 ) 4823 4785 ) 4824 *1 50(PortIoOut4786 *149 (PortIoOut 4825 4787 uid 3746,0 4826 4788 shape (CompositeShape … … 4866 4828 ) 4867 4829 ) 4868 *15 1(PortIoOut4830 *150 (PortIoOut 4869 4831 uid 3752,0 4870 4832 shape (CompositeShape … … 4910 4872 ) 4911 4873 ) 4912 *15 2(PortIoOut4874 *151 (PortIoOut 4913 4875 uid 3758,0 4914 4876 shape (CompositeShape … … 4954 4916 ) 4955 4917 ) 4956 *15 3(Net4918 *152 (Net 4957 4919 uid 3864,0 4958 4920 decl (Decl 4959 4921 n "TRG_V" 4960 4922 t "std_logic" 4961 o 4 24923 o 43 4962 4924 suid 126,0 4963 4925 ) … … 4967 4929 font "Courier New,8,0" 4968 4930 ) 4969 xt "39000,3 6600,53500,37400"4931 xt "39000,37400,53500,38200" 4970 4932 st "TRG_V : std_logic" 4971 4933 ) 4972 4934 ) 4973 *15 4(Net4935 *153 (Net 4974 4936 uid 3866,0 4975 4937 decl (Decl 4976 4938 n "RS485_C_RE" 4977 4939 t "std_logic" 4978 o 3 24940 o 33 4979 4941 suid 127,0 4980 4942 ) … … 4984 4946 font "Courier New,8,0" 4985 4947 ) 4986 xt "39000,2 8600,53500,29400"4948 xt "39000,29400,53500,30200" 4987 4949 st "RS485_C_RE : std_logic" 4988 4950 ) 4989 4951 ) 4990 *15 5(Net4952 *154 (Net 4991 4953 uid 3868,0 4992 4954 decl (Decl 4993 4955 n "RS485_C_DE" 4994 4956 t "std_logic" 4995 o 3 14957 o 32 4996 4958 suid 128,0 4997 4959 ) … … 5001 4963 font "Courier New,8,0" 5002 4964 ) 5003 xt "39000,2 7800,53500,28600"4965 xt "39000,28600,53500,29400" 5004 4966 st "RS485_C_DE : std_logic" 5005 4967 ) 5006 4968 ) 5007 *15 6(Net4969 *155 (Net 5008 4970 uid 3870,0 5009 4971 decl (Decl 5010 4972 n "RS485_E_RE" 5011 4973 t "std_logic" 5012 o 3 44974 o 35 5013 4975 suid 129,0 5014 4976 ) … … 5018 4980 font "Courier New,8,0" 5019 4981 ) 5020 xt "39000,3 0200,53500,31000"4982 xt "39000,31000,53500,31800" 5021 4983 st "RS485_E_RE : std_logic" 5022 4984 ) 5023 4985 ) 5024 *15 7(Net4986 *156 (Net 5025 4987 uid 3872,0 5026 4988 decl (Decl 5027 4989 n "RS485_E_DE" 5028 4990 t "std_logic" 5029 o 3 34991 o 34 5030 4992 suid 130,0 5031 4993 ) … … 5035 4997 font "Courier New,8,0" 5036 4998 ) 5037 xt "39000, 29400,53500,30200"4999 xt "39000,30200,53500,31000" 5038 5000 st "RS485_E_DE : std_logic" 5039 5001 ) 5040 5002 ) 5041 *15 8(Net5003 *157 (Net 5042 5004 uid 3874,0 5043 5005 decl (Decl 5044 5006 n "DENABLE" 5045 5007 t "std_logic" 5046 o 2 25008 o 23 5047 5009 suid 131,0 5048 5010 i "'0'" … … 5053 5015 font "Courier New,8,0" 5054 5016 ) 5055 xt "39000,2 0600,68000,21400"5017 xt "39000,21400,68000,22200" 5056 5018 st "DENABLE : std_logic := '0'" 5057 5019 ) 5058 5020 ) 5059 *15 9(Net5021 *158 (Net 5060 5022 uid 3876,0 5061 5023 decl (Decl 5062 5024 n "SRIN" 5063 5025 t "std_logic" 5064 o 3 65026 o 37 5065 5027 suid 132,0 5066 5028 ) … … 5070 5032 font "Courier New,8,0" 5071 5033 ) 5072 xt "39000,3 1800,53500,32600"5034 xt "39000,32600,53500,33400" 5073 5035 st "SRIN : std_logic" 5074 5036 ) 5075 5037 ) 5076 *1 60(Net5038 *159 (Net 5077 5039 uid 3878,0 5078 5040 decl (Decl 5079 5041 n "EE_CS" 5080 5042 t "std_logic" 5081 o 2 75043 o 28 5082 5044 suid 133,0 5083 5045 ) … … 5087 5049 font "Courier New,8,0" 5088 5050 ) 5089 xt "39000,2 4600,53500,25400"5051 xt "39000,25400,53500,26200" 5090 5052 st "EE_CS : std_logic" 5091 5053 ) 5092 5054 ) 5093 *16 1(Net5055 *160 (Net 5094 5056 uid 3880,0 5095 5057 decl (Decl … … 5097 5059 t "std_logic_vector" 5098 5060 b "( 2 DOWNTO 0 )" 5099 o 2 85061 o 29 5100 5062 suid 134,0 5101 5063 i "(others => '1')" … … 5106 5068 font "Courier New,8,0" 5107 5069 ) 5108 xt "39000,2 5400,74000,26200"5070 xt "39000,26200,74000,27000" 5109 5071 st "LED : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')" 5110 5072 ) 5111 5073 ) 5112 *16 2(PortIoOut5074 *161 (PortIoOut 5113 5075 uid 3995,0 5114 5076 shape (CompositeShape … … 5155 5117 ) 5156 5118 ) 5157 *16 3(PortIoOut5119 *162 (PortIoOut 5158 5120 uid 4001,0 5159 5121 shape (CompositeShape … … 5200 5162 ) 5201 5163 ) 5202 *16 4(PortIoOut5164 *163 (PortIoOut 5203 5165 uid 4007,0 5204 5166 shape (CompositeShape … … 5245 5207 ) 5246 5208 ) 5247 *16 5(PortIoOut5209 *164 (PortIoOut 5248 5210 uid 4013,0 5249 5211 shape (CompositeShape … … 5290 5252 ) 5291 5253 ) 5292 *16 6(PortIoOut5254 *165 (PortIoOut 5293 5255 uid 4916,0 5294 5256 shape (CompositeShape … … 5334 5296 ) 5335 5297 ) 5336 *16 7(Net5298 *166 (Net 5337 5299 uid 5320,0 5338 5300 decl (Decl … … 5340 5302 t "std_logic_vector" 5341 5303 b "(7 DOWNTO 0)" 5342 o 2 55304 o 26 5343 5305 suid 141,0 5344 5306 i "(OTHERS => '0')" … … 5349 5311 font "Courier New,8,0" 5350 5312 ) 5351 xt "39000,23 000,74000,23800"5313 xt "39000,23800,74000,24600" 5352 5314 st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 5353 5315 ) 5354 5316 ) 5355 *16 8(PortIoIn5317 *167 (PortIoIn 5356 5318 uid 5650,0 5357 5319 shape (CompositeShape … … 5366 5328 sl 0 5367 5329 ro 270 5368 xt " -30000,88625,-28500,89375"5330 xt "9000,78625,10500,79375" 5369 5331 ) 5370 5332 (Line … … 5372 5334 sl 0 5373 5335 ro 270 5374 xt " -28500,89000,-28000,89000"5375 pts [ 5376 " -28500,89000"5377 " -28000,89000"5336 xt "10500,79000,11000,79000" 5337 pts [ 5338 "10500,79000" 5339 "11000,79000" 5378 5340 ] 5379 5341 ) … … 5390 5352 va (VaSet 5391 5353 ) 5392 xt " -35500,88500,-31000,89500"5354 xt "3500,78500,8000,79500" 5393 5355 st "TEST_TRG" 5394 5356 ju 2 5395 blo " -31000,89300"5396 tm "WireNameMgr" 5397 ) 5398 ) 5399 ) 5400 *16 9(Net5357 blo "8000,79300" 5358 tm "WireNameMgr" 5359 ) 5360 ) 5361 ) 5362 *168 (Net 5401 5363 uid 5662,0 5402 5364 decl (Decl … … 5415 5377 ) 5416 5378 ) 5417 *1 70(Net5379 *169 (Net 5418 5380 uid 6138,0 5419 5381 decl (Decl 5420 5382 n "TRG_OR" 5421 5383 t "std_logic" 5422 o 5 35384 o 54 5423 5385 suid 146,0 5424 5386 ) … … 5428 5390 font "Courier New,8,0" 5429 5391 ) 5430 xt "39000,4 6400,57000,47200"5392 xt "39000,47200,57000,48000" 5431 5393 st "SIGNAL TRG_OR : std_logic" 5432 5394 ) 5433 5395 ) 5434 *171 (SaComponent 5435 uid 6250,0 5436 optionalChildren [ 5437 *172 (CptPort 5438 uid 6235,0 5439 ps "OnEdgeStrategy" 5440 shape (Triangle 5441 uid 6236,0 5442 ro 90 5443 va (VaSet 5444 vasetType 1 5445 fg "0,65535,0" 5446 ) 5447 xt "-11750,87625,-11000,88375" 5448 ) 5449 tg (CPTG 5450 uid 6237,0 5451 ps "CptPortTextPlaceStrategy" 5452 stg "VerticalLayoutStrategy" 5453 f (Text 5454 uid 6238,0 5455 va (VaSet 5456 ) 5457 xt "-10000,87500,-8700,88500" 5458 st "clk" 5459 blo "-10000,88300" 5460 ) 5461 ) 5462 thePort (LogicalPort 5463 decl (Decl 5464 n "clk" 5465 t "STD_LOGIC" 5466 preAdd 0 5467 posAdd 0 5468 o 1 5469 suid 1,0 5470 ) 5471 ) 5472 ) 5473 *173 (CptPort 5474 uid 6239,0 5475 ps "OnEdgeStrategy" 5476 shape (Triangle 5477 uid 6240,0 5478 ro 90 5479 va (VaSet 5480 vasetType 1 5481 fg "0,65535,0" 5482 ) 5483 xt "-11750,88625,-11000,89375" 5484 ) 5485 tg (CPTG 5486 uid 6241,0 5487 ps "CptPortTextPlaceStrategy" 5488 stg "VerticalLayoutStrategy" 5489 f (Text 5490 uid 6242,0 5491 va (VaSet 5492 ) 5493 xt "-10000,88500,-5800,89500" 5494 st "trigger_in" 5495 blo "-10000,89300" 5496 ) 5497 ) 5498 thePort (LogicalPort 5499 decl (Decl 5500 n "trigger_in" 5501 t "STD_LOGIC" 5502 prec "-- rst : in STD_LOGIC;" 5503 preAdd 0 5504 posAdd 0 5505 o 2 5506 suid 2,0 5507 ) 5508 ) 5509 ) 5510 *174 (CptPort 5511 uid 6243,0 5512 ps "OnEdgeStrategy" 5513 shape (Triangle 5514 uid 6244,0 5515 ro 90 5516 va (VaSet 5517 vasetType 1 5518 fg "0,65535,0" 5519 ) 5520 xt "1000,88625,1750,89375" 5521 ) 5522 tg (CPTG 5523 uid 6245,0 5524 ps "CptPortTextPlaceStrategy" 5525 stg "RightVerticalLayoutStrategy" 5526 f (Text 5527 uid 6246,0 5528 va (VaSet 5529 ) 5530 xt "-4600,88500,0,89500" 5531 st "trigger_out" 5532 ju 2 5533 blo "0,89300" 5534 ) 5535 ) 5536 thePort (LogicalPort 5537 m 1 5538 decl (Decl 5539 n "trigger_out" 5540 t "STD_LOGIC" 5541 preAdd 0 5542 posAdd 0 5543 o 3 5544 suid 3,0 5545 i "'0'" 5546 ) 5547 ) 5548 ) 5549 ] 5550 shape (Rectangle 5551 uid 6251,0 5552 va (VaSet 5553 vasetType 1 5554 fg "0,65535,0" 5555 lineColor "0,32896,0" 5556 lineWidth 2 5557 ) 5558 xt "-11000,87000,1000,92000" 5559 ) 5560 oxt "25000,13000,37000,18000" 5561 ttg (MlTextGroup 5562 uid 6252,0 5563 ps "CenterOffsetStrategy" 5564 stg "VerticalLayoutStrategy" 5565 textVec [ 5566 *175 (Text 5567 uid 6253,0 5568 va (VaSet 5569 font "Arial,8,1" 5570 ) 5571 xt "-10800,92000,-4200,93000" 5572 st "FACT_FAD_LIB" 5573 blo "-10800,92800" 5574 tm "BdLibraryNameMgr" 5575 ) 5576 *176 (Text 5577 uid 6254,0 5578 va (VaSet 5579 font "Arial,8,1" 5580 ) 5581 xt "-10800,93000,-6400,94000" 5582 st "debouncer" 5583 blo "-10800,93800" 5584 tm "CptNameMgr" 5585 ) 5586 *177 (Text 5587 uid 6255,0 5588 va (VaSet 5589 font "Arial,8,1" 5590 ) 5591 xt "-10800,94000,-9800,95000" 5592 st "I0" 5593 blo "-10800,94800" 5594 tm "InstanceNameMgr" 5595 ) 5596 ] 5597 ) 5598 ga (GenericAssociation 5599 uid 6256,0 5600 ps "EdgeToEdgeStrategy" 5601 matrix (Matrix 5602 uid 6257,0 5603 text (MLText 5604 uid 6258,0 5605 va (VaSet 5606 font "Courier New,8,0" 5607 ) 5608 xt "-11000,86200,4000,87000" 5609 st "WIDTH = 17 ( INTEGER ) " 5610 ) 5611 header "" 5612 ) 5613 elements [ 5614 (GiElement 5615 name "WIDTH" 5616 type "INTEGER" 5617 value "17" 5618 ) 5619 ] 5620 ) 5621 viewicon (ZoomableIcon 5622 uid 6259,0 5623 sl 0 5624 va (VaSet 5625 vasetType 1 5626 fg "49152,49152,49152" 5627 ) 5628 xt "-10750,90250,-9250,91750" 5629 iconName "VhdlFileViewIcon.png" 5630 iconMaskName "VhdlFileViewIcon.msk" 5631 ftype 10 5632 ) 5633 ordering 1 5634 viewiconposition 0 5635 portVis (PortSigDisplay 5636 ) 5637 archFileType "UNKNOWN" 5638 ) 5639 *178 (Net 5640 uid 6278,0 5641 decl (Decl 5642 n "trigger_out" 5643 t "STD_LOGIC" 5644 preAdd 0 5645 posAdd 0 5646 o 60 5647 suid 147,0 5648 i "'0'" 5649 ) 5650 declText (MLText 5651 uid 6279,0 5652 va (VaSet 5653 font "Courier New,8,0" 5654 ) 5655 xt "39000,52000,71500,52800" 5656 st "SIGNAL trigger_out : STD_LOGIC := '0'" 5657 ) 5658 ) 5659 *179 (Net 5660 uid 6326,0 5661 decl (Decl 5662 n "not_TEST_TRG" 5663 t "STD_LOGIC" 5664 o 58 5665 suid 148,0 5666 ) 5667 declText (MLText 5668 uid 6327,0 5669 va (VaSet 5670 font "Courier New,8,0" 5671 ) 5672 xt "39000,50400,57000,51200" 5673 st "SIGNAL not_TEST_TRG : STD_LOGIC" 5674 ) 5675 ) 5676 *180 (MWC 5677 uid 6539,0 5678 optionalChildren [ 5679 *181 (CptPort 5680 uid 6526,0 5681 optionalChildren [ 5682 *182 (Line 5683 uid 6530,0 5684 layer 5 5685 sl 0 5686 va (VaSet 5687 vasetType 3 5688 ) 5689 xt "-22000,89000,-20999,89000" 5690 pts [ 5691 "-22000,89000" 5692 "-20999,89000" 5693 ] 5694 ) 5695 ] 5696 ps "OnEdgeStrategy" 5697 shape (Triangle 5698 uid 6527,0 5699 ro 90 5700 va (VaSet 5701 vasetType 1 5702 isHidden 1 5703 fg "0,65535,65535" 5704 ) 5705 xt "-22750,88625,-22000,89375" 5706 ) 5707 tg (CPTG 5708 uid 6528,0 5709 ps "CptPortTextPlaceStrategy" 5710 stg "VerticalLayoutStrategy" 5711 f (Text 5712 uid 6529,0 5713 sl 0 5714 va (VaSet 5715 isHidden 1 5716 font "arial,8,0" 5717 ) 5718 xt "-25000,88500,-23600,89500" 5719 st "din" 5720 blo "-25000,89300" 5721 ) 5722 s (Text 5723 uid 6548,0 5724 sl 0 5725 va (VaSet 5726 font "arial,8,0" 5727 ) 5728 xt "-25000,89500,-25000,89500" 5729 blo "-25000,89500" 5730 ) 5731 ) 5732 thePort (LogicalPort 5733 decl (Decl 5734 n "din" 5735 t "std_logic" 5736 o 11 5737 suid 1,0 5738 ) 5739 ) 5740 ) 5741 *183 (CptPort 5742 uid 6531,0 5743 optionalChildren [ 5744 *184 (Line 5745 uid 6535,0 5746 layer 5 5747 sl 0 5748 va (VaSet 5749 vasetType 3 5750 ) 5751 xt "-17249,89000,-17000,89000" 5752 pts [ 5753 "-17000,89000" 5754 "-17249,89000" 5755 ] 5756 ) 5757 *185 (Circle 5758 uid 6536,0 5759 va (VaSet 5760 vasetType 1 5761 fg "65535,65535,65535" 5762 lineColor "26368,26368,26368" 5763 ) 5764 xt "-17999,88625,-17249,89375" 5765 radius 375 5766 ) 5767 ] 5768 ps "OnEdgeStrategy" 5769 shape (Triangle 5770 uid 6532,0 5771 ro 90 5772 va (VaSet 5773 vasetType 1 5774 isHidden 1 5775 fg "0,65535,65535" 5776 ) 5777 xt "-17000,88625,-16250,89375" 5778 ) 5779 tg (CPTG 5780 uid 6533,0 5781 ps "CptPortTextPlaceStrategy" 5782 stg "RightVerticalLayoutStrategy" 5783 f (Text 5784 uid 6534,0 5785 sl 0 5786 va (VaSet 5787 isHidden 1 5788 font "arial,8,0" 5789 ) 5790 xt "-15050,88500,-13250,89500" 5791 st "dout" 5792 ju 2 5793 blo "-13250,89300" 5794 ) 5795 s (Text 5796 uid 6549,0 5797 sl 0 5798 va (VaSet 5799 font "arial,8,0" 5800 ) 5801 xt "-13250,89500,-13250,89500" 5802 ju 2 5803 blo "-13250,89500" 5804 ) 5805 ) 5806 thePort (LogicalPort 5807 m 1 5808 decl (Decl 5809 n "dout" 5810 t "STD_LOGIC" 5811 o 58 5812 suid 2,0 5813 ) 5814 ) 5815 ) 5816 *186 (CommentGraphic 5817 uid 6537,0 5818 shape (CustomPolygon 5819 pts [ 5820 "-21000,87000" 5821 "-18000,89000" 5822 "-21000,91000" 5823 "-21000,87000" 5824 ] 5825 uid 6538,0 5826 layer 0 5827 sl 0 5828 va (VaSet 5829 vasetType 1 5830 fg "0,65535,65535" 5831 bg "0,65535,65535" 5832 lineColor "26368,26368,26368" 5833 ) 5834 xt "-21000,87000,-18000,91000" 5835 ) 5836 oxt "7000,6000,10000,10000" 5837 ) 5838 ] 5839 shape (Rectangle 5840 uid 6540,0 5841 va (VaSet 5842 vasetType 1 5843 transparent 1 5844 fg "0,65535,0" 5845 lineColor "65535,65535,65535" 5846 lineWidth -1 5847 ) 5848 xt "-22000,87000,-17000,91000" 5849 fos 1 5850 ) 5851 showPorts 0 5852 oxt "6000,6000,11000,10000" 5853 ttg (MlTextGroup 5854 uid 6541,0 5855 ps "CenterOffsetStrategy" 5856 stg "VerticalLayoutStrategy" 5857 textVec [ 5858 *187 (Text 5859 uid 6542,0 5860 va (VaSet 5861 isHidden 1 5862 font "arial,8,0" 5863 ) 5864 xt "-19650,89100,-14850,90100" 5865 st "moduleware" 5866 blo "-19650,89900" 5867 ) 5868 *188 (Text 5869 uid 6543,0 5870 va (VaSet 5871 font "arial,8,0" 5872 ) 5873 xt "-19650,90100,-18350,91100" 5874 st "inv" 5875 blo "-19650,90900" 5876 ) 5877 *189 (Text 5878 uid 6544,0 5879 va (VaSet 5880 font "arial,8,0" 5881 ) 5882 xt "-19650,91100,-18650,92100" 5883 st "I1" 5884 blo "-19650,91900" 5885 tm "InstanceNameMgr" 5886 ) 5887 ] 5888 ) 5889 ga (GenericAssociation 5890 uid 6545,0 5891 ps "EdgeToEdgeStrategy" 5892 matrix (Matrix 5893 uid 6546,0 5894 text (MLText 5895 uid 6547,0 5896 va (VaSet 5897 font "arial,8,0" 5898 ) 5899 xt "-25000,68400,-25000,68400" 5900 ) 5901 header "" 5902 ) 5903 elements [ 5904 ] 5905 ) 5906 sed 1 5907 awe 1 5908 portVis (PortSigDisplay 5909 disp 1 5910 sN 0 5911 sTC 0 5912 selT 0 5913 ) 5914 prms (Property 5915 pclass "params" 5916 pname "params" 5917 ptn "String" 5918 ) 5919 visOptions (mwParamsVisibilityOptions 5920 ) 5921 ) 5922 *190 (MWC 5396 *170 (MWC 5923 5397 uid 6586,0 5924 5398 optionalChildren [ 5925 *1 91 (CptPort5399 *171 (CptPort 5926 5400 uid 6550,0 5927 5401 optionalChildren [ 5928 *1 92 (Line5402 *172 (Line 5929 5403 uid 6554,0 5930 5404 layer 5 … … 5970 5444 decl (Decl 5971 5445 n "din1" 5972 t "STD_LOGIC" 5973 preAdd 0 5974 posAdd 0 5975 o 60 5446 t "std_logic" 5447 o 11 5976 5448 suid 1,0 5977 i "'0'" 5978 ) 5979 ) 5980 ) 5981 *193 (CptPort 5449 ) 5450 ) 5451 ) 5452 *173 (CptPort 5982 5453 uid 6555,0 5983 5454 optionalChildren [ 5984 *1 94 (Property5455 *174 (Property 5985 5456 uid 6559,0 5986 5457 pclass "_MW_GEOM_" … … 5988 5459 ptn "String" 5989 5460 ) 5990 *1 95 (Line5461 *175 (Line 5991 5462 uid 6560,0 5992 5463 layer 5 … … 6035 5506 n "dout" 6036 5507 t "std_logic" 6037 o 5 35508 o 54 6038 5509 suid 2,0 6039 5510 ) 6040 5511 ) 6041 5512 ) 6042 *1 96 (CptPort5513 *176 (CptPort 6043 5514 uid 6561,0 6044 5515 optionalChildren [ 6045 *1 97 (Line5516 *177 (Line 6046 5517 uid 6565,0 6047 5518 layer 5 … … 6093 5564 ) 6094 5565 ) 6095 *1 98 (CommentGraphic5566 *178 (CommentGraphic 6096 5567 uid 6566,0 6097 5568 shape (Arc2D … … 6114 5585 oxt "7000,6003,11000,8000" 6115 5586 ) 6116 *1 99 (CommentGraphic5587 *179 (CommentGraphic 6117 5588 uid 6568,0 6118 5589 shape (Arc2D … … 6135 5606 oxt "6996,8005,11000,10000" 6136 5607 ) 6137 * 200 (Grouping5608 *180 (Grouping 6138 5609 uid 6570,0 6139 5610 optionalChildren [ 6140 * 201 (CommentGraphic5611 *181 (CommentGraphic 6141 5612 uid 6572,0 6142 5613 optionalChildren [ 6143 * 202 (Property5614 *182 (Property 6144 5615 uid 6574,0 6145 5616 pclass "_MW_GEOM_" … … 6172 5643 oxt "7000,6000,11000,9998" 6173 5644 ) 6174 * 203 (CommentGraphic5645 *183 (CommentGraphic 6175 5646 uid 6575,0 6176 5647 optionalChildren [ 6177 * 204 (Property5648 *184 (Property 6178 5649 uid 6577,0 6179 5650 pclass "_MW_GEOM_" … … 6217 5688 oxt "7000,6000,11000,10000" 6218 5689 ) 6219 * 205 (CommentGraphic5690 *185 (CommentGraphic 6220 5691 uid 6578,0 6221 5692 shape (PolyLine2D … … 6236 5707 oxt "11000,8000,11000,8000" 6237 5708 ) 6238 * 206 (CommentGraphic5709 *186 (CommentGraphic 6239 5710 uid 6580,0 6240 5711 optionalChildren [ 6241 * 207 (Property5712 *187 (Property 6242 5713 uid 6582,0 6243 5714 pclass "_MW_GEOM_" … … 6263 5734 oxt "7000,6000,7000,6000" 6264 5735 ) 6265 * 208 (CommentGraphic5736 *188 (CommentGraphic 6266 5737 uid 6583,0 6267 5738 optionalChildren [ 6268 * 209 (Property5739 *189 (Property 6269 5740 uid 6585,0 6270 5741 pclass "_MW_GEOM_" … … 6309 5780 stg "VerticalLayoutStrategy" 6310 5781 textVec [ 6311 * 210 (Text5782 *190 (Text 6312 5783 uid 6589,0 6313 5784 va (VaSet … … 6319 5790 blo "15500,77300" 6320 5791 ) 6321 * 211 (Text5792 *191 (Text 6322 5793 uid 6590,0 6323 5794 va (VaSet … … 6328 5799 blo "15500,78300" 6329 5800 ) 6330 * 212 (Text5801 *192 (Text 6331 5802 uid 6591,0 6332 5803 va (VaSet … … 6373 5844 ) 6374 5845 ) 6375 * 213 (PortIoIn5846 *193 (PortIoIn 6376 5847 uid 6781,0 6377 5848 shape (CompositeShape … … 6418 5889 ) 6419 5890 ) 6420 * 214 (Net5891 *194 (Net 6421 5892 uid 6793,0 6422 5893 decl (Decl … … 6436 5907 ) 6437 5908 ) 6438 * 215 (PortIoOut5909 *195 (PortIoOut 6439 5910 uid 6874,0 6440 5911 shape (CompositeShape … … 6480 5951 ) 6481 5952 ) 6482 * 216 (Net5953 *196 (Net 6483 5954 uid 6886,0 6484 5955 decl (Decl … … 6486 5957 t "std_logic_vector" 6487 5958 b "(3 DOWNTO 0)" 6488 o 2 65959 o 27 6489 5960 suid 154,0 6490 5961 i "(others => '0')" … … 6495 5966 font "Courier New,8,0" 6496 5967 ) 6497 xt "39000,2 3800,74000,24600"5968 xt "39000,24600,74000,25400" 6498 5969 st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0')" 6499 5970 ) 6500 5971 ) 6501 * 217 (HdlText5972 *197 (HdlText 6502 5973 uid 6888,0 6503 5974 optionalChildren [ 6504 * 218 (EmbeddedText5975 *198 (EmbeddedText 6505 5976 uid 6894,0 6506 5977 commentText (CommentText … … 6550 6021 stg "VerticalLayoutStrategy" 6551 6022 textVec [ 6552 * 219 (Text6023 *199 (Text 6553 6024 uid 6891,0 6554 6025 va (VaSet … … 6560 6031 tm "HdlTextNameMgr" 6561 6032 ) 6562 *2 20 (Text6033 *200 (Text 6563 6034 uid 6892,0 6564 6035 va (VaSet … … 6586 6057 viewiconposition 0 6587 6058 ) 6588 *2 21 (HdlText6059 *201 (HdlText 6589 6060 uid 7092,0 6590 6061 optionalChildren [ 6591 *2 22 (EmbeddedText6062 *202 (EmbeddedText 6592 6063 uid 7098,0 6593 6064 commentText (CommentText … … 6602 6073 lineWidth 2 6603 6074 ) 6604 xt "2 7000,137000,45000,145000"6075 xt "26000,137000,46000,143000" 6605 6076 ) 6606 6077 oxt "0,0,18000,5000" … … 6609 6080 va (VaSet 6610 6081 ) 6611 xt "2 7200,137200,39400,142200"6082 xt "26200,137200,40000,141200" 6612 6083 st " 6613 6084 -- eb2 8 6614 A1_T(0) <= dummy; 6615 A1_T(1) <= RSRLOAD; 6616 A1_T(2) <= D0_SROUT; 6617 A1_T(3) <= D1_SROUT; 6085 A1_T(3 downto 0) <= drs_channel_id; 6086 D_A <= drs_channel_id; 6087 A1_T(4) <= TRG_OR; 6618 6088 " 6619 6089 tm "HdlTextMgr" 6620 6090 wrapOption 3 6621 visibleHeight 80006622 visibleWidth 180006091 visibleHeight 6000 6092 visibleWidth 20000 6623 6093 ) 6624 6094 ) … … 6641 6111 stg "VerticalLayoutStrategy" 6642 6112 textVec [ 6643 *2 23 (Text6113 *203 (Text 6644 6114 uid 7095,0 6645 6115 va (VaSet … … 6651 6121 tm "HdlTextNameMgr" 6652 6122 ) 6653 *2 24 (Text6123 *204 (Text 6654 6124 uid 7096,0 6655 6125 va (VaSet … … 6677 6147 viewiconposition 0 6678 6148 ) 6679 *2 25 (PortIoOut6149 *205 (PortIoOut 6680 6150 uid 7138,0 6681 6151 shape (CompositeShape … … 6721 6191 ) 6722 6192 ) 6723 *2 26 (Net6193 *206 (Net 6724 6194 uid 7150,0 6725 6195 decl (Decl 6726 6196 n "A1_T" 6727 6197 t "std_logic_vector" 6728 b "( 3DOWNTO 0)"6729 o 1 56198 b "(7 DOWNTO 0)" 6199 o 16 6730 6200 suid 155,0 6201 i "(OTHERS => '0')" 6731 6202 ) 6732 6203 declText (MLText … … 6735 6206 font "Courier New,8,0" 6736 6207 ) 6737 xt "39000,15 000,63500,15800"6738 st "A1_T : std_logic_vector( 3 DOWNTO 0)"6739 ) 6740 ) 6741 *2 27 (Net6208 xt "39000,15800,74000,16600" 6209 st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 6210 ) 6211 ) 6212 *207 (Net 6742 6213 uid 7485,0 6743 6214 decl (Decl 6744 6215 n "dummy" 6745 6216 t "std_logic" 6746 o 606217 o 59 6747 6218 suid 157,0 6748 6219 ) … … 6752 6223 font "Courier New,8,0" 6753 6224 ) 6754 xt "39000, 49600,57000,50400"6225 xt "39000,51200,57000,52000" 6755 6226 st "SIGNAL dummy : std_logic" 6756 6227 ) 6757 6228 ) 6758 *2 28 (MWC6229 *208 (MWC 6759 6230 uid 7652,0 6760 6231 optionalChildren [ 6761 *2 29 (CptPort6232 *209 (CptPort 6762 6233 uid 7632,0 6763 6234 optionalChildren [ 6764 *2 30 (Line6235 *210 (Line 6765 6236 uid 7636,0 6766 6237 layer 5 … … 6816 6287 n "s" 6817 6288 t "std_logic" 6818 o 606289 o 59 6819 6290 suid 1,0 6820 6291 ) 6821 6292 ) 6822 6293 ) 6823 *2 31 (CptPort6294 *211 (CptPort 6824 6295 uid 7637,0 6825 6296 optionalChildren [ 6826 *2 32 (Line6297 *212 (Line 6827 6298 uid 7641,0 6828 6299 layer 5 … … 6881 6352 n "t" 6882 6353 t "std_logic" 6883 o 2 16354 o 22 6884 6355 suid 2,0 6885 6356 ) 6886 6357 ) 6887 6358 ) 6888 *2 33 (CommentGraphic6359 *213 (CommentGraphic 6889 6360 uid 7642,0 6890 6361 shape (PolyLine2D … … 6907 6378 oxt "6000,6000,7000,7000" 6908 6379 ) 6909 *2 34 (CommentGraphic6380 *214 (CommentGraphic 6910 6381 uid 7644,0 6911 6382 shape (PolyLine2D … … 6928 6399 oxt "6000,7000,7000,8000" 6929 6400 ) 6930 *2 35 (CommentGraphic6401 *215 (CommentGraphic 6931 6402 uid 7646,0 6932 6403 shape (PolyLine2D … … 6949 6420 oxt "6988,7329,7988,7329" 6950 6421 ) 6951 *2 36 (CommentGraphic6422 *216 (CommentGraphic 6952 6423 uid 7648,0 6953 6424 shape (PolyLine2D … … 6968 6439 oxt "8000,7000,9000,7000" 6969 6440 ) 6970 *2 37 (CommentGraphic6441 *217 (CommentGraphic 6971 6442 uid 7650,0 6972 6443 shape (PolyLine2D … … 7009 6480 stg "VerticalLayoutStrategy" 7010 6481 textVec [ 7011 *2 38 (Text6482 *218 (Text 7012 6483 uid 7655,0 7013 6484 va (VaSet … … 7019 6490 blo "90350,83900" 7020 6491 ) 7021 *2 39 (Text6492 *219 (Text 7022 6493 uid 7656,0 7023 6494 va (VaSet … … 7028 6499 blo "90350,84900" 7029 6500 ) 7030 *2 40 (Text6501 *220 (Text 7031 6502 uid 7657,0 7032 6503 va (VaSet … … 7073 6544 ) 7074 6545 ) 7075 *241 (Wire 6546 *221 (Net 6547 uid 8851,0 6548 decl (Decl 6549 n "drs_channel_id" 6550 t "std_logic_vector" 6551 b "(3 downto 0)" 6552 o 58 6553 suid 159,0 6554 i "(others => '0')" 6555 ) 6556 declText (MLText 6557 uid 8852,0 6558 va (VaSet 6559 font "Courier New,8,0" 6560 ) 6561 xt "39000,50400,77500,51200" 6562 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 6563 ) 6564 ) 6565 *222 (Net 6566 uid 9201,0 6567 decl (Decl 6568 n "A0_T" 6569 t "std_logic_vector" 6570 b "(7 DOWNTO 0)" 6571 o 15 6572 suid 162,0 6573 i "(OTHERS => '0')" 6574 ) 6575 declText (MLText 6576 uid 9202,0 6577 va (VaSet 6578 font "Courier New,8,0" 6579 ) 6580 xt "39000,15000,74000,15800" 6581 st "A0_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 6582 ) 6583 ) 6584 *223 (PortIoOut 6585 uid 9294,0 6586 shape (CompositeShape 6587 uid 9295,0 6588 va (VaSet 6589 vasetType 1 6590 fg "0,0,32768" 6591 ) 6592 optionalChildren [ 6593 (Pentagon 6594 uid 9296,0 6595 sl 0 6596 ro 270 6597 xt "64500,139625,66000,140375" 6598 ) 6599 (Line 6600 uid 9297,0 6601 sl 0 6602 ro 270 6603 xt "64000,140000,64500,140000" 6604 pts [ 6605 "64000,140000" 6606 "64500,140000" 6607 ] 6608 ) 6609 ] 6610 ) 6611 stc 0 6612 sf 1 6613 tg (WTG 6614 uid 9298,0 6615 ps "PortIoTextPlaceStrategy" 6616 stg "STSignalDisplayStrategy" 6617 f (Text 6618 uid 9299,0 6619 va (VaSet 6620 ) 6621 xt "67000,139500,69200,140500" 6622 st "A0_T" 6623 blo "67000,140300" 6624 tm "WireNameMgr" 6625 ) 6626 ) 6627 ) 6628 *224 (Net 6629 uid 9500,0 6630 decl (Decl 6631 n "CLK_50" 6632 t "std_logic" 6633 o 52 6634 suid 163,0 6635 ) 6636 declText (MLText 6637 uid 9501,0 6638 va (VaSet 6639 font "Courier New,8,0" 6640 ) 6641 xt "39000,45600,57000,46400" 6642 st "SIGNAL CLK_50 : std_logic" 6643 ) 6644 ) 6645 *225 (Wire 7076 6646 uid 245,0 7077 6647 shape (OrthoPolyLine … … 7110 6680 ) 7111 6681 ) 7112 on & 707113 ) 7114 *2 42(Wire6682 on &69 6683 ) 6684 *226 (Wire 7115 6685 uid 277,0 7116 6686 shape (OrthoPolyLine … … 7150 6720 on &53 7151 6721 ) 7152 *2 43(Wire6722 *227 (Wire 7153 6723 uid 285,0 7154 6724 shape (OrthoPolyLine … … 7188 6758 on &54 7189 6759 ) 7190 *2 44(Wire6760 *228 (Wire 7191 6761 uid 362,0 7192 6762 shape (OrthoPolyLine … … 7201 6771 ] 7202 6772 ) 7203 start &7 86773 start &77 7204 6774 end &16 7205 6775 sat 32 … … 7224 6794 ) 7225 6795 ) 7226 on &7 97227 ) 7228 *2 45(Wire6796 on &78 6797 ) 6798 *229 (Wire 7229 6799 uid 418,0 7230 6800 shape (OrthoPolyLine … … 7262 6832 ) 7263 6833 ) 7264 on &13 17265 ) 7266 *2 46(Wire6834 on &130 6835 ) 6836 *230 (Wire 7267 6837 uid 426,0 7268 6838 shape (OrthoPolyLine … … 7302 6872 ) 7303 6873 ) 7304 on &12 97305 ) 7306 *2 47(Wire6874 on &128 6875 ) 6876 *231 (Wire 7307 6877 uid 434,0 7308 6878 shape (OrthoPolyLine … … 7340 6910 ) 7341 6911 ) 7342 on &13 57343 ) 7344 *2 48(Wire6912 on &134 6913 ) 6914 *232 (Wire 7345 6915 uid 442,0 7346 6916 shape (OrthoPolyLine … … 7380 6950 ) 7381 6951 ) 7382 on &1 307383 ) 7384 *2 49(Wire6952 on &129 6953 ) 6954 *233 (Wire 7385 6955 uid 450,0 7386 6956 shape (OrthoPolyLine … … 7418 6988 ) 7419 6989 ) 7420 on &13 47421 ) 7422 *2 50(Wire6990 on &133 6991 ) 6992 *234 (Wire 7423 6993 uid 458,0 7424 6994 shape (OrthoPolyLine … … 7456 7026 ) 7457 7027 ) 7458 on &13 27459 ) 7460 *2 51(Wire7028 on &131 7029 ) 7030 *235 (Wire 7461 7031 uid 466,0 7462 7032 shape (OrthoPolyLine … … 7494 7064 ) 7495 7065 ) 7496 on &13 37497 ) 7498 *2 52(Wire7066 on &132 7067 ) 7068 *236 (Wire 7499 7069 uid 1467,0 7500 7070 shape (OrthoPolyLine … … 7509 7079 ] 7510 7080 ) 7511 start &8 27081 start &81 7512 7082 end &28 7513 7083 sat 2 … … 7532 7102 on &62 7533 7103 ) 7534 *2 53(Wire7104 *237 (Wire 7535 7105 uid 1730,0 7536 7106 shape (OrthoPolyLine … … 7546 7116 ] 7547 7117 ) 7548 start & 807118 start &79 7549 7119 end &29 7550 7120 sat 32 … … 7570 7140 ) 7571 7141 ) 7572 on &8 17573 ) 7574 *2 54(Wire7142 on &80 7143 ) 7144 *238 (Wire 7575 7145 uid 1833,0 7576 7146 shape (OrthoPolyLine … … 7580 7150 lineWidth 2 7581 7151 ) 7582 xt "21000,109000,51250,109000" 7583 pts [ 7584 "51250,109000" 7585 "21000,109000" 7586 ] 7587 ) 7588 start &30 7589 end &110 7152 xt "6000,134000,31000,134000" 7153 pts [ 7154 "31000,134000" 7155 "6000,134000" 7156 ] 7157 ) 7158 start &201 7159 end &109 7160 sat 2 7161 eat 32 7162 sty 1 7163 stc 0 7164 st 0 7165 sf 1 7166 si 0 7167 tg (WTG 7168 uid 1837,0 7169 ps "ConnStartEndStrategy" 7170 stg "STSignalDisplayStrategy" 7171 f (Text 7172 uid 1838,0 7173 va (VaSet 7174 isHidden 1 7175 ) 7176 xt "7000,133000,8900,134000" 7177 st "D_A" 7178 blo "7000,133800" 7179 tm "WireNameMgr" 7180 ) 7181 ) 7182 on &110 7183 ) 7184 *239 (Wire 7185 uid 1841,0 7186 shape (OrthoPolyLine 7187 uid 1842,0 7188 va (VaSet 7189 vasetType 3 7190 ) 7191 xt "21000,110000,51250,110000" 7192 pts [ 7193 "51250,110000" 7194 "21000,110000" 7195 ] 7196 ) 7197 start &31 7198 end &111 7199 sat 32 7200 eat 32 7201 stc 0 7202 st 0 7203 sf 1 7204 si 0 7205 tg (WTG 7206 uid 1845,0 7207 ps "ConnStartEndStrategy" 7208 stg "STSignalDisplayStrategy" 7209 f (Text 7210 uid 1846,0 7211 va (VaSet 7212 isHidden 1 7213 ) 7214 xt "22000,109000,25500,110000" 7215 st "DWRITE" 7216 blo "22000,109800" 7217 tm "WireNameMgr" 7218 ) 7219 ) 7220 on &112 7221 ) 7222 *240 (Wire 7223 uid 1865,0 7224 shape (OrthoPolyLine 7225 uid 1866,0 7226 va (VaSet 7227 vasetType 3 7228 ) 7229 xt "21000,105000,51250,105000" 7230 pts [ 7231 "21000,105000" 7232 "51250,105000" 7233 ] 7234 ) 7235 start &101 7236 end &32 7237 sat 32 7238 eat 32 7239 stc 0 7240 st 0 7241 sf 1 7242 si 0 7243 tg (WTG 7244 uid 1869,0 7245 ps "ConnStartEndStrategy" 7246 stg "STSignalDisplayStrategy" 7247 f (Text 7248 uid 1870,0 7249 va (VaSet 7250 isHidden 1 7251 ) 7252 xt "22000,104000,26600,105000" 7253 st "D0_SROUT" 7254 blo "22000,104800" 7255 tm "WireNameMgr" 7256 ) 7257 ) 7258 on &105 7259 ) 7260 *241 (Wire 7261 uid 1873,0 7262 shape (OrthoPolyLine 7263 uid 1874,0 7264 va (VaSet 7265 vasetType 3 7266 ) 7267 xt "21000,106000,51250,106000" 7268 pts [ 7269 "21000,106000" 7270 "51250,106000" 7271 ] 7272 ) 7273 start &102 7274 end &33 7275 sat 32 7276 eat 32 7277 stc 0 7278 st 0 7279 sf 1 7280 si 0 7281 tg (WTG 7282 uid 1877,0 7283 ps "ConnStartEndStrategy" 7284 stg "STSignalDisplayStrategy" 7285 f (Text 7286 uid 1878,0 7287 va (VaSet 7288 isHidden 1 7289 ) 7290 xt "22000,105000,26600,106000" 7291 st "D1_SROUT" 7292 blo "22000,105800" 7293 tm "WireNameMgr" 7294 ) 7295 ) 7296 on &106 7297 ) 7298 *242 (Wire 7299 uid 1881,0 7300 shape (OrthoPolyLine 7301 uid 1882,0 7302 va (VaSet 7303 vasetType 3 7304 ) 7305 xt "21000,107000,51250,107000" 7306 pts [ 7307 "21000,107000" 7308 "51250,107000" 7309 ] 7310 ) 7311 start &103 7312 end &34 7313 sat 32 7314 eat 32 7315 stc 0 7316 st 0 7317 sf 1 7318 si 0 7319 tg (WTG 7320 uid 1885,0 7321 ps "ConnStartEndStrategy" 7322 stg "STSignalDisplayStrategy" 7323 f (Text 7324 uid 1886,0 7325 va (VaSet 7326 isHidden 1 7327 ) 7328 xt "22000,106000,26600,107000" 7329 st "D2_SROUT" 7330 blo "22000,106800" 7331 tm "WireNameMgr" 7332 ) 7333 ) 7334 on &107 7335 ) 7336 *243 (Wire 7337 uid 1889,0 7338 shape (OrthoPolyLine 7339 uid 1890,0 7340 va (VaSet 7341 vasetType 3 7342 ) 7343 xt "21000,108000,51250,108000" 7344 pts [ 7345 "21000,108000" 7346 "51250,108000" 7347 ] 7348 ) 7349 start &104 7350 end &35 7351 sat 32 7352 eat 32 7353 stc 0 7354 st 0 7355 sf 1 7356 si 0 7357 tg (WTG 7358 uid 1893,0 7359 ps "ConnStartEndStrategy" 7360 stg "STSignalDisplayStrategy" 7361 f (Text 7362 uid 1894,0 7363 va (VaSet 7364 isHidden 1 7365 ) 7366 xt "22000,107000,26600,108000" 7367 st "D3_SROUT" 7368 blo "22000,107800" 7369 tm "WireNameMgr" 7370 ) 7371 ) 7372 on &108 7373 ) 7374 *244 (Wire 7375 uid 2409,0 7376 shape (OrthoPolyLine 7377 uid 2410,0 7378 va (VaSet 7379 vasetType 3 7380 ) 7381 xt "21000,111000,51250,111000" 7382 pts [ 7383 "51250,111000" 7384 "21000,111000" 7385 ] 7386 ) 7387 start &36 7388 end &64 7389 sat 32 7390 eat 32 7391 stc 0 7392 st 0 7393 sf 1 7394 si 0 7395 tg (WTG 7396 uid 2413,0 7397 ps "ConnStartEndStrategy" 7398 stg "STSignalDisplayStrategy" 7399 f (Text 7400 uid 2414,0 7401 va (VaSet 7402 isHidden 1 7403 ) 7404 xt "22000,110000,26200,111000" 7405 st "RSRLOAD" 7406 blo "22000,110800" 7407 tm "WireNameMgr" 7408 ) 7409 ) 7410 on &63 7411 ) 7412 *245 (Wire 7413 uid 2423,0 7414 shape (OrthoPolyLine 7415 uid 2424,0 7416 va (VaSet 7417 vasetType 3 7418 ) 7419 xt "32000,113000,51250,113000" 7420 pts [ 7421 "51250,113000" 7422 "32000,113000" 7423 ] 7424 ) 7425 start &37 7426 end &93 7427 sat 32 7428 eat 1 7429 stc 0 7430 st 0 7431 sf 1 7432 si 0 7433 tg (WTG 7434 uid 2427,0 7435 ps "ConnStartEndStrategy" 7436 stg "STSignalDisplayStrategy" 7437 f (Text 7438 uid 2428,0 7439 va (VaSet 7440 isHidden 1 7441 ) 7442 xt "66250,109000,69250,110000" 7443 st "SRCLK" 7444 blo "66250,109800" 7445 tm "WireNameMgr" 7446 ) 7447 ) 7448 on &65 7449 ) 7450 *246 (Wire 7451 uid 3009,0 7452 shape (OrthoPolyLine 7453 uid 3010,0 7454 va (VaSet 7455 vasetType 3 7456 ) 7457 xt "80750,98000,111000,98000" 7458 pts [ 7459 "80750,98000" 7460 "111000,98000" 7461 ] 7462 ) 7463 start &39 7464 end &126 7465 sat 32 7466 eat 32 7467 stc 0 7468 st 0 7469 sf 1 7470 si 0 7471 tg (WTG 7472 uid 3011,0 7473 ps "ConnStartEndStrategy" 7474 stg "STSignalDisplayStrategy" 7475 f (Text 7476 uid 3012,0 7477 va (VaSet 7478 isHidden 1 7479 ) 7480 xt "82000,97000,84800,98000" 7481 st "S_CLK" 7482 blo "82000,97800" 7483 tm "WireNameMgr" 7484 ) 7485 ) 7486 on &127 7487 ) 7488 *247 (Wire 7489 uid 3015,0 7490 shape (OrthoPolyLine 7491 uid 3016,0 7492 va (VaSet 7493 vasetType 3 7494 ) 7495 xt "80750,99000,111000,99000" 7496 pts [ 7497 "80750,99000" 7498 "111000,99000" 7499 ] 7500 ) 7501 start &41 7502 end &135 7503 sat 32 7504 eat 32 7505 stc 0 7506 st 0 7507 sf 1 7508 si 0 7509 tg (WTG 7510 uid 3017,0 7511 ps "ConnStartEndStrategy" 7512 stg "STSignalDisplayStrategy" 7513 f (Text 7514 uid 3018,0 7515 va (VaSet 7516 isHidden 1 7517 ) 7518 xt "82750,98000,85150,99000" 7519 st "MISO" 7520 blo "82750,98800" 7521 tm "WireNameMgr" 7522 ) 7523 ) 7524 on &138 7525 ) 7526 *248 (Wire 7527 uid 3021,0 7528 shape (OrthoPolyLine 7529 uid 3022,0 7530 va (VaSet 7531 vasetType 3 7532 lineWidth 2 7533 ) 7534 xt "80750,89000,100000,89000" 7535 pts [ 7536 "80750,89000" 7537 "100000,89000" 7538 ] 7539 ) 7540 start &40 7541 end &114 7542 sat 32 7543 eat 1 7544 sty 1 7545 st 0 7546 sf 1 7547 si 0 7548 tg (WTG 7549 uid 3023,0 7550 ps "ConnStartEndStrategy" 7551 stg "STSignalDisplayStrategy" 7552 f (Text 7553 uid 3024,0 7554 va (VaSet 7555 ) 7556 xt "92000,88000,98500,89000" 7557 st "sensor_cs : (3:0)" 7558 blo "92000,88800" 7559 tm "WireNameMgr" 7560 ) 7561 ) 7562 on &66 7563 ) 7564 *249 (Wire 7565 uid 3027,0 7566 shape (OrthoPolyLine 7567 uid 3028,0 7568 va (VaSet 7569 vasetType 3 7570 ) 7571 xt "94000,87000,111000,87000" 7572 pts [ 7573 "94000,87000" 7574 "111000,87000" 7575 ] 7576 ) 7577 start &211 7578 end &113 7579 ss 0 7580 sat 32 7581 eat 32 7582 stc 0 7583 st 0 7584 sf 1 7585 si 0 7586 tg (WTG 7587 uid 3031,0 7588 ps "ConnStartEndStrategy" 7589 stg "STSignalDisplayStrategy" 7590 f (Text 7591 uid 3032,0 7592 va (VaSet 7593 isHidden 1 7594 ) 7595 xt "95000,86000,98600,87000" 7596 st "DAC_CS" 7597 blo "95000,86800" 7598 tm "WireNameMgr" 7599 ) 7600 ) 7601 on &67 7602 ) 7603 *250 (Wire 7604 uid 3218,0 7605 shape (OrthoPolyLine 7606 uid 3219,0 7607 va (VaSet 7608 vasetType 3 7609 ) 7610 xt "11000,77000,13000,77000" 7611 pts [ 7612 "11000,77000" 7613 "13000,77000" 7614 ] 7615 ) 7616 start &47 7617 end &176 7618 sat 32 7619 eat 32 7620 stc 0 7621 st 0 7622 sf 1 7623 si 0 7624 tg (WTG 7625 uid 3220,0 7626 ps "ConnStartEndStrategy" 7627 stg "STSignalDisplayStrategy" 7628 f (Text 7629 uid 3221,0 7630 va (VaSet 7631 isHidden 1 7632 ) 7633 xt "22000,76000,24100,77000" 7634 st "TRG" 7635 blo "22000,76800" 7636 tm "WireNameMgr" 7637 ) 7638 ) 7639 on &70 7640 ) 7641 *251 (Wire 7642 uid 3260,0 7643 shape (OrthoPolyLine 7644 uid 3261,0 7645 va (VaSet 7646 vasetType 3 7647 lineWidth 2 7648 ) 7649 xt "21000,70000,24000,70000" 7650 pts [ 7651 "21000,70000" 7652 "24000,70000" 7653 ] 7654 ) 7655 start &68 7656 end &71 7657 sat 32 7658 eat 2 7659 sty 1 7660 stc 0 7661 st 0 7662 sf 1 7663 si 0 7664 tg (WTG 7665 uid 3264,0 7666 ps "ConnStartEndStrategy" 7667 stg "STSignalDisplayStrategy" 7668 f (Text 7669 uid 3265,0 7670 va (VaSet 7671 isHidden 1 7672 ) 7673 xt "23000,69000,25800,70000" 7674 st "A_CLK" 7675 blo "23000,69800" 7676 tm "WireNameMgr" 7677 ) 7678 ) 7679 on &75 7680 ) 7681 *252 (Wire 7682 uid 3270,0 7683 shape (OrthoPolyLine 7684 uid 3271,0 7685 va (VaSet 7686 vasetType 3 7687 ) 7688 xt "32000,70000,51250,70000" 7689 pts [ 7690 "51250,70000" 7691 "32000,70000" 7692 ] 7693 ) 7694 start &25 7695 end &71 7696 sat 32 7697 eat 1 7698 st 0 7699 sf 1 7700 si 0 7701 tg (WTG 7702 uid 3274,0 7703 ps "ConnStartEndStrategy" 7704 stg "STSignalDisplayStrategy" 7705 f (Text 7706 uid 3275,0 7707 va (VaSet 7708 ) 7709 xt "46000,69000,50500,70000" 7710 st "CLK_25_PS" 7711 blo "46000,69800" 7712 tm "WireNameMgr" 7713 ) 7714 ) 7715 on &76 7716 ) 7717 *253 (Wire 7718 uid 3318,0 7719 shape (OrthoPolyLine 7720 uid 3319,0 7721 va (VaSet 7722 vasetType 3 7723 lineWidth 2 7724 ) 7725 xt "21000,95000,24000,95000" 7726 pts [ 7727 "21000,95000" 7728 "24000,95000" 7729 ] 7730 ) 7731 start &85 7732 end &81 7733 sat 32 7734 eat 1 7735 sty 1 7736 stc 0 7737 st 0 7738 sf 1 7739 si 0 7740 tg (WTG 7741 uid 3322,0 7742 ps "ConnStartEndStrategy" 7743 stg "STSignalDisplayStrategy" 7744 f (Text 7745 uid 3323,0 7746 va (VaSet 7747 isHidden 1 7748 ) 7749 xt "23000,94000,25300,95000" 7750 st "A0_D" 7751 blo "23000,94800" 7752 tm "WireNameMgr" 7753 ) 7754 ) 7755 on &89 7756 ) 7757 *254 (Wire 7758 uid 3352,0 7759 shape (OrthoPolyLine 7760 uid 3353,0 7761 va (VaSet 7762 vasetType 3 7763 lineWidth 2 7764 ) 7765 xt "21000,96000,24000,96000" 7766 pts [ 7767 "21000,96000" 7768 "24000,96000" 7769 ] 7770 ) 7771 start &86 7772 end &81 7773 sat 32 7774 eat 1 7775 sty 1 7776 stc 0 7777 st 0 7778 sf 1 7779 si 0 7780 tg (WTG 7781 uid 3356,0 7782 ps "ConnStartEndStrategy" 7783 stg "STSignalDisplayStrategy" 7784 f (Text 7785 uid 3357,0 7786 va (VaSet 7787 isHidden 1 7788 ) 7789 xt "23000,95000,25300,96000" 7790 st "A1_D" 7791 blo "23000,95800" 7792 tm "WireNameMgr" 7793 ) 7794 ) 7795 on &90 7796 ) 7797 *255 (Wire 7798 uid 3360,0 7799 shape (OrthoPolyLine 7800 uid 3361,0 7801 va (VaSet 7802 vasetType 3 7803 lineWidth 2 7804 ) 7805 xt "21000,97000,24000,97000" 7806 pts [ 7807 "21000,97000" 7808 "24000,97000" 7809 ] 7810 ) 7811 start &87 7812 end &81 7813 sat 32 7814 eat 1 7815 sty 1 7816 stc 0 7817 st 0 7818 sf 1 7819 si 0 7820 tg (WTG 7821 uid 3364,0 7822 ps "ConnStartEndStrategy" 7823 stg "STSignalDisplayStrategy" 7824 f (Text 7825 uid 3365,0 7826 va (VaSet 7827 isHidden 1 7828 ) 7829 xt "23000,96000,25300,97000" 7830 st "A2_D" 7831 blo "23000,96800" 7832 tm "WireNameMgr" 7833 ) 7834 ) 7835 on &91 7836 ) 7837 *256 (Wire 7838 uid 3368,0 7839 shape (OrthoPolyLine 7840 uid 3369,0 7841 va (VaSet 7842 vasetType 3 7843 lineWidth 2 7844 ) 7845 xt "21000,98000,24000,98000" 7846 pts [ 7847 "21000,98000" 7848 "24000,98000" 7849 ] 7850 ) 7851 start &88 7852 end &81 7853 sat 32 7854 eat 1 7855 sty 1 7856 stc 0 7857 st 0 7858 sf 1 7859 si 0 7860 tg (WTG 7861 uid 3372,0 7862 ps "ConnStartEndStrategy" 7863 stg "STSignalDisplayStrategy" 7864 f (Text 7865 uid 3373,0 7866 va (VaSet 7867 isHidden 1 7868 ) 7869 xt "23000,97000,25300,98000" 7870 st "A3_D" 7871 blo "23000,97800" 7872 tm "WireNameMgr" 7873 ) 7874 ) 7875 on &92 7876 ) 7877 *257 (Wire 7878 uid 3430,0 7879 shape (OrthoPolyLine 7880 uid 3431,0 7881 va (VaSet 7882 vasetType 3 7883 ) 7884 xt "21000,113000,24000,113000" 7885 pts [ 7886 "21000,113000" 7887 "24000,113000" 7888 ] 7889 ) 7890 start &161 7891 end &93 7892 sat 32 7893 eat 2 7894 stc 0 7895 st 0 7896 sf 1 7897 si 0 7898 tg (WTG 7899 uid 3434,0 7900 ps "ConnStartEndStrategy" 7901 stg "STSignalDisplayStrategy" 7902 f (Text 7903 uid 3435,0 7904 va (VaSet 7905 isHidden 1 7906 ) 7907 xt "23000,112000,27400,113000" 7908 st "D0_SRCLK" 7909 blo "23000,112800" 7910 tm "WireNameMgr" 7911 ) 7912 ) 7913 on &97 7914 ) 7915 *258 (Wire 7916 uid 3438,0 7917 shape (OrthoPolyLine 7918 uid 3439,0 7919 va (VaSet 7920 vasetType 3 7921 ) 7922 xt "21000,114000,24000,114000" 7923 pts [ 7924 "21000,114000" 7925 "24000,114000" 7926 ] 7927 ) 7928 start &162 7929 end &93 7930 sat 32 7931 eat 2 7932 stc 0 7933 st 0 7934 sf 1 7935 si 0 7936 tg (WTG 7937 uid 3442,0 7938 ps "ConnStartEndStrategy" 7939 stg "STSignalDisplayStrategy" 7940 f (Text 7941 uid 3443,0 7942 va (VaSet 7943 isHidden 1 7944 ) 7945 xt "23000,113000,27400,114000" 7946 st "D1_SRCLK" 7947 blo "23000,113800" 7948 tm "WireNameMgr" 7949 ) 7950 ) 7951 on &98 7952 ) 7953 *259 (Wire 7954 uid 3446,0 7955 shape (OrthoPolyLine 7956 uid 3447,0 7957 va (VaSet 7958 vasetType 3 7959 ) 7960 xt "21000,115000,24000,115000" 7961 pts [ 7962 "21000,115000" 7963 "24000,115000" 7964 ] 7965 ) 7966 start &163 7967 end &93 7968 sat 32 7969 eat 2 7970 stc 0 7971 st 0 7972 sf 1 7973 si 0 7974 tg (WTG 7975 uid 3450,0 7976 ps "ConnStartEndStrategy" 7977 stg "STSignalDisplayStrategy" 7978 f (Text 7979 uid 3451,0 7980 va (VaSet 7981 isHidden 1 7982 ) 7983 xt "23000,114000,27400,115000" 7984 st "D2_SRCLK" 7985 blo "23000,114800" 7986 tm "WireNameMgr" 7987 ) 7988 ) 7989 on &99 7990 ) 7991 *260 (Wire 7992 uid 3454,0 7993 shape (OrthoPolyLine 7994 uid 3455,0 7995 va (VaSet 7996 vasetType 3 7997 ) 7998 xt "21000,116000,24000,116000" 7999 pts [ 8000 "21000,116000" 8001 "24000,116000" 8002 ] 8003 ) 8004 start &164 8005 end &93 8006 sat 32 8007 eat 2 8008 stc 0 8009 st 0 8010 sf 1 8011 si 0 8012 tg (WTG 8013 uid 3458,0 8014 ps "ConnStartEndStrategy" 8015 stg "STSignalDisplayStrategy" 8016 f (Text 8017 uid 3459,0 8018 va (VaSet 8019 isHidden 1 8020 ) 8021 xt "23000,115000,27400,116000" 8022 st "D3_SRCLK" 8023 blo "23000,115800" 8024 tm "WireNameMgr" 8025 ) 8026 ) 8027 on &100 8028 ) 8029 *261 (Wire 8030 uid 3574,0 8031 shape (OrthoPolyLine 8032 uid 3575,0 8033 va (VaSet 8034 vasetType 3 8035 ) 8036 xt "108000,89000,111000,89000" 8037 pts [ 8038 "111000,89000" 8039 "108000,89000" 8040 ] 8041 ) 8042 start &118 8043 end &114 8044 sat 32 8045 eat 2 8046 stc 0 8047 st 0 8048 sf 1 8049 si 0 8050 tg (WTG 8051 uid 3578,0 8052 ps "ConnStartEndStrategy" 8053 stg "STSignalDisplayStrategy" 8054 f (Text 8055 uid 3579,0 8056 va (VaSet 8057 isHidden 1 8058 ) 8059 xt "108000,88000,110800,89000" 8060 st "T0_CS" 8061 blo "108000,88800" 8062 tm "WireNameMgr" 8063 ) 8064 ) 8065 on &122 8066 ) 8067 *262 (Wire 8068 uid 3582,0 8069 shape (OrthoPolyLine 8070 uid 3583,0 8071 va (VaSet 8072 vasetType 3 8073 ) 8074 xt "108000,90000,111000,90000" 8075 pts [ 8076 "111000,90000" 8077 "108000,90000" 8078 ] 8079 ) 8080 start &119 8081 end &114 8082 sat 32 8083 eat 2 8084 stc 0 8085 st 0 8086 sf 1 8087 si 0 8088 tg (WTG 8089 uid 3586,0 8090 ps "ConnStartEndStrategy" 8091 stg "STSignalDisplayStrategy" 8092 f (Text 8093 uid 3587,0 8094 va (VaSet 8095 isHidden 1 8096 ) 8097 xt "108000,89000,110800,90000" 8098 st "T1_CS" 8099 blo "108000,89800" 8100 tm "WireNameMgr" 8101 ) 8102 ) 8103 on &123 8104 ) 8105 *263 (Wire 8106 uid 3590,0 8107 shape (OrthoPolyLine 8108 uid 3591,0 8109 va (VaSet 8110 vasetType 3 8111 ) 8112 xt "108000,91000,111000,91000" 8113 pts [ 8114 "111000,91000" 8115 "108000,91000" 8116 ] 8117 ) 8118 start &120 8119 end &114 8120 sat 32 8121 eat 2 8122 stc 0 8123 st 0 8124 sf 1 8125 si 0 8126 tg (WTG 8127 uid 3594,0 8128 ps "ConnStartEndStrategy" 8129 stg "STSignalDisplayStrategy" 8130 f (Text 8131 uid 3595,0 8132 va (VaSet 8133 isHidden 1 8134 ) 8135 xt "108000,90000,110800,91000" 8136 st "T2_CS" 8137 blo "108000,90800" 8138 tm "WireNameMgr" 8139 ) 8140 ) 8141 on &124 8142 ) 8143 *264 (Wire 8144 uid 3598,0 8145 shape (OrthoPolyLine 8146 uid 3599,0 8147 va (VaSet 8148 vasetType 3 8149 ) 8150 xt "108000,92000,111000,92000" 8151 pts [ 8152 "111000,92000" 8153 "108000,92000" 8154 ] 8155 ) 8156 start &121 8157 end &114 8158 sat 32 8159 eat 2 8160 stc 0 8161 st 0 8162 sf 1 8163 si 0 8164 tg (WTG 8165 uid 3602,0 8166 ps "ConnStartEndStrategy" 8167 stg "STSignalDisplayStrategy" 8168 f (Text 8169 uid 3603,0 8170 va (VaSet 8171 isHidden 1 8172 ) 8173 xt "108000,91000,110800,92000" 8174 st "T3_CS" 8175 blo "108000,91800" 8176 tm "WireNameMgr" 8177 ) 8178 ) 8179 on &125 8180 ) 8181 *265 (Wire 8182 uid 3682,0 8183 shape (OrthoPolyLine 8184 uid 3683,0 8185 va (VaSet 8186 vasetType 3 8187 ) 8188 xt "80750,100000,111000,100000" 8189 pts [ 8190 "80750,100000" 8191 "111000,100000" 8192 ] 8193 ) 8194 start &42 8195 end &137 8196 sat 32 8197 eat 32 8198 stc 0 8199 st 0 8200 sf 1 8201 si 0 8202 tg (WTG 8203 uid 3686,0 8204 ps "ConnStartEndStrategy" 8205 stg "STSignalDisplayStrategy" 8206 f (Text 8207 uid 3687,0 8208 va (VaSet 8209 isHidden 1 8210 ) 8211 xt "82000,99000,84400,100000" 8212 st "MOSI" 8213 blo "82000,99800" 8214 tm "WireNameMgr" 8215 ) 8216 ) 8217 on &136 8218 ) 8219 *266 (Wire 8220 uid 3778,0 8221 shape (OrthoPolyLine 8222 uid 3779,0 8223 va (VaSet 8224 vasetType 3 8225 ) 8226 xt "108000,103000,111000,103000" 8227 pts [ 8228 "111000,103000" 8229 "108000,103000" 8230 ] 8231 ) 8232 start &143 8233 end &139 8234 sat 32 8235 eat 2 8236 stc 0 8237 st 0 8238 sf 1 8239 si 0 8240 tg (WTG 8241 uid 3782,0 8242 ps "ConnStartEndStrategy" 8243 stg "STSignalDisplayStrategy" 8244 f (Text 8245 uid 3783,0 8246 va (VaSet 8247 isHidden 1 8248 ) 8249 xt "108000,102000,111000,103000" 8250 st "TRG_V" 8251 blo "108000,102800" 8252 tm "WireNameMgr" 8253 ) 8254 ) 8255 on &152 8256 ) 8257 *267 (Wire 8258 uid 3786,0 8259 shape (OrthoPolyLine 8260 uid 3787,0 8261 va (VaSet 8262 vasetType 3 8263 ) 8264 xt "108000,104000,111000,104000" 8265 pts [ 8266 "111000,104000" 8267 "108000,104000" 8268 ] 8269 ) 8270 start &144 8271 end &139 8272 sat 32 8273 eat 2 8274 stc 0 8275 st 0 8276 sf 1 8277 si 0 8278 tg (WTG 8279 uid 3790,0 8280 ps "ConnStartEndStrategy" 8281 stg "STSignalDisplayStrategy" 8282 f (Text 8283 uid 3791,0 8284 va (VaSet 8285 isHidden 1 8286 ) 8287 xt "108000,103000,113600,104000" 8288 st "RS485_C_RE" 8289 blo "108000,103800" 8290 tm "WireNameMgr" 8291 ) 8292 ) 8293 on &153 8294 ) 8295 *268 (Wire 8296 uid 3794,0 8297 shape (OrthoPolyLine 8298 uid 3795,0 8299 va (VaSet 8300 vasetType 3 8301 ) 8302 xt "108000,105000,111000,105000" 8303 pts [ 8304 "111000,105000" 8305 "108000,105000" 8306 ] 8307 ) 8308 start &145 8309 end &139 8310 sat 32 8311 eat 2 8312 stc 0 8313 st 0 8314 sf 1 8315 si 0 8316 tg (WTG 8317 uid 3798,0 8318 ps "ConnStartEndStrategy" 8319 stg "STSignalDisplayStrategy" 8320 f (Text 8321 uid 3799,0 8322 va (VaSet 8323 isHidden 1 8324 ) 8325 xt "108000,104000,113600,105000" 8326 st "RS485_C_DE" 8327 blo "108000,104800" 8328 tm "WireNameMgr" 8329 ) 8330 ) 8331 on &154 8332 ) 8333 *269 (Wire 8334 uid 3802,0 8335 shape (OrthoPolyLine 8336 uid 3803,0 8337 va (VaSet 8338 vasetType 3 8339 ) 8340 xt "108000,106000,111000,106000" 8341 pts [ 8342 "111000,106000" 8343 "108000,106000" 8344 ] 8345 ) 8346 start &146 8347 end &139 8348 sat 32 8349 eat 2 8350 stc 0 8351 st 0 8352 sf 1 8353 si 0 8354 tg (WTG 8355 uid 3806,0 8356 ps "ConnStartEndStrategy" 8357 stg "STSignalDisplayStrategy" 8358 f (Text 8359 uid 3807,0 8360 va (VaSet 8361 isHidden 1 8362 ) 8363 xt "108000,105000,113500,106000" 8364 st "RS485_E_RE" 8365 blo "108000,105800" 8366 tm "WireNameMgr" 8367 ) 8368 ) 8369 on &155 8370 ) 8371 *270 (Wire 8372 uid 3810,0 8373 shape (OrthoPolyLine 8374 uid 3811,0 8375 va (VaSet 8376 vasetType 3 8377 ) 8378 xt "108000,107000,111000,107000" 8379 pts [ 8380 "111000,107000" 8381 "108000,107000" 8382 ] 8383 ) 8384 start &147 8385 end &139 8386 sat 32 8387 eat 2 8388 stc 0 8389 st 0 8390 sf 1 8391 si 0 8392 tg (WTG 8393 uid 3814,0 8394 ps "ConnStartEndStrategy" 8395 stg "STSignalDisplayStrategy" 8396 f (Text 8397 uid 3815,0 8398 va (VaSet 8399 isHidden 1 8400 ) 8401 xt "108000,106000,113500,107000" 8402 st "RS485_E_DE" 8403 blo "108000,106800" 8404 tm "WireNameMgr" 8405 ) 8406 ) 8407 on &156 8408 ) 8409 *271 (Wire 8410 uid 3826,0 8411 shape (OrthoPolyLine 8412 uid 3827,0 8413 va (VaSet 8414 vasetType 3 8415 ) 8416 xt "108000,109000,111000,109000" 8417 pts [ 8418 "111000,109000" 8419 "108000,109000" 8420 ] 8421 ) 8422 start &149 8423 end &139 8424 sat 32 8425 eat 2 8426 stc 0 8427 st 0 8428 sf 1 8429 si 0 8430 tg (WTG 8431 uid 3830,0 8432 ps "ConnStartEndStrategy" 8433 stg "STSignalDisplayStrategy" 8434 f (Text 8435 uid 3831,0 8436 va (VaSet 8437 isHidden 1 8438 ) 8439 xt "108000,108000,110300,109000" 8440 st "SRIN" 8441 blo "108000,108800" 8442 tm "WireNameMgr" 8443 ) 8444 ) 8445 on &158 8446 ) 8447 *272 (Wire 8448 uid 3834,0 8449 shape (OrthoPolyLine 8450 uid 3835,0 8451 va (VaSet 8452 vasetType 3 8453 ) 8454 xt "108000,110000,111000,110000" 8455 pts [ 8456 "111000,110000" 8457 "108000,110000" 8458 ] 8459 ) 8460 start &150 8461 end &139 8462 sat 32 8463 eat 2 8464 stc 0 8465 st 0 8466 sf 1 8467 si 0 8468 tg (WTG 8469 uid 3838,0 8470 ps "ConnStartEndStrategy" 8471 stg "STSignalDisplayStrategy" 8472 f (Text 8473 uid 3839,0 8474 va (VaSet 8475 isHidden 1 8476 ) 8477 xt "108000,109000,110900,110000" 8478 st "EE_CS" 8479 blo "108000,109800" 8480 tm "WireNameMgr" 8481 ) 8482 ) 8483 on &159 8484 ) 8485 *273 (Wire 8486 uid 3842,0 8487 shape (OrthoPolyLine 8488 uid 3843,0 8489 va (VaSet 8490 vasetType 3 8491 lineWidth 2 8492 ) 8493 xt "108000,111000,111000,111000" 8494 pts [ 8495 "111000,111000" 8496 "108000,111000" 8497 ] 8498 ) 8499 start &151 8500 end &139 8501 sat 32 8502 eat 2 8503 sty 1 8504 stc 0 8505 st 0 8506 sf 1 8507 si 0 8508 tg (WTG 8509 uid 3846,0 8510 ps "ConnStartEndStrategy" 8511 stg "STSignalDisplayStrategy" 8512 f (Text 8513 uid 3847,0 8514 va (VaSet 8515 isHidden 1 8516 ) 8517 xt "108000,110000,109900,111000" 8518 st "LED" 8519 blo "108000,110800" 8520 tm "WireNameMgr" 8521 ) 8522 ) 8523 on &160 8524 ) 8525 *274 (Wire 8526 uid 4942,0 8527 shape (OrthoPolyLine 8528 uid 4943,0 8529 va (VaSet 8530 vasetType 3 8531 lineWidth 2 8532 ) 8533 xt "80750,120000,111000,120000" 8534 pts [ 8535 "80750,120000" 8536 "111000,120000" 8537 ] 8538 ) 8539 start &14 8540 end &165 7590 8541 sat 32 7591 8542 eat 32 … … 7596 8547 si 0 7597 8548 tg (WTG 7598 uid 1837,08549 uid 4948,0 7599 8550 ps "ConnStartEndStrategy" 7600 8551 stg "STSignalDisplayStrategy" 7601 8552 f (Text 7602 uid 1838,08553 uid 4949,0 7603 8554 va (VaSet 7604 8555 isHidden 1 7605 8556 ) 7606 xt " 22000,108000,23900,109000"7607 st "D_ A"7608 blo " 22000,108800"7609 tm "WireNameMgr" 7610 ) 7611 ) 7612 on &1 117613 ) 7614 *2 55 (Wire7615 uid 1841,08557 xt "82750,117000,84650,118000" 8558 st "D_T" 8559 blo "82750,117800" 8560 tm "WireNameMgr" 8561 ) 8562 ) 8563 on &166 8564 ) 8565 *275 (Wire 8566 uid 6130,0 7616 8567 shape (OrthoPolyLine 7617 uid 1842,08568 uid 6131,0 7618 8569 va (VaSet 7619 8570 vasetType 3 7620 8571 ) 7621 xt "21000,110000,51250,110000" 7622 pts [ 7623 "51250,110000" 7624 "21000,110000" 7625 ] 7626 ) 7627 start &31 7628 end &112 8572 xt "19000,78000,51250,78000" 8573 pts [ 8574 "19000,78000" 8575 "51250,78000" 8576 ] 8577 ) 8578 start &173 8579 end &15 8580 sat 32 8581 eat 32 8582 st 0 8583 sf 1 8584 si 0 8585 tg (WTG 8586 uid 6136,0 8587 ps "ConnStartEndStrategy" 8588 stg "STSignalDisplayStrategy" 8589 f (Text 8590 uid 6137,0 8591 va (VaSet 8592 ) 8593 xt "21000,77000,24700,78000" 8594 st "TRG_OR" 8595 blo "21000,77800" 8596 tm "WireNameMgr" 8597 ) 8598 ) 8599 on &169 8600 ) 8601 *276 (Wire 8602 uid 6306,0 8603 shape (OrthoPolyLine 8604 uid 6307,0 8605 va (VaSet 8606 vasetType 3 8607 ) 8608 xt "11000,79000,13000,79000" 8609 pts [ 8610 "11000,79000" 8611 "13000,79000" 8612 ] 8613 ) 8614 start &167 8615 end &171 7629 8616 sat 32 7630 8617 eat 32 … … 7634 8621 si 0 7635 8622 tg (WTG 7636 uid 1845,08623 uid 6312,0 7637 8624 ps "ConnStartEndStrategy" 7638 8625 stg "STSignalDisplayStrategy" 7639 8626 f (Text 7640 uid 1846,08627 uid 6313,0 7641 8628 va (VaSet 7642 8629 isHidden 1 7643 8630 ) 7644 xt " 22000,109000,25500,110000"7645 st " DWRITE"7646 blo " 22000,109800"7647 tm "WireNameMgr" 7648 ) 7649 ) 7650 on &1 137651 ) 7652 *2 56(Wire7653 uid 1865,08631 xt "13000,78000,17500,79000" 8632 st "TEST_TRG" 8633 blo "13000,78800" 8634 tm "WireNameMgr" 8635 ) 8636 ) 8637 on &168 8638 ) 8639 *277 (Wire 8640 uid 6431,0 7654 8641 shape (OrthoPolyLine 7655 uid 1866,08642 uid 6432,0 7656 8643 va (VaSet 7657 8644 vasetType 3 7658 8645 ) 7659 xt " 21000,105000,51250,105000"7660 pts [ 7661 " 21000,105000"7662 " 51250,105000"7663 ] 7664 ) 7665 start & 1027666 end & 328646 xt "80750,121000,111000,121000" 8647 pts [ 8648 "80750,121000" 8649 "111000,121000" 8650 ] 8651 ) 8652 start &43 8653 end &148 7667 8654 sat 32 7668 8655 eat 32 … … 7672 8659 si 0 7673 8660 tg (WTG 7674 uid 1869,08661 uid 6435,0 7675 8662 ps "ConnStartEndStrategy" 7676 8663 stg "STSignalDisplayStrategy" 7677 8664 f (Text 7678 uid 1870,08665 uid 6436,0 7679 8666 va (VaSet 7680 8667 isHidden 1 7681 8668 ) 7682 xt " 22000,104000,26600,105000"7683 st "D 0_SROUT"7684 blo " 22000,104800"7685 tm "WireNameMgr" 7686 ) 7687 ) 7688 on &1 067689 ) 7690 *2 57(Wire7691 uid 1873,08669 xt "92000,120000,96000,121000" 8670 st "DENABLE" 8671 blo "92000,120800" 8672 tm "WireNameMgr" 8673 ) 8674 ) 8675 on &157 8676 ) 8677 *278 (Wire 8678 uid 6787,0 7692 8679 shape (OrthoPolyLine 7693 uid 1874,0 7694 va (VaSet 7695 vasetType 3 7696 ) 7697 xt "21000,106000,51250,106000" 7698 pts [ 7699 "21000,106000" 7700 "51250,106000" 7701 ] 7702 ) 7703 start &103 7704 end &33 7705 sat 32 7706 eat 32 7707 stc 0 7708 st 0 7709 sf 1 7710 si 0 7711 tg (WTG 7712 uid 1877,0 7713 ps "ConnStartEndStrategy" 7714 stg "STSignalDisplayStrategy" 7715 f (Text 7716 uid 1878,0 7717 va (VaSet 7718 isHidden 1 7719 ) 7720 xt "22000,105000,26600,106000" 7721 st "D1_SROUT" 7722 blo "22000,105800" 7723 tm "WireNameMgr" 7724 ) 7725 ) 7726 on &107 7727 ) 7728 *258 (Wire 7729 uid 1881,0 7730 shape (OrthoPolyLine 7731 uid 1882,0 7732 va (VaSet 7733 vasetType 3 7734 ) 7735 xt "21000,107000,51250,107000" 7736 pts [ 7737 "21000,107000" 7738 "51250,107000" 7739 ] 7740 ) 7741 start &104 7742 end &34 7743 sat 32 7744 eat 32 7745 stc 0 7746 st 0 7747 sf 1 7748 si 0 7749 tg (WTG 7750 uid 1885,0 7751 ps "ConnStartEndStrategy" 7752 stg "STSignalDisplayStrategy" 7753 f (Text 7754 uid 1886,0 7755 va (VaSet 7756 isHidden 1 7757 ) 7758 xt "22000,106000,26600,107000" 7759 st "D2_SROUT" 7760 blo "22000,106800" 7761 tm "WireNameMgr" 7762 ) 7763 ) 7764 on &108 7765 ) 7766 *259 (Wire 7767 uid 1889,0 7768 shape (OrthoPolyLine 7769 uid 1890,0 7770 va (VaSet 7771 vasetType 3 7772 ) 7773 xt "21000,108000,51250,108000" 7774 pts [ 7775 "21000,108000" 7776 "51250,108000" 7777 ] 7778 ) 7779 start &105 7780 end &35 7781 sat 32 7782 eat 32 7783 stc 0 7784 st 0 7785 sf 1 7786 si 0 7787 tg (WTG 7788 uid 1893,0 7789 ps "ConnStartEndStrategy" 7790 stg "STSignalDisplayStrategy" 7791 f (Text 7792 uid 1894,0 7793 va (VaSet 7794 isHidden 1 7795 ) 7796 xt "22000,107000,26600,108000" 7797 st "D3_SROUT" 7798 blo "22000,107800" 7799 tm "WireNameMgr" 7800 ) 7801 ) 7802 on &109 7803 ) 7804 *260 (Wire 7805 uid 2269,0 7806 shape (OrthoPolyLine 7807 uid 2270,0 7808 va (VaSet 7809 vasetType 3 7810 ) 7811 xt "-15000,69000,51250,88000" 7812 pts [ 7813 "51250,69000" 7814 "-15000,69000" 7815 "-15000,88000" 7816 "-11750,88000" 7817 ] 7818 ) 7819 start &26 7820 end &172 7821 sat 32 7822 eat 32 7823 stc 0 7824 st 0 7825 sf 1 7826 si 0 7827 tg (WTG 7828 uid 2273,0 7829 ps "ConnStartEndStrategy" 7830 stg "STSignalDisplayStrategy" 7831 f (Text 7832 uid 2274,0 7833 va (VaSet 7834 isHidden 1 7835 ) 7836 xt "50250,68000,53350,69000" 7837 st "CLK_50" 7838 blo "50250,68800" 7839 tm "WireNameMgr" 7840 ) 7841 ) 7842 on &63 7843 ) 7844 *261 (Wire 7845 uid 2409,0 7846 shape (OrthoPolyLine 7847 uid 2410,0 7848 va (VaSet 7849 vasetType 3 7850 ) 7851 xt "21000,111000,51250,111000" 7852 pts [ 7853 "51250,111000" 7854 "21000,111000" 7855 ] 7856 ) 7857 start &36 7858 end &65 7859 sat 32 7860 eat 32 7861 stc 0 7862 st 0 7863 sf 1 7864 si 0 7865 tg (WTG 7866 uid 2413,0 7867 ps "ConnStartEndStrategy" 7868 stg "STSignalDisplayStrategy" 7869 f (Text 7870 uid 2414,0 7871 va (VaSet 7872 isHidden 1 7873 ) 7874 xt "22000,110000,26200,111000" 7875 st "RSRLOAD" 7876 blo "22000,110800" 7877 tm "WireNameMgr" 7878 ) 7879 ) 7880 on &64 7881 ) 7882 *262 (Wire 7883 uid 2423,0 7884 shape (OrthoPolyLine 7885 uid 2424,0 7886 va (VaSet 7887 vasetType 3 7888 ) 7889 xt "32000,113000,51250,113000" 7890 pts [ 7891 "51250,113000" 7892 "32000,113000" 7893 ] 7894 ) 7895 start &37 7896 end &94 7897 sat 32 7898 eat 1 7899 stc 0 7900 st 0 7901 sf 1 7902 si 0 7903 tg (WTG 7904 uid 2427,0 7905 ps "ConnStartEndStrategy" 7906 stg "STSignalDisplayStrategy" 7907 f (Text 7908 uid 2428,0 7909 va (VaSet 7910 isHidden 1 7911 ) 7912 xt "66250,109000,69250,110000" 7913 st "SRCLK" 7914 blo "66250,109800" 7915 tm "WireNameMgr" 7916 ) 7917 ) 7918 on &66 7919 ) 7920 *263 (Wire 7921 uid 3009,0 7922 shape (OrthoPolyLine 7923 uid 3010,0 7924 va (VaSet 7925 vasetType 3 7926 ) 7927 xt "80750,98000,111000,98000" 7928 pts [ 7929 "80750,98000" 7930 "111000,98000" 7931 ] 7932 ) 7933 start &39 7934 end &127 7935 sat 32 7936 eat 32 7937 stc 0 7938 st 0 7939 sf 1 7940 si 0 7941 tg (WTG 7942 uid 3011,0 7943 ps "ConnStartEndStrategy" 7944 stg "STSignalDisplayStrategy" 7945 f (Text 7946 uid 3012,0 7947 va (VaSet 7948 isHidden 1 7949 ) 7950 xt "82000,97000,84800,98000" 7951 st "S_CLK" 7952 blo "82000,97800" 7953 tm "WireNameMgr" 7954 ) 7955 ) 7956 on &128 7957 ) 7958 *264 (Wire 7959 uid 3015,0 7960 shape (OrthoPolyLine 7961 uid 3016,0 7962 va (VaSet 7963 vasetType 3 7964 ) 7965 xt "80750,99000,111000,99000" 7966 pts [ 7967 "80750,99000" 7968 "111000,99000" 7969 ] 7970 ) 7971 start &41 7972 end &136 7973 sat 32 7974 eat 32 7975 stc 0 7976 st 0 7977 sf 1 7978 si 0 7979 tg (WTG 7980 uid 3017,0 7981 ps "ConnStartEndStrategy" 7982 stg "STSignalDisplayStrategy" 7983 f (Text 7984 uid 3018,0 7985 va (VaSet 7986 isHidden 1 7987 ) 7988 xt "82750,98000,85150,99000" 7989 st "MISO" 7990 blo "82750,98800" 7991 tm "WireNameMgr" 7992 ) 7993 ) 7994 on &139 7995 ) 7996 *265 (Wire 7997 uid 3021,0 7998 shape (OrthoPolyLine 7999 uid 3022,0 8680 uid 6788,0 8000 8681 va (VaSet 8001 8682 vasetType 3 8002 8683 lineWidth 2 8003 8684 ) 8004 xt " 80750,89000,100000,89000"8005 pts [ 8006 " 80750,89000"8007 " 100000,89000"8008 ] 8009 ) 8010 start & 408011 end &1 158685 xt "93000,132000,99000,132000" 8686 pts [ 8687 "93000,132000" 8688 "99000,132000" 8689 ] 8690 ) 8691 start &193 8692 end &197 8012 8693 sat 32 8013 8694 eat 1 … … 8017 8698 si 0 8018 8699 tg (WTG 8019 uid 3023,08700 uid 6791,0 8020 8701 ps "ConnStartEndStrategy" 8021 8702 stg "STSignalDisplayStrategy" 8022 8703 f (Text 8023 uid 3024,0 8024 va (VaSet 8025 ) 8026 xt "92000,88000,98500,89000" 8027 st "sensor_cs : (3:0)" 8028 blo "92000,88800" 8029 tm "WireNameMgr" 8030 ) 8031 ) 8032 on &67 8033 ) 8034 *266 (Wire 8035 uid 3027,0 8704 uid 6792,0 8705 va (VaSet 8706 isHidden 1 8707 ) 8708 xt "95000,131000,101800,132000" 8709 st "D_PLLLCK : (3:0)" 8710 blo "95000,131800" 8711 tm "WireNameMgr" 8712 ) 8713 ) 8714 on &194 8715 ) 8716 *279 (Wire 8717 uid 6880,0 8036 8718 shape (OrthoPolyLine 8037 uid 3028,0 8038 va (VaSet 8039 vasetType 3 8040 ) 8041 xt "94000,87000,111000,87000" 8042 pts [ 8043 "94000,87000" 8044 "111000,87000" 8045 ] 8046 ) 8047 start &231 8048 end &114 8049 ss 0 8050 sat 32 8051 eat 32 8052 stc 0 8053 st 0 8054 sf 1 8055 si 0 8056 tg (WTG 8057 uid 3031,0 8058 ps "ConnStartEndStrategy" 8059 stg "STSignalDisplayStrategy" 8060 f (Text 8061 uid 3032,0 8062 va (VaSet 8063 isHidden 1 8064 ) 8065 xt "95000,86000,98600,87000" 8066 st "DAC_CS" 8067 blo "95000,86800" 8068 tm "WireNameMgr" 8069 ) 8070 ) 8071 on &68 8072 ) 8073 *267 (Wire 8074 uid 3218,0 8075 shape (OrthoPolyLine 8076 uid 3219,0 8077 va (VaSet 8078 vasetType 3 8079 ) 8080 xt "11000,77000,13000,77000" 8081 pts [ 8082 "11000,77000" 8083 "13000,77000" 8084 ] 8085 ) 8086 start &47 8087 end &196 8088 sat 32 8089 eat 32 8090 stc 0 8091 st 0 8092 sf 1 8093 si 0 8094 tg (WTG 8095 uid 3220,0 8096 ps "ConnStartEndStrategy" 8097 stg "STSignalDisplayStrategy" 8098 f (Text 8099 uid 3221,0 8100 va (VaSet 8101 isHidden 1 8102 ) 8103 xt "22000,76000,24100,77000" 8104 st "TRG" 8105 blo "22000,76800" 8106 tm "WireNameMgr" 8107 ) 8108 ) 8109 on &71 8110 ) 8111 *268 (Wire 8112 uid 3260,0 8113 shape (OrthoPolyLine 8114 uid 3261,0 8719 uid 6881,0 8115 8720 va (VaSet 8116 8721 vasetType 3 8117 8722 lineWidth 2 8118 8723 ) 8119 xt " 21000,70000,24000,70000"8120 pts [ 8121 " 21000,70000"8122 " 24000,70000"8123 ] 8124 ) 8125 start & 698126 end & 728127 sat 328128 eat 28724 xt "102000,132000,109000,132000" 8725 pts [ 8726 "102000,132000" 8727 "109000,132000" 8728 ] 8729 ) 8730 start &197 8731 end &195 8732 sat 2 8733 eat 32 8129 8734 sty 1 8130 stc 08131 8735 st 0 8132 8736 sf 1 8133 8737 si 0 8134 8738 tg (WTG 8135 uid 3264,08739 uid 6884,0 8136 8740 ps "ConnStartEndStrategy" 8137 8741 stg "STSignalDisplayStrategy" 8138 8742 f (Text 8139 uid 3265,08743 uid 6885,0 8140 8744 va (VaSet 8141 8745 isHidden 1 8142 8746 ) 8143 xt " 23000,69000,25800,70000"8144 st " A_CLK"8145 blo " 23000,69800"8146 tm "WireNameMgr" 8147 ) 8148 ) 8149 on & 768150 ) 8151 *2 69(Wire8152 uid 3270,08747 xt "104000,131000,108900,132000" 8748 st "D_T2 : (3:0)" 8749 blo "104000,131800" 8750 tm "WireNameMgr" 8751 ) 8752 ) 8753 on &196 8754 ) 8755 *280 (Wire 8756 uid 7144,0 8153 8757 shape (OrthoPolyLine 8154 uid 3271,0 8155 va (VaSet 8156 vasetType 3 8157 ) 8158 xt "32000,70000,51250,70000" 8159 pts [ 8160 "51250,70000" 8161 "32000,70000" 8162 ] 8163 ) 8164 start &25 8165 end &72 8166 sat 32 8167 eat 1 8168 st 0 8169 sf 1 8170 si 0 8171 tg (WTG 8172 uid 3274,0 8173 ps "ConnStartEndStrategy" 8174 stg "STSignalDisplayStrategy" 8175 f (Text 8176 uid 3275,0 8177 va (VaSet 8178 ) 8179 xt "46000,69000,50500,70000" 8180 st "CLK_25_PS" 8181 blo "46000,69800" 8182 tm "WireNameMgr" 8183 ) 8184 ) 8185 on &77 8186 ) 8187 *270 (Wire 8188 uid 3318,0 8189 shape (OrthoPolyLine 8190 uid 3319,0 8758 uid 7145,0 8191 8759 va (VaSet 8192 8760 vasetType 3 8193 8761 lineWidth 2 8194 8762 ) 8195 xt "21000,95000,24000,95000" 8196 pts [ 8197 "21000,95000" 8198 "24000,95000" 8199 ] 8200 ) 8201 start &86 8202 end &82 8203 sat 32 8204 eat 1 8205 sty 1 8206 stc 0 8207 st 0 8208 sf 1 8209 si 0 8210 tg (WTG 8211 uid 3322,0 8212 ps "ConnStartEndStrategy" 8213 stg "STSignalDisplayStrategy" 8214 f (Text 8215 uid 3323,0 8216 va (VaSet 8217 isHidden 1 8218 ) 8219 xt "23000,94000,25300,95000" 8220 st "A0_D" 8221 blo "23000,94800" 8222 tm "WireNameMgr" 8223 ) 8224 ) 8225 on &90 8226 ) 8227 *271 (Wire 8228 uid 3352,0 8229 shape (OrthoPolyLine 8230 uid 3353,0 8231 va (VaSet 8232 vasetType 3 8233 lineWidth 2 8234 ) 8235 xt "21000,96000,24000,96000" 8236 pts [ 8237 "21000,96000" 8238 "24000,96000" 8239 ] 8240 ) 8241 start &87 8242 end &82 8243 sat 32 8244 eat 1 8245 sty 1 8246 stc 0 8247 st 0 8248 sf 1 8249 si 0 8250 tg (WTG 8251 uid 3356,0 8252 ps "ConnStartEndStrategy" 8253 stg "STSignalDisplayStrategy" 8254 f (Text 8255 uid 3357,0 8256 va (VaSet 8257 isHidden 1 8258 ) 8259 xt "23000,95000,25300,96000" 8260 st "A1_D" 8261 blo "23000,95800" 8262 tm "WireNameMgr" 8263 ) 8264 ) 8265 on &91 8266 ) 8267 *272 (Wire 8268 uid 3360,0 8269 shape (OrthoPolyLine 8270 uid 3361,0 8271 va (VaSet 8272 vasetType 3 8273 lineWidth 2 8274 ) 8275 xt "21000,97000,24000,97000" 8276 pts [ 8277 "21000,97000" 8278 "24000,97000" 8279 ] 8280 ) 8281 start &88 8282 end &82 8283 sat 32 8284 eat 1 8285 sty 1 8286 stc 0 8287 st 0 8288 sf 1 8289 si 0 8290 tg (WTG 8291 uid 3364,0 8292 ps "ConnStartEndStrategy" 8293 stg "STSignalDisplayStrategy" 8294 f (Text 8295 uid 3365,0 8296 va (VaSet 8297 isHidden 1 8298 ) 8299 xt "23000,96000,25300,97000" 8300 st "A2_D" 8301 blo "23000,96800" 8302 tm "WireNameMgr" 8303 ) 8304 ) 8305 on &92 8306 ) 8307 *273 (Wire 8308 uid 3368,0 8309 shape (OrthoPolyLine 8310 uid 3369,0 8311 va (VaSet 8312 vasetType 3 8313 lineWidth 2 8314 ) 8315 xt "21000,98000,24000,98000" 8316 pts [ 8317 "21000,98000" 8318 "24000,98000" 8319 ] 8320 ) 8321 start &89 8322 end &82 8323 sat 32 8324 eat 1 8325 sty 1 8326 stc 0 8327 st 0 8328 sf 1 8329 si 0 8330 tg (WTG 8331 uid 3372,0 8332 ps "ConnStartEndStrategy" 8333 stg "STSignalDisplayStrategy" 8334 f (Text 8335 uid 3373,0 8336 va (VaSet 8337 isHidden 1 8338 ) 8339 xt "23000,97000,25300,98000" 8340 st "A3_D" 8341 blo "23000,97800" 8342 tm "WireNameMgr" 8343 ) 8344 ) 8345 on &93 8346 ) 8347 *274 (Wire 8348 uid 3430,0 8349 shape (OrthoPolyLine 8350 uid 3431,0 8351 va (VaSet 8352 vasetType 3 8353 ) 8354 xt "21000,113000,24000,113000" 8355 pts [ 8356 "21000,113000" 8357 "24000,113000" 8358 ] 8359 ) 8360 start &162 8361 end &94 8362 sat 32 8363 eat 2 8364 stc 0 8365 st 0 8366 sf 1 8367 si 0 8368 tg (WTG 8369 uid 3434,0 8370 ps "ConnStartEndStrategy" 8371 stg "STSignalDisplayStrategy" 8372 f (Text 8373 uid 3435,0 8374 va (VaSet 8375 isHidden 1 8376 ) 8377 xt "23000,112000,27400,113000" 8378 st "D0_SRCLK" 8379 blo "23000,112800" 8380 tm "WireNameMgr" 8381 ) 8382 ) 8383 on &98 8384 ) 8385 *275 (Wire 8386 uid 3438,0 8387 shape (OrthoPolyLine 8388 uid 3439,0 8389 va (VaSet 8390 vasetType 3 8391 ) 8392 xt "21000,114000,24000,114000" 8393 pts [ 8394 "21000,114000" 8395 "24000,114000" 8396 ] 8397 ) 8398 start &163 8399 end &94 8400 sat 32 8401 eat 2 8402 stc 0 8403 st 0 8404 sf 1 8405 si 0 8406 tg (WTG 8407 uid 3442,0 8408 ps "ConnStartEndStrategy" 8409 stg "STSignalDisplayStrategy" 8410 f (Text 8411 uid 3443,0 8412 va (VaSet 8413 isHidden 1 8414 ) 8415 xt "23000,113000,27400,114000" 8416 st "D1_SRCLK" 8417 blo "23000,113800" 8418 tm "WireNameMgr" 8419 ) 8420 ) 8421 on &99 8422 ) 8423 *276 (Wire 8424 uid 3446,0 8425 shape (OrthoPolyLine 8426 uid 3447,0 8427 va (VaSet 8428 vasetType 3 8429 ) 8430 xt "21000,115000,24000,115000" 8431 pts [ 8432 "21000,115000" 8433 "24000,115000" 8434 ] 8435 ) 8436 start &164 8437 end &94 8438 sat 32 8439 eat 2 8440 stc 0 8441 st 0 8442 sf 1 8443 si 0 8444 tg (WTG 8445 uid 3450,0 8446 ps "ConnStartEndStrategy" 8447 stg "STSignalDisplayStrategy" 8448 f (Text 8449 uid 3451,0 8450 va (VaSet 8451 isHidden 1 8452 ) 8453 xt "23000,114000,27400,115000" 8454 st "D2_SRCLK" 8455 blo "23000,114800" 8456 tm "WireNameMgr" 8457 ) 8458 ) 8459 on &100 8460 ) 8461 *277 (Wire 8462 uid 3454,0 8463 shape (OrthoPolyLine 8464 uid 3455,0 8465 va (VaSet 8466 vasetType 3 8467 ) 8468 xt "21000,116000,24000,116000" 8469 pts [ 8470 "21000,116000" 8471 "24000,116000" 8472 ] 8473 ) 8474 start &165 8475 end &94 8476 sat 32 8477 eat 2 8478 stc 0 8479 st 0 8480 sf 1 8481 si 0 8482 tg (WTG 8483 uid 3458,0 8484 ps "ConnStartEndStrategy" 8485 stg "STSignalDisplayStrategy" 8486 f (Text 8487 uid 3459,0 8488 va (VaSet 8489 isHidden 1 8490 ) 8491 xt "23000,115000,27400,116000" 8492 st "D3_SRCLK" 8493 blo "23000,115800" 8494 tm "WireNameMgr" 8495 ) 8496 ) 8497 on &101 8498 ) 8499 *278 (Wire 8500 uid 3574,0 8501 shape (OrthoPolyLine 8502 uid 3575,0 8503 va (VaSet 8504 vasetType 3 8505 ) 8506 xt "108000,89000,111000,89000" 8507 pts [ 8508 "111000,89000" 8509 "108000,89000" 8510 ] 8511 ) 8512 start &119 8513 end &115 8514 sat 32 8515 eat 2 8516 stc 0 8517 st 0 8518 sf 1 8519 si 0 8520 tg (WTG 8521 uid 3578,0 8522 ps "ConnStartEndStrategy" 8523 stg "STSignalDisplayStrategy" 8524 f (Text 8525 uid 3579,0 8526 va (VaSet 8527 isHidden 1 8528 ) 8529 xt "108000,88000,110800,89000" 8530 st "T0_CS" 8531 blo "108000,88800" 8532 tm "WireNameMgr" 8533 ) 8534 ) 8535 on &123 8536 ) 8537 *279 (Wire 8538 uid 3582,0 8539 shape (OrthoPolyLine 8540 uid 3583,0 8541 va (VaSet 8542 vasetType 3 8543 ) 8544 xt "108000,90000,111000,90000" 8545 pts [ 8546 "111000,90000" 8547 "108000,90000" 8548 ] 8549 ) 8550 start &120 8551 end &115 8552 sat 32 8553 eat 2 8554 stc 0 8555 st 0 8556 sf 1 8557 si 0 8558 tg (WTG 8559 uid 3586,0 8560 ps "ConnStartEndStrategy" 8561 stg "STSignalDisplayStrategy" 8562 f (Text 8563 uid 3587,0 8564 va (VaSet 8565 isHidden 1 8566 ) 8567 xt "108000,89000,110800,90000" 8568 st "T1_CS" 8569 blo "108000,89800" 8570 tm "WireNameMgr" 8571 ) 8572 ) 8573 on &124 8574 ) 8575 *280 (Wire 8576 uid 3590,0 8577 shape (OrthoPolyLine 8578 uid 3591,0 8579 va (VaSet 8580 vasetType 3 8581 ) 8582 xt "108000,91000,111000,91000" 8583 pts [ 8584 "111000,91000" 8585 "108000,91000" 8586 ] 8587 ) 8588 start &121 8589 end &115 8590 sat 32 8591 eat 2 8592 stc 0 8593 st 0 8594 sf 1 8595 si 0 8596 tg (WTG 8597 uid 3594,0 8598 ps "ConnStartEndStrategy" 8599 stg "STSignalDisplayStrategy" 8600 f (Text 8601 uid 3595,0 8602 va (VaSet 8603 isHidden 1 8604 ) 8605 xt "108000,90000,110800,91000" 8606 st "T2_CS" 8607 blo "108000,90800" 8608 tm "WireNameMgr" 8609 ) 8610 ) 8611 on &125 8612 ) 8613 *281 (Wire 8614 uid 3598,0 8615 shape (OrthoPolyLine 8616 uid 3599,0 8617 va (VaSet 8618 vasetType 3 8619 ) 8620 xt "108000,92000,111000,92000" 8621 pts [ 8622 "111000,92000" 8623 "108000,92000" 8624 ] 8625 ) 8626 start &122 8627 end &115 8628 sat 32 8629 eat 2 8630 stc 0 8631 st 0 8632 sf 1 8633 si 0 8634 tg (WTG 8635 uid 3602,0 8636 ps "ConnStartEndStrategy" 8637 stg "STSignalDisplayStrategy" 8638 f (Text 8639 uid 3603,0 8640 va (VaSet 8641 isHidden 1 8642 ) 8643 xt "108000,91000,110800,92000" 8644 st "T3_CS" 8645 blo "108000,91800" 8646 tm "WireNameMgr" 8647 ) 8648 ) 8649 on &126 8650 ) 8651 *282 (Wire 8652 uid 3682,0 8653 shape (OrthoPolyLine 8654 uid 3683,0 8655 va (VaSet 8656 vasetType 3 8657 ) 8658 xt "80750,100000,111000,100000" 8659 pts [ 8660 "80750,100000" 8661 "111000,100000" 8662 ] 8663 ) 8664 start &42 8665 end &138 8666 sat 32 8667 eat 32 8668 stc 0 8669 st 0 8670 sf 1 8671 si 0 8672 tg (WTG 8673 uid 3686,0 8674 ps "ConnStartEndStrategy" 8675 stg "STSignalDisplayStrategy" 8676 f (Text 8677 uid 3687,0 8678 va (VaSet 8679 isHidden 1 8680 ) 8681 xt "82000,99000,84400,100000" 8682 st "MOSI" 8683 blo "82000,99800" 8684 tm "WireNameMgr" 8685 ) 8686 ) 8687 on &137 8688 ) 8689 *283 (Wire 8690 uid 3778,0 8691 shape (OrthoPolyLine 8692 uid 3779,0 8693 va (VaSet 8694 vasetType 3 8695 ) 8696 xt "108000,103000,111000,103000" 8697 pts [ 8698 "111000,103000" 8699 "108000,103000" 8700 ] 8701 ) 8702 start &144 8703 end &140 8704 sat 32 8705 eat 2 8706 stc 0 8707 st 0 8708 sf 1 8709 si 0 8710 tg (WTG 8711 uid 3782,0 8712 ps "ConnStartEndStrategy" 8713 stg "STSignalDisplayStrategy" 8714 f (Text 8715 uid 3783,0 8716 va (VaSet 8717 isHidden 1 8718 ) 8719 xt "108000,102000,111000,103000" 8720 st "TRG_V" 8721 blo "108000,102800" 8722 tm "WireNameMgr" 8723 ) 8724 ) 8725 on &153 8726 ) 8727 *284 (Wire 8728 uid 3786,0 8729 shape (OrthoPolyLine 8730 uid 3787,0 8731 va (VaSet 8732 vasetType 3 8733 ) 8734 xt "108000,104000,111000,104000" 8735 pts [ 8736 "111000,104000" 8737 "108000,104000" 8738 ] 8739 ) 8740 start &145 8741 end &140 8742 sat 32 8743 eat 2 8744 stc 0 8745 st 0 8746 sf 1 8747 si 0 8748 tg (WTG 8749 uid 3790,0 8750 ps "ConnStartEndStrategy" 8751 stg "STSignalDisplayStrategy" 8752 f (Text 8753 uid 3791,0 8754 va (VaSet 8755 isHidden 1 8756 ) 8757 xt "108000,103000,113600,104000" 8758 st "RS485_C_RE" 8759 blo "108000,103800" 8760 tm "WireNameMgr" 8761 ) 8762 ) 8763 on &154 8764 ) 8765 *285 (Wire 8766 uid 3794,0 8767 shape (OrthoPolyLine 8768 uid 3795,0 8769 va (VaSet 8770 vasetType 3 8771 ) 8772 xt "108000,105000,111000,105000" 8773 pts [ 8774 "111000,105000" 8775 "108000,105000" 8776 ] 8777 ) 8778 start &146 8779 end &140 8780 sat 32 8781 eat 2 8782 stc 0 8783 st 0 8784 sf 1 8785 si 0 8786 tg (WTG 8787 uid 3798,0 8788 ps "ConnStartEndStrategy" 8789 stg "STSignalDisplayStrategy" 8790 f (Text 8791 uid 3799,0 8792 va (VaSet 8793 isHidden 1 8794 ) 8795 xt "108000,104000,113600,105000" 8796 st "RS485_C_DE" 8797 blo "108000,104800" 8798 tm "WireNameMgr" 8799 ) 8800 ) 8801 on &155 8802 ) 8803 *286 (Wire 8804 uid 3802,0 8805 shape (OrthoPolyLine 8806 uid 3803,0 8807 va (VaSet 8808 vasetType 3 8809 ) 8810 xt "108000,106000,111000,106000" 8811 pts [ 8812 "111000,106000" 8813 "108000,106000" 8814 ] 8815 ) 8816 start &147 8817 end &140 8818 sat 32 8819 eat 2 8820 stc 0 8821 st 0 8822 sf 1 8823 si 0 8824 tg (WTG 8825 uid 3806,0 8826 ps "ConnStartEndStrategy" 8827 stg "STSignalDisplayStrategy" 8828 f (Text 8829 uid 3807,0 8830 va (VaSet 8831 isHidden 1 8832 ) 8833 xt "108000,105000,113500,106000" 8834 st "RS485_E_RE" 8835 blo "108000,105800" 8836 tm "WireNameMgr" 8837 ) 8838 ) 8839 on &156 8840 ) 8841 *287 (Wire 8842 uid 3810,0 8843 shape (OrthoPolyLine 8844 uid 3811,0 8845 va (VaSet 8846 vasetType 3 8847 ) 8848 xt "108000,107000,111000,107000" 8849 pts [ 8850 "111000,107000" 8851 "108000,107000" 8852 ] 8853 ) 8854 start &148 8855 end &140 8856 sat 32 8857 eat 2 8858 stc 0 8859 st 0 8860 sf 1 8861 si 0 8862 tg (WTG 8863 uid 3814,0 8864 ps "ConnStartEndStrategy" 8865 stg "STSignalDisplayStrategy" 8866 f (Text 8867 uid 3815,0 8868 va (VaSet 8869 isHidden 1 8870 ) 8871 xt "108000,106000,113500,107000" 8872 st "RS485_E_DE" 8873 blo "108000,106800" 8874 tm "WireNameMgr" 8875 ) 8876 ) 8877 on &157 8878 ) 8879 *288 (Wire 8880 uid 3826,0 8881 shape (OrthoPolyLine 8882 uid 3827,0 8883 va (VaSet 8884 vasetType 3 8885 ) 8886 xt "108000,109000,111000,109000" 8887 pts [ 8888 "111000,109000" 8889 "108000,109000" 8890 ] 8891 ) 8892 start &150 8893 end &140 8894 sat 32 8895 eat 2 8896 stc 0 8897 st 0 8898 sf 1 8899 si 0 8900 tg (WTG 8901 uid 3830,0 8902 ps "ConnStartEndStrategy" 8903 stg "STSignalDisplayStrategy" 8904 f (Text 8905 uid 3831,0 8906 va (VaSet 8907 isHidden 1 8908 ) 8909 xt "108000,108000,110300,109000" 8910 st "SRIN" 8911 blo "108000,108800" 8912 tm "WireNameMgr" 8913 ) 8914 ) 8915 on &159 8916 ) 8917 *289 (Wire 8918 uid 3834,0 8919 shape (OrthoPolyLine 8920 uid 3835,0 8921 va (VaSet 8922 vasetType 3 8923 ) 8924 xt "108000,110000,111000,110000" 8925 pts [ 8926 "111000,110000" 8927 "108000,110000" 8928 ] 8929 ) 8930 start &151 8931 end &140 8932 sat 32 8933 eat 2 8934 stc 0 8935 st 0 8936 sf 1 8937 si 0 8938 tg (WTG 8939 uid 3838,0 8940 ps "ConnStartEndStrategy" 8941 stg "STSignalDisplayStrategy" 8942 f (Text 8943 uid 3839,0 8944 va (VaSet 8945 isHidden 1 8946 ) 8947 xt "108000,109000,110900,110000" 8948 st "EE_CS" 8949 blo "108000,109800" 8950 tm "WireNameMgr" 8951 ) 8952 ) 8953 on &160 8954 ) 8955 *290 (Wire 8956 uid 3842,0 8957 shape (OrthoPolyLine 8958 uid 3843,0 8959 va (VaSet 8960 vasetType 3 8961 lineWidth 2 8962 ) 8963 xt "108000,111000,111000,111000" 8964 pts [ 8965 "111000,111000" 8966 "108000,111000" 8967 ] 8968 ) 8969 start &152 8970 end &140 8971 sat 32 8972 eat 2 8973 sty 1 8974 stc 0 8975 st 0 8976 sf 1 8977 si 0 8978 tg (WTG 8979 uid 3846,0 8980 ps "ConnStartEndStrategy" 8981 stg "STSignalDisplayStrategy" 8982 f (Text 8983 uid 3847,0 8984 va (VaSet 8985 isHidden 1 8986 ) 8987 xt "108000,110000,109900,111000" 8988 st "LED" 8989 blo "108000,110800" 8990 tm "WireNameMgr" 8991 ) 8992 ) 8993 on &161 8994 ) 8995 *291 (Wire 8996 uid 4942,0 8997 shape (OrthoPolyLine 8998 uid 4943,0 8999 va (VaSet 9000 vasetType 3 9001 lineWidth 2 9002 ) 9003 xt "80750,120000,111000,120000" 9004 pts [ 9005 "80750,120000" 9006 "111000,120000" 9007 ] 9008 ) 9009 start &14 9010 end &166 9011 sat 32 8763 xt "39000,132000,44000,132000" 8764 pts [ 8765 "39000,132000" 8766 "44000,132000" 8767 ] 8768 ) 8769 start &201 8770 end &205 8771 sat 2 9012 8772 eat 32 9013 8773 sty 1 9014 stc 09015 8774 st 0 9016 8775 sf 1 9017 8776 si 0 9018 8777 tg (WTG 9019 uid 4948,08778 uid 7148,0 9020 8779 ps "ConnStartEndStrategy" 9021 8780 stg "STSignalDisplayStrategy" 9022 8781 f (Text 9023 uid 4949,08782 uid 7149,0 9024 8783 va (VaSet 9025 8784 isHidden 1 9026 8785 ) 9027 xt " 82750,117000,84650,118000"9028 st " D_T"9029 blo " 82750,117800"9030 tm "WireNameMgr" 9031 ) 9032 ) 9033 on & 1679034 ) 9035 *2 92(Wire9036 uid 6130,08786 xt "41000,131000,45800,132000" 8787 st "A1_T : (7:0)" 8788 blo "41000,131800" 8789 tm "WireNameMgr" 8790 ) 8791 ) 8792 on &206 8793 ) 8794 *281 (Wire 8795 uid 7477,0 9037 8796 shape (OrthoPolyLine 9038 uid 6131,08797 uid 7478,0 9039 8798 va (VaSet 9040 8799 vasetType 3 9041 8800 ) 9042 xt "19000,78000,51250,78000" 9043 pts [ 9044 "19000,78000" 9045 "51250,78000" 9046 ] 9047 ) 9048 start &193 9049 end &15 9050 sat 32 9051 eat 32 9052 st 0 9053 sf 1 9054 si 0 9055 tg (WTG 9056 uid 6136,0 9057 ps "ConnStartEndStrategy" 9058 stg "STSignalDisplayStrategy" 9059 f (Text 9060 uid 6137,0 9061 va (VaSet 9062 ) 9063 xt "21000,77000,24700,78000" 9064 st "TRG_OR" 9065 blo "21000,77800" 9066 tm "WireNameMgr" 9067 ) 9068 ) 9069 on &170 9070 ) 9071 *293 (Wire 9072 uid 6288,0 9073 shape (OrthoPolyLine 9074 uid 6289,0 9075 va (VaSet 9076 vasetType 3 9077 ) 9078 xt "1750,79000,13000,89000" 9079 pts [ 9080 "1750,89000" 9081 "9000,89000" 9082 "9000,86000" 9083 "9000,79000" 9084 "13000,79000" 9085 ] 9086 ) 9087 start &174 9088 end &191 9089 sat 32 9090 eat 32 9091 st 0 9092 sf 1 9093 si 0 9094 tg (WTG 9095 uid 6294,0 9096 ps "ConnStartEndStrategy" 9097 stg "STSignalDisplayStrategy" 9098 f (Text 9099 uid 6295,0 9100 va (VaSet 9101 ) 9102 xt "4000,88000,8600,89000" 9103 st "trigger_out" 9104 blo "4000,88800" 9105 tm "WireNameMgr" 9106 ) 9107 ) 9108 on &178 9109 ) 9110 *294 (Wire 9111 uid 6306,0 9112 shape (OrthoPolyLine 9113 uid 6307,0 9114 va (VaSet 9115 vasetType 3 9116 ) 9117 xt "-28000,89000,-22000,89000" 9118 pts [ 9119 "-28000,89000" 9120 "-22000,89000" 9121 ] 9122 ) 9123 start &168 9124 end &181 8801 xt "80750,87000,91000,87000" 8802 pts [ 8803 "80750,87000" 8804 "91000,87000" 8805 ] 8806 ) 8807 start &38 8808 end &209 9125 8809 es 0 9126 8810 sat 32 … … 9130 8814 si 0 9131 8815 tg (WTG 9132 uid 6312,08816 uid 7483,0 9133 8817 ps "ConnStartEndStrategy" 9134 8818 stg "STSignalDisplayStrategy" 9135 8819 f (Text 9136 uid 6313,09137 va (VaSet 9138 ) 9139 xt " -26000,88000,-21500,89000"9140 st " TEST_TRG"9141 blo " -26000,88800"9142 tm "WireNameMgr" 9143 ) 9144 ) 9145 on & 1699146 ) 9147 *2 95(Wire9148 uid 6328,08820 uid 7484,0 8821 va (VaSet 8822 ) 8823 xt "83000,86000,85700,87000" 8824 st "dummy" 8825 blo "83000,86800" 8826 tm "WireNameMgr" 8827 ) 8828 ) 8829 on &207 8830 ) 8831 *282 (Wire 8832 uid 8853,0 9149 8833 shape (OrthoPolyLine 9150 uid 6329,0 9151 va (VaSet 9152 vasetType 3 9153 ) 9154 xt "-17000,89000,-11750,89000" 9155 pts [ 9156 "-17000,89000" 9157 "-11750,89000" 9158 ] 9159 ) 9160 start &183 9161 end &173 9162 sat 32 9163 eat 32 9164 st 0 9165 sf 1 9166 si 0 9167 tg (WTG 9168 uid 6334,0 9169 ps "ConnStartEndStrategy" 9170 stg "STSignalDisplayStrategy" 9171 f (Text 9172 uid 6335,0 9173 va (VaSet 9174 ) 9175 xt "-18000,92000,-11700,93000" 9176 st "not_TEST_TRG" 9177 blo "-18000,92800" 9178 tm "WireNameMgr" 9179 ) 9180 ) 9181 on &179 9182 ) 9183 *296 (Wire 9184 uid 6431,0 9185 shape (OrthoPolyLine 9186 uid 6432,0 9187 va (VaSet 9188 vasetType 3 9189 ) 9190 xt "80750,121000,111000,121000" 9191 pts [ 9192 "80750,121000" 9193 "111000,121000" 9194 ] 9195 ) 9196 start &43 9197 end &149 9198 sat 32 9199 eat 32 9200 stc 0 9201 st 0 9202 sf 1 9203 si 0 9204 tg (WTG 9205 uid 6435,0 9206 ps "ConnStartEndStrategy" 9207 stg "STSignalDisplayStrategy" 9208 f (Text 9209 uid 6436,0 9210 va (VaSet 9211 isHidden 1 9212 ) 9213 xt "92000,120000,96000,121000" 9214 st "DENABLE" 9215 blo "92000,120800" 9216 tm "WireNameMgr" 9217 ) 9218 ) 9219 on &158 9220 ) 9221 *297 (Wire 9222 uid 6787,0 9223 shape (OrthoPolyLine 9224 uid 6788,0 8834 uid 8854,0 9225 8835 va (VaSet 9226 8836 vasetType 3 9227 8837 lineWidth 2 9228 8838 ) 9229 xt "93000,132000,99000,132000" 9230 pts [ 9231 "93000,132000" 9232 "99000,132000" 9233 ] 9234 ) 9235 start &213 9236 end &217 8839 xt "10000,109000,51250,132000" 8840 pts [ 8841 "51250,109000" 8842 "10000,109000" 8843 "10000,132000" 8844 "31000,132000" 8845 ] 8846 ) 8847 start &30 8848 end &201 9237 8849 sat 32 9238 8850 eat 1 … … 9242 8854 si 0 9243 8855 tg (WTG 9244 uid 6791,08856 uid 8857,0 9245 8857 ps "ConnStartEndStrategy" 9246 8858 stg "STSignalDisplayStrategy" 9247 8859 f (Text 9248 uid 6792,0 9249 va (VaSet 9250 isHidden 1 9251 ) 9252 xt "95000,131000,101800,132000" 9253 st "D_PLLLCK : (3:0)" 9254 blo "95000,131800" 9255 tm "WireNameMgr" 9256 ) 9257 ) 9258 on &214 9259 ) 9260 *298 (Wire 9261 uid 6880,0 8860 uid 8858,0 8861 va (VaSet 8862 ) 8863 xt "42000,108000,50500,109000" 8864 st "drs_channel_id : (3:0)" 8865 blo "42000,108800" 8866 tm "WireNameMgr" 8867 ) 8868 ) 8869 on &221 8870 ) 8871 *283 (Wire 8872 uid 9193,0 9262 8873 shape (OrthoPolyLine 9263 uid 6881,08874 uid 9194,0 9264 8875 va (VaSet 9265 8876 vasetType 3 9266 8877 lineWidth 2 9267 8878 ) 9268 xt "102000,132000,109000,132000" 9269 pts [ 9270 "102000,132000" 9271 "109000,132000" 9272 ] 9273 ) 9274 start &217 9275 end &215 9276 sat 2 8879 xt "93000,136000,103000,136000" 8880 pts [ 8881 "93000,136000" 8882 "103000,136000" 8883 ] 8884 ) 8885 sat 16 8886 eat 16 8887 sty 1 8888 st 0 8889 sf 1 8890 si 0 8891 tg (WTG 8892 uid 9199,0 8893 ps "ConnStartEndStrategy" 8894 stg "STSignalDisplayStrategy" 8895 f (Text 8896 uid 9200,0 8897 va (VaSet 8898 ) 8899 xt "95000,135000,99800,136000" 8900 st "A0_T : (7:0)" 8901 blo "95000,135800" 8902 tm "WireNameMgr" 8903 ) 8904 ) 8905 on &222 8906 ) 8907 *284 (Wire 8908 uid 9300,0 8909 shape (OrthoPolyLine 8910 uid 9301,0 8911 va (VaSet 8912 vasetType 3 8913 lineWidth 2 8914 ) 8915 xt "54000,140000,64000,140000" 8916 pts [ 8917 "54000,140000" 8918 "64000,140000" 8919 ] 8920 ) 8921 end &223 8922 sat 16 9277 8923 eat 32 9278 8924 sty 1 … … 9281 8927 si 0 9282 8928 tg (WTG 9283 uid 6884,08929 uid 9304,0 9284 8930 ps "ConnStartEndStrategy" 9285 8931 stg "STSignalDisplayStrategy" 9286 8932 f (Text 9287 uid 6885,08933 uid 9305,0 9288 8934 va (VaSet 9289 8935 isHidden 1 9290 8936 ) 9291 xt " 104000,131000,108900,132000"9292 st " D_T2 : (3:0)"9293 blo " 104000,131800"9294 tm "WireNameMgr" 9295 ) 9296 ) 9297 on &2 169298 ) 9299 *2 99(Wire9300 uid 7102,08937 xt "56000,139000,60800,140000" 8938 st "A0_T : (7:0)" 8939 blo "56000,139800" 8940 tm "WireNameMgr" 8941 ) 8942 ) 8943 on &222 8944 ) 8945 *285 (Wire 8946 uid 9492,0 9301 8947 shape (OrthoPolyLine 9302 uid 7103,08948 uid 9493,0 9303 8949 va (VaSet 9304 8950 vasetType 3 9305 8951 ) 9306 xt "21000,13 2000,31000,132000"9307 pts [ 9308 "21000,13 2000"9309 "31000,13 2000"9310 ] 9311 ) 9312 end &2 218952 xt "21000,135000,31000,135000" 8953 pts [ 8954 "21000,135000" 8955 "31000,135000" 8956 ] 8957 ) 8958 end &201 9313 8959 sat 16 9314 8960 eat 1 … … 9317 8963 si 0 9318 8964 tg (WTG 9319 uid 7108,08965 uid 9498,0 9320 8966 ps "ConnStartEndStrategy" 9321 8967 stg "STSignalDisplayStrategy" 9322 8968 f (Text 9323 uid 7109,09324 va (VaSet 9325 ) 9326 xt "23000,13 1000,27600,132000"9327 st " D0_SROUT"9328 blo "23000,13 1800"9329 tm "WireNameMgr" 9330 ) 9331 ) 9332 on &1 069333 ) 9334 * 300(Wire9335 uid 7110,08969 uid 9499,0 8970 va (VaSet 8971 ) 8972 xt "23000,134000,26700,135000" 8973 st "TRG_OR" 8974 blo "23000,134800" 8975 tm "WireNameMgr" 8976 ) 8977 ) 8978 on &169 8979 ) 8980 *286 (Wire 8981 uid 9502,0 9336 8982 shape (OrthoPolyLine 9337 uid 7111,08983 uid 9503,0 9338 8984 va (VaSet 9339 8985 vasetType 3 9340 8986 ) 9341 xt " 21000,133000,31000,133000"9342 pts [ 9343 " 21000,133000"9344 " 31000,133000"9345 ] 9346 ) 9347 end &221 9348 sat 169349 eat 1 8987 xt "46000,69000,51250,69000" 8988 pts [ 8989 "51250,69000" 8990 "46000,69000" 8991 ] 8992 ) 8993 start &26 8994 sat 32 8995 eat 16 9350 8996 st 0 9351 8997 sf 1 9352 8998 si 0 9353 8999 tg (WTG 9354 uid 7116,09000 uid 9506,0 9355 9001 ps "ConnStartEndStrategy" 9356 9002 stg "STSignalDisplayStrategy" 9357 9003 f (Text 9358 uid 7117,0 9359 va (VaSet 9360 ) 9361 xt "23000,132000,27600,133000" 9362 st "D1_SROUT" 9363 blo "23000,132800" 9364 tm "WireNameMgr" 9365 ) 9366 ) 9367 on &107 9368 ) 9369 *301 (Wire 9370 uid 7118,0 9371 shape (OrthoPolyLine 9372 uid 7119,0 9373 va (VaSet 9374 vasetType 3 9375 ) 9376 xt "21000,134000,31000,134000" 9377 pts [ 9378 "21000,134000" 9379 "31000,134000" 9380 ] 9381 ) 9382 end &221 9383 sat 16 9384 eat 1 9385 st 0 9386 sf 1 9387 si 0 9388 tg (WTG 9389 uid 7124,0 9390 ps "ConnStartEndStrategy" 9391 stg "STSignalDisplayStrategy" 9392 f (Text 9393 uid 7125,0 9394 va (VaSet 9395 ) 9396 xt "23000,133000,27200,134000" 9397 st "RSRLOAD" 9398 blo "23000,133800" 9399 tm "WireNameMgr" 9400 ) 9401 ) 9402 on &64 9403 ) 9404 *302 (Wire 9405 uid 7144,0 9406 shape (OrthoPolyLine 9407 uid 7145,0 9408 va (VaSet 9409 vasetType 3 9410 lineWidth 2 9411 ) 9412 xt "39000,132000,44000,132000" 9413 pts [ 9414 "39000,132000" 9415 "44000,132000" 9416 ] 9417 ) 9418 start &221 9419 end &225 9420 sat 2 9421 eat 32 9422 sty 1 9423 st 0 9424 sf 1 9425 si 0 9426 tg (WTG 9427 uid 7148,0 9428 ps "ConnStartEndStrategy" 9429 stg "STSignalDisplayStrategy" 9430 f (Text 9431 uid 7149,0 9432 va (VaSet 9433 isHidden 1 9434 ) 9435 xt "41000,131000,45800,132000" 9436 st "A1_T : (3:0)" 9437 blo "41000,131800" 9438 tm "WireNameMgr" 9439 ) 9440 ) 9441 on &226 9442 ) 9443 *303 (Wire 9444 uid 7477,0 9445 shape (OrthoPolyLine 9446 uid 7478,0 9447 va (VaSet 9448 vasetType 3 9449 ) 9450 xt "80750,87000,91000,87000" 9451 pts [ 9452 "80750,87000" 9453 "91000,87000" 9454 ] 9455 ) 9456 start &38 9457 end &229 9458 es 0 9459 sat 32 9460 eat 32 9461 st 0 9462 sf 1 9463 si 0 9464 tg (WTG 9465 uid 7483,0 9466 ps "ConnStartEndStrategy" 9467 stg "STSignalDisplayStrategy" 9468 f (Text 9469 uid 7484,0 9470 va (VaSet 9471 ) 9472 xt "83000,86000,85700,87000" 9473 st "dummy" 9474 blo "83000,86800" 9475 tm "WireNameMgr" 9476 ) 9477 ) 9478 on &227 9479 ) 9480 *304 (Wire 9481 uid 7487,0 9482 shape (OrthoPolyLine 9483 uid 7488,0 9484 va (VaSet 9485 vasetType 3 9486 ) 9487 xt "21000,135000,31000,135000" 9488 pts [ 9489 "21000,135000" 9490 "31000,135000" 9491 ] 9492 ) 9493 end &221 9494 sat 16 9495 eat 1 9496 st 0 9497 sf 1 9498 si 0 9499 tg (WTG 9500 uid 7493,0 9501 ps "ConnStartEndStrategy" 9502 stg "STSignalDisplayStrategy" 9503 f (Text 9504 uid 7494,0 9505 va (VaSet 9506 ) 9507 xt "23000,134000,25700,135000" 9508 st "dummy" 9509 blo "23000,134800" 9510 tm "WireNameMgr" 9511 ) 9512 ) 9513 on &227 9004 uid 9507,0 9005 va (VaSet 9006 ) 9007 xt "47000,68000,50100,69000" 9008 st "CLK_50" 9009 blo "47000,68800" 9010 tm "WireNameMgr" 9011 ) 9012 ) 9013 on &224 9514 9014 ) 9515 9015 ] … … 9525 9025 color "26368,26368,26368" 9526 9026 ) 9527 packageList * 305(PackageList9027 packageList *287 (PackageList 9528 9028 uid 41,0 9529 9029 stg "VerticalLayoutStrategy" 9530 9030 textVec [ 9531 * 306(Text9031 *288 (Text 9532 9032 uid 42,0 9533 9033 va (VaSet … … 9538 9038 blo "0,800" 9539 9039 ) 9540 * 307(MLText9040 *289 (MLText 9541 9041 uid 43,0 9542 9042 va (VaSet … … 9559 9059 stg "VerticalLayoutStrategy" 9560 9060 textVec [ 9561 * 308(Text9061 *290 (Text 9562 9062 uid 45,0 9563 9063 va (VaSet … … 9569 9069 blo "20000,800" 9570 9070 ) 9571 * 309(Text9071 *291 (Text 9572 9072 uid 46,0 9573 9073 va (VaSet … … 9579 9079 blo "20000,1800" 9580 9080 ) 9581 * 310(MLText9081 *292 (MLText 9582 9082 uid 47,0 9583 9083 va (VaSet … … 9589 9089 tm "BdCompilerDirectivesTextMgr" 9590 9090 ) 9591 * 311(Text9091 *293 (Text 9592 9092 uid 48,0 9593 9093 va (VaSet … … 9599 9099 blo "20000,4800" 9600 9100 ) 9601 * 312(MLText9101 *294 (MLText 9602 9102 uid 49,0 9603 9103 va (VaSet … … 9607 9107 tm "BdCompilerDirectivesTextMgr" 9608 9108 ) 9609 * 313(Text9109 *295 (Text 9610 9110 uid 50,0 9611 9111 va (VaSet … … 9617 9117 blo "20000,5800" 9618 9118 ) 9619 * 314(MLText9119 *296 (MLText 9620 9120 uid 51,0 9621 9121 va (VaSet … … 9628 9128 associable 1 9629 9129 ) 9630 windowSize "0, 0,1281,1002"9631 viewArea "- 23100,-5300,61780,62940"9632 cachedDiagramExtent " -35500,0,699000,450107"9130 windowSize "0,22,1281,1024" 9131 viewArea "-13800,92200,71080,160440" 9132 cachedDiagramExtent "0,0,699000,450107" 9633 9133 pageSetupInfo (PageSetupInfo 9634 9134 ptrCmd "" … … 9641 9141 ) 9642 9142 hasePageBreakOrigin 1 9643 pageBreakOrigin " -73000,0"9644 lastUid 8652,09143 pageBreakOrigin "0,0" 9144 lastUid 9715,0 9645 9145 defaultCommentText (CommentText 9646 9146 shape (Rectangle … … 9704 9204 stg "VerticalLayoutStrategy" 9705 9205 textVec [ 9706 * 315(Text9206 *297 (Text 9707 9207 va (VaSet 9708 9208 font "Arial,8,1" … … 9713 9213 tm "BdLibraryNameMgr" 9714 9214 ) 9715 * 316(Text9215 *298 (Text 9716 9216 va (VaSet 9717 9217 font "Arial,8,1" … … 9722 9222 tm "BlkNameMgr" 9723 9223 ) 9724 * 317(Text9224 *299 (Text 9725 9225 va (VaSet 9726 9226 font "Arial,8,1" … … 9773 9273 stg "VerticalLayoutStrategy" 9774 9274 textVec [ 9775 *3 18(Text9275 *300 (Text 9776 9276 va (VaSet 9777 9277 font "Arial,8,1" … … 9781 9281 blo "550,4300" 9782 9282 ) 9783 *3 19(Text9283 *301 (Text 9784 9284 va (VaSet 9785 9285 font "Arial,8,1" … … 9789 9289 blo "550,5300" 9790 9290 ) 9791 *3 20(Text9291 *302 (Text 9792 9292 va (VaSet 9793 9293 font "Arial,8,1" … … 9838 9338 stg "VerticalLayoutStrategy" 9839 9339 textVec [ 9840 *3 21(Text9340 *303 (Text 9841 9341 va (VaSet 9842 9342 font "Arial,8,1" … … 9847 9347 tm "BdLibraryNameMgr" 9848 9348 ) 9849 *3 22(Text9349 *304 (Text 9850 9350 va (VaSet 9851 9351 font "Arial,8,1" … … 9856 9356 tm "CptNameMgr" 9857 9357 ) 9858 *3 23(Text9358 *305 (Text 9859 9359 va (VaSet 9860 9360 font "Arial,8,1" … … 9910 9410 stg "VerticalLayoutStrategy" 9911 9411 textVec [ 9912 *3 24(Text9412 *306 (Text 9913 9413 va (VaSet 9914 9414 font "Arial,8,1" … … 9918 9418 blo "500,4300" 9919 9419 ) 9920 *3 25(Text9420 *307 (Text 9921 9421 va (VaSet 9922 9422 font "Arial,8,1" … … 9926 9426 blo "500,5300" 9927 9427 ) 9928 *3 26(Text9428 *308 (Text 9929 9429 va (VaSet 9930 9430 font "Arial,8,1" … … 9971 9471 stg "VerticalLayoutStrategy" 9972 9472 textVec [ 9973 *3 27(Text9473 *309 (Text 9974 9474 va (VaSet 9975 9475 font "Arial,8,1" … … 9979 9479 blo "50,4300" 9980 9480 ) 9981 *3 28(Text9481 *310 (Text 9982 9482 va (VaSet 9983 9483 font "Arial,8,1" … … 9987 9487 blo "50,5300" 9988 9488 ) 9989 *3 29(Text9489 *311 (Text 9990 9490 va (VaSet 9991 9491 font "Arial,8,1" … … 10028 9528 stg "VerticalLayoutStrategy" 10029 9529 textVec [ 10030 *3 30(Text9530 *312 (Text 10031 9531 va (VaSet 10032 9532 font "Arial,8,1" … … 10037 9537 tm "HdlTextNameMgr" 10038 9538 ) 10039 *3 31(Text9539 *313 (Text 10040 9540 va (VaSet 10041 9541 font "Arial,8,1" … … 10440 9940 stg "VerticalLayoutStrategy" 10441 9941 textVec [ 10442 *3 32(Text9942 *314 (Text 10443 9943 va (VaSet 10444 9944 font "Arial,8,1" … … 10448 9948 blo "14100,20800" 10449 9949 ) 10450 *3 33(MLText9950 *315 (MLText 10451 9951 va (VaSet 10452 9952 ) … … 10500 10000 stg "VerticalLayoutStrategy" 10501 10001 textVec [ 10502 *3 34(Text10002 *316 (Text 10503 10003 va (VaSet 10504 10004 font "Arial,8,1" … … 10508 10008 blo "14100,20800" 10509 10009 ) 10510 *3 35(MLText10010 *317 (MLText 10511 10011 va (VaSet 10512 10012 ) … … 10626 10126 font "Arial,8,1" 10627 10127 ) 10628 xt "37000,43 000,44100,44000"10128 xt "37000,43800,44100,44800" 10629 10129 st "Diagram Signals:" 10630 blo "37000,4 3800"10130 blo "37000,44600" 10631 10131 ) 10632 10132 postUserLabel (Text … … 10652 10152 commonDM (CommonDM 10653 10153 ldm (LogicalDM 10654 suid 1 58,010154 suid 163,0 10655 10155 usingSuid 1 10656 emptyRow *3 36(LEmptyRow10156 emptyRow *318 (LEmptyRow 10657 10157 ) 10658 10158 uid 54,0 10659 10159 optionalChildren [ 10660 *3 37(RefLabelRowHdr10661 ) 10662 *3 38(TitleRowHdr10663 ) 10664 *3 39(FilterRowHdr10665 ) 10666 *3 40(RefLabelColHdr10160 *319 (RefLabelRowHdr 10161 ) 10162 *320 (TitleRowHdr 10163 ) 10164 *321 (FilterRowHdr 10165 ) 10166 *322 (RefLabelColHdr 10667 10167 tm "RefLabelColHdrMgr" 10668 10168 ) 10669 *3 41(RowExpandColHdr10169 *323 (RowExpandColHdr 10670 10170 tm "RowExpandColHdrMgr" 10671 10171 ) 10672 *3 42(GroupColHdr10172 *324 (GroupColHdr 10673 10173 tm "GroupColHdrMgr" 10674 10174 ) 10675 *3 43(NameColHdr10175 *325 (NameColHdr 10676 10176 tm "BlockDiagramNameColHdrMgr" 10677 10177 ) 10678 *3 44(ModeColHdr10178 *326 (ModeColHdr 10679 10179 tm "BlockDiagramModeColHdrMgr" 10680 10180 ) 10681 *3 45(TypeColHdr10181 *327 (TypeColHdr 10682 10182 tm "BlockDiagramTypeColHdrMgr" 10683 10183 ) 10684 *3 46(BoundsColHdr10184 *328 (BoundsColHdr 10685 10185 tm "BlockDiagramBoundsColHdrMgr" 10686 10186 ) 10687 *3 47(InitColHdr10187 *329 (InitColHdr 10688 10188 tm "BlockDiagramInitColHdrMgr" 10689 10189 ) 10690 *3 48(EolColHdr10190 *330 (EolColHdr 10691 10191 tm "BlockDiagramEolColHdrMgr" 10692 10192 ) 10693 *3 49(LeafLogPort10193 *331 (LeafLogPort 10694 10194 port (LogicalPort 10695 10195 m 4 … … 10700 10200 preAdd 0 10701 10201 posAdd 0 10702 o 5 510202 o 56 10703 10203 suid 5,0 10704 10204 ) … … 10706 10206 uid 327,0 10707 10207 ) 10708 *3 50(LeafLogPort10208 *332 (LeafLogPort 10709 10209 port (LogicalPort 10710 10210 m 4 … … 10713 10213 t "std_logic_vector" 10714 10214 b "(1 downto 0)" 10715 o 5 610215 o 57 10716 10216 suid 6,0 10717 10217 ) … … 10719 10219 uid 329,0 10720 10220 ) 10721 *3 51(LeafLogPort10221 *333 (LeafLogPort 10722 10222 port (LogicalPort 10723 10223 m 4 … … 10725 10225 n "adc_data_array" 10726 10226 t "adc_data_array_type" 10727 o 5 410227 o 55 10728 10228 suid 29,0 10729 10229 ) … … 10731 10231 uid 1491,0 10732 10232 ) 10733 *352 (LeafLogPort 10233 *334 (LeafLogPort 10234 port (LogicalPort 10235 m 1 10236 decl (Decl 10237 n "RSRLOAD" 10238 t "std_logic" 10239 o 36 10240 suid 57,0 10241 i "'0'" 10242 ) 10243 ) 10244 uid 2435,0 10245 ) 10246 *335 (LeafLogPort 10734 10247 port (LogicalPort 10735 10248 m 4 10736 10249 decl (Decl 10737 n "CLK_50"10738 t "std_logic"10739 preAdd 010740 posAdd 010741 o 5110742 suid 54,010743 )10744 )10745 uid 2275,010746 )10747 *353 (LeafLogPort10748 port (LogicalPort10749 m 110750 decl (Decl10751 n "RSRLOAD"10752 t "std_logic"10753 o 3510754 suid 57,010755 i "'0'"10756 )10757 )10758 uid 2435,010759 )10760 *354 (LeafLogPort10761 port (LogicalPort10762 m 410763 decl (Decl10764 10250 n "SRCLK" 10765 10251 t "std_logic" 10766 o 5 210252 o 53 10767 10253 suid 58,0 10768 10254 i "'0'" … … 10771 10257 uid 2437,0 10772 10258 ) 10773 *3 55(LeafLogPort10259 *336 (LeafLogPort 10774 10260 port (LogicalPort 10775 10261 m 4 … … 10778 10264 t "std_logic_vector" 10779 10265 b "(3 DOWNTO 0)" 10780 o 5910266 o 60 10781 10267 suid 65,0 10782 10268 ) … … 10784 10270 uid 3037,0 10785 10271 ) 10786 *3 56(LeafLogPort10272 *337 (LeafLogPort 10787 10273 port (LogicalPort 10788 10274 m 1 … … 10790 10276 n "DAC_CS" 10791 10277 t "std_logic" 10792 o 2 110278 o 22 10793 10279 suid 66,0 10794 10280 ) … … 10796 10282 uid 3039,0 10797 10283 ) 10798 *3 57(LeafLogPort10284 *338 (LeafLogPort 10799 10285 port (LogicalPort 10800 10286 decl (Decl … … 10809 10295 uid 3276,0 10810 10296 ) 10811 *3 58(LeafLogPort10297 *339 (LeafLogPort 10812 10298 port (LogicalPort 10813 10299 decl (Decl … … 10820 10306 uid 3278,0 10821 10307 ) 10822 *3 59(LeafLogPort10308 *340 (LeafLogPort 10823 10309 port (LogicalPort 10824 10310 m 1 … … 10827 10313 t "std_logic_vector" 10828 10314 b "(3 downto 0)" 10829 o 1 610315 o 17 10830 10316 suid 71,0 10831 10317 ) … … 10833 10319 uid 3280,0 10834 10320 ) 10835 *3 60(LeafLogPort10321 *341 (LeafLogPort 10836 10322 port (LogicalPort 10837 10323 m 4 … … 10839 10325 n "CLK_25_PS" 10840 10326 t "std_logic" 10841 o 5 010327 o 51 10842 10328 suid 72,0 10843 10329 ) … … 10845 10331 uid 3282,0 10846 10332 ) 10847 *3 61(LeafLogPort10333 *342 (LeafLogPort 10848 10334 port (LogicalPort 10849 10335 m 1 … … 10853 10339 preAdd 0 10854 10340 posAdd 0 10855 o 3 010341 o 31 10856 10342 suid 73,0 10857 10343 ) … … 10859 10345 uid 3382,0 10860 10346 ) 10861 *3 62(LeafLogPort10347 *343 (LeafLogPort 10862 10348 port (LogicalPort 10863 10349 decl (Decl … … 10871 10357 uid 3384,0 10872 10358 ) 10873 *3 63(LeafLogPort10359 *344 (LeafLogPort 10874 10360 port (LogicalPort 10875 10361 decl (Decl … … 10883 10369 uid 3386,0 10884 10370 ) 10885 *3 64(LeafLogPort10371 *345 (LeafLogPort 10886 10372 port (LogicalPort 10887 10373 decl (Decl … … 10895 10381 uid 3388,0 10896 10382 ) 10897 *3 65(LeafLogPort10383 *346 (LeafLogPort 10898 10384 port (LogicalPort 10899 10385 decl (Decl … … 10907 10393 uid 3390,0 10908 10394 ) 10909 *3 66(LeafLogPort10395 *347 (LeafLogPort 10910 10396 port (LogicalPort 10911 10397 decl (Decl … … 10919 10405 uid 3392,0 10920 10406 ) 10921 *3 67(LeafLogPort10407 *348 (LeafLogPort 10922 10408 port (LogicalPort 10923 10409 m 1 … … 10925 10411 n "D0_SRCLK" 10926 10412 t "STD_LOGIC" 10927 o 1 710413 o 18 10928 10414 suid 87,0 10929 10415 ) … … 10931 10417 uid 3468,0 10932 10418 ) 10933 *3 68(LeafLogPort10419 *349 (LeafLogPort 10934 10420 port (LogicalPort 10935 10421 m 1 … … 10937 10423 n "D1_SRCLK" 10938 10424 t "STD_LOGIC" 10939 o 1 810425 o 19 10940 10426 suid 88,0 10941 10427 ) … … 10943 10429 uid 3470,0 10944 10430 ) 10945 *3 69(LeafLogPort10431 *350 (LeafLogPort 10946 10432 port (LogicalPort 10947 10433 m 1 … … 10949 10435 n "D2_SRCLK" 10950 10436 t "STD_LOGIC" 10951 o 1910437 o 20 10952 10438 suid 89,0 10953 10439 ) … … 10955 10441 uid 3472,0 10956 10442 ) 10957 *3 70(LeafLogPort10443 *351 (LeafLogPort 10958 10444 port (LogicalPort 10959 10445 m 1 … … 10961 10447 n "D3_SRCLK" 10962 10448 t "STD_LOGIC" 10963 o 2 010449 o 21 10964 10450 suid 90,0 10965 10451 ) … … 10967 10453 uid 3474,0 10968 10454 ) 10969 *3 71(LeafLogPort10455 *352 (LeafLogPort 10970 10456 port (LogicalPort 10971 10457 decl (Decl … … 10978 10464 uid 3524,0 10979 10465 ) 10980 *3 72(LeafLogPort10466 *353 (LeafLogPort 10981 10467 port (LogicalPort 10982 10468 decl (Decl … … 10989 10475 uid 3526,0 10990 10476 ) 10991 *3 73(LeafLogPort10477 *354 (LeafLogPort 10992 10478 port (LogicalPort 10993 10479 decl (Decl … … 11000 10486 uid 3528,0 11001 10487 ) 11002 *3 74(LeafLogPort10488 *355 (LeafLogPort 11003 10489 port (LogicalPort 11004 10490 decl (Decl … … 11011 10497 uid 3530,0 11012 10498 ) 11013 *3 75(LeafLogPort10499 *356 (LeafLogPort 11014 10500 port (LogicalPort 11015 10501 m 1 … … 11018 10504 t "std_logic_vector" 11019 10505 b "(3 DOWNTO 0)" 11020 o 2 410506 o 25 11021 10507 suid 95,0 11022 10508 i "(others => '0')" … … 11025 10511 uid 3532,0 11026 10512 ) 11027 *3 76(LeafLogPort10513 *357 (LeafLogPort 11028 10514 port (LogicalPort 11029 10515 m 1 … … 11031 10517 n "DWRITE" 11032 10518 t "std_logic" 11033 o 2 310519 o 24 11034 10520 suid 96,0 11035 10521 i "'0'" … … 11038 10524 uid 3534,0 11039 10525 ) 11040 *3 77(LeafLogPort10526 *358 (LeafLogPort 11041 10527 port (LogicalPort 11042 10528 m 1 … … 11044 10530 n "T0_CS" 11045 10531 t "std_logic" 11046 o 3 810532 o 39 11047 10533 suid 101,0 11048 10534 ) … … 11050 10536 uid 3646,0 11051 10537 ) 11052 *3 78(LeafLogPort10538 *359 (LeafLogPort 11053 10539 port (LogicalPort 11054 10540 m 1 … … 11056 10542 n "T1_CS" 11057 10543 t "std_logic" 11058 o 3910544 o 40 11059 10545 suid 102,0 11060 10546 ) … … 11062 10548 uid 3648,0 11063 10549 ) 11064 *3 79(LeafLogPort10550 *360 (LeafLogPort 11065 10551 port (LogicalPort 11066 10552 m 1 … … 11068 10554 n "T2_CS" 11069 10555 t "std_logic" 11070 o 4 010556 o 41 11071 10557 suid 103,0 11072 10558 ) … … 11074 10560 uid 3650,0 11075 10561 ) 11076 *3 80(LeafLogPort10562 *361 (LeafLogPort 11077 10563 port (LogicalPort 11078 10564 m 1 … … 11080 10566 n "T3_CS" 11081 10567 t "std_logic" 11082 o 4 110568 o 42 11083 10569 suid 104,0 11084 10570 ) … … 11086 10572 uid 3652,0 11087 10573 ) 11088 *3 81(LeafLogPort10574 *362 (LeafLogPort 11089 10575 port (LogicalPort 11090 10576 m 1 … … 11092 10578 n "S_CLK" 11093 10579 t "std_logic" 11094 o 3 710580 o 38 11095 10581 suid 105,0 11096 10582 ) … … 11098 10584 uid 3654,0 11099 10585 ) 11100 *3 82(LeafLogPort10586 *363 (LeafLogPort 11101 10587 port (LogicalPort 11102 10588 m 1 … … 11105 10591 t "std_logic_vector" 11106 10592 b "(9 DOWNTO 0)" 11107 o 4 310593 o 44 11108 10594 suid 106,0 11109 10595 ) … … 11111 10597 uid 3656,0 11112 10598 ) 11113 *3 83(LeafLogPort10599 *364 (LeafLogPort 11114 10600 port (LogicalPort 11115 10601 m 2 … … 11118 10604 t "std_logic_vector" 11119 10605 b "(15 DOWNTO 0)" 11120 o 4910606 o 50 11121 10607 suid 107,0 11122 10608 ) … … 11124 10610 uid 3658,0 11125 10611 ) 11126 *3 84(LeafLogPort10612 *365 (LeafLogPort 11127 10613 port (LogicalPort 11128 10614 m 1 … … 11130 10616 n "W_RES" 11131 10617 t "std_logic" 11132 o 4 610618 o 47 11133 10619 suid 108,0 11134 10620 i "'1'" … … 11137 10623 uid 3660,0 11138 10624 ) 11139 *3 85(LeafLogPort10625 *366 (LeafLogPort 11140 10626 port (LogicalPort 11141 10627 m 1 … … 11143 10629 n "W_RD" 11144 10630 t "std_logic" 11145 o 4 510631 o 46 11146 10632 suid 109,0 11147 10633 i "'1'" … … 11150 10636 uid 3662,0 11151 10637 ) 11152 *3 86(LeafLogPort10638 *367 (LeafLogPort 11153 10639 port (LogicalPort 11154 10640 m 1 … … 11156 10642 n "W_WR" 11157 10643 t "std_logic" 11158 o 4 710644 o 48 11159 10645 suid 110,0 11160 10646 i "'1'" … … 11163 10649 uid 3664,0 11164 10650 ) 11165 *3 87(LeafLogPort10651 *368 (LeafLogPort 11166 10652 port (LogicalPort 11167 10653 decl (Decl … … 11174 10660 uid 3666,0 11175 10661 ) 11176 *3 88(LeafLogPort10662 *369 (LeafLogPort 11177 10663 port (LogicalPort 11178 10664 m 1 … … 11180 10666 n "W_CS" 11181 10667 t "std_logic" 11182 o 4 410668 o 45 11183 10669 suid 112,0 11184 10670 i "'1'" … … 11187 10673 uid 3668,0 11188 10674 ) 11189 *3 89(LeafLogPort10675 *370 (LeafLogPort 11190 10676 port (LogicalPort 11191 10677 m 1 … … 11193 10679 n "MOSI" 11194 10680 t "std_logic" 11195 o 2910681 o 30 11196 10682 suid 113,0 11197 10683 i "'0'" … … 11200 10686 uid 3696,0 11201 10687 ) 11202 *3 90(LeafLogPort10688 *371 (LeafLogPort 11203 10689 port (LogicalPort 11204 10690 m 2 … … 11208 10694 preAdd 0 11209 10695 posAdd 0 11210 o 4 810696 o 49 11211 10697 suid 114,0 11212 10698 ) … … 11214 10700 uid 3698,0 11215 10701 ) 11216 *3 91(LeafLogPort10702 *372 (LeafLogPort 11217 10703 port (LogicalPort 11218 10704 m 1 … … 11220 10706 n "TRG_V" 11221 10707 t "std_logic" 11222 o 4 210708 o 43 11223 10709 suid 126,0 11224 10710 ) … … 11226 10712 uid 3886,0 11227 10713 ) 11228 *3 92(LeafLogPort10714 *373 (LeafLogPort 11229 10715 port (LogicalPort 11230 10716 m 1 … … 11232 10718 n "RS485_C_RE" 11233 10719 t "std_logic" 11234 o 3 210720 o 33 11235 10721 suid 127,0 11236 10722 ) … … 11238 10724 uid 3888,0 11239 10725 ) 11240 *3 93(LeafLogPort10726 *374 (LeafLogPort 11241 10727 port (LogicalPort 11242 10728 m 1 … … 11244 10730 n "RS485_C_DE" 11245 10731 t "std_logic" 11246 o 3 110732 o 32 11247 10733 suid 128,0 11248 10734 ) … … 11250 10736 uid 3890,0 11251 10737 ) 11252 *3 94(LeafLogPort10738 *375 (LeafLogPort 11253 10739 port (LogicalPort 11254 10740 m 1 … … 11256 10742 n "RS485_E_RE" 11257 10743 t "std_logic" 11258 o 3 410744 o 35 11259 10745 suid 129,0 11260 10746 ) … … 11262 10748 uid 3892,0 11263 10749 ) 11264 *3 95(LeafLogPort10750 *376 (LeafLogPort 11265 10751 port (LogicalPort 11266 10752 m 1 … … 11268 10754 n "RS485_E_DE" 11269 10755 t "std_logic" 11270 o 3 310756 o 34 11271 10757 suid 130,0 11272 10758 ) … … 11274 10760 uid 3894,0 11275 10761 ) 11276 *3 96(LeafLogPort10762 *377 (LeafLogPort 11277 10763 port (LogicalPort 11278 10764 m 1 … … 11280 10766 n "DENABLE" 11281 10767 t "std_logic" 11282 o 2 210768 o 23 11283 10769 suid 131,0 11284 10770 i "'0'" … … 11287 10773 uid 3896,0 11288 10774 ) 11289 *3 97(LeafLogPort10775 *378 (LeafLogPort 11290 10776 port (LogicalPort 11291 10777 m 1 … … 11293 10779 n "SRIN" 11294 10780 t "std_logic" 11295 o 3 610781 o 37 11296 10782 suid 132,0 11297 10783 ) … … 11299 10785 uid 3898,0 11300 10786 ) 11301 *3 98(LeafLogPort10787 *379 (LeafLogPort 11302 10788 port (LogicalPort 11303 10789 m 1 … … 11305 10791 n "EE_CS" 11306 10792 t "std_logic" 11307 o 2 710793 o 28 11308 10794 suid 133,0 11309 10795 ) … … 11311 10797 uid 3900,0 11312 10798 ) 11313 *3 99(LeafLogPort10799 *380 (LeafLogPort 11314 10800 port (LogicalPort 11315 10801 m 1 … … 11318 10804 t "std_logic_vector" 11319 10805 b "( 2 DOWNTO 0 )" 11320 o 2 810806 o 29 11321 10807 suid 134,0 11322 10808 i "(others => '1')" … … 11325 10811 uid 3902,0 11326 10812 ) 11327 * 400(LeafLogPort10813 *381 (LeafLogPort 11328 10814 port (LogicalPort 11329 10815 m 1 … … 11332 10818 t "std_logic_vector" 11333 10819 b "(7 DOWNTO 0)" 11334 o 2 510820 o 26 11335 10821 suid 141,0 11336 10822 i "(OTHERS => '0')" … … 11339 10825 uid 5322,0 11340 10826 ) 11341 * 401(LeafLogPort10827 *382 (LeafLogPort 11342 10828 port (LogicalPort 11343 10829 decl (Decl … … 11351 10837 scheme 0 11352 10838 ) 11353 * 402(LeafLogPort10839 *383 (LeafLogPort 11354 10840 port (LogicalPort 11355 10841 m 4 … … 11357 10843 n "TRG_OR" 11358 10844 t "std_logic" 11359 o 5 310845 o 54 11360 10846 suid 146,0 11361 10847 ) … … 11364 10850 scheme 0 11365 10851 ) 11366 *403 (LeafLogPort 11367 port (LogicalPort 11368 m 4 11369 decl (Decl 11370 n "trigger_out" 11371 t "STD_LOGIC" 11372 preAdd 0 11373 posAdd 0 11374 o 60 11375 suid 147,0 11376 i "'0'" 11377 ) 11378 ) 11379 uid 6286,0 11380 ) 11381 *404 (LeafLogPort 11382 port (LogicalPort 11383 m 4 11384 decl (Decl 11385 n "not_TEST_TRG" 11386 t "STD_LOGIC" 11387 o 58 11388 suid 148,0 11389 ) 11390 ) 11391 uid 6314,0 11392 scheme 0 11393 ) 11394 *405 (LeafLogPort 10852 *384 (LeafLogPort 11395 10853 port (LogicalPort 11396 10854 decl (Decl … … 11405 10863 scheme 0 11406 10864 ) 11407 * 406(LeafLogPort10865 *385 (LeafLogPort 11408 10866 port (LogicalPort 11409 10867 m 1 … … 11412 10870 t "std_logic_vector" 11413 10871 b "(3 DOWNTO 0)" 11414 o 2 610872 o 27 11415 10873 suid 154,0 11416 10874 i "(others => '0')" … … 11420 10878 scheme 0 11421 10879 ) 11422 * 407(LeafLogPort10880 *386 (LeafLogPort 11423 10881 port (LogicalPort 11424 10882 m 1 … … 11426 10884 n "A1_T" 11427 10885 t "std_logic_vector" 11428 b "( 3DOWNTO 0)"11429 o 1 510886 b "(7 DOWNTO 0)" 10887 o 16 11430 10888 suid 155,0 10889 i "(OTHERS => '0')" 11431 10890 ) 11432 10891 ) … … 11434 10893 scheme 0 11435 10894 ) 11436 * 408(LeafLogPort10895 *387 (LeafLogPort 11437 10896 port (LogicalPort 11438 10897 m 4 … … 11440 10899 n "dummy" 11441 10900 t "std_logic" 11442 o 6010901 o 59 11443 10902 suid 157,0 11444 10903 ) … … 11446 10905 uid 7473,0 11447 10906 scheme 0 10907 ) 10908 *388 (LeafLogPort 10909 port (LogicalPort 10910 m 4 10911 decl (Decl 10912 n "drs_channel_id" 10913 t "std_logic_vector" 10914 b "(3 downto 0)" 10915 o 58 10916 suid 159,0 10917 i "(others => '0')" 10918 ) 10919 ) 10920 uid 8875,0 10921 ) 10922 *389 (LeafLogPort 10923 port (LogicalPort 10924 m 1 10925 decl (Decl 10926 n "A0_T" 10927 t "std_logic_vector" 10928 b "(7 DOWNTO 0)" 10929 o 15 10930 suid 162,0 10931 i "(OTHERS => '0')" 10932 ) 10933 ) 10934 uid 9191,0 10935 scheme 0 10936 ) 10937 *390 (LeafLogPort 10938 port (LogicalPort 10939 m 4 10940 decl (Decl 10941 n "CLK_50" 10942 t "std_logic" 10943 o 52 10944 suid 163,0 10945 ) 10946 ) 10947 uid 9516,0 11448 10948 ) 11449 10949 ] … … 11454 10954 uid 67,0 11455 10955 optionalChildren [ 11456 * 409(Sheet10956 *391 (Sheet 11457 10957 sheetRow (SheetRow 11458 10958 headerVa (MVa … … 11471 10971 font "Tahoma,10,0" 11472 10972 ) 11473 emptyMRCItem * 410(MRCItem11474 litem &3 3610973 emptyMRCItem *392 (MRCItem 10974 litem &318 11475 10975 pos 60 11476 10976 dimension 20 … … 11478 10978 uid 69,0 11479 10979 optionalChildren [ 11480 * 411(MRCItem11481 litem &3 3710980 *393 (MRCItem 10981 litem &319 11482 10982 pos 0 11483 10983 dimension 20 11484 10984 uid 70,0 11485 10985 ) 11486 * 412(MRCItem11487 litem &3 3810986 *394 (MRCItem 10987 litem &320 11488 10988 pos 1 11489 10989 dimension 23 11490 10990 uid 71,0 11491 10991 ) 11492 * 413(MRCItem11493 litem &3 3910992 *395 (MRCItem 10993 litem &321 11494 10994 pos 2 11495 10995 hidden 1 … … 11497 10997 uid 72,0 11498 10998 ) 11499 * 414(MRCItem11500 litem &3 4911501 pos 4410999 *396 (MRCItem 11000 litem &331 11001 pos 50 11502 11002 dimension 20 11503 11003 uid 328,0 11504 11004 ) 11505 * 415(MRCItem11506 litem &3 5011507 pos 4511005 *397 (MRCItem 11006 litem &332 11007 pos 51 11508 11008 dimension 20 11509 11009 uid 330,0 11510 11010 ) 11511 * 416(MRCItem11512 litem &3 5111513 pos 4611011 *398 (MRCItem 11012 litem &333 11013 pos 52 11514 11014 dimension 20 11515 11015 uid 1492,0 11516 11016 ) 11517 *417 (MRCItem 11518 litem &352 11519 pos 47 11520 dimension 20 11521 uid 2276,0 11522 ) 11523 *418 (MRCItem 11524 litem &353 11017 *399 (MRCItem 11018 litem &334 11525 11019 pos 0 11526 11020 dimension 20 11527 11021 uid 2436,0 11528 11022 ) 11529 *4 19(MRCItem11530 litem &3 5411531 pos 4811023 *400 (MRCItem 11024 litem &335 11025 pos 53 11532 11026 dimension 20 11533 11027 uid 2438,0 11534 11028 ) 11535 *4 20(MRCItem11536 litem &3 5511537 pos 4911029 *401 (MRCItem 11030 litem &336 11031 pos 54 11538 11032 dimension 20 11539 11033 uid 3038,0 11540 11034 ) 11541 *4 21(MRCItem11542 litem &3 5611035 *402 (MRCItem 11036 litem &337 11543 11037 pos 1 11544 11038 dimension 20 11545 11039 uid 3040,0 11546 11040 ) 11547 *4 22(MRCItem11548 litem &3 5711041 *403 (MRCItem 11042 litem &338 11549 11043 pos 2 11550 11044 dimension 20 11551 11045 uid 3277,0 11552 11046 ) 11553 *4 23(MRCItem11554 litem &3 5811047 *404 (MRCItem 11048 litem &339 11555 11049 pos 3 11556 11050 dimension 20 11557 11051 uid 3279,0 11558 11052 ) 11559 *4 24(MRCItem11560 litem &3 5911053 *405 (MRCItem 11054 litem &340 11561 11055 pos 4 11562 11056 dimension 20 11563 11057 uid 3281,0 11564 11058 ) 11565 *4 25(MRCItem11566 litem &3 6011567 pos 5 011059 *406 (MRCItem 11060 litem &341 11061 pos 55 11568 11062 dimension 20 11569 11063 uid 3283,0 11570 11064 ) 11571 *4 26(MRCItem11572 litem &3 6111065 *407 (MRCItem 11066 litem &342 11573 11067 pos 5 11574 11068 dimension 20 11575 11069 uid 3383,0 11576 11070 ) 11577 *4 27(MRCItem11578 litem &3 6211071 *408 (MRCItem 11072 litem &343 11579 11073 pos 6 11580 11074 dimension 20 11581 11075 uid 3385,0 11582 11076 ) 11583 *4 28(MRCItem11584 litem &3 6311077 *409 (MRCItem 11078 litem &344 11585 11079 pos 7 11586 11080 dimension 20 11587 11081 uid 3387,0 11588 11082 ) 11589 *4 29(MRCItem11590 litem &3 6411083 *410 (MRCItem 11084 litem &345 11591 11085 pos 8 11592 11086 dimension 20 11593 11087 uid 3389,0 11594 11088 ) 11595 *4 30(MRCItem11596 litem &3 6511089 *411 (MRCItem 11090 litem &346 11597 11091 pos 9 11598 11092 dimension 20 11599 11093 uid 3391,0 11600 11094 ) 11601 *4 31(MRCItem11602 litem &3 6611095 *412 (MRCItem 11096 litem &347 11603 11097 pos 10 11604 11098 dimension 20 11605 11099 uid 3393,0 11606 11100 ) 11607 *4 32(MRCItem11608 litem &3 6711101 *413 (MRCItem 11102 litem &348 11609 11103 pos 11 11610 11104 dimension 20 11611 11105 uid 3469,0 11612 11106 ) 11613 *4 33(MRCItem11614 litem &3 6811107 *414 (MRCItem 11108 litem &349 11615 11109 pos 12 11616 11110 dimension 20 11617 11111 uid 3471,0 11618 11112 ) 11619 *4 34(MRCItem11620 litem &3 6911113 *415 (MRCItem 11114 litem &350 11621 11115 pos 13 11622 11116 dimension 20 11623 11117 uid 3473,0 11624 11118 ) 11625 *4 35(MRCItem11626 litem &3 7011119 *416 (MRCItem 11120 litem &351 11627 11121 pos 14 11628 11122 dimension 20 11629 11123 uid 3475,0 11630 11124 ) 11631 *4 36(MRCItem11632 litem &3 7111125 *417 (MRCItem 11126 litem &352 11633 11127 pos 15 11634 11128 dimension 20 11635 11129 uid 3525,0 11636 11130 ) 11637 *4 37(MRCItem11638 litem &3 7211131 *418 (MRCItem 11132 litem &353 11639 11133 pos 16 11640 11134 dimension 20 11641 11135 uid 3527,0 11642 11136 ) 11643 *4 38(MRCItem11644 litem &3 7311137 *419 (MRCItem 11138 litem &354 11645 11139 pos 17 11646 11140 dimension 20 11647 11141 uid 3529,0 11648 11142 ) 11649 *4 39(MRCItem11650 litem &3 7411143 *420 (MRCItem 11144 litem &355 11651 11145 pos 18 11652 11146 dimension 20 11653 11147 uid 3531,0 11654 11148 ) 11655 *4 40(MRCItem11656 litem &3 7511149 *421 (MRCItem 11150 litem &356 11657 11151 pos 19 11658 11152 dimension 20 11659 11153 uid 3533,0 11660 11154 ) 11661 *4 41(MRCItem11662 litem &3 7611155 *422 (MRCItem 11156 litem &357 11663 11157 pos 20 11664 11158 dimension 20 11665 11159 uid 3535,0 11666 11160 ) 11667 *4 42(MRCItem11668 litem &3 7711161 *423 (MRCItem 11162 litem &358 11669 11163 pos 21 11670 11164 dimension 20 11671 11165 uid 3647,0 11672 11166 ) 11673 *4 43(MRCItem11674 litem &3 7811167 *424 (MRCItem 11168 litem &359 11675 11169 pos 22 11676 11170 dimension 20 11677 11171 uid 3649,0 11678 11172 ) 11679 *4 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pos 29 11718 11212 dimension 20 11719 11213 uid 3663,0 11720 11214 ) 11721 *4 51(MRCItem11722 litem &3 8611215 *432 (MRCItem 11216 litem &367 11723 11217 pos 30 11724 11218 dimension 20 11725 11219 uid 3665,0 11726 11220 ) 11727 *4 52(MRCItem11728 litem &3 8711221 *433 (MRCItem 11222 litem &368 11729 11223 pos 31 11730 11224 dimension 20 11731 11225 uid 3667,0 11732 11226 ) 11733 *4 53(MRCItem11734 litem &3 8811227 *434 (MRCItem 11228 litem &369 11735 11229 pos 32 11736 11230 dimension 20 11737 11231 uid 3669,0 11738 11232 ) 11739 *4 54(MRCItem11740 litem &3 8911233 *435 (MRCItem 11234 litem &370 11741 11235 pos 33 11742 11236 dimension 20 11743 11237 uid 3697,0 11744 11238 ) 11745 *4 55(MRCItem11746 litem &3 9011239 *436 (MRCItem 11240 litem &371 11747 11241 pos 34 11748 11242 dimension 20 11749 11243 uid 3699,0 11750 11244 ) 11751 *4 56(MRCItem11752 litem &3 9111245 *437 (MRCItem 11246 litem &372 11753 11247 pos 35 11754 11248 dimension 20 11755 11249 uid 3887,0 11756 11250 ) 11757 *4 57(MRCItem11758 litem &3 9211251 *438 (MRCItem 11252 litem &373 11759 11253 pos 36 11760 11254 dimension 20 11761 11255 uid 3889,0 11762 11256 ) 11763 *4 58(MRCItem11764 litem &3 9311257 *439 (MRCItem 11258 litem &374 11765 11259 pos 37 11766 11260 dimension 20 11767 11261 uid 3891,0 11768 11262 ) 11769 *4 59(MRCItem11770 litem &3 9411263 *440 (MRCItem 11264 litem &375 11771 11265 pos 38 11772 11266 dimension 20 11773 11267 uid 3893,0 11774 11268 ) 11775 *4 60(MRCItem11776 litem &3 9511269 *441 (MRCItem 11270 litem &376 11777 11271 pos 39 11778 11272 dimension 20 11779 11273 uid 3895,0 11780 11274 ) 11781 *4 61(MRCItem11782 litem &3 9611275 *442 (MRCItem 11276 litem &377 11783 11277 pos 40 11784 11278 dimension 20 11785 11279 uid 3897,0 11786 11280 ) 11787 *4 62(MRCItem11788 litem &3 9711281 *443 (MRCItem 11282 litem &378 11789 11283 pos 41 11790 11284 dimension 20 11791 11285 uid 3899,0 11792 11286 ) 11793 *4 63(MRCItem11794 litem &3 9811287 *444 (MRCItem 11288 litem &379 11795 11289 pos 42 11796 11290 dimension 20 11797 11291 uid 3901,0 11798 11292 ) 11799 *4 64(MRCItem11800 litem &3 9911293 *445 (MRCItem 11294 litem &380 11801 11295 pos 43 11802 11296 dimension 20 11803 11297 uid 3903,0 11804 11298 ) 11805 *4 65(MRCItem11806 litem & 40011807 pos 5111299 *446 (MRCItem 11300 litem &381 11301 pos 44 11808 11302 dimension 20 11809 11303 uid 5323,0 11810 11304 ) 11811 *4 66(MRCItem11812 litem & 40111813 pos 5211305 *447 (MRCItem 11306 litem &382 11307 pos 45 11814 11308 dimension 20 11815 11309 uid 5649,0 11816 11310 ) 11817 *4 67(MRCItem11818 litem & 40211819 pos 5 311311 *448 (MRCItem 11312 litem &383 11313 pos 56 11820 11314 dimension 20 11821 11315 uid 6129,0 11822 11316 ) 11823 *468 (MRCItem 11824 litem &403 11825 pos 54 11826 dimension 20 11827 uid 6287,0 11828 ) 11829 *469 (MRCItem 11830 litem &404 11831 pos 55 11832 dimension 20 11833 uid 6315,0 11834 ) 11835 *470 (MRCItem 11836 litem &405 11837 pos 56 11317 *449 (MRCItem 11318 litem &384 11319 pos 46 11838 11320 dimension 20 11839 11321 uid 6778,0 11840 11322 ) 11841 *471 (MRCItem 11842 litem &406 11323 *450 (MRCItem 11324 litem &385 11325 pos 47 11326 dimension 20 11327 uid 6873,0 11328 ) 11329 *451 (MRCItem 11330 litem &386 11331 pos 48 11332 dimension 20 11333 uid 7135,0 11334 ) 11335 *452 (MRCItem 11336 litem &387 11843 11337 pos 57 11844 11338 dimension 20 11845 uid 6873,011846 ) 11847 *4 72(MRCItem11848 litem & 40711339 uid 7474,0 11340 ) 11341 *453 (MRCItem 11342 litem &388 11849 11343 pos 58 11850 11344 dimension 20 11851 uid 7135,0 11852 ) 11853 *473 (MRCItem 11854 litem &408 11345 uid 8876,0 11346 ) 11347 *454 (MRCItem 11348 litem &389 11349 pos 49 11350 dimension 20 11351 uid 9192,0 11352 ) 11353 *455 (MRCItem 11354 litem &390 11855 11355 pos 59 11856 11356 dimension 20 11857 uid 7474,011357 uid 9517,0 11858 11358 ) 11859 11359 ] … … 11868 11368 uid 73,0 11869 11369 optionalChildren [ 11870 *4 74(MRCItem11871 litem &3 4011370 *456 (MRCItem 11371 litem &322 11872 11372 pos 0 11873 11373 dimension 20 11874 11374 uid 74,0 11875 11375 ) 11876 *4 75(MRCItem11877 litem &3 4211376 *457 (MRCItem 11377 litem &324 11878 11378 pos 1 11879 11379 dimension 50 11880 11380 uid 75,0 11881 11381 ) 11882 *4 76(MRCItem11883 litem &3 4311382 *458 (MRCItem 11383 litem &325 11884 11384 pos 2 11885 11385 dimension 100 11886 11386 uid 76,0 11887 11387 ) 11888 *4 77(MRCItem11889 litem &3 4411388 *459 (MRCItem 11389 litem &326 11890 11390 pos 3 11891 11391 dimension 50 11892 11392 uid 77,0 11893 11393 ) 11894 *4 78(MRCItem11895 litem &3 4511394 *460 (MRCItem 11395 litem &327 11896 11396 pos 4 11897 11397 dimension 100 11898 11398 uid 78,0 11899 11399 ) 11900 *4 79(MRCItem11901 litem &3 4611400 *461 (MRCItem 11401 litem &328 11902 11402 pos 5 11903 11403 dimension 100 11904 11404 uid 79,0 11905 11405 ) 11906 *4 80(MRCItem11907 litem &3 4711406 *462 (MRCItem 11407 litem &329 11908 11408 pos 6 11909 11409 dimension 92 11910 11410 uid 80,0 11911 11411 ) 11912 *4 81(MRCItem11913 litem &3 4811412 *463 (MRCItem 11413 litem &330 11914 11414 pos 7 11915 11415 dimension 80 … … 11931 11431 genericsCommonDM (CommonDM 11932 11432 ldm (LogicalDM 11933 emptyRow *4 82(LEmptyRow11433 emptyRow *464 (LEmptyRow 11934 11434 ) 11935 11435 uid 83,0 11936 11436 optionalChildren [ 11937 *4 83(RefLabelRowHdr11938 ) 11939 *4 84(TitleRowHdr11940 ) 11941 *4 85(FilterRowHdr11942 ) 11943 *4 86(RefLabelColHdr11437 *465 (RefLabelRowHdr 11438 ) 11439 *466 (TitleRowHdr 11440 ) 11441 *467 (FilterRowHdr 11442 ) 11443 *468 (RefLabelColHdr 11944 11444 tm "RefLabelColHdrMgr" 11945 11445 ) 11946 *4 87(RowExpandColHdr11446 *469 (RowExpandColHdr 11947 11447 tm "RowExpandColHdrMgr" 11948 11448 ) 11949 *4 88(GroupColHdr11449 *470 (GroupColHdr 11950 11450 tm "GroupColHdrMgr" 11951 11451 ) 11952 *4 89(NameColHdr11452 *471 (NameColHdr 11953 11453 tm "GenericNameColHdrMgr" 11954 11454 ) 11955 *4 90(TypeColHdr11455 *472 (TypeColHdr 11956 11456 tm "GenericTypeColHdrMgr" 11957 11457 ) 11958 *4 91(InitColHdr11458 *473 (InitColHdr 11959 11459 tm "GenericValueColHdrMgr" 11960 11460 ) 11961 *4 92(PragmaColHdr11461 *474 (PragmaColHdr 11962 11462 tm "GenericPragmaColHdrMgr" 11963 11463 ) 11964 *4 93(EolColHdr11464 *475 (EolColHdr 11965 11465 tm "GenericEolColHdrMgr" 11966 11466 ) … … 11972 11472 uid 95,0 11973 11473 optionalChildren [ 11974 *4 94(Sheet11474 *476 (Sheet 11975 11475 sheetRow (SheetRow 11976 11476 headerVa (MVa … … 11989 11489 font "Tahoma,10,0" 11990 11490 ) 11991 emptyMRCItem *4 95(MRCItem11992 litem &4 8211491 emptyMRCItem *477 (MRCItem 11492 litem &464 11993 11493 pos 0 11994 11494 dimension 20 … … 11996 11496 uid 97,0 11997 11497 optionalChildren [ 11998 *4 96(MRCItem11999 litem &4 8311498 *478 (MRCItem 11499 litem &465 12000 11500 pos 0 12001 11501 dimension 20 12002 11502 uid 98,0 12003 11503 ) 12004 *4 97(MRCItem12005 litem &4 8411504 *479 (MRCItem 11505 litem &466 12006 11506 pos 1 12007 11507 dimension 23 12008 11508 uid 99,0 12009 11509 ) 12010 *4 98(MRCItem12011 litem &4 8511510 *480 (MRCItem 11511 litem &467 12012 11512 pos 2 12013 11513 hidden 1 … … 12026 11526 uid 101,0 12027 11527 optionalChildren [ 12028 *4 99(MRCItem12029 litem &4 8611528 *481 (MRCItem 11529 litem &468 12030 11530 pos 0 12031 11531 dimension 20 12032 11532 uid 102,0 12033 11533 ) 12034 * 500(MRCItem12035 litem &4 8811534 *482 (MRCItem 11535 litem &470 12036 11536 pos 1 12037 11537 dimension 50 12038 11538 uid 103,0 12039 11539 ) 12040 * 501(MRCItem12041 litem &4 8911540 *483 (MRCItem 11541 litem &471 12042 11542 pos 2 12043 11543 dimension 100 12044 11544 uid 104,0 12045 11545 ) 12046 * 502(MRCItem12047 litem &4 9011546 *484 (MRCItem 11547 litem &472 12048 11548 pos 3 12049 11549 dimension 100 12050 11550 uid 105,0 12051 11551 ) 12052 * 503(MRCItem12053 litem &4 9111552 *485 (MRCItem 11553 litem &473 12054 11554 pos 4 12055 11555 dimension 50 12056 11556 uid 106,0 12057 11557 ) 12058 * 504(MRCItem12059 litem &4 9211558 *486 (MRCItem 11559 litem &474 12060 11560 pos 5 12061 11561 dimension 50 12062 11562 uid 107,0 12063 11563 ) 12064 * 505(MRCItem12065 litem &4 9311564 *487 (MRCItem 11565 litem &475 12066 11566 pos 6 12067 11567 dimension 80 -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb
r246 r252 21 21 commonDM (CommonDM 22 22 ldm (LogicalDM 23 suid 6 6,023 suid 67,0 24 24 usingSuid 1 25 25 emptyRow *1 (LEmptyRow … … 659 659 n "A1_T" 660 660 t "std_logic_vector" 661 b "( 3DOWNTO 0)"661 b "(7 DOWNTO 0)" 662 662 o 15 663 663 suid 66,0 664 i "(OTHERS => '0')" 664 665 ) 665 666 ) … … 1239 1240 (vvPair 1240 1241 variable "HDLDir" 1241 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hdl"1242 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" 1242 1243 ) 1243 1244 (vvPair 1244 1245 variable "HDSDir" 1245 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hds"1246 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 1246 1247 ) 1247 1248 (vvPair 1248 1249 variable "SideDataDesignDir" 1249 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info"1250 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info" 1250 1251 ) 1251 1252 (vvPair 1252 1253 variable "SideDataUserDir" 1253 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user"1254 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user" 1254 1255 ) 1255 1256 (vvPair 1256 1257 variable "SourceDir" 1257 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hds"1258 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 1258 1259 ) 1259 1260 (vvPair … … 1271 1272 (vvPair 1272 1273 variable "d" 1273 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board"1274 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board" 1274 1275 ) 1275 1276 (vvPair 1276 1277 variable "d_logical" 1277 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hds\\FAD_Board"1278 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board" 1278 1279 ) 1279 1280 (vvPair 1280 1281 variable "date" 1281 value "1 6.06.2010"1282 value "14.07.2010" 1282 1283 ) 1283 1284 (vvPair … … 1291 1292 (vvPair 1292 1293 variable "dd" 1293 value "1 6"1294 value "14" 1294 1295 ) 1295 1296 (vvPair … … 1319 1320 (vvPair 1320 1321 variable "host" 1321 value " TU-CC4900F8C7D2"1322 value "E5B-LABOR6" 1322 1323 ) 1323 1324 (vvPair … … 1330 1331 ) 1331 1332 (vvPair 1333 variable "library_downstream_HdsLintPlugin" 1334 value "$HDS_PROJECT_DIR\\FACT_FAD_lib\\designcheck" 1335 ) 1336 (vvPair 1332 1337 variable "library_downstream_ISEPARInvoke" 1333 1338 value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" … … 1347 1352 (vvPair 1348 1353 variable "mm" 1349 value "0 6"1354 value "07" 1350 1355 ) 1351 1356 (vvPair … … 1355 1360 (vvPair 1356 1361 variable "month" 1357 value "Ju n"1362 value "Jul" 1358 1363 ) 1359 1364 (vvPair 1360 1365 variable "month_long" 1361 value "Ju ni"1366 value "Juli" 1362 1367 ) 1363 1368 (vvPair 1364 1369 variable "p" 1365 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb"1370 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb" 1366 1371 ) 1367 1372 (vvPair 1368 1373 variable "p_logical" 1369 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb"1374 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb" 1370 1375 ) 1371 1376 (vvPair … … 1423 1428 (vvPair 1424 1429 variable "time" 1425 value "15: 30:04"1430 value "15:25:08" 1426 1431 ) 1427 1432 (vvPair … … 1500 1505 ) 1501 1506 xt "44000,29200,76000,30000" 1502 st "RSRLOAD : OUT std_logic := '0' ;" 1507 st "RSRLOAD : OUT std_logic := '0' ; 1508 " 1503 1509 ) 1504 1510 thePort (LogicalPort … … 1545 1551 ) 1546 1552 xt "44000,12400,61500,13200" 1547 st "X_50M : IN STD_LOGIC ;" 1553 st "X_50M : IN STD_LOGIC ; 1554 " 1548 1555 ) 1549 1556 thePort (LogicalPort … … 1590 1597 ) 1591 1598 xt "44000,10800,61500,11600" 1592 st "TRG : IN STD_LOGIC ;" 1599 st "TRG : IN STD_LOGIC ; 1600 " 1593 1601 ) 1594 1602 thePort (LogicalPort … … 1634 1642 ) 1635 1643 xt "44000,14000,71500,14800" 1636 st "A_CLK : OUT std_logic_vector (3 downto 0) ;" 1644 st "A_CLK : OUT std_logic_vector (3 downto 0) ; 1645 " 1637 1646 ) 1638 1647 thePort (LogicalPort … … 1680 1689 ) 1681 1690 xt "44000,25200,61500,26000" 1682 st "OE_ADC : OUT STD_LOGIC ;" 1691 st "OE_ADC : OUT STD_LOGIC ; 1692 " 1683 1693 ) 1684 1694 thePort (LogicalPort … … 1726 1736 ) 1727 1737 xt "44000,5200,71500,6000" 1728 st "A_OTR : IN std_logic_vector (3 DOWNTO 0) ;" 1738 st "A_OTR : IN std_logic_vector (3 DOWNTO 0) ; 1739 " 1729 1740 ) 1730 1741 thePort (LogicalPort … … 1770 1781 ) 1771 1782 xt "44000,2000,72000,2800" 1772 st "A0_D : IN std_logic_vector (11 DOWNTO 0) ;" 1783 st "A0_D : IN std_logic_vector (11 DOWNTO 0) ; 1784 " 1773 1785 ) 1774 1786 thePort (LogicalPort … … 1814 1826 ) 1815 1827 xt "44000,2800,72000,3600" 1816 st "A1_D : IN std_logic_vector (11 DOWNTO 0) ;" 1828 st "A1_D : IN std_logic_vector (11 DOWNTO 0) ; 1829 " 1817 1830 ) 1818 1831 thePort (LogicalPort … … 1858 1871 ) 1859 1872 xt "44000,3600,72000,4400" 1860 st "A2_D : IN std_logic_vector (11 DOWNTO 0) ;" 1873 st "A2_D : IN std_logic_vector (11 DOWNTO 0) ; 1874 " 1861 1875 ) 1862 1876 thePort (LogicalPort … … 1902 1916 ) 1903 1917 xt "44000,4400,72000,5200" 1904 st "A3_D : IN std_logic_vector (11 DOWNTO 0) ;" 1918 st "A3_D : IN std_logic_vector (11 DOWNTO 0) ; 1919 " 1905 1920 ) 1906 1921 thePort (LogicalPort … … 1947 1962 ) 1948 1963 xt "44000,14800,61500,15600" 1949 st "D0_SRCLK : OUT STD_LOGIC ;" 1964 st "D0_SRCLK : OUT STD_LOGIC ; 1965 " 1950 1966 ) 1951 1967 thePort (LogicalPort … … 1992 2008 ) 1993 2009 xt "44000,15600,61500,16400" 1994 st "D1_SRCLK : OUT STD_LOGIC ;" 2010 st "D1_SRCLK : OUT STD_LOGIC ; 2011 " 1995 2012 ) 1996 2013 thePort (LogicalPort … … 2037 2054 ) 2038 2055 xt "44000,16400,61500,17200" 2039 st "D2_SRCLK : OUT STD_LOGIC ;" 2056 st "D2_SRCLK : OUT STD_LOGIC ; 2057 " 2040 2058 ) 2041 2059 thePort (LogicalPort … … 2082 2100 ) 2083 2101 xt "44000,17200,61500,18000" 2084 st "D3_SRCLK : OUT STD_LOGIC ;" 2102 st "D3_SRCLK : OUT STD_LOGIC ; 2103 " 2085 2104 ) 2086 2105 thePort (LogicalPort … … 2126 2145 ) 2127 2146 xt "44000,6000,61500,6800" 2128 st "D0_SROUT : IN std_logic ;" 2147 st "D0_SROUT : IN std_logic ; 2148 " 2129 2149 ) 2130 2150 thePort (LogicalPort … … 2169 2189 ) 2170 2190 xt "44000,6800,61500,7600" 2171 st "D1_SROUT : IN std_logic ;" 2191 st "D1_SROUT : IN std_logic ; 2192 " 2172 2193 ) 2173 2194 thePort (LogicalPort … … 2212 2233 ) 2213 2234 xt "44000,7600,61500,8400" 2214 st "D2_SROUT : IN std_logic ;" 2235 st "D2_SROUT : IN std_logic ; 2236 " 2215 2237 ) 2216 2238 thePort (LogicalPort … … 2255 2277 ) 2256 2278 xt "44000,8400,61500,9200" 2257 st "D3_SROUT : IN std_logic ;" 2279 st "D3_SROUT : IN std_logic ; 2280 " 2258 2281 ) 2259 2282 thePort (LogicalPort … … 2309 2332 ) 2310 2333 xt "44000,20400,82000,21200" 2311 st "D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ;" 2334 st "D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ; 2335 " 2312 2336 ) 2313 2337 thePort (LogicalPort … … 2366 2390 ) 2367 2391 xt "44000,19600,76000,20400" 2368 st "DWRITE : OUT std_logic := '0' ;" 2392 st "DWRITE : OUT std_logic := '0' ; 2393 " 2369 2394 ) 2370 2395 thePort (LogicalPort … … 2412 2437 ) 2413 2438 xt "44000,18000,61500,18800" 2414 st "DAC_CS : OUT std_logic ;" 2439 st "DAC_CS : OUT std_logic ; 2440 " 2415 2441 ) 2416 2442 thePort (LogicalPort … … 2457 2483 ) 2458 2484 xt "44000,31600,61500,32400" 2459 st "T0_CS : OUT std_logic ;" 2485 st "T0_CS : OUT std_logic ; 2486 " 2460 2487 ) 2461 2488 thePort (LogicalPort … … 2502 2529 ) 2503 2530 xt "44000,32400,61500,33200" 2504 st "T1_CS : OUT std_logic ;" 2531 st "T1_CS : OUT std_logic ; 2532 " 2505 2533 ) 2506 2534 thePort (LogicalPort … … 2547 2575 ) 2548 2576 xt "44000,33200,61500,34000" 2549 st "T2_CS : OUT std_logic ;" 2577 st "T2_CS : OUT std_logic ; 2578 " 2550 2579 ) 2551 2580 thePort (LogicalPort … … 2592 2621 ) 2593 2622 xt "44000,34000,61500,34800" 2594 st "T3_CS : OUT std_logic ;" 2623 st "T3_CS : OUT std_logic ; 2624 " 2595 2625 ) 2596 2626 thePort (LogicalPort … … 2637 2667 ) 2638 2668 xt "44000,30800,61500,31600" 2639 st "S_CLK : OUT std_logic ;" 2669 st "S_CLK : OUT std_logic ; 2670 " 2640 2671 ) 2641 2672 thePort (LogicalPort … … 2682 2713 ) 2683 2714 xt "44000,35600,71500,36400" 2684 st "W_A : OUT std_logic_vector (9 DOWNTO 0) ;" 2715 st "W_A : OUT std_logic_vector (9 DOWNTO 0) ; 2716 " 2685 2717 ) 2686 2718 thePort (LogicalPort … … 2728 2760 ) 2729 2761 xt "44000,40400,71000,41200" 2730 st "W_D : INOUT std_logic_vector (15 DOWNTO 0)" 2762 st "W_D : INOUT std_logic_vector (15 DOWNTO 0) 2763 " 2731 2764 ) 2732 2765 thePort (LogicalPort … … 2784 2817 ) 2785 2818 xt "44000,38000,76000,38800" 2786 st "W_RES : OUT std_logic := '1' ;" 2819 st "W_RES : OUT std_logic := '1' ; 2820 " 2787 2821 ) 2788 2822 thePort (LogicalPort … … 2840 2874 ) 2841 2875 xt "44000,37200,76000,38000" 2842 st "W_RD : OUT std_logic := '1' ;" 2876 st "W_RD : OUT std_logic := '1' ; 2877 " 2843 2878 ) 2844 2879 thePort (LogicalPort … … 2896 2931 ) 2897 2932 xt "44000,38800,76000,39600" 2898 st "W_WR : OUT std_logic := '1' ;" 2933 st "W_WR : OUT std_logic := '1' ; 2934 " 2899 2935 ) 2900 2936 thePort (LogicalPort … … 2941 2977 ) 2942 2978 xt "44000,11600,61500,12400" 2943 st "W_INT : IN std_logic ;" 2979 st "W_INT : IN std_logic ; 2980 " 2944 2981 ) 2945 2982 thePort (LogicalPort … … 2995 3032 ) 2996 3033 xt "44000,36400,76000,37200" 2997 st "W_CS : OUT std_logic := '1' ;" 3034 st "W_CS : OUT std_logic := '1' ; 3035 " 2998 3036 ) 2999 3037 thePort (LogicalPort … … 3051 3089 ) 3052 3090 xt "44000,24400,76000,25200" 3053 st "MOSI : OUT std_logic := '0' ;" 3091 st "MOSI : OUT std_logic := '0' ; 3092 " 3054 3093 ) 3055 3094 thePort (LogicalPort … … 3097 3136 ) 3098 3137 xt "44000,39600,61500,40400" 3099 st "MISO : INOUT std_logic ;" 3138 st "MISO : INOUT std_logic ; 3139 " 3100 3140 ) 3101 3141 thePort (LogicalPort … … 3144 3184 ) 3145 3185 xt "44000,34800,61500,35600" 3146 st "TRG_V : OUT std_logic ;" 3186 st "TRG_V : OUT std_logic ; 3187 " 3147 3188 ) 3148 3189 thePort (LogicalPort … … 3189 3230 ) 3190 3231 xt "44000,26800,61500,27600" 3191 st "RS485_C_RE : OUT std_logic ;" 3232 st "RS485_C_RE : OUT std_logic ; 3233 " 3192 3234 ) 3193 3235 thePort (LogicalPort … … 3234 3276 ) 3235 3277 xt "44000,26000,61500,26800" 3236 st "RS485_C_DE : OUT std_logic ;" 3278 st "RS485_C_DE : OUT std_logic ; 3279 " 3237 3280 ) 3238 3281 thePort (LogicalPort … … 3279 3322 ) 3280 3323 xt "44000,28400,61500,29200" 3281 st "RS485_E_RE : OUT std_logic ;" 3324 st "RS485_E_RE : OUT std_logic ; 3325 " 3282 3326 ) 3283 3327 thePort (LogicalPort … … 3324 3368 ) 3325 3369 xt "44000,27600,61500,28400" 3326 st "RS485_E_DE : OUT std_logic ;" 3370 st "RS485_E_DE : OUT std_logic ; 3371 " 3327 3372 ) 3328 3373 thePort (LogicalPort … … 3379 3424 ) 3380 3425 xt "44000,18800,76000,19600" 3381 st "DENABLE : OUT std_logic := '0' ;" 3426 st "DENABLE : OUT std_logic := '0' ; 3427 " 3382 3428 ) 3383 3429 thePort (LogicalPort … … 3425 3471 ) 3426 3472 xt "44000,30000,61500,30800" 3427 st "SRIN : OUT std_logic ;" 3473 st "SRIN : OUT std_logic ; 3474 " 3428 3475 ) 3429 3476 thePort (LogicalPort … … 3470 3517 ) 3471 3518 xt "44000,22800,61500,23600" 3472 st "EE_CS : OUT std_logic ;" 3519 st "EE_CS : OUT std_logic ; 3520 " 3473 3521 ) 3474 3522 thePort (LogicalPort … … 3525 3573 ) 3526 3574 xt "44000,21200,82000,22000" 3527 st "D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ;" 3575 st "D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ; 3576 " 3528 3577 ) 3529 3578 thePort (LogicalPort … … 3582 3631 ) 3583 3632 xt "44000,23600,82000,24400" 3584 st "LED : OUT std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ;" 3633 st "LED : OUT std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ; 3634 " 3585 3635 ) 3586 3636 thePort (LogicalPort … … 3628 3678 ) 3629 3679 xt "44000,10000,61500,10800" 3630 st "TEST_TRG : IN std_logic ;" 3680 st "TEST_TRG : IN std_logic ; 3681 " 3631 3682 ) 3632 3683 thePort (LogicalPort … … 3671 3722 ) 3672 3723 xt "44000,9200,71500,10000" 3673 st "D_PLLLCK : IN std_logic_vector (3 DOWNTO 0) ;" 3724 st "D_PLLLCK : IN std_logic_vector (3 DOWNTO 0) ; 3725 " 3674 3726 ) 3675 3727 thePort (LogicalPort … … 3726 3778 ) 3727 3779 xt "44000,22000,82000,22800" 3728 st "D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ;" 3780 st "D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ; 3781 " 3729 3782 ) 3730 3783 thePort (LogicalPort … … 3761 3814 ) 3762 3815 xt "27200,97500,32000,98500" 3763 st "A1_T : ( 3:0)"3816 st "A1_T : (7:0)" 3764 3817 ju 2 3765 3818 blo "32000,98300" 3766 3819 tm "CptPortNameMgr" 3767 3820 ) 3821 t (Text 3822 uid 3123,0 3823 va (VaSet 3824 ) 3825 xt "25100,98500,32000,99500" 3826 st "(OTHERS => '0')" 3827 ju 2 3828 blo "32000,99300" 3829 tm "InitValueDelayMgr" 3830 ) 3768 3831 ) 3769 3832 dt (MLText … … 3772 3835 font "Courier New,8,0" 3773 3836 ) 3774 xt "44000,13200,71500,14000" 3775 st "A1_T : OUT std_logic_vector (3 DOWNTO 0) ;" 3837 xt "44000,13200,82000,14000" 3838 st "A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ; 3839 " 3776 3840 ) 3777 3841 thePort (LogicalPort … … 3780 3844 n "A1_T" 3781 3845 t "std_logic_vector" 3782 b "( 3DOWNTO 0)"3846 b "(7 DOWNTO 0)" 3783 3847 o 15 3784 3848 suid 66,0 3849 i "(OTHERS => '0')" 3785 3850 ) 3786 3851 ) … … 3795 3860 lineWidth 2 3796 3861 ) 3797 xt "15000,6000,33000, 99000"3862 xt "15000,6000,33000,101000" 3798 3863 ) 3799 3864 oxt "15000,6000,33000,26000" … … 3869 3934 bg "0,0,32768" 3870 3935 ) 3871 xt "36200,48000,45 700,49000"3936 xt "36200,48000,45500,49000" 3872 3937 st " 3873 3938 by %user on %dd %month %year … … 4452 4517 ) 4453 4518 ) 4454 lastUid 3 076,04519 lastUid 3292,0 4455 4520 activeModelName "Symbol:CDM" 4456 4521 )
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