Context Navigation

← Previous Change
Next Change →

@f@a@d_main

Timestamp:

07/16/10 16:25:44 (15 years ago)

Author:

dneise

Message:

DRS addresses may not be set via
sa 44 0 .. 31

Location:

FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main

Files:

: 2 edited

struct.bd (modified) (399 diffs)
struct.bd.bak (modified) (9 diffs)

Legend:

: Unmodified
: Added
: Removed

FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd

-              r249
+              r252
 uid 8277,0
+)
+(Instance
+name "U_0"
+duLibraryName "moduleware"
+duName "mux"
+elements [
+]
+mwi 1
+uid 8562,0
+)
+]
 libraryRefs [
 …
 (vvPair
 variable "time"
 value "11:42:03"
+value "14:21:30"
+)
 (vvPair
 …
 font "Courier New,8,0"
+)
+xt "-85000,84200,-41500,85000"
+st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\""
+xt "-85000,86600,-41500,87400"
+st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\"
+"
+)
+)
 …
+)
 xt "-85000,47400,-45000,48200"
+st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
+st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
+"
+)
+)
 …
+)
 xt "-85000,61800,-52500,62600"
+st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)"
+st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,69000,-45000,69800"
+st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)"
+xt "-85000,71400,-45000,72200"
+st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,69800,-52500,70600"
+st "SIGNAL ram_data               : std_logic_vector(15 downto 0)"
+xt "-85000,72200,-52500,73000"
+st "SIGNAL ram_data               : std_logic_vector(15 downto 0)
+"
+)
+)
 …
+)
 xt "-85000,39800,-45000,40600"
+st "wiz_reset              : std_logic                                    := '1'"
+st "wiz_reset              : std_logic                                    := '1'
+"
+)
+)
 …
+)
 xt "-85000,37400,-56500,38200"
+st "wiz_addr               : std_logic_vector(9 DOWNTO 0)"
+st "wiz_addr               : std_logic_vector(9 DOWNTO 0)
+"
+)
+)
 …
+)
 xt "-85000,42200,-56000,43000"
+st "wiz_data               : std_logic_vector(15 DOWNTO 0)"
+st "wiz_data               : std_logic_vector(15 DOWNTO 0)
+"
+)
+)
 …
+)
 xt "-85000,38200,-45000,39000"
+st "wiz_cs                 : std_logic                                    := '1'"
+st "wiz_cs                 : std_logic                                    := '1'
+"
+)
+)
 …
+)
 xt "-85000,40600,-45000,41400"
+st "wiz_wr                 : std_logic                                    := '1'"
+st "wiz_wr                 : std_logic                                    := '1'
+"
+)
+)
 …
+)
 xt "-85000,39000,-45000,39800"
+st "wiz_rd                 : std_logic                                    := '1'"
+st "wiz_rd                 : std_logic                                    := '1'
+"
+)
+)
 …
+)
 xt "-85000,26200,-66500,27000"
+st "wiz_int                : std_logic"
+st "wiz_int                : std_logic
+"
+)
+)
 …
+)
 xt "-85000,23800,-56500,24600"
+st "board_id               : std_logic_vector(3 downto 0)"
+st "board_id               : std_logic_vector(3 downto 0)
+"
+)
+)
 …
+)
 xt "-85000,25400,-66500,26200"
+st "trigger                : std_logic"
+st "trigger                : std_logic
+"
+)
+)
 …
+)
 xt "-85000,24600,-56500,25400"
+st "crate_id               : std_logic_vector(1 downto 0)"
+st "crate_id               : std_logic_vector(1 downto 0)
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,77000,-52500,77800"
+st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)"
+xt "-85000,79400,-52500,80200"
+st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,70600,-45000,71400"
+st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
+xt "-85000,73000,-45000,73800"
+st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,78600,-62500,79400"
+st "SIGNAL wiz_busy               : std_logic"
+xt "-85000,81000,-62500,81800"
+st "SIGNAL wiz_busy               : std_logic
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,81000,-41500,81800"
+st "SIGNAL wiz_write_ea           : std_logic                                    := '0'"
+xt "-85000,83400,-41500,84200"
+st "SIGNAL wiz_write_ea           : std_logic                                    := '0'
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,83400,-35500,84200"
+st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')"
+xt "-85000,85800,-35500,86600"
+st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,80200,-35500,81000"
+st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')"
+xt "-85000,82600,-35500,83400"
+st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,79400,-35500,80200"
+st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')"
+xt "-85000,81800,-35500,82600"
+st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,81800,-41500,82600"
+st "SIGNAL wiz_write_end          : std_logic                                    := '0'"
+xt "-85000,84200,-41500,85000"
+st "SIGNAL wiz_write_end          : std_logic                                    := '0'
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,82600,-41500,83400"
+st "SIGNAL wiz_write_header       : std_logic                                    := '0'"
+xt "-85000,85000,-41500,85800"
+st "SIGNAL wiz_write_header       : std_logic                                    := '0'
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,71400,-62500,72200"
+st "SIGNAL ram_write_ea           : std_logic"
+xt "-85000,73800,-62500,74600"
+st "SIGNAL ram_write_ea           : std_logic
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,72200,-41500,73000"
+st "SIGNAL ram_write_ready        : std_logic                                    := '0'"
+xt "-85000,74600,-41500,75400"
+st "SIGNAL ram_write_ready        : std_logic                                    := '0'
+"
+)
+)
 …
+)
 xt "-85000,54600,-41500,55400"
+st "SIGNAL config_start           : std_logic                                    := '0'"
+st "SIGNAL config_start           : std_logic                                    := '0'
+"
+)
+)
 …
+)
 xt "-85000,52200,-62500,53000"
+st "SIGNAL config_ready           : std_logic"
+st "SIGNAL config_ready           : std_logic
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,73800,-61000,74600"
+st "SIGNAL roi_max                : roi_max_type"
+xt "-85000,76200,-61000,77000"
+st "SIGNAL roi_max                : roi_max_type
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,68200,-52500,69000"
+st "SIGNAL package_length         : std_logic_vector(15 downto 0)"
+xt "-85000,70600,-52500,71400"
+st "SIGNAL package_length         : std_logic_vector(15 downto 0)
+"
+)
+)
 …
+)
 xt "-85000,30200,-45000,31000"
+st "adc_oeb                : std_logic                                    := '1'"
+st "adc_oeb                : std_logic                                    := '1'
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,73000,-60000,73800"
+st "SIGNAL roi_array              : roi_array_type"
+xt "-85000,75400,-60000,76200"
+st "SIGNAL roi_array              : roi_array_type
+"
+)
+)
 …
+)
 xt "-85000,27000,-66500,27800"
+st "CLK_25_PS              : std_logic"
+st "CLK_25_PS              : std_logic
+"
+)
+)
 …
+)
 xt "-85000,27800,-66500,28600"
+st "CLK_50                 : std_logic"
+st "CLK_50                 : std_logic
+"
+)
+)
 …
+)
 xt "-85000,45000,-62500,45800"
+st "SIGNAL CLK_25                 : std_logic"
+st "SIGNAL CLK_25                 : std_logic
+"
+)
+)
 …
+)
 xt "-85000,18200,-66500,19000"
+st "CLK                    : std_logic"
+st "CLK                    : std_logic
+"
+)
+)
 …
+)
 xt "-85000,23000,-56500,23800"
+st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)"
+st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)
+"
+)
+)
 …
+)
 xt "-85000,22200,-61000,23000"
+st "adc_data_array         : adc_data_array_type"
+st "adc_data_array         : adc_data_array_type
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,62600,-41500,63400"
+st "SIGNAL drs_clk_en             : std_logic                                    := '0'"
+xt "-85000,65000,-41500,65800"
+st "SIGNAL drs_clk_en             : std_logic                                    := '0'
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,65000,-56500,65800"
+st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type"
+xt "-85000,67400,-56500,68200"
+st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,63400,-41500,64200"
+st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'"
+xt "-85000,65800,-41500,66600"
+st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'
+"
+)
+)
 …
+)
 xt "-85000,32600,-39000,33400"
+st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')"
+st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')
+"
+)
+)
 …
+)
 xt "-85000,33400,-45000,34200"
+st "drs_dwrite             : std_logic                                    := '1'"
+st "drs_dwrite             : std_logic                                    := '1'
+"
+)
+)
 …
 sl 0
 ro 90
 xt "-28000,56625,-26500,57375"
+xt "-39000,99625,-37500,100375"
+)
 (Line
 …
 sl 0
 ro 90
 xt "-26500,57000,-26000,57000"
+xt "-37500,100000,-37000,100000"
 pts [
 "-26000,57000"
 "-26500,57000"
+"-37000,100000"
+"-37500,100000"
+]
+)
 …
 va (VaSet
+)
 xt "-34900,56500,-29000,57500"
+xt "-45900,99500,-40000,100500"
 st "drs_channel_id"
 ju 2
 blo "-29000,57300"
+blo "-40000,100300"
 tm "WireNameMgr"
+)
 …
+)
 xt "-85000,19000,-66500,19800"
+st "SROUT_in_0             : std_logic"
+st "SROUT_in_0             : std_logic
+"
+)
+)
 …
+)
 xt "-85000,19800,-66500,20600"
+st "SROUT_in_1             : std_logic"
+st "SROUT_in_1             : std_logic
+"
+)
+)
 …
+)
 xt "-85000,20600,-66500,21400"
+st "SROUT_in_2             : std_logic"
+st "SROUT_in_2             : std_logic
+"
+)
+)
 …
+)
 xt "-85000,21400,-66500,22200"
+st "SROUT_in_3             : std_logic"
+st "SROUT_in_3             : std_logic
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "-85000,64200,-62500,65000"
+st "SIGNAL drs_read_s_cell_ready  : std_logic"
+xt "-85000,66600,-62500,67400"
+st "SIGNAL drs_read_s_cell_ready  : std_logic
+"
+)
+)
 …
+)
 xt "-85000,28600,-45000,29400"
+st "RSRLOAD                : std_logic                                    := '0'"
+st "RSRLOAD                : std_logic                                    := '0'
+"
+)
+)
 …
+)
 xt "-85000,29400,-45000,30200"
+st "SRCLK                  : std_logic                                    := '0'"
+st "SRCLK                  : std_logic                                    := '0'
+"
+)
+)
 …
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
 o 12
+o 14
 suid 5,0
+)
 …
 n "roi_array"
 t "roi_array_type"
 o 11
+o 13
 suid 6,0
+)
 …
+)
+)
+*227 (CptPort
+uid 8500,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 8501,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "92000,109625,92750,110375"
+)
+tg (CPTG
+uid 8502,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 8503,0
+va (VaSet
+)
+xt "83800,109500,91000,110500"
+st "drs_address : (3:0)"
+ju 2
+blo "91000,110300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_address"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 11
+suid 13,0
+)
+)
+)
+*228 (CptPort
+uid 8504,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 8505,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "92000,110625,92750,111375"
+)
+tg (CPTG
+uid 8506,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 8507,0
+va (VaSet
+)
+xt "83800,110500,91000,111500"
+st "drs_address_mode"
+ju 2
+blo "91000,111300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_address_mode"
+t "std_logic"
+o 12
+suid 14,0
+)
+)
+)
+]
 shape (Rectangle
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *227 (Text
+*229 (Text
 uid 5075,0
 va (VaSet
 …
 tm "BdLibraryNameMgr"
+)
 *228 (Text
+*230 (Text
 uid 5076,0
 va (VaSet
 …
 tm "CptNameMgr"
+)
 *229 (Text
+*231 (Text
 uid 5077,0
 va (VaSet
 …
 archFileType "UNKNOWN"
+)
 *230 (Net
+*232 (Net
 uid 5088,0
 decl (Decl
 …
+)
 xt "-85000,48200,-53000,49000"
+st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)"
+)
+)
+*231 (Net
+st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)
+"
+)
+)
+*233 (Net
 uid 5096,0
 decl (Decl
 …
+)
 xt "-85000,50600,-62500,51400"
+st "SIGNAL config_data_valid      : std_logic"
+)
+)
+*232 (Net
+st "SIGNAL config_data_valid      : std_logic
+"
+)
+)
+*234 (Net
 uid 5104,0
 decl (Decl
 …
+)
 xt "-85000,49000,-62500,49800"
+st "SIGNAL config_busy            : std_logic"
+)
+)
+*233 (Net
+st "SIGNAL config_busy            : std_logic
+"
+)
+)
+*235 (Net
 uid 5112,0
 decl (Decl
 …
+)
 xt "-85000,49800,-52500,50600"
+st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)"
+)
+)
+*234 (Net
+st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)
+"
+)
+)
+*236 (Net
 uid 5120,0
 decl (Decl
 …
+)
 xt "-85000,60200,-62500,61000"
+st "SIGNAL config_wr_en           : std_logic"
+)
+)
+*235 (Net
+st "SIGNAL config_wr_en           : std_logic
+"
+)
+)
+*237 (Net
 uid 5128,0
 decl (Decl
 …
+)
 xt "-85000,51400,-62500,52200"
+st "SIGNAL config_rd_en           : std_logic"
+)
+)
+*236 (Net
+st "SIGNAL config_rd_en           : std_logic
+"
+)
+)
+*238 (Net
 uid 5144,0
 decl (Decl
 …
+)
 xt "-85000,61000,-60000,61800"
+st "SIGNAL dac_array              : dac_array_type"
+)
+)
+*237 (Net
+st "SIGNAL dac_array              : dac_array_type
+"
+)
+)
+*239 (Net
 uid 5194,0
 decl (Decl
 …
+)
 xt "-85000,55400,-62500,56200"
+st "SIGNAL config_start_cm        : std_logic"
+)
+)
+*238 (Net
+st "SIGNAL config_start_cm        : std_logic
+"
+)
+)
+*240 (Net
 uid 5196,0
 decl (Decl
 …
+)
 xt "-85000,53000,-62500,53800"
+st "SIGNAL config_ready_cm        : std_logic"
+)
+)
+*239 (Net
+st "SIGNAL config_ready_cm        : std_logic
+"
+)
+)
+*241 (Net
 uid 5220,0
 decl (Decl
 …
+)
 xt "-85000,34200,-39000,35000"
+st "led                    : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')"
+)
+)
+*240 (Net
+st "led                    : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')
+"
+)
+)
+*242 (Net
 uid 5279,0
 decl (Decl
 …
 font "Courier New,8,0"
+)
+xt "-85000,74600,-41500,75400"
+st "SIGNAL s_trigger              : std_logic                                    := '0'"
+)
+)
+*241 (Net
+xt "-85000,77000,-41500,77800"
+st "SIGNAL s_trigger              : std_logic                                    := '0'
+"
+)
+)
+*243 (Net
 uid 5472,0
 decl (Decl
 …
 font "Courier New,8,0"
+)
+xt "-85000,76200,-62500,77000"
+st "SIGNAL sensor_ready           : std_logic"
+)
+)
+*242 (Net
+xt "-85000,78600,-62500,79400"
+st "SIGNAL sensor_ready           : std_logic
+"
+)
+)
+*244 (Net
 uid 5478,0
 decl (Decl
 …
 font "Courier New,8,0"
+)
+xt "-85000,75400,-58500,76200"
+st "SIGNAL sensor_array           : sensor_array_type"
+)
+)
+*243 (Net
+xt "-85000,77800,-58500,78600"
+st "SIGNAL sensor_array           : sensor_array_type
+"
+)
+)
+*245 (Net
 uid 5588,0
 decl (Decl
 …
+)
 xt "-85000,53800,-62500,54600"
+st "SIGNAL config_ready_spi       : std_logic"
+)
+)
+*244 (Net
+st "SIGNAL config_ready_spi       : std_logic
+"
+)
+)
+*246 (Net
 uid 5632,0
 lang 10
 …
+)
 xt "-85000,46600,-53000,47400"
+st "SIGNAL adc_otr                : std_logic_vector(3 DOWNTO 0)"
+)
+)
+*245 (Net
+st "SIGNAL adc_otr                : std_logic_vector(3 DOWNTO 0)
+"
+)
+)
+*247 (Net
 uid 5640,0
 decl (Decl
 …
+)
 xt "-85000,45800,-57500,46600"
+st "SIGNAL adc_data_array_int     : adc_data_array_type"
+)
+)
+*246 (SaComponent
+st "SIGNAL adc_data_array_int     : adc_data_array_type
+"
+)
+)
+*248 (SaComponent
 uid 5678,0
 optionalChildren [
 *247 (CptPort
+*249 (CptPort
 uid 5658,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *248 (CptPort
+*250 (CptPort
 uid 5662,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *249 (CptPort
+*251 (CptPort
 uid 5666,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *250 (CptPort
+*252 (CptPort
 uid 5670,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *251 (CptPort
+*253 (CptPort
 uid 5674,0
 ps "OnEdgeStrategy"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *252 (Text
+*254 (Text
 uid 5681,0
 va (VaSet
 …
 tm "BdLibraryNameMgr"
+)
 *253 (Text
+*255 (Text
 uid 5682,0
 va (VaSet
 …
 tm "CptNameMgr"
+)
 *254 (Text
+*256 (Text
 uid 5683,0
 va (VaSet
 …
 archFileType "UNKNOWN"
+)
 *255 (Net
+*257 (Net
 uid 5743,0
 decl (Decl
 …
+)
 xt "-85000,56200,-41500,57000"
+st "SIGNAL config_start_spi       : std_logic                                    := '0'"
+)
+)
+*256 (SaComponent
+st "SIGNAL config_start_spi       : std_logic                                    := '0'
+"
+)
+)
+*258 (SaComponent
 uid 5793,0
 optionalChildren [
 *257 (CptPort
+*259 (CptPort
 uid 5753,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *258 (CptPort
+*260 (CptPort
 uid 5761,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *259 (CptPort
+*261 (CptPort
 uid 5765,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *260 (CptPort
+*262 (CptPort
 uid 5769,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *261 (CptPort
+*263 (CptPort
 uid 5773,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *262 (CptPort
+*264 (CptPort
 uid 5777,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *263 (CptPort
+*265 (CptPort
 uid 5781,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *264 (CptPort
+*266 (CptPort
 uid 5785,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *265 (CptPort
+*267 (CptPort
 uid 5789,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *266 (CptPort
+*268 (CptPort
 uid 5986,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *267 (CptPort
+*269 (CptPort
 uid 6154,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *268 (CptPort
+*270 (CptPort
 uid 6317,0
 ps "OnEdgeStrategy"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *269 (Text
+*271 (Text
 uid 5796,0
 va (VaSet
 …
 tm "BdLibraryNameMgr"
+)
 *270 (Text
+*272 (Text
 uid 5797,0
 va (VaSet
 …
 tm "CptNameMgr"
+)
 *271 (Text
+*273 (Text
 uid 5798,0
 va (VaSet
 …
 archFileType "UNKNOWN"
+)
 *272 (Net
+*274 (Net
 uid 5811,0
 decl (Decl
 …
+)
 xt "-85000,35800,-66500,36600"
+st "sclk                   : std_logic"
+)
+)
+*273 (Net
+st "sclk                   : std_logic
+"
+)
+)
+*275 (Net
 uid 5819,0
 decl (Decl
 …
+)
 xt "-85000,41400,-66500,42200"
+st "sio                    : std_logic"
+)
+)
+*274 (Net
+st "sio                    : std_logic
+"
+)
+)
+*276 (Net
 uid 5827,0
 decl (Decl
 …
+)
 xt "-85000,31000,-66500,31800"
+st "dac_cs                 : std_logic"
+)
+)
+*275 (Net
+st "dac_cs                 : std_logic
+"
+)
+)
+*277 (Net
 uid 5835,0
 decl (Decl
 …
+)
 xt "-85000,36600,-56500,37400"
+st "sensor_cs              : std_logic_vector(3 DOWNTO 0)"
+)
+)
+*276 (PortIoOut
+st "sensor_cs              : std_logic_vector(3 DOWNTO 0)
+"
+)
+)
+*278 (PortIoOut
 uid 5843,0
 shape (CompositeShape
 …
+)
+)
 *277 (PortIoInOut
+*279 (PortIoInOut
 uid 5849,0
 shape (CompositeShape
 …
+)
+)
 *278 (PortIoOut
+*280 (PortIoOut
 uid 5855,0
 shape (CompositeShape
 …
+)
+)
 *279 (PortIoOut
+*281 (PortIoOut
 uid 5861,0
 shape (CompositeShape
 …
+)
+)
 *280 (Net
+*282 (Net
 uid 5948,0
 decl (Decl
 …
 font "Courier New,8,0"
+)
+xt "-85000,67400,-41500,68200"
+st "SIGNAL new_config             : std_logic                                    := '0'"
+)
+)
+*281 (Net
+xt "-85000,69800,-41500,70600"
+st "SIGNAL new_config             : std_logic                                    := '0'
+"
+)
+)
+*283 (Net
 uid 5960,0
 decl (Decl
 …
+)
 xt "-85000,57000,-62500,57800"
+st "SIGNAL config_started         : std_logic"
+)
+)
+*282 (Net
+st "SIGNAL config_started         : std_logic
+"
+)
+)
+*284 (Net
 uid 6012,0
 decl (Decl
 …
+)
 xt "-85000,59400,-41500,60200"
+st "SIGNAL config_started_spi     : std_logic                                    := '0'"
+)
+)
+*283 (Net
+st "SIGNAL config_started_spi     : std_logic                                    := '0'
+"
+)
+)
+*285 (Net
 uid 6014,0
 decl (Decl
 …
+)
 xt "-85000,57800,-41500,58600"
+st "SIGNAL config_started_cu      : std_logic                                    := '0'"
+)
+)
+*284 (Net
+st "SIGNAL config_started_cu      : std_logic                                    := '0'
+"
+)
+)
+*286 (Net
 uid 6016,0
 decl (Decl
 …
+)
 xt "-85000,58600,-62500,59400"
+st "SIGNAL config_started_mm      : std_logic"
+)
+)
+*285 (Net
+st "SIGNAL config_started_mm      : std_logic
+"
+)
+)
+*287 (Net
 uid 6158,0
 decl (Decl
 …
+)
 xt "-85000,35000,-45000,35800"
+st "mosi                   : std_logic                                    := '0'"
+)
+)
+*286 (PortIoOut
+st "mosi                   : std_logic                                    := '0'
+"
+)
+)
+*288 (PortIoOut
 uid 6166,0
 shape (CompositeShape
 …
+)
+)
 *287 (Net
+*289 (Net
 uid 6360,0
 decl (Decl
 …
+)
 xt "-85000,31800,-31500,32600"
+st "denable                : std_logic                                    := '0' -- default domino wave off"
+)
+)
+*288 (PortIoOut
+st "denable                : std_logic                                    := '0' -- default domino wave off
+"
+)
+)
+*290 (PortIoOut
 uid 6368,0
 shape (CompositeShape
 …
+)
+)
 *289 (Net
+*291 (Net
 uid 6450,0
 decl (Decl
 …
 font "Courier New,8,0"
+)
+xt "-85000,66600,-41500,67400"
+st "SIGNAL dwrite_enable          : std_logic                                    := '1'"
+)
+)
+*290 (MWC
+xt "-85000,69000,-41500,69800"
+st "SIGNAL dwrite_enable          : std_logic                                    := '1'
+"
+)
+)
+*292 (MWC
 uid 6529,0
 optionalChildren [
 *291 (CptPort
+*293 (CptPort
 uid 6501,0
 optionalChildren [
 *292 (Line
+*294 (Line
 uid 6505,0
 layer 5
 …
+]
+)
 *293 (Property
+*295 (Property
 uid 6506,0
 pclass "_MW_GEOM_"
 …
+)
+)
 *294 (CptPort
+*296 (CptPort
 uid 6507,0
 optionalChildren [
 *295 (Line
+*297 (Line
 uid 6511,0
 layer 5
 …
+)
+)
 *296 (CptPort
+*298 (CptPort
 uid 6512,0
 optionalChildren [
 *297 (Line
+*299 (Line
 uid 6516,0
 layer 5
 …
+)
+)
 *298 (CommentGraphic
+*300 (CommentGraphic
 uid 6517,0
 optionalChildren [
 *299 (Property
+*301 (Property
 uid 6519,0
 pclass "_MW_GEOM_"
 …
 oxt "11000,10000,11000,10000"
+)
 *300 (CommentGraphic
+*302 (CommentGraphic
 uid 6520,0
 optionalChildren [
 *301 (Property
+*303 (Property
 uid 6522,0
 pclass "_MW_GEOM_"
 …
 oxt "11000,6000,11000,6000"
+)
 *302 (Grouping
+*304 (Grouping
 uid 6523,0
 optionalChildren [
 *303 (CommentGraphic
+*305 (CommentGraphic
 uid 6525,0
 shape (PolyLine2D
 …
 oxt "9000,6000,11000,10000"
+)
 *304 (CommentGraphic
+*306 (CommentGraphic
 uid 6527,0
 shape (Arc2D
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *305 (Text
+*307 (Text
 uid 6532,0
 va (VaSet
 …
 blo "3500,59300"
+)
 *306 (Text
+*308 (Text
 uid 6533,0
 va (VaSet
 …
 blo "3500,60300"
+)
 *307 (Text
+*309 (Text
 uid 6534,0
 va (VaSet
 …
+)
+)
 *308 (Net
+*310 (Net
 uid 6544,0
 decl (Decl
 …
 font "Courier New,8,0"
+)
+xt "-85000,65800,-41500,66600"
+st "SIGNAL dwrite                 : std_logic                                    := '1'"
+)
+)
+*309 (SaComponent
+xt "-85000,68200,-41500,69000"
+st "SIGNAL dwrite                 : std_logic                                    := '1'
+"
+)
+)
+*311 (SaComponent
 uid 8277,0
 optionalChildren [
 *310 (CptPort
+*312 (CptPort
 uid 8246,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *311 (CptPort
+*313 (CptPort
 uid 8250,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *312 (CptPort
+*314 (CptPort
 uid 8254,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *313 (CptPort
+*315 (CptPort
 uid 8258,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *314 (CptPort
+*316 (CptPort
 uid 8262,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *315 (CptPort
+*317 (CptPort
 uid 8266,0
 ps "OnEdgeStrategy"
 …
+)
+)
 *316 (CptPort
+*318 (CptPort
 uid 8270,0
 ps "OnEdgeStrategy"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *317 (Text
+*319 (Text
 uid 8280,0
 va (VaSet
 …
 tm "BdLibraryNameMgr"
+)
 *318 (Text
+*320 (Text
 uid 8281,0
 va (VaSet
 …
 tm "CptNameMgr"
+)
 *319 (Text
+*321 (Text
 uid 8282,0
 va (VaSet
 …
 archFileType "UNKNOWN"
+)
 *320 (Net
+*322 (Net
 uid 8414,0
 lang 2
 …
 font "Courier New,8,0"
+)
+xt "-85000,77800,-62500,78600"
+st "SIGNAL wiz_ack                : std_logic"
+)
+)
+*321 (Wire
+xt "-85000,80200,-62500,81000"
+st "SIGNAL wiz_ack                : std_logic
+"
+)
+)
+*323 (Net
+uid 8508,0
+decl (Decl
+n "drs_address"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 82
+suid 184,0
+i "(others => '0')"
+)
+declText (MLText
+uid 8509,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "-85000,62600,-35500,63400"
+st "SIGNAL drs_address            : std_logic_vector(3 DOWNTO 0)                 := (others => '0')
+"
+)
+)
+*324 (Net
+uid 8516,0
+decl (Decl
+n "drs_address_mode"
+t "std_logic"
+o 83
+suid 185,0
+)
+declText (MLText
+uid 8517,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "-85000,63400,-62500,64200"
+st "SIGNAL drs_address_mode       : std_logic
+"
+)
+)
+*325 (MWC
+uid 8562,0
+optionalChildren [
+*326 (CptPort
+uid 8524,0
+optionalChildren [
+*327 (Line
+uid 8528,0
+layer 5
+sl 0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "-29999,101000,-29000,101000"
+pts [
+"-29000,101000"
+"-29999,101000"
+]
+)
+]
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 8525,0
+ro 270
+va (VaSet
+vasetType 1
+isHidden 1
+fg "0,65535,65535"
+)
+xt "-29000,100625,-28250,101375"
+)
+tg (CPTG
+uid 8526,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 8527,0
+sl 0
+va (VaSet
+isHidden 1
+font "arial,8,0"
+)
+xt "-98971,288551,-97171,289551"
+st "din0"
+ju 2
+blo "-97171,289351"
+)
+s (Text
+uid 8571,0
+sl 0
+va (VaSet
+font "arial,8,0"
+)
+xt "-97171,289551,-97171,289551"
+ju 2
+blo "-97171,289551"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "din0"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 84
+suid 1,0
+i "(others => '0')"
+)
+)
+)
+*328 (CptPort
+uid 8529,0
+optionalChildren [
+*329 (Line
+uid 8533,0
+layer 5
+sl 0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "-33000,100000,-31999,100000"
+pts [
+"-33000,100000"
+"-31999,100000"
+]
+)
+*330 (Property
+uid 8534,0
+pclass "_MW_GEOM_"
+pname "fixed"
+ptn "String"
+)
+]
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 8530,0
+ro 270
+va (VaSet
+vasetType 1
+isHidden 1
+fg "0,65535,65535"
+)
+xt "-33750,99625,-33000,100375"
+)
+tg (CPTG
+uid 8531,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 8532,0
+sl 0
+va (VaSet
+isHidden 1
+font "arial,8,0"
+)
+xt "-100999,287527,-99199,288527"
+st "dout"
+blo "-100999,288327"
+)
+s (Text
+uid 8572,0
+sl 0
+va (VaSet
+font "arial,8,0"
+)
+xt "-100999,288527,-100999,288527"
+blo "-100999,288527"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "dout"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 19
+suid 2,0
+i "(others => '0')"
+)
+)
+)
+*331 (CptPort
+uid 8535,0
+optionalChildren [
+*332 (Line
+uid 8539,0
+layer 5
+sl 0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "-29999,99000,-29000,99000"
+pts [
+"-29000,99000"
+"-29999,99000"
+]
+)
+]
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 8536,0
+ro 270
+va (VaSet
+vasetType 1
+isHidden 1
+fg "0,65535,65535"
+)
+xt "-29000,98625,-28250,99375"
+)
+tg (CPTG
+uid 8537,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 8538,0
+sl 0
+va (VaSet
+isHidden 1
+font "arial,8,0"
+)
+xt "-98971,286503,-97171,287503"
+st "din1"
+ju 2
+blo "-97171,287303"
+)
+s (Text
+uid 8573,0
+sl 0
+va (VaSet
+font "arial,8,0"
+)
+xt "-97171,287503,-97171,287503"
+ju 2
+blo "-97171,287503"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "din1"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 82
+suid 3,0
+i "(others => '0')"
+)
+)
+)
+*333 (CptPort
+uid 8540,0
+optionalChildren [
+*334 (Line
+uid 8544,0
+layer 5
+sl 0
+va (VaSet
+vasetType 3
+)
+xt "-31000,101333,-31000,103000"
+pts [
+"-31000,103000"
+"-31000,101333"
+]
+)
+]
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 8541,0
+va (VaSet
+vasetType 1
+isHidden 1
+fg "0,65535,65535"
+)
+xt "-31375,103000,-30625,103750"
+)
+tg (CPTG
+uid 8542,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 8543,0
+sl 0
+ro 270
+va (VaSet
+isHidden 1
+font "arial,8,0"
+)
+xt "-99473,289183,-98473,290583"
+st "sel"
+blo "-98673,290583"
+)
+s (Text
+uid 8574,0
+sl 0
+ro 270
+va (VaSet
+font "arial,8,0"
+)
+xt "-98473,290583,-98473,290583"
+blo "-98473,290583"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "sel"
+t "std_logic"
+o 83
+suid 4,0
+)
+)
+)
+*335 (CommentGraphic
+uid 8545,0
+shape (CustomPolygon
+pts [
+"-30000,102000"
+"-32000,100666"
+"-32000,99334"
+"-30000,98000"
+"-30000,102000"
+]
+uid 8546,0
+layer 0
+sl 0
+va (VaSet
+vasetType 1
+fg "0,65535,65535"
+bg "0,65535,65535"
+lineColor "26368,26368,26368"
+)
+xt "-32000,98000,-30000,102000"
+)
+oxt "7000,7000,9000,11000"
+)
+*336 (CommentGraphic
+uid 8547,0
+optionalChildren [
+*337 (Property
+uid 8549,0
+pclass "_MW_GEOM_"
+pname "expand"
+ptn "String"
+)
+]
+shape (PolyLine2D
+pts [
+"-30000,98000"
+"-30000,98000"
+]
+uid 8548,0
+layer 0
+sl 0
+va (VaSet
+vasetType 1
+transparent 1
+fg "49152,49152,49152"
+)
+xt "-30000,98000,-30000,98000"
+)
+oxt "9000,7000,9000,7000"
+)
+*338 (CommentGraphic
+uid 8550,0
+optionalChildren [
+*339 (Property
+uid 8552,0
+pclass "_MW_GEOM_"
+pname "expand"
+ptn "String"
+)
+]
+shape (PolyLine2D
+pts [
+"-30000,102000"
+"-30000,102000"
+]
+uid 8551,0
+layer 0
+sl 0
+va (VaSet
+vasetType 1
+transparent 1
+fg "49152,49152,49152"
+)
+xt "-30000,102000,-30000,102000"
+)
+oxt "9000,11000,9000,11000"
+)
+*340 (CommentText
+uid 8553,0
+shape (Rectangle
+uid 8554,0
+sl 0
+va (VaSet
+vasetType 1
+transparent 1
+fg "65535,65535,65535"
+lineColor "65535,65535,65535"
+lineWidth -1
+)
+xt "-32000,100000,-30000,101506"
+)
+oxt "7000,9000,9000,10506"
+text (MLText
+uid 8555,0
+sl 0
+va (VaSet
+font "arial,8,0"
+)
+xt "-31800,100200,-30600,101200"
+st "
+Lo
+"
+tm "CommentText"
+wrapOption 3
+visibleHeight 1506
+visibleWidth 2000
+)
+)
+*341 (CommentText
+uid 8556,0
+shape (Rectangle
+uid 8557,0
+layer 8
+sl 0
+va (VaSet
+vasetType 1
+transparent 1
+fg "65535,65535,65535"
+lineColor "65535,65535,65535"
+lineWidth -1
+)
+xt "-32000,98000,-30002,99556"
+)
+oxt "7000,7000,8998,8556"
+text (MLText
+uid 8558,0
+sl 0
+va (VaSet
+font "arial,8,0"
+)
+xt "-31800,98200,-30600,99200"
+st "
+Hi
+"
+tm "CommentText"
+wrapOption 3
+visibleHeight 1556
+visibleWidth 1998
+)
+)
+*342 (CommentText
+uid 8559,0
+shape (Rectangle
+uid 8560,0
+layer 0
+sl 0
+va (VaSet
+vasetType 1
+transparent 1
+fg "65535,65535,65535"
+lineColor "65535,65535,65535"
+lineWidth -1
+)
+xt "-32111,99517,-30111,100517"
+)
+oxt "6889,8517,8889,9517"
+text (MLText
+uid 8561,0
+sl 0
+va (VaSet
+font "arial,8,0"
+)
+xt "-31911,99717,-30211,100717"
+st "
+mux
+"
+tm "CommentText"
+wrapOption 3
+visibleHeight 1000
+visibleWidth 2000
+)
+)
+]
+shape (Rectangle
+uid 8563,0
+va (VaSet
+vasetType 1
+transparent 1
+fg "65535,65535,65535"
+lineWidth -1
+)
+xt "-33000,97000,-29000,103000"
+fos 1
+)
+showPorts 0
+oxt "6000,6000,10000,12000"
+ttg (MlTextGroup
+uid 8564,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*343 (Text
+uid 8565,0
+va (VaSet
+isHidden 1
+font "arial,8,0"
+)
+xt "-30650,102100,-25850,103100"
+st "moduleware"
+blo "-30650,102900"
+)
+*344 (Text
+uid 8566,0
+va (VaSet
+font "arial,8,0"
+)
+xt "-30650,103100,-28950,104100"
+st "mux"
+blo "-30650,103900"
+)
+*345 (Text
+uid 8567,0
+va (VaSet
+font "arial,8,0"
+)
+xt "-30650,104100,-28850,105100"
+st "U_0"
+blo "-30650,104900"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 8568,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 8569,0
+text (MLText
+uid 8570,0
+va (VaSet
+font "arial,8,0"
+)
+xt "-36000,79400,-36000,79400"
+)
+header ""
+)
+elements [
+]
+)
+sed 1
+awe 1
+portVis (PortSigDisplay
+disp 1
+sN 0
+sTC 0
+selT 0
+)
+prms (Property
+pclass "params"
+pname "params"
+ptn "String"
+)
+de 1
+visOptions (mwParamsVisibilityOptions
+)
+)
+*346 (Net
+uid 8583,0
+decl (Decl
+n "drs_channel_internal"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 84
+suid 187,0
+i "(others => '0')"
+)
+declText (MLText
+uid 8584,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "-85000,64200,-35500,65000"
+st "SIGNAL drs_channel_internal   : std_logic_vector(3 DOWNTO 0)                 := (others => '0')
+"
+)
+)
+*347 (Wire
 uid 322,0
 shape (OrthoPolyLine
 …
+)
 start &26
 end &313
+end &315
 sat 32
 eat 32
 …
 on &2
+)
 *322 (Wire
+*348 (Wire
 uid 328,0
 shape (OrthoPolyLine
 …
+)
 start &25
 end &312
+end &314
 sat 32
 eat 32
 …
 on &3
+)
 *323 (Wire
+*349 (Wire
 uid 334,0
 shape (OrthoPolyLine
 …
+)
 start &24
 end &311
+end &313
 sat 32
 eat 32
 …
 on &4
+)
 *324 (Wire
+*350 (Wire
 uid 364,0
 shape (OrthoPolyLine
 …
+)
 start &79
 end &315
+end &317
 sat 32
 eat 32
 …
 on &5
+)
 *325 (Wire
+*351 (Wire
 uid 370,0
 shape (OrthoPolyLine
 …
+)
 start &78
 end &316
+end &318
 sat 32
 eat 32
 …
 on &6
+)
 *326 (Wire
+*352 (Wire
 uid 376,0
 shape (OrthoPolyLine
 …
 on &7
+)
 *327 (Wire
+*353 (Wire
 uid 384,0
 shape (OrthoPolyLine
 …
 on &8
+)
 *328 (Wire
+*354 (Wire
 uid 392,0
 shape (OrthoPolyLine
 …
 on &9
+)
 *329 (Wire
+*355 (Wire
 uid 400,0
 shape (OrthoPolyLine
 …
 on &10
+)
 *330 (Wire
+*356 (Wire
 uid 408,0
 shape (OrthoPolyLine
 …
 on &11
+)
 *331 (Wire
+*357 (Wire
 uid 424,0
 shape (OrthoPolyLine
 …
 on &12
+)
 *332 (Wire
+*358 (Wire
 uid 432,0
 shape (OrthoPolyLine
 …
 on &13
+)
 *333 (Wire
+*359 (Wire
 uid 1411,0
 shape (OrthoPolyLine
 …
 on &64
+)
 *334 (Wire
+*360 (Wire
 uid 1425,0
 optionalChildren [
 *335 (BdJunction
+*361 (BdJunction
 uid 4391,0
 ps "OnConnectorStrategy"
 …
 on &65
+)
 *336 (Wire
+*362 (Wire
 uid 1682,0
 shape (OrthoPolyLine
 …
 on &100
+)
 *337 (Wire
+*363 (Wire
 uid 1983,0
 shape (OrthoPolyLine
 …
 on &108
+)
 *338 (Wire
+*364 (Wire
 uid 2299,0
 shape (OrthoPolyLine
 …
 on &109
+)
 *339 (Wire
+*365 (Wire
 uid 2470,0
 shape (OrthoPolyLine
 …
 on &132
+)
 *340 (Wire
+*366 (Wire
 uid 2476,0
 shape (OrthoPolyLine
 …
 on &133
+)
 *341 (Wire
+*367 (Wire
 uid 2482,0
 shape (OrthoPolyLine
 …
 on &134
+)
 *342 (Wire
+*368 (Wire
 uid 2488,0
 shape (OrthoPolyLine
 …
 on &135
+)
 *343 (Wire
+*369 (Wire
 uid 2494,0
 shape (OrthoPolyLine
 …
 on &136
+)
 *344 (Wire
+*370 (Wire
 uid 2500,0
 shape (OrthoPolyLine
 …
 on &137
+)
 *345 (Wire
+*371 (Wire
 uid 2506,0
 shape (OrthoPolyLine
 …
 on &138
+)
 *346 (Wire
+*372 (Wire
 uid 2576,0
 shape (OrthoPolyLine
 …
 on &139
+)
 *347 (Wire
+*373 (Wire
 uid 2582,0
 shape (OrthoPolyLine
 …
 on &140
+)
 *348 (Wire
+*374 (Wire
 uid 2588,0
 shape (OrthoPolyLine
 …
 on &141
+)
 *349 (Wire
+*375 (Wire
 uid 2594,0
 shape (OrthoPolyLine
 …
 on &142
+)
 *350 (Wire
+*376 (Wire
 uid 2600,0
 shape (OrthoPolyLine
 …
 on &143
+)
 *351 (Wire
+*377 (Wire
 uid 2642,0
 shape (OrthoPolyLine
 …
 on &144
+)
 *352 (Wire
+*378 (Wire
 uid 2778,0
 shape (OrthoPolyLine
 …
 on &145
+)
 *353 (Wire
+*379 (Wire
 uid 2786,0
 shape (OrthoPolyLine
 …
+)
 start &147
 end &250
+end &252
 sat 32
 eat 32
 …
 on &176
+)
 *354 (Wire
+*380 (Wire
 uid 2876,0
 shape (OrthoPolyLine
 …
+]
+)
 start &335
+start &361
 end &103
 es 0
 …
 on &65
+)
 *355 (Wire
+*381 (Wire
 uid 3888,0
 optionalChildren [
 *356 (BdJunction
+*382 (BdJunction
 uid 4230,0
 ps "OnConnectorStrategy"
 …
+)
+)
 *357 (BdJunction
+*383 (BdJunction
 uid 4244,0
 ps "OnConnectorStrategy"
 …
 on &164
+)
 *358 (Wire
+*384 (Wire
 uid 3984,0
 shape (OrthoPolyLine
 …
 on &162
+)
 *359 (Wire
+*385 (Wire
 uid 4042,0
 shape (OrthoPolyLine
 …
 on &175
+)
 *360 (Wire
+*386 (Wire
 uid 4226,0
 shape (OrthoPolyLine
 …
+)
 start &174
 end &356
+end &382
 sat 32
 eat 32
 …
 on &164
+)
 *361 (Wire
+*387 (Wire
 uid 4240,0
 shape (OrthoPolyLine
 …
+]
+)
 start &314
 end &357
+start &316
+end &383
 sat 32
 eat 32
 …
 on &164
+)
 *362 (Wire
+*388 (Wire
 uid 4272,0
 shape (OrthoPolyLine
 …
+)
 start &178
 end &247
+end &249
 sat 32
 eat 32
 …
 on &177
+)
 *363 (Wire
+*389 (Wire
 uid 4401,0
 shape (OrthoPolyLine
 …
 on &179
+)
 *364 (Wire
+*390 (Wire
 uid 4407,0
 shape (OrthoPolyLine
 …
 on &180
+)
 *365 (Wire
+*391 (Wire
 uid 4419,0
 shape (OrthoPolyLine
 …
 on &181
+)
 *366 (Wire
+*392 (Wire
 uid 4537,0
 shape (OrthoPolyLine
 …
 lineWidth 2
+)
 xt "-26000,57000,18250,57000"
+xt "-37000,100000,-33000,100000"
 pts [
 "18250,57000"
 "-26000,57000"
+]
+)
 start &39
+"-33000,100000"
+"-37000,100000"
+]
+)
+start &328
 end &184
 sat 32
 …
 isHidden 1
+)
 xt "-20000,56000,-14100,57000"
+xt "-71000,99000,-65100,100000"
 st "drs_channel_id"
 blo "-20000,56800"
+blo "-71000,99800"
 tm "WireNameMgr"
+)
 …
 on &182
+)
 *367 (Wire
+*393 (Wire
 uid 4545,0
 shape (OrthoPolyLine
 …
+]
+)
 start &291
+start &293
 end &185
 sat 32
 …
 on &183
+)
 *368 (Wire
+*394 (Wire
 uid 4671,0
 shape (OrthoPolyLine
 …
 on &186
+)
 *369 (Wire
+*395 (Wire
 uid 4679,0
 shape (OrthoPolyLine
 …
 on &187
+)
 *370 (Wire
+*396 (Wire
 uid 4687,0
 shape (OrthoPolyLine
 …
 on &188
+)
 *371 (Wire
+*397 (Wire
 uid 4695,0
 shape (OrthoPolyLine
 …
 on &189
+)
 *372 (Wire
+*398 (Wire
 uid 4743,0
 shape (OrthoPolyLine
 …
 on &194
+)
 *373 (Wire
+*399 (Wire
 uid 4757,0
 optionalChildren [
 *374 (BdJunction
+*400 (BdJunction
 uid 6076,0
 ps "OnConnectorStrategy"
 …
+)
 start &196
 end *375 (BdJunction
+end *401 (BdJunction
 uid 6080,0
 ps "OnConnectorStrategy"
 …
 on &173
+)
 *376 (Wire
+*402 (Wire
 uid 4948,0
 shape (OrthoPolyLine
 …
 on &210
+)
 *377 (Wire
+*403 (Wire
 uid 4962,0
 shape (OrthoPolyLine
 …
 on &212
+)
 *378 (Wire
+*404 (Wire
 uid 5090,0
 shape (OrthoPolyLine
 …
+)
+)
 on &230
+)
 *379 (Wire
+on &232
+)
+*405 (Wire
 uid 5098,0
 shape (OrthoPolyLine
 …
+)
+)
 on &231
+)
 *380 (Wire
+on &233
+)
+*406 (Wire
 uid 5106,0
 shape (OrthoPolyLine
 …
+)
+)
 on &232
+)
 *381 (Wire
+on &234
+)
+*407 (Wire
 uid 5114,0
 shape (OrthoPolyLine
 …
+)
+)
 on &233
+)
 *382 (Wire
+on &235
+)
+*408 (Wire
 uid 5122,0
 shape (OrthoPolyLine
 …
+)
+)
 on &234
+)
 *383 (Wire
+on &236
+)
+*409 (Wire
 uid 5130,0
 shape (OrthoPolyLine
 …
+)
+)
 on &235
+)
 *384 (Wire
+on &237
+)
+*410 (Wire
 uid 5138,0
 optionalChildren [
 *385 (BdJunction
+*411 (BdJunction
 uid 5400,0
 ps "OnConnectorStrategy"
 …
 on &148
+)
 *386 (Wire
+*412 (Wire
 uid 5146,0
 shape (OrthoPolyLine
 …
+)
 start &222
 end &258
+end &260
 es 0
 sat 32
 …
+)
+)
 on &236
+)
 *387 (Wire
+on &238
+)
+*413 (Wire
 uid 5168,0
 shape (OrthoPolyLine
 …
+]
+)
 start &385
+start &411
 end &125
 sat 32
 …
 on &148
+)
 *388 (Wire
+*414 (Wire
 uid 5184,0
 shape (OrthoPolyLine
 …
+)
+)
 on &237
+)
 *389 (Wire
+on &239
+)
+*415 (Wire
 uid 5190,0
 shape (OrthoPolyLine
 …
+)
+)
 on &238
+)
 *390 (Wire
+on &240
+)
+*416 (Wire
 uid 5222,0
 shape (OrthoPolyLine
 …
+)
+)
 on &239
+)
 *391 (Wire
+on &241
+)
+*417 (Wire
 uid 5281,0
 shape (OrthoPolyLine
 …
+)
+)
 on &240
+)
 *392 (Wire
+on &242
+)
+*418 (Wire
 uid 5404,0
 shape (OrthoPolyLine
 …
+]
+)
 start &259
+start &261
 end &50
 sat 32
 …
+)
+)
 on &243
+)
 *393 (Wire
+on &245
+)
+*419 (Wire
 uid 5474,0
 shape (OrthoPolyLine
 …
+]
+)
 start &262
+start &264
 end &52
 sat 32
 …
+)
+)
 on &241
+)
 *394 (Wire
+on &243
+)
+*420 (Wire
 uid 5480,0
 shape (OrthoPolyLine
 …
+]
+)
 start &261
+start &263
 end &51
 sat 32
 …
+)
+)
 on &242
+)
 *395 (Wire
+on &244
+)
+*421 (Wire
 uid 5582,0
 shape (OrthoPolyLine
 …
 on &164
+)
 *396 (Wire
+*422 (Wire
 uid 5602,0
 optionalChildren [
 &375
 *397 (BdJunction
+&401
+*423 (BdJunction
 uid 6086,0
 ps "OnConnectorStrategy"
 …
+)
 start &23
 end &310
+end &312
 sat 32
 eat 32
 …
 on &173
+)
 *398 (Wire
+*424 (Wire
 uid 5626,0
 shape (OrthoPolyLine
 …
+)
 start &45
 end &248
+end &250
 sat 32
 eat 32
 …
+)
+)
 on &245
+)
 *399 (Wire
+on &247
+)
+*425 (Wire
 uid 5634,0
 shape (OrthoPolyLine
 …
+)
 start &38
 end &249
+end &251
 sat 32
 eat 32
 …
+)
+)
 on &244
+)
 *400 (Wire
+on &246
+)
+*426 (Wire
 uid 5646,0
 shape (OrthoPolyLine
 …
+]
+)
 end &251
+end &253
 sat 16
 eat 32
 …
 on &162
+)
 *401 (Wire
+*427 (Wire
 uid 5745,0
 shape (OrthoPolyLine
 …
+)
 start &54
 end &260
+end &262
 sat 32
 eat 32
 …
+)
+)
 on &255
+)
 *402 (Wire
+on &257
+)
+*428 (Wire
 uid 5805,0
 shape (OrthoPolyLine
 …
+]
+)
 end &265
+end &267
 sat 16
 eat 32
 …
 on &164
+)
 *403 (Wire
+*429 (Wire
 uid 5813,0
 shape (OrthoPolyLine
 …
+]
+)
 start &257
 end &276
+start &259
+end &278
 sat 32
 eat 32
 …
+)
+)
 on &272
+)
 *404 (Wire
+on &274
+)
+*430 (Wire
 uid 5821,0
 shape (OrthoPolyLine
 …
+]
+)
 start &268
 end &277
+start &270
+end &279
 sat 32
 eat 32
 …
+)
+)
 on &273
+)
 *405 (Wire
+on &275
+)
+*431 (Wire
 uid 5829,0
 shape (OrthoPolyLine
 …
+]
+)
 start &263
 end &278
+start &265
+end &280
 sat 32
 eat 32
 …
+)
+)
 on &274
+)
 *406 (Wire
+on &276
+)
+*432 (Wire
 uid 5837,0
 shape (OrthoPolyLine
 …
+]
+)
 start &264
 end &279
+start &266
+end &281
 sat 32
 eat 32
 …
+)
+)
 on &275
+)
 *407 (Wire
+on &277
+)
+*433 (Wire
 uid 5950,0
 shape (OrthoPolyLine
 …
+)
+)
 on &280
+)
 *408 (Wire
+on &282
+)
+*434 (Wire
 uid 5962,0
 shape (OrthoPolyLine
 …
+)
+)
 on &281
+)
 *409 (Wire
+on &283
+)
+*435 (Wire
 uid 6002,0
 shape (OrthoPolyLine
 …
+)
+)
 on &283
+)
 *410 (Wire
+on &285
+)
+*436 (Wire
 uid 6008,0
 shape (OrthoPolyLine
 …
+]
+)
 start &266
+start &268
 end &59
 sat 32
 …
+)
+)
 on &282
+)
 *411 (Wire
+on &284
+)
+*437 (Wire
 uid 6018,0
 shape (OrthoPolyLine
 …
+)
+)
 on &284
+)
 *412 (Wire
+on &286
+)
+*438 (Wire
 uid 6064,0
 shape (OrthoPolyLine
 …
+)
+)
 on &236
+)
 *413 (Wire
+on &238
+)
+*439 (Wire
 uid 6072,0
 shape (OrthoPolyLine
 …
+)
 start &167
 end &374
+end &400
 sat 32
 eat 32
 …
 on &173
+)
 *414 (Wire
+*440 (Wire
 uid 6082,0
 shape (OrthoPolyLine
 …
+)
 start &112
 end &397
+end &423
 sat 32
 eat 32
 …
 on &173
+)
 *415 (Wire
+*441 (Wire
 uid 6160,0
 shape (OrthoPolyLine
 …
+]
+)
 start &267
 end &286
+start &269
+end &288
 sat 32
 eat 32
 …
+)
+)
 on &285
+)
 *416 (Wire
+on &287
+)
+*442 (Wire
 uid 6276,0
 shape (OrthoPolyLine
 …
 on &162
+)
 *417 (Wire
+*443 (Wire
 uid 6362,0
 shape (OrthoPolyLine
 …
+)
 start &94
 end &288
+end &290
 sat 32
 eat 32
 …
+)
+)
 on &287
+)
 *418 (Wire
+on &289
+)
+*444 (Wire
 uid 6452,0
 shape (OrthoPolyLine
 …
+)
+)
 on &289
+)
 *419 (Wire
+on &291
+)
+*445 (Wire
 uid 6540,0
 shape (OrthoPolyLine
 …
+]
+)
 start &294
+start &296
 end &41
 sat 32
 …
+)
+)
 on &308
+)
 *420 (Wire
+on &310
+)
+*446 (Wire
 uid 6548,0
 shape (OrthoPolyLine
 …
+]
+)
 start &296
+start &298
 sat 32
 eat 16
 …
+)
+)
 on &289
+)
 *421 (Wire
+on &291
+)
+*447 (Wire
 uid 8416,0
 shape (OrthoPolyLine
 …
+)
+)
+on &320
+on &322
+)
+*448 (Wire
+uid 8510,0
+shape (OrthoPolyLine
+uid 8511,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "92750,110000,102000,110000"
+pts [
+"92750,110000"
+"102000,110000"
+]
+)
+start &227
+sat 32
+eat 16
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 8514,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 8515,0
+va (VaSet
+)
+xt "94000,109000,101200,110000"
+st "drs_address : (3:0)"
+blo "94000,109800"
+tm "WireNameMgr"
+)
+)
+on &323
+)
+*449 (Wire
+uid 8518,0
+shape (OrthoPolyLine
+uid 8519,0
+va (VaSet
+vasetType 3
+)
+xt "92750,111000,102000,111000"
+pts [
+"92750,111000"
+"102000,111000"
+]
+)
+start &228
+sat 32
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 8522,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 8523,0
+va (VaSet
+)
+xt "94000,110000,101200,111000"
+st "drs_address_mode"
+blo "94000,110800"
+tm "WireNameMgr"
+)
+)
+on &324
+)
+*450 (Wire
+uid 8577,0
+shape (OrthoPolyLine
+uid 8578,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "7000,57000,18250,57000"
+pts [
+"18250,57000"
+"7000,57000"
+]
+)
+start &39
+sat 32
+eat 16
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 8581,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 8582,0
+va (VaSet
+)
+xt "8000,56000,18400,57000"
+st "drs_channel_internal : (3:0)"
+blo "8000,56800"
+tm "WireNameMgr"
+)
+)
+on &346
+)
+*451 (Wire
+uid 8587,0
+shape (OrthoPolyLine
+uid 8588,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "-29000,101000,-20000,101000"
+pts [
+"-20000,101000"
+"-29000,101000"
+]
+)
+end &326
+sat 16
+eat 32
+sty 1
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 8591,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 8592,0
+va (VaSet
+)
+xt "-29000,100000,-20800,101000"
+st "drs_channel_internal"
+blo "-29000,100800"
+tm "WireNameMgr"
+)
+)
+on &346
+)
+*452 (Wire
+uid 8595,0
+shape (OrthoPolyLine
+uid 8596,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "-29000,99000,-20000,99000"
+pts [
+"-20000,99000"
+"-29000,99000"
+]
+)
+end &331
+sat 16
+eat 32
+sty 1
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 8599,0
+ps "ConnStartEndStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 8600,0
+va (VaSet
+)
+xt "-29000,98000,-24000,99000"
+st "drs_address"
+blo "-29000,98800"
+tm "WireNameMgr"
+)
+)
+on &323
+)
+*453 (Wire
+uid 8603,0
+shape (OrthoPolyLine
+uid 8604,0
+va (VaSet
+vasetType 3
+)
+xt "-31000,103000,-20000,107000"
+pts [
+"-20000,107000"
+"-31000,107000"
+"-31000,103000"
+]
+)
+end &333
+sat 16
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 8607,0
+ps "ConnStartEndStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 8608,0
+va (VaSet
+)
+xt "-29000,106000,-21800,107000"
+st "drs_address_mode"
+blo "-29000,106800"
+tm "WireNameMgr"
+)
+)
+on &324
+)
+]
 …
 color "26368,26368,26368"
+)
 packageList *422 (PackageList
+packageList *454 (PackageList
 uid 41,0
 stg "VerticalLayoutStrategy"
 textVec [
 *423 (Text
+*455 (Text
 uid 42,0
 va (VaSet
 …
 blo "-87000,1800"
+)
 *424 (MLText
+*456 (MLText
 uid 43,0
 va (VaSet
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *425 (Text
+*457 (Text
 uid 45,0
 va (VaSet
 …
 blo "20000,800"
+)
 *426 (Text
+*458 (Text
 uid 46,0
 va (VaSet
 …
 blo "20000,1800"
+)
 *427 (MLText
+*459 (MLText
 uid 47,0
 va (VaSet
 …
 tm "BdCompilerDirectivesTextMgr"
+)
 *428 (Text
+*460 (Text
 uid 48,0
 va (VaSet
 …
 blo "20000,4800"
+)
 *429 (MLText
+*461 (MLText
 uid 49,0
 va (VaSet
 …
 tm "BdCompilerDirectivesTextMgr"
+)
 *430 (Text
+*462 (Text
 uid 50,0
 va (VaSet
 …
 blo "20000,5800"
+)
 *431 (MLText
+*463 (MLText
 uid 51,0
 va (VaSet
 …
+)
 windowSize "0,0,1281,1024"
 viewArea "-62364,34906,23843,105999"
 cachedDiagramExtent "-87000,0,162300,301700"
+viewArea "-73966,37109,33461,125703"
+cachedDiagramExtent "-100999,0,162300,301700"
 pageSetupInfo (PageSetupInfo
 ptrCmd "eDocPrintPro,winspool,"
 …
 hasePageBreakOrigin 1
 pageBreakOrigin "-73000,0"
 lastUid 8460,0
+lastUid 8614,0
 defaultCommentText (CommentText
 shape (Rectangle
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *432 (Text
+*464 (Text
 va (VaSet
 font "Arial,8,1"
 …
 tm "BdLibraryNameMgr"
+)
 *433 (Text
+*465 (Text
 va (VaSet
 font "Arial,8,1"
 …
 tm "BlkNameMgr"
+)
 *434 (Text
+*466 (Text
 va (VaSet
 font "Arial,8,1"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *435 (Text
+*467 (Text
 va (VaSet
 font "Arial,8,1"
 …
 blo "550,4300"
+)
 *436 (Text
+*468 (Text
 va (VaSet
 font "Arial,8,1"
 …
 blo "550,5300"
+)
 *437 (Text
+*469 (Text
 va (VaSet
 font "Arial,8,1"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *438 (Text
+*470 (Text
 va (VaSet
 font "Arial,8,1"
 …
 tm "BdLibraryNameMgr"
+)
 *439 (Text
+*471 (Text
 va (VaSet
 font "Arial,8,1"
 …
 tm "CptNameMgr"
+)
 *440 (Text
+*472 (Text
 va (VaSet
 font "Arial,8,1"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *441 (Text
+*473 (Text
 va (VaSet
 font "Arial,8,1"
 …
 blo "500,4300"
+)
 *442 (Text
+*474 (Text
 va (VaSet
 font "Arial,8,1"
 …
 blo "500,5300"
+)
 *443 (Text
+*475 (Text
 va (VaSet
 font "Arial,8,1"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *444 (Text
+*476 (Text
 va (VaSet
 font "Arial,8,1"
 …
 blo "50,4300"
+)
 *445 (Text
+*477 (Text
 va (VaSet
 font "Arial,8,1"
 …
 blo "50,5300"
+)
 *446 (Text
+*478 (Text
 va (VaSet
 font "Arial,8,1"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *447 (Text
+*479 (Text
 va (VaSet
 font "Arial,8,1"
 …
 tm "HdlTextNameMgr"
+)
 *448 (Text
+*480 (Text
 va (VaSet
 font "Arial,8,1"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *449 (Text
+*481 (Text
 va (VaSet
 font "Arial,8,1"
 …
 blo "14100,20800"
+)
 *450 (MLText
+*482 (MLText
 va (VaSet
+)
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *451 (Text
+*483 (Text
 va (VaSet
 font "Arial,8,1"
 …
 blo "14100,20800"
+)
 *452 (MLText
+*484 (MLText
 va (VaSet
+)
 …
 font "Arial,8,1"
+)
 xt "-87000,85000,-82300,86000"
+xt "-87000,87400,-82300,88400"
 st "Post User:"
 blo "-87000,85800"
+blo "-87000,88200"
+)
 postUserText (MLText
 …
 commonDM (CommonDM
 ldm (LogicalDM
 suid 183,0
+suid 190,0
 usingSuid 1
 emptyRow *453 (LEmptyRow
+emptyRow *485 (LEmptyRow
+)
 uid 54,0
 optionalChildren [
 *454 (RefLabelRowHdr
+)
 *455 (TitleRowHdr
+)
 *456 (FilterRowHdr
+)
 *457 (RefLabelColHdr
+*486 (RefLabelRowHdr
+)
+*487 (TitleRowHdr
+)
+*488 (FilterRowHdr
+)
+*489 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
+)
 *458 (RowExpandColHdr
+*490 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
+)
 *459 (GroupColHdr
+*491 (GroupColHdr
 tm "GroupColHdrMgr"
+)
 *460 (NameColHdr
+*492 (NameColHdr
 tm "BlockDiagramNameColHdrMgr"
+)
 *461 (ModeColHdr
+*493 (ModeColHdr
 tm "BlockDiagramModeColHdrMgr"
+)
 *462 (TypeColHdr
+*494 (TypeColHdr
 tm "BlockDiagramTypeColHdrMgr"
+)
 *463 (BoundsColHdr
+*495 (BoundsColHdr
 tm "BlockDiagramBoundsColHdrMgr"
+)
 *464 (InitColHdr
+*496 (InitColHdr
 tm "BlockDiagramInitColHdrMgr"
+)
 *465 (EolColHdr
+*497 (EolColHdr
 tm "BlockDiagramEolColHdrMgr"
+)
 *466 (LeafLogPort
+*498 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 516,0
+)
 *467 (LeafLogPort
+*499 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 518,0
+)
 *468 (LeafLogPort
+*500 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 520,0
+)
 *469 (LeafLogPort
+*501 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 530,0
+)
 *470 (LeafLogPort
+*502 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 532,0
+)
 *471 (LeafLogPort
+*503 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 534,0
+)
 *472 (LeafLogPort
+*504 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 536,0
+)
 *473 (LeafLogPort
+*505 (LeafLogPort
 port (LogicalPort
 m 2
 …
 uid 538,0
+)
 *474 (LeafLogPort
+*506 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 540,0
+)
 *475 (LeafLogPort
+*507 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 542,0
+)
 *476 (LeafLogPort
+*508 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 546,0
+)
 *477 (LeafLogPort
+*509 (LeafLogPort
 port (LogicalPort
 decl (Decl
 …
 uid 548,0
+)
 *478 (LeafLogPort
+*510 (LeafLogPort
 port (LogicalPort
 decl (Decl
 …
 uid 1455,0
+)
 *479 (LeafLogPort
+*511 (LeafLogPort
 port (LogicalPort
 decl (Decl
 …
 uid 1457,0
+)
 *480 (LeafLogPort
+*512 (LeafLogPort
 port (LogicalPort
 decl (Decl
 …
 uid 1694,0
+)
 *481 (LeafLogPort
+*513 (LeafLogPort
 port (LogicalPort
 lang 2
 …
 uid 1993,0
+)
 *482 (LeafLogPort
+*514 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 2305,0
+)
 *483 (LeafLogPort
+*515 (LeafLogPort
 port (LogicalPort
 lang 2
 …
 uid 2510,0
+)
 *484 (LeafLogPort
+*516 (LeafLogPort
 port (LogicalPort
 lang 2
 …
 uid 2512,0
+)
 *485 (LeafLogPort
+*517 (LeafLogPort
 port (LogicalPort
 lang 2
 …
 uid 2514,0
+)
 *486 (LeafLogPort
+*518 (LeafLogPort
 port (LogicalPort
 lang 2
 …
 uid 2516,0
+)
 *487 (LeafLogPort
+*519 (LeafLogPort
 port (LogicalPort
 lang 2
 …
 uid 2518,0
+)
 *488 (LeafLogPort
+*520 (LeafLogPort
 port (LogicalPort
 lang 2
 …
 uid 2520,0
+)
 *489 (LeafLogPort
+*521 (LeafLogPort
 port (LogicalPort
 lang 2
 …
 uid 2522,0
+)
 *490 (LeafLogPort
+*522 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 2604,0
+)
 *491 (LeafLogPort
+*523 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 2606,0
+)
 *492 (LeafLogPort
+*524 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 2608,0
+)
 *493 (LeafLogPort
+*525 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 2610,0
+)
 *494 (LeafLogPort
+*526 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 2612,0
+)
 *495 (LeafLogPort
+*527 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 2646,0
+)
 *496 (LeafLogPort
+*528 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 2812,0
+)
 *497 (LeafLogPort
+*529 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 2962,0
+)
 *498 (LeafLogPort
+*530 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 3902,0
+)
 *499 (LeafLogPort
+*531 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 4070,0
+)
 *500 (LeafLogPort
+*532 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 4212,0
+)
 *501 (LeafLogPort
+*533 (LeafLogPort
 port (LogicalPort
 decl (Decl
 …
 uid 4234,0
+)
 *502 (LeafLogPort
+*534 (LeafLogPort
 port (LogicalPort
 decl (Decl
 …
 uid 4262,0
+)
 *503 (LeafLogPort
+*535 (LeafLogPort
 port (LogicalPort
 decl (Decl
 …
 uid 4276,0
+)
 *504 (LeafLogPort
+*536 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 4563,0
+)
 *505 (LeafLogPort
+*537 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 4565,0
+)
 *506 (LeafLogPort
+*538 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 4569,0
+)
 *507 (LeafLogPort
+*539 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 4585,0
+)
 *508 (LeafLogPort
+*540 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 4587,0
+)
 *509 (LeafLogPort
+*541 (LeafLogPort
 port (LogicalPort
 decl (Decl
 …
 uid 4733,0
+)
 *510 (LeafLogPort
+*542 (LeafLogPort
 port (LogicalPort
 decl (Decl
 …
 uid 4735,0
+)
 *511 (LeafLogPort
+*543 (LeafLogPort
 port (LogicalPort
 decl (Decl
 …
 uid 4737,0
+)
 *512 (LeafLogPort
+*544 (LeafLogPort
 port (LogicalPort
 decl (Decl
 …
 uid 4739,0
+)
 *513 (LeafLogPort
+*545 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 4749,0
+)
 *514 (LeafLogPort
+*546 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 4974,0
+)
 *515 (LeafLogPort
+*547 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 4976,0
+)
 *516 (LeafLogPort
+*548 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5198,0
+)
 *517 (LeafLogPort
+*549 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5200,0
+)
 *518 (LeafLogPort
+*550 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5202,0
+)
 *519 (LeafLogPort
+*551 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5204,0
+)
 *520 (LeafLogPort
+*552 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5206,0
+)
 *521 (LeafLogPort
+*553 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5208,0
+)
 *522 (LeafLogPort
+*554 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5210,0
+)
 *523 (LeafLogPort
+*555 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5212,0
+)
 *524 (LeafLogPort
+*556 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5214,0
+)
 *525 (LeafLogPort
+*557 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 5226,0
+)
 *526 (LeafLogPort
+*558 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5285,0
+)
 *527 (LeafLogPort
+*559 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5502,0
+)
 *528 (LeafLogPort
+*560 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5504,0
+)
 *529 (LeafLogPort
+*561 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5600,0
+)
 *530 (LeafLogPort
+*562 (LeafLogPort
 port (LogicalPort
 lang 10
 …
 uid 5642,0
+)
 *531 (LeafLogPort
+*563 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5644,0
+)
 *532 (LeafLogPort
+*564 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5751,0
+)
 *533 (LeafLogPort
+*565 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 5867,0
+)
 *534 (LeafLogPort
+*566 (LeafLogPort
 port (LogicalPort
 m 2
 …
 uid 5869,0
+)
 *535 (LeafLogPort
+*567 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 5871,0
+)
 *536 (LeafLogPort
+*568 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 5873,0
+)
 *537 (LeafLogPort
+*569 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5966,0
+)
 *538 (LeafLogPort
+*570 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 5968,0
+)
 *539 (LeafLogPort
+*571 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 6022,0
+)
 *540 (LeafLogPort
+*572 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 6024,0
+)
 *541 (LeafLogPort
+*573 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 6026,0
+)
 *542 (LeafLogPort
+*574 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 6172,0
+)
 *543 (LeafLogPort
+*575 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 6374,0
+)
 *544 (LeafLogPort
+*576 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 6464,0
+)
 *545 (LeafLogPort
+*577 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 6554,0
+)
 *546 (LeafLogPort
+*578 (LeafLogPort
 port (LogicalPort
 lang 2
 …
+)
 uid 8420,0
+)
+*579 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "drs_address"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 82
+suid 184,0
+i "(others => '0')"
+)
+)
+uid 8609,0
+)
+*580 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "drs_address_mode"
+t "std_logic"
+o 83
+suid 185,0
+)
+)
+uid 8611,0
+)
+*581 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "drs_channel_internal"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 84
+suid 187,0
+i "(others => '0')"
+)
+)
+uid 8613,0
+)
+]
 …
 uid 67,0
 optionalChildren [
 *547 (Sheet
+*582 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
 …
 font "Tahoma,10,0"
+)
 emptyMRCItem *548 (MRCItem
 litem &453
 pos 81
+emptyMRCItem *583 (MRCItem
+litem &485
+pos 84
 dimension 20
+)
 uid 69,0
 optionalChildren [
 *549 (MRCItem
 litem &454
+*584 (MRCItem
+litem &486
 pos 0
 dimension 20
 uid 70,0
+)
 *550 (MRCItem
 litem &455
+*585 (MRCItem
+litem &487
 pos 1
 dimension 23
 uid 71,0
+)
 *551 (MRCItem
 litem &456
+*586 (MRCItem
+litem &488
 pos 2
 hidden 1
 …
 uid 72,0
+)
 *552 (MRCItem
 litem &466
+*587 (MRCItem
+litem &498
 pos 31
 dimension 20
 uid 517,0
+)
 *553 (MRCItem
 litem &467
+*588 (MRCItem
+litem &499
 pos 32
 dimension 20
 uid 519,0
+)
 *554 (MRCItem
 litem &468
+*589 (MRCItem
+litem &500
 pos 33
 dimension 20
 uid 521,0
+)
 *555 (MRCItem
 litem &469
+*590 (MRCItem
+litem &501
 pos 34
 dimension 20
 uid 531,0
+)
 *556 (MRCItem
 litem &470
+*591 (MRCItem
+litem &502
 pos 35
 dimension 20
 uid 533,0
+)
 *557 (MRCItem
 litem &471
+*592 (MRCItem
+litem &503
 pos 0
 dimension 20
 uid 535,0
+)
 *558 (MRCItem
 litem &472
+*593 (MRCItem
+litem &504
 pos 1
 dimension 20
 uid 537,0
+)
 *559 (MRCItem
 litem &473
+*594 (MRCItem
+litem &505
 pos 2
 dimension 20
 uid 539,0
+)
 *560 (MRCItem
 litem &474
+*595 (MRCItem
+litem &506
 pos 3
 dimension 20
 uid 541,0
+)
 *561 (MRCItem
 litem &475
+*596 (MRCItem
+litem &507
 pos 4
 dimension 20
 uid 543,0
+)
 *562 (MRCItem
 litem &476
+*597 (MRCItem
+litem &508
 pos 5
 dimension 20
 uid 547,0
+)
 *563 (MRCItem
 litem &477
+*598 (MRCItem
+litem &509
 pos 6
 dimension 20
 uid 549,0
+)
 *564 (MRCItem
 litem &478
+*599 (MRCItem
+litem &510
 pos 8
 dimension 20
 uid 1456,0
+)
 *565 (MRCItem
 litem &479
+*600 (MRCItem
+litem &511
 pos 7
 dimension 20
 uid 1458,0
+)
 *566 (MRCItem
 litem &480
+*601 (MRCItem
+litem &512
 pos 9
 dimension 20
 uid 1695,0
+)
 *567 (MRCItem
 litem &481
+*602 (MRCItem
+litem &513
 pos 36
 dimension 20
 uid 1994,0
+)
 *568 (MRCItem
 litem &482
+*603 (MRCItem
+litem &514
 pos 37
 dimension 20
 uid 2306,0
+)
 *569 (MRCItem
 litem &483
+*604 (MRCItem
+litem &515
 pos 38
 dimension 20
 uid 2511,0
+)
 *570 (MRCItem
 litem &484
+*605 (MRCItem
+litem &516
 pos 39
 dimension 20
 uid 2513,0
+)
 *571 (MRCItem
 litem &485
+*606 (MRCItem
+litem &517
 pos 40
 dimension 20
 uid 2515,0
+)
 *572 (MRCItem
 litem &486
+*607 (MRCItem
+litem &518
 pos 41
 dimension 20
 uid 2517,0
+)
 *573 (MRCItem
 litem &487
+*608 (MRCItem
+litem &519
 pos 42
 dimension 20
 uid 2519,0
+)
 *574 (MRCItem
 litem &488
+*609 (MRCItem
+litem &520
 pos 43
 dimension 20
 uid 2521,0
+)
 *575 (MRCItem
 litem &489
+*610 (MRCItem
+litem &521
 pos 44
 dimension 20
 uid 2523,0
+)
 *576 (MRCItem
 litem &490
+*611 (MRCItem
+litem &522
 pos 45
 dimension 20
 uid 2605,0
+)
 *577 (MRCItem
 litem &491
+*612 (MRCItem
+litem &523
 pos 46
 dimension 20
 uid 2607,0
+)
 *578 (MRCItem
 litem &492
+*613 (MRCItem
+litem &524
 pos 47
 dimension 20
 uid 2609,0
+)
 *579 (MRCItem
 litem &493
+*614 (MRCItem
+litem &525
 pos 48
 dimension 20
 uid 2611,0
+)
 *580 (MRCItem
 litem &494
+*615 (MRCItem
+litem &526
 pos 49
 dimension 20
 uid 2613,0
+)
 *581 (MRCItem
 litem &495
+*616 (MRCItem
+litem &527
 pos 50
 dimension 20
 uid 2647,0
+)
 *582 (MRCItem
 litem &496
+*617 (MRCItem
+litem &528
 pos 10
 dimension 20
 uid 2813,0
+)
 *583 (MRCItem
 litem &497
+*618 (MRCItem
+litem &529
 pos 51
 dimension 20
 uid 2963,0
+)
 *584 (MRCItem
 litem &498
+*619 (MRCItem
+litem &530
 pos 11
 dimension 20
 uid 3903,0
+)
 *585 (MRCItem
 litem &499
+*620 (MRCItem
+litem &531
 pos 12
 dimension 20
 uid 4071,0
+)
 *586 (MRCItem
 litem &500
+*621 (MRCItem
+litem &532
 pos 52
 dimension 20
 uid 4213,0
+)
 *587 (MRCItem
 litem &501
+*622 (MRCItem
+litem &533
 pos 13
 dimension 20
 uid 4235,0
+)
 *588 (MRCItem
 litem &502
+*623 (MRCItem
+litem &534
 pos 14
 dimension 20
 uid 4263,0
+)
 *589 (MRCItem
 litem &503
+*624 (MRCItem
+litem &535
 pos 15
 dimension 20
 uid 4277,0
+)
 *590 (MRCItem
 litem &504
+*625 (MRCItem
+litem &536
 pos 53
 dimension 20
 uid 4564,0
+)
 *591 (MRCItem
 litem &505
+*626 (MRCItem
+litem &537
 pos 54
 dimension 20
 uid 4566,0
+)
 *592 (MRCItem
 litem &506
+*627 (MRCItem
+litem &538
 pos 55
 dimension 20
 uid 4570,0
+)
 *593 (MRCItem
 litem &507
+*628 (MRCItem
+litem &539
 pos 16
 dimension 20
 uid 4586,0
+)
 *594 (MRCItem
 litem &508
+*629 (MRCItem
+litem &540
 pos 17
 dimension 20
 uid 4588,0
+)
 *595 (MRCItem
 litem &509
+*630 (MRCItem
+litem &541
 pos 18
 dimension 20
 uid 4734,0
+)
 *596 (MRCItem
 litem &510
+*631 (MRCItem
+litem &542
 pos 19
 dimension 20
 uid 4736,0
+)
 *597 (MRCItem
 litem &511
+*632 (MRCItem
+litem &543
 pos 20
 dimension 20
 uid 4738,0
+)
 *598 (MRCItem
 litem &512
+*633 (MRCItem
+litem &544
 pos 21
 dimension 20
 uid 4740,0
+)
 *599 (MRCItem
 litem &513
+*634 (MRCItem
+litem &545
 pos 56
 dimension 20
 uid 4750,0
+)
 *600 (MRCItem
 litem &514
+*635 (MRCItem
+litem &546
 pos 22
 dimension 20
 uid 4975,0
+)
 *601 (MRCItem
 litem &515
+*636 (MRCItem
+litem &547
 pos 23
 dimension 20
 uid 4977,0
+)
 *602 (MRCItem
 litem &516
+*637 (MRCItem
+litem &548
 pos 57
 dimension 20
 uid 5199,0
+)
 *603 (MRCItem
 litem &517
+*638 (MRCItem
+litem &549
 pos 58
 dimension 20
 uid 5201,0
+)
 *604 (MRCItem
 litem &518
+*639 (MRCItem
+litem &550
 pos 59
 dimension 20
 uid 5203,0
+)
 *605 (MRCItem
 litem &519
+*640 (MRCItem
+litem &551
 pos 60
 dimension 20
 uid 5205,0
+)
 *606 (MRCItem
 litem &520
+*641 (MRCItem
+litem &552
 pos 61
 dimension 20
 uid 5207,0
+)
 *607 (MRCItem
 litem &521
+*642 (MRCItem
+litem &553
 pos 62
 dimension 20
 uid 5209,0
+)
 *608 (MRCItem
 litem &522
+*643 (MRCItem
+litem &554
 pos 63
 dimension 20
 uid 5211,0
+)
 *609 (MRCItem
 litem &523
+*644 (MRCItem
+litem &555
 pos 64
 dimension 20
 uid 5213,0
+)
 *610 (MRCItem
 litem &524
+*645 (MRCItem
+litem &556
 pos 65
 dimension 20
 uid 5215,0
+)
 *611 (MRCItem
 litem &525
+*646 (MRCItem
+litem &557
 pos 24
 dimension 20
 uid 5227,0
+)
 *612 (MRCItem
 litem &526
+*647 (MRCItem
+litem &558
 pos 66
 dimension 20
 uid 5286,0
+)
 *613 (MRCItem
 litem &527
+*648 (MRCItem
+litem &559
 pos 67
 dimension 20
 uid 5503,0
+)
 *614 (MRCItem
 litem &528
+*649 (MRCItem
+litem &560
 pos 68
 dimension 20
 uid 5505,0
+)
 *615 (MRCItem
 litem &529
+*650 (MRCItem
+litem &561
 pos 69
 dimension 20
 uid 5601,0
+)
 *616 (MRCItem
 litem &530
+*651 (MRCItem
+litem &562
 pos 70
 dimension 20
 uid 5643,0
+)
 *617 (MRCItem
 litem &531
+*652 (MRCItem
+litem &563
 pos 71
 dimension 20
 uid 5645,0
+)
 *618 (MRCItem
 litem &532
+*653 (MRCItem
+litem &564
 pos 72
 dimension 20
 uid 5752,0
+)
 *619 (MRCItem
 litem &533
+*654 (MRCItem
+litem &565
 pos 25
 dimension 20
 uid 5868,0
+)
 *620 (MRCItem
 litem &534
+*655 (MRCItem
+litem &566
 pos 26
 dimension 20
 uid 5870,0
+)
 *621 (MRCItem
 litem &535
+*656 (MRCItem
+litem &567
 pos 27
 dimension 20
 uid 5872,0
+)
 *622 (MRCItem
 litem &536
+*657 (MRCItem
+litem &568
 pos 28
 dimension 20
 uid 5874,0
+)
 *623 (MRCItem
 litem &537
+*658 (MRCItem
+litem &569
 pos 73
 dimension 20
 uid 5967,0
+)
 *624 (MRCItem
 litem &538
+*659 (MRCItem
+litem &570
 pos 74
 dimension 20
 uid 5969,0
+)
 *625 (MRCItem
 litem &539
+*660 (MRCItem
+litem &571
 pos 75
 dimension 20
 uid 6023,0
+)
 *626 (MRCItem
 litem &540
+*661 (MRCItem
+litem &572
 pos 76
 dimension 20
 uid 6025,0
+)
 *627 (MRCItem
 litem &541
+*662 (MRCItem
+litem &573
 pos 77
 dimension 20
 uid 6027,0
+)
 *628 (MRCItem
 litem &542
+*663 (MRCItem
+litem &574
 pos 29
 dimension 20
 uid 6173,0
+)
 *629 (MRCItem
 litem &543
+*664 (MRCItem
+litem &575
 pos 30
 dimension 20
 uid 6375,0
+)
 *630 (MRCItem
 litem &544
+*665 (MRCItem
+litem &576
 pos 78
 dimension 20
 uid 6465,0
+)
 *631 (MRCItem
 litem &545
+*666 (MRCItem
+litem &577
 pos 79
 dimension 20
 uid 6555,0
+)
 *632 (MRCItem
 litem &546
+*667 (MRCItem
+litem &578
 pos 80
 dimension 20
 uid 8421,0
+)
+*668 (MRCItem
+litem &579
+pos 81
+dimension 20
+uid 8610,0
+)
+*669 (MRCItem
+litem &580
+pos 82
+dimension 20
+uid 8612,0
+)
+*670 (MRCItem
+litem &581
+pos 83
+dimension 20
+uid 8614,0
+)
+]
 …
 uid 73,0
 optionalChildren [
 *633 (MRCItem
 litem &457
+*671 (MRCItem
+litem &489
 pos 0
 dimension 20
 uid 74,0
+)
 *634 (MRCItem
 litem &459
+*672 (MRCItem
+litem &491
 pos 1
 dimension 50
 uid 75,0
+)
 *635 (MRCItem
 litem &460
+*673 (MRCItem
+litem &492
 pos 2
 dimension 100
 uid 76,0
+)
 *636 (MRCItem
 litem &461
+*674 (MRCItem
+litem &493
 pos 3
 dimension 50
 uid 77,0
+)
 *637 (MRCItem
 litem &462
+*675 (MRCItem
+litem &494
 pos 4
 dimension 100
 uid 78,0
+)
 *638 (MRCItem
 litem &463
+*676 (MRCItem
+litem &495
 pos 5
 dimension 100
 uid 79,0
+)
 *639 (MRCItem
 litem &464
+*677 (MRCItem
+litem &496
 pos 6
 dimension 50
 uid 80,0
+)
 *640 (MRCItem
 litem &465
+*678 (MRCItem
+litem &497
 pos 7
 dimension 80
 …
 genericsCommonDM (CommonDM
 ldm (LogicalDM
 emptyRow *641 (LEmptyRow
+emptyRow *679 (LEmptyRow
+)
 uid 83,0
 optionalChildren [
 *642 (RefLabelRowHdr
+)
 *643 (TitleRowHdr
+)
 *644 (FilterRowHdr
+)
 *645 (RefLabelColHdr
+*680 (RefLabelRowHdr
+)
+*681 (TitleRowHdr
+)
+*682 (FilterRowHdr
+)
+*683 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
+)
 *646 (RowExpandColHdr
+*684 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
+)
 *647 (GroupColHdr
+*685 (GroupColHdr
 tm "GroupColHdrMgr"
+)
 *648 (NameColHdr
+*686 (NameColHdr
 tm "GenericNameColHdrMgr"
+)
 *649 (TypeColHdr
+*687 (TypeColHdr
 tm "GenericTypeColHdrMgr"
+)
 *650 (InitColHdr
+*688 (InitColHdr
 tm "GenericValueColHdrMgr"
+)
 *651 (PragmaColHdr
+*689 (PragmaColHdr
 tm "GenericPragmaColHdrMgr"
+)
 *652 (EolColHdr
+*690 (EolColHdr
 tm "GenericEolColHdrMgr"
+)
 *653 (LogGeneric
+*691 (LogGeneric
 generic (GiElement
 name "RAMADDRWIDTH64b"
 …
 uid 95,0
 optionalChildren [
 *654 (Sheet
+*692 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
 …
 font "Tahoma,10,0"
+)
 emptyMRCItem *655 (MRCItem
 litem &641
+emptyMRCItem *693 (MRCItem
+litem &679
 pos 1
 dimension 20
 …
 uid 97,0
 optionalChildren [
 *656 (MRCItem
 litem &642
+*694 (MRCItem
+litem &680
 pos 0
 dimension 20
 uid 98,0
+)
 *657 (MRCItem
 litem &643
+*695 (MRCItem
+litem &681
 pos 1
 dimension 23
 uid 99,0
+)
 *658 (MRCItem
 litem &644
+*696 (MRCItem
+litem &682
 pos 2
 hidden 1
 …
 uid 100,0
+)
 *659 (MRCItem
 litem &653
+*697 (MRCItem
+litem &691
 pos 0
 dimension 20
 …
 uid 101,0
 optionalChildren [
 *660 (MRCItem
 litem &645
+*698 (MRCItem
+litem &683
 pos 0
 dimension 20
 uid 102,0
+)
 *661 (MRCItem
 litem &647
+*699 (MRCItem
+litem &685
 pos 1
 dimension 50
 uid 103,0
+)
 *662 (MRCItem
 litem &648
+*700 (MRCItem
+litem &686
 pos 2
 dimension 186
 uid 104,0
+)
 *663 (MRCItem
 litem &649
+*701 (MRCItem
+litem &687
 pos 3
 dimension 96
 uid 105,0
+)
 *664 (MRCItem
 litem &650
+*702 (MRCItem
+litem &688
 pos 4
 dimension 50
 uid 106,0
+)
 *665 (MRCItem
 litem &651
+*703 (MRCItem
+litem &689
 pos 5
 dimension 50
 uid 107,0
+)
 *666 (MRCItem
 litem &652
+*704 (MRCItem
+litem &690
 pos 6
 dimension 80

FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak

-              r246
+              r252
 (vvPair
 variable "HDLDir"
 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hdl"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
+)
 (vvPair
 variable "HDSDir"
 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
+)
 (vvPair
 variable "SideDataDesignDir"
 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info"
+)
 (vvPair
 variable "SideDataUserDir"
 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user"
+)
 (vvPair
 variable "SourceDir"
 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
+)
 (vvPair
 …
 (vvPair
 variable "d"
 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main"
+)
 (vvPair
 variable "d_logical"
 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main"
+)
 (vvPair
 variable "date"
 value "02.07.2010"
+value "12.07.2010"
+)
 (vvPair
 variable "day"
 value "Fr"
+value "Mo"
+)
 (vvPair
 variable "day_long"
 value "Freitag"
+value "Montag"
+)
 (vvPair
 variable "dd"
 value "02"
+value "12"
+)
 (vvPair
 …
 (vvPair
 variable "p"
 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd"
+)
 (vvPair
 variable "p_logical"
 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd"
+)
 (vvPair
 …
 (vvPair
 variable "time"
 value "10:38:34"
+value "11:42:03"
+)
 (vvPair
 …
 va (VaSet
+)
 xt "-25000,74000,-20500,75000"
+xt "-25000,73000,-20500,74000"
 st "CLK_25_PS"
 blo "-25000,74800"
+blo "-25000,73800"
 tm "WireNameMgr"
+)
 …
 vasetType 3
+)
 xt "-23000,63000,-18750,63000"
+xt "-27000,63000,-18750,63000"
 pts [
 "-23000,63000"
+"-27000,63000"
 "-18750,63000"
+]
 …
 va (VaSet
+)
 xt "-22000,62000,-17500,63000"
+xt "-24000,62000,-19500,63000"
 st "CLK_25_PS"
 blo "-22000,62800"
+blo "-24000,62800"
 tm "WireNameMgr"
+)
 …
+)
 windowSize "0,0,1281,1024"
 viewArea "63050,40700,132015,97575"
+viewArea "-62364,34906,23843,105999"
 cachedDiagramExtent "-87000,0,162300,301700"
 pageSetupInfo (PageSetupInfo
 …
 hasePageBreakOrigin 1
 pageBreakOrigin "-73000,0"
 lastUid 8421,0
+lastUid 8460,0
 defaultCommentText (CommentText
 shape (Rectangle

Note: See TracChangeset for help on using the changeset viewer.

Context Navigation

Changeset 252 for FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main

Legend:

FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd

FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak

Download in other formats: