Changeset 252 for FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit

FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd

-              r246
+              r252
+)
 version "29.1"
 appVersion "2009.1 (Build 12)"
+appVersion "2009.2 (Build 10)"
 noEmbeddedEditors 1
 model (BlockDiag
 …
 (vvPair
 variable "HDLDir"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hdl"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
+)
 (vvPair
 variable "HDSDir"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
+)
 (vvPair
 variable "SideDataDesignDir"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info"
+)
 (vvPair
 variable "SideDataUserDir"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user"
+)
 (vvPair
 variable "SourceDir"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
+)
 (vvPair
 …
 (vvPair
 variable "d"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
+)
 (vvPair
 variable "d_logical"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
+)
 (vvPair
 variable "date"
 value "27.05.2010"
+value "12.07.2010"
+)
 (vvPair
 variable "day"
 value "Do"
+value "Mo"
+)
 (vvPair
 variable "day_long"
 value "Donnerstag"
+value "Montag"
+)
 (vvPair
 variable "dd"
 value "27"
+value "12"
+)
 (vvPair
 …
 (vvPair
 variable "host"
 value "IHP110"
+value "TU-CC4900F8C7D2"
+)
 (vvPair
 …
 (vvPair
 variable "mm"
 value "05"
+value "07"
+)
 (vvPair
 …
 (vvPair
 variable "month"
 value "Mai"
+value "Jul"
+)
 (vvPair
 variable "month_long"
 value "Mai"
+value "Juli"
+)
 (vvPair
 variable "p"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
+)
 (vvPair
 variable "p_logical"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
+)
 (vvPair
 …
 (vvPair
 variable "task_ModelSimPath"
 value "D:\\modeltech_6.5e\\win32"
+value "<TBD>"
+)
 (vvPair
 …
 (vvPair
 variable "time"
 value "10:24:05"
+value "14:13:34"
+)
 (vvPair
 …
 (vvPair
 variable "user"
 value "daqct3"
+value "dneise"
+)
 (vvPair
 variable "version"
 value "2009.1 (Build 12)"
+value "2009.2 (Build 10)"
+)
 (vvPair
 …
 bg "0,0,32768"
+)
 xt "16200,76000,25900,77000"
+xt "16200,76000,25500,77000"
 st "
 by %user on %dd %month %year
 …
 font "Courier New,8,0"
+)
+xt "22000,2000,38000,2800"
+st "clk               : STD_LOGIC"
+xt "29000,2200,45000,3000"
+st "clk               : STD_LOGIC
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "22000,15000,51500,15800"
+st "SIGNAL ram_wren          : std_logic_VECTOR(0 DOWNTO 0)"
+xt "29000,16800,58500,17600"
+st "SIGNAL ram_wren          : std_logic_VECTOR(0 DOWNTO 0)
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "22000,2800,48000,3600"
+st "config_addr       : std_logic_vector(7 DOWNTO 0)"
+xt "29000,3000,55000,3800"
+st "config_addr       : std_logic_vector(7 DOWNTO 0)
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "22000,13400,52000,14200"
+st "SIGNAL ram_data_in       : std_logic_VECTOR(15 DOWNTO 0)"
+xt "29000,15200,59000,16000"
+st "SIGNAL ram_data_in       : std_logic_VECTOR(15 DOWNTO 0)
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "22000,6800,38000,7600"
+st "config_data_valid : std_logic"
+xt "29000,7000,45000,7800"
+st "config_data_valid : std_logic
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "22000,6000,38000,6800"
+st "config_busy       : std_logic"
+xt "29000,6200,45000,7000"
+st "config_busy       : std_logic
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "22000,10800,48500,11600"
+st "config_data       : std_logic_vector(15 DOWNTO 0)"
+xt "29000,12600,55500,13400"
+st "config_data       : std_logic_vector(15 DOWNTO 0)
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "22000,10000,40500,10800"
+st "roi_array         : roi_array_type"
+xt "29000,11800,47500,12600"
+st "roi_array         : roi_array_type
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "22000,12600,51500,13400"
+st "SIGNAL ram_addr          : std_logic_VECTOR(7 DOWNTO 0)"
+xt "29000,14400,58500,15200"
+st "SIGNAL ram_addr          : std_logic_VECTOR(7 DOWNTO 0)
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "22000,5200,38000,6000"
+st "config_wr_en      : std_logic"
+xt "29000,5400,45000,6200"
+st "config_wr_en      : std_logic
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "22000,14200,52000,15000"
+st "SIGNAL ram_data_out      : std_logic_VECTOR(15 DOWNTO 0)"
+xt "29000,16000,59000,16800"
+st "SIGNAL ram_data_out      : std_logic_VECTOR(15 DOWNTO 0)
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "22000,9200,40500,10000"
+st "dac_array         : dac_array_type"
+xt "29000,9400,47500,10200"
+st "dac_array         : dac_array_type
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "22000,3600,38000,4400"
+st "config_rd_en      : std_logic"
+xt "29000,3800,45000,4600"
+st "config_rd_en      : std_logic
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "22000,4400,38000,5200"
+st "config_start      : std_logic"
+xt "29000,4600,45000,5400"
+st "config_start      : std_logic
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "22000,7600,38000,8400"
+st "config_ready      : std_logic"
+xt "29000,7800,45000,8600"
+st "config_ready      : std_logic
+"
+)
+)
 …
 sl 0
 ro 270
 xt "3000,23625,4500,24375"
+xt "2000,19625,3500,20375"
+)
 (Line
 …
 sl 0
 ro 270
 xt "4500,24000,5000,24000"
+xt "3500,20000,4000,20000"
 pts [
 "4500,24000"
 "5000,24000"
+"3500,20000"
+"4000,20000"
+]
+)
 …
 va (VaSet
+)
 xt "700,23500,2000,24500"
+xt "700,19500,2000,20500"
 st "clk"
 ju 2
 blo "2000,24300"
+blo "2000,20300"
 tm "WireNameMgr"
+)
 …
 sl 0
 ro 270
 xt "42500,28625,44000,29375"
+xt "36500,28625,38000,29375"
+)
 (Line
 …
 sl 0
 ro 270
 xt "42000,29000,42500,29000"
+xt "36000,29000,36500,29000"
 pts [
 "42000,29000"
 "42500,29000"
+"36000,29000"
+"36500,29000"
+]
+)
 …
 va (VaSet
+)
 xt "45000,28500,50100,29500"
+xt "39000,28500,44100,29500"
 st "config_ready"
 blo "45000,29300"
+blo "39000,29300"
 tm "WireNameMgr"
+)
 …
 sl 0
 ro 90
 xt "42500,29625,44000,30375"
+xt "36500,29625,38000,30375"
+)
 (Line
 …
 sl 0
 ro 90
 xt "42000,30000,42500,30000"
+xt "36000,30000,36500,30000"
 pts [
 "42500,30000"
 "42000,30000"
+"36500,30000"
+"36000,30000"
+]
+)
 …
 va (VaSet
+)
 xt "45000,29500,49800,30500"
+xt "39000,29500,43800,30500"
 st "config_start"
 blo "45000,30300"
+blo "39000,30300"
 tm "WireNameMgr"
+)
 …
 uid 381,0
 sl 0
 xt "42500,24625,44000,25375"
+xt "36500,24625,38000,25375"
+)
 (Line
 uid 382,0
 sl 0
 xt "42000,25000,42500,25000"
+xt "36000,25000,36500,25000"
 pts [
 "42000,25000"
 "42500,25000"
+"36000,25000"
+"36500,25000"
+]
+)
 …
 va (VaSet
+)
 xt "45000,24500,49700,25500"
+xt "39000,24500,43700,25500"
 st "config_data"
 blo "45000,25300"
+blo "39000,25300"
 tm "WireNameMgr"
+)
 …
 sl 0
 ro 90
 xt "42500,23625,44000,24375"
+xt "36500,23625,38000,24375"
+)
 (Line
 …
 sl 0
 ro 90
 xt "42000,24000,42500,24000"
+xt "36000,24000,36500,24000"
 pts [
 "42500,24000"
 "42000,24000"
+"36500,24000"
+"36000,24000"
+]
+)
 …
 va (VaSet
+)
 xt "45000,23500,49800,24500"
+xt "39000,23500,43800,24500"
 st "config_addr"
 blo "45000,24300"
+blo "39000,24300"
 tm "WireNameMgr"
+)
 …
 sl 0
 ro 90
 xt "42500,26625,44000,27375"
+xt "36500,26625,38000,27375"
+)
 (Line
 …
 sl 0
 ro 90
 xt "42000,27000,42500,27000"
+xt "36000,27000,36500,27000"
 pts [
 "42500,27000"
 "42000,27000"
+"36500,27000"
+"36000,27000"
+]
+)
 …
 va (VaSet
+)
 xt "45000,26500,50300,27500"
+xt "39000,26500,44300,27500"
 st "config_wr_en"
 blo "45000,27300"
+blo "39000,27300"
 tm "WireNameMgr"
+)
 …
 sl 0
 ro 90
 xt "42500,27625,44000,28375"
+xt "36500,27625,38000,28375"
+)
 (Line
 …
 sl 0
 ro 90
 xt "42000,28000,42500,28000"
+xt "36000,28000,36500,28000"
 pts [
 "42500,28000"
 "42000,28000"
+"36500,28000"
+"36000,28000"
+]
+)
 …
 va (VaSet
+)
 xt "45000,27500,50200,28500"
+xt "39000,27500,44200,28500"
 st "config_rd_en"
 blo "45000,28300"
+blo "39000,28300"
 tm "WireNameMgr"
+)
 …
 sl 0
 ro 270
 xt "42500,33625,44000,34375"
+xt "36500,33625,38000,34375"
+)
 (Line
 …
 sl 0
 ro 270
 xt "42000,34000,42500,34000"
+xt "36000,34000,36500,34000"
 pts [
 "42000,34000"
 "42500,34000"
+"36000,34000"
+"36500,34000"
+]
+)
 …
 va (VaSet
+)
 xt "45000,33500,48700,34500"
+xt "39000,33500,42700,34500"
 st "dac_array"
 blo "45000,34300"
+blo "39000,34300"
 tm "WireNameMgr"
+)
 …
 sl 0
 ro 270
 xt "42500,34625,44000,35375"
+xt "36500,34625,38000,35375"
+)
 (Line
 …
 sl 0
 ro 270
 xt "42000,35000,42500,35000"
+xt "36000,35000,36500,35000"
 pts [
 "42000,35000"
 "42500,35000"
+"36000,35000"
+"36500,35000"
+]
+)
 …
 va (VaSet
+)
 xt "45000,34500,48400,35500"
+xt "39000,34500,42400,35500"
 st "roi_array"
 blo "45000,35300"
+blo "39000,35300"
 tm "WireNameMgr"
+)
 …
 sl 0
 ro 270
 xt "42500,31625,44000,32375"
+xt "36500,31625,38000,32375"
+)
 (Line
 …
 sl 0
 ro 270
 xt "42000,32000,42500,32000"
+xt "36000,32000,36500,32000"
 pts [
 "42000,32000"
 "42500,32000"
+"36000,32000"
+"36500,32000"
+]
+)
 …
 va (VaSet
+)
 xt "45000,31500,51600,32500"
+xt "39000,31500,45600,32500"
 st "config_data_valid"
 blo "45000,32300"
+blo "39000,32300"
 tm "WireNameMgr"
+)
 …
 sl 0
 ro 270
 xt "42500,32625,44000,33375"
+xt "36500,32625,38000,33375"
+)
 (Line
 …
 sl 0
 ro 270
 xt "42000,33000,42500,33000"
+xt "36000,33000,36500,33000"
 pts [
 "42000,33000"
 "42500,33000"
+"36000,33000"
+"36500,33000"
+]
+)
 …
 va (VaSet
+)
 xt "45000,32500,49800,33500"
+xt "39000,32500,43800,33500"
 st "config_busy"
 blo "45000,33300"
+blo "39000,33300"
 tm "WireNameMgr"
+)
 …
 fg "0,65535,0"
+)
 xt "12250,23625,13000,24375"
+xt "6250,23625,7000,24375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "14000,23500,15300,24500"
+xt "8000,23500,9300,24500"
 st "clk"
 blo "14000,24300"
+blo "8000,24300"
+)
+)
 …
 fg "0,65535,0"
+)
 xt "38000,28625,38750,29375"
+xt "32000,28625,32750,29375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "31900,28500,37000,29500"
+xt "25900,28500,31000,29500"
 st "config_ready"
 ju 2
 blo "37000,29300"
+blo "31000,29300"
+)
+)
 …
 fg "0,65535,0"
+)
 xt "38000,29625,38750,30375"
+xt "32000,29625,32750,30375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "32200,29500,37000,30500"
+xt "26200,29500,31000,30500"
 st "config_start"
 ju 2
 blo "37000,30300"
+blo "31000,30300"
+)
+)
 …
 fg "0,65535,0"
+)
 xt "38000,24625,38750,25375"
+xt "32000,24625,32750,25375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "29300,24500,37000,25500"
+xt "23300,24500,31000,25500"
 st "config_data : (15:0)"
 ju 2
 blo "37000,25300"
+blo "31000,25300"
+)
+)
 …
 fg "0,65535,0"
+)
 xt "38000,23625,38750,24375"
+xt "32000,23625,32750,24375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "23600,23500,37000,24500"
+xt "17600,23500,31000,24500"
 st "config_addr : (ADDR_WIDTH - 1:0)"
 ju 2
 blo "37000,24300"
+blo "31000,24300"
+)
+)
 …
 fg "0,65535,0"
+)
 xt "38000,26625,38750,27375"
+xt "32000,26625,32750,27375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "31700,26500,37000,27500"
+xt "25700,26500,31000,27500"
 st "config_wr_en"
 ju 2
 blo "37000,27300"
+blo "31000,27300"
+)
+)
 …
 fg "0,65535,0"
+)
 xt "38000,27625,38750,28375"
+xt "32000,27625,32750,28375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "31800,27500,37000,28500"
+xt "25800,27500,31000,28500"
 st "config_rd_en"
 ju 2
 blo "37000,28300"
+blo "31000,28300"
+)
+)
 …
 fg "0,65535,0"
+)
 xt "38000,31625,38750,32375"
+xt "32000,31625,32750,32375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "30400,31500,37000,32500"
+xt "24400,31500,31000,32500"
 st "config_data_valid"
 ju 2
 blo "37000,32300"
+blo "31000,32300"
+)
+)
 …
 fg "0,65535,0"
+)
 xt "38000,32625,38750,33375"
+xt "32000,32625,32750,33375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "32200,32500,37000,33500"
+xt "26200,32500,31000,33500"
 st "config_busy"
 ju 2
 blo "37000,33300"
+blo "31000,33300"
+)
+)
 …
 fg "0,65535,0"
+)
 xt "38000,33625,38750,34375"
+xt "32000,33625,32750,34375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "33300,33500,37000,34500"
+xt "27300,33500,31000,34500"
 st "dac_array"
 ju 2
 blo "37000,34300"
+blo "31000,34300"
+)
+)
 …
 fg "0,65535,0"
+)
 xt "38000,34625,38750,35375"
+xt "32000,34625,32750,35375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "33600,34500,37000,35500"
+xt "27600,34500,31000,35500"
 st "roi_array"
 ju 2
 blo "37000,35300"
+blo "31000,35300"
+)
+)
 …
 fg "0,65535,0"
+)
 xt "38000,37625,38750,38375"
+xt "32000,37625,32750,38375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "29100,37500,37000,38500"
+xt "23100,37500,31000,38500"
 st "ram_data_in : (15:0)"
 ju 2
 blo "37000,38300"
+blo "31000,38300"
+)
+)
 …
 fg "0,65535,0"
+)
 xt "38000,38625,38750,39375"
+xt "32000,38625,32750,39375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "29100,38500,37000,39500"
+xt "23100,38500,31000,39500"
 st "ram_write_en : (0:0)"
 ju 2
 blo "37000,39300"
+blo "31000,39300"
+)
+)
 …
 fg "0,65535,0"
+)
 xt "12250,24625,13000,25375"
+xt "6250,38625,7000,39375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "14000,24500,22300,25500"
+xt "8000,38500,16300,39500"
 st "ram_data_out : (15:0)"
 blo "14000,25300"
+blo "8000,39300"
+)
+)
 …
 fg "0,65535,0"
+)
 xt "38000,39625,38750,40375"
+xt "32000,39625,32750,40375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "24400,39500,37000,40500"
+xt "18400,39500,31000,40500"
 st "ram_addr : (ADDR_WIDTH - 1:0)"
 ju 2
 blo "37000,40300"
+blo "31000,40300"
+)
+)
 …
 fg "0,65535,0"
+)
 xt "38000,30625,38750,31375"
+xt "32000,30625,32750,31375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "31400,30500,37000,31500"
+xt "25400,30500,31000,31500"
 st "config_started"
 ju 2
 blo "37000,31300"
+blo "31000,31300"
+)
+)
 …
+)
+)
+*55 (CptPort
+uid 1198,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1199,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "32000,21625,32750,22375"
+)
+tg (CPTG
+uid 1200,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1201,0
+va (VaSet
+)
+xt "23800,21500,31000,22500"
+st "drs_address : (3:0)"
+ju 2
+blo "31000,22300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_address"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 17
+suid 24,0
+)
+)
+)
+*56 (CptPort
+uid 1202,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1203,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "32000,20625,32750,21375"
+)
+tg (CPTG
+uid 1204,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1205,0
+va (VaSet
+)
+xt "23800,20500,31000,21500"
+st "drs_address_mode"
+ju 2
+blo "31000,21300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_address_mode"
+t "std_logic"
+o 18
+suid 25,0
+)
+)
+)
+]
 shape (Rectangle
 …
 lineWidth 2
+)
 xt "13000,23000,38000,42000"
+xt "7000,20000,32000,41000"
+)
 oxt "42000,14000,67000,32000"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *55 (Text
+*57 (Text
 uid 963,0
 va (VaSet
 font "Arial,8,1"
+)
 xt "12950,42000,19150,43000"
+xt "6950,42000,13150,43000"
 st "FACT_FAD_lib"
 blo "12950,42800"
+blo "6950,42800"
 tm "BdLibraryNameMgr"
+)
 *56 (Text
+*58 (Text
 uid 964,0
 va (VaSet
 font "Arial,8,1"
+)
 xt "12950,43000,20050,44000"
+xt "6950,43000,14050,44000"
 st "control_manager"
 blo "12950,43800"
+blo "6950,43800"
 tm "CptNameMgr"
+)
 *57 (Text
+*59 (Text
 uid 965,0
 va (VaSet
 font "Arial,8,1"
+)
 xt "12950,44000,20650,45000"
+xt "6950,44000,14650,45000"
 st "I_control_manager"
 blo "12950,44800"
+blo "6950,44800"
 tm "InstanceNameMgr"
+)
 …
 font "Courier New,8,0"
+)
 xt "12500,10600,30000,13000"
+xt "10000,17600,27500,20000"
 st "NO_OF_ROI  = 36    ( integer )
 NO_OF_DAC  = 8     ( integer )
 …
 fg "49152,49152,49152"
+)
 xt "13250,40250,14750,41750"
+xt "7250,39250,8750,40750"
 iconName "VhdlFileViewIcon.png"
 iconMaskName "VhdlFileViewIcon.msk"
 …
 archFileType "UNKNOWN"
+)
 *58 (SaComponent
+*60 (SaComponent
 uid 993,0
 optionalChildren [
 *59 (CptPort
+*61 (CptPort
 uid 970,0
 ps "OnEdgeStrategy"
 shape (Triangle
 uid 971,0
 ro 90
+ro 180
 va (VaSet
 vasetType 1
 fg "0,65535,0"
+)
 xt "19250,50625,20000,51375"
+xt "42625,41250,43375,42000"
+)
 tg (CPTG
 uid 972,0
 ps "CptPortTextPlaceStrategy"
 stg "VerticalLayoutStrategy"
+stg "RightVerticalLayoutStrategy"
 f (Text
 uid 973,0
+va (VaSet
+)
+xt "21000,50500,22700,51500"
+ro 270
+va (VaSet
+)
+xt "42500,43000,43500,44700"
 st "clka"
+blo "21000,51300"
+ju 2
+blo "43300,43000"
+)
+)
 …
+)
+)
 *60 (CptPort
+*62 (CptPort
 uid 974,0
 ps "OnEdgeStrategy"
 …
 fg "0,65535,0"
+)
 xt "19250,52625,20000,53375"
+xt "39250,45625,40000,46375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "21000,52500,25800,53500"
+xt "41000,45500,45800,46500"
 st "dina : (15:0)"
 blo "21000,53300"
+blo "41000,46300"
+)
+)
 …
+)
+)
 *61 (CptPort
+*63 (CptPort
 uid 978,0
 ps "OnEdgeStrategy"
 …
 fg "0,65535,0"
+)
 xt "19250,54625,20000,55375"
+xt "39250,47625,40000,48375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "21000,54500,25900,55500"
+xt "41000,47500,45900,48500"
 st "addra : (7:0)"
 blo "21000,55300"
+blo "41000,48300"
+)
+)
 …
+)
+)
 *62 (CptPort
+*64 (CptPort
 uid 982,0
 ps "OnEdgeStrategy"
 …
 fg "0,65535,0"
+)
 xt "19250,53625,20000,54375"
+xt "39250,46625,40000,47375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "21000,53500,25300,54500"
+xt "41000,46500,45300,47500"
 st "wea : (0:0)"
 blo "21000,54300"
+blo "41000,47300"
+)
+)
 …
+)
+)
 *63 (CptPort
+*65 (CptPort
 uid 986,0
 ps "OnEdgeStrategy"
 …
 fg "0,65535,0"
+)
 xt "30000,50625,30750,51375"
+xt "50000,43625,50750,44375"
+)
 tg (CPTG
 …
 va (VaSet
+)
 xt "23800,50500,29000,51500"
+xt "43800,43500,49000,44500"
 st "douta : (15:0)"
 ju 2
 blo "29000,51300"
+blo "49000,44300"
+)
+)
 …
 lineWidth 2
+)
 xt "20000,49000,30000,59000"
+xt "40000,42000,50000,52000"
+)
 oxt "30000,7000,40000,17000"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *64 (Text
+*66 (Text
 uid 996,0
 va (VaSet
 font "Arial,8,1"
+)
 xt "20200,59000,26400,60000"
+xt "40200,52000,46400,53000"
 st "FACT_FAD_lib"
 blo "20200,59800"
+blo "40200,52800"
 tm "BdLibraryNameMgr"
+)
 *65 (Text
+*67 (Text
 uid 997,0
 va (VaSet
 font "Arial,8,1"
+)
 xt "20200,60000,30100,61000"
+xt "40200,53000,50100,54000"
 st "controlRAM_16bit_x256"
 blo "20200,60800"
+blo "40200,53800"
 tm "CptNameMgr"
+)
 *66 (Text
+*68 (Text
 uid 998,0
 va (VaSet
 font "Arial,8,1"
+)
 xt "20200,61000,26100,62000"
+xt "40200,54000,46100,55000"
 st "I_control_ram"
 blo "20200,61800"
+blo "40200,54800"
 tm "InstanceNameMgr"
+)
 …
 font "Courier New,8,0"
+)
 xt "19500,48000,19500,48000"
+xt "39500,41000,39500,41000"
+)
 header ""
 …
 fg "49152,49152,49152"
+)
 xt "20250,57250,21750,58750"
+xt "40250,50250,41750,51750"
 iconName "VhdlFileViewIcon.png"
 iconMaskName "VhdlFileViewIcon.msk"
 …
 archFileType "UNKNOWN"
+)
 *67 (Net
+*69 (Net
 uid 1082,0
 decl (Decl
 …
 font "Courier New,8,0"
+)
+xt "22000,8400,41500,9200"
+st "config_started    : std_logic := '0'"
+)
+)
+*68 (PortIoOut
+xt "29000,8600,48500,9400"
+st "config_started    : std_logic := '0'
+"
+)
+)
+*70 (PortIoOut
 uid 1090,0
 shape (CompositeShape
 …
 sl 0
 ro 270
 xt "42500,30625,44000,31375"
+xt "36500,30625,38000,31375"
+)
 (Line
 …
 sl 0
 ro 270
 xt "42000,31000,42500,31000"
+xt "36000,31000,36500,31000"
 pts [
 "42000,31000"
 "42500,31000"
+"36000,31000"
+"36500,31000"
+]
+)
 …
 va (VaSet
+)
 xt "45000,30500,50600,31500"
+xt "39000,30500,44600,31500"
 st "config_started"
 blo "45000,31300"
+blo "39000,31300"
 tm "WireNameMgr"
+)
+)
+)
+*69 (Wire
+*71 (Net
+uid 1206,0
+decl (Decl
+n "drs_address"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 17
+suid 19,0
+)
+declText (MLText
+uid 1207,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "29000,10200,55000,11000"
+st "drs_address       : std_logic_vector(3 DOWNTO 0)
+"
+)
+)
+*72 (PortIoOut
+uid 1214,0
+shape (CompositeShape
+uid 1215,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 1216,0
+sl 0
+ro 270
+xt "36500,21625,38000,22375"
+)
+(Line
+uid 1217,0
+sl 0
+ro 270
+xt "36000,22000,36500,22000"
+pts [
+"36000,22000"
+"36500,22000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 1218,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1219,0
+va (VaSet
+)
+xt "39000,21500,44000,22500"
+st "drs_address"
+blo "39000,22300"
+tm "WireNameMgr"
+)
+)
+)
+*73 (Net
+uid 1220,0
+decl (Decl
+n "drs_address_mode"
+t "std_logic"
+o 18
+suid 20,0
+)
+declText (MLText
+uid 1221,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "29000,11000,45000,11800"
+st "drs_address_mode  : std_logic
+"
+)
+)
+*74 (PortIoOut
+uid 1228,0
+shape (CompositeShape
+uid 1229,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 1230,0
+sl 0
+ro 270
+xt "36500,20625,38000,21375"
+)
+(Line
+uid 1231,0
+sl 0
+ro 270
+xt "36000,21000,36500,21000"
+pts [
+"36000,21000"
+"36500,21000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 1232,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1233,0
+va (VaSet
+)
+xt "39000,20500,46200,21500"
+st "drs_address_mode"
+blo "39000,21300"
+tm "WireNameMgr"
+)
+)
+)
+*75 (Wire
 uid 227,0
 shape (OrthoPolyLine
 …
 lineWidth 2
+)
 xt "38750,24000,42000,24000"
+xt "32750,24000,36000,24000"
 pts [
+"42000,24000"
+"40000,24000"
+"38750,24000"
+"36000,24000"
+"32750,24000"
+]
+)
 …
 isHidden 1
+)
 xt "45000,23000,49800,24000"
+xt "39000,23000,43800,24000"
 st "config_addr"
 blo "45000,23800"
+blo "39000,23800"
 tm "WireNameMgr"
+)
 …
 on &14
+)
 *70 (Wire
+*76 (Wire
 uid 233,0
 shape (OrthoPolyLine
 …
 lineWidth 2
+)
 xt "13000,39000,43000,54000"
+xt "32750,39000,39250,47000"
 pts [
+"19250,54000"
+"13000,54000"
+"13000,47000"
+"43000,47000"
+"43000,39000"
+"38750,39000"
+]
+)
+start &62
+"39250,47000"
+"34000,47000"
+"34000,39000"
+"32750,39000"
+]
+)
+start &64
 end &51
 sat 32
 …
 va (VaSet
+)
 xt "23000,46000,29300,47000"
+xt "34000,46000,40300,47000"
 st "ram_wren : (0:0)"
 blo "23000,46800"
+blo "34000,46800"
 tm "WireNameMgr"
+)
 …
 on &13
+)
 *71 (Wire
+*77 (Wire
 uid 237,0
 shape (OrthoPolyLine
 …
 lineWidth 2
+)
 xt "14000,38000,44000,53000"
+xt "32750,38000,39250,46000"
 pts [
+"19250,53000"
+"14000,53000"
+"14000,48000"
+"44000,48000"
+"44000,38000"
+"38750,38000"
+]
+)
+start &60
+"39250,46000"
+"35000,46000"
+"35000,38000"
+"32750,38000"
+]
+)
+start &62
 end &50
 sat 32
 …
 va (VaSet
+)
 xt "23000,47000,30900,48000"
+xt "33000,37000,40900,38000"
 st "ram_data_in : (15:0)"
 blo "23000,47800"
+blo "33000,37800"
 tm "WireNameMgr"
+)
 …
 on &15
+)
 *72 (Wire
+*78 (Wire
 uid 241,0
 shape (OrthoPolyLine
 …
 vasetType 3
+)
 xt "5000,24000,12250,24000"
+xt "4000,20000,6250,24000"
 pts [
+"4000,20000"
+"5000,20000"
 "5000,24000"
 "12250,24000"
+"6250,24000"
+]
+)
 …
 isHidden 1
+)
 xt "7000,23000,8300,24000"
+xt "6000,19000,7300,20000"
 st "clk"
 blo "7000,23800"
+blo "6000,19800"
 tm "WireNameMgr"
+)
 …
 on &12
+)
 *73 (Wire
+*79 (Wire
 uid 255,0
 shape (OrthoPolyLine
 …
 vasetType 3
+)
 xt "38750,32000,42000,32000"
+xt "32750,32000,36000,32000"
 pts [
 "38750,32000"
 "42000,32000"
+"32750,32000"
+"36000,32000"
+]
+)
 …
 isHidden 1
+)
 xt "45000,30000,51600,31000"
+xt "39000,30000,45600,31000"
 st "config_data_valid"
 blo "45000,30800"
+blo "39000,30800"
 tm "WireNameMgr"
+)
 …
 on &16
+)
 *74 (Wire
+*80 (Wire
 uid 261,0
 shape (OrthoPolyLine
 …
 vasetType 3
+)
 xt "38750,33000,42000,33000"
+xt "32750,33000,36000,33000"
 pts [
 "38750,33000"
 "42000,33000"
+"32750,33000"
+"36000,33000"
+]
+)
 …
 isHidden 1
+)
 xt "45000,31000,49800,32000"
+xt "39000,31000,43800,32000"
 st "config_busy"
 blo "45000,31800"
+blo "39000,31800"
 tm "WireNameMgr"
+)
 …
 on &17
+)
 *75 (Wire
+*81 (Wire
 uid 267,0
 shape (OrthoPolyLine
 …
 lineWidth 2
+)
 xt "38750,25000,42000,25000"
+xt "32750,25000,36000,25000"
 pts [
+"42000,25000"
+"40000,25000"
+"38750,25000"
+"36000,25000"
+"32750,25000"
+]
+)
 …
 isHidden 1
+)
 xt "45000,24000,49700,25000"
+xt "39000,24000,43700,25000"
 st "config_data"
 blo "45000,24800"
+blo "39000,24800"
 tm "WireNameMgr"
+)
 …
 on &18
+)
 *76 (Wire
+*82 (Wire
 uid 273,0
 shape (OrthoPolyLine
 …
 vasetType 3
+)
 xt "38750,35000,42000,35000"
+xt "32750,35000,36000,35000"
 pts [
+"38750,35000"
+"40000,35000"
+"42000,35000"
+"32750,35000"
+"36000,35000"
+]
+)
 …
 isHidden 1
+)
 xt "45000,34000,48400,35000"
+xt "39000,34000,42400,35000"
 st "roi_array"
 blo "45000,34800"
+blo "39000,34800"
 tm "WireNameMgr"
+)
 …
 on &19
+)
 *77 (Wire
+*83 (Wire
 uid 279,0
 shape (OrthoPolyLine
 …
 vasetType 3
+)
 xt "17000,51000,19250,51000"
+xt "43000,38000,43000,41250"
 pts [
 "17000,51000"
 "19250,51000"
+]
+)
 end &59
+"43000,38000"
+"43000,41250"
+]
+)
+end &61
 sat 16
 eat 32
 …
 va (VaSet
+)
 xt "18000,50000,19300,51000"
+xt "44000,37000,45300,38000"
 st "clk"
 blo "18000,50800"
+blo "44000,37800"
 tm "WireNameMgr"
+)
 …
 on &12
+)
 *78 (Wire
+*84 (Wire
 uid 285,0
 shape (OrthoPolyLine
 …
 lineWidth 2
+)
 xt "12000,40000,42000,55000"
+xt "32750,40000,39250,48000"
 pts [
+"38750,40000"
+"42000,40000"
+"42000,46000"
+"12000,46000"
+"12000,55000"
+"19250,55000"
+"32750,40000"
+"33000,40000"
+"33000,48000"
+"39250,48000"
+]
+)
 start &53
 end &61
+end &63
 sat 32
 eat 32
 …
 va (VaSet
+)
 xt "23000,45000,29200,46000"
+xt "33000,47000,39200,48000"
 st "ram_addr : (7:0)"
 blo "23000,45800"
+blo "33000,47800"
 tm "WireNameMgr"
+)
 …
 on &20
+)
 *79 (Wire
+*85 (Wire
 uid 289,0
 shape (OrthoPolyLine
 …
 vasetType 3
+)
 xt "38750,30000,42000,30000"
+xt "32750,30000,36000,30000"
 pts [
+"42000,30000"
+"40000,30000"
+"38750,30000"
+"36000,30000"
+"32750,30000"
+]
+)
 …
 isHidden 1
+)
 xt "45000,29000,49800,30000"
+xt "39000,29000,43800,30000"
 st "config_start"
 blo "45000,29800"
+blo "39000,29800"
 tm "WireNameMgr"
+)
 …
 on &25
+)
 *80 (Wire
+*86 (Wire
 uid 295,0
 shape (OrthoPolyLine
 …
 vasetType 3
+)
 xt "38750,27000,42000,27000"
+xt "32750,27000,36000,27000"
 pts [
+"42000,27000"
+"40000,27000"
+"38750,27000"
+"36000,27000"
+"32750,27000"
+]
+)
 …
 isHidden 1
+)
 xt "45000,26000,50300,27000"
+xt "39000,26000,44300,27000"
 st "config_wr_en"
 blo "45000,26800"
+blo "39000,26800"
 tm "WireNameMgr"
+)
 …
 on &21
+)
 *81 (Wire
+*87 (Wire
 uid 301,0
 shape (OrthoPolyLine
 …
 lineWidth 2
+)
 xt "9000,25000,34000,64000"
+xt "3000,39000,52000,56000"
 pts [
 "12250,25000"
 "9000,25000"
 "9000,64000"
 "34000,64000"
 "34000,51000"
 "30750,51000"
+"6250,39000"
+"3000,39000"
+"3000,56000"
+"52000,56000"
+"52000,44000"
+"50750,44000"
+]
+)
 start &52
 end &63
+end &65
 sat 32
 eat 32
 …
 va (VaSet
+)
 xt "20000,63000,28300,64000"
+xt "33000,55000,41300,56000"
 st "ram_data_out : (15:0)"
 blo "20000,63800"
+blo "33000,55800"
 tm "WireNameMgr"
+)
 …
 on &22
+)
 *82 (Wire
+*88 (Wire
 uid 305,0
 shape (OrthoPolyLine
 …
 vasetType 3
+)
 xt "38750,34000,42000,34000"
+xt "32750,34000,36000,34000"
 pts [
+"38750,34000"
+"40000,34000"
+"42000,34000"
+"32750,34000"
+"36000,34000"
+]
+)
 …
 isHidden 1
+)
 xt "45000,33000,48700,34000"
+xt "39000,33000,42700,34000"
 st "dac_array"
 blo "45000,33800"
+blo "39000,33800"
 tm "WireNameMgr"
+)
 …
 on &23
+)
 *83 (Wire
+*89 (Wire
 uid 311,0
 shape (OrthoPolyLine
 …
 vasetType 3
+)
 xt "38750,28000,42000,28000"
+xt "32750,28000,36000,28000"
 pts [
+"42000,28000"
+"40000,28000"
+"38750,28000"
+"36000,28000"
+"32750,28000"
+]
+)
 …
 isHidden 1
+)
 xt "45000,27000,50200,28000"
+xt "39000,27000,44200,28000"
 st "config_rd_en"
 blo "45000,27800"
+blo "39000,27800"
 tm "WireNameMgr"
+)
 …
 on &24
+)
 *84 (Wire
+*90 (Wire
 uid 321,0
 shape (OrthoPolyLine
 …
 vasetType 3
+)
 xt "38750,29000,42000,29000"
+xt "32750,29000,36000,29000"
 pts [
+"38750,29000"
+"40000,29000"
+"42000,29000"
+"32750,29000"
+"36000,29000"
+]
+)
 …
 isHidden 1
+)
 xt "45000,28000,50100,29000"
+xt "39000,28000,44100,29000"
 st "config_ready"
 blo "45000,28800"
+blo "39000,28800"
 tm "WireNameMgr"
+)
 …
 on &26
+)
 *85 (Wire
+*91 (Wire
 uid 1084,0
 shape (OrthoPolyLine
 …
 vasetType 3
+)
 xt "38750,31000,42000,31000"
+xt "32750,31000,36000,31000"
 pts [
 "38750,31000"
 "42000,31000"
+"32750,31000"
+"36000,31000"
+]
+)
 start &54
 end &68
+end &70
 sat 32
 eat 32
 …
 isHidden 1
+)
 xt "40000,30000,45600,31000"
+xt "34000,30000,39600,31000"
 st "config_started"
 blo "40000,30800"
+blo "34000,30800"
 tm "WireNameMgr"
+)
+)
+on &67
+on &69
+)
+*92 (Wire
+uid 1208,0
+shape (OrthoPolyLine
+uid 1209,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "32750,22000,36000,22000"
+pts [
+"32750,22000"
+"36000,22000"
+]
+)
+start &55
+end &72
+sat 32
+eat 32
+sty 1
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 1212,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1213,0
+va (VaSet
+isHidden 1
+)
+xt "34000,21000,39000,22000"
+st "drs_address"
+blo "34000,21800"
+tm "WireNameMgr"
+)
+)
+on &71
+)
+*93 (Wire
+uid 1222,0
+shape (OrthoPolyLine
+uid 1223,0
+va (VaSet
+vasetType 3
+)
+xt "32750,21000,36000,21000"
+pts [
+"32750,21000"
+"36000,21000"
+]
+)
+start &56
+end &74
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 1226,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1227,0
+va (VaSet
+isHidden 1
+)
+xt "34000,20000,41200,21000"
+st "drs_address_mode"
+blo "34000,20800"
+tm "WireNameMgr"
+)
+)
+on &73
+)
+]
 …
 color "26368,26368,26368"
+)
 packageList *86 (PackageList
+packageList *94 (PackageList
 uid 41,0
 stg "VerticalLayoutStrategy"
 textVec [
 *87 (Text
+*95 (Text
 uid 42,0
 va (VaSet
 font "arial,8,1"
+)
 xt "0,0,5400,1000"
+xt "1000,1000,6400,2000"
 st "Package List"
 blo "0,800"
+)
 *88 (MLText
+blo "1000,1800"
+)
+*96 (MLText
 uid 43,0
 va (VaSet
+)
 xt "0,1000,15300,6000"
+xt "1000,2000,16300,7000"
 st "LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *89 (Text
+*97 (Text
 uid 45,0
 va (VaSet
 …
 blo "20000,800"
+)
 *90 (Text
+*98 (Text
 uid 46,0
 va (VaSet
 …
 blo "20000,1800"
+)
 *91 (MLText
+*99 (MLText
 uid 47,0
 va (VaSet
 …
 tm "BdCompilerDirectivesTextMgr"
+)
 *92 (Text
+*100 (Text
 uid 48,0
 va (VaSet
 …
 blo "20000,4800"
+)
 *93 (MLText
+*101 (MLText
 uid 49,0
 va (VaSet
 …
 tm "BdCompilerDirectivesTextMgr"
+)
 *94 (Text
+*102 (Text
 uid 50,0
 va (VaSet
 …
 blo "20000,5800"
+)
 *95 (MLText
+*103 (MLText
 uid 51,0
 va (VaSet
 …
 associable 1
+)
 windowSize "0,22,1286,1024"
 viewArea "834,29654,54098,72685"
 cachedDiagramExtent "0,0,53000,77000"
+windowSize "0,0,1281,1002"
+viewArea "-6400,12000,60443,65739"
+cachedDiagramExtent "700,0,59000,77000"
 pageSetupInfo (PageSetupInfo
 ptrCmd "Brother HL-5270DN series,winspool,"
 …
 hasePageBreakOrigin 1
 pageBreakOrigin "0,0"
 lastUid 1122,0
+lastUid 1237,0
 defaultCommentText (CommentText
 shape (Rectangle
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *96 (Text
+*104 (Text
 va (VaSet
 font "Arial,8,1"
 …
 tm "BdLibraryNameMgr"
+)
 *97 (Text
+*105 (Text
 va (VaSet
 font "Arial,8,1"
 …
 tm "BlkNameMgr"
+)
 *98 (Text
+*106 (Text
 va (VaSet
 font "Arial,8,1"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *99 (Text
+*107 (Text
 va (VaSet
 font "Arial,8,1"
 …
 blo "550,4300"
+)
 *100 (Text
+*108 (Text
 va (VaSet
 font "Arial,8,1"
 …
 blo "550,5300"
+)
 *101 (Text
+*109 (Text
 va (VaSet
 font "Arial,8,1"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *102 (Text
+*110 (Text
 va (VaSet
 font "Arial,8,1"
 …
 tm "BdLibraryNameMgr"
+)
 *103 (Text
+*111 (Text
 va (VaSet
 font "Arial,8,1"
 …
 tm "CptNameMgr"
+)
 *104 (Text
+*112 (Text
 va (VaSet
 font "Arial,8,1"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *105 (Text
+*113 (Text
 va (VaSet
 font "Arial,8,1"
 …
 blo "500,4300"
+)
 *106 (Text
+*114 (Text
 va (VaSet
 font "Arial,8,1"
 …
 blo "500,5300"
+)
 *107 (Text
+*115 (Text
 va (VaSet
 font "Arial,8,1"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *108 (Text
+*116 (Text
 va (VaSet
 font "Arial,8,1"
 …
 blo "50,4300"
+)
 *109 (Text
+*117 (Text
 va (VaSet
 font "Arial,8,1"
 …
 blo "50,5300"
+)
 *110 (Text
+*118 (Text
 va (VaSet
 font "Arial,8,1"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *111 (Text
+*119 (Text
 va (VaSet
 font "Arial,8,1"
 …
 tm "HdlTextNameMgr"
+)
 *112 (Text
+*120 (Text
 va (VaSet
 font "Arial,8,1"
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *113 (Text
+*121 (Text
 va (VaSet
 font "Arial,8,1"
 …
 blo "14100,20800"
+)
 *114 (MLText
+*122 (MLText
 va (VaSet
+)
 …
 stg "VerticalLayoutStrategy"
 textVec [
 *115 (Text
+*123 (Text
 va (VaSet
 font "Arial,8,1"
 …
 blo "14100,20800"
+)
 *116 (MLText
+*124 (MLText
 va (VaSet
+)
 …
 font "Arial,8,1"
+)
 xt "20000,0,25400,1000"
+xt "27000,200,32400,1200"
 st "Declarations"
 blo "20000,800"
+blo "27000,1000"
+)
 portLabel (Text
 …
 font "Arial,8,1"
+)
 xt "20000,1000,22700,2000"
+xt "27000,1200,29700,2200"
 st "Ports:"
 blo "20000,1800"
+blo "27000,2000"
+)
 preUserLabel (Text
 …
 font "Arial,8,1"
+)
 xt "20000,0,23800,1000"
+xt "27000,200,30800,1200"
 st "Pre User:"
 blo "20000,800"
+blo "27000,1000"
+)
 preUserText (MLText
 …
 font "Courier New,8,0"
+)
 xt "20000,0,20000,0"
+xt "27000,200,27000,200"
 tm "BdDeclarativeTextMgr"
+)
 …
 font "Arial,8,1"
+)
 xt "20000,11600,27100,12600"
+xt "27000,13400,34100,14400"
 st "Diagram Signals:"
 blo "20000,12400"
+blo "27000,14200"
+)
 postUserLabel (Text
 …
 font "Arial,8,1"
+)
 xt "20000,0,24700,1000"
+xt "27000,200,31700,1200"
 st "Post User:"
 blo "20000,800"
+blo "27000,1000"
+)
 postUserText (MLText
 …
 font "Courier New,8,0"
+)
 xt "20000,0,20000,0"
+xt "27000,200,27000,200"
 tm "BdDeclarativeTextMgr"
+)
 …
 commonDM (CommonDM
 ldm (LogicalDM
 suid 18,0
+suid 20,0
 usingSuid 1
 emptyRow *117 (LEmptyRow
+emptyRow *125 (LEmptyRow
+)
 uid 54,0
 optionalChildren [
 *118 (RefLabelRowHdr
+)
 *119 (TitleRowHdr
+)
 *120 (FilterRowHdr
+)
 *121 (RefLabelColHdr
+*126 (RefLabelRowHdr
+)
+*127 (TitleRowHdr
+)
+*128 (FilterRowHdr
+)
+*129 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
+)
 *122 (RowExpandColHdr
+*130 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
+)
 *123 (GroupColHdr
+*131 (GroupColHdr
 tm "GroupColHdrMgr"
+)
 *124 (NameColHdr
+*132 (NameColHdr
 tm "BlockDiagramNameColHdrMgr"
+)
 *125 (ModeColHdr
+*133 (ModeColHdr
 tm "BlockDiagramModeColHdrMgr"
+)
 *126 (TypeColHdr
+*134 (TypeColHdr
 tm "BlockDiagramTypeColHdrMgr"
+)
 *127 (BoundsColHdr
+*135 (BoundsColHdr
 tm "BlockDiagramBoundsColHdrMgr"
+)
 *128 (InitColHdr
+*136 (InitColHdr
 tm "BlockDiagramInitColHdrMgr"
+)
 *129 (EolColHdr
+*137 (EolColHdr
 tm "BlockDiagramEolColHdrMgr"
+)
 *130 (LeafLogPort
+*138 (LeafLogPort
 port (LogicalPort
 decl (Decl
 …
 uid 427,0
+)
 *131 (LeafLogPort
+*139 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 429,0
+)
 *132 (LeafLogPort
+*140 (LeafLogPort
 port (LogicalPort
 decl (Decl
 …
 uid 431,0
+)
 *133 (LeafLogPort
+*141 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 433,0
+)
 *134 (LeafLogPort
+*142 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 435,0
+)
 *135 (LeafLogPort
+*143 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 437,0
+)
 *136 (LeafLogPort
+*144 (LeafLogPort
 port (LogicalPort
 m 2
 …
 uid 439,0
+)
 *137 (LeafLogPort
+*145 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 441,0
+)
 *138 (LeafLogPort
+*146 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 443,0
+)
 *139 (LeafLogPort
+*147 (LeafLogPort
 port (LogicalPort
 decl (Decl
 …
 uid 445,0
+)
 *140 (LeafLogPort
+*148 (LeafLogPort
 port (LogicalPort
 m 4
 …
 uid 447,0
+)
 *141 (LeafLogPort
+*149 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 449,0
+)
 *142 (LeafLogPort
+*150 (LeafLogPort
 port (LogicalPort
 decl (Decl
 …
 uid 451,0
+)
 *143 (LeafLogPort
+*151 (LeafLogPort
 port (LogicalPort
 decl (Decl
 …
 uid 453,0
+)
 *144 (LeafLogPort
+*152 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 457,0
+)
 *145 (LeafLogPort
+*153 (LeafLogPort
 port (LogicalPort
 m 1
 …
 uid 1096,0
+)
+*154 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "drs_address"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 17
+suid 19,0
+)
+)
+uid 1234,0
+)
+*155 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "drs_address_mode"
+t "std_logic"
+o 18
+suid 20,0
+)
+)
+uid 1236,0
+)
+]
+)
 …
 uid 67,0
 optionalChildren [
 *146 (Sheet
+*156 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
 …
 font "Tahoma,10,0"
+)
 emptyMRCItem *147 (MRCItem
 litem &117
 pos 16
+emptyMRCItem *157 (MRCItem
+litem &125
+pos 18
 dimension 20
+)
 uid 69,0
 optionalChildren [
 *148 (MRCItem
 litem &118
+*158 (MRCItem
+litem &126
 pos 0
 dimension 20
 uid 70,0
+)
 *149 (MRCItem
 litem &119
+*159 (MRCItem
+litem &127
 pos 1
 dimension 23
 uid 71,0
+)
 *150 (MRCItem
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+*160 (MRCItem
+litem &128
 pos 2
 hidden 1
 …
 uid 72,0
+)
 *151 (MRCItem
 litem &130
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+litem &138
 pos 0
 dimension 20
 uid 428,0
+)
 *152 (MRCItem
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 pos 11
 dimension 20
 uid 430,0
+)
 *153 (MRCItem
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+litem &140
 pos 1
 dimension 20
 uid 432,0
+)
 *154 (MRCItem
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 pos 12
 dimension 20
 uid 434,0
+)
 *155 (MRCItem
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+litem &142
 pos 2
 dimension 20
 uid 436,0
+)
 *156 (MRCItem
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+litem &143
 pos 3
 dimension 20
 uid 438,0
+)
 *157 (MRCItem
 litem &136
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+litem &144
 pos 4
 dimension 20
 uid 440,0
+)
 *158 (MRCItem
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+litem &145
 pos 5
 dimension 20
 uid 442,0
+)
 *159 (MRCItem
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+*169 (MRCItem
+litem &146
 pos 13
 dimension 20
 uid 444,0
+)
 *160 (MRCItem
 litem &139
+*170 (MRCItem
+litem &147
 pos 6
 dimension 20
 uid 446,0
+)
 *161 (MRCItem
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+*171 (MRCItem
+litem &148
 pos 14
 dimension 20
 uid 448,0
+)
 *162 (MRCItem
 litem &141
+*172 (MRCItem
+litem &149
 pos 7
 dimension 20
 uid 450,0
+)
 *163 (MRCItem
 litem &142
+*173 (MRCItem
+litem &150
 pos 8
 dimension 20
 uid 452,0
+)
 *164 (MRCItem
 litem &143
+*174 (MRCItem
+litem &151
 pos 9
 dimension 20
 uid 454,0
+)
 *165 (MRCItem
 litem &144
+*175 (MRCItem
+litem &152
 pos 10
 dimension 20
 uid 458,0
+)
 *166 (MRCItem
 litem &145
+*176 (MRCItem
+litem &153
 pos 15
 dimension 20
 uid 1097,0
+)
+*177 (MRCItem
+litem &154
+pos 16
+dimension 20
+uid 1235,0
+)
+*178 (MRCItem
+litem &155
+pos 17
+dimension 20
+uid 1237,0
+)
+]
 …
 uid 73,0
 optionalChildren [
 *167 (MRCItem
 litem &121
+*179 (MRCItem
+litem &129
 pos 0
 dimension 20
 uid 74,0
+)
 *168 (MRCItem
 litem &123
+*180 (MRCItem
+litem &131
 pos 1
 dimension 50
 uid 75,0
+)
 *169 (MRCItem
 litem &124
+*181 (MRCItem
+litem &132
 pos 2
 dimension 100
 uid 76,0
+)
 *170 (MRCItem
 litem &125
+*182 (MRCItem
+litem &133
 pos 3
 dimension 50
 uid 77,0
+)
 *171 (MRCItem
 litem &126
+*183 (MRCItem
+litem &134
 pos 4
 dimension 100
 uid 78,0
+)
 *172 (MRCItem
 litem &127
+*184 (MRCItem
+litem &135
 pos 5
 dimension 100
 uid 79,0
+)
 *173 (MRCItem
 litem &128
+*185 (MRCItem
+litem &136
 pos 6
 dimension 50
 uid 80,0
+)
 *174 (MRCItem
 litem &129
+*186 (MRCItem
+litem &137
 pos 7
 dimension 80
 …
 genericsCommonDM (CommonDM
 ldm (LogicalDM
 emptyRow *175 (LEmptyRow
+emptyRow *187 (LEmptyRow
+)
 uid 83,0
 optionalChildren [
 *176 (RefLabelRowHdr
+)
 *177 (TitleRowHdr
+)
 *178 (FilterRowHdr
+)
 *179 (RefLabelColHdr
+*188 (RefLabelRowHdr
+)
+*189 (TitleRowHdr
+)
+*190 (FilterRowHdr
+)
+*191 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
+)
 *180 (RowExpandColHdr
+*192 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
+)
 *181 (GroupColHdr
+*193 (GroupColHdr
 tm "GroupColHdrMgr"
+)
 *182 (NameColHdr
+*194 (NameColHdr
 tm "GenericNameColHdrMgr"
+)
 *183 (TypeColHdr
+*195 (TypeColHdr
 tm "GenericTypeColHdrMgr"
+)
 *184 (InitColHdr
+*196 (InitColHdr
 tm "GenericValueColHdrMgr"
+)
 *185 (PragmaColHdr
+*197 (PragmaColHdr
 tm "GenericPragmaColHdrMgr"
+)
 *186 (EolColHdr
+*198 (EolColHdr
 tm "GenericEolColHdrMgr"
+)
 …
 uid 95,0
 optionalChildren [
 *187 (Sheet
+*199 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
 …
 font "Tahoma,10,0"
+)
 emptyMRCItem *188 (MRCItem
 litem &175
+emptyMRCItem *200 (MRCItem
+litem &187
 pos 0
 dimension 20
 …
 uid 97,0
 optionalChildren [
 *189 (MRCItem
 litem &176
+*201 (MRCItem
+litem &188
 pos 0
 dimension 20
 uid 98,0
+)
 *190 (MRCItem
 litem &177
+*202 (MRCItem
+litem &189
 pos 1
 dimension 23
 uid 99,0
+)
 *191 (MRCItem
 litem &178
+*203 (MRCItem
+litem &190
 pos 2
 hidden 1
 …
 uid 101,0
 optionalChildren [
 *192 (MRCItem
 litem &179
+*204 (MRCItem
+litem &191
 pos 0
 dimension 20
 uid 102,0
+)
 *193 (MRCItem
 litem &181
+*205 (MRCItem
+litem &193
 pos 1
 dimension 50
 uid 103,0
+)
 *194 (MRCItem
 litem &182
+*206 (MRCItem
+litem &194
 pos 2
 dimension 100
 uid 104,0
+)
 *195 (MRCItem
 litem &183
+*207 (MRCItem
+litem &195
 pos 3
 dimension 100
 uid 105,0
+)
 *196 (MRCItem
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+*208 (MRCItem
+litem &196
 pos 4
 dimension 50
 uid 106,0
+)
 *197 (MRCItem
 litem &185
+*209 (MRCItem
+litem &197
 pos 5
 dimension 50
 uid 107,0
+)
 *198 (MRCItem
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+*210 (MRCItem
+litem &198
 pos 6
 dimension 80

FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.bak

r246	r252
60	60	)
61	61	version "29.1"
62		appVersion "2009.~~1 (Build 12~~)"
	62	appVersion "2009.2 (Build 10)"
63	63	noEmbeddedEditors 1
64	64	model (BlockDiag
…	…
67	67	(vvPair
68	68	variable "HDLDir"
69		value "~~D:\\FAD_Firmwar~~e\\FACT_FAD\\FACT_FAD_lib\\hdl"
	69	value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
70	70	)
71	71	(vvPair
72	72	variable "HDSDir"
73		value "~~D:\\FAD_Firmwar~~e\\FACT_FAD\\FACT_FAD_lib\\hds"
	73	value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
74	74	)
75	75	(vvPair
76	76	variable "SideDataDesignDir"
77		value "~~D:\\FAD_Firmwar~~e\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info"
	77	value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info"
78	78	)
79	79	(vvPair
80	80	variable "SideDataUserDir"
81		value "~~D:\\FAD_Firmwar~~e\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user"
	81	value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user"
82	82	)
83	83	(vvPair
84	84	variable "SourceDir"
85		value "~~D:\\FAD_Firmwar~~e\\FACT_FAD\\FACT_FAD_lib\\hds"
	85	value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
86	86	)
87	87	(vvPair
…	…
99	99	(vvPair
100	100	variable "d"
101		value "~~D:\\FAD_Firmwar~~e\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
	101	value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
102	102	)
103	103	(vvPair
104	104	variable "d_logical"
105		value "~~D:\\FAD_Firmwar~~e\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
	105	value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
106	106	)
107	107	(vvPair
108	108	variable "date"
109		value "~~27.05~~.2010"
	109	value "12.07.2010"
110	110	)
111	111	(vvPair
112	112	variable "day"
113		value "Do"
	113	value "Mo"
114	114	)
115	115	(vvPair
116	116	variable "day_long"
117		value "~~Donners~~tag"
	117	value "Montag"
118	118	)
119	119	(vvPair
120	120	variable "dd"
121		value "27"
	121	value "12"
122	122	)
123	123	(vvPair
…	…
147	147	(vvPair
148	148	variable "host"
149		value "~~IHP110~~"
	149	value "TU-CC4900F8C7D2"
150	150	)
151	151	(vvPair
…	…
175	175	(vvPair
176	176	variable "mm"
177		value "05"
	177	value "07"
178	178	)
179	179	(vvPair
…	…
183	183	(vvPair
184	184	variable "month"
185		value "~~Mai~~"
	185	value "Jul"
186	186	)
187	187	(vvPair
188	188	variable "month_long"
189		value "Mai"
	189	value "Juli"
190	190	)
191	191	(vvPair
192	192	variable "p"
193		value "~~D:\\FAD_Firmwar~~e\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
	193	value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
194	194	)
195	195	(vvPair
196	196	variable "p_logical"
197		value "~~D:\\FAD_Firmwar~~e\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
	197	value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
198	198	)
199	199	(vvPair
…	…
219	219	(vvPair
220	220	variable "task_ModelSimPath"
221		value "~~D:\\modeltech_6.5e\\win32~~"
	221	value "<TBD>"
222	222	)
223	223	(vvPair
…	…
251	251	(vvPair
252	252	variable "time"
253		value "1~~0:24:01~~"
	253	value "13:47:38"
254	254	)
255	255	(vvPair
…	…
259	259	(vvPair
260	260	variable "user"
261		value "d~~aqct3~~"
	261	value "dneise"
262	262	)
263	263	(vvPair
264	264	variable "version"
265		value "2009.~~1 (Build 12~~)"
	265	value "2009.2 (Build 10)"
266	266	)
267	267	(vvPair
…	…
303	303	bg "0,0,32768"
304	304	)
305		xt "16200,76000,24500,77000"
	305	xt "16200,76000,25500,77000"
306	306	st "
307	307	by %user on %dd %month %year
…	…
621	621	font "Courier New,8,0"
622	622	)
623		xt "22000,2000,38000,2800"
624		st "clk : STD_LOGIC
625		"
	623	xt "29000,2200,45000,3000"
	624	st "clk : STD_LOGIC"
626	625	)
627	626	)
…	…
640	639	font "Courier New,8,0"
641	640	)
642		xt "22000,15000,51500,15800"
643		st "SIGNAL ram_wren : std_logic_VECTOR(0 DOWNTO 0)
644		"
	641	xt "29000,15200,58500,16000"
	642	st "SIGNAL ram_wren : std_logic_VECTOR(0 DOWNTO 0)"
645	643	)
646	644	)
…	…
659	657	font "Courier New,8,0"
660	658	)
661		xt "22000,2800,48000,3600"
662		st "config_addr : std_logic_vector(7 DOWNTO 0)
663		"
	659	xt "29000,3000,55000,3800"
	660	st "config_addr : std_logic_vector(7 DOWNTO 0)"
664	661	)
665	662	)
…	…
678	675	font "Courier New,8,0"
679	676	)
680		xt "22000,13400,52000,14200"
681		st "SIGNAL ram_data_in : std_logic_VECTOR(15 DOWNTO 0)
682		"
	677	xt "29000,13600,59000,14400"
	678	st "SIGNAL ram_data_in : std_logic_VECTOR(15 DOWNTO 0)"
683	679	)
684	680	)
…	…
696	692	font "Courier New,8,0"
697	693	)
698		xt "22000,6800,38000,7600"
699		st "config_data_valid : std_logic
700		"
	694	xt "29000,7000,45000,7800"
	695	st "config_data_valid : std_logic"
701	696	)
702	697	)
…	…
714	709	font "Courier New,8,0"
715	710	)
716		xt "22000,6000,38000,6800"
717		st "config_busy : std_logic
718		"
	711	xt "29000,6200,45000,7000"
	712	st "config_busy : std_logic"
719	713	)
720	714	)
…	…
733	727	font "Courier New,8,0"
734	728	)
735		xt "22000,10800,48500,11600"
736		st "config_data : std_logic_vector(15 DOWNTO 0)
737		"
	729	xt "29000,11000,55500,11800"
	730	st "config_data : std_logic_vector(15 DOWNTO 0)"
738	731	)
739	732	)
…	…
751	744	font "Courier New,8,0"
752	745	)
753		xt "22000,10000,40500,10800"
754		st "roi_array : roi_array_type
755		"
	746	xt "29000,10200,47500,11000"
	747	st "roi_array : roi_array_type"
756	748	)
757	749	)
…	…
770	762	font "Courier New,8,0"
771	763	)
772		xt "22000,12600,51500,13400"
773		st "SIGNAL ram_addr : std_logic_VECTOR(7 DOWNTO 0)
774		"
	764	xt "29000,12800,58500,13600"
	765	st "SIGNAL ram_addr : std_logic_VECTOR(7 DOWNTO 0)"
775	766	)
776	767	)
…	…
788	779	font "Courier New,8,0"
789	780	)
790		xt "22000,5200,38000,6000"
791		st "config_wr_en : std_logic
792		"
	781	xt "29000,5400,45000,6200"
	782	st "config_wr_en : std_logic"
793	783	)
794	784	)
…	…
807	797	font "Courier New,8,0"
808	798	)
809		xt "22000,14200,52000,15000"
810		st "SIGNAL ram_data_out : std_logic_VECTOR(15 DOWNTO 0)
811		"
	799	xt "29000,14400,59000,15200"
	800	st "SIGNAL ram_data_out : std_logic_VECTOR(15 DOWNTO 0)"
812	801	)
813	802	)
…	…
825	814	font "Courier New,8,0"
826	815	)
827		xt "22000,9200,40500,10000"
828		st "dac_array : dac_array_type
829		"
	816	xt "29000,9400,47500,10200"
	817	st "dac_array : dac_array_type"
830	818	)
831	819	)
…	…
843	831	font "Courier New,8,0"
844	832	)
845		xt "22000,3600,38000,4400"
846		st "config_rd_en : std_logic
847		"
	833	xt "29000,3800,45000,4600"
	834	st "config_rd_en : std_logic"
848	835	)
849	836	)
…	…
861	848	font "Courier New,8,0"
862	849	)
863		xt "22000,4400,38000,5200"
864		st "config_start : std_logic
865		"
	850	xt "29000,4600,45000,5400"
	851	st "config_start : std_logic"
866	852	)
867	853	)
…	…
879	865	font "Courier New,8,0"
880	866	)
881		xt "22000,7600,38000,8400"
882		st "config_ready : std_logic
883		"
	867	xt "29000,7800,45000,8600"
	868	st "config_ready : std_logic"
884	869	)
885	870	)
…	…
897	882	sl 0
898	883	ro 270
899		xt "~~3000,23625,4500,24~~375"
	884	xt "2000,19625,3500,20375"
900	885	)
901	886	(Line
…	…
903	888	sl 0
904	889	ro 270
905		xt "~~4500,24000,5000,24~~000"
	890	xt "3500,20000,4000,20000"
906	891	pts [
907		"~~4500,24~~000"
908		"~~5000,24~~000"
	892	"3500,20000"
	893	"4000,20000"
909	894	]
910	895	)
…	…
921	906	va (VaSet
922	907	)
923		xt "700,~~23500,2000,24~~500"
	908	xt "700,19500,2000,20500"
924	909	st "clk"
925	910	ju 2
926		blo "2000,24300"
	911	blo "2000,20300"
927	912	tm "WireNameMgr"
928	913	)
…	…
942	927	sl 0
943	928	ro 270
944		xt "~~42500,28625,44~~000,29375"
	929	xt "36500,28625,38000,29375"
945	930	)
946	931	(Line
…	…
948	933	sl 0
949	934	ro 270
950		xt "~~42000,29000,42~~500,29000"
	935	xt "36000,29000,36500,29000"
951	936	pts [
952		"42000,29000"
953		"42500,29000"
	937	"36000,29000"
	938	"36500,29000"
954	939	]
955	940	)
…	…
966	951	va (VaSet
967	952	)
968		xt "~~45000,28500,50~~100,29500"
	953	xt "39000,28500,44100,29500"
969	954	st "config_ready"
970		blo "45000,29300"
	955	blo "39000,29300"
971	956	tm "WireNameMgr"
972	957	)
…	…
986	971	sl 0
987	972	ro 90
988		xt "~~42500,29625,44~~000,30375"
	973	xt "36500,29625,38000,30375"
989	974	)
990	975	(Line
…	…
992	977	sl 0
993	978	ro 90
994		xt "~~42000,30000,42~~500,30000"
	979	xt "36000,30000,36500,30000"
995	980	pts [
996		"42500,30000"
997		"42000,30000"
	981	"36500,30000"
	982	"36000,30000"
998	983	]
999	984	)
…	…
1010	995	va (VaSet
1011	996	)
1012		xt "~~45000,29500,49~~800,30500"
	997	xt "39000,29500,43800,30500"
1013	998	st "config_start"
1014		blo "45000,30300"
	999	blo "39000,30300"
1015	1000	tm "WireNameMgr"
1016	1001	)
…	…
1029	1014	uid 381,0
1030	1015	sl 0
1031		xt "~~42500,24625,44~~000,25375"
	1016	xt "36500,24625,38000,25375"
1032	1017	)
1033	1018	(Line
1034	1019	uid 382,0
1035	1020	sl 0
1036		xt "~~42000,25000,42~~500,25000"
	1021	xt "36000,25000,36500,25000"
1037	1022	pts [
1038		"42000,25000"
1039		"42500,25000"
	1023	"36000,25000"
	1024	"36500,25000"
1040	1025	]
1041	1026	)
…	…
1052	1037	va (VaSet
1053	1038	)
1054		xt "~~45000,24500,49~~700,25500"
	1039	xt "39000,24500,43700,25500"
1055	1040	st "config_data"
1056		blo "45000,25300"
	1041	blo "39000,25300"
1057	1042	tm "WireNameMgr"
1058	1043	)
…	…
1072	1057	sl 0
1073	1058	ro 90
1074		xt "~~42500,23625,44~~000,24375"
	1059	xt "36500,23625,38000,24375"
1075	1060	)
1076	1061	(Line
…	…
1078	1063	sl 0
1079	1064	ro 90
1080		xt "~~42000,24000,42~~500,24000"
	1065	xt "36000,24000,36500,24000"
1081	1066	pts [
1082		"42500,24000"
1083		"42000,24000"
	1067	"36500,24000"
	1068	"36000,24000"
1084	1069	]
1085	1070	)
…	…
1096	1081	va (VaSet
1097	1082	)
1098		xt "~~45000,23500,49~~800,24500"
	1083	xt "39000,23500,43800,24500"
1099	1084	st "config_addr"
1100		blo "45000,24300"
	1085	blo "39000,24300"
1101	1086	tm "WireNameMgr"
1102	1087	)
…	…
1116	1101	sl 0
1117	1102	ro 90
1118		xt "~~42500,26625,44~~000,27375"
	1103	xt "36500,26625,38000,27375"
1119	1104	)
1120	1105	(Line
…	…
1122	1107	sl 0
1123	1108	ro 90
1124		xt "~~42000,27000,42~~500,27000"
	1109	xt "36000,27000,36500,27000"
1125	1110	pts [
1126		"42500,27000"
1127		"42000,27000"
	1111	"36500,27000"
	1112	"36000,27000"
1128	1113	]
1129	1114	)
…	…
1140	1125	va (VaSet
1141	1126	)
1142		xt "~~45000,26500,50~~300,27500"
	1127	xt "39000,26500,44300,27500"
1143	1128	st "config_wr_en"
1144		blo "45000,27300"
	1129	blo "39000,27300"
1145	1130	tm "WireNameMgr"
1146	1131	)
…	…
1160	1145	sl 0
1161	1146	ro 90
1162		xt "~~42500,27625,44~~000,28375"
	1147	xt "36500,27625,38000,28375"
1163	1148	)
1164	1149	(Line
…	…
1166	1151	sl 0
1167	1152	ro 90
1168		xt "~~42000,28000,42~~500,28000"
	1153	xt "36000,28000,36500,28000"
1169	1154	pts [
1170		"42500,28000"
1171		"42000,28000"
	1155	"36500,28000"
	1156	"36000,28000"
1172	1157	]
1173	1158	)
…	…
1184	1169	va (VaSet
1185	1170	)
1186		xt "~~45000,27500,50~~200,28500"
	1171	xt "39000,27500,44200,28500"
1187	1172	st "config_rd_en"
1188		blo "45000,28300"
	1173	blo "39000,28300"
1189	1174	tm "WireNameMgr"
1190	1175	)
…	…
1204	1189	sl 0
1205	1190	ro 270
1206		xt "~~42500,33625,44~~000,34375"
	1191	xt "36500,33625,38000,34375"
1207	1192	)
1208	1193	(Line
…	…
1210	1195	sl 0
1211	1196	ro 270
1212		xt "~~42000,34000,42~~500,34000"
	1197	xt "36000,34000,36500,34000"
1213	1198	pts [
1214		"42000,34000"
1215		"42500,34000"
	1199	"36000,34000"
	1200	"36500,34000"
1216	1201	]
1217	1202	)
…	…
1228	1213	va (VaSet
1229	1214	)
1230		xt "~~45000,33500,48~~700,34500"
	1215	xt "39000,33500,42700,34500"
1231	1216	st "dac_array"
1232		blo "45000,34300"
	1217	blo "39000,34300"
1233	1218	tm "WireNameMgr"
1234	1219	)
…	…
1248	1233	sl 0
1249	1234	ro 270
1250		xt "~~42500,34625,44~~000,35375"
	1235	xt "36500,34625,38000,35375"
1251	1236	)
1252	1237	(Line
…	…
1254	1239	sl 0
1255	1240	ro 270
1256		xt "~~42000,35000,42~~500,35000"
	1241	xt "36000,35000,36500,35000"
1257	1242	pts [
1258		"42000,35000"
1259		"42500,35000"
	1243	"36000,35000"
	1244	"36500,35000"
1260	1245	]
1261	1246	)
…	…
1272	1257	va (VaSet
1273	1258	)
1274		xt "~~45000,34500,48~~400,35500"
	1259	xt "39000,34500,42400,35500"
1275	1260	st "roi_array"
1276		blo "45000,35300"
	1261	blo "39000,35300"
1277	1262	tm "WireNameMgr"
1278	1263	)
…	…
1292	1277	sl 0
1293	1278	ro 270
1294		xt "~~42500,31625,44~~000,32375"
	1279	xt "36500,31625,38000,32375"
1295	1280	)
1296	1281	(Line
…	…
1298	1283	sl 0
1299	1284	ro 270
1300		xt "~~42000,32000,42~~500,32000"
	1285	xt "36000,32000,36500,32000"
1301	1286	pts [
1302		"42000,32000"
1303		"42500,32000"
	1287	"36000,32000"
	1288	"36500,32000"
1304	1289	]
1305	1290	)
…	…
1316	1301	va (VaSet
1317	1302	)
1318		xt "~~45000,31500,51~~600,32500"
	1303	xt "39000,31500,45600,32500"
1319	1304	st "config_data_valid"
1320		blo "45000,32300"
	1305	blo "39000,32300"
1321	1306	tm "WireNameMgr"
1322	1307	)
…	…
1336	1321	sl 0
1337	1322	ro 270
1338		xt "~~42500,32625,44~~000,33375"
	1323	xt "36500,32625,38000,33375"
1339	1324	)
1340	1325	(Line
…	…
1342	1327	sl 0
1343	1328	ro 270
1344		xt "~~42000,33000,42~~500,33000"
	1329	xt "36000,33000,36500,33000"
1345	1330	pts [
1346		"42000,33000"
1347		"42500,33000"
	1331	"36000,33000"
	1332	"36500,33000"
1348	1333	]
1349	1334	)
…	…
1360	1345	va (VaSet
1361	1346	)
1362		xt "~~45000,32500,49~~800,33500"
	1347	xt "39000,32500,43800,33500"
1363	1348	st "config_busy"
1364		blo "45000,33300"
	1349	blo "39000,33300"
1365	1350	tm "WireNameMgr"
1366	1351	)
…	…
1380	1365	fg "0,65535,0"
1381	1366	)
1382		xt "~~12250,23625,13~~000,24375"
	1367	xt "6250,23625,7000,24375"
1383	1368	)
1384	1369	tg (CPTG
…	…
1390	1375	va (VaSet
1391	1376	)
1392		xt "~~14000,23500,15~~300,24500"
	1377	xt "8000,23500,9300,24500"
1393	1378	st "clk"
1394		blo "14000,24300"
	1379	blo "8000,24300"
1395	1380	)
1396	1381	)
…	…
1416	1401	fg "0,65535,0"
1417	1402	)
1418		xt "3~~8000,28625,38~~750,29375"
	1403	xt "32000,28625,32750,29375"
1419	1404	)
1420	1405	tg (CPTG
…	…
1426	1411	va (VaSet
1427	1412	)
1428		xt "~~31900,28500,37~~000,29500"
	1413	xt "25900,28500,31000,29500"
1429	1414	st "config_ready"
1430	1415	ju 2
1431		blo "37000,29300"
	1416	blo "31000,29300"
1432	1417	)
1433	1418	)
…	…
1455	1440	fg "0,65535,0"
1456	1441	)
1457		xt "3~~8000,29625,38~~750,30375"
	1442	xt "32000,29625,32750,30375"
1458	1443	)
1459	1444	tg (CPTG
…	…
1465	1450	va (VaSet
1466	1451	)
1467		xt "~~32200,29500,37~~000,30500"
	1452	xt "26200,29500,31000,30500"
1468	1453	st "config_start"
1469	1454	ju 2
1470		blo "37000,30300"
	1455	blo "31000,30300"
1471	1456	)
1472	1457	)
…	…
1492	1477	fg "0,65535,0"
1493	1478	)
1494		xt "3~~8000,24625,38~~750,25375"
	1479	xt "32000,24625,32750,25375"
1495	1480	)
1496	1481	tg (CPTG
…	…
1502	1487	va (VaSet
1503	1488	)
1504		xt "2~~9300,24500,37~~000,25500"
	1489	xt "23300,24500,31000,25500"
1505	1490	st "config_data : (15:0)"
1506	1491	ju 2
1507		blo "37000,25300"
	1492	blo "31000,25300"
1508	1493	)
1509	1494	)
…	…
1532	1517	fg "0,65535,0"
1533	1518	)
1534		xt "3~~8000,23625,38~~750,24375"
	1519	xt "32000,23625,32750,24375"
1535	1520	)
1536	1521	tg (CPTG
…	…
1542	1527	va (VaSet
1543	1528	)
1544		xt "~~23600,23500,37~~000,24500"
	1529	xt "17600,23500,31000,24500"
1545	1530	st "config_addr : (ADDR_WIDTH - 1:0)"
1546	1531	ju 2
1547		blo "37000,24300"
	1532	blo "31000,24300"
1548	1533	)
1549	1534	)
…	…
1570	1555	fg "0,65535,0"
1571	1556	)
1572		xt "3~~8000,26625,38~~750,27375"
	1557	xt "32000,26625,32750,27375"
1573	1558	)
1574	1559	tg (CPTG
…	…
1580	1565	va (VaSet
1581	1566	)
1582		xt "~~31700,26500,37~~000,27500"
	1567	xt "25700,26500,31000,27500"
1583	1568	st "config_wr_en"
1584	1569	ju 2
1585		blo "37000,27300"
	1570	blo "31000,27300"
1586	1571	)
1587	1572	)
…	…
1607	1592	fg "0,65535,0"
1608	1593	)
1609		xt "3~~8000,27625,38~~750,28375"
	1594	xt "32000,27625,32750,28375"
1610	1595	)
1611	1596	tg (CPTG
…	…
1617	1602	va (VaSet
1618	1603	)
1619		xt "~~31800,27500,37~~000,28500"
	1604	xt "25800,27500,31000,28500"
1620	1605	st "config_rd_en"
1621	1606	ju 2
1622		blo "37000,28300"
	1607	blo "31000,28300"
1623	1608	)
1624	1609	)
…	…
1644	1629	fg "0,65535,0"
1645	1630	)
1646		xt "3~~8000,31625,38~~750,32375"
	1631	xt "32000,31625,32750,32375"
1647	1632	)
1648	1633	tg (CPTG
…	…
1654	1639	va (VaSet
1655	1640	)
1656		xt "~~30400,31500,37~~000,32500"
	1641	xt "24400,31500,31000,32500"
1657	1642	st "config_data_valid"
1658	1643	ju 2
1659		blo "37000,32300"
	1644	blo "31000,32300"
1660	1645	)
1661	1646	)
…	…
1683	1668	fg "0,65535,0"
1684	1669	)
1685		xt "3~~8000,32625,38~~750,33375"
	1670	xt "32000,32625,32750,33375"
1686	1671	)
1687	1672	tg (CPTG
…	…
1693	1678	va (VaSet
1694	1679	)
1695		xt "~~32200,32500,37~~000,33500"
	1680	xt "26200,32500,31000,33500"
1696	1681	st "config_busy"
1697	1682	ju 2
1698		blo "37000,33300"
	1683	blo "31000,33300"
1699	1684	)
1700	1685	)
…	…
1722	1707	fg "0,65535,0"
1723	1708	)
1724		xt "3~~8000,33625,38~~750,34375"
	1709	xt "32000,33625,32750,34375"
1725	1710	)
1726	1711	tg (CPTG
…	…
1732	1717	va (VaSet
1733	1718	)
1734		xt "~~33300,33500,37~~000,34500"
	1719	xt "27300,33500,31000,34500"
1735	1720	st "dac_array"
1736	1721	ju 2
1737		blo "37000,34300"
	1722	blo "31000,34300"
1738	1723	)
1739	1724	)
…	…
1760	1745	fg "0,65535,0"
1761	1746	)
1762		xt "3~~8000,34625,38~~750,35375"
	1747	xt "32000,34625,32750,35375"
1763	1748	)
1764	1749	tg (CPTG
…	…
1770	1755	va (VaSet
1771	1756	)
1772		xt "~~33600,34500,37~~000,35500"
	1757	xt "27600,34500,31000,35500"
1773	1758	st "roi_array"
1774	1759	ju 2
1775		blo "37000,35300"
	1760	blo "31000,35300"
1776	1761	)
1777	1762	)
…	…
1798	1783	fg "0,65535,0"
1799	1784	)
1800		xt "3~~8000,37625,38~~750,38375"
	1785	xt "32000,37625,32750,38375"
1801	1786	)
1802	1787	tg (CPTG
…	…
1808	1793	va (VaSet
1809	1794	)
1810		xt "2~~9100,37500,37~~000,38500"
	1795	xt "23100,37500,31000,38500"
1811	1796	st "ram_data_in : (15:0)"
1812	1797	ju 2
1813		blo "37000,38300"
	1798	blo "31000,38300"
1814	1799	)
1815	1800	)
…	…
1835	1820	fg "0,65535,0"
1836	1821	)
1837		xt "3~~8000,38625,38~~750,39375"
	1822	xt "32000,38625,32750,39375"
1838	1823	)
1839	1824	tg (CPTG
…	…
1845	1830	va (VaSet
1846	1831	)
1847		xt "2~~9100,38500,37~~000,39500"
	1832	xt "23100,38500,31000,39500"
1848	1833	st "ram_write_en : (0:0)"
1849	1834	ju 2
1850		blo "37000,39300"
	1835	blo "31000,39300"
1851	1836	)
1852	1837	)
…	…
1872	1857	fg "0,65535,0"
1873	1858	)
1874		xt "~~12250,24625,13000,25~~375"
	1859	xt "6250,38625,7000,39375"
1875	1860	)
1876	1861	tg (CPTG
…	…
1882	1867	va (VaSet
1883	1868	)
1884		xt "~~14000,24500,22300,25~~500"
	1869	xt "8000,38500,16300,39500"
1885	1870	st "ram_data_out : (15:0)"
1886		blo "~~14000,25~~300"
	1871	blo "8000,39300"
1887	1872	)
1888	1873	)
…	…
1907	1892	fg "0,65535,0"
1908	1893	)
1909		xt "3~~8000,39625,38~~750,40375"
	1894	xt "32000,39625,32750,40375"
1910	1895	)
1911	1896	tg (CPTG
…	…
1917	1902	va (VaSet
1918	1903	)
1919		xt "~~24400,39500,37~~000,40500"
	1904	xt "18400,39500,31000,40500"
1920	1905	st "ram_addr : (ADDR_WIDTH - 1:0)"
1921	1906	ju 2
1922		blo "37000,40300"
	1907	blo "31000,40300"
1923	1908	)
1924	1909	)
…	…
1944	1929	fg "0,65535,0"
1945	1930	)
1946		xt "3~~8000,30625,38~~750,31375"
	1931	xt "32000,30625,32750,31375"
1947	1932	)
1948	1933	tg (CPTG
…	…
1954	1939	va (VaSet
1955	1940	)
1956		xt "~~31400,30500,37~~000,31500"
	1941	xt "25400,30500,31000,31500"
1957	1942	st "config_started"
1958	1943	ju 2
1959		blo "37000,31300"
	1944	blo "31000,31300"
1960	1945	)
1961	1946	)
…	…
1980	1965	lineWidth 2
1981	1966	)
1982		xt "~~13000,23000,38~~000,42000"
	1967	xt "7000,23000,32000,42000"
1983	1968	)
1984	1969	oxt "42000,14000,67000,32000"
…	…
1993	1978	font "Arial,8,1"
1994	1979	)
1995		xt "~~12950,42000,19~~150,43000"
	1980	xt "6950,42000,13150,43000"
1996	1981	st "FACT_FAD_lib"
1997		blo "12950,42800"
	1982	blo "6950,42800"
1998	1983	tm "BdLibraryNameMgr"
1999	1984	)
…	…
2003	1988	font "Arial,8,1"
2004	1989	)
2005		xt "~~12950,43000,20~~050,44000"
	1990	xt "6950,43000,14050,44000"
2006	1991	st "control_manager"
2007		blo "12950,43800"
	1992	blo "6950,43800"
2008	1993	tm "CptNameMgr"
2009	1994	)
…	…
2013	1998	font "Arial,8,1"
2014	1999	)
2015		xt "~~12950,44000,20~~650,45000"
	2000	xt "6950,44000,14650,45000"
2016	2001	st "I_control_manager"
2017		blo "12950,44800"
	2002	blo "6950,44800"
2018	2003	tm "InstanceNameMgr"
2019	2004	)
…	…
2030	2015	font "Courier New,8,0"
2031	2016	)
2032		xt "1~~2500,10600,30000,1~~3000"
	2017	xt "10000,20600,27500,23000"
2033	2018	st "NO_OF_ROI = 36 ( integer )
2034	2019	NO_OF_DAC = 8 ( integer )
…	…
2062	2047	fg "49152,49152,49152"
2063	2048	)
2064		xt "~~13250,40250,14~~750,41750"
	2049	xt "7250,40250,8750,41750"
2065	2050	iconName "VhdlFileViewIcon.png"
2066	2051	iconMaskName "VhdlFileViewIcon.msk"
…	…
2081	2066	shape (Triangle
2082	2067	uid 971,0
2083		ro 90
	2068	ro 180
2084	2069	va (VaSet
2085	2070	vasetType 1
2086	2071	fg "0,65535,0"
2087	2072	)
2088		xt "~~19250,50625,20000,51375~~"
	2073	xt "42625,41250,43375,42000"
2089	2074	)
2090	2075	tg (CPTG
2091	2076	uid 972,0
2092	2077	ps "CptPortTextPlaceStrategy"
2093		stg "VerticalLayoutStrategy"
	2078	stg "RightVerticalLayoutStrategy"
2094	2079	f (Text
2095	2080	uid 973,0
2096		va (VaSet
2097		)
2098		xt "21000,50500,22700,51500"
	2081	ro 270
	2082	va (VaSet
	2083	)
	2084	xt "42500,43000,43500,44700"
2099	2085	st "clka"
2100		blo "21000,51300"
	2086	ju 2
	2087	blo "43300,43000"
2101	2088	)
2102	2089	)
…	…
2122	2109	fg "0,65535,0"
2123	2110	)
2124		xt "~~19250,52625,20000,53~~375"
	2111	xt "39250,45625,40000,46375"
2125	2112	)
2126	2113	tg (CPTG
…	…
2132	2119	va (VaSet
2133	2120	)
2134		xt "~~21000,52500,25800,53~~500"
	2121	xt "41000,45500,45800,46500"
2135	2122	st "dina : (15:0)"
2136		blo "~~21000,53~~300"
	2123	blo "41000,46300"
2137	2124	)
2138	2125	)
…	…
2159	2146	fg "0,65535,0"
2160	2147	)
2161		xt "~~19250,54625,20000,55~~375"
	2148	xt "39250,47625,40000,48375"
2162	2149	)
2163	2150	tg (CPTG
…	…
2169	2156	va (VaSet
2170	2157	)
2171		xt "~~21000,54500,25900,55~~500"
	2158	xt "41000,47500,45900,48500"
2172	2159	st "addra : (7:0)"
2173		blo "~~21000,55~~300"
	2160	blo "41000,48300"
2174	2161	)
2175	2162	)
…	…
2196	2183	fg "0,65535,0"
2197	2184	)
2198		xt "~~19250,53625,20000,54~~375"
	2185	xt "39250,46625,40000,47375"
2199	2186	)
2200	2187	tg (CPTG
…	…
2206	2193	va (VaSet
2207	2194	)
2208		xt "~~21000,53500,25300,54~~500"
	2195	xt "41000,46500,45300,47500"
2209	2196	st "wea : (0:0)"
2210		blo "~~21000,54~~300"
	2197	blo "41000,47300"
2211	2198	)
2212	2199	)
…	…
2233	2220	fg "0,65535,0"
2234	2221	)
2235		xt "~~30000,50625,30750,51~~375"
	2222	xt "50000,43625,50750,44375"
2236	2223	)
2237	2224	tg (CPTG
…	…
2243	2230	va (VaSet
2244	2231	)
2245		xt "~~23800,50500,29000,51~~500"
	2232	xt "43800,43500,49000,44500"
2246	2233	st "douta : (15:0)"
2247	2234	ju 2
2248		blo "~~29000,51~~300"
	2235	blo "49000,44300"
2249	2236	)
2250	2237	)
…	…
2271	2258	lineWidth 2
2272	2259	)
2273		xt "~~20000,49000,30000,59~~000"
	2260	xt "40000,42000,50000,52000"
2274	2261	)
2275	2262	oxt "30000,7000,40000,17000"
…	…
2284	2271	font "Arial,8,1"
2285	2272	)
2286		xt "~~20200,59000,26400,60~~000"
	2273	xt "40200,52000,46400,53000"
2287	2274	st "FACT_FAD_lib"
2288		blo "~~20200,59~~800"
	2275	blo "40200,52800"
2289	2276	tm "BdLibraryNameMgr"
2290	2277	)
…	…
2294	2281	font "Arial,8,1"
2295	2282	)
2296		xt "~~20200,60000,30100,61~~000"
	2283	xt "40200,53000,50100,54000"
2297	2284	st "controlRAM_16bit_x256"
2298		blo "~~20200,60~~800"
	2285	blo "40200,53800"
2299	2286	tm "CptNameMgr"
2300	2287	)
…	…
2304	2291	font "Arial,8,1"
2305	2292	)
2306		xt "~~20200,61000,26100,62~~000"
	2293	xt "40200,54000,46100,55000"
2307	2294	st "I_control_ram"
2308		blo "~~20200,61~~800"
	2295	blo "40200,54800"
2309	2296	tm "InstanceNameMgr"
2310	2297	)
…	…
2321	2308	font "Courier New,8,0"
2322	2309	)
2323		xt "~~19500,48000,19500,48~~000"
	2310	xt "39500,41000,39500,41000"
2324	2311	)
2325	2312	header ""
…	…
2335	2322	fg "49152,49152,49152"
2336	2323	)
2337		xt "20250,57250,21750,58750"
2338		iconName "UnknownFile.png"
2339		iconMaskName "UnknownFile.msk"
	2324	xt "40250,50250,41750,51750"
	2325	iconName "VhdlFileViewIcon.png"
	2326	iconMaskName "VhdlFileViewIcon.msk"
	2327	ftype 10
2340	2328	)
2341	2329	ordering 1
…	…
2360	2348	font "Courier New,8,0"
2361	2349	)
2362		xt "22000,8400,41500,9200"
2363		st "config_started : std_logic := '0'
2364		"
	2350	xt "29000,8600,48500,9400"
	2351	st "config_started : std_logic := '0'"
2365	2352	)
2366	2353	)
…	…
2378	2365	sl 0
2379	2366	ro 270
2380		xt "~~42500,30625,44~~000,31375"
	2367	xt "36500,30625,38000,31375"
2381	2368	)
2382	2369	(Line
…	…
2384	2371	sl 0
2385	2372	ro 270
2386		xt "~~42000,31000,42~~500,31000"
	2373	xt "36000,31000,36500,31000"
2387	2374	pts [
2388		"42000,31000"
2389		"42500,31000"
	2375	"36000,31000"
	2376	"36500,31000"
2390	2377	]
2391	2378	)
…	…
2402	2389	va (VaSet
2403	2390	)
2404		xt "~~45000,30500,50~~600,31500"
	2391	xt "39000,30500,44600,31500"
2405	2392	st "config_started"
2406		blo "45000,31300"
	2393	blo "39000,31300"
2407	2394	tm "WireNameMgr"
2408	2395	)
…	…
2417	2404	lineWidth 2
2418	2405	)
2419		xt "3~~8750,24000,42~~000,24000"
	2406	xt "32750,24000,36000,24000"
2420	2407	pts [
2421		"42000,24000"
2422		"40000,24000"
2423		"38750,24000"
	2408	"36000,24000"
	2409	"32750,24000"
2424	2410	]
2425	2411	)
…	…
2442	2428	isHidden 1
2443	2429	)
2444		xt "~~45000,23000,49~~800,24000"
	2430	xt "39000,23000,43800,24000"
2445	2431	st "config_addr"
2446		blo "45000,23800"
	2432	blo "39000,23800"
2447	2433	tm "WireNameMgr"
2448	2434	)
…	…
2458	2444	lineWidth 2
2459	2445	)
2460		xt "~~13000,39000,43000,54~~000"
	2446	xt "32750,39000,39250,47000"
2461	2447	pts [
2462		"19250,54000"
2463		"13000,54000"
2464		"13000,47000"
2465		"43000,47000"
2466		"43000,39000"
2467		"38750,39000"
	2448	"39250,47000"
	2449	"34000,47000"
	2450	"34000,39000"
	2451	"32750,39000"
2468	2452	]
2469	2453	)
…	…
2484	2468	va (VaSet
2485	2469	)
2486		xt "~~23000,46000,29~~300,47000"
	2470	xt "34000,46000,40300,47000"
2487	2471	st "ram_wren : (0:0)"
2488		blo "23000,46800"
	2472	blo "34000,46800"
2489	2473	tm "WireNameMgr"
2490	2474	)
…	…
2500	2484	lineWidth 2
2501	2485	)
2502		xt "~~14000,38000,44000,53~~000"
	2486	xt "32750,38000,39250,46000"
2503	2487	pts [
2504		"19250,53000"
2505		"14000,53000"
2506		"14000,48000"
2507		"44000,48000"
2508		"44000,38000"
2509		"38750,38000"
	2488	"39250,46000"
	2489	"35000,46000"
	2490	"35000,38000"
	2491	"32750,38000"
2510	2492	]
2511	2493	)
…	…
2526	2508	va (VaSet
2527	2509	)
2528		xt "~~23000,47000,30900,4~~8000"
	2510	xt "33000,37000,40900,38000"
2529	2511	st "ram_data_in : (15:0)"
2530		blo "~~23000,4~~7800"
	2512	blo "33000,37800"
2531	2513	tm "WireNameMgr"
2532	2514	)
…	…
2541	2523	vasetType 3
2542	2524	)
2543		xt "~~5000,24000,12~~250,24000"
	2525	xt "4000,20000,6250,24000"
2544	2526	pts [
	2527	"4000,20000"
	2528	"5000,20000"
2545	2529	"5000,24000"
2546		"12250,24000"
	2530	"6250,24000"
2547	2531	]
2548	2532	)
…	…
2564	2548	isHidden 1
2565	2549	)
2566		xt "~~7000,23000,8300,24~~000"
	2550	xt "6000,19000,7300,20000"
2567	2551	st "clk"
2568		blo "~~7000,23~~800"
	2552	blo "6000,19800"
2569	2553	tm "WireNameMgr"
2570	2554	)
…	…
2579	2563	vasetType 3
2580	2564	)
2581		xt "3~~8750,32000,42~~000,32000"
	2565	xt "32750,32000,36000,32000"
2582	2566	pts [
2583		"38750,32000"
2584		"42000,32000"
	2567	"32750,32000"
	2568	"36000,32000"
2585	2569	]
2586	2570	)
…	…
2602	2586	isHidden 1
2603	2587	)
2604		xt "~~45000,30000,51~~600,31000"
	2588	xt "39000,30000,45600,31000"
2605	2589	st "config_data_valid"
2606		blo "45000,30800"
	2590	blo "39000,30800"
2607	2591	tm "WireNameMgr"
2608	2592	)
…	…
2617	2601	vasetType 3
2618	2602	)
2619		xt "3~~8750,33000,42~~000,33000"
	2603	xt "32750,33000,36000,33000"
2620	2604	pts [
2621		"38750,33000"
2622		"42000,33000"
	2605	"32750,33000"
	2606	"36000,33000"
2623	2607	]
2624	2608	)
…	…
2640	2624	isHidden 1
2641	2625	)
2642		xt "~~45000,31000,49~~800,32000"
	2626	xt "39000,31000,43800,32000"
2643	2627	st "config_busy"
2644		blo "45000,31800"
	2628	blo "39000,31800"
2645	2629	tm "WireNameMgr"
2646	2630	)
…	…
2656	2640	lineWidth 2
2657	2641	)
2658		xt "3~~8750,25000,42~~000,25000"
	2642	xt "32750,25000,36000,25000"
2659	2643	pts [
2660		"42000,25000"
2661		"40000,25000"
2662		"38750,25000"
	2644	"36000,25000"
	2645	"32750,25000"
2663	2646	]
2664	2647	)
…	…
2681	2664	isHidden 1
2682	2665	)
2683		xt "~~45000,24000,49~~700,25000"
	2666	xt "39000,24000,43700,25000"
2684	2667	st "config_data"
2685		blo "45000,24800"
	2668	blo "39000,24800"
2686	2669	tm "WireNameMgr"
2687	2670	)
…	…
2696	2679	vasetType 3
2697	2680	)
2698		xt "3~~8750,35000,42~~000,35000"
	2681	xt "32750,35000,36000,35000"
2699	2682	pts [
2700		"38750,35000"
2701		"40000,35000"
2702		"42000,35000"
	2683	"32750,35000"
	2684	"36000,35000"
2703	2685	]
2704	2686	)
…	…
2720	2702	isHidden 1
2721	2703	)
2722		xt "~~45000,34000,48~~400,35000"
	2704	xt "39000,34000,42400,35000"
2723	2705	st "roi_array"
2724		blo "45000,34800"
	2706	blo "39000,34800"
2725	2707	tm "WireNameMgr"
2726	2708	)
…	…
2735	2717	vasetType 3
2736	2718	)
2737		xt "~~17000,51000,19250,5100~~0"
	2719	xt "43000,38000,43000,41250"
2738	2720	pts [
2739		"~~17000,51~~000"
2740		"~~19250,5100~~0"
	2721	"43000,38000"
	2722	"43000,41250"
2741	2723	]
2742	2724	)
…	…
2755	2737	va (VaSet
2756	2738	)
2757		xt "~~18000,50000,19300,51~~000"
	2739	xt "44000,37000,45300,38000"
2758	2740	st "clk"
2759		blo "~~18000,50~~800"
	2741	blo "44000,37800"
2760	2742	tm "WireNameMgr"
2761	2743	)
…	…
2771	2753	lineWidth 2
2772	2754	)
2773		xt "~~12000,40000,42000,55~~000"
	2755	xt "32750,40000,39250,48000"
2774	2756	pts [
2775		"38750,40000"
2776		"42000,40000"
2777		"42000,46000"
2778		"12000,46000"
2779		"12000,55000"
2780		"19250,55000"
	2757	"32750,40000"
	2758	"33000,40000"
	2759	"33000,48000"
	2760	"39250,48000"
2781	2761	]
2782	2762	)
…	…
2797	2777	va (VaSet
2798	2778	)
2799		xt "~~23000,45000,29200,46~~000"
	2779	xt "33000,47000,39200,48000"
2800	2780	st "ram_addr : (7:0)"
2801		blo "~~23000,45~~800"
	2781	blo "33000,47800"
2802	2782	tm "WireNameMgr"
2803	2783	)
…	…
2812	2792	vasetType 3
2813	2793	)
2814		xt "3~~8750,30000,42~~000,30000"
	2794	xt "32750,30000,36000,30000"
2815	2795	pts [
2816		"42000,30000"
2817		"40000,30000"
2818		"38750,30000"
	2796	"36000,30000"
	2797	"32750,30000"
2819	2798	]
2820	2799	)
…	…
2836	2815	isHidden 1
2837	2816	)
2838		xt "~~45000,29000,49~~800,30000"
	2817	xt "39000,29000,43800,30000"
2839	2818	st "config_start"
2840		blo "45000,29800"
	2819	blo "39000,29800"
2841	2820	tm "WireNameMgr"
2842	2821	)
…	…
2851	2830	vasetType 3
2852	2831	)
2853		xt "3~~8750,27000,42~~000,27000"
	2832	xt "32750,27000,36000,27000"
2854	2833	pts [
2855		"42000,27000"
2856		"40000,27000"
2857		"38750,27000"
	2834	"36000,27000"
	2835	"32750,27000"
2858	2836	]
2859	2837	)
…	…
2875	2853	isHidden 1
2876	2854	)
2877		xt "~~45000,26000,50~~300,27000"
	2855	xt "39000,26000,44300,27000"
2878	2856	st "config_wr_en"
2879		blo "45000,26800"
	2857	blo "39000,26800"
2880	2858	tm "WireNameMgr"
2881	2859	)
…	…
2891	2869	lineWidth 2
2892	2870	)
2893		xt "~~9000,25000,34000,64~~000"
	2871	xt "3000,39000,52000,56000"
2894	2872	pts [
2895		"~~12250,25~~000"
2896		"~~9000,25~~000"
2897		"~~9000,64~~000"
2898		"~~34000,64~~000"
2899		"~~34000,51~~000"
2900		"~~30750,51~~000"
	2873	"6250,39000"
	2874	"3000,39000"
	2875	"3000,56000"
	2876	"52000,56000"
	2877	"52000,44000"
	2878	"50750,44000"
2901	2879	]
2902	2880	)
…	…
2917	2895	va (VaSet
2918	2896	)
2919		xt "~~20000,63000,28300,64~~000"
	2897	xt "33000,55000,41300,56000"
2920	2898	st "ram_data_out : (15:0)"
2921		blo "~~20000,63~~800"
	2899	blo "33000,55800"
2922	2900	tm "WireNameMgr"
2923	2901	)
…	…
2932	2910	vasetType 3
2933	2911	)
2934		xt "3~~8750,34000,42~~000,34000"
	2912	xt "32750,34000,36000,34000"
2935	2913	pts [
2936		"38750,34000"
2937		"40000,34000"
2938		"42000,34000"
	2914	"32750,34000"
	2915	"36000,34000"
2939	2916	]
2940	2917	)
…	…
2956	2933	isHidden 1
2957	2934	)
2958		xt "~~45000,33000,48~~700,34000"
	2935	xt "39000,33000,42700,34000"
2959	2936	st "dac_array"
2960		blo "45000,33800"
	2937	blo "39000,33800"
2961	2938	tm "WireNameMgr"
2962	2939	)
…	…
2971	2948	vasetType 3
2972	2949	)
2973		xt "3~~8750,28000,42~~000,28000"
	2950	xt "32750,28000,36000,28000"
2974	2951	pts [
2975		"42000,28000"
2976		"40000,28000"
2977		"38750,28000"
	2952	"36000,28000"
	2953	"32750,28000"
2978	2954	]
2979	2955	)
…	…
2995	2971	isHidden 1
2996	2972	)
2997		xt "~~45000,27000,50~~200,28000"
	2973	xt "39000,27000,44200,28000"
2998	2974	st "config_rd_en"
2999		blo "45000,27800"
	2975	blo "39000,27800"
3000	2976	tm "WireNameMgr"
3001	2977	)
…	…
3010	2986	vasetType 3
3011	2987	)
3012		xt "3~~8750,29000,42~~000,29000"
	2988	xt "32750,29000,36000,29000"
3013	2989	pts [
3014		"38750,29000"
3015		"40000,29000"
3016		"42000,29000"
	2990	"32750,29000"
	2991	"36000,29000"
3017	2992	]
3018	2993	)
…	…
3034	3009	isHidden 1
3035	3010	)
3036		xt "~~45000,28000,50~~100,29000"
	3011	xt "39000,28000,44100,29000"
3037	3012	st "config_ready"
3038		blo "45000,28800"
	3013	blo "39000,28800"
3039	3014	tm "WireNameMgr"
3040	3015	)
…	…
3049	3024	vasetType 3
3050	3025	)
3051		xt "3~~8750,31000,42~~000,31000"
	3026	xt "32750,31000,36000,31000"
3052	3027	pts [
3053		"38750,31000"
3054		"42000,31000"
	3028	"32750,31000"
	3029	"36000,31000"
3055	3030	]
3056	3031	)
…	…
3072	3047	isHidden 1
3073	3048	)
3074		xt "~~40000,30000,45~~600,31000"
	3049	xt "34000,30000,39600,31000"
3075	3050	st "config_started"
3076		blo "40000,30800"
	3051	blo "34000,30800"
3077	3052	tm "WireNameMgr"
3078	3053	)
…	…
3101	3076	font "arial,8,1"
3102	3077	)
3103		xt "~~0,0,5400,1~~000"
	3078	xt "1000,1000,6400,2000"
3104	3079	st "Package List"
3105		blo "0,800"
	3080	blo "1000,1800"
3106	3081	)
3107	3082	*88 (MLText
…	…
3109	3084	va (VaSet
3110	3085	)
3111		xt "~~0,1000,15300,6~~000"
	3086	xt "1000,2000,16300,7000"
3112	3087	st "LIBRARY ieee;
3113	3088	USE ieee.std_logic_1164.ALL;
…	…
3192	3167	associable 1
3193	3168	)
3194		windowSize "0,~~22,1286,1024~~"
3195		viewArea "~~834,16774,54098,59806~~"
3196		cachedDiagramExtent "~~0,0,53~~000,77000"
	3169	windowSize "0,0,1281,1002"
	3170	viewArea "-6400,12035,60443,65774"
	3171	cachedDiagramExtent "700,0,59000,77000"
3197	3172	pageSetupInfo (PageSetupInfo
3198	3173	ptrCmd "Brother HL-5270DN series,winspool,"
…	…
3220	3195	hasePageBreakOrigin 1
3221	3196	pageBreakOrigin "0,0"
3222		lastUid 1122,0
	3197	lastUid 1172,0
3223	3198	defaultCommentText (CommentText
3224	3199	shape (Rectangle
…	…
4167	4142	font "Arial,8,1"
4168	4143	)
4169		xt "2~~0000,0,25400,10~~00"
	4144	xt "27000,200,32400,1200"
4170	4145	st "Declarations"
4171		blo "2~~0000,8~~00"
	4146	blo "27000,1000"
4172	4147	)
4173	4148	portLabel (Text
…	…
4176	4151	font "Arial,8,1"
4177	4152	)
4178		xt "2~~0000,1000,22700,20~~00"
	4153	xt "27000,1200,29700,2200"
4179	4154	st "Ports:"
4180		blo "2~~0000,18~~00"
	4155	blo "27000,2000"
4181	4156	)
4182	4157	preUserLabel (Text
…	…
4186	4161	font "Arial,8,1"
4187	4162	)
4188		xt "2~~0000,0,23800,10~~00"
	4163	xt "27000,200,30800,1200"
4189	4164	st "Pre User:"
4190		blo "2~~0000,8~~00"
	4165	blo "27000,1000"
4191	4166	)
4192	4167	preUserText (MLText
…	…
4196	4171	font "Courier New,8,0"
4197	4172	)
4198		xt "2~~0000,0,20000,~~0"
	4173	xt "27000,200,27000,200"
4199	4174	tm "BdDeclarativeTextMgr"
4200	4175	)
…	…
4204	4179	font "Arial,8,1"
4205	4180	)
4206		xt "2~~0000,11600,27100,126~~00"
	4181	xt "27000,11800,34100,12800"
4207	4182	st "Diagram Signals:"
4208		blo "2~~0000,124~~00"
	4183	blo "27000,12600"
4209	4184	)
4210	4185	postUserLabel (Text
…	…
4214	4189	font "Arial,8,1"
4215	4190	)
4216		xt "2~~0000,0,24700,10~~00"
	4191	xt "27000,200,31700,1200"
4217	4192	st "Post User:"
4218		blo "2~~0000,8~~00"
	4193	blo "27000,1000"
4219	4194	)
4220	4195	postUserText (MLText
…	…
4224	4199	font "Courier New,8,0"
4225	4200	)
4226		xt "2~~0000,0,20000,~~0"
	4201	xt "27000,200,27000,200"
4227	4202	tm "BdDeclarativeTextMgr"
4228	4203	)

FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/symbol.sb

-              r246
+              r252
+)
 version "24.1"
 appVersion "2009.1 (Build 12)"
+appVersion "2009.2 (Build 10)"
 model (Symbol
 commonDM (CommonDM
 ldm (LogicalDM
 suid 12,0
+suid 14,0
 usingSuid 1
 emptyRow *1 (LEmptyRow
 …
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
 o 12
+o 14
 suid 5,0
+)
 …
 n "roi_array"
 t "roi_array_type"
 o 11
+o 13
 suid 6,0
+)
 …
 uid 349,0
+)
+*26 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "drs_address"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 11
+suid 13,0
+)
+)
+uid 518,0
+)
+*27 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "drs_address_mode"
+t "std_logic"
+o 12
+suid 14,0
+)
+)
+uid 520,0
+)
+]
+)
 …
 uid 66,0
 optionalChildren [
 *26 (Sheet
+*28 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
 …
 font "Tahoma,10,0"
+)
 emptyMRCItem *27 (MRCItem
+emptyMRCItem *29 (MRCItem
 litem &1
 pos 11
 …
 uid 68,0
 optionalChildren [
 *28 (MRCItem
+*30 (MRCItem
 litem &2
 pos 0
 …
 uid 69,0
+)
 *29 (MRCItem
+*31 (MRCItem
 litem &3
 pos 1
 …
 uid 70,0
+)
 *30 (MRCItem
+*32 (MRCItem
 litem &4
 pos 2
 …
 uid 71,0
+)
 *31 (MRCItem
+*33 (MRCItem
 litem &14
 pos 0
 …
 uid 108,0
+)
 *32 (MRCItem
+*34 (MRCItem
 litem &15
 pos 1
 …
 uid 110,0
+)
 *33 (MRCItem
+*35 (MRCItem
 litem &16
 pos 2
 …
 uid 112,0
+)
 *34 (MRCItem
+*36 (MRCItem
 litem &17
 pos 3
 …
 uid 114,0
+)
 *35 (MRCItem
+*37 (MRCItem
 litem &18
 pos 4
 …
 uid 116,0
+)
 *36 (MRCItem
+*38 (MRCItem
 litem &19
 pos 5
 …
 uid 118,0
+)
 *37 (MRCItem
+*39 (MRCItem
 litem &20
 pos 6
 …
 uid 120,0
+)
 *38 (MRCItem
+*40 (MRCItem
 litem &21
 pos 7
 …
 uid 122,0
+)
 *39 (MRCItem
+*41 (MRCItem
 litem &22
 pos 8
 …
 uid 124,0
+)
 *40 (MRCItem
+*42 (MRCItem
 litem &23
 pos 9
 …
 uid 126,0
+)
 *41 (MRCItem
+*43 (MRCItem
 litem &24
 pos 10
 …
 uid 128,0
+)
 *42 (MRCItem
+*44 (MRCItem
 litem &25
 pos 11
 dimension 20
 uid 348,0
+)
+*45 (MRCItem
+litem &26
+pos 12
+dimension 20
+uid 517,0
+)
+*46 (MRCItem
+litem &27
+pos 13
+dimension 20
+uid 519,0
+)
+]
 …
 uid 72,0
 optionalChildren [
 *43 (MRCItem
+*47 (MRCItem
 litem &5
 pos 0
 …
 uid 73,0
+)
 *44 (MRCItem
+*48 (MRCItem
 litem &7
 pos 1
 …
 uid 74,0
+)
 *45 (MRCItem
+*49 (MRCItem
 litem &8
 pos 2
 …
 uid 75,0
+)
 *46 (MRCItem
+*50 (MRCItem
 litem &9
 pos 3
 …
 uid 76,0
+)
 *47 (MRCItem
+*51 (MRCItem
 litem &10
 pos 4
 …
 uid 77,0
+)
 *48 (MRCItem
+*52 (MRCItem
 litem &11
 pos 5
 …
 uid 78,0
+)
 *49 (MRCItem
+*53 (MRCItem
 litem &12
 pos 6
 …
 uid 79,0
+)
 *50 (MRCItem
+*54 (MRCItem
 litem &13
 pos 7
 …
 genericsCommonDM (CommonDM
 ldm (LogicalDM
 emptyRow *51 (LEmptyRow
+emptyRow *55 (LEmptyRow
+)
 uid 82,0
 optionalChildren [
 *52 (RefLabelRowHdr
+)
 *53 (TitleRowHdr
+)
 *54 (FilterRowHdr
+)
 *55 (RefLabelColHdr
+*56 (RefLabelRowHdr
+)
+*57 (TitleRowHdr
+)
+*58 (FilterRowHdr
+)
+*59 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
+)
 *56 (RowExpandColHdr
+*60 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
+)
 *57 (GroupColHdr
+*61 (GroupColHdr
 tm "GroupColHdrMgr"
+)
 *58 (NameColHdr
+*62 (NameColHdr
 tm "GenericNameColHdrMgr"
+)
 *59 (TypeColHdr
+*63 (TypeColHdr
 tm "GenericTypeColHdrMgr"
+)
 *60 (InitColHdr
+*64 (InitColHdr
 tm "GenericValueColHdrMgr"
+)
 *61 (PragmaColHdr
+*65 (PragmaColHdr
 tm "GenericPragmaColHdrMgr"
+)
 *62 (EolColHdr
+*66 (EolColHdr
 tm "GenericEolColHdrMgr"
+)
 …
 uid 94,0
 optionalChildren [
 *63 (Sheet
+*67 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
 …
 font "Tahoma,10,0"
+)
 emptyMRCItem *64 (MRCItem
 litem &51
+emptyMRCItem *68 (MRCItem
+litem &55
 pos 0
 dimension 20
 …
 uid 96,0
 optionalChildren [
 *65 (MRCItem
 litem &52
+*69 (MRCItem
+litem &56
 pos 0
 dimension 20
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+)
 *66 (MRCItem
 litem &53
+*70 (MRCItem
+litem &57
 pos 1
 dimension 23
 uid 98,0
+)
 *67 (MRCItem
 litem &54
+*71 (MRCItem
+litem &58
 pos 2
 hidden 1
 …
 uid 100,0
 optionalChildren [
 *68 (MRCItem
 litem &55
+*72 (MRCItem
+litem &59
 pos 0
 dimension 20
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+)
 *69 (MRCItem
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+litem &61
 pos 1
 dimension 50
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+)
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+litem &62
 pos 2
 dimension 100
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+)
 *71 (MRCItem
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+*75 (MRCItem
+litem &63
 pos 3
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+)
 *72 (MRCItem
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+litem &64
 pos 4
 dimension 50
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+)
 *73 (MRCItem
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+litem &65
 pos 5
 dimension 50
 uid 106,0
+)
 *74 (MRCItem
 litem &62
+*78 (MRCItem
+litem &66
 pos 6
 dimension 80
 …
 (vvPair
 variable "HDLDir"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hdl"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
+)
 (vvPair
 variable "HDSDir"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
+)
 (vvPair
 variable "SideDataDesignDir"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.info"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.info"
+)
 (vvPair
 variable "SideDataUserDir"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.user"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.user"
+)
 (vvPair
 variable "SourceDir"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
+)
 (vvPair
 …
 (vvPair
 variable "d"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
+)
 (vvPair
 variable "d_logical"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
+)
 (vvPair
 variable "date"
 value "27.05.2010"
+value "12.07.2010"
+)
 (vvPair
 variable "day"
 value "Do"
+value "Mo"
+)
 (vvPair
 variable "day_long"
 value "Donnerstag"
+value "Montag"
+)
 (vvPair
 variable "dd"
 value "27"
+value "12"
+)
 (vvPair
 …
 (vvPair
 variable "host"
 value "IHP110"
+value "TU-CC4900F8C7D2"
+)
 (vvPair
 …
 (vvPair
 variable "mm"
 value "05"
+value "07"
+)
 (vvPair
 …
 (vvPair
 variable "month"
 value "Mai"
+value "Jul"
+)
 (vvPair
 variable "month_long"
 value "Mai"
+value "Juli"
+)
 (vvPair
 variable "p"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb"
+)
 (vvPair
 variable "p_logical"
 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb"
+value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb"
+)
 (vvPair
 …
 (vvPair
 variable "task_ModelSimPath"
 value "D:\\modeltech_6.5e\\win32"
+value "<TBD>"
+)
 (vvPair
 …
 (vvPair
 variable "time"
 value "10:24:05"
+value "14:13:34"
+)
 (vvPair
 …
 (vvPair
 variable "user"
 value "daqct3"
+value "dneise"
+)
 (vvPair
 variable "version"
 value "2009.1 (Build 12)"
+value "2009.2 (Build 10)"
+)
 (vvPair
 …
 uid 51,0
 optionalChildren [
 *75 (SymbolBody
+*79 (SymbolBody
 uid 8,0
 optionalChildren [
 *76 (CptPort
+*80 (CptPort
 uid 130,0
 ps "OnEdgeStrategy"
 …
+)
 xt "44000,2000,65000,2800"
+st "clk               : IN     STD_LOGIC  ;"
+st "clk               : IN     STD_LOGIC  ;
+"
+)
 thePort (LogicalPort
 …
+)
+)
 *77 (CptPort
+*81 (CptPort
 uid 135,0
 ps "OnEdgeStrategy"
 …
+)
 xt "44000,2800,75000,3600"
+st "config_addr       : IN     std_logic_vector (7 DOWNTO 0) ;"
+st "config_addr       : IN     std_logic_vector (7 DOWNTO 0) ;
+"
+)
 thePort (LogicalPort
 …
+)
+)
 *78 (CptPort
+*82 (CptPort
 uid 140,0
 ps "OnEdgeStrategy"
 …
+)
 xt "44000,6800,65000,7600"
+st "config_data_valid : OUT    std_logic  ;"
+st "config_data_valid : OUT    std_logic  ;
+"
+)
 thePort (LogicalPort
 …
+)
+)
 *79 (CptPort
+*83 (CptPort
 uid 145,0
 ps "OnEdgeStrategy"
 …
+)
 xt "44000,6000,65000,6800"
+st "config_busy       : OUT    std_logic  ;"
+st "config_busy       : OUT    std_logic  ;
+"
+)
 thePort (LogicalPort
 …
+)
+)
 *80 (CptPort
+*84 (CptPort
 uid 150,0
 ps "OnEdgeStrategy"
 …
 font "Courier New,8,0"
+)
+xt "44000,10800,74500,11600"
+st "config_data       : INOUT  std_logic_vector (15 DOWNTO 0)"
+xt "44000,12400,74500,13200"
+st "config_data       : INOUT  std_logic_vector (15 DOWNTO 0)
+"
+)
 thePort (LogicalPort
 …
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
 o 12
+o 14
 suid 5,0
+)
+)
+)
 *81 (CptPort
+*85 (CptPort
 uid 155,0
 ps "OnEdgeStrategy"
 …
 font "Courier New,8,0"
+)
+xt "44000,10000,68000,10800"
+st "roi_array         : OUT    roi_array_type  ;"
+xt "44000,11600,68000,12400"
+st "roi_array         : OUT    roi_array_type  ;
+"
+)
 thePort (LogicalPort
 …
 n "roi_array"
 t "roi_array_type"
 o 11
+o 13
 suid 6,0
+)
+)
+)
 *82 (CptPort
+*86 (CptPort
 uid 160,0
 ps "OnEdgeStrategy"
 …
+)
 xt "44000,5200,65000,6000"
+st "config_wr_en      : IN     std_logic  ;"
+st "config_wr_en      : IN     std_logic  ;
+"
+)
 thePort (LogicalPort
 …
+)
+)
 *83 (CptPort
+*87 (CptPort
 uid 165,0
 ps "OnEdgeStrategy"
 …
+)
 xt "44000,9200,68000,10000"
+st "dac_array         : OUT    dac_array_type  ;"
+st "dac_array         : OUT    dac_array_type  ;
+"
+)
 thePort (LogicalPort
 …
+)
+)
 *84 (CptPort
+*88 (CptPort
 uid 170,0
 ps "OnEdgeStrategy"
 …
+)
 xt "44000,3600,65000,4400"
+st "config_rd_en      : IN     std_logic  ;"
+st "config_rd_en      : IN     std_logic  ;
+"
+)
 thePort (LogicalPort
 …
+)
+)
 *85 (CptPort
+*89 (CptPort
 uid 175,0
 ps "OnEdgeStrategy"
 …
+)
 xt "44000,4400,65000,5200"
+st "config_start      : IN     std_logic  ;"
+st "config_start      : IN     std_logic  ;
+"
+)
 thePort (LogicalPort
 …
+)
+)
 *86 (CptPort
+*90 (CptPort
 uid 180,0
 ps "OnEdgeStrategy"
 …
+)
 xt "44000,7600,65000,8400"
+st "config_ready      : OUT    std_logic  ;"
+st "config_ready      : OUT    std_logic  ;
+"
+)
 thePort (LogicalPort
 …
+)
+)
 *87 (CptPort
+*91 (CptPort
 uid 350,0
 ps "OnEdgeStrategy"
 …
+)
 xt "44000,8400,69000,9200"
+st "config_started    : OUT    std_logic  := '0' ;"
+st "config_started    : OUT    std_logic  := '0' ;
+"
+)
 thePort (LogicalPort
 …
+)
+)
+*92 (CptPort
+uid 521,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 522,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "33000,28625,33750,29375"
+)
+tg (CPTG
+uid 523,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 524,0
+va (VaSet
+)
+xt "24800,28500,32000,29500"
+st "drs_address : (3:0)"
+ju 2
+blo "32000,29300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 525,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "44000,10000,75000,10800"
+st "drs_address       : OUT    std_logic_vector (3 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_address"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 11
+suid 13,0
+)
+)
+)
+*93 (CptPort
+uid 526,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 527,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "33000,30625,33750,31375"
+)
+tg (CPTG
+uid 528,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 529,0
+va (VaSet
+)
+xt "24800,30500,32000,31500"
+st "drs_address_mode"
+ju 2
+blo "32000,31300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 530,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "44000,10800,65000,11600"
+st "drs_address_mode  : OUT    std_logic  ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_address_mode"
+t "std_logic"
+o 12
+suid 14,0
+)
+)
+)
+]
 shape (Rectangle
 …
 lineWidth 2
+)
 xt "15000,13000,33000,28000"
+xt "15000,13000,33000,32000"
+)
 oxt "15000,13000,33000,26000"
 …
+)
+)
 gi *88 (GenericInterface
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 uid 13,0
 ps "CenterOffsetStrategy"
 …
+)
+)
 *89 (Grouping
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 uid 16,0
 optionalChildren [
 *90 (CommentText
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 uid 18,0
 shape (Rectangle
 …
 bg "0,0,32768"
+)
 xt "36200,48000,45900,49000"
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 st "
 by %user on %dd %month %year
 …
 titleBlock 1
+)
 *91 (CommentText
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 shape (Rectangle
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 titleBlock 1
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 shape (Rectangle
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 titleBlock 1
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 shape (Rectangle
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 titleBlock 1
+)
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 shape (Rectangle
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 titleBlock 1
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 shape (Rectangle
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 titleBlock 1
+)
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 shape (Rectangle
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 titleBlock 1
+)
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 shape (Rectangle
 …
 color "26368,26368,26368"
+)
 packageList *100 (PackageList
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 uid 48,0
 stg "VerticalLayoutStrategy"
 textVec [
 *101 (Text
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 va (VaSet
 …
 blo "0,800"
+)
 *102 (MLText
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 va (VaSet
 …
+)
+)
 gi *103 (GenericInterface
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 matrix (Matrix
 …
+)
+)
 DeclarativeBlock *104 (SymDeclBlock
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 uid 1,0
 stg "SymDeclLayoutStrategy"
 …
 font "Arial,8,1"
+)
 xt "42000,11600,44400,12600"
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 st "User:"
 blo "42000,12400"
+blo "42000,14000"
+)
 internalLabel (Text
 …
 font "Courier New,8,0"
+)
 xt "44000,12600,44000,12600"
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 tm "SyDeclarativeTextMgr"
+)
 …
+)
+)
 lastUid 401,0
+lastUid 530,0
 okToSyncOnLoad 1
 OkToSyncGenericsOnLoad 1

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