Index: FPGA/FTU/test_firmware/FTU_test5/FTU_test5.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test5/FTU_test5.vhd	(revision 268)
+++ FPGA/FTU/test_firmware/FTU_test5/FTU_test5.vhd	(revision 268)
@@ -0,0 +1,173 @@
+----------------------------------------------------------------------------------
+-- Company:        ETH Zurich, Institute for Particle Physics
+-- Engineer:       P. Vogler, Q. Weitzel
+-- 
+-- Create Date:    07/14/2010
+-- Design Name:    
+-- Module Name:    FTU_test5 - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description:    Test firmware for FTU board, set thresholds and enables 										
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library ftu_definitions_test5;
+USE ftu_definitions_test5.ftu_array_types.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+
+entity FTU_test5 is
+  port(
+    -- global control 
+    ext_clk   : IN  STD_LOGIC;                      -- external clock from FTU board
+    brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- geographic board/slot address
+    brd_id    : in  STD_LOGIC_VECTOR(7 downto 0);   -- local solder-programmable board ID
+
+    -- rate counters LVDS inputs
+    -- use IBUFDS differential input buffer
+    patch_A_p     : IN  STD_LOGIC;                  -- logic signal from first trigger patch
+    patch_A_n     : IN  STD_LOGIC;           
+    patch_B_p     : IN  STD_LOGIC;                  -- logic signal from second trigger patch
+    patch_B_n     : IN  STD_LOGIC;
+    patch_C_p     : IN  STD_LOGIC;                  -- logic signal from third trigger patch
+    patch_C_n     : IN  STD_LOGIC;
+    patch_D_p     : IN  STD_LOGIC;                  -- logic signal from fourth trigger patch
+    patch_D_n     : IN  STD_LOGIC;
+    trig_prim_p   : IN  STD_LOGIC;                  -- logic signal from n-out-of-4 circuit
+    trig_prim_n   : IN  STD_LOGIC;
+    
+    -- DAC interface
+    sck           : OUT STD_LOGIC;                  -- serial clock to DAC
+    mosi          : OUT STD_LOGIC;                  -- serial data to DAC, master-out-slave-in
+    clr           : OUT STD_LOGIC;                  -- clear signal to DAC
+    cs_ld         : OUT STD_LOGIC;                  -- chip select or load to DAC
+    
+    -- RS-485 interface to FTM
+    rx            : IN  STD_LOGIC;                  -- serial data from FTM
+    tx            : OUT STD_LOGIC;                  -- serial data to FTM
+    rx_en         : OUT STD_LOGIC;                  -- enable RS-485 receiver
+    tx_en         : OUT STD_LOGIC;                  -- enable RS-485 transmitter
+
+    -- analog buffer enable
+    enables_A   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
+    enables_B   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
+    enables_C   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
+    enables_D   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
+
+    -- testpoints
+    TP_A        : out STD_LOGIC_VECTOR(11 downto 0)   -- testpoints    
+  );
+end FTU_test5;
+
+
+architecture Behavioral of FTU_test5 is
+
+  component FTU_test5_dac_dcm
+    port(
+      CLKIN_IN        : IN  STD_LOGIC; 
+      RST_IN          : IN  STD_LOGIC; 
+      CLKFX_OUT       : OUT STD_LOGIC; 
+      CLKIN_IBUFG_OUT : OUT STD_LOGIC; 
+      LOCKED_OUT      : OUT STD_LOGIC
+    );
+  end component;
+  
+  component FTU_test5_dac_control
+    port(
+      clk      : IN  STD_LOGIC;
+      reset    : IN  STD_LOGIC;
+      dacs     : IN  dac_array_type;
+      clr      : OUT STD_LOGIC;
+      mosi     : OUT STD_LOGIC;
+      sck      : OUT STD_LOGIC;
+      cs_ld    : OUT STD_LOGIC
+    );
+  end component;
+
+  signal reset_sig : STD_LOGIC := '0';  -- initialize reset to 0 at power up 
+  signal clk_50M_sig : STD_LOGIC;
+
+  --signal enable_sig : enable_array_type := DEFAULT_ENABLE;
+  signal enable_sig    : enable_array_type;
+  signal dac_array_sig : dac_array_type;
+
+  type FTU_test5_StateType is (Running);
+  signal FTU_test5_State, FTU_test5_NextState: FTU_test5_StateType;
+  
+begin
+
+  Inst_FTU_test5_dac_dcm : FTU_test5_dac_dcm
+    port map(
+      CLKIN_IN => ext_clk,
+      RST_IN => reset_sig,
+      CLKFX_OUT => clk_50M_sig,
+      CLKIN_IBUFG_OUT => open,
+      LOCKED_OUT => open
+    );
+  
+  Inst_FTU_test5_dac_control : FTU_test5_dac_control
+    port map(
+      clk     => clk_50M_sig,
+      reset   => reset_sig,
+      dacs    => dac_array_sig,
+      clr     => clr,
+      mosi    => mosi,
+      sck     => sck,
+      cs_ld   => cs_ld
+    );
+
+  enable_sig <= ("0000000000000000","0000000000000000","0000000000000000","0000000000000000") when (brd_add(3 downto 0) = "0000") else
+                ("0000000101010101","0000000101010101","0000000101010101","0000000101010101") when (brd_add(3 downto 0) = "0001") else
+                ("0000000010101010","0000000010101010","0000000010101010","0000000010101010") when (brd_add(3 downto 0) = "0010") else
+                ("0000000000000001","0000000000000001","0000000000000001","0000000000000001") when (brd_add(3 downto 0) = "0011") else
+                ("0000000000000011","0000000000000011","0000000000000011","0000000000000011") when (brd_add(3 downto 0) = "0100") else
+                ("0000000000001111","0000000000001111","0000000000001111","0000000000001111") when (brd_add(3 downto 0) = "0101") else
+                ("0000000000111111","0000000000111111","0000000000111111","0000000000111111") when (brd_add(3 downto 0) = "0110") else
+                ("0000000111111111","0000000111111111","0000000111111111","0000000111111111") when (brd_add(3 downto 0) = "0111") else
+                ("0000000111110000","0000000111110000","0000000111110000","0000000111110000") when (brd_add(3 downto 0) = "1000") else
+                ("0000000000011111","0000000000011111","0000000000011111","0000000000011111") when (brd_add(3 downto 0) = "1001") else
+                DEFAULT_ENABLE;
+
+  dac_array_sig <= (100,100,100,100,0,0,0,100) when (brd_add(5 downto 4) = "00") else
+                   (200,200,200,200,0,0,0,100) when (brd_add(5 downto 4) = "01") else
+                   (300,300,300,300,0,0,0,100) when (brd_add(5 downto 4) = "10") else
+                   DEFAULT_DAC;
+    
+  enables_A <= enable_sig(0)(8 downto 0);
+  enables_B <= enable_sig(1)(8 downto 0);
+  enables_C <= enable_sig(2)(8 downto 0);
+  enables_D <= enable_sig(3)(8 downto 0);
+  
+  --FTU main state machine (two-process implementation)
+
+  FTU_test5_Registers: process (ext_clk)
+  begin
+    if Rising_edge(ext_clk) then
+      FTU_test5_State <= FTU_test5_NextState;
+    end if;
+  end process FTU_test5_Registers;
+
+  FTU_test5_C_logic: process (FTU_test5_State)
+  begin
+    FTU_test5_NextState <= FTU_test5_State;
+    case FTU_test5_State is
+      when Running =>
+        reset_sig <= '0';
+    end case;
+  end process FTU_test5_C_logic;
+  
+end Behavioral;
Index: FPGA/FTU/test_firmware/FTU_test5/FTU_test5_dac_control.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test5/FTU_test5_dac_control.vhd	(revision 268)
+++ FPGA/FTU/test_firmware/FTU_test5/FTU_test5_dac_control.vhd	(revision 268)
@@ -0,0 +1,132 @@
+----------------------------------------------------------------------------------
+-- Company:        ETH Zurich, Institute for Particle Physics
+-- Engineer:       P. Vogler, Q. Weitzel
+-- 
+-- Create Date:    07/14/2010 
+-- Design Name: 
+-- Module Name:    FTU_test5_dac_control - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description:     
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library ftu_definitions_test5;
+USE ftu_definitions_test5.ftu_array_types.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity FTU_test5_dac_control is
+  port(
+    clk      : IN     STD_LOGIC;
+    reset    : IN     STD_LOGIC;
+    dacs     : IN     dac_array_type;
+    clr      : OUT    STD_LOGIC;
+    mosi     : OUT    STD_LOGIC;
+    sck      : OUT    STD_LOGIC;
+    cs_ld    : out    STD_LOGIC
+  );
+end FTU_test5_dac_control;
+
+architecture Behavioral of FTU_test5_dac_control is
+
+  component FTU_test5_spi_interface
+    port(
+      clk_50MHz      : IN     std_logic;
+      config_start   : IN     std_logic;
+      dac_array      : IN     dac_array_type;
+      config_ready   : OUT    std_logic;
+      config_started : OUT    std_logic;
+      dac_cs         : OUT    std_logic;
+      mosi           : OUT    std_logic;
+      sclk           : OUT    std_logic;
+      miso           : INOUT  std_logic
+   );
+  end component;
+
+  signal clk_sig            : std_logic;
+  signal reset_sig          : std_logic;
+
+  signal clr_sig            : std_logic;
+  signal mosi_sig           : std_logic := '0';
+  signal serial_clock_sig   : std_logic;
+  signal dac_cs_sig         : std_logic;
+  
+  signal config_start_sig   : std_logic := '0';  
+  signal config_ready_sig   : std_logic;
+  signal config_started_sig : std_logic := '0';
+  --signal dac_array_sig      : dac_array_type := DEFAULT_DAC;
+  signal dac_array_sig      : dac_array_type;
+  
+  -- Build an enumerated type for the state machine
+  type state_type is (START, WAITING, STOP);
+
+  -- Register to hold the current state
+  signal dac_ctrl_state, next_state : state_type;
+  
+begin
+
+  reset_sig <= reset;
+  clk_sig <= clk;
+  mosi <= mosi_sig;
+  sck <= serial_clock_sig;
+  cs_ld <= dac_cs_sig;
+  dac_array_sig <= dacs;
+  
+  -- FSM for dac control: first process
+  FSM_Registers: process(clk_sig, reset_sig)
+  begin
+    if reset_sig = '1' then
+      dac_ctrl_state <= START;
+    elsif Rising_edge(clk_sig) then
+      dac_ctrl_state <= next_state;
+    end if;
+  end process;
+
+  -- FSM for dac control: second process
+  FSM_logic: process(dac_ctrl_state, config_ready_sig)
+  begin
+    next_state <= dac_ctrl_state;
+    case dac_ctrl_state is
+      when START =>
+        config_start_sig <= '1';
+        next_state <= WAITING;        
+      when WAITING =>
+        config_start_sig <= '1';
+        if (config_ready_sig = '1') then          
+          next_state <= STOP;          
+        else
+          next_state <= WAITING;
+        end if;
+      when STOP =>
+        config_start_sig <= '0';
+    end case;
+  end process;
+    
+  Inst_FTU_test5_spi_interface : FTU_test5_spi_interface
+    port map(
+      clk_50MHz      => clk_sig,
+      config_start   => config_start_sig,
+      dac_array      => dac_array_sig,
+      config_ready   => config_ready_sig,
+      config_started => config_started_sig,
+      dac_cs         => dac_cs_sig,
+      mosi           => mosi_sig,
+      sclk           => serial_clock_sig,
+      miso           => open
+    );
+
+end Behavioral;
Index: FPGA/FTU/test_firmware/FTU_test5/FTU_test5_dac_dcm.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test5/FTU_test5_dac_dcm.vhd	(revision 268)
+++ FPGA/FTU/test_firmware/FTU_test5/FTU_test5_dac_dcm.vhd	(revision 268)
@@ -0,0 +1,90 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
+--------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 11.1
+--  \   \         Application : xaw2vhdl
+--  /   /         Filename : FTU_dac_dcm.vhd
+-- /___/   /\     Timestamp : 01/20/2010 16:36:17
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--Command: xaw2vhdl-st /home/qweitzel/FPGA/FACT/FTU/source/ip_cores/FTU_dac_dcm.xaw /home/qweitzel/FPGA/FACT/FTU/source/ip_cores/FTU_dac_dcm
+--Design Name: FTU_dac_dcm
+--Device: xc3s400an-4fgg400
+--
+-- Module FTU_dac_dcm
+-- Generated by Xilinx Architecture Wizard
+-- Written for synthesis tool: XST
+-- Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI
+-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 6.54 ns
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+
+entity FTU_test5_dac_dcm is
+   port ( CLKIN_IN        : in    std_logic; 
+          RST_IN          : in    std_logic; 
+          CLKFX_OUT       : out   std_logic; 
+          CLKIN_IBUFG_OUT : out   std_logic; 
+          LOCKED_OUT      : out   std_logic);
+end FTU_test5_dac_dcm;
+
+architecture BEHAVIORAL of FTU_test5_dac_dcm is
+   signal CLKFX_BUF       : std_logic;
+   signal CLKIN_IBUFG     : std_logic;
+   signal GND_BIT         : std_logic;
+begin
+   GND_BIT <= '0';
+   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
+   CLKFX_BUFG_INST : BUFG
+      port map (I=>CLKFX_BUF,
+                O=>CLKFX_OUT);
+   
+   CLKIN_IBUFG_INST : IBUFG
+      port map (I=>CLKIN_IN,
+                O=>CLKIN_IBUFG);
+   
+   DCM_SP_INST : DCM_SP
+   generic map( CLK_FEEDBACK => "NONE",
+            CLKDV_DIVIDE => 2.0,
+            CLKFX_DIVIDE => 2,
+            CLKFX_MULTIPLY => 2,
+            CLKIN_DIVIDE_BY_2 => FALSE,
+            CLKIN_PERIOD => 20.000,
+            CLKOUT_PHASE_SHIFT => "NONE",
+            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
+            DFS_FREQUENCY_MODE => "LOW",
+            DLL_FREQUENCY_MODE => "LOW",
+            DUTY_CYCLE_CORRECTION => TRUE,
+            FACTORY_JF => x"C080",
+            PHASE_SHIFT => 0,
+            STARTUP_WAIT => FALSE)
+      port map (CLKFB=>GND_BIT,
+                CLKIN=>CLKIN_IBUFG,
+                DSSEN=>GND_BIT,
+                PSCLK=>GND_BIT,
+                PSEN=>GND_BIT,
+                PSINCDEC=>GND_BIT,
+                RST=>RST_IN,
+                CLKDV=>open,
+                CLKFX=>CLKFX_BUF,
+                CLKFX180=>open,
+                CLK0=>open,
+                CLK2X=>open,
+                CLK2X180=>open,
+                CLK90=>open,
+                CLK180=>open,
+                CLK270=>open,
+                LOCKED=>LOCKED_OUT,
+                PSDONE=>open,
+                STATUS=>open);
+   
+end BEHAVIORAL;
+
+
Index: FPGA/FTU/test_firmware/FTU_test5/FTU_test5_spi_clock_gen.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test5/FTU_test5_spi_clock_gen.vhd	(revision 268)
+++ FPGA/FTU/test_firmware/FTU_test5/FTU_test5_spi_clock_gen.vhd	(revision 268)
@@ -0,0 +1,47 @@
+--
+-- VHDL Architecture FACT_FAD_lib.spi_clock_generator.beha
+--
+-- Created:
+--          by - Benjamin Krumm.UNKNOWN (EEPC8)
+--          at - 14:49:19 01.04.2010
+--
+-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY FTU_test5_spi_clock_generator IS
+   GENERIC( 
+      CLK_DIVIDER : integer := 25   --2 MHz @ 50 MHz
+   );
+   PORT( 
+      clk  : IN     std_logic;
+      sclk : OUT    std_logic  := '0'
+   );
+END FTU_test5_spi_clock_generator;
+
+ARCHITECTURE beha OF FTU_test5_spi_clock_generator IS
+  
+BEGIN
+  
+  spi_clk_proc: process (clk)
+    variable Z: integer range 0 to clk_divider - 1;
+  begin
+    if rising_edge(clk) then
+      if (Z < clk_divider - 1) then 
+        Z := Z + 1;
+      else 
+        Z := 0;
+      end if;
+      if (Z = 0) then 
+        sclk <= '1';
+      end if;
+      if (Z = clk_divider / 2) then 
+        sclk <= '0';
+      end if;
+    end if;
+  end process spi_clk_proc;
+
+END ARCHITECTURE beha;
Index: FPGA/FTU/test_firmware/FTU_test5/FTU_test5_spi_controller.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test5/FTU_test5_spi_controller.vhd	(revision 268)
+++ FPGA/FTU/test_firmware/FTU_test5/FTU_test5_spi_controller.vhd	(revision 268)
@@ -0,0 +1,81 @@
+--
+-- VHDL Architecture FACT_FAD_lib.spi_controller.beha
+--
+-- Created:
+--          by - Benjamin Krumm.UNKNOWN (EEPC8)
+--          at - 10:37:20 12.04.2010
+--
+-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
+--
+-- modified by Q. Weitzel
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY FTU_test5_spi_controller IS
+   PORT( 
+      clk          : IN     std_logic;
+      miso         : INOUT  std_logic := 'Z';
+      mosi         : OUT    std_logic := '0';
+      dac_id       : IN     std_logic_vector (2 DOWNTO 0);
+      --data         : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z');
+      data         : IN  std_logic_vector (15 DOWNTO 0) := (others => '0');
+      dac_cs       : OUT    std_logic := '1';
+      dac_start    : IN     std_logic;
+      dac_ready    : OUT    std_logic := '0'
+   );
+END FTU_test5_spi_controller ;
+
+ARCHITECTURE beha OF FTU_test5_spi_controller IS
+  
+  type TYPE_SPI_STATE is (SPI_IDLE, SPI_LOAD_DAC, SPI_LOAD_COMMAND);
+   
+  signal spi_state     : TYPE_SPI_STATE := SPI_IDLE;
+  signal spi_cycle_cnt : integer range 0 to 25 := 0;
+  signal shift_reg     : std_logic_vector (23 downto 0) := (others => '0');
+  signal data_reg      : std_logic_vector (15 downto 0) := (others => '0');
+  
+BEGIN
+  
+  spi_write_proc: process (clk)
+  begin
+    if falling_edge(clk) then
+      dac_cs <= '1';
+      miso <= 'Z';
+      mosi <= '0';
+      --data <= (others => 'Z');
+      case spi_state is
+        when SPI_IDLE =>
+          if (dac_start = '1') then
+            dac_ready <= '0';
+            spi_state <= SPI_LOAD_COMMAND; 
+          end if;
+          
+        when SPI_LOAD_COMMAND =>
+          spi_cycle_cnt <= 0;   
+            if (dac_start = '1') then
+              shift_reg <= "0011" & '0' & dac_id & data(11 downto 0) & "0000";
+              spi_state <= SPI_LOAD_DAC;
+            end if;
+        
+        -- start loading DACs 
+       when SPI_LOAD_DAC => 
+          dac_cs <= '0';
+          if (spi_cycle_cnt < 24) then
+            mosi <= shift_reg(23);
+            shift_reg <= shift_reg(22 downto 0) & shift_reg(23);
+            dac_ready <= '0';
+            spi_cycle_cnt <= spi_cycle_cnt + 1;
+            spi_state <= SPI_LOAD_DAC;
+          else
+            dac_cs <= '1';
+            dac_ready <= '1';
+            spi_state <= SPI_IDLE;
+          end if;
+      end case;
+    end if;
+  end process spi_write_proc;
+      
+END ARCHITECTURE beha;
Index: FPGA/FTU/test_firmware/FTU_test5/FTU_test5_spi_distributor.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test5/FTU_test5_spi_distributor.vhd	(revision 268)
+++ FPGA/FTU/test_firmware/FTU_test5/FTU_test5_spi_distributor.vhd	(revision 268)
@@ -0,0 +1,91 @@
+--
+-- VHDL Architecture FACT_FAD_lib.spi_distributor.beha
+--
+-- Created:
+--          by - Benjamin Krumm.UNKNOWN (EEPC8)
+--          at - 09:24:21 23.04.2010
+--
+-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
+--
+-- modified by Q. Weitzel
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+library ftu_definitions_test5;
+USE ftu_definitions_test5.ftu_array_types.all;
+
+ENTITY FTU_test5_spi_distributor IS
+  PORT(
+    clk               : IN    std_logic; -- 50MHz
+    config_start      : IN    std_logic;
+    config_ready      : OUT   std_logic := '0'; 
+    config_started    : OUT   std_logic := '0'; 
+    dac_array         : IN    dac_array_type;
+    dac_config_start  : OUT   std_logic := '0';
+    dac_config_ready  : IN    std_logic;
+    dac_id            : OUT   std_logic_vector(2 downto 0) := (others => '0');
+    --data              : INOUT std_logic_vector(15 downto 0) := (others => 'Z')
+    data              : OUT std_logic_vector(15 downto 0) := (others => '0')
+  );
+END ENTITY FTU_test5_spi_distributor;
+
+ARCHITECTURE beha OF FTU_test5_spi_distributor IS
+
+  type TYPE_SPI_DISTRIBUTION_STATE is (INIT, IDLE, CONFIG_DAC);
+    
+  signal spi_distr_state       : TYPE_SPI_DISTRIBUTION_STATE := INIT;
+  signal dac_id_cnt            : integer range 0 to 7 := 0;
+  
+BEGIN
+  
+  spi_distribute_proc: process (clk)
+  begin
+    
+    if rising_edge(clk) then
+      --data <= (others => 'Z');
+      data <= (others => '0');
+      case spi_distr_state is
+        when INIT =>
+          --data <= (others => 'Z');
+          data <= (others => '0');
+          spi_distr_state <= IDLE;
+        when IDLE =>
+          --data <= (others => 'Z');
+          data <= (others => '0');
+         -- start DAC configuration
+          if (config_start = '1') then
+            config_started <= '1';
+            config_ready <= '0';
+            dac_config_start <= '1';
+            dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length);
+            data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length);          
+            spi_distr_state <= CONFIG_DAC;
+          end if;
+                 
+        -- DAC configuration
+        when CONFIG_DAC =>
+          dac_config_start <= '1';
+          dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length);
+          data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length);
+          if (dac_config_ready = '1') then
+            dac_config_start <= '0';
+            if (dac_id_cnt < 7) then
+              dac_id_cnt <= dac_id_cnt + 1;
+              dac_config_start <= '1';
+              spi_distr_state <= CONFIG_DAC;
+            else
+              dac_id_cnt <= 0;
+              config_started <= '0';
+              config_ready <= '1';
+              spi_distr_state <= IDLE;
+            end if;
+          end if; 
+      end case;  
+    end if;
+    
+  end process spi_distribute_proc;
+  
+END ARCHITECTURE beha;
+
Index: FPGA/FTU/test_firmware/FTU_test5/FTU_test5_spi_interface.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test5/FTU_test5_spi_interface.vhd	(revision 268)
+++ FPGA/FTU/test_firmware/FTU_test5/FTU_test5_spi_interface.vhd	(revision 268)
@@ -0,0 +1,138 @@
+----------------------------------------------------------------------------------
+-- Company:        ETH Zurich, Institute for Particle Physics
+-- Engineer:       P. Vogler, Q. Weitzel
+--
+-- Create Date:    07/14/2010
+-- Design Name:
+-- Module Name:    FTU_test5_spi_interface - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:    Based on VHDL Entity FACT_FAD_lib.spi_interface.symbol
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library ftu_definitions_test5;
+USE ftu_definitions_test5.ftu_array_types.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+ENTITY FTU_test5_spi_interface IS
+   PORT(
+      clk_50MHz      : IN     std_logic;
+      config_start   : IN     std_logic;
+      dac_array      : IN     dac_array_type;
+      config_ready   : OUT    std_logic;
+      config_started : OUT    std_logic  := '0';
+      dac_cs         : OUT    std_logic;
+      mosi           : OUT    std_logic  := '0';
+      sclk           : OUT    std_logic;
+      miso           : INOUT  std_logic
+   );
+END FTU_test5_spi_interface;
+
+ARCHITECTURE struct OF FTU_test5_spi_interface IS
+
+   -- Internal signal declarations
+   SIGNAL dac_config_ready : std_logic;
+   SIGNAL dac_config_start : std_logic;
+   SIGNAL dac_id           : std_logic_vector(2 DOWNTO 0);
+   SIGNAL data             : std_logic_vector(15 DOWNTO 0);
+
+   -- Implicit buffer signal declarations
+   SIGNAL sclk_internal : std_logic;
+
+
+   -- Component Declarations
+   COMPONENT FTU_test5_spi_clock_generator
+   GENERIC (
+      CLK_DIVIDER : integer := 25      --2 MHz @ 50 MHz
+   );
+   PORT (
+      clk  : IN     std_logic;
+      sclk : OUT    std_logic  := '0'
+   );
+   END COMPONENT;
+   
+   COMPONENT FTU_test5_spi_controller
+   PORT (
+      clk          : IN     std_logic;
+      dac_id       : IN     std_logic_vector (2 DOWNTO 0);
+      dac_start    : IN     std_logic;
+      dac_cs       : OUT    std_logic                      := '1';
+      dac_ready    : OUT    std_logic                      := '0';
+      mosi         : OUT    std_logic                      := '0';
+      --data         : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z');
+      data         : IN  std_logic_vector (15 DOWNTO 0) := (others => '0');
+      miso         : INOUT  std_logic                      := 'Z'
+   );
+   END COMPONENT;
+   
+   COMPONENT FTU_test5_spi_distributor
+   PORT (
+      clk               : IN     std_logic;
+      config_start      : IN     std_logic;
+      dac_array         : IN     dac_array_type;
+      dac_config_ready  : IN     std_logic;
+      config_ready      : OUT    std_logic                      := '0';
+      config_started    : OUT    std_logic                      := '0';
+      dac_config_start  : OUT    std_logic                      := '0';
+      dac_id            : OUT    std_logic_vector (2 DOWNTO 0)  := (others => '0');
+      --data              : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z')
+      data              : OUT  std_logic_vector (15 DOWNTO 0) := (others => '0')
+   );
+   END COMPONENT;
+
+BEGIN
+
+   -- Instance port mappings.
+   Inst_FTU_test5_spi_clock_generator : FTU_test5_spi_clock_generator
+      GENERIC MAP (
+         CLK_DIVIDER => 25         --2 MHz @ 50 MHz
+      )
+      PORT MAP (
+         clk  => clk_50MHz,
+         sclk => sclk_internal
+      );
+   
+   Inst_FTU_test5_spi_controller : FTU_test5_spi_controller
+      PORT MAP (
+         clk          => sclk_internal,
+         miso         => miso,
+         mosi         => mosi,
+         dac_id       => dac_id,
+         data         => data,
+         dac_cs       => dac_cs,
+         dac_start    => dac_config_start,
+         dac_ready    => dac_config_ready
+      );
+   
+   Inst_FTU_test5_spi_distributor : FTU_test5_spi_distributor
+      PORT MAP (
+         clk               => sclk_internal,
+         config_start      => config_start,
+         config_ready      => config_ready,
+         config_started    => config_started,
+         dac_array         => dac_array,
+         dac_config_start  => dac_config_start,
+         dac_config_ready  => dac_config_ready,
+         dac_id            => dac_id,
+         data              => data
+      );
+
+   -- Implicit buffered output assignments
+   sclk <= sclk_internal;
+
+END struct;
Index: FPGA/FTU/test_firmware/FTU_test5/FTU_test5_tb.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test5/FTU_test5_tb.vhd	(revision 268)
+++ FPGA/FTU/test_firmware/FTU_test5/FTU_test5_tb.vhd	(revision 268)
@@ -0,0 +1,180 @@
+--------------------------------------------------------------------------------
+-- Company:       ETH Zurich, Institute for Particle Physics
+-- Engineer:      P. Vogler, Q. Weitzel
+--
+-- Create Date:   07/14/2010
+-- Design Name:   
+-- Module Name:   FTU_test5_tb.vhd
+-- Project Name:  
+-- Target Device:  
+-- Tool versions:  
+-- Description:   Testbench for test5 entity of FACT FTU board 
+-- 
+-- VHDL Test Bench Created by ISE for module: FTU_test5
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--
+-- based on testbench for FTU_test1
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.ALL;
+ 
+entity FTU_test5_tb is
+end FTU_test5_tb;
+
+architecture behavior of FTU_test5_tb is 
+
+  -- Component Declaration for the Unit Under Test (UUT)
+ 
+  component FTU_test5
+    port(
+      -- global control
+      ext_clk   : IN  STD_LOGIC;                      -- external clock from FTU board
+      --reset     : in  STD_LOGIC;                      -- reset
+      brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- geographic board/slot address
+      brd_id    : IN  STD_LOGIC_VECTOR(7 downto 0);   -- local solder-programmable address
+
+      -- rate counters LVDS inputs
+      -- use IBUFDS differential input buffer
+      patch_A_p     : IN  STD_LOGIC;                  -- logic signal from first trigger patch
+      patch_A_n     : IN  STD_LOGIC;
+      patch_B_p     : IN  STD_LOGIC;                  -- logic signal from second trigger patch
+      patch_B_n     : IN  STD_LOGIC;
+      patch_C_p     : IN  STD_LOGIC;                  -- logic signal from third trigger patch
+      patch_C_n     : IN  STD_LOGIC;
+      patch_D_p     : IN  STD_LOGIC;                  -- logic signal from fourth trigger patch
+      patch_D_n     : IN  STD_LOGIC;
+      trig_prim_p   : IN  STD_LOGIC;                  -- logic signal from n-out-of-4 circuit
+      trig_prim_n   : IN  STD_LOGIC;
+
+      -- DAC interface
+      -- miso          : IN  STD_LOGIC;                  -- master-in-slave-out
+      sck           : OUT STD_LOGIC;                  -- serial clock to DAC
+      mosi          : OUT STD_LOGIC;                  -- serial data to DAC, master-out-slave-in
+      clr           : OUT STD_LOGIC;                  -- clear signal to DAC
+      cs_ld         : OUT STD_LOGIC;                  -- chip select or load to DAC
+
+      -- RS-485 interface to FTM
+      rx            : IN  STD_LOGIC;                  -- serial data from FTM
+      tx            : OUT STD_LOGIC;                  -- serial data to FTM
+      rx_en         : OUT STD_LOGIC;                  -- enable RS-485 receiver
+      tx_en         : OUT STD_LOGIC;                  -- enable RS-485 transmitter
+
+      -- analog buffer enable
+      enables_A   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
+      enables_B   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
+      enables_C   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
+      enables_D   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
+
+      -- testpoints
+      TP_A       : out STD_LOGIC_VECTOR(11 downto 0)   -- testpoints
+    );
+  end component;
+    
+  --Inputs
+  signal ext_clk     : STD_LOGIC := '0';
+  --signal reset       : STD_LOGIC := '0';
+  signal brd_add     : STD_LOGIC_VECTOR(5 downto 0) := "000001";
+  signal brd_id      : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
+  signal patch_A_p   : STD_LOGIC := '0';
+  signal patch_A_n   : STD_LOGIC := '0';
+  signal patch_B_p   : STD_LOGIC := '0';
+  signal patch_B_n   : STD_LOGIC := '0';
+  signal patch_C_p   : STD_LOGIC := '0';
+  signal patch_C_n   : STD_LOGIC := '0';
+  signal patch_D_p   : STD_LOGIC := '0';
+  signal patch_D_n   : STD_LOGIC := '0';
+  signal trig_prim_p : STD_LOGIC := '0';
+  signal trig_prim_n : STD_LOGIC := '0';
+  -- signal miso        : STD_LOGIC := '0';
+  signal rx          : STD_LOGIC := '0';
+
+  --Outputs
+  signal enables_A : STD_LOGIC_VECTOR(8 downto 0);
+  signal enables_B : STD_LOGIC_VECTOR(8 downto 0);
+  signal enables_C : STD_LOGIC_VECTOR(8 downto 0);
+  signal enables_D : STD_LOGIC_VECTOR(8 downto 0);
+  signal clr       : STD_LOGIC;
+  signal cs_ld     : STD_LOGIC;
+  signal sck       : STD_LOGIC;
+  signal mosi      : STD_LOGIC;
+  signal tx        : STD_LOGIC;
+  signal rx_en     : STD_LOGIC;
+  signal tx_en     : STD_LOGIC;
+  signal TP_A      : STD_LOGIC_VECTOR(11 downto 0);
+  
+  -- Clock period definitions
+  constant ext_clk_period : TIME := 20 ns;
+ 
+begin
+ 
+  -- Instantiate the Unit Under Test (UUT)
+  uut: FTU_test5
+    port map(
+      ext_clk     => ext_clk,
+      --reset       => reset,
+      brd_add     => brd_add,
+      brd_id      => brd_id,
+      patch_A_p   => patch_A_p,
+      patch_A_n   => patch_A_n,
+      patch_B_p   => patch_B_p,
+      patch_B_n   => patch_B_n,
+      patch_C_p   => patch_C_p,
+      patch_C_n   => patch_C_n,
+      patch_D_p   => patch_D_p,
+      patch_D_n   => patch_D_n,
+      trig_prim_p => trig_prim_p,
+      trig_prim_n => trig_prim_n,
+      -- miso        => miso,
+      rx          => rx,
+      rx_en       => rx_en,
+      enables_A   => enables_A,
+      enables_B   => enables_B,
+      enables_C   => enables_C,
+      enables_D   => enables_D,
+      clr         => clr,
+      cs_ld       => cs_ld,
+      sck         => sck,
+      mosi        => mosi,
+      tx          => tx,
+      tx_en       => tx_en,
+      TP_A        => TP_A
+    );
+
+  -- Clock process definitions
+  ext_clk_proc: process
+  begin
+    ext_clk <= '0';
+    wait for ext_clk_period/2;
+    ext_clk <= '1';
+    wait for ext_clk_period/2;
+  end process ext_clk_proc;
+ 
+  -- Stimulus process
+  stim_proc: process
+  begin		
+    -- hold reset state for 100ms.
+    wait for 100ms;	
+    
+    wait for ext_clk_period*10;
+
+    -- insert stimulus here 
+
+    wait;
+  end process stim_proc;
+
+end;
Index: FPGA/FTU/test_firmware/FTU_test5/ftu_board_test5.ucf
===================================================================
--- FPGA/FTU/test_firmware/FTU_test5/ftu_board_test5.ucf	(revision 268)
+++ FPGA/FTU/test_firmware/FTU_test5/ftu_board_test5.ucf	(revision 268)
@@ -0,0 +1,145 @@
+########################################################
+# FTU Board 
+# FACT Trigger Unit
+#
+# Pin location constraints
+#
+# by Patrick Vogler, Quirin Weitzel
+# 14 July 2010
+########################################################
+
+
+#Clock
+#######################################################
+NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk	
+
+
+# RS-485 Interface
+#######################################################
+#NET rx_en LOC  = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver		
+#NET tx_en LOC  = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter		
+#NET tx    LOC  = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM		
+#NET rx    LOC  = R20 | IOSTANDARD=LVCMOS33;               # 485_DI: serial data from FTM
+
+
+# Board ID - inputs 
+# local board-ID "solder programmable"
+#######################################################
+#NET brd_id<0> LOC  = C4 | IOSTANDARD=LVCMOS33; # P0		
+#NET brd_id<1> LOC  = C5 | IOSTANDARD=LVCMOS33; # P1		
+#NET brd_id<2> LOC  = C6 | IOSTANDARD=LVCMOS33; # P2		
+#NET brd_id<3> LOC  = C7 | IOSTANDARD=LVCMOS33; # P3		
+#NET brd_id<4> LOC  = C8 | IOSTANDARD=LVCMOS33; # P4		
+#NET brd_id<5> LOC  = B8 | IOSTANDARD=LVCMOS33; # P5		
+#NET brd_id<6> LOC  = C9 | IOSTANDARD=LVCMOS33; # P6	
+#NET brd_id<7> LOC  = B9 | IOSTANDARD=LVCMOS33; # P7	
+
+
+# Board Addresses
+# geographical slot address
+#######################################################
+NET brd_add<0> LOC  = A15 | IOSTANDARD=LVCMOS33; # ADDR0
+NET brd_add<1> LOC  = B15 | IOSTANDARD=LVCMOS33; # ADDR1
+NET brd_add<2> LOC  = A16 | IOSTANDARD=LVCMOS33; # ADDR2
+NET brd_add<3> LOC  = A17 | IOSTANDARD=LVCMOS33; # ADDR3
+NET brd_add<4> LOC  = A18 | IOSTANDARD=LVCMOS33; # ADDR4
+NET brd_add<5> LOC  = B18 | IOSTANDARD=LVCMOS33; # ADDR5
+
+
+# DAC SPI Interface
+#######################################################
+NET mosi   LOC  = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in 		
+NET sck    LOC  = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC			
+NET cs_ld  LOC  = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC			
+NET clr    LOC  = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC	
+
+
+# Testpoints
+######################################################
+# on Connector J5
+#NET TP_A<0> LOC  = B3 | IOSTANDARD=LVCMOS33;  # TP0_0
+#NET TP_A<1> LOC  = A3 | IOSTANDARD=LVCMOS33;  # TP1_0
+#NET TP_A<2> LOC  = A4 | IOSTANDARD=LVCMOS33;  # TP2_0
+#NET TP_A<3> LOC  = B5 | IOSTANDARD=LVCMOS33;  # TP2_0
+
+# on Connector J6
+#NET TP_A<4> LOC  = A5 | IOSTANDARD=LVCMOS33;  # TP4_0
+#NET TP_A<5> LOC  = A6 | IOSTANDARD=LVCMOS33;  # TP5_0
+#NET TP_A<6> LOC  = B7 | IOSTANDARD=LVCMOS33;  # TP6_0
+#NET TP_A<7> LOC  = A7 | IOSTANDARD=LVCMOS33;  # TP7_0
+
+# on Connector J7
+#NET TP_A<8>  LOC  = B11  | IOSTANDARD=LVCMOS33;  # TP8_0
+#NET TP_A<9>  LOC  = A12  | IOSTANDARD=LVCMOS33;  # TP9_0
+#NET TP_A<10> LOC  = B12  | IOSTANDARD=LVCMOS33;  # TP10_0
+#NET TP_A<11> LOC  = A14  | IOSTANDARD=LVCMOS33;  # TP11_0
+
+
+# Rate counter LVDS Inputs
+######################################################
+# logic signal from first trigger patch
+#NET patch_A_p  LOC  = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P
+#NET patch_A_n  LOC  = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N
+
+# logic signal from second trigger patch
+#NET patch_B_p  LOC  = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P
+#NET patch_B_n  LOC  = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N
+
+# logic signal from third trigger patch
+#NET patch_C_p  LOC  = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P
+#NET patch_C_n  LOC  = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N
+
+# logic signal from fourth trigger patch
+#NET patch_D_p  LOC  = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P
+#NET patch_D_n  LOC  = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N
+
+#The Trigger Primitive: logic signal from n-out-of-4 circuit
+#NET trig_prim_p   LOC  = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+
+#NET trig_prim_n   LOC  = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P-
+
+
+# Enables 
+######################################################
+# Patch 0
+NET enables_A<0>  LOC  = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 
+NET enables_A<1>  LOC  = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1
+NET enables_A<2>  LOC  = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2
+NET enables_A<3>  LOC  = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3
+NET enables_A<4>  LOC  = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4
+NET enables_A<5>  LOC  = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5
+NET enables_A<6>  LOC  = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6
+NET enables_A<7>  LOC  = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7 
+NET enables_A<8>  LOC  = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8  
+
+## Patch 1
+NET enables_B<0>  LOC  = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0
+NET enables_B<1>  LOC  = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1
+NET enables_B<2>  LOC  = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2
+NET enables_B<3>  LOC  = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3
+NET enables_B<4>  LOC  = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4
+NET enables_B<5>  LOC  = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5
+NET enables_B<6>  LOC  = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6
+NET enables_B<7>  LOC  = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7
+NET enables_B<8>  LOC  = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8
+
+# Patch 2
+NET enables_C<0>   LOC  = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0
+NET enables_C<1>   LOC  = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1
+NET enables_C<2>   LOC  = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2
+NET enables_C<3>   LOC  = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3
+NET enables_C<4>   LOC  = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4
+NET enables_C<5>   LOC  = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5
+NET enables_C<6>   LOC  = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6
+NET enables_C<7>   LOC  = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7
+NET enables_C<8>   LOC  = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8
+
+# Patch 3
+NET enables_D<0>   LOC  = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<1>   LOC  = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<2>   LOC  = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<3>   LOC  = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<4>   LOC  = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<5>   LOC  = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<6>   LOC  = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<7>   LOC  = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
+NET enables_D<8>   LOC  = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 
Index: FPGA/FTU/test_firmware/FTU_test5/ftu_definitions_test5.vhd
===================================================================
--- FPGA/FTU/test_firmware/FTU_test5/ftu_definitions_test5.vhd	(revision 268)
+++ FPGA/FTU/test_firmware/FTU_test5/ftu_definitions_test5.vhd	(revision 268)
@@ -0,0 +1,18 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+-- use IEEE.NUMERIC_STD.ALL;
+
+package ftu_array_types is
+
+  type enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
+  constant DEFAULT_ENABLE : enable_array_type := ("0000000111111111", --patch A                                                                      
+                                                  "0000000111111111", --patch B
+                                                  "0000000111111111", --patch C
+                                                  "0000000111111111");--patch D
+  
+  type dac_array_type is array (0 to 7) of integer range 0 to 2**12 - 1;
+  constant DEFAULT_DAC : dac_array_type := (500, 500, 500, 500, 0, 0, 0, 100);
+   
+end ftu_array_types;
