Index: /FPGA/FTU/test_firmware/FTU_test6/FTU_test6.vhd =================================================================== --- /FPGA/FTU/test_firmware/FTU_test6/FTU_test6.vhd (revision 9621) +++ /FPGA/FTU/test_firmware/FTU_test6/FTU_test6.vhd (revision 9621) @@ -0,0 +1,256 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 07/30/2010 +-- Design Name: +-- Module Name: FTU_test6 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTU board, set enables via RS485 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ftu_definitions_test6; +USE ftu_definitions_test6.ftu_array_types.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +entity FTU_test6 is + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : in STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); +end FTU_test6; + + +architecture Behavioral of FTU_test6 is + + component FTU_test6_dcm + port( + CLKIN_IN : IN STD_LOGIC; + RST_IN : IN STD_LOGIC; + CLKFX_OUT : OUT STD_LOGIC; + CLKIN_IBUFG_OUT : OUT STD_LOGIC; + LOCKED_OUT : OUT STD_LOGIC + ); + end component; + + component FTU_test6_rs485_interface + GENERIC( + CLOCK_FREQUENCY : integer := 50000000; -- Hertz + BAUD_RATE : integer := 250000 -- bits / sec + ); + PORT( + clk : IN std_logic; + -- RS485 + rx_d : IN std_logic; + rx_en : OUT std_logic; + tx_d : OUT std_logic; + tx_en : OUT std_logic; + -- FPGA + rx_data : OUT std_logic_vector(7 DOWNTO 0); + rx_busy : OUT std_logic := '0'; + rx_valid : OUT std_logic := '0'; + tx_data : IN std_logic_vector(7 DOWNTO 0); + tx_busy : OUT std_logic := '0'; + tx_start : IN std_logic + ); + end component; + + signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up + signal clk_50M_sig : STD_LOGIC; + + signal enable_sig : enable_array_type := DEFAULT_ENABLE; + + signal rx_en_sig : STD_LOGIC := '0'; + signal tx_en_sig : STD_LOGIC := '0'; + signal rx_sig : STD_LOGIC; + signal tx_sig : STD_LOGIC := 'X'; + signal rx_data_sig : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); + signal rx_busy_sig : STD_LOGIC; + signal rx_valid_sig : STD_LOGIC; + + type FTU_test6_StateType is (INIT, RUN1, RUN2, RUN3, RUN4); + signal FTU_test6_State, FTU_test6_NextState: FTU_test6_StateType; + +begin + + Inst_FTU_test6_dcm : FTU_test6_dcm + port map( + CLKIN_IN => ext_clk, + RST_IN => reset_sig, + CLKFX_OUT => clk_50M_sig, + CLKIN_IBUFG_OUT => open, + LOCKED_OUT => open + ); + + Inst_FTU_test6_rs485_interface : FTU_test6_rs485_interface + generic map( + CLOCK_FREQUENCY => 50000000, + BAUD_RATE => 10000000 --simulation + --BAUD_RATE => 19600 --implement + ) + port map( + clk => clk_50M_sig, + -- RS485 + rx_d => rx_sig, + rx_en => rx_en_sig, + tx_d => tx_sig, + tx_en => tx_en_sig, + -- FPGA + rx_data => rx_data_sig, + rx_busy => rx_busy_sig, + rx_valid => rx_valid_sig, + tx_data => (others => '0'), + tx_busy => open, + tx_start => '0' + ); + + enables_A <= enable_sig(0)(8 downto 0); + enables_B <= enable_sig(1)(8 downto 0); + enables_C <= enable_sig(2)(8 downto 0); + enables_D <= enable_sig(3)(8 downto 0); + + rx_en <= rx_en_sig; + tx_en <= tx_en_sig; + tx <= tx_sig; + rx_sig <= rx; + + --FTU main state machine (two-process implementation) + + FTU_test6_Registers: process (clk_50M_sig) + begin + if Rising_edge(clk_50M_sig) then + FTU_test6_State <= FTU_test6_NextState; + end if; + end process FTU_test6_Registers; + + FTU_test6_C_logic: process (FTU_test6_State, rx_data_sig, rx_valid_sig) + begin + FTU_test6_NextState <= FTU_test6_State; + case FTU_test6_State is + when INIT => + reset_sig <= '0'; + enable_sig <= DEFAULT_ENABLE; + if (rx_data_sig = "00110001" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN1; + elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN2; + elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN3; + elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN4; + else + FTU_test6_NextState <= INIT; + end if; + when RUN1 => + reset_sig <= '0'; + enable_sig <= ("0000000000000000","0000000111111111","0000000111111111","0000000111111111"); + if (rx_data_sig = "00110000" and rx_valid_sig = '1') then + FTU_test6_NextState <= INIT; + elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN2; + elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN3; + elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN4; + else + FTU_test6_NextState <= RUN1; + end if; + when RUN2 => + reset_sig <= '0'; + enable_sig <= ("0000000111111111","0000000000000000","0000000111111111","0000000111111111"); + if (rx_data_sig = "00110000" and rx_valid_sig = '1') then + FTU_test6_NextState <= INIT; + elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN1; + elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN3; + elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN4; + else + FTU_test6_NextState <= RUN2; + end if; + when RUN3 => + reset_sig <= '0'; + enable_sig <= ("0000000111111111","0000000111111111","0000000000000000","0000000111111111"); + if (rx_data_sig = "00110000" and rx_valid_sig = '1') then + FTU_test6_NextState <= INIT; + elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN1; + elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN2; + elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN4; + else + FTU_test6_NextState <= RUN3; + end if; + when RUN4 => + reset_sig <= '0'; + enable_sig <= ("0000000111111111","0000000111111111","0000000111111111","0000000000000000"); + if (rx_data_sig = "00110000" and rx_valid_sig = '1') then + FTU_test6_NextState <= INIT; + elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN1; + elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN2; + elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN3; + else + FTU_test6_NextState <= RUN4; + end if; + end case; + end process FTU_test6_C_logic; + +end Behavioral; Index: /FPGA/FTU/test_firmware/FTU_test6/FTU_test6_dcm.vhd =================================================================== --- /FPGA/FTU/test_firmware/FTU_test6/FTU_test6_dcm.vhd (revision 9621) +++ /FPGA/FTU/test_firmware/FTU_test6/FTU_test6_dcm.vhd (revision 9621) @@ -0,0 +1,90 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.1 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTU_dac_dcm.vhd +-- /___/ /\ Timestamp : 01/20/2010 16:36:17 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /home/qweitzel/FPGA/FACT/FTU/source/ip_cores/FTU_dac_dcm.xaw /home/qweitzel/FPGA/FACT/FTU/source/ip_cores/FTU_dac_dcm +--Design Name: FTU_dac_dcm +--Device: xc3s400an-4fgg400 +-- +-- Module FTU_dac_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 6.54 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTU_test6_dcm is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end FTU_test6_dcm; + +architecture BEHAVIORAL of FTU_test6_dcm is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 2, + CLKFX_MULTIPLY => 2, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: /FPGA/FTU/test_firmware/FTU_test6/FTU_test6_rs485_interface.vhd =================================================================== --- /FPGA/FTU/test_firmware/FTU_test6/FTU_test6_rs485_interface.vhd (revision 9621) +++ /FPGA/FTU/test_firmware/FTU_test6/FTU_test6_rs485_interface.vhd (revision 9621) @@ -0,0 +1,124 @@ +-- +-- VHDL Architecture FACT_FAD_lib.rs485_interface.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 13:24:23 08.06.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- +-- modified by Q. Weitzel, 30 July 2010 +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +ENTITY FTU_test6_rs485_interface IS + GENERIC( + CLOCK_FREQUENCY : integer := 50000000; -- Hertz + BAUD_RATE : integer := 250000 -- bits / sec + ); + PORT( + clk : IN std_logic; + -- RS485 + rx_d : IN std_logic; + rx_en : OUT std_logic; + tx_d : OUT std_logic; + tx_en : OUT std_logic; + -- FPGA + rx_data : OUT std_logic_vector (7 DOWNTO 0); + rx_busy : OUT std_logic := '0'; + rx_valid : OUT std_logic := '0'; + tx_data : IN std_logic_vector (7 DOWNTO 0); + tx_busy : OUT std_logic := '0'; + tx_start : IN std_logic + ); + +-- Declarations + +END FTU_test6_rs485_interface; + +ARCHITECTURE beha OF FTU_test6_rs485_interface IS + + signal tx_start_f : std_logic := '0'; + signal tx_sr : std_logic_vector(10 downto 0) := (others => '1'); -- start bit, 8 data bits, 2 stop bit + signal tx_bitcnt : integer range 0 to 11 := 11; + signal tx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1); + + signal flow_ctrl : std_logic := '0'; -- '0' -> RX enable, '1' -> TX enable + + signal rx_dsr : std_logic_vector(3 downto 0) := (others => '1'); + signal rx_sr : std_logic_vector(7 downto 0) := (others => '0'); + signal rx_bitcnt : integer range 0 to 11 := 11; + signal rx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1); + +BEGIN + + + -- Senden + tx_data_proc: process(clk) + begin + if rising_edge(clk) then + tx_start_f <= tx_start; + if (tx_start = '1' or tx_bitcnt < 11) then + flow_ctrl <= '1'; + else + flow_ctrl <= '0'; + end if; + if (tx_start = '1' and tx_start_f = '0') then -- steigende Flanke, los gehts + tx_cnt <= 0; -- Zaehler initialisieren + tx_bitcnt <= 0; + tx_sr <= "11" & tx_data & '0'; -- 2 x Stopbit, 8 Datenbits, Startbit, rechts gehts los + else + if (tx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then + tx_cnt <= tx_cnt + 1; + else -- naechstes Bit ausgeben + if (tx_bitcnt < 11) then + tx_cnt <= 0; + tx_bitcnt <= tx_bitcnt + 1; + tx_sr <= '1' & tx_sr(tx_sr'left downto 1); + end if; + end if; + end if; + end if; + end process; + + tx_en <= flow_ctrl; + tx_d <= tx_sr(0); -- LSB first + tx_busy <= '1' when (tx_start = '1' or tx_bitcnt < 11) else '0'; + + -- Empfangen + rx_data_proc: process(clk) + begin + if rising_edge(clk) then + rx_dsr <= rx_dsr(rx_dsr'left - 1 downto 0) & rx_d; + if (rx_bitcnt < 11) then -- Empfang laeuft + if (rx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then + rx_cnt <= rx_cnt + 1; + else + rx_cnt <= 0; + rx_bitcnt <= rx_bitcnt + 1; + if (rx_bitcnt < 9) then + rx_sr <= rx_dsr(rx_dsr'left - 1) & rx_sr(rx_sr'left downto 1); -- rechts schieben, weil LSB first + else + rx_valid <= '1'; + end if; + end if; + else + if (rx_dsr(3 downto 2) = "10") then -- warten auf Start bit + rx_valid <= '0'; + rx_cnt <= ((CLOCK_FREQUENCY / BAUD_RATE) - 1) / 2; + rx_bitcnt <= 0; + end if; + end if; + end if; + end process; + + rx_en <= flow_ctrl; + rx_data <= rx_sr; + rx_busy <= '1' when (rx_bitcnt < 11) else '0'; + +END ARCHITECTURE beha; + Index: /FPGA/FTU/test_firmware/FTU_test6/FTU_test6_tb.vhd =================================================================== --- /FPGA/FTU/test_firmware/FTU_test6/FTU_test6_tb.vhd (revision 9621) +++ /FPGA/FTU/test_firmware/FTU_test6/FTU_test6_tb.vhd (revision 9621) @@ -0,0 +1,194 @@ +-------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 07/30/2010 +-- Design Name: +-- Module Name: FTU_test6_tb.vhd +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: Testbench for test6 entity of FACT FTU board +-- +-- VHDL Test Bench Created by ISE for module: FTU_test6 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-- +-- based on testbench for FTU_test1 +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity FTU_test6_tb is +end FTU_test6_tb; + +architecture behavior of FTU_test6_tb is + + -- Component Declaration for the Unit Under Test (UUT) + + component FTU_test6 + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable address + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); + end component; + + --Inputs + signal ext_clk : STD_LOGIC := '0'; + signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); + signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); + signal patch_A_p : STD_LOGIC := '0'; + signal patch_A_n : STD_LOGIC := '0'; + signal patch_B_p : STD_LOGIC := '0'; + signal patch_B_n : STD_LOGIC := '0'; + signal patch_C_p : STD_LOGIC := '0'; + signal patch_C_n : STD_LOGIC := '0'; + signal patch_D_p : STD_LOGIC := '0'; + signal patch_D_n : STD_LOGIC := '0'; + signal trig_prim_p : STD_LOGIC := '0'; + signal trig_prim_n : STD_LOGIC := '0'; + signal rx : STD_LOGIC := '0'; + + --Outputs + signal enables_A : STD_LOGIC_VECTOR(8 downto 0); + signal enables_B : STD_LOGIC_VECTOR(8 downto 0); + signal enables_C : STD_LOGIC_VECTOR(8 downto 0); + signal enables_D : STD_LOGIC_VECTOR(8 downto 0); + signal clr : STD_LOGIC; + signal cs_ld : STD_LOGIC; + signal sck : STD_LOGIC; + signal mosi : STD_LOGIC; + signal tx : STD_LOGIC; + signal rx_en : STD_LOGIC; + signal tx_en : STD_LOGIC; + signal TP_A : STD_LOGIC_VECTOR(11 downto 0); + + -- Clock period definitions + constant ext_clk_period : TIME := 20 ns; + +begin + + -- Instantiate the Unit Under Test (UUT) + uut: FTU_test6 + port map( + ext_clk => ext_clk, + brd_add => brd_add, + brd_id => brd_id, + patch_A_p => patch_A_p, + patch_A_n => patch_A_n, + patch_B_p => patch_B_p, + patch_B_n => patch_B_n, + patch_C_p => patch_C_p, + patch_C_n => patch_C_n, + patch_D_p => patch_D_p, + patch_D_n => patch_D_n, + trig_prim_p => trig_prim_p, + trig_prim_n => trig_prim_n, + rx => rx, + rx_en => rx_en, + enables_A => enables_A, + enables_B => enables_B, + enables_C => enables_C, + enables_D => enables_D, + clr => clr, + cs_ld => cs_ld, + sck => sck, + mosi => mosi, + tx => tx, + tx_en => tx_en, + TP_A => TP_A + ); + + -- Clock process definitions + ext_clk_proc: process + begin + ext_clk <= '0'; + wait for ext_clk_period/2; + ext_clk <= '1'; + wait for ext_clk_period/2; + end process ext_clk_proc; + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + --wait for 100ms; + + wait for ext_clk_period*10; + + rx <= '1'; --start bit + wait for ext_clk_period*5; + rx <= '1'; + wait for ext_clk_period*5; + rx <= '0'; + wait for ext_clk_period*5; + rx <= '0'; + wait for ext_clk_period*5; + rx <= '0'; + wait for ext_clk_period*5; + rx <= '1'; + wait for ext_clk_period*5; + rx <= '1'; + wait for ext_clk_period*5; + rx <= '0'; + wait for ext_clk_period*5; + rx <= '0'; + wait for ext_clk_period*5; + rx <= '0'; --parity bit + wait for ext_clk_period*5; + rx <= '1'; --stop bit + + wait; + end process stim_proc; + +end; Index: /FPGA/FTU/test_firmware/FTU_test6/ftu_board_test6.ucf =================================================================== --- /FPGA/FTU/test_firmware/FTU_test6/ftu_board_test6.ucf (revision 9621) +++ /FPGA/FTU/test_firmware/FTU_test6/ftu_board_test6.ucf (revision 9621) @@ -0,0 +1,145 @@ +######################################################## +# FTU Board +# FACT Trigger Unit +# +# Pin location constraints +# +# by Patrick Vogler, Quirin Weitzel +# 30 July 2010 (for FTU_test6) +######################################################## + + +#Clock +####################################################### +NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk + + +# RS-485 Interface +####################################################### +NET rx_en LOC = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver +NET tx_en LOC = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter +NET tx LOC = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM +NET rx LOC = R20 | IOSTANDARD=LVCMOS33; # 485_DI: serial data from FTM + + +# Board ID - inputs +# local board-ID "solder programmable" +####################################################### +#NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0 +#NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1 +#NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2 +#NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3 +#NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4 +#NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5 +#NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6 +#NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7 + + +# Board Addresses +# geographical slot address +####################################################### +#NET brd_add<0> LOC = A15 | IOSTANDARD=LVCMOS33; # ADDR0 +#NET brd_add<1> LOC = B15 | IOSTANDARD=LVCMOS33; # ADDR1 +#NET brd_add<2> LOC = A16 | IOSTANDARD=LVCMOS33; # ADDR2 +#NET brd_add<3> LOC = A17 | IOSTANDARD=LVCMOS33; # ADDR3 +#NET brd_add<4> LOC = A18 | IOSTANDARD=LVCMOS33; # ADDR4 +#NET brd_add<5> LOC = B18 | IOSTANDARD=LVCMOS33; # ADDR5 + + +# DAC SPI Interface +####################################################### +#NET mosi LOC = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in +#NET sck LOC = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC +#NET cs_ld LOC = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC +#NET clr LOC = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC + + +# Testpoints +###################################################### +# on Connector J5 +#NET TP_A<0> LOC = B3 | IOSTANDARD=LVCMOS33; # TP0_0 +#NET TP_A<1> LOC = A3 | IOSTANDARD=LVCMOS33; # TP1_0 +#NET TP_A<2> LOC = A4 | IOSTANDARD=LVCMOS33; # TP2_0 +#NET TP_A<3> LOC = B5 | IOSTANDARD=LVCMOS33; # TP2_0 + +# on Connector J6 +#NET TP_A<4> LOC = A5 | IOSTANDARD=LVCMOS33; # TP4_0 +#NET TP_A<5> LOC = A6 | IOSTANDARD=LVCMOS33; # TP5_0 +#NET TP_A<6> LOC = B7 | IOSTANDARD=LVCMOS33; # TP6_0 +#NET TP_A<7> LOC = A7 | IOSTANDARD=LVCMOS33; # TP7_0 + +# on Connector J7 +#NET TP_A<8> LOC = B11 | IOSTANDARD=LVCMOS33; # TP8_0 +#NET TP_A<9> LOC = A12 | IOSTANDARD=LVCMOS33; # TP9_0 +#NET TP_A<10> LOC = B12 | IOSTANDARD=LVCMOS33; # TP10_0 +#NET TP_A<11> LOC = A14 | IOSTANDARD=LVCMOS33; # TP11_0 + + +# Rate counter LVDS Inputs +###################################################### +# logic signal from first trigger patch +#NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P +#NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N + +# logic signal from second trigger patch +#NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P +#NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N + +# logic signal from third trigger patch +#NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P +#NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N + +# logic signal from fourth trigger patch +#NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P +#NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N + +#The Trigger Primitive: logic signal from n-out-of-4 circuit +#NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+ +#NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P- + + +# Enables +###################################################### +# Patch 0 +NET enables_A<0> LOC = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 +NET enables_A<1> LOC = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1 +NET enables_A<2> LOC = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2 +NET enables_A<3> LOC = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3 +NET enables_A<4> LOC = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4 +NET enables_A<5> LOC = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5 +NET enables_A<6> LOC = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6 +NET enables_A<7> LOC = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7 +NET enables_A<8> LOC = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8 + +## Patch 1 +NET enables_B<0> LOC = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0 +NET enables_B<1> LOC = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1 +NET enables_B<2> LOC = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2 +NET enables_B<3> LOC = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3 +NET enables_B<4> LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4 +NET enables_B<5> LOC = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5 +NET enables_B<6> LOC = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6 +NET enables_B<7> LOC = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7 +NET enables_B<8> LOC = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8 + +# Patch 2 +NET enables_C<0> LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0 +NET enables_C<1> LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1 +NET enables_C<2> LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2 +NET enables_C<3> LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3 +NET enables_C<4> LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4 +NET enables_C<5> LOC = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5 +NET enables_C<6> LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6 +NET enables_C<7> LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7 +NET enables_C<8> LOC = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8 + +# Patch 3 +NET enables_D<0> LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<1> LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<2> LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<3> LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<4> LOC = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<5> LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<6> LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<7> LOC = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<8> LOC = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 Index: /FPGA/FTU/test_firmware/FTU_test6/ftu_definitions_test6.vhd =================================================================== --- /FPGA/FTU/test_firmware/FTU_test6/ftu_definitions_test6.vhd (revision 9621) +++ /FPGA/FTU/test_firmware/FTU_test6/ftu_definitions_test6.vhd (revision 9621) @@ -0,0 +1,18 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- use IEEE.NUMERIC_STD.ALL; + +package ftu_array_types is + + type enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0); + constant DEFAULT_ENABLE : enable_array_type := ("0000000111111111", --patch A + "0000000111111111", --patch B + "0000000111111111", --patch C + "0000000111111111");--patch D + + type dac_array_type is array (0 to 7) of integer range 0 to 2**12 - 1; + constant DEFAULT_DAC : dac_array_type := (500, 500, 500, 500, 0, 0, 0, 100); + +end ftu_array_types;