Index: /FPGA/FTU/FTU_top.vhd
===================================================================
--- /FPGA/FTU/FTU_top.vhd	(revision 9826)
+++ /FPGA/FTU/FTU_top.vhd	(revision 9827)
@@ -19,8 +19,10 @@
 --
 ----------------------------------------------------------------------------------
+
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
 library ftu_definitions;
 USE ftu_definitions.ftu_array_types.all;
@@ -83,22 +85,19 @@
   
   signal clk_50M_sig   : STD_LOGIC;         -- generated by internal DCM
-  signal clk_ready_sig : STD_LOGIC := '0';  -- set high by FTU_clk_gen when DCMs have locked 
-
-  signal ram_wea_sig  : STD_LOGIC_VECTOR(0 downto 0) := "0";  -- RAM write enable for port A
-  signal ram_web_sig  : STD_LOGIC_VECTOR(0 downto 0) := "0";  -- RAM write enable for port B
-  signal ram_ada_cntr : INTEGER range 0 to 2**5 - 1 := 0;
-  signal ram_adb_cntr : INTEGER range 0 to 2**4 - 1 := 0;
-  signal ram_ada_sig  : STD_LOGIC_VECTOR(4 downto 0);
-  signal ram_adb_sig  : STD_LOGIC_VECTOR(3 downto 0);
-  signal ram_dia_sig  : STD_LOGIC_VECTOR(7 downto 0);
-  signal ram_dib_sig  : STD_LOGIC_VECTOR(15 downto 0);
-  signal ram_doa_sig  : STD_LOGIC_VECTOR(7 downto 0);
-  signal ram_dob_sig  : STD_LOGIC_VECTOR(15 downto 0);
-    
-  type FTU_top_StateType is (IDLE, INIT, RUNNING, RESET);
-  signal FTU_top_State, FTU_top_NextState: FTU_top_StateType;
-
+  signal clk_ready_sig : STD_LOGIC := '0';  -- set high by FTU_clk_gen when DCMs have locked
+
+  --signal ram_wea_sig  : STD_LOGIC_VECTOR(0 downto 0) := "0";  -- RAM write enable for port A
+  --signal ram_web_sig  : STD_LOGIC_VECTOR(0 downto 0) := "0";  -- RAM write enable for port B
+  --signal ram_ada_cntr : INTEGER range 0 to 2**5 - 1 := 0;
+  --signal ram_adb_cntr : INTEGER range 0 to 2**4 - 1 := 0;
+  --signal ram_ada_sig  : STD_LOGIC_VECTOR(4 downto 0);
+  --signal ram_adb_sig  : STD_LOGIC_VECTOR(3 downto 0);
+  --signal ram_dia_sig  : STD_LOGIC_VECTOR(7 downto 0);
+  --signal ram_dib_sig  : STD_LOGIC_VECTOR(15 downto 0);
+  --signal ram_doa_sig  : STD_LOGIC_VECTOR(7 downto 0);
+  --signal ram_dob_sig  : STD_LOGIC_VECTOR(15 downto 0);
+    
   component FTU_clk_gen
-    port (
+    port(
       clk    : IN  STD_LOGIC;
       rst    : IN  STD_LOGIC;
@@ -108,4 +107,14 @@
   end component;
 
+  component FTU_control
+    port(
+      clk_50MHz    : IN std_logic;
+      clk_ready    : IN std_logic;
+      config_ready : IN std_logic;
+      reset        : OUT std_logic;
+      config_start : OUT std_logic
+    );
+  end component;
+    
   component FTU_spi_interface
     port(
@@ -121,24 +130,24 @@
   end component;
 
-  component FTU_dual_port_ram
-    port(
-      clka  : IN  std_logic;
-      ena   : IN  std_logic;
-      wea   : IN  std_logic_VECTOR(0 downto 0);
-      addra : IN  std_logic_VECTOR(4 downto 0);
-      dina  : IN  std_logic_VECTOR(7 downto 0);
-      douta : OUT std_logic_VECTOR(7 downto 0);
-      clkb  : IN  std_logic;
-      enb   : IN  std_logic;
-      web   : IN  std_logic_VECTOR(0 downto 0);
-      addrb : IN  std_logic_VECTOR(3 downto 0);
-      dinb  : IN  std_logic_VECTOR(15 downto 0);
-      doutb : OUT std_logic_VECTOR(15 downto 0)
-    );
-  end component;
+  --component FTU_dual_port_ram
+  --  port(
+  --    clka  : IN  std_logic;
+  --    ena   : IN  std_logic;
+  --    wea   : IN  std_logic_VECTOR(0 downto 0);
+  --    addra : IN  std_logic_VECTOR(4 downto 0);
+  --    dina  : IN  std_logic_VECTOR(7 downto 0);
+  --    douta : OUT std_logic_VECTOR(7 downto 0);
+  --    clkb  : IN  std_logic;
+  --    enb   : IN  std_logic;
+  --    web   : IN  std_logic_VECTOR(0 downto 0);
+  --    addrb : IN  std_logic_VECTOR(3 downto 0);
+  --    dinb  : IN  std_logic_VECTOR(15 downto 0);
+  --    doutb : OUT std_logic_VECTOR(15 downto 0)
+  --  );
+  --end component;
 
   -- Synplicity black box declaration
-  attribute syn_black_box : boolean;
-  attribute syn_black_box of FTU_dual_port_ram: component is true;
+  --attribute syn_black_box : boolean;
+  --attribute syn_black_box of FTU_dual_port_ram: component is true;
   
 begin
@@ -147,5 +156,5 @@
   
   Inst_FTU_clk_gen : FTU_clk_gen
-    port map (
+    port map(
       clk    => ext_clk,
       rst    => reset_sig,
@@ -154,4 +163,13 @@
     );
 
+  Inst_FTU_control : FTU_control
+    port map(
+      clk_50MHz    => clk_50M_sig,
+      clk_ready    => clk_ready_sig,
+      config_ready => config_ready_sig,
+      reset        => reset_sig,
+      config_start => config_start_sig
+    );
+  
   Inst_FTU_spi_interface : FTU_spi_interface
     port map(
@@ -166,76 +184,19 @@
     );
 
-  Inst_FTU_dual_port_ram : FTU_dual_port_ram
-    port map(
-      clka  => clk_50M_sig,
-      ena   => '1',
-      wea   => ram_wea_sig,
-      addra => ram_ada_sig,
-      dina  => ram_dia_sig,
-      douta => ram_doa_sig,
-      clkb  => clk_50M_sig,
-      enb   => '1',
-      web   => ram_web_sig,
-      addrb => ram_adb_sig,
-      dinb  => ram_dib_sig,
-      doutb => ram_dob_sig
-    );
-  
-  --FTU main state machine (two-process implementation)
-  --sensitive to external clock
-
-  FTU_top_Registers: process (ext_clk)
-  begin
-    if Rising_edge(ext_clk) then
-      FTU_top_State <= FTU_top_NextState;
-    end if;
-  end process FTU_top_Registers;
-
-  FTU_top_C_logic: process (FTU_top_State, clk_ready_sig, config_ready_sig, ram_adb_cntr)
-  begin
-    FTU_top_NextState <= FTU_top_State;
-    case FTU_top_State is
-      when IDLE =>                      -- wait for DMCs to lock
-        reset_sig <= '0';
-        dac_clr_sig <= '1';
-        config_start_sig <= '0';
-        ram_web_sig <= "0";
-        if (clk_ready_sig = '1') then
-          FTU_top_NextState <= RUNNING;
-        end if;          
-      when INIT =>                      -- load default config data to RAM 
-        reset_sig <= '0';
-        dac_clr_sig <= '1';
-        config_start_sig <= '0';
-        ram_web_sig <= "1";
-        ram_adb_cntr <= ram_adb_cntr + 1;
-        ram_adb_sig <= conv_std_logic_vector(ram_adb_cntr, 4);        
-        if (ram_adb_cntr < 4) then
-          ram_dib_sig <= DEFAULT_ENABLE(ram_adb_cntr);
-          FTU_top_NextState <= INIT;
-        elsif (ram_adb_cntr < 4 + 5) then
-          ram_dib_sig <= conv_std_logic_vector(DEFAULT_DAC(ram_adb_cntr - 4), 16);
-          FTU_top_NextState <= INIT;
-        elsif (ram_adb_cntr < 32) then
-          ram_dib_sig <= (others => '0');
-          FTU_top_NextState <= INIT;
-        else
-          ram_adb_cntr <= 0;
-          ram_web_sig <= "0";
-          FTU_top_NextState <= RUNNING;
-        end if;
-      when RUNNING =>                   -- count triggers and react to commands
-        reset_sig <= '0';
-        dac_clr_sig <= '1';
-        config_start_sig <= '0';
-        ram_web_sig <= "0";
-      when RESET =>                     -- reset/clear and start from scratch
-        reset_sig <= '1';
-        dac_clr_sig <= '0';
-        config_start_sig <= '0';
-        ram_web_sig <= "0";
-        FTU_top_NextState <= IDLE;
-    end case;
-  end process FTU_top_C_logic;
+  --Inst_FTU_dual_port_ram : FTU_dual_port_ram
+  --  port map(
+  --    clka  => clk_50M_sig,
+  --    ena   => '1',
+  --    wea   => ram_wea_sig,
+  --    addra => ram_ada_sig,
+  --    dina  => ram_dia_sig,
+  --    douta => ram_doa_sig,
+  --    clkb  => clk_50M_sig,
+  --    enb   => '1',
+  --    web   => ram_web_sig,
+  --    addrb => ram_adb_sig,
+  --    dinb  => ram_dib_sig,
+  --    doutb => ram_dob_sig
+  --  );
   
 end Behavioral;