Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD.hdp =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD.hdp (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD.hdp (revision 9841) @@ -0,0 +1,50 @@ +[DesignChecker] +FACT_FAD_lib = $HDS_PROJECT_DIR\FACT_FAD_lib\designcheck +[ModelSim] +FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/work +FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/work +secureip = C:/FPGAdv82PS/Xilinx_Lib/secureip +simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim +unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro +unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim +XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib +[QuestaSim] +secureip = C:/FPGAdv82PS/Xilinx_Lib/secureip +simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim +unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro +unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim +XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib +[XilinxISE] +FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/ise +[hdl] +FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hdl +FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/hdl +unisim = $HDS_PROJECT_DIR/unisim/hdl +[hdl_vm] +FACT_FAD_TB_lib = $HDS_HOME/examples/hds_scratch/hds_repository/FACT_FAD_TB_lib/hdl_vm +[hds] +FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hds +FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/hds +unisim = $HDS_PROJECT_DIR/unisim/hds +[hds_settings] +default_library = FACT_FAD_lib +design_root = FACT_FAD_lib.FAD_Board(struct)@f@a@d_@board/struct.bd +project_description = FPGA design for data acquisition from FACT +version = 1 +[hds_vm] +FACT_FAD_TB_lib = $HDS_HOME/examples/hds_scratch/hds_repository/FACT_FAD_TB_lib/hds_vm +[library_files_inclusion] +FACT_FAD_lib = specify +FACT_FAD_TB_lib = all +[library_type] +FACT_FAD_lib = regular +FACT_FAD_TB_lib = regular +secureip = downstream_only +simprim = downstream_only +unimacro = downstream_only +unisim = standard +XilinxCoreLib = downstream_only +[protected_library_traversal] +unisim = no +[shared] +others = $HDS_TEAM_HOME/shared.hdp Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD.info/xilinxcorelib.lpf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD.info/xilinxcorelib.lpf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD.info/xilinxcorelib.lpf (revision 9841) @@ -0,0 +1,3 @@ +version "1.0" +pathExcludes [ +] Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_beha.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_beha.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_beha.vhd (revision 9841) @@ -0,0 +1,106 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:44:52 01/07/2010 +-- Design Name: +-- Module Name: adc_emulator - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +-- hds interface_start +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_unsigned.all; +USE ieee.std_logic_textio.all; +LIBRARY std; +USE std.textio.all; + +ENTITY adc_emulator IS + GENERIC( + INPUT_FILE : string := "filename" + ); + PORT( + clk : IN std_logic; + data : OUT std_logic_vector (11 downto 0); + otr : OUT std_logic; + oeb : IN std_logic + ); + +-- Declarations + +END adc_emulator ; + +architecture Behavioral of adc_emulator is + + -- type_rom_type has to be a multiple of 4 bit because HREAD is used + type type_shift_reg is array (0 to 7) of std_logic_vector(12 downto 0); + type type_rom_array is array (0 to 1024) of std_logic_vector(15 downto 0); + + -- 'InitRomFromFile' reads one column of 'rom_filename' and puts the returned value to 'rom(i)' + impure function InitRomFromFile (rom_filename : in string) return type_rom_array is + file rom_file : text open read_mode is rom_filename; + variable rom_file_line: line; + variable rom : type_rom_array; + begin + for i in 0 to 1023 loop + readline(rom_file, rom_file_line); + hread(rom_file_line, rom(i)); + end loop; + return rom; + end function InitRomFromFile; + + signal rom : type_rom_array := InitRomFromFile(INPUT_FILE); + signal rom_reg : type_shift_reg; + signal rom_addr : std_logic_vector(9 downto 0) := (others => '0'); + signal rom_data : std_logic_vector(12 downto 0); + +begin + + rom_data <= rom(conv_integer(rom_addr))(12 downto 0); + data <= rom_reg(7)(11 downto 0) when oeb = '0' else (others => 'Z'); + otr <= rom_reg(7)(12); + + fetch_data_proc: process(clk) + begin + if rising_edge(clk) then + if (oeb = '0') then + rom_addr <= rom_addr + 1; + else + rom_addr <= (others => '0'); + end if; + end if; + end process fetch_data_proc; + + + ad_conv_proc: process(clk) + begin + if rising_edge(clk) then + if (oeb = '0') then + if (conv_integer(rom_data) > 2**12-1) then + rom_reg(0) <= '1' & X"FFF"; -- set OTR flag when rom_data is too high and set adc value to max + else + rom_reg(0) <= rom_data; -- shifting input cause output is shifted 7 cycles + end if; + rom_reg(1) <= rom_reg(0); + rom_reg(2) <= rom_reg(1); + rom_reg(3) <= rom_reg(2); + rom_reg(4) <= rom_reg(3); + rom_reg(5) <= rom_reg(4); + rom_reg(6) <= rom_reg(5); + rom_reg(7) <= rom_reg(6); + end if; + end if; + end process ad_conv_proc; + +end Behavioral; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_beha.vhd.bak =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_beha.vhd.bak (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_beha.vhd.bak (revision 9841) @@ -0,0 +1,106 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:44:52 01/07/2010 +-- Design Name: +-- Module Name: adc_emulator - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +-- hds interface_start +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_unsigned.all; +USE ieee.std_logic_textio.all; +LIBRARY std; +USE std.textio.all; + +ENTITY adc_emulator IS + GENERIC( + INPUT_FILE : string := "filename" + ); + PORT( + clk : IN STD_LOGIC; + data : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); + otr : OUT STD_LOGIC; + oeb : IN STD_LOGIC + ); + +-- Declarations + +END adc_emulator ; + +architecture Behavioral of adc_emulator is + + -- type_rom_type has to be a multiple of 4 bit because HREAD is used + type type_shift_reg is array (0 to 7) of std_logic_vector(12 downto 0); + type type_rom_array is array (0 to 1024) of std_logic_vector(15 downto 0); + + -- 'InitRomFromFile' reads one column of 'rom_filename' and puts the returned value to 'rom(i)' + impure function InitRomFromFile (rom_filename : in string) return type_rom_array is + file rom_file : text open read_mode is rom_filename; + variable rom_file_line: line; + variable rom : type_rom_array; + begin + for i in 0 to 1023 loop + readline(rom_file, rom_file_line); + hread(rom_file_line, rom(i)); + end loop; + return rom; + end function InitRomFromFile; + + signal rom : type_rom_array := InitRomFromFile(INPUT_FILE); + signal rom_reg : type_shift_reg; + signal rom_addr : std_logic_vector(9 downto 0) := (others => '0'); + signal rom_data : std_logic_vector(12 downto 0); + +begin + + rom_data <= rom(conv_integer(rom_addr))(12 downto 0); + data <= rom_reg(7)(11 downto 0) when oeb = '0' else (others => 'Z'); + otr <= rom_reg(7)(12); + + fetch_data_proc: process(clk) + begin + if rising_edge(clk) then + if (oeb = '0') then + rom_addr <= rom_addr + 1; + else + rom_addr <= (others => '0'); + end if; + end if; + end process fetch_data_proc; + + + ad_conv_proc: process(clk) + begin + if rising_edge(clk) then + if (oeb = '0') then + if (conv_integer(rom_data) > 2**12-1) then + rom_reg(0) <= '1' & X"FFF"; -- set OTR flag when rom_data is too high and set adc value to max + else + rom_reg(0) <= rom_data; -- shifting input cause output is shifted 7 cycles + end if; + rom_reg(1) <= rom_reg(0); + rom_reg(2) <= rom_reg(1); + rom_reg(3) <= rom_reg(2); + rom_reg(4) <= rom_reg(3); + rom_reg(5) <= rom_reg(4); + rom_reg(6) <= rom_reg(5); + rom_reg(7) <= rom_reg(6); + end if; + end if; + end process ad_conv_proc; + +end Behavioral; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_tb_struct.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_tb_struct.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_tb_struct.vhd (revision 9841) @@ -0,0 +1,112 @@ +-- VHDL Entity FACT_FAD_TB_lib.adc_emulator_tb.symbol +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 14:21:48 24.06.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +ENTITY adc_emulator_tb IS +-- Declarations + +END adc_emulator_tb ; + +-- +-- VHDL Architecture FACT_FAD_TB_lib.adc_emulator_tb.struct +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 14:21:48 24.06.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +USE ieee.std_logic_textio.all; +LIBRARY std; +USE std.textio.all; + +LIBRARY FACT_FAD_TB_lib; + +ARCHITECTURE struct OF adc_emulator_tb IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL clk : std_logic := '0'; + SIGNAL data : std_logic_vector(11 DOWNTO 0); + SIGNAL oeb : std_logic; + SIGNAL otr : std_logic; + + + -- Component Declarations + COMPONENT adc_emulator + GENERIC ( + INPUT_FILE : string := "filename" + ); + PORT ( + clk : IN STD_LOGIC ; + data : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); + otr : OUT STD_LOGIC ; + oeb : IN STD_LOGIC + ); + END COMPONENT; + COMPONENT clock_generator + GENERIC ( + clock_period : time := 20 ns; + reset_time : time := 50 ns + ); + PORT ( + clk : OUT std_logic := '0'; + rst : OUT std_logic := '0' + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : adc_emulator USE ENTITY FACT_FAD_TB_lib.adc_emulator; + FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb_adcTB_oeb + -- eb_adcTB_oeb 1: enable ADC + enable_proc: process + begin + oeb <= '1'; + wait for 1 us; + oeb <= '0'; + wait; + end process enable_proc; + + + -- Instance port mappings. + I_adcTB_adc : adc_emulator + GENERIC MAP ( + INPUT_FILE => "../memory_files/analog_input_ch0.txt" + ) + PORT MAP ( + clk => clk, + data => data, + otr => otr, + oeb => oeb + ); + I_adcTB_clock : clock_generator + GENERIC MAP ( + clock_period => 20 ns, + reset_time => 50 ns + ) + PORT MAP ( + clk => clk, + rst => OPEN + ); + +END struct; Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd (revision 9841) @@ -0,0 +1,60 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:40:20 01/07/2010 +-- Design Name: +-- Module Name: clock_generator - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +-- hds interface_start +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_unsigned.all; + +-- synthesis translate_off +ENTITY clock_generator IS + GENERIC( + clock_period : time := 20 ns; + reset_time : time := 50 ns + ); + PORT( + clk : out std_logic := '0'; + rst : out std_logic := '0' + ); +END clock_generator ; +-- hds interface_end + +architecture Behavioral of clock_generator is + +begin + + clock_gen_proc: process + begin + clk <= '0'; + wait for clock_period / 2; + clk <= '1'; + wait for clock_period / 2; + end process clock_gen_proc; + + reset_gen_proc: process + begin + rst <= '1'; + wait for reset_time; + rst <= '0'; + wait; + end process reset_gen_proc; + + +end Behavioral; +--synthesis translate_on Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd.bak =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd.bak (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd.bak (revision 9841) @@ -0,0 +1,64 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:40:20 01/07/2010 +-- Design Name: +-- Module Name: clock_generator - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +-- hds interface_start +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- synthesis translate_off +-- +ENTITY clock_generator IS + GENERIC( + clock_period : time := 20 ns; + reset_time : time := 50 ns + ); + PORT( + clk : OUT STD_LOGIC := '0'; + rst : OUT STD_LOGIC := '0' + ); + +-- Declarations + +END clock_generator ; +-- hds interface_end + +architecture Behavioral of clock_generator is + +begin + + clock_gen_proc: process + begin + clk <= '0'; + wait for clock_period / 2; + clk <= '1'; + wait for clock_period / 2; + end process clock_gen_proc; + + reset_gen_proc: process + begin + rst <= '1'; + wait for reset_time; + rst <= '0'; + wait; + end process reset_gen_proc; + + +end Behavioral; +--synthesis translate_on Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd (revision 9841) @@ -0,0 +1,281 @@ +-- VHDL Entity FACT_FAD_TB_lib.fad_main_tb.symbol +-- +-- Created: +-- by - dneise.UNKNOWN (TU-CC4900F8C7D2) +-- at - 15:53:42 30.06.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +ENTITY fad_main_tb IS +-- Declarations + +END fad_main_tb ; + +-- +-- VHDL Architecture FACT_FAD_TB_lib.fad_main_tb.struct +-- +-- Created: +-- by - dneise.UNKNOWN (TU-CC4900F8C7D2) +-- at - 15:53:42 30.06.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; +USE ieee.std_logic_textio.all; +LIBRARY std; +USE std.textio.all; + +LIBRARY FACT_FAD_lib; +LIBRARY FACT_FAD_TB_lib; + +ARCHITECTURE struct OF fad_main_tb IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL CLK_25_PS : std_logic; + SIGNAL CLK_50 : std_logic; + SIGNAL RSRLOAD : std_logic := '0'; + SIGNAL SRCLK : std_logic := '0'; + SIGNAL SROUT_in_0 : std_logic; + SIGNAL SROUT_in_1 : std_logic; + SIGNAL SROUT_in_2 : std_logic; + SIGNAL SROUT_in_3 : std_logic; + SIGNAL adc_data : std_logic_vector(11 DOWNTO 0); + SIGNAL adc_data_array : adc_data_array_type; + SIGNAL adc_oeb : std_logic; + SIGNAL adc_otr : STD_LOGIC; + SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0); + SIGNAL board_id : std_logic_vector(3 DOWNTO 0); + SIGNAL clk : STD_LOGIC; + SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); + SIGNAL dac_cs : std_logic; + SIGNAL denable : std_logic := '0'; -- default domino wave off + SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0'); + SIGNAL drs_dwrite : std_logic := '1'; + SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL mosi : std_logic := '0'; + SIGNAL sclk : std_logic; + SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); + SIGNAL sio : std_logic; + SIGNAL trigger : std_logic; + SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0); + SIGNAL wiz_cs : std_logic := '1'; + SIGNAL wiz_data : std_logic_vector(15 DOWNTO 0); + SIGNAL wiz_int : std_logic; + SIGNAL wiz_rd : std_logic := '1'; + SIGNAL wiz_reset : std_logic := '1'; + SIGNAL wiz_wr : std_logic := '1'; + + + -- Component Declarations + COMPONENT FAD_main + GENERIC ( + RAMADDRWIDTH64b : integer := 12 + ); + PORT ( + CLK : IN std_logic ; + SROUT_in_0 : IN std_logic ; + SROUT_in_1 : IN std_logic ; + SROUT_in_2 : IN std_logic ; + SROUT_in_3 : IN std_logic ; + adc_data_array : IN adc_data_array_type ; + adc_otr_array : IN std_logic_vector (3 DOWNTO 0); + board_id : IN std_logic_vector (3 DOWNTO 0); + crate_id : IN std_logic_vector (1 DOWNTO 0); + trigger : IN std_logic ; + wiz_int : IN std_logic ; + CLK_25_PS : OUT std_logic ; + CLK_50 : OUT std_logic ; + RSRLOAD : OUT std_logic := '0'; + SRCLK : OUT std_logic := '0'; + adc_oeb : OUT std_logic := '1'; + dac_cs : OUT std_logic ; + denable : OUT std_logic := '0'; -- default domino wave off + drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + drs_dwrite : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + mosi : OUT std_logic := '0'; + sclk : OUT std_logic ; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0); + wiz_addr : OUT std_logic_vector (9 DOWNTO 0); + wiz_cs : OUT std_logic := '1'; + wiz_rd : OUT std_logic := '1'; + wiz_reset : OUT std_logic := '1'; + wiz_wr : OUT std_logic := '1'; + sio : INOUT std_logic ; + wiz_data : INOUT std_logic_vector (15 DOWNTO 0) + ); + END COMPONENT; + COMPONENT adc_emulator + GENERIC ( + INPUT_FILE : string := "filename" + ); + PORT ( + clk : IN STD_LOGIC ; + data : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); + otr : OUT STD_LOGIC ; + oeb : IN STD_LOGIC + ); + END COMPONENT; + COMPONENT clock_generator + GENERIC ( + clock_period : time := 20 ns; + reset_time : time := 50 ns + ); + PORT ( + clk : OUT std_logic := '0'; + rst : OUT std_logic := '0' + ); + END COMPONENT; + COMPONENT max6662_emulator + GENERIC ( + DRS_TEMPERATURE : integer := 51 + ); + PORT ( + sclk : IN std_logic ; + sio : INOUT std_logic ; + sensor_cs : IN std_logic_vector (3 DOWNTO 0) + ); + END COMPONENT; + COMPONENT trigger_generator + GENERIC ( + TRIGGER_RATE : time := 1 ms; + PULSE_WIDTH : time := 20 ns + ); + PORT ( + trigger : OUT std_logic + ); + END COMPONENT; + COMPONENT w5300_emulator + PORT ( + addr : IN std_logic_vector (9 DOWNTO 0); + data : INOUT std_logic_vector (15 DOWNTO 0); + rd : IN std_logic ; + wr : IN std_logic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main; + FOR ALL : adc_emulator USE ENTITY FACT_FAD_TB_lib.adc_emulator; + FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator; + FOR ALL : max6662_emulator USE ENTITY FACT_FAD_TB_lib.max6662_emulator; + FOR ALL : trigger_generator USE ENTITY FACT_FAD_TB_lib.trigger_generator; + FOR ALL : w5300_emulator USE ENTITY FACT_FAD_TB_lib.w5300_emulator; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb_mainTB_ID + -- eb_ID 1: hard-wired IDs + board_id <= "0101"; + crate_id <= "01"; + + -- HDL Embedded Text Block 2 eb_mainTB_adc + -- eb_adc 2: ADC routing + adc_data_array(0) <= adc_data; + adc_data_array(1) <= adc_data; + adc_data_array(2) <= adc_data; + adc_data_array(3) <= adc_data; + adc_otr_array(0) <= adc_otr; + adc_otr_array(1) <= adc_otr; + adc_otr_array(2) <= adc_otr; + adc_otr_array(3) <= adc_otr; + + + -- Instance port mappings. + I_mainTB_FPGA : FAD_main + GENERIC MAP ( + RAMADDRWIDTH64b => 15 + ) + PORT MAP ( + CLK => clk, + SROUT_in_0 => SROUT_in_0, + SROUT_in_1 => SROUT_in_1, + SROUT_in_2 => SROUT_in_2, + SROUT_in_3 => SROUT_in_3, + adc_data_array => adc_data_array, + adc_otr_array => adc_otr_array, + board_id => board_id, + crate_id => crate_id, + trigger => trigger, + wiz_int => wiz_int, + CLK_25_PS => CLK_25_PS, + CLK_50 => CLK_50, + RSRLOAD => RSRLOAD, + SRCLK => SRCLK, + adc_oeb => adc_oeb, + dac_cs => dac_cs, + denable => denable, + drs_channel_id => drs_channel_id, + drs_dwrite => drs_dwrite, + led => led, + mosi => mosi, + sclk => sclk, + sensor_cs => sensor_cs, + wiz_addr => wiz_addr, + wiz_cs => wiz_cs, + wiz_rd => wiz_rd, + wiz_reset => wiz_reset, + wiz_wr => wiz_wr, + sio => sio, + wiz_data => wiz_data + ); + I_mainTB_adc : adc_emulator + GENERIC MAP ( + INPUT_FILE => "../memory_files/analog_input_ch0.txt" + ) + PORT MAP ( + clk => clk, + data => adc_data, + otr => adc_otr, + oeb => adc_oeb + ); + I_mainTB_clock : clock_generator + GENERIC MAP ( + clock_period => 20 ns, + reset_time => 50 ns + ) + PORT MAP ( + clk => clk, + rst => OPEN + ); + I_mainTB_max6662 : max6662_emulator + GENERIC MAP ( + DRS_TEMPERATURE => 51 + ) + PORT MAP ( + sclk => sclk, + sio => sio, + sensor_cs => sensor_cs + ); + I_mainTB_trigger : trigger_generator + GENERIC MAP ( + TRIGGER_RATE => 1 ms, + PULSE_WIDTH => 20 ns + ) + PORT MAP ( + trigger => trigger + ); + I_mainTB_w5300 : w5300_emulator + PORT MAP ( + addr => wiz_addr, + data => wiz_data, + rd => wiz_rd, + wr => wiz_wr + ); + +END struct; Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/max6662_emulator_beha.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/max6662_emulator_beha.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/max6662_emulator_beha.vhd (revision 9841) @@ -0,0 +1,65 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.spi_devices_emulator.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 09:26:11 28.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +ENTITY max6662_emulator IS + GENERIC( + DRS_TEMPERATURE : integer := 51 + ); + PORT( + sclk : in std_logic; + sio : inout std_logic; + sensor_cs : in std_logic_vector (3 DOWNTO 0) + ); + +-- Declarations + +END max6662_emulator ; + +ARCHITECTURE beha OF max6662_emulator IS + + signal data : std_logic_vector(15 downto 0) := (others => '0'); + signal spi_cycle_cnt : integer := 0; + signal temperature : integer range -55 to 150 := DRS_TEMPERATURE; + +BEGIN + + spi_cnt_proc: process (sclk) + begin + if rising_edge(sclk) then + if (sensor_cs /= "1111") then + spi_cycle_cnt <= spi_cycle_cnt + 1; + else + spi_cycle_cnt <= 0; + end if; + end if; + end process spi_cnt_proc; + + sensor_data_proc: process (spi_cycle_cnt, sclk) + begin + if falling_edge(sclk) then + sio <= 'Z'; + if (spi_cycle_cnt = 1) then + data <= '0' & conv_std_logic_vector(temperature + conv_integer(sensor_cs), 12) & "000"; + end if; + if (spi_cycle_cnt > 7) then + sio <= data(15); + data(15 downto 1) <= data(14 downto 0); + end if; + end if; + end process sensor_data_proc; + +END ARCHITECTURE beha; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/max6662_emulator_beha.vhd.bak =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/max6662_emulator_beha.vhd.bak (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/max6662_emulator_beha.vhd.bak (revision 9841) @@ -0,0 +1,65 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.spi_devices_emulator.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 09:26:11 28.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +ENTITY max6662_emulator IS + GENERIC( + DRS_TEMPERATURE : integer := 51 + ); + PORT( + sclk : IN std_logic; + sio : INOUT std_logic; + sensor_cs : IN std_logic_vector (3 DOWNTO 0) + ); + +-- Declarations + +END max6662_emulator ; + +ARCHITECTURE beha OF max6662_emulator IS + + signal data : std_logic_vector(15 downto 0) := (others => '0'); + signal spi_cycle_cnt : integer := 0; + signal temperature : integer range -55 to 150 := DRS_TEMPERATURE; + +BEGIN + + spi_cnt_proc: process (sclk) + begin + if rising_edge(sclk) then + if (sensor_cs /= "1111") then + spi_cycle_cnt <= spi_cycle_cnt + 1; + else + spi_cycle_cnt <= 0; + end if; + end if; + end process spi_cnt_proc; + + sensor_data_proc: process (spi_cycle_cnt, sclk) + begin + if falling_edge(sclk) then + sio <= 'Z'; + if (spi_cycle_cnt = 1) then + data <= '0' & conv_std_logic_vector(temperature + conv_integer(sensor_cs), 12) & "000"; + end if; + if (spi_cycle_cnt > 7) then + sio <= data(15); + data(15 downto 1) <= data(14 downto 0); + end if; + end if; + end process sensor_data_proc; + +END ARCHITECTURE beha; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/trigger__generator_beha.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/trigger__generator_beha.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/trigger__generator_beha.vhd (revision 9841) @@ -0,0 +1,42 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.simple_trigger.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 14:01:15 10.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +--USE ieee.NUMERIC_STD.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library FACT_FAD_lib; +use FACT_FAD_lib.fad_definitions.all; + +entity trigger_generator is + generic( + TRIGGER_RATE : time := 1 ms; + PULSE_WIDTH : time := 20 ns + ); + port( + trigger : out std_logic + ); +end trigger_generator ; + +architecture beha of trigger_generator is +begin + + trigger_proc: process + begin + trigger <= '0'; + wait for TRIGGER_RATE; + --trigger <= '1'; + wait for PULSE_WIDTH; + trigger <= '0'; + --wait; + end process trigger_proc; +end architecture beha; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/trigger__generator_beha.vhd.bak =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/trigger__generator_beha.vhd.bak (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/trigger__generator_beha.vhd.bak (revision 9841) @@ -0,0 +1,42 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.simple_trigger.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 14:01:15 10.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +--USE ieee.NUMERIC_STD.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library FACT_FAD_lib; +use FACT_FAD_lib.fad_definitions.all; + +entity trigger_generator is + generic( + TRIGGER_RATE : time := 1 ms; + PULSE_WIDTH : time := 20 ns + ); + port( + trigger : out std_logic + ); +end trigger_generator ; + +architecture beha of trigger_generator is +begin + + trigger_proc: process + begin + trigger <= '0'; + wait for TRIGGER_RATE; + trigger <= '1'; + wait for PULSE_WIDTH; + trigger <= '0'; + --wait; + end process trigger_proc; +end architecture beha; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd (revision 9841) @@ -0,0 +1,89 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.w5300_emulator.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 07:51:36 04.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +ENTITY w5300_emulator IS + PORT( + addr : in std_logic_vector (9 DOWNTO 0); + data : inout std_logic_vector (15 DOWNTO 0); + rd : in std_logic; + wr : in std_logic + ); + +-- Declarations + +END w5300_emulator ; + +architecture beha of w5300_emulator is + + signal open_done : std_logic_vector(7 downto 0) := (others => '0'); + signal data_temp : std_logic_vector(15 downto 0); + + signal RSR_0, RSR_1 : std_logic_vector (15 downto 0); + signal FIFOR_CNT : integer := 0; + +begin + + data <= data_temp when (rd = '0') else (others => 'Z'); + data_temp <= data when (wr = '0') else (others => 'Z'); + + set_proc : process + begin + RSR_0 <= X"0000"; + RSR_1 <= X"0000"; + wait for 250 us; + RSR_1 <= X"0001"; + wait for 200 us; + RSR_1 <= X"0002"; + wait; + end process set_proc; + + w5300_proc : process (addr) + begin + for i in 0 to 7 loop + if (addr = conv_integer(W5300_S0_SSR) + i * 64) then + if (open_done(i) = '0') then + data_temp <= X"0013"; + open_done(i) <= '1'; + else + data_temp <= X"0017"; + end if; + elsif (addr = conv_integer(W5300_S0_TX_FSR) + i * conv_integer(W5300_S_INC)) then + data_temp <= X"0000"; + elsif (addr = conv_integer(W5300_S0_TX_FSR + 2) + i * conv_integer(W5300_S_INC)) then + data_temp <= X"3C00"; + elsif (addr = conv_integer(W5300_S0_RX_RSR)) then + data_temp <= RSR_0; + elsif (addr = conv_integer(W5300_S0_RX_RSR) + 2) then + data_temp <= RSR_1; + elsif (addr = conv_integer(W5300_S0_RX_FIFOR)) then + if (FIFOR_CNT = 0) then + data_temp <= X"B000"; +-- FIFOR_CNT <= 1; + elsif (FIFOR_CNT = 1) then + data_temp <= X"0500"; + FIFOR_CNT <= 2; + elsif (FIFOR_CNT = 2) then + data_temp <= X"0000"; + end if; + else + null; + end if; + end loop; + end process w5300_proc; + + +end architecture beha; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd.bak =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd.bak (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd.bak (revision 9841) @@ -0,0 +1,89 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.w5300_emulator.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 07:51:36 04.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +ENTITY w5300_emulator IS + PORT( + addr : in std_logic_vector (9 DOWNTO 0); + data : inout std_logic_vector (15 DOWNTO 0); + rd : in std_logic; + wr : in std_logic + ); + +-- Declarations + +END w5300_emulator ; + +architecture beha of w5300_emulator is + + signal open_done : std_logic_vector(7 downto 0) := (others => '0'); + signal data_temp : std_logic_vector(15 downto 0); + + signal RSR_0, RSR_1 : std_logic_vector (15 downto 0); + signal FIFOR_CNT : integer := 0; + +begin + + data <= data_temp when (rd = '0') else (others => 'Z'); + data_temp <= data when (wr = '0') else (others => 'Z'); + + set_proc : process + begin + RSR_0 <= X"0000"; + RSR_1 <= X"0000"; + wait for 250 us; + RSR_1 <= X"0001"; + wait for 200 us; + RSR_1 <= X"0002"; + wait; + end process set_proc; + + w5300_proc : process (addr) + begin + for i in 0 to 7 loop + if (addr = conv_integer(W5300_S0_SSR) + i * 64) then + if (open_done(i) = '0') then + data_temp <= X"0013"; + open_done(i) <= '1'; + else + data_temp <= X"0017"; + end if; + elsif (addr = conv_integer(W5300_S0_TX_FSR) + i * conv_integer(W5300_S_INC)) then + data_temp <= X"0000"; + elsif (addr = conv_integer(W5300_S0_TX_FSR + 2) + i * conv_integer(W5300_S_INC)) then + data_temp <= X"3C00"; + elsif (addr = conv_integer(W5300_S0_RX_RSR)) then + data_temp <= RSR_0; + elsif (addr = conv_integer(W5300_S0_RX_RSR) + 2) then + data_temp <= RSR_1; + elsif (addr = conv_integer(W5300_S0_RX_FIFOR)) then + if (FIFOR_CNT = 0) then + data_temp <= X"A000"; +-- FIFOR_CNT <= 1; + elsif (FIFOR_CNT = 1) then + data_temp <= X"0500"; + FIFOR_CNT <= 2; + elsif (FIFOR_CNT = 2) then + data_temp <= X"0000"; + end if; + else + null; + end if; + end loop; + end process w5300_proc; + + +end architecture beha; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_adc_emulator_beha.vhd._fpf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_adc_emulator_beha.vhd._fpf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_adc_emulator_beha.vhd._fpf (revision 9841) @@ -0,0 +1,3 @@ +INCLUDE list { + DEFAULT atom 1 +} Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_clock_generator_beha.vhd._fpf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_clock_generator_beha.vhd._fpf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_clock_generator_beha.vhd._fpf (revision 9841) @@ -0,0 +1,3 @@ +INCLUDE list { + DEFAULT atom 1 +} Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_max6662_emulator_beha.vhd._fpf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_max6662_emulator_beha.vhd._fpf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_max6662_emulator_beha.vhd._fpf (revision 9841) @@ -0,0 +1,3 @@ +INCLUDE list { + DEFAULT atom 1 +} Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_trigger__generator_beha.vhd._fpf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_trigger__generator_beha.vhd._fpf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_trigger__generator_beha.vhd._fpf (revision 9841) @@ -0,0 +1,3 @@ +INCLUDE list { + DEFAULT atom 1 +} Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_w5300_emulator_beha.vhd._fpf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_w5300_emulator_beha.vhd._fpf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_w5300_emulator_beha.vhd._fpf (revision 9841) @@ -0,0 +1,3 @@ +INCLUDE list { + DEFAULT atom 1 +} Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.xrf/adc_emulator_tb_struct.xrf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.xrf/adc_emulator_tb_struct.xrf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.xrf/adc_emulator_tb_struct.xrf (revision 9841) @@ -0,0 +1,125 @@ +DESIGN adc_emulator_tb +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN adc_emulator_tb +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN adc_emulator_tb +VIEW symbol.sb +GRAPHIC 1,0 13 0 +DESIGN adc_emulator_tb +VIEW symbol.sb +GRAPHIC 1,0 14 0 +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 17 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 41,0 26 0 +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 33 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 0,0 36 2 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 185,0 41 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 191,0 42 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 207,0 43 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 199,0 44 0 +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 45 +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 46 +LIBRARY FACT_FAD_TB_lib +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 138,0 48 0 +DESIGN adc_emulator +VIEW symbol.sb +GRAPHIC 14,0 49 1 +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 48,0 53 0 +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 53,0 54 0 +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 58,0 55 0 +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 63,0 56 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 175,0 59 0 +DESIGN clock_generator +VIEW symbol.sb +GRAPHIC 14,0 60 1 +DESIGN clock_generator +VIEW @behavioral +GRAPHIC 48,0 65 0 +DESIGN clock_generator +VIEW @behavioral +GRAPHIC 53,0 66 0 +LIBRARY FACT_FAD_TB_lib +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 69 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 138,0 72 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 175,0 73 0 +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 76 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 223,0 79 0 +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 88 +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 89 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 138,0 91 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 145,0 92 1 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 187,0 96 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 193,0 97 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 201,0 98 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 209,0 99 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 175,0 101 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 182,0 102 1 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 187,0 107 0 +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 111 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.xrf/fad_main_tb_struct.xrf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.xrf/fad_main_tb_struct.xrf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/.xrf/fad_main_tb_struct.xrf (revision 9841) @@ -0,0 +1,507 @@ +DESIGN fad_main_tb +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN fad_main_tb +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN fad_main_tb +VIEW symbol.sb +GRAPHIC 1,0 13 0 +DESIGN fad_main_tb +VIEW symbol.sb +GRAPHIC 1,0 14 0 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 17 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 41,0 26 0 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 36 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 0,0 40 2 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 823,0 45 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 831,0 46 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 855,0 47 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 863,0 48 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 871,0 49 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 879,0 50 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 887,0 51 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 895,0 52 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 568,0 53 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 536,0 54 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 544,0 55 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 560,0 56 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 528,0 57 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 440,0 58 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 284,0 59 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 448,0 60 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 799,0 61 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 815,0 62 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 839,0 63 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 847,0 64 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 775,0 65 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 807,0 66 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 378,0 67 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 372,0 68 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 384,0 69 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 424,0 70 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 316,0 71 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 783,0 72 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 322,0 73 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 791,0 74 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 328,0 75 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 767,0 76 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 334,0 77 0 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 78 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 79 +LIBRARY FACT_FAD_lib +DESIGN @f@a@d_main +VIEW struct +GRAPHIC 233,0 81 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 14,0 82 1 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1755,0 86 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2710,0 87 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2715,0 88 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2720,0 89 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2725,0 90 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2282,0 91 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1976,0 92 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 923,0 93 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 928,0 94 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 464,0 95 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1062,0 96 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1389,0 97 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1725,0 98 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2987,0 99 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2992,0 100 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 833,0 101 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 3641,0 102 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 4144,0 103 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2448,0 104 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2453,0 105 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 163,0 106 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 4067,0 107 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 3631,0 108 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 3646,0 109 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1037,0 110 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1047,0 111 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1057,0 112 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 135,0 113 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1052,0 114 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 3636,0 115 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1042,0 116 0 +LIBRARY FACT_FAD_TB_lib +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 508,0 119 0 +DESIGN adc_emulator +VIEW symbol.sb +GRAPHIC 14,0 120 1 +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 48,0 124 0 +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 53,0 125 0 +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 58,0 126 0 +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 63,0 127 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 274,0 130 0 +DESIGN clock_generator +VIEW symbol.sb +GRAPHIC 14,0 131 1 +DESIGN clock_generator +VIEW @behavioral +GRAPHIC 48,0 136 0 +DESIGN clock_generator +VIEW @behavioral +GRAPHIC 53,0 137 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 362,0 140 0 +DESIGN max6662_emulator +VIEW symbol.sb +GRAPHIC 14,0 141 1 +DESIGN max6662_emulator +VIEW beha +GRAPHIC 48,0 145 0 +DESIGN max6662_emulator +VIEW beha +GRAPHIC 53,0 146 0 +DESIGN max6662_emulator +VIEW beha +GRAPHIC 58,0 147 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 414,0 150 0 +DESIGN trigger_generator +VIEW symbol.sb +GRAPHIC 14,0 151 1 +DESIGN trigger_generator +VIEW beha +GRAPHIC 48,0 156 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 306,0 159 0 +DESIGN w5300_emulator +VIEW beha +GRAPHIC 48,0 161 0 +DESIGN w5300_emulator +VIEW beha +GRAPHIC 53,0 162 0 +DESIGN w5300_emulator +VIEW beha +GRAPHIC 58,0 163 0 +DESIGN w5300_emulator +VIEW beha +GRAPHIC 63,0 164 0 +LIBRARY FACT_FAD_TB_lib +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 167 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 233,0 170 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 508,0 171 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 274,0 172 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 362,0 173 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 414,0 174 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 306,0 175 0 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 178 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 430,0 181 0 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 185 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 518,0 186 0 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 196 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 197 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 233,0 199 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 240,0 200 1 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 286,0 204 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 873,0 205 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 881,0 206 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 889,0 207 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 897,0 208 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 538,0 209 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 530,0 210 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 442,0 211 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 450,0 212 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 426,0 213 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 793,0 214 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 825,0 215 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 833,0 216 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 857,0 217 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 865,0 218 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 546,0 219 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 801,0 220 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 817,0 221 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 841,0 222 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 849,0 223 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 777,0 224 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 809,0 225 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 380,0 226 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 374,0 227 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 318,0 228 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 785,0 229 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 330,0 230 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 769,0 231 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 336,0 232 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 386,0 233 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 324,0 234 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 508,0 236 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 515,0 237 1 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 578,0 241 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 570,0 242 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 562,0 243 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 554,0 244 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 274,0 246 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 281,0 247 1 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 286,0 252 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 362,0 255 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 369,0 256 1 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 380,0 260 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 386,0 261 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 374,0 262 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 414,0 264 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 421,0 265 1 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 426,0 270 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 306,0 272 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 318,0 274 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 324,0 275 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 330,0 276 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 336,0 277 0 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 280 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_adc_emulator._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_adc_emulator._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_adc_emulator._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom Behavioral +DEFAULT_FILE atom adc_emulator_beha.vhd Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_adc_emulator_tb._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_adc_emulator_tb._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_adc_emulator_tb._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom adc_emulator_tb/struct.bd Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_clock_generator._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_clock_generator._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_clock_generator._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom clock_generator_beha.vhd +DEFAULT_ARCHITECTURE atom Behavioral Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_fad_main_tb._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_fad_main_tb._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_fad_main_tb._epf (revision 9841) @@ -0,0 +1,3 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom fad_main_tb/struct.bd +TOP_MARKER atom 1 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_max6662_emulator._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_max6662_emulator._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_max6662_emulator._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom max6662_emulator_beha.vhd +DEFAULT_ARCHITECTURE atom beha Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_trigger_generator._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_trigger_generator._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_trigger_generator._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom trigger__generator_beha.vhd +DEFAULT_ARCHITECTURE atom beha Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_w5300_emulator._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_w5300_emulator._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/_w5300_emulator._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom w5300_emulator_beha.vhd +DEFAULT_ARCHITECTURE atom beha Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/adc_emulator/symbol.sb =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/adc_emulator/symbol.sb (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/adc_emulator/symbol.sb (revision 9841) @@ -0,0 +1,1573 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_unsigned" +) +(DmPackageRef +library "ieee" +unitName "std_logic_textio" +) +(DmPackageRef +library "std" +unitName "textio" +) +] +libraryRefs [ +"ieee" +"std" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 4,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 87,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +decl (Decl +n "clk" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +uid 74,0 +) +*15 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "data" +t "STD_LOGIC_VECTOR" +b "(11 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +) +) +uid 76,0 +) +*16 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "otr" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +) +) +uid 78,0 +) +*17 (LogPort +port (LogicalPort +decl (Decl +n "oeb" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 4 +suid 4,0 +) +) +uid 80,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 100,0 +optionalChildren [ +*18 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *19 (MRCItem +litem &1 +pos 3 +dimension 20 +) +uid 102,0 +optionalChildren [ +*20 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 103,0 +) +*21 (MRCItem +litem &3 +pos 1 +dimension 23 +uid 104,0 +) +*22 (MRCItem +litem &4 +pos 2 +hidden 1 +dimension 20 +uid 105,0 +) +*23 (MRCItem +litem &14 +pos 0 +dimension 20 +uid 75,0 +) +*24 (MRCItem +litem &15 +pos 1 +dimension 20 +uid 77,0 +) +*25 (MRCItem +litem &16 +pos 2 +dimension 20 +uid 79,0 +) +*26 (MRCItem +litem &17 +pos 3 +dimension 20 +uid 81,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 106,0 +optionalChildren [ +*27 (MRCItem +litem &5 +pos 0 +dimension 20 +uid 107,0 +) +*28 (MRCItem +litem &7 +pos 1 +dimension 50 +uid 108,0 +) +*29 (MRCItem +litem &8 +pos 2 +dimension 100 +uid 109,0 +) +*30 (MRCItem +litem &9 +pos 3 +dimension 50 +uid 110,0 +) +*31 (MRCItem +litem &10 +pos 4 +dimension 100 +uid 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+editShortBounds 1 +uid 128,0 +optionalChildren [ +*48 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *49 (MRCItem +litem &35 +pos 3 +dimension 20 +) +uid 130,0 +optionalChildren [ +*50 (MRCItem +litem &36 +pos 0 +dimension 20 +uid 131,0 +) +*51 (MRCItem +litem &37 +pos 1 +dimension 23 +uid 132,0 +) +*52 (MRCItem +litem &38 +pos 2 +hidden 1 +dimension 20 +uid 133,0 +) +*53 (MRCItem +litem &47 +pos 0 +dimension 20 +uid 168,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 134,0 +optionalChildren [ +*54 (MRCItem +litem &39 +pos 0 +dimension 20 +uid 135,0 +) +*55 (MRCItem +litem &41 +pos 1 +dimension 50 +uid 136,0 +) +*56 (MRCItem +litem &42 +pos 2 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"Declarations" +blo "0,5800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "0,6000,2700,7000" +st "Ports:" +blo "0,6800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "0,10200,2400,11200" +st "User:" +blo "0,11000" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "0,5000,5800,6000" +st "Internal User:" +blo "0,5800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,11200,2000,11200" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,5000,0,5000" +tm "SyDeclarativeTextMgr" +) +) +lastUid 191,0 +activeModelName "Symbol:CDM" +) Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/adc_emulator_tb/struct.bd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/adc_emulator_tb/struct.bd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/adc_emulator_tb/struct.bd (revision 9841) @@ -0,0 +1,2868 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "ieee" +unitName "std_logic_unsigned" +) +(DmPackageRef +library "ieee" +unitName "std_logic_textio" +) +(DmPackageRef +library "std" +unitName "textio" +) +] +instances [ +(Instance +name "I_adcTB_adc" +duLibraryName "FACT_FAD_TB_lib" +duName "adc_emulator" +elements [ +(GiElement +name "INPUT_FILE" +type "string" +value "\"../memory_files/analog_input_ch0.txt\"" +) +] +mwi 0 +uid 138,0 +) +(Instance +name "I_adcTB_clock" +duLibraryName "FACT_FAD_TB_lib" +duName "clock_generator" +elements [ +(GiElement +name "clock_period" +type "time" +value "20 ns" +) +(GiElement +name "reset_time" +type "time" +value "50 ns" +) +] +mwi 0 +uid 175,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb_adcTB_oeb" +number "1" +) +] +libraryRefs [ +"ieee" +"std" +] +) +version "29.1" +appVersion "2009.2 (Build 10)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb" +) +(vvPair +variable "d_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb" +) +(vvPair +variable "date" +value "23.06.2010" +) +(vvPair +variable "day" +value "Mi" +) +(vvPair +variable "day_long" +value "Mittwoch" +) +(vvPair +variable "dd" +value "23" +) +(vvPair +variable "entity_name" +value "adc_emulator_tb" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "EEPC8" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_TB_lib" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR\\FACT_FAD_TB_lib\\work" +) +(vvPair +variable "mm" +value "06" +) +(vvPair +variable "module_name" +value "adc_emulator_tb" +) +(vvPair +variable "month" +value "Jun" +) +(vvPair +variable "month_long" +value "Juni" +) +(vvPair +variable "p" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb\\struct.bd" +) +(vvPair +variable "p_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$HDS_HOME/../Modeltech/win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "$HDS_HOME/../Precision/Mgc_home/bin" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "12:03:45" +) +(vvPair +variable "unit" +value "adc_emulator_tb" +) +(vvPair +variable "user" +value "Benjamin Krumm" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 52,0 +optionalChildren [ +*1 (Grouping +uid 9,0 +optionalChildren [ +*2 (CommentText +uid 11,0 +shape (Rectangle +uid 12,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 13,0 +va (VaSet +fg "0,0,32768" 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(MRCItem +litem &105 +pos 1 +dimension 23 +uid 99,0 +) +*119 (MRCItem +litem &106 +pos 2 +hidden 1 +dimension 20 +uid 100,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 101,0 +optionalChildren [ +*120 (MRCItem +litem &107 +pos 0 +dimension 20 +uid 102,0 +) +*121 (MRCItem +litem &109 +pos 1 +dimension 50 +uid 103,0 +) +*122 (MRCItem +litem &110 +pos 2 +dimension 100 +uid 104,0 +) +*123 (MRCItem +litem &111 +pos 3 +dimension 100 +uid 105,0 +) +*124 (MRCItem +litem &112 +pos 4 +dimension 50 +uid 106,0 +) +*125 (MRCItem +litem &113 +pos 5 +dimension 50 +uid 107,0 +) +*126 (MRCItem +litem &114 +pos 6 +dimension 80 +uid 108,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 96,0 +vaOverrides [ +] +) +] +) +uid 82,0 +type 1 +) +activeModelName "BlockDiag" +) Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/adc_emulator_tb/struct.bd.bak =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/adc_emulator_tb/struct.bd.bak (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/adc_emulator_tb/struct.bd.bak (revision 9841) @@ -0,0 +1,2864 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "ieee" +unitName "std_logic_unsigned" +) +(DmPackageRef +library "ieee" +unitName "std_logic_textio" +) +(DmPackageRef +library "std" +unitName "textio" +) +] +instances [ +(Instance +name "I_adcTB_adc" +duLibraryName "FACT_FAD_TB_lib" +duName "adc_emulator" +elements [ +(GiElement +name "INPUT_FILE" +type "string" +value "\"../memory_files/analog_input_ch0.txt\"" +) +] +mwi 0 +uid 138,0 +) +(Instance +name "I_adcTB_clock" +duLibraryName "FACT_FAD_TB_lib" +duName "clock_generator" +elements [ +(GiElement +name "clock_period" +type "time" +value "20 ns" +) +(GiElement +name "reset_time" +type "time" +value "50 ns" +) +] +mwi 0 +uid 175,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb_adcTB_oeb" +number "1" +) +] +libraryRefs [ +"ieee" +"std" +] +) +version "29.1" +appVersion "2009.2 (Build 10)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb" +) +(vvPair +variable "d_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb" +) +(vvPair +variable "date" +value "23.06.2010" +) +(vvPair +variable "day" +value "Mi" +) +(vvPair +variable "day_long" +value "Mittwoch" +) +(vvPair +variable "dd" +value "23" +) +(vvPair +variable "entity_name" +value "adc_emulator_tb" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "EEPC8" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_TB_lib" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR\\FACT_FAD_TB_lib\\work" +) +(vvPair +variable "mm" +value "06" +) +(vvPair +variable "module_name" +value "adc_emulator_tb" +) +(vvPair +variable "month" +value "Jun" +) +(vvPair +variable "month_long" +value "Juni" +) +(vvPair +variable "p" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb\\struct.bd" +) +(vvPair +variable "p_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$HDS_HOME/../Modeltech/win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "$HDS_HOME/../Precision/Mgc_home/bin" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "12:01:28" +) +(vvPair +variable "unit" +value "adc_emulator_tb" +) +(vvPair +variable "user" +value "Benjamin Krumm" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 52,0 +optionalChildren [ +*1 (Grouping +uid 9,0 +optionalChildren [ +*2 (CommentText +uid 11,0 +shape (Rectangle +uid 12,0 +sl 0 +va (VaSet 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/firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/clock_generator/symbol.sb =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/clock_generator/symbol.sb (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/clock_generator/symbol.sb (revision 9841) @@ -0,0 +1,1452 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_unsigned" +) +] +libraryRefs [ +"ieee" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 2,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 77,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm 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"SideDataDesignDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb" +) +(vvPair +variable "d_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb" +) +(vvPair +variable "date" +value "25.06.2010" +) +(vvPair +variable "day" +value "Fr" +) +(vvPair +variable "day_long" +value "Freitag" +) +(vvPair +variable "dd" +value "25" +) +(vvPair +variable "entity_name" +value "fad_main_tb" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "EEPC8" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_TB_lib" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work" +) +(vvPair +variable "mm" +value "06" +) +(vvPair +variable "module_name" +value "fad_main_tb" +) +(vvPair +variable "month" +value "Jun" +) +(vvPair +variable "month_long" +value "Juni" +) +(vvPair +variable "p" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd" +) +(vvPair +variable "p_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$HDS_HOME/../Modeltech/win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "$HDS_HOME/../Precision/Mgc_home/bin" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "08:48:16" +) +(vvPair +variable "unit" +value "fad_main_tb" +) +(vvPair +variable "user" +value "Benjamin Krumm" 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358,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 359,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "122250,47625,123000,48375" +) +tg (CPTG +uid 360,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 361,0 +va (VaSet +) +xt "124000,47500,130500,48500" +st "sensor_cs : (3:0)" +blo "124000,48300" +) +) +thePort (LogicalPort +decl (Decl +n "sensor_cs" +t "std_logic_vector" +b "(3 downto 0)" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +) +) +) +] +shape (Rectangle +uid 363,0 +va (VaSet +vasetType 1 +fg "0,49152,49152" +lineColor "0,0,50000" +lineWidth 2 +) +xt "123000,46000,133000,56000" +) +oxt "30000,3000,40000,13000" +ttg (MlTextGroup +uid 364,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*70 (Text +uid 365,0 +va (VaSet +font "Arial,8,1" +) +xt "123200,56000,130900,57000" +st "FACT_FAD_TB_lib" +blo "123200,56800" +tm "BdLibraryNameMgr" +) +*71 (Text +uid 366,0 +va (VaSet +font "Arial,8,1" +) +xt "123200,57000,130800,58000" +st "max6662_emulator" +blo "123200,57800" +tm "CptNameMgr" +) +*72 (Text +uid 367,0 +va (VaSet +font "Arial,8,1" +) +xt "123200,58000,131000,59000" +st "I_mainTB_max6662" +blo "123200,58800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 368,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 369,0 +text (MLText +uid 370,0 +va (VaSet +font "Courier New,8,0" +) +xt "123000,45200,143000,46000" +st "DRS_TEMPERATURE = 51 ( integer ) " +) +header "" +) +elements [ +(GiElement +name "DRS_TEMPERATURE" +type "integer" +value "51" +) +] +) +viewicon (ZoomableIcon +uid 371,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "123250,54250,124750,55750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sIVOD 1 +) +archFileType "UNKNOWN" +) +*73 (Net +uid 372,0 +decl (Decl +n "sensor_cs" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 6 +suid 6,0 +) +declText (MLText +uid 373,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,34000,30000,34800" +st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" +) +) +*74 (Net +uid 378,0 +decl (Decl +n "sclk" +t "std_logic" +o 7 +suid 7,0 +) +declText (MLText +uid 379,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,33200,20000,34000" +st "SIGNAL sclk : std_logic" +) +) +*75 (Net +uid 384,0 +decl (Decl +n "sio" +t "std_logic" +preAdd 0 +posAdd 0 +o 8 +suid 8,0 +) +declText (MLText +uid 385,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,34800,20000,35600" +st "SIGNAL sio : std_logic" +) +) +*76 (SaComponent +uid 414,0 +optionalChildren [ +*77 (CptPort +uid 410,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 411,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,31625,58750,32375" +) +tg (CPTG +uid 412,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 413,0 +va (VaSet +) +xt "54200,31500,57000,32500" +st "trigger" +ju 2 +blo "57000,32300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "trigger" +t "std_logic" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +] +shape (Rectangle +uid 415,0 +va (VaSet +vasetType 1 +fg "0,49152,49152" +lineColor "0,0,50000" +lineWidth 2 +) +xt "50000,30000,58000,36000" +) +oxt "19000,4000,29000,14000" +ttg (MlTextGroup +uid 416,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*78 (Text +uid 417,0 +va (VaSet +font "Arial,8,1" +) +xt "50200,36000,57900,37000" +st "FACT_FAD_TB_lib" +blo "50200,36800" +tm "BdLibraryNameMgr" +) +*79 (Text +uid 418,0 +va (VaSet +font "Arial,8,1" +) +xt "50200,37000,57500,38000" +st "trigger_generator" +blo "50200,37800" +tm "CptNameMgr" +) +*80 (Text +uid 419,0 +va (VaSet +font "Arial,8,1" +) +xt "50200,38000,57400,39000" +st "I_mainTB_trigger" +blo "50200,38800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 420,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 421,0 +text (MLText +uid 422,0 +va (VaSet +font "Courier New,8,0" +) +xt "50000,28400,68500,30000" +st "TRIGGER_RATE = 1 ms ( time ) +PULSE_WIDTH = 20 ns ( time ) " +) +header "" +) +elements [ +(GiElement +name "TRIGGER_RATE" +type "time" +value "1 ms" +) +(GiElement +name "PULSE_WIDTH" +type "time" +value "20 ns" +) +] +) +viewicon (ZoomableIcon +uid 423,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "50250,34250,51750,35750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sIVOD 1 +) +archFileType "UNKNOWN" +) +*81 (Net +uid 424,0 +decl (Decl +n "trigger" +t "std_logic" +preAdd 0 +posAdd 0 +o 9 +suid 9,0 +) +declText (MLText +uid 425,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,35600,20000,36400" +st "SIGNAL trigger : std_logic" +) +) +*82 (HdlText +uid 430,0 +optionalChildren [ +*83 (EmbeddedText +uid 436,0 +commentText (CommentText +uid 437,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 438,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "50000,45000,60000,49000" +) +oxt "0,0,18000,5000" +text (MLText +uid 439,0 +va (VaSet +) +xt "50200,45200,60200,48200" +st " +-- eb_ID 1: hard-wired IDs +board_id <= \"0101\"; +crate_id <= \"01\"; + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 4000 +visibleWidth 10000 +) +) +) +] +shape (Rectangle +uid 431,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "50000,40000,58000,45000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 432,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*84 (Text +uid 433,0 +va (VaSet +font "Arial,8,1" +) +xt "51150,41000,57350,42000" +st "eb_mainTB_ID" +blo "51150,41800" +tm "HdlTextNameMgr" +) +*85 (Text +uid 434,0 +va (VaSet +font "Arial,8,1" +) +xt "51150,42000,51950,43000" +st "1" +blo "51150,42800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 435,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "50250,43250,51750,44750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*86 (Net +uid 440,0 +decl (Decl +n "board_id" +t "std_logic_vector" +b "(3 downto 0)" +preAdd 0 +posAdd 0 +o 10 +suid 10,0 +) +declText (MLText +uid 441,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,26000,30000,26800" +st "SIGNAL board_id : std_logic_vector(3 downto 0)" +) +) +*87 (Net +uid 448,0 +decl (Decl +n "crate_id" +t "std_logic_vector" +b "(1 downto 0)" +o 11 +suid 11,0 +) +declText (MLText +uid 449,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,27600,30000,28400" +st "SIGNAL crate_id : std_logic_vector(1 downto 0)" +) +) +*88 (SaComponent +uid 508,0 +optionalChildren [ +*89 (CptPort +uid 489,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 490,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "29250,52625,30000,53375" +) +tg (CPTG +uid 491,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 492,0 +va (VaSet +) +xt "31000,52500,32300,53500" +st "clk" +blo "31000,53300" +) +) +thePort (LogicalPort +decl (Decl +n "clk" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*90 (CptPort +uid 493,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 494,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40000,54625,40750,55375" +) +tg (CPTG +uid 495,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 496,0 +va (VaSet +) +xt "34200,54500,39000,55500" +st "data : (11:0)" +ju 2 +blo "39000,55300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "data" +t "STD_LOGIC_VECTOR" +b "(11 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +) +) +) +*91 (CptPort +uid 497,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 498,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40000,52625,40750,53375" +) +tg (CPTG +uid 499,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 500,0 +va (VaSet +) +xt "37700,52500,39000,53500" +st "otr" +ju 2 +blo "39000,53300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "otr" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +) +) +) +*92 (CptPort +uid 501,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 502,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40000,53625,40750,54375" +) +tg (CPTG +uid 503,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 504,0 +va (VaSet +) +xt "37400,53500,39000,54500" +st "oeb" +ju 2 +blo "39000,54300" +) +) +thePort (LogicalPort +decl (Decl +n "oeb" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 4 +suid 4,0 +) +) +) +] +shape (Rectangle +uid 509,0 +va (VaSet +vasetType 1 +fg "0,49152,49152" +lineColor "0,0,50000" +lineWidth 2 +) +xt "30000,51000,40000,58000" +) +oxt "29000,7000,39000,17000" +ttg (MlTextGroup +uid 510,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*93 (Text +uid 511,0 +va (VaSet +font "Arial,8,1" +) +xt "30200,58000,37900,59000" +st "FACT_FAD_TB_lib" +blo "30200,58800" +tm "BdLibraryNameMgr" +) +*94 (Text +uid 512,0 +va (VaSet +font "Arial,8,1" +) +xt "30200,59000,36000,60000" +st "adc_emulator" +blo "30200,59800" +tm "CptNameMgr" +) +*95 (Text +uid 513,0 +va (VaSet +font "Arial,8,1" +) +xt "30200,60000,36200,61000" +st "I_mainTB_adc" +blo "30200,60800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 514,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 515,0 +text (MLText +uid 516,0 +va (VaSet +font "Courier New,8,0" +) +xt "30000,50200,65500,51000" +st "INPUT_FILE = \"../memory_files/analog_input_ch0.txt\" ( string ) " +) +header "" +) +elements [ +(GiElement +name "INPUT_FILE" +type "string" +value "\"../memory_files/analog_input_ch0.txt\"" +) +] +) +viewicon (ZoomableIcon +uid 517,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "30250,56250,31750,57750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sIVOD 1 +) +archFileType "UNKNOWN" +) +*96 (HdlText +uid 518,0 +optionalChildren [ +*97 (EmbeddedText +uid 524,0 +commentText (CommentText +uid 525,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 526,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "50000,57000,62000,67000" +) +oxt "0,0,18000,5000" +text (MLText +uid 527,0 +va (VaSet +) +xt "50200,57200,62100,66200" +st " +-- eb_adc 2: ADC routing +adc_data_array(0) <= adc_data; +adc_data_array(1) <= adc_data; +adc_data_array(2) <= adc_data; +adc_data_array(3) <= adc_data; +adc_otr_array(0) <= adc_otr; +adc_otr_array(1) <= adc_otr; +adc_otr_array(2) <= adc_otr; +adc_otr_array(3) <= adc_otr; + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 10000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 519,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "50000,51000,58000,57000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 520,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*98 (Text +uid 521,0 +va (VaSet +font "Arial,8,1" +) +xt "51150,52000,57850,53000" +st "eb_mainTB_adc" +blo "51150,52800" +tm "HdlTextNameMgr" +) +*99 (Text +uid 522,0 +va (VaSet +font "Arial,8,1" +) +xt "51150,53000,51950,54000" +st "2" +blo "51150,53800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 523,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "50250,55250,51750,56750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*100 (Net +uid 528,0 +decl (Decl +n "adc_otr_array" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 12 +suid 12,0 +) +declText (MLText +uid 529,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,25200,30000,26000" +st "SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0)" +) +) +*101 (Net +uid 536,0 +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 13 +suid 13,0 +) +declText (MLText +uid 537,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22800,25500,23600" +st "SIGNAL adc_data_array : adc_data_array_type" +) +) +*102 (Net +uid 544,0 +decl (Decl +n "adc_oeb" +t "std_logic" +preAdd 0 +posAdd 0 +o 14 +suid 14,0 +) +declText (MLText +uid 545,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,23600,20000,24400" +st "SIGNAL adc_oeb : std_logic" +) +) +*103 (Net +uid 560,0 +decl (Decl +n "adc_otr" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 16 +suid 16,0 +) +declText (MLText +uid 561,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,24400,20000,25200" +st "SIGNAL adc_otr : STD_LOGIC" +) +) +*104 (Net +uid 568,0 +decl (Decl +n "adc_data" +t "std_logic_vector" +b "(11 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 17 +suid 17,0 +) +declText (MLText +uid 569,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22000,30500,22800" +st "SIGNAL adc_data : std_logic_vector(11 DOWNTO 0)" +) +) +*105 (Net +uid 767,0 +decl (Decl +n "wiz_reset" +t "std_logic" +o 21 +suid 23,0 +i "'1'" +) +declText (MLText +uid 768,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,40400,33500,41200" +st "SIGNAL wiz_reset : std_logic := '1'" +) +) +*106 (Net +uid 775,0 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 DOWNTO 0)" +posAdd 0 +o 22 +suid 24,0 +i "(OTHERS => '0')" +) +declText (MLText +uid 776,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,31600,39500,32400" +st "SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" +) +) +*107 (Net +uid 783,0 +decl (Decl +n "wiz_cs" +t "std_logic" +o 23 +suid 25,0 +i "'1'" +) +declText (MLText +uid 784,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,37200,33500,38000" +st "SIGNAL wiz_cs : std_logic := '1'" +) +) +*108 (Net +uid 791,0 +decl (Decl +n "wiz_int" +t "std_logic" +o 24 +suid 26,0 +) +declText (MLText +uid 792,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,38800,20000,39600" +st "SIGNAL wiz_int : std_logic" +) +) +*109 (Net +uid 799,0 +decl (Decl +n "dac_cs" +t "std_logic" +o 25 +suid 27,0 +) +declText (MLText +uid 800,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,28400,20000,29200" +st "SIGNAL dac_cs : std_logic" +) +) +*110 (Net +uid 807,0 +decl (Decl +n "mosi" +t "std_logic" +o 26 +suid 28,0 +i "'0'" +) +declText (MLText +uid 808,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,32400,33500,33200" +st "SIGNAL mosi : std_logic := '0'" +) +) +*111 (Net +uid 815,0 +decl (Decl +n "denable" +t "std_logic" +eolc "-- default domino wave off" +posAdd 0 +o 27 +suid 29,0 +i "'0'" +) +declText (MLText +uid 816,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,29200,47000,30000" +st "SIGNAL denable : std_logic := '0' -- default domino wave off" +) +) +*112 (Net +uid 823,0 +decl (Decl +n "CLK_25_PS" +t "std_logic" +o 28 +suid 30,0 +) +declText (MLText +uid 824,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,15600,20000,16400" +st "SIGNAL CLK_25_PS : std_logic" +) +) +*113 (Net +uid 831,0 +decl (Decl +n "CLK_50" +t "std_logic" +o 29 +suid 31,0 +) +declText (MLText +uid 832,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,16400,20000,17200" +st "SIGNAL CLK_50 : std_logic" +) +) +*114 (Net +uid 839,0 +decl (Decl +n "drs_channel_id" +t "std_logic_vector" +b "(3 downto 0)" +o 30 +suid 32,0 +i "(others => '0')" +) +declText (MLText +uid 840,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,30000,39500,30800" +st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" +) +) +*115 (Net +uid 847,0 +decl (Decl +n "drs_dwrite" +t "std_logic" +o 31 +suid 33,0 +i "'1'" +) +declText (MLText +uid 848,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,30800,33500,31600" +st "SIGNAL drs_dwrite : std_logic := '1'" +) +) +*116 (Net +uid 855,0 +decl (Decl +n "RSRLOAD" +t "std_logic" +o 32 +suid 34,0 +i "'0'" +) +declText (MLText +uid 856,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,17200,33500,18000" +st "SIGNAL RSRLOAD : std_logic := '0'" +) +) +*117 (Net +uid 863,0 +decl (Decl +n "SRCLK" +t "std_logic" +o 33 +suid 35,0 +i "'0'" +) +declText (MLText +uid 864,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,18000,33500,18800" +st "SIGNAL SRCLK : std_logic := '0'" +) +) +*118 (Net +uid 871,0 +decl (Decl +n "SROUT_in_0" +t "std_logic" +o 30 +suid 36,0 +) +declText (MLText +uid 872,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,18800,20000,19600" +st "SIGNAL SROUT_in_0 : std_logic" +) +) +*119 (Net +uid 879,0 +decl (Decl +n "SROUT_in_1" +t "std_logic" +o 31 +suid 37,0 +) +declText (MLText +uid 880,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,19600,20000,20400" +st "SIGNAL SROUT_in_1 : std_logic" +) +) +*120 (Net +uid 887,0 +decl (Decl +n "SROUT_in_2" +t "std_logic" +o 32 +suid 38,0 +) +declText (MLText +uid 888,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,20400,20000,21200" +st "SIGNAL SROUT_in_2 : std_logic" +) +) +*121 (Net +uid 895,0 +decl (Decl +n "SROUT_in_3" +t "std_logic" +o 33 +suid 39,0 +) +declText (MLText +uid 896,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,21200,20000,22000" +st "SIGNAL SROUT_in_3 : std_logic" +) +) +*122 (Wire +uid 286,0 +shape (OrthoPolyLine +uid 287,0 +va (VaSet +vasetType 3 +) +xt "58750,21000,80250,21000" +pts [ +"58750,21000" +"80250,21000" +] +) +start &48 +end &27 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 288,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 289,0 +va (VaSet +) +xt "71000,20000,72300,21000" +st "clk" +blo "71000,20800" +tm "WireNameMgr" +) +) +on &53 +) +*123 (Wire +uid 318,0 +shape (OrthoPolyLine +uid 319,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "109750,21000,122250,21000" +pts [ +"109750,21000" +"122250,21000" +] +) +start &19 +end &55 +sat 32 +eat 32 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 320,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 321,0 +va (VaSet +) +xt "111000,20000,117000,21000" +st "wiz_addr : (9:0)" +blo "111000,20800" +tm "WireNameMgr" +) +) +on &62 +) +*124 (Wire +uid 324,0 +shape (OrthoPolyLine +uid 325,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "109750,22000,122250,22000" +pts [ +"109750,22000" +"122250,22000" +] +) +start &20 +end &56 +sat 32 +eat 32 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 326,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" 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1 +si 0 +tg (WTG +uid 446,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 447,0 +va (VaSet +) +xt "71000,33000,76900,34000" +st "board_id : (3:0)" +blo "71000,33800" +tm "WireNameMgr" +) +) +on &86 +) +*132 (Wire +uid 450,0 +shape (OrthoPolyLine +uid 451,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "58000,35000,80250,43000" +pts [ +"80250,35000" +"65000,35000" +"65000,43000" +"58000,43000" +] +) +start &18 +end &82 +sat 32 +eat 2 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 454,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 455,0 +va (VaSet +) +xt "71000,34000,76700,35000" +st "crate_id : (1:0)" +blo "71000,34800" +tm "WireNameMgr" +) +) +on &87 +) +*133 (Wire +uid 530,0 +shape (OrthoPolyLine +uid 531,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "58000,42000,80250,53000" +pts [ +"80250,42000" +"68000,42000" +"68000,53000" +"58000,53000" +] +) +start &28 +end &96 +sat 32 +eat 2 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 534,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 535,0 +va (VaSet +) +xt "71000,41000,79000,42000" +st "adc_otr_array : (3:0)" +blo "71000,41800" +tm "WireNameMgr" +) +) +on &100 +) +*134 (Wire +uid 538,0 +shape (OrthoPolyLine +uid 539,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "58000,48000,80250,55000" +pts [ +"80250,48000" +"70000,48000" +"70000,55000" +"58000,55000" +] +) +start &29 +end &96 +sat 32 +eat 2 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 542,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 543,0 +va (VaSet +) +xt "71000,47000,76900,48000" +st "adc_data_array" +blo "71000,47800" +tm "WireNameMgr" +) +) +on &101 +) +*135 (Wire +uid 546,0 +shape (OrthoPolyLine +uid 547,0 +va (VaSet +vasetType 3 +) +xt "58000,43000,80250,54000" +pts [ +"80250,43000" +"69000,43000" +"69000,54000" +"58000,54000" +] +) +start &16 +end &96 +sat 32 +eat 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 550,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 551,0 +va (VaSet +) +xt "71000,42000,74200,43000" +st "adc_oeb" +blo "71000,42800" +tm "WireNameMgr" +) +) +on &102 +) +*136 (Wire +uid 554,0 +shape (OrthoPolyLine +uid 555,0 +va (VaSet +vasetType 3 +) +xt "40750,54000,50000,54000" +pts [ +"50000,54000" +"40750,54000" +] +) +start &96 +end &92 +sat 2 +eat 32 +st 0 +sf 1 +tg (WTG +uid 558,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 559,0 +va (VaSet +) +xt "42000,53000,45200,54000" +st "adc_oeb" +blo "42000,53800" +tm "WireNameMgr" +) +) +on &102 +) +*137 (Wire +uid 562,0 +shape (OrthoPolyLine +uid 563,0 +va (VaSet +vasetType 3 +) +xt "40750,53000,50000,53000" +pts [ +"40750,53000" +"50000,53000" +] +) +start &91 +end &96 +sat 32 +eat 1 +st 0 +sf 1 +tg (WTG +uid 566,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 567,0 +va (VaSet +) +xt "42000,52000,44900,53000" +st "adc_otr" +blo "42000,52800" +tm "WireNameMgr" +) +) +on &103 +) +*138 (Wire +uid 570,0 +shape (OrthoPolyLine +uid 571,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "40750,55000,50000,55000" +pts [ +"40750,55000" +"50000,55000" +] +) +start &90 +end &96 +sat 32 +eat 1 +sty 1 +st 0 +sf 1 +tg (WTG +uid 574,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 575,0 +va (VaSet +) +xt "42000,54000,48400,55000" +st "adc_data : (11:0)" +blo "42000,54800" +tm "WireNameMgr" +) +) +on &104 +) +*139 (Wire +uid 578,0 +shape (OrthoPolyLine +uid 579,0 +va (VaSet +vasetType 3 +) +xt "25000,53000,29250,53000" +pts [ +"29250,53000" +"25000,53000" +] +) +start &89 +sat 32 +eat 16 +st 0 +sf 1 +tg (WTG +uid 582,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 583,0 +va (VaSet +) +xt "26250,52000,27550,53000" +st "clk" +blo "26250,52800" +tm "WireNameMgr" +) +) +on &53 +) +*140 (Wire +uid 769,0 +shape (OrthoPolyLine +uid 770,0 +va (VaSet +vasetType 3 +) +xt "109750,24000,116000,24000" +pts [ +"109750,24000" +"116000,24000" +] +) +start &13 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 773,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 774,0 +va (VaSet +) +xt "111000,23000,114600,24000" +st "wiz_reset" +blo "111000,23800" +tm "WireNameMgr" +) +) +on &105 +) +*141 (Wire +uid 777,0 +shape (OrthoPolyLine +uid 778,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "109750,70000,116000,70000" +pts [ +"109750,70000" +"116000,70000" +] +) +start &14 +sat 32 +eat 16 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 781,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 782,0 +va (VaSet +) +xt "111000,69000,115000,70000" +st "led : (7:0)" +blo "111000,69800" +tm "WireNameMgr" +) +) +on &106 +) +*142 (Wire +uid 785,0 +shape (OrthoPolyLine +uid 786,0 +va (VaSet +vasetType 3 +) +xt "109750,28000,116000,28000" +pts [ +"109750,28000" +"116000,28000" +] +) +start &21 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 789,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 790,0 +va (VaSet +) +xt "111000,27000,113700,28000" +st "wiz_cs" +blo "111000,27800" +tm "WireNameMgr" +) +) +on &107 +) +*143 (Wire +uid 793,0 +shape (OrthoPolyLine +uid 794,0 +va (VaSet +vasetType 3 +) +xt "109750,27000,116000,27000" +pts [ +"116000,27000" +"109750,27000" +] +) +end &24 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 797,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 798,0 +va (VaSet +) +xt "111000,26000,113700,27000" +st "wiz_int" +blo "111000,26800" +tm "WireNameMgr" +) +) +on &108 +) +*144 (Wire +uid 801,0 +shape (OrthoPolyLine +uid 802,0 +va (VaSet +vasetType 3 +) +xt "109750,40000,116000,40000" +pts [ +"109750,40000" +"116000,40000" +] +) +start &40 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 805,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 806,0 +va (VaSet +) +xt "111000,39000,113800,40000" +st "dac_cs" +blo "111000,39800" +tm "WireNameMgr" +) +) +on &109 +) +*145 (Wire +uid 809,0 +shape (OrthoPolyLine +uid 810,0 +va (VaSet +vasetType 3 +) +xt "109750,53000,116000,53000" +pts [ +"109750,53000" +"116000,53000" +] +) +start &42 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 813,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 814,0 +va (VaSet +) +xt "111000,52000,113000,53000" +st "mosi" +blo "111000,52800" +tm "WireNameMgr" +) +) +on &110 +) +*146 (Wire +uid 817,0 +shape (OrthoPolyLine +uid 818,0 +va (VaSet +vasetType 3 +) +xt "109750,71000,116000,71000" +pts [ +"109750,71000" +"116000,71000" +] +) +start &43 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 821,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 822,0 +va (VaSet +) +xt "111000,70000,114000,71000" +st "denable" +blo "111000,70800" +tm "WireNameMgr" +) +) +on &111 +) +*147 (Wire +uid 825,0 +shape (OrthoPolyLine +uid 826,0 +va (VaSet +vasetType 3 +) +xt "70000,23000,80250,23000" +pts [ +"80250,23000" +"70000,23000" +] +) +start &25 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 829,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 830,0 +va (VaSet +) +xt "71000,22000,75500,23000" +st "CLK_25_PS" +blo "71000,22800" +tm "WireNameMgr" +) +) +on &112 +) +*148 (Wire +uid 833,0 +shape (OrthoPolyLine +uid 834,0 +va (VaSet +vasetType 3 +) +xt "70000,22000,80250,22000" +pts [ +"80250,22000" +"70000,22000" +] +) +start &26 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 837,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 838,0 +va (VaSet +) +xt "71000,21000,74100,22000" +st "CLK_50" +blo "71000,21800" +tm "WireNameMgr" +) +) +on &113 +) +*149 (Wire +uid 841,0 +shape (OrthoPolyLine +uid 842,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "70000,62000,80250,62000" +pts [ +"80250,62000" +"70000,62000" +] +) +start &30 +sat 32 +eat 16 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 845,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 846,0 +va (VaSet +) +xt "71000,61000,79500,62000" +st "drs_channel_id : (3:0)" +blo "71000,61800" +tm "WireNameMgr" +) +) +on &114 +) +*150 (Wire +uid 849,0 +shape (OrthoPolyLine +uid 850,0 +va (VaSet +vasetType 3 +) +xt "70000,63000,80250,63000" +pts [ +"80250,63000" +"70000,63000" +] +) +start &31 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 853,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 854,0 +va (VaSet +) +xt "71000,62000,75300,63000" +st "drs_dwrite" +blo "71000,62800" +tm "WireNameMgr" +) +) +on &115 +) +*151 (Wire +uid 857,0 +shape (OrthoPolyLine +uid 858,0 +va (VaSet +vasetType 3 +) +xt "70000,64000,80250,64000" +pts [ +"80250,64000" +"70000,64000" +] +) +start &36 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 861,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 862,0 +va (VaSet +) +xt "71000,63000,75200,64000" +st "RSRLOAD" +blo "71000,63800" +tm "WireNameMgr" +) +) +on &116 +) +*152 (Wire +uid 865,0 +shape (OrthoPolyLine +uid 866,0 +va (VaSet +vasetType 3 +) +xt "70000,66000,80250,66000" +pts [ +"80250,66000" +"70000,66000" +] +) +start &37 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 869,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 870,0 +va (VaSet +) +xt "71000,65000,74000,66000" +st "SRCLK" +blo "71000,65800" +tm "WireNameMgr" +) +) +on &117 +) +*153 (Wire +uid 873,0 +shape (OrthoPolyLine +uid 874,0 +va (VaSet +vasetType 3 +) +xt "70000,58000,80250,58000" +pts [ +"70000,58000" +"80250,58000" +] +) +end &32 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 877,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 878,0 +va (VaSet +) +xt "71000,57000,76400,58000" +st "SROUT_in_0" +blo "71000,57800" +tm "WireNameMgr" +) +) +on &118 +) +*154 (Wire +uid 881,0 +shape (OrthoPolyLine +uid 882,0 +va (VaSet +vasetType 3 +) +xt "70000,59000,80250,59000" +pts [ +"70000,59000" +"80250,59000" +] +) +end &33 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 885,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 886,0 +va (VaSet +) +xt "71000,58000,76400,59000" +st "SROUT_in_1" +blo "71000,58800" +tm "WireNameMgr" +) +) +on &119 +) +*155 (Wire +uid 889,0 +shape (OrthoPolyLine +uid 890,0 +va (VaSet +vasetType 3 +) +xt "70000,60000,80250,60000" +pts [ +"70000,60000" +"80250,60000" +] +) +end &34 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 893,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 894,0 +va (VaSet +) +xt "71000,59000,76400,60000" +st "SROUT_in_2" +blo "71000,59800" +tm "WireNameMgr" +) +) +on &120 +) +*156 (Wire +uid 897,0 +shape (OrthoPolyLine +uid 898,0 +va (VaSet +vasetType 3 +) +xt "70000,61000,80250,61000" +pts [ +"70000,61000" +"80250,61000" +] +) +end &35 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 901,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 902,0 +va (VaSet +) +xt "71000,60000,76400,61000" +st "SROUT_in_3" +blo "71000,60800" +tm "WireNameMgr" +) +) +on &121 +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" 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+uid 82,0 +type 1 +) +activeModelName "BlockDiag" +) Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak (revision 9841) @@ -0,0 +1,7015 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "ieee" +unitName "std_logic_unsigned" +) +(DmPackageRef +library "FACT_FAD_lib" +unitName "fad_definitions" +) +(DmPackageRef +library "ieee" +unitName "std_logic_textio" +) +(DmPackageRef +library "std" +unitName "textio" +) +] +instances [ +(Instance +name "I_mainTB_FPGA" +duLibraryName "FACT_FAD_lib" +duName "FAD_main" +elements [ +(GiElement +name "RAMADDRWIDTH64b" +type "integer" +value "15" +) +] +mwi 0 +uid 233,0 +) +(Instance +name "I_mainTB_clock" +duLibraryName "FACT_FAD_TB_lib" +duName "clock_generator" +elements [ +(GiElement +name "clock_period" +type "time" +value "20 ns" +) +(GiElement +name "reset_time" +type "time" +value "50 ns" +) +] +mwi 0 +uid 274,0 +) +(Instance +name "I_mainTB_w5300" +duLibraryName "FACT_FAD_TB_lib" +duName "w5300_emulator" +elements [ +] +mwi 0 +uid 306,0 +) +(Instance +name "I_mainTB_max6662" +duLibraryName "FACT_FAD_TB_lib" +duName "max6662_emulator" +elements [ +(GiElement +name "DRS_TEMPERATURE" +type "integer" +value "51" +) +] +mwi 0 +uid 362,0 +) +(Instance +name "I_mainTB_trigger" +duLibraryName "FACT_FAD_TB_lib" +duName "trigger_generator" +elements [ +(GiElement +name "TRIGGER_RATE" +type "time" +value "1 ms" +) +(GiElement +name "PULSE_WIDTH" +type "time" +value "20 ns" +) +] +mwi 0 +uid 414,0 +) +(Instance +name "I_mainTB_adc" +duLibraryName "FACT_FAD_TB_lib" +duName "adc_emulator" +elements [ +(GiElement +name "INPUT_FILE" +type "string" +value "\"../memory_files/analog_input_ch0.txt\"" +) +] +mwi 0 +uid 508,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb_mainTB_ID" +number "1" +) +(EmbeddedInstance +name "eb_mainTB_adc" +number "2" +) +] +libraryRefs [ +"ieee" +"FACT_FAD_lib" +"std" +] +) +version "29.1" +appVersion "2009.2 (Build 10)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb" +) +(vvPair +variable "d_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb" +) +(vvPair +variable "date" +value "25.06.2010" +) +(vvPair +variable "day" +value "Fr" +) +(vvPair +variable "day_long" +value "Freitag" +) +(vvPair +variable "dd" +value "25" +) +(vvPair +variable "entity_name" +value "fad_main_tb" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "EEPC8" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_TB_lib" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work" +) +(vvPair +variable "mm" +value "06" +) +(vvPair +variable "module_name" +value "fad_main_tb" +) +(vvPair +variable "month" +value "Jun" +) +(vvPair +variable "month_long" +value "Juni" +) +(vvPair +variable "p" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd" +) +(vvPair +variable "p_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$HDS_HOME/../Modeltech/win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "$HDS_HOME/../Precision/Mgc_home/bin" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "08:17:47" +) +(vvPair +variable "unit" +value "fad_main_tb" +) +(vvPair +variable "user" +value "Benjamin Krumm" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 52,0 +optionalChildren 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+crate_id <= \"01\"; + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 4000 +visibleWidth 10000 +) +) +) +] +shape (Rectangle +uid 431,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "50000,40000,58000,45000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 432,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*84 (Text +uid 433,0 +va (VaSet +font "Arial,8,1" +) +xt "51150,41000,57350,42000" +st "eb_mainTB_ID" +blo "51150,41800" +tm "HdlTextNameMgr" +) +*85 (Text +uid 434,0 +va (VaSet +font "Arial,8,1" +) +xt "51150,42000,51950,43000" +st "1" +blo "51150,42800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 435,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "50250,43250,51750,44750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*86 (Net +uid 440,0 +decl (Decl +n "board_id" +t "std_logic_vector" +b "(3 downto 0)" +preAdd 0 +posAdd 0 +o 10 +suid 10,0 +) +declText (MLText +uid 441,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,26000,30000,26800" +st "SIGNAL board_id : std_logic_vector(3 downto 0)" +) +) +*87 (Net +uid 448,0 +decl (Decl +n "crate_id" +t "std_logic_vector" +b "(1 downto 0)" +o 11 +suid 11,0 +) +declText (MLText +uid 449,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,27600,30000,28400" +st "SIGNAL crate_id : std_logic_vector(1 downto 0)" +) +) +*88 (SaComponent +uid 508,0 +optionalChildren [ +*89 (CptPort +uid 489,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 490,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "29250,52625,30000,53375" +) +tg (CPTG +uid 491,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 492,0 +va (VaSet +) +xt "31000,52500,32300,53500" +st "clk" +blo "31000,53300" +) +) +thePort (LogicalPort +decl (Decl +n "clk" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*90 (CptPort +uid 493,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 494,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40000,54625,40750,55375" +) +tg (CPTG +uid 495,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 496,0 +va (VaSet +) +xt "34200,54500,39000,55500" +st "data : (11:0)" +ju 2 +blo "39000,55300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "data" +t "STD_LOGIC_VECTOR" +b "(11 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +) +) +) +*91 (CptPort +uid 497,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 498,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40000,52625,40750,53375" +) +tg (CPTG +uid 499,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 500,0 +va (VaSet +) +xt "37700,52500,39000,53500" +st "otr" +ju 2 +blo "39000,53300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "otr" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +) +) +) +*92 (CptPort +uid 501,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 502,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40000,53625,40750,54375" +) +tg (CPTG +uid 503,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 504,0 +va (VaSet +) +xt "37400,53500,39000,54500" +st "oeb" +ju 2 +blo "39000,54300" +) +) +thePort (LogicalPort +decl (Decl +n "oeb" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 4 +suid 4,0 +) +) +) +] +shape (Rectangle +uid 509,0 +va (VaSet +vasetType 1 +fg "0,49152,49152" +lineColor "0,0,50000" +lineWidth 2 +) +xt "30000,51000,40000,58000" +) +oxt "29000,7000,39000,17000" +ttg (MlTextGroup +uid 510,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*93 (Text +uid 511,0 +va (VaSet +font "Arial,8,1" +) +xt "30200,58000,37900,59000" +st "FACT_FAD_TB_lib" +blo "30200,58800" +tm "BdLibraryNameMgr" +) +*94 (Text +uid 512,0 +va (VaSet +font "Arial,8,1" +) +xt "30200,59000,36000,60000" +st "adc_emulator" +blo "30200,59800" +tm "CptNameMgr" +) +*95 (Text +uid 513,0 +va (VaSet +font "Arial,8,1" +) +xt "30200,60000,36200,61000" +st "I_mainTB_adc" +blo "30200,60800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 514,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 515,0 +text (MLText +uid 516,0 +va (VaSet +font "Courier New,8,0" +) +xt "30000,50200,65500,51000" +st "INPUT_FILE = \"../memory_files/analog_input_ch0.txt\" ( string ) " +) +header "" +) +elements [ +(GiElement +name "INPUT_FILE" +type "string" +value "\"../memory_files/analog_input_ch0.txt\"" +) +] +) +viewicon (ZoomableIcon +uid 517,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "30250,56250,31750,57750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sIVOD 1 +) +archFileType "UNKNOWN" +) +*96 (HdlText +uid 518,0 +optionalChildren [ +*97 (EmbeddedText +uid 524,0 +commentText (CommentText +uid 525,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 526,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "50000,57000,62000,67000" +) +oxt "0,0,18000,5000" +text (MLText +uid 527,0 +va (VaSet +) +xt "50200,57200,62100,66200" +st " +-- eb_adc 2: ADC routing +adc_data_array(0) <= adc_data; +adc_data_array(1) <= adc_data; +adc_data_array(2) <= adc_data; +adc_data_array(3) <= adc_data; +adc_otr_array(0) <= adc_otr; +adc_otr_array(1) <= adc_otr; +adc_otr_array(2) <= adc_otr; +adc_otr_array(3) <= adc_otr; + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 10000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 519,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "50000,51000,58000,57000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 520,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*98 (Text +uid 521,0 +va (VaSet +font "Arial,8,1" +) +xt "51150,52000,57850,53000" +st "eb_mainTB_adc" +blo "51150,52800" +tm "HdlTextNameMgr" +) +*99 (Text +uid 522,0 +va (VaSet +font "Arial,8,1" +) +xt "51150,53000,51950,54000" +st "2" +blo "51150,53800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 523,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "50250,55250,51750,56750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*100 (Net +uid 528,0 +decl (Decl +n "adc_otr_array" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 12 +suid 12,0 +) +declText (MLText +uid 529,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,25200,30000,26000" +st "SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0)" +) +) +*101 (Net +uid 536,0 +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 13 +suid 13,0 +) +declText (MLText +uid 537,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22800,25500,23600" +st "SIGNAL adc_data_array : adc_data_array_type" +) +) +*102 (Net +uid 544,0 +decl (Decl +n "adc_oeb" +t "std_logic" +preAdd 0 +posAdd 0 +o 14 +suid 14,0 +) +declText (MLText +uid 545,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,23600,20000,24400" +st "SIGNAL adc_oeb : std_logic" +) +) +*103 (Net +uid 560,0 +decl (Decl +n "adc_otr" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 16 +suid 16,0 +) +declText (MLText +uid 561,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,24400,20000,25200" +st "SIGNAL adc_otr : STD_LOGIC" +) +) +*104 (Net +uid 568,0 +decl (Decl +n "adc_data" +t "std_logic_vector" +b "(11 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 17 +suid 17,0 +) +declText (MLText +uid 569,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22000,30500,22800" +st "SIGNAL adc_data : std_logic_vector(11 DOWNTO 0)" +) +) +*105 (Net +uid 767,0 +decl (Decl +n "wiz_reset" +t "std_logic" +o 21 +suid 23,0 +i "'1'" +) +declText (MLText +uid 768,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,40400,33500,41200" +st "SIGNAL wiz_reset : std_logic := '1'" +) +) +*106 (Net +uid 775,0 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 DOWNTO 0)" +posAdd 0 +o 22 +suid 24,0 +i "(OTHERS => '0')" +) +declText (MLText +uid 776,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,31600,39500,32400" +st "SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" +) +) +*107 (Net +uid 783,0 +decl (Decl +n "wiz_cs" +t "std_logic" +o 23 +suid 25,0 +i "'1'" +) +declText (MLText +uid 784,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,37200,33500,38000" +st "SIGNAL wiz_cs : std_logic := '1'" +) +) +*108 (Net +uid 791,0 +decl (Decl +n "wiz_int" +t "std_logic" +o 24 +suid 26,0 +) +declText (MLText +uid 792,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,38800,20000,39600" +st "SIGNAL wiz_int : std_logic" +) +) +*109 (Net +uid 799,0 +decl (Decl +n "dac_cs" +t "std_logic" +o 25 +suid 27,0 +) +declText (MLText +uid 800,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,28400,20000,29200" +st "SIGNAL dac_cs : std_logic" +) +) +*110 (Net +uid 807,0 +decl (Decl +n "mosi" +t "std_logic" +o 26 +suid 28,0 +i "'0'" +) +declText (MLText +uid 808,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,32400,33500,33200" +st "SIGNAL mosi : std_logic := '0'" +) +) +*111 (Net +uid 815,0 +decl (Decl +n "denable" +t "std_logic" +eolc "-- default domino wave off" +posAdd 0 +o 27 +suid 29,0 +i "'0'" +) +declText (MLText +uid 816,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,29200,47000,30000" +st "SIGNAL denable : std_logic := '0' -- default domino wave off" +) +) +*112 (Net +uid 823,0 +decl (Decl +n "CLK_25_PS" +t "std_logic" +o 28 +suid 30,0 +) +declText (MLText +uid 824,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,15600,20000,16400" +st "SIGNAL CLK_25_PS : std_logic" +) +) +*113 (Net +uid 831,0 +decl (Decl +n "CLK_50" +t "std_logic" +o 29 +suid 31,0 +) +declText (MLText +uid 832,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,16400,20000,17200" +st "SIGNAL CLK_50 : std_logic" +) +) +*114 (Net +uid 839,0 +decl (Decl +n "drs_channel_id" +t "std_logic_vector" +b "(3 downto 0)" +o 30 +suid 32,0 +i "(others => '0')" +) +declText (MLText +uid 840,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,30000,39500,30800" +st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" +) +) +*115 (Net +uid 847,0 +decl (Decl +n "drs_dwrite" +t "std_logic" +o 31 +suid 33,0 +i "'1'" +) +declText (MLText +uid 848,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,30800,33500,31600" +st "SIGNAL drs_dwrite : std_logic := '1'" +) +) +*116 (Net +uid 855,0 +decl (Decl +n "RSRLOAD" +t "std_logic" +o 32 +suid 34,0 +i "'0'" +) +declText (MLText +uid 856,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,17200,33500,18000" +st "SIGNAL RSRLOAD : std_logic := '0'" +) +) +*117 (Net +uid 863,0 +decl (Decl +n "SRCLK" +t "std_logic" +o 33 +suid 35,0 +i "'0'" +) +declText (MLText +uid 864,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,18000,33500,18800" +st "SIGNAL SRCLK : std_logic := '0'" +) +) +*118 (Net +uid 871,0 +decl (Decl +n "SROUT_in_0" +t "std_logic" +o 30 +suid 36,0 +) +declText (MLText +uid 872,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,18800,20000,19600" +st "SIGNAL SROUT_in_0 : std_logic" +) +) +*119 (Net +uid 879,0 +decl (Decl +n "SROUT_in_1" +t "std_logic" +o 31 +suid 37,0 +) +declText (MLText +uid 880,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,19600,20000,20400" +st "SIGNAL SROUT_in_1 : std_logic" +) +) +*120 (Net +uid 887,0 +decl (Decl +n "SROUT_in_2" +t "std_logic" +o 32 +suid 38,0 +) +declText (MLText +uid 888,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,20400,20000,21200" +st "SIGNAL SROUT_in_2 : std_logic" +) +) +*121 (Net +uid 895,0 +decl (Decl +n "SROUT_in_3" +t "std_logic" +o 33 +suid 39,0 +) +declText (MLText +uid 896,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,21200,20000,22000" +st "SIGNAL SROUT_in_3 : std_logic" +) +) +*122 (Wire +uid 286,0 +shape (OrthoPolyLine +uid 287,0 +va (VaSet +vasetType 3 +) +xt "58750,21000,80250,21000" +pts [ +"58750,21000" +"80250,21000" +] +) +start &48 +end &27 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 288,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 289,0 +va (VaSet +) +xt "71000,20000,72300,21000" +st "clk" +blo "71000,20800" +tm "WireNameMgr" +) +) +on &53 +) +*123 (Wire +uid 318,0 +shape (OrthoPolyLine +uid 319,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "109750,21000,122250,21000" +pts [ +"109750,21000" +"122250,21000" +] +) +start &19 +end &55 +sat 32 +eat 32 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 320,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 321,0 +va (VaSet +) +xt "111000,20000,117000,21000" +st "wiz_addr : (9:0)" +blo "111000,20800" +tm "WireNameMgr" +) +) +on &62 +) +*124 (Wire +uid 324,0 +shape (OrthoPolyLine +uid 325,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "109750,22000,122250,22000" +pts [ +"109750,22000" +"122250,22000" +] +) +start &20 +end &56 +sat 32 +eat 32 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 326,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 327,0 +va (VaSet +) +xt "111000,21000,117300,22000" +st "wiz_data : (15:0)" +blo "111000,21800" +tm "WireNameMgr" +) +) +on &63 +) +*125 (Wire +uid 330,0 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+"120000,48000" +"122250,48000" +] +) +start &41 +end &69 +sat 32 +eat 32 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 376,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 377,0 +va (VaSet +) +xt "111000,41000,117500,42000" +st "sensor_cs : (3:0)" +blo "111000,41800" +tm "WireNameMgr" +) +) +on &73 +) +*128 (Wire +uid 380,0 +shape (OrthoPolyLine +uid 381,0 +va (VaSet +vasetType 3 +) +xt "109750,51000,122250,51000" +pts [ +"109750,51000" +"122250,51000" +] +) +start &38 +end &67 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 382,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 383,0 +va (VaSet +) +xt "111000,50000,112700,51000" +st "sclk" +blo "111000,50800" +tm "WireNameMgr" +) +) +on &74 +) +*129 (Wire +uid 386,0 +shape (OrthoPolyLine +uid 387,0 +va (VaSet +vasetType 3 +) +xt "109750,52000,122250,52000" +pts [ +"109750,52000" +"122250,52000" +] +) +start &39 +end &68 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 388,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 389,0 +va (VaSet +) +xt "111000,51000,112400,52000" +st "sio" +blo "111000,51800" +tm "WireNameMgr" +) +) +on &75 +) +*130 (Wire +uid 426,0 +shape (OrthoPolyLine +uid 427,0 +va (VaSet +vasetType 3 +) +xt "58750,32000,80250,32000" +pts [ +"58750,32000" +"80250,32000" +] +) +start &77 +end &15 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 428,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 429,0 +va (VaSet +) +xt "71000,31000,73800,32000" +st "trigger" +blo "71000,31800" +tm "WireNameMgr" +) +) +on &81 +) +*131 (Wire +uid 442,0 +shape (OrthoPolyLine +uid 443,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "58000,34000,80250,42000" +pts [ +"80250,34000" +"64000,34000" +"64000,42000" +"58000,42000" +] +) +start &17 +end &82 +sat 32 +eat 2 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 446,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 447,0 +va (VaSet +) +xt "71000,33000,76900,34000" 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=================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/fad_main_tb/symbol.sb (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/fad_main_tb/symbol.sb (revision 9841) @@ -0,0 +1,1174 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +] +libraryRefs [ +"ieee" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +usingSuid 1 +emptyRow *1 (LEmptyRow +) +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr 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/firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/max6662_emulator/symbol.sb (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/max6662_emulator/symbol.sb (revision 9841) @@ -0,0 +1,1443 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "ieee" +unitName "std_logic_unsigned" +) +(DmPackageRef +library "FACT_FAD_lib" +unitName "fad_definitions" +) +] +libraryRefs [ +"ieee" +"FACT_FAD_lib" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 3,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm 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+value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\max6662_emulator\\symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\max6662_emulator\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\max6662_emulator" +) +(vvPair +variable "d_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\max6662_emulator" +) +(vvPair +variable "date" +value "23.06.2010" +) +(vvPair +variable "day" +value "Mi" +) +(vvPair +variable "day_long" +value "Mittwoch" +) +(vvPair +variable "dd" +value "23" +) +(vvPair +variable "entity_name" +value "max6662_emulator" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "EEPC8" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_TB_lib" +) +(vvPair +variable "mm" +value "06" +) +(vvPair +variable "module_name" +value "max6662_emulator" +) +(vvPair +variable "month" +value "Jun" +) +(vvPair +variable "month_long" +value "Juni" +) +(vvPair +variable "p" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\max6662_emulator\\symbol.sb" +) +(vvPair +variable "p_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\max6662_emulator\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$HDS_HOME/../Modeltech/win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "$HDS_HOME/../Precision/Mgc_home/bin" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "10:43:22" +) +(vvPair +variable "unit" +value "max6662_emulator" +) +(vvPair +variable "user" +value "Benjamin Krumm" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +optionalChildren [ +*59 (SymbolBody +uid 8,0 +optionalChildren [ +*60 (CptPort +uid 48,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 49,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "29250,4625,30000,5375" +) +tg (CPTG +uid 50,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 51,0 +va (VaSet +) +xt "31000,4500,32700,5500" +st "sclk" +blo "31000,5300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 52,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,11000,19000,11800" +st "sclk : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "sclk" +t "std_logic" +preAdd 0 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"19000,18000,60000,23000" +) +oxt "14000,66000,55000,71000" +) +*71 (CommentText +uid 57,0 +shape (Rectangle +uid 58,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,-6000,33000,0" +) +text (MLText +uid 59,0 +va (VaSet +fg "0,0,32768" +font "Arial,10,0" +) +xt "200,-5800,32200,-600" +st " +Created using Mentor Graphics HDL2Graphics(TM) Technology +on - 10:50:06 23.06.2010 +from - D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hdl\\trigger__generator_beha.vhd + +" +tm "CommentText" +wrapOption 3 +visibleHeight 5600 +visibleWidth 32600 +) +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *72 (PackageList +uid 62,0 +stg "VerticalLayoutStrategy" +textVec [ +*73 (Text +uid 63,0 +va (VaSet +font "Arial,8,1" +) +xt "0,1000,5400,2000" +st "Package List" +blo "0,1800" +) +*74 (MLText +uid 64,0 +va (VaSet +) +xt "0,2000,14100,10000" +st "LIBRARY ieee; +USE ieee.std_logic_1164.all; +--USE ieee.NUMERIC_STD.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library FACT_FAD_lib; +use FACT_FAD_lib.fad_definitions.all;" +tm "PackageList" +) +] +) +windowSize "0,0,1015,690" +viewArea "0,0,0,0" +cachedDiagramExtent "0,0,0,0" +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *75 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *76 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "0,11000,5400,12000" +st "Declarations" +blo "0,11800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "0,12000,2700,13000" +st "Ports:" +blo "0,12800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "0,13800,2400,14800" +st "User:" +blo "0,14600" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "0,11000,5800,12000" +st "Internal User:" +blo "0,11800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,14800,2000,14800" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,11000,0,11000" +tm "SyDeclarativeTextMgr" +) +) +lastUid 125,0 +activeModelName "Symbol:CDM" +) Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/w5300_emulator/symbol.sb =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/w5300_emulator/symbol.sb (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/hds/w5300_emulator/symbol.sb (revision 9841) @@ -0,0 +1,1515 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "ieee" +unitName "std_logic_unsigned" +) +(DmPackageRef +library "FACT_FAD_lib" +unitName "fad_definitions" +) +] +libraryRefs [ +"ieee" +"FACT_FAD_lib" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 4,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 84,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) 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"39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *19 (MRCItem +litem &1 +pos 3 +dimension 20 +) +uid 99,0 +optionalChildren [ +*20 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 100,0 +) +*21 (MRCItem +litem &3 +pos 1 +dimension 23 +uid 101,0 +) +*22 (MRCItem +litem &4 +pos 2 +hidden 1 +dimension 20 +uid 102,0 +) +*23 (MRCItem +litem &14 +pos 0 +dimension 20 +uid 72,0 +) +*24 (MRCItem +litem &15 +pos 1 +dimension 20 +uid 74,0 +) +*25 (MRCItem +litem &16 +pos 2 +dimension 20 +uid 76,0 +) +*26 (MRCItem +litem &17 +pos 3 +dimension 20 +uid 78,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 103,0 +optionalChildren [ +*27 (MRCItem +litem &5 +pos 0 +dimension 20 +uid 104,0 +) +*28 (MRCItem +litem &7 +pos 1 +dimension 50 +uid 105,0 +) +*29 (MRCItem +litem &8 +pos 2 +dimension 100 +uid 106,0 +) +*30 (MRCItem +litem &9 +pos 3 +dimension 50 +uid 107,0 +) +*31 (MRCItem +litem &10 +pos 4 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+cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *48 (MRCItem +litem &35 +pos 3 +dimension 20 +) +uid 127,0 +optionalChildren [ +*49 (MRCItem +litem &36 +pos 0 +dimension 20 +uid 128,0 +) +*50 (MRCItem +litem &37 +pos 1 +dimension 23 +uid 129,0 +) +*51 (MRCItem +litem &38 +pos 2 +hidden 1 +dimension 20 +uid 130,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 131,0 +optionalChildren [ +*52 (MRCItem +litem &39 +pos 0 +dimension 20 +uid 132,0 +) +*53 (MRCItem +litem &41 +pos 1 +dimension 50 +uid 133,0 +) +*54 (MRCItem +litem &42 +pos 2 +dimension 100 +uid 134,0 +) +*55 (MRCItem +litem &43 +pos 3 +dimension 100 +uid 135,0 +) +*56 (MRCItem +litem &44 +pos 4 +dimension 50 +uid 136,0 +) +*57 (MRCItem +litem &45 +pos 5 +dimension 50 +uid 137,0 +) +*58 (MRCItem +litem &46 +pos 6 +dimension 80 +uid 138,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 126,0 +vaOverrides [ +] +) +] +) +uid 112,0 +type 1 +) +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\w5300_emulator\\symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\w5300_emulator\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\w5300_emulator" +) +(vvPair +variable "d_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\w5300_emulator" +) +(vvPair +variable "date" +value "23.06.2010" +) +(vvPair +variable "day" +value "Mi" +) +(vvPair +variable "day_long" +value "Mittwoch" +) +(vvPair +variable "dd" +value "23" +) +(vvPair +variable "entity_name" +value "w5300_emulator" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "EEPC8" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_TB_lib" +) +(vvPair +variable "mm" +value "06" +) +(vvPair +variable "module_name" +value "w5300_emulator" +) +(vvPair +variable "month" +value "Jun" +) +(vvPair +variable "month_long" +value "Juni" +) +(vvPair +variable "p" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\w5300_emulator\\symbol.sb" +) +(vvPair +variable "p_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\w5300_emulator\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$HDS_HOME/../Modeltech/win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "$HDS_HOME/../Precision/Mgc_home/bin" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "10:45:51" +) +(vvPair +variable "unit" +value "w5300_emulator" +) +(vvPair +variable "user" +value "Benjamin Krumm" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 82,0 +optionalChildren [ +*59 (SymbolBody +uid 8,0 +optionalChildren [ +*60 (CptPort +uid 48,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 49,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "28250,1625,29000,2375" +) +tg (CPTG +uid 50,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 51,0 +va (VaSet +) +xt "30000,1500,34500,2500" +st "addr : (9:0)" +blo "30000,2300" +tm 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1 +fg "65280,65280,46080" +) +xt "29000,19000,33000,20000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "29200,19000,31300,20000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*74 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "29000,20000,33000,21000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "29200,20000,31900,21000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*75 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "33000,19000,50000,20000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "33200,19000,49200,20000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "29000,16000,70000,21000" +) +oxt "14000,66000,55000,71000" +) +*76 (CommentText +uid 68,0 +shape (Rectangle +uid 69,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,-6000,33000,0" +) +text (MLText +uid 70,0 +va (VaSet +fg "0,0,32768" +font "Arial,10,0" +) +xt "200,-5800,32300,-600" +st " +Created using Mentor Graphics HDL2Graphics(TM) Technology +on - 10:43:29 23.06.2010 +from - D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hdl\\w5300_emulator_beha.vhd + +" +tm "CommentText" +wrapOption 3 +visibleHeight 5600 +visibleWidth 32600 +) +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *77 (PackageList +uid 79,0 +stg "VerticalLayoutStrategy" +textVec [ +*78 (Text +uid 80,0 +va (VaSet +font "Arial,8,1" +) +xt "0,1000,5400,2000" +st "Package List" +blo "0,1800" +) +*79 (MLText +uid 81,0 +va (VaSet +) +xt "0,2000,14500,8000" +st "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all;" +tm "PackageList" +) +] +) +windowSize "0,0,1015,690" +viewArea "0,0,0,0" +cachedDiagramExtent "0,0,0,0" +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *80 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *81 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "0,9000,5400,10000" +st "Declarations" +blo "0,9800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "0,10000,2700,11000" +st "Ports:" +blo "0,10800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "0,14200,2400,15200" +st "User:" +blo "0,15000" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "0,9000,5800,10000" +st "Internal User:" +blo "0,9800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,15200,2000,15200" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,9000,0,9000" +tm "SyDeclarativeTextMgr" +) +) +lastUid 138,0 +activeModelName "Symbol:CDM" +) Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/memory_files/analog_input_ch0.txt =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/memory_files/analog_input_ch0.txt (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/memory_files/analog_input_ch0.txt (revision 9841) @@ -0,0 +1,1024 @@ +11ac -- 0 +0816 -- 1 +0629 -- 2 +0113 -- 3 +169c -- 4 +0b71 -- 5 +035e -- 6 +15d6 -- 7 +1929 -- 8 +14f6 -- 9 +122d -- 10 +09c5 +0fd6 +076b +0451 +1809 +1059 +1730 +0c14 +1be4 +0ffc -- 20 +131f +18e6 +10aa +1447 +1a73 +095d +1a12 +1a02 +0259 +0025 -- 30 +0221 +1fbc +0515 +17ba +1541 +0fe5 +1895 +0132 +1eac +058a -- 40 +1d7f +0cd3 +054f +16f0 +05d3 +0d35 +1f00 +030d +137c +1727 -- 50 +02dd +0020 +05c7 +051e +1e8c +0f30 +157e +0ccb +1c29 +0213 -- 60 +094c +1bd4 +16cf +14d1 +100b +0a08 +0ac1 +0fb0 +0f10 +0824 -- 70 +17c3 +15fe +0d68 +1659 +127d +064c +1397 +19ba +0e74 +0d3e -- 80 +0a5c +1704 +0686 +0b32 +1d47 +0201 +19f5 +1ff6 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/firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/memory_files/analog_input_ch3.txt (revision 9841) @@ -0,0 +1,1024 @@ +06f2 +06dc +0431 +048e +0c17 +1ac5 +0ddf +1b8e +0245 +1730 +104d +11ce +0634 +0e9a +059f +14ac +1ede +19d4 +0733 +1cdd +16a3 +08c8 +183e +0e2a +13bc +16eb +0a9b +1f77 +0286 +0879 +19de +110c +0587 +1beb +0830 +1245 +1f64 +0fc0 +1c64 +0a76 +1729 +0a6f +1103 +09a3 +10e0 +072f +0dd2 +04be +1059 +085f +0116 +0097 +0d32 +053e +0295 +1e29 +0e9e +1607 +10d2 +152c +1029 +0e67 +1908 +19cc +1d51 +1f41 +0c47 +0a49 +066a +1359 +1547 +0f1d +1d70 +1cbd +05b3 +0c33 +17c4 +0e9a +1d49 +0c8d +0918 +05dd +0f1e +1a26 +0762 +1947 +03d9 +0048 +1955 +0a06 +03a6 +095d +1eee +0738 +1a4d +08c2 +1167 +1737 +0c52 +119f +1ae7 +0389 +1e54 +1cff +1318 +11f9 +0327 +1075 +1f8a +1662 +0664 +0003 +18bd +0444 +0c13 +0a4c +1f48 +1ee1 +1269 +040a +1b68 +0bff +10f4 +1c64 +0fb3 +0bea +102f +1637 +026f +1cf1 +1acc +008d +0248 +0ba9 +11a5 +058f +0788 +121f +070e +1569 +1620 +1363 +00bd +02f3 +03a1 +03a3 +109f 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+2dc +399 +388 +0db +389 +3c4 +02e +29e +083 +306 +05f +35b +117 +3b0 +27f +037 +356 +359 +364 +11a +135 +251 +041 +0d5 +155 +3ee +1c6 +27a +194 +288 +2b3 +37f +3c8 +39e +273 +136 +2ca +15f +357 +3d4 +20f +1e5 +0fe +113 +3b9 +1b7 +314 +100 +2e6 +1b0 +230 +026 +2a2 +0f8 +28c +08b +357 +2b3 +385 +39a +1fe +1b3 +10a +1fb +053 +0df +393 +179 +13d +149 +16c +1f6 +001 +38f +30b +34f +152 +32d +11b +39d +0d9 +0c5 +393 +3e3 +057 +28d +0dc +2cf +111 +1e8 +1de +017 +1da +3bc +1d6 +05c +0db +303 +0c0 +2da +224 +19b +3c3 +19d +044 +03a +024 +313 +1ed +33d +338 +02a +197 +3e7 +2c1 +139 +21f +126 +1a3 +1c5 +002 +0c3 +067 +355 +36a +155 +01c +044 +1b8 +2af +273 +24f +26d +241 +179 +33e +101 +1f6 +39f +01d +268 +1c9 +0e2 +1d4 +2af +1b4 +280 +1f2 +0fb +09d +23c +3b5 +15f +2fa +2d7 +160 +134 +06e +233 +2ee +01e +3df +15a +33e +0c9 +0e8 +1bc +355 +26e +382 +037 +029 +186 +186 +35c +238 +3e1 +292 +0a5 +1b6 +2d5 +229 +348 +11b +072 +2bd +0ef +373 +36a +018 +20a +093 +3c2 +0b0 +3ff +288 +06f +1a3 +10a +1c7 +3f8 +32a +384 +179 +065 +212 +22e +3d9 +39d +09e +17f +2a1 +3c8 +07c +019 +1f4 +097 +03e +2cb +20c +3f8 +248 +3eb +255 +178 +3a4 +066 +0d6 +187 +0d4 +1c9 +23d +188 +2de +1be +3aa +2a4 +1cf +0b5 +25f +08e +116 +3d5 +2cc +299 +369 +0ca +346 +096 +20a +1f1 +031 +2d8 +2fe +1ce +1af +33f +12f +000 +0c1 +1ac +158 +252 +2c9 +2d5 +341 +118 +0ea +2be +06f +350 +2c7 +389 +06b +17d +2e2 +272 +11e +3bb +20f +2d9 +120 +03f +37c +2e2 +198 +365 +28a +110 +00e +06b +175 +1ce +3f3 +0b3 +335 +2c4 +10c +3f7 +357 +250 +3e0 +087 +027 +2ba +329 +0a8 +26c +180 +2ec +33c +220 +173 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/memory_files/simple_counter.txt =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/memory_files/simple_counter.txt (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/memory_files/simple_counter.txt (revision 9841) @@ -0,0 +1,1024 @@ +0000 -- 0 +0001 -- 1 +0002 -- 2 +0003 -- 3 +0004 -- 4 +0005 -- 5 +0006 -- 6 +0007 -- 7 +0008 -- 8 +0009 -- 9 +000a -- 10 +000b -- 11 +000c -- 12 +000d -- 13 +000e -- 14 +000f -- 15 +0010 -- 16 +0011 -- 17 +0012 -- 18 +0013 -- 19 +0014 -- 20 +0015 -- 21 +0016 -- 22 +0017 -- 23 +0018 -- 24 +0019 -- 25 +001a -- 26 +001b -- 27 +001c -- 28 +001d -- 29 +001e -- 30 +001f -- 31 +0020 -- 32 +0021 -- 33 +0022 -- 34 +0023 -- 35 +0024 -- 36 +0025 -- 37 +0026 -- 38 +0027 -- 39 +0028 -- 40 +0029 -- 41 +002a -- 42 +002b -- 43 +002c -- 44 +002d -- 45 +002e -- 46 +002f -- 47 +0030 -- 48 +0031 -- 49 +0032 -- 50 +0033 -- 51 +0034 -- 52 +0035 -- 53 +0036 -- 54 +0037 -- 55 +0038 -- 56 +0039 -- 57 +003a -- 58 +003b -- 59 +003c -- 60 +003d -- 61 +003e -- 62 +003f -- 63 +0040 -- 64 +0041 -- 65 +0042 -- 66 +0043 -- 67 +0044 -- 68 +0045 -- 69 +0046 -- 70 +0047 -- 71 +0048 -- 72 +0049 -- 73 +004a -- 74 +004b -- 75 +004c -- 76 +004d -- 77 +004e -- 78 +004f -- 79 +0050 -- 80 +0051 -- 81 +0052 -- 82 +0053 -- 83 +0054 -- 84 +0055 -- 85 +0056 -- 86 +0057 -- 87 +0058 -- 88 +0059 -- 89 +005a -- 90 +005b -- 91 +005c -- 92 +005d -- 93 +005e -- 94 +005f -- 95 +0060 -- 96 +0061 -- 97 +0062 -- 98 +0063 -- 99 +0064 -- 100 +0065 -- 101 +0066 -- 102 +0067 -- 103 +0068 -- 104 +0069 -- 105 +006a -- 106 +006b -- 107 +006c -- 108 +006d -- 109 +006e -- 110 +006f -- 111 +0070 -- 112 +0071 -- 113 +0072 -- 114 +0073 -- 115 +0074 -- 116 +0075 -- 117 +0076 -- 118 +0077 -- 119 +0078 -- 120 +0079 -- 121 +007a -- 122 +007b -- 123 +007c -- 124 +007d -- 125 +007e -- 126 +007f -- 127 +0080 -- 128 +0081 -- 129 +0082 -- 130 +0083 -- 131 +0084 -- 132 +0085 -- 133 +0086 -- 134 +0087 -- 135 +0088 -- 136 +0089 -- 137 +008a -- 138 +008b -- 139 +008c -- 140 +008d -- 141 +008e -- 142 +008f -- 143 +0090 -- 144 +0091 -- 145 +0092 -- 146 +0093 -- 147 +0094 -- 148 +0095 -- 149 +0096 -- 150 +0097 -- 151 +0098 -- 152 +0099 -- 153 +009a -- 154 +009b -- 155 +009c -- 156 +009d -- 157 +009e -- 158 +009f -- 159 +00a0 -- 160 +00a1 -- 161 +00a2 -- 162 +00a3 -- 163 +00a4 -- 164 +00a5 -- 165 +00a6 -- 166 +00a7 -- 167 +00a8 -- 168 +00a9 -- 169 +00aa -- 170 +00ab -- 171 +00ac -- 172 +00ad -- 173 +00ae -- 174 +00af -- 175 +00b0 -- 176 +00b1 -- 177 +00b2 -- 178 +00b3 -- 179 +00b4 -- 180 +00b5 -- 181 +00b6 -- 182 +00b7 -- 183 +00b8 -- 184 +00b9 -- 185 +00ba -- 186 +00bb -- 187 +00bc -- 188 +00bd -- 189 +00be -- 190 +00bf -- 191 +00c0 -- 192 +00c1 -- 193 +00c2 -- 194 +00c3 -- 195 +00c4 -- 196 +00c5 -- 197 +00c6 -- 198 +00c7 -- 199 +00c8 -- 200 +00c9 -- 201 +00ca -- 202 +00cb -- 203 +00cc -- 204 +00cd -- 205 +00ce -- 206 +00cf -- 207 +00d0 -- 208 +00d1 -- 209 +00d2 -- 210 +00d3 -- 211 +00d4 -- 212 +00d5 -- 213 +00d6 -- 214 +00d7 -- 215 +00d8 -- 216 +00d9 -- 217 +00da -- 218 +00db -- 219 +00dc -- 220 +00dd -- 221 +00de -- 222 +00df -- 223 +00e0 -- 224 +00e1 -- 225 +00e2 -- 226 +00e3 -- 227 +00e4 -- 228 +00e5 -- 229 +00e6 -- 230 +00e7 -- 231 +00e8 -- 232 +00e9 -- 233 +00ea -- 234 +00eb -- 235 +00ec -- 236 +00ed -- 237 +00ee -- 238 +00ef -- 239 +00f0 -- 240 +00f1 -- 241 +00f2 -- 242 +00f3 -- 243 +00f4 -- 244 +00f5 -- 245 +00f6 -- 246 +00f7 -- 247 +00f8 -- 248 +00f9 -- 249 +00fa -- 250 +00fb -- 251 +00fc -- 252 +00fd -- 253 +00fe -- 254 +00ff -- 255 +0100 -- 256 +0101 -- 257 +0102 -- 258 +0103 -- 259 +0104 -- 260 +0105 -- 261 +0106 -- 262 +0107 -- 263 +0108 -- 264 +0109 -- 265 +010a -- 266 +010b -- 267 +010c -- 268 +010d -- 269 +010e -- 270 +010f -- 271 +0110 -- 272 +0111 -- 273 +0112 -- 274 +0113 -- 275 +0114 -- 276 +0115 -- 277 +0116 -- 278 +0117 -- 279 +0118 -- 280 +0119 -- 281 +011a -- 282 +011b -- 283 +011c -- 284 +011d -- 285 +011e -- 286 +011f -- 287 +0120 -- 288 +0121 -- 289 +0122 -- 290 +0123 -- 291 +0124 -- 292 +0125 -- 293 +0126 -- 294 +0127 -- 295 +0128 -- 296 +0129 -- 297 +012a -- 298 +012b -- 299 +012c -- 300 +012d -- 301 +012e -- 302 +012f -- 303 +0130 -- 304 +0131 -- 305 +0132 -- 306 +0133 -- 307 +0134 -- 308 +0135 -- 309 +0136 -- 310 +0137 -- 311 +0138 -- 312 +0139 -- 313 +013a -- 314 +013b -- 315 +013c -- 316 +013d -- 317 +013e -- 318 +013f -- 319 +0140 -- 320 +0141 -- 321 +0142 -- 322 +0143 -- 323 +0144 -- 324 +0145 -- 325 +0146 -- 326 +0147 -- 327 +0148 -- 328 +0149 -- 329 +014a -- 330 +014b -- 331 +014c -- 332 +014d -- 333 +014e -- 334 +014f -- 335 +0150 -- 336 +0151 -- 337 +0152 -- 338 +0153 -- 339 +0154 -- 340 +0155 -- 341 +0156 -- 342 +0157 -- 343 +0158 -- 344 +0159 -- 345 +015a -- 346 +015b -- 347 +015c -- 348 +015d -- 349 +015e -- 350 +015f -- 351 +0160 -- 352 +0161 -- 353 +0162 -- 354 +0163 -- 355 +0164 -- 356 +0165 -- 357 +0166 -- 358 +0167 -- 359 +0168 -- 360 +0169 -- 361 +016a -- 362 +016b -- 363 +016c -- 364 +016d -- 365 +016e -- 366 +016f -- 367 +0170 -- 368 +0171 -- 369 +0172 -- 370 +0173 -- 371 +0174 -- 372 +0175 -- 373 +0176 -- 374 +0177 -- 375 +0178 -- 376 +0179 -- 377 +017a -- 378 +017b -- 379 +017c -- 380 +017d -- 381 +017e -- 382 +017f -- 383 +0180 -- 384 +0181 -- 385 +0182 -- 386 +0183 -- 387 +0184 -- 388 +0185 -- 389 +0186 -- 390 +0187 -- 391 +0188 -- 392 +0189 -- 393 +018a -- 394 +018b -- 395 +018c -- 396 +018d -- 397 +018e -- 398 +018f -- 399 +0190 -- 400 +0191 -- 401 +0192 -- 402 +0193 -- 403 +0194 -- 404 +0195 -- 405 +0196 -- 406 +0197 -- 407 +0198 -- 408 +0199 -- 409 +019a -- 410 +019b -- 411 +019c -- 412 +019d -- 413 +019e -- 414 +019f -- 415 +01a0 -- 416 +01a1 -- 417 +01a2 -- 418 +01a3 -- 419 +01a4 -- 420 +01a5 -- 421 +01a6 -- 422 +01a7 -- 423 +01a8 -- 424 +01a9 -- 425 +01aa -- 426 +01ab -- 427 +01ac -- 428 +01ad -- 429 +01ae -- 430 +01af -- 431 +01b0 -- 432 +01b1 -- 433 +01b2 -- 434 +01b3 -- 435 +01b4 -- 436 +01b5 -- 437 +01b6 -- 438 +01b7 -- 439 +01b8 -- 440 +01b9 -- 441 +01ba -- 442 +01bb -- 443 +01bc -- 444 +01bd -- 445 +01be -- 446 +01bf -- 447 +01c0 -- 448 +01c1 -- 449 +01c2 -- 450 +01c3 -- 451 +01c4 -- 452 +01c5 -- 453 +01c6 -- 454 +01c7 -- 455 +01c8 -- 456 +01c9 -- 457 +01ca -- 458 +01cb -- 459 +01cc -- 460 +01cd -- 461 +01ce -- 462 +01cf -- 463 +01d0 -- 464 +01d1 -- 465 +01d2 -- 466 +01d3 -- 467 +01d4 -- 468 +01d5 -- 469 +01d6 -- 470 +01d7 -- 471 +01d8 -- 472 +01d9 -- 473 +01da -- 474 +01db -- 475 +01dc -- 476 +01dd -- 477 +01de -- 478 +01df -- 479 +01e0 -- 480 +01e1 -- 481 +01e2 -- 482 +01e3 -- 483 +01e4 -- 484 +01e5 -- 485 +01e6 -- 486 +01e7 -- 487 +01e8 -- 488 +01e9 -- 489 +01ea -- 490 +01eb -- 491 +01ec -- 492 +01ed -- 493 +01ee -- 494 +01ef -- 495 +01f0 -- 496 +01f1 -- 497 +01f2 -- 498 +01f3 -- 499 +01f4 -- 500 +01f5 -- 501 +01f6 -- 502 +01f7 -- 503 +01f8 -- 504 +01f9 -- 505 +01fa -- 506 +01fb -- 507 +01fc -- 508 +01fd -- 509 +01fe -- 510 +01ff -- 511 +0200 -- 512 +0201 -- 513 +0202 -- 514 +0203 -- 515 +0204 -- 516 +0205 -- 517 +0206 -- 518 +0207 -- 519 +0208 -- 520 +0209 -- 521 +020a -- 522 +020b -- 523 +020c -- 524 +020d -- 525 +020e -- 526 +020f -- 527 +0210 -- 528 +0211 -- 529 +0212 -- 530 +0213 -- 531 +0214 -- 532 +0215 -- 533 +0216 -- 534 +0217 -- 535 +0218 -- 536 +0219 -- 537 +021a -- 538 +021b -- 539 +021c -- 540 +021d -- 541 +021e -- 542 +021f -- 543 +0220 -- 544 +0221 -- 545 +0222 -- 546 +0223 -- 547 +0224 -- 548 +0225 -- 549 +0226 -- 550 +0227 -- 551 +0228 -- 552 +0229 -- 553 +022a -- 554 +022b -- 555 +022c -- 556 +022d -- 557 +022e -- 558 +022f -- 559 +0230 -- 560 +0231 -- 561 +0232 -- 562 +0233 -- 563 +0234 -- 564 +0235 -- 565 +0236 -- 566 +0237 -- 567 +0238 -- 568 +0239 -- 569 +023a -- 570 +023b -- 571 +023c -- 572 +023d -- 573 +023e -- 574 +023f -- 575 +0240 -- 576 +0241 -- 577 +0242 -- 578 +0243 -- 579 +0244 -- 580 +0245 -- 581 +0246 -- 582 +0247 -- 583 +0248 -- 584 +0249 -- 585 +024a -- 586 +024b -- 587 +024c -- 588 +024d -- 589 +024e -- 590 +024f -- 591 +0250 -- 592 +0251 -- 593 +0252 -- 594 +0253 -- 595 +0254 -- 596 +0255 -- 597 +0256 -- 598 +0257 -- 599 +0258 -- 600 +0259 -- 601 +025a -- 602 +025b -- 603 +025c -- 604 +025d -- 605 +025e -- 606 +025f -- 607 +0260 -- 608 +0261 -- 609 +0262 -- 610 +0263 -- 611 +0264 -- 612 +0265 -- 613 +0266 -- 614 +0267 -- 615 +0268 -- 616 +0269 -- 617 +026a -- 618 +026b -- 619 +026c -- 620 +026d -- 621 +026e -- 622 +026f -- 623 +0270 -- 624 +0271 -- 625 +0272 -- 626 +0273 -- 627 +0274 -- 628 +0275 -- 629 +0276 -- 630 +0277 -- 631 +0278 -- 632 +0279 -- 633 +027a -- 634 +027b -- 635 +027c -- 636 +027d -- 637 +027e -- 638 +027f -- 639 +0280 -- 640 +0281 -- 641 +0282 -- 642 +0283 -- 643 +0284 -- 644 +0285 -- 645 +0286 -- 646 +0287 -- 647 +0288 -- 648 +0289 -- 649 +028a -- 650 +028b -- 651 +028c -- 652 +028d -- 653 +028e -- 654 +028f -- 655 +0290 -- 656 +0291 -- 657 +0292 -- 658 +0293 -- 659 +0294 -- 660 +0295 -- 661 +0296 -- 662 +0297 -- 663 +0298 -- 664 +0299 -- 665 +029a -- 666 +029b -- 667 +029c -- 668 +029d -- 669 +029e -- 670 +029f -- 671 +02a0 -- 672 +02a1 -- 673 +02a2 -- 674 +02a3 -- 675 +02a4 -- 676 +02a5 -- 677 +02a6 -- 678 +02a7 -- 679 +02a8 -- 680 +02a9 -- 681 +02aa -- 682 +02ab -- 683 +02ac -- 684 +02ad -- 685 +02ae -- 686 +02af -- 687 +02b0 -- 688 +02b1 -- 689 +02b2 -- 690 +02b3 -- 691 +02b4 -- 692 +02b5 -- 693 +02b6 -- 694 +02b7 -- 695 +02b8 -- 696 +02b9 -- 697 +02ba -- 698 +02bb -- 699 +02bc -- 700 +02bd -- 701 +02be -- 702 +02bf -- 703 +02c0 -- 704 +02c1 -- 705 +02c2 -- 706 +02c3 -- 707 +02c4 -- 708 +02c5 -- 709 +02c6 -- 710 +02c7 -- 711 +02c8 -- 712 +02c9 -- 713 +02ca -- 714 +02cb -- 715 +02cc -- 716 +02cd -- 717 +02ce -- 718 +02cf -- 719 +02d0 -- 720 +02d1 -- 721 +02d2 -- 722 +02d3 -- 723 +02d4 -- 724 +02d5 -- 725 +02d6 -- 726 +02d7 -- 727 +02d8 -- 728 +02d9 -- 729 +02da -- 730 +02db -- 731 +02dc -- 732 +02dd -- 733 +02de -- 734 +02df -- 735 +02e0 -- 736 +02e1 -- 737 +02e2 -- 738 +02e3 -- 739 +02e4 -- 740 +02e5 -- 741 +02e6 -- 742 +02e7 -- 743 +02e8 -- 744 +02e9 -- 745 +02ea -- 746 +02eb -- 747 +02ec -- 748 +02ed -- 749 +02ee -- 750 +02ef -- 751 +02f0 -- 752 +02f1 -- 753 +02f2 -- 754 +02f3 -- 755 +02f4 -- 756 +02f5 -- 757 +02f6 -- 758 +02f7 -- 759 +02f8 -- 760 +02f9 -- 761 +02fa -- 762 +02fb -- 763 +02fc -- 764 +02fd -- 765 +02fe -- 766 +02ff -- 767 +0300 -- 768 +0301 -- 769 +0302 -- 770 +0303 -- 771 +0304 -- 772 +0305 -- 773 +0306 -- 774 +0307 -- 775 +0308 -- 776 +0309 -- 777 +030a -- 778 +030b -- 779 +030c -- 780 +030d -- 781 +030e -- 782 +030f -- 783 +0310 -- 784 +0311 -- 785 +0312 -- 786 +0313 -- 787 +0314 -- 788 +0315 -- 789 +0316 -- 790 +0317 -- 791 +0318 -- 792 +0319 -- 793 +031a -- 794 +031b -- 795 +031c -- 796 +031d -- 797 +031e -- 798 +031f -- 799 +0320 -- 800 +0321 -- 801 +0322 -- 802 +0323 -- 803 +0324 -- 804 +0325 -- 805 +0326 -- 806 +0327 -- 807 +0328 -- 808 +0329 -- 809 +032a -- 810 +032b -- 811 +032c -- 812 +032d -- 813 +032e -- 814 +032f -- 815 +0330 -- 816 +0331 -- 817 +0332 -- 818 +0333 -- 819 +0334 -- 820 +0335 -- 821 +0336 -- 822 +0337 -- 823 +0338 -- 824 +0339 -- 825 +033a -- 826 +033b -- 827 +033c -- 828 +033d -- 829 +033e -- 830 +033f -- 831 +0340 -- 832 +0341 -- 833 +0342 -- 834 +0343 -- 835 +0344 -- 836 +0345 -- 837 +0346 -- 838 +0347 -- 839 +0348 -- 840 +0349 -- 841 +034a -- 842 +034b -- 843 +034c -- 844 +034d -- 845 +034e -- 846 +034f -- 847 +0350 -- 848 +0351 -- 849 +0352 -- 850 +0353 -- 851 +0354 -- 852 +0355 -- 853 +0356 -- 854 +0357 -- 855 +0358 -- 856 +0359 -- 857 +035a -- 858 +035b -- 859 +035c -- 860 +035d -- 861 +035e -- 862 +035f -- 863 +0360 -- 864 +0361 -- 865 +0362 -- 866 +0363 -- 867 +0364 -- 868 +0365 -- 869 +0366 -- 870 +0367 -- 871 +0368 -- 872 +0369 -- 873 +036a -- 874 +036b -- 875 +036c -- 876 +036d -- 877 +036e -- 878 +036f -- 879 +0370 -- 880 +0371 -- 881 +0372 -- 882 +0373 -- 883 +0374 -- 884 +0375 -- 885 +0376 -- 886 +0377 -- 887 +0378 -- 888 +0379 -- 889 +037a -- 890 +037b -- 891 +037c -- 892 +037d -- 893 +037e -- 894 +037f -- 895 +0380 -- 896 +0381 -- 897 +0382 -- 898 +0383 -- 899 +0384 -- 900 +0385 -- 901 +0386 -- 902 +0387 -- 903 +0388 -- 904 +0389 -- 905 +038a -- 906 +038b -- 907 +038c -- 908 +038d -- 909 +038e -- 910 +038f -- 911 +0390 -- 912 +0391 -- 913 +0392 -- 914 +0393 -- 915 +0394 -- 916 +0395 -- 917 +0396 -- 918 +0397 -- 919 +0398 -- 920 +0399 -- 921 +039a -- 922 +039b -- 923 +039c -- 924 +039d -- 925 +039e -- 926 +039f -- 927 +03a0 -- 928 +03a1 -- 929 +03a2 -- 930 +03a3 -- 931 +03a4 -- 932 +03a5 -- 933 +03a6 -- 934 +03a7 -- 935 +03a8 -- 936 +03a9 -- 937 +03aa -- 938 +03ab -- 939 +03ac -- 940 +03ad -- 941 +03ae -- 942 +03af -- 943 +03b0 -- 944 +03b1 -- 945 +03b2 -- 946 +03b3 -- 947 +03b4 -- 948 +03b5 -- 949 +03b6 -- 950 +03b7 -- 951 +03b8 -- 952 +03b9 -- 953 +03ba -- 954 +03bb -- 955 +03bc -- 956 +03bd -- 957 +03be -- 958 +03bf -- 959 +03c0 -- 960 +03c1 -- 961 +03c2 -- 962 +03c3 -- 963 +03c4 -- 964 +03c5 -- 965 +03c6 -- 966 +03c7 -- 967 +03c8 -- 968 +03c9 -- 969 +03ca -- 970 +03cb -- 971 +03cc -- 972 +03cd -- 973 +03ce -- 974 +03cf -- 975 +03d0 -- 976 +03d1 -- 977 +03d2 -- 978 +03d3 -- 979 +03d4 -- 980 +03d5 -- 981 +03d6 -- 982 +03d7 -- 983 +03d8 -- 984 +03d9 -- 985 +03da -- 986 +03db -- 987 +03dc -- 988 +03dd -- 989 +03de -- 990 +03df -- 991 +03e0 -- 992 +03e1 -- 993 +03e2 -- 994 +03e3 -- 995 +03e4 -- 996 +03e5 -- 997 +03e6 -- 998 +03e7 -- 999 +03e8 -- 1000 +03e9 -- 1001 +03ea -- 1002 +03eb -- 1003 +03ec -- 1004 +03ed -- 1005 +03ee -- 1006 +03ef -- 1007 +03f0 -- 1008 +03f1 -- 1009 +03f2 -- 1010 +03f3 -- 1011 +03f4 -- 1012 +03f5 -- 1013 +03f6 -- 1014 +03f7 -- 1015 +03f8 -- 1016 +03f9 -- 1017 +03fa -- 1018 +03fb -- 1019 +03fc -- 1020 +03fd -- 1021 +03fe -- 1022 +03ff -- 1023 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/simulation_files/adcTB_complete.do =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/simulation_files/adcTB_complete.do (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/simulation_files/adcTB_complete.do (revision 9841) @@ -0,0 +1,30 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider {ADC EMULATOR} +add wave -noupdate /adc_emulator_tb/clk +add wave -noupdate /adc_emulator_tb/otr +add wave -noupdate /adc_emulator_tb/oeb +add wave -noupdate -radix hexadecimal /adc_emulator_tb/data +add wave -noupdate -divider {ADC ROM} +add wave -noupdate -expand -group {adc rom} -radix hexadecimal /adc_emulator_tb/i_adctb_adc/rom_addr +add wave -noupdate -expand -group {adc rom} -radix hexadecimal /adc_emulator_tb/i_adctb_adc/rom_data +add wave -noupdate -expand -group {adc rom} -radix hexadecimal /adc_emulator_tb/i_adctb_adc/rom_reg +add wave -noupdate -expand -group {adc rom} -radix hexadecimal -subitemconfig {/adc_emulator_tb/i_adctb_adc/rom(0) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(2) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(3) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(4) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(5) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(6) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(7) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(8) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(9) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(10) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(11) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(12) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(13) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(14) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(15) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(16) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(17) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(18) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(19) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(20) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(21) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(22) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(23) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(24) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(25) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(26) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(27) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(28) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(29) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(30) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(31) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(32) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(33) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(34) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(35) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(36) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(37) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(38) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(39) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(40) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(41) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(42) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(43) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(44) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(45) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(46) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(47) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(48) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(49) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(50) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(51) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(52) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(53) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(54) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(55) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(56) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(57) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(58) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(59) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(60) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(61) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(62) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(63) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(64) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(65) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(66) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(67) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(68) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(69) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(70) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(71) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(72) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(73) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(74) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(75) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(76) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(77) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(78) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(79) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(80) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(81) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(82) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(83) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(84) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(85) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(86) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(87) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(88) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(89) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(90) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(91) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(92) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(93) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(94) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(95) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(96) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(97) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(98) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(99) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(100) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(101) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(102) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(103) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(104) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(105) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(106) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(107) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(108) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(109) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(110) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(111) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(112) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(113) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(114) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(115) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(116) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(117) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(118) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(119) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(120) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(121) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(122) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(123) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(124) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(125) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(126) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(127) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(128) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(129) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(130) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(131) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(132) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(133) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(134) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(135) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(136) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(137) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(138) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(139) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(140) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(141) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(142) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(143) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(144) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(145) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(146) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(147) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(148) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(149) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(150) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(151) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(152) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(153) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(154) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(155) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(156) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(157) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(158) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(159) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(160) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(161) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(162) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(163) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(164) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(165) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(166) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(167) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(168) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(169) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(170) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(171) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(172) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(173) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(174) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(175) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(176) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(177) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(178) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(179) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(180) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(181) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(182) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(183) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(184) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(185) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(186) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(187) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(188) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(189) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(190) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(191) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(192) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(193) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(194) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(195) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(196) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(197) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(198) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(199) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(200) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(201) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(202) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(203) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(204) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(205) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(206) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(207) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(208) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(209) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(210) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(211) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(212) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(213) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(214) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(215) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(216) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(217) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(218) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(219) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(220) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(221) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(222) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(223) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(224) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(225) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(226) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(227) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(228) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(229) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(230) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(231) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(232) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(233) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(234) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(235) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(236) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(237) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(238) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(239) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(240) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(241) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(242) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(243) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(244) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(245) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(246) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(247) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(248) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(249) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(250) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(251) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(252) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(253) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(254) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(255) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(256) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(257) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(258) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(259) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(260) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(261) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(262) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(263) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(264) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(265) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(266) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(267) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(268) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(269) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(270) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(271) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(272) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(273) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(274) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(275) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(276) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(277) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(278) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(279) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(280) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(281) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(282) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(283) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(284) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(285) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(286) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(287) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(288) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(289) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(290) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(291) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(292) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(293) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(294) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(295) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(296) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(297) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(298) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(299) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(300) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(301) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(302) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(303) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(304) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(305) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(306) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(307) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(308) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(309) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(310) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(311) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(312) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(313) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(314) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(315) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(316) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(317) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(318) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(319) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(320) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(321) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(322) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(323) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(324) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(325) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(326) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(327) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(328) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(329) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(330) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(331) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(332) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(333) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(334) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(335) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(336) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(337) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(338) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(339) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(340) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(341) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(342) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(343) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(344) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(345) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(346) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(347) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(348) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(349) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(350) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(351) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(352) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(353) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(354) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(355) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(356) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(357) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(358) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(359) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(360) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(361) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(362) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(363) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(364) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(365) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(366) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(367) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(368) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(369) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(370) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(371) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(372) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(373) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(374) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(375) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(376) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(377) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(378) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(379) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(380) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(381) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(382) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(383) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(384) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(385) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(386) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(387) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(388) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(389) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(390) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(391) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(392) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(393) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(394) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(395) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(396) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(397) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(398) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(399) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(400) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(401) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(402) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(403) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(404) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(405) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(406) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(407) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(408) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(409) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(410) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(411) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(412) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(413) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(414) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(415) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(416) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(417) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(418) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(419) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(420) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(421) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(422) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(423) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(424) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(425) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(426) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(427) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(428) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(429) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(430) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(431) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(432) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(433) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(434) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(435) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(436) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(437) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(438) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(439) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(440) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(441) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(442) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(443) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(444) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(445) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(446) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(447) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(448) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(449) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(450) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(451) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(452) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(453) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(454) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(455) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(456) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(457) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(458) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(459) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(460) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(461) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(462) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(463) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(464) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(465) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(466) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(467) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(468) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(469) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(470) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(471) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(472) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(473) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(474) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(475) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(476) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(477) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(478) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(479) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(480) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(481) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(482) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(483) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(484) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(485) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(486) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(487) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(488) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(489) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(490) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(491) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(492) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(493) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(494) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(495) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(496) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(497) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(498) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(499) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(500) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(501) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(502) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(503) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(504) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(505) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(506) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(507) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(508) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(509) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(510) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(511) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(512) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(513) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(514) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(515) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(516) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(517) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(518) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(519) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(520) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(521) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(522) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(523) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(524) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(525) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(526) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(527) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(528) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(529) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(530) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(531) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(532) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(533) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(534) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(535) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(536) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(537) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(538) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(539) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(540) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(541) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(542) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(543) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(544) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(545) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(546) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(547) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(548) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(549) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(550) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(551) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(552) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(553) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(554) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(555) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(556) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(557) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(558) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(559) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(560) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(561) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(562) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(563) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(564) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(565) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(566) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(567) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(568) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(569) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(570) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(571) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(572) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(573) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(574) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(575) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(576) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(577) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(578) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(579) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(580) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(581) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(582) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(583) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(584) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(585) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(586) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(587) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(588) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(589) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(590) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(591) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(592) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(593) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(594) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(595) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(596) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(597) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(598) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(599) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(600) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(601) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(602) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(603) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(604) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(605) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(606) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(607) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(608) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(609) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(610) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(611) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(612) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(613) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(614) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(615) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(616) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(617) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(618) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(619) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(620) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(621) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(622) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(623) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(624) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(625) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(626) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(627) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(628) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(629) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(630) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(631) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(632) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(633) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(634) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(635) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(636) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(637) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(638) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(639) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(640) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(641) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(642) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(643) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(644) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(645) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(646) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(647) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(648) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(649) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(650) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(651) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(652) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(653) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(654) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(655) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(656) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(657) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(658) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(659) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(660) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(661) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(662) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(663) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(664) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(665) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(666) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(667) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(668) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(669) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(670) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(671) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(672) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(673) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(674) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(675) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(676) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(677) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(678) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(679) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(680) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(681) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(682) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(683) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(684) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(685) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(686) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(687) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(688) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(689) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(690) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(691) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(692) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(693) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(694) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(695) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(696) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(697) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(698) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(699) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(700) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(701) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(702) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(703) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(704) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(705) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(706) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(707) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(708) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(709) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(710) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(711) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(712) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(713) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(714) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(715) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(716) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(717) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(718) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(719) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(720) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(721) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(722) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(723) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(724) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(725) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(726) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(727) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(728) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(729) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(730) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(731) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(732) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(733) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(734) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(735) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(736) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(737) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(738) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(739) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(740) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(741) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(742) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(743) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(744) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(745) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(746) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(747) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(748) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(749) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(750) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(751) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(752) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(753) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(754) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(755) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(756) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(757) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(758) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(759) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(760) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(761) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(762) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(763) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(764) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(765) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(766) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(767) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(768) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(769) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(770) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(771) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(772) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(773) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(774) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(775) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(776) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(777) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(778) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(779) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(780) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(781) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(782) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(783) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(784) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(785) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(786) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(787) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(788) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(789) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(790) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(791) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(792) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(793) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(794) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(795) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(796) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(797) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(798) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(799) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(800) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(801) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(802) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(803) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(804) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(805) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(806) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(807) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(808) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(809) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(810) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(811) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(812) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(813) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(814) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(815) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(816) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(817) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(818) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(819) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(820) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(821) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(822) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(823) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(824) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(825) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(826) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(827) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(828) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(829) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(830) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(831) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(832) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(833) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(834) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(835) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(836) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(837) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(838) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(839) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(840) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(841) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(842) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(843) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(844) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(845) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(846) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(847) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(848) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(849) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(850) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(851) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(852) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(853) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(854) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(855) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(856) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(857) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(858) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(859) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(860) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(861) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(862) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(863) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(864) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(865) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(866) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(867) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(868) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(869) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(870) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(871) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(872) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(873) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(874) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(875) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(876) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(877) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(878) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(879) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(880) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(881) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(882) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(883) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(884) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(885) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(886) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(887) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(888) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(889) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(890) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(891) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(892) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(893) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(894) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(895) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(896) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(897) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(898) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(899) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(900) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(901) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(902) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(903) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(904) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(905) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(906) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(907) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(908) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(909) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(910) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(911) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(912) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(913) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(914) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(915) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(916) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(917) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(918) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(919) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(920) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(921) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(922) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(923) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(924) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(925) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(926) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(927) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(928) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(929) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(930) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(931) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(932) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(933) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(934) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(935) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(936) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(937) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(938) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(939) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(940) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(941) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(942) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(943) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(944) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(945) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(946) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(947) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(948) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(949) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(950) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(951) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(952) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(953) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(954) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(955) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(956) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(957) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(958) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(959) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(960) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(961) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(962) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(963) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(964) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(965) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(966) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(967) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(968) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(969) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(970) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(971) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(972) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(973) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(974) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(975) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(976) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(977) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(978) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(979) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(980) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(981) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(982) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(983) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(984) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(985) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(986) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(987) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(988) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(989) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(990) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(991) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(992) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(993) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(994) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(995) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(996) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(997) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(998) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(999) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1000) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1001) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1002) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1003) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1004) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1005) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1006) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1007) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1008) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1009) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1010) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1011) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1012) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1013) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1014) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1015) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1016) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1017) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1018) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1019) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1020) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1021) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1022) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1023) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1024) {-radix hexadecimal}} /adc_emulator_tb/i_adctb_adc/rom +add wave -noupdate -expand -group {adc rom} -radix hexadecimal /adc_emulator_tb/i_adctb_adc/input_file +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {1010000 ps} 0} +configure wave -namecolwidth 115 +configure wave -valuecolwidth 152 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {2067988 ps} Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/simulation_files/boardTB_complete.do =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/simulation_files/boardTB_complete.do (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_TB_lib/simulation_files/boardTB_complete.do (revision 9841) @@ -0,0 +1,65 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fad_main_tb/clk +add wave -noupdate /fad_main_tb/clk_50 +add wave -noupdate /fad_main_tb/clk_25_ps +add wave -noupdate /fad_main_tb/trigger +add wave -noupdate -divider ADC +add wave -noupdate -radix hexadecimal /fad_main_tb/adc_data +add wave -noupdate /fad_main_tb/adc_otr +add wave -noupdate -radix hexadecimal /fad_main_tb/adc_data_array +add wave -noupdate /fad_main_tb/adc_oeb +add wave -noupdate /fad_main_tb/adc_otr_array +add wave -noupdate -divider {DRS4 INTERFACE} +add wave -noupdate /fad_main_tb/denable +add wave -noupdate /fad_main_tb/drs_dwrite +add wave -noupdate -radix unsigned /fad_main_tb/drs_channel_id +add wave -noupdate /fad_main_tb/rsrload +add wave -noupdate /fad_main_tb/srclk +add wave -noupdate /fad_main_tb/srout_in_0 +add wave -noupdate /fad_main_tb/srout_in_1 +add wave -noupdate /fad_main_tb/srout_in_2 +add wave -noupdate /fad_main_tb/srout_in_3 +add wave -noupdate -divider {SPI INTERFACE} +add wave -noupdate /fad_main_tb/sclk +add wave -noupdate /fad_main_tb/mosi +add wave -noupdate /fad_main_tb/sio +add wave -noupdate /fad_main_tb/dac_cs +add wave -noupdate /fad_main_tb/sensor_cs +add wave -noupdate -divider RAM +add wave -noupdate -radix hexadecimal /fad_main_tb/i_maintb_fpga/ram_data +add wave -noupdate -radix hexadecimal /fad_main_tb/i_maintb_fpga/ram_addr +add wave -noupdate -radix hexadecimal /fad_main_tb/i_maintb_fpga/i_main_ethernet/local_ram_start_addr +add wave -noupdate -radix hexadecimal /fad_main_tb/i_maintb_fpga/i_main_ethernet/local_ram_addr +add wave -noupdate -divider {ETHERNET INTERFACE} +add wave -noupdate /fad_main_tb/wiz_reset +add wave -noupdate -radix hexadecimal /fad_main_tb/wiz_addr +add wave -noupdate -radix hexadecimal /fad_main_tb/wiz_data +add wave -noupdate /fad_main_tb/wiz_cs +add wave -noupdate /fad_main_tb/wiz_rd +add wave -noupdate /fad_main_tb/wiz_wr +add wave -noupdate /fad_main_tb/wiz_int +add wave -noupdate -divider {FAD ID} +add wave -noupdate /fad_main_tb/board_id +add wave -noupdate /fad_main_tb/crate_id +add wave -noupdate -divider +add wave -noupdate /fad_main_tb/led +add wave -noupdate /fad_main_tb/i_maintb_fpga/i_main_ethernet/s_trigger +add wave -noupdate /fad_main_tb/i_maintb_fpga/i_main_ethernet/chk_recv_cntr +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {3394736453 ps} 1} {{Cursor 2} {3394460449 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {3390161132 ps} {3397338868 ps} Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/DCM_25MHz_38nsPS_BEHAVIORAL.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/DCM_25MHz_38nsPS_BEHAVIORAL.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/DCM_25MHz_38nsPS_BEHAVIORAL.vhd (revision 9841) @@ -0,0 +1,183 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 10.1.03 +-- \ \ Application : xaw2vhdl +-- / / Filename : DCM_25MHz_38nsPS.vhd +-- /___/ /\ Timestamp : 03/29/2010 10:34:42 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st C:\DOKUME~1\FPGA_D~1\LOKALE~1\Temp\coregen_FPGA_Developer\coregen\project\DCM_25MHz_38nsPS.xaw C:\DOKUME~1\FPGA_D~1\LOKALE~1\Temp\coregen_FPGA_Developer\coregen\project\DCM_25MHz_38nsPS +--Design Name: DCM_25MHz_38nsPS +--Device: xc3s700a-4fg484 +-- +-- Module DCM_25MHz_38nsPS +-- Written for synthesis tool: Precision + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity DCM_25MHz_38nsPS is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end DCM_25MHz_38nsPS; + +architecture BEHAVIORAL of DCM_25MHz_38nsPS is + +-- hds translate_off + + attribute CLK_FEEDBACK : string ; + attribute CLKDV_DIVIDE : string ; + attribute CLKFX_DIVIDE : string ; + attribute CLKFX_MULTIPLY : string ; + attribute CLKIN_DIVIDE_BY_2 : string ; + attribute CLKIN_PERIOD : string ; + attribute CLKOUT_PHASE_SHIFT : string ; + attribute DESKEW_ADJUST : string ; + attribute DFS_FREQUENCY_MODE : string ; + attribute DLL_FREQUENCY_MODE : string ; + attribute DUTY_CYCLE_CORRECTION : string ; + attribute FACTORY_JF : string ; + attribute PHASE_SHIFT : string ; + attribute STARTUP_WAIT : string ; + signal CLKFB_IN : std_logic; + signal CLKIN_IBUFG : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; + component IBUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + component BUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + component DCM_SP + -- synthesis translate_off + generic( CLK_FEEDBACK : string := "1X"; + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := FALSE; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DUTY_CYCLE_CORRECTION : boolean := TRUE; + FACTORY_JF : bit_vector := x"C080"; + PHASE_SHIFT : integer := 0; + STARTUP_WAIT : boolean := FALSE; + DSS_MODE : string := "NONE"); + -- synthesis translate_on + port ( CLKIN : in std_logic; + CLKFB : in std_logic; + RST : in std_logic; + PSEN : in std_logic; + PSINCDEC : in std_logic; + PSCLK : in std_logic; + DSSEN : in std_logic; + CLK0 : out std_logic; + CLK90 : out std_logic; + CLK180 : out std_logic; + CLK270 : out std_logic; + CLKDV : out std_logic; + CLK2X : out std_logic; + CLK2X180 : out std_logic; + CLKFX : out std_logic; + CLKFX180 : out std_logic; + STATUS : out std_logic_vector (7 downto 0); + LOCKED : out std_logic; + PSDONE : out std_logic); + end component; + + attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X"; + attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0"; + attribute CLKFX_DIVIDE of DCM_SP_INST : label is "1"; + attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "4"; + attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE"; + attribute CLKIN_PERIOD of DCM_SP_INST : label is "40.000"; + attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "FIXED"; + attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS"; + attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; + attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; + attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE"; + attribute FACTORY_JF of DCM_SP_INST : label is "C080"; + attribute PHASE_SHIFT of DCM_SP_INST : label is "243"; + attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE"; + +-- hds translate_on + +begin + +-- hds translate_off + + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLK0_OUT <= CLKFB_IN; + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + -- synthesis translate_off + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 4, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 40.000, + CLKOUT_PHASE_SHIFT => "FIXED", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 243, + STARTUP_WAIT => FALSE) + -- synthesis translate_on + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>open, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + + +-- hds translate_on + +end BEHAVIORAL; + + + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/DCM_25MHz_noPS_BEHAVIORAL.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/DCM_25MHz_noPS_BEHAVIORAL.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/DCM_25MHz_noPS_BEHAVIORAL.vhd (revision 9841) @@ -0,0 +1,189 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 10.1.03 +-- \ \ Application : xaw2vhdl +-- / / Filename : DCM_25MHz_noPS.vhd +-- /___/ /\ Timestamp : 03/29/2010 10:36:52 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st C:/DOKUME~1/FPGA_D~1/LOKALE~1/Temp/coregen_FPGA_Developer/coregen/project/DCM_25MHz_noPS.xaw C:/DOKUME~1/FPGA_D~1/LOKALE~1/Temp/coregen_FPGA_Developer/coregen/project/DCM_25MHz_noPS +--Design Name: DCM_25MHz_noPS +--Device: xc3s700a-4fg484 +-- +-- Module DCM_25MHz_noPS +-- Written for synthesis tool: Precision + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity DCM_25MHz_noPS is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKDV_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end DCM_25MHz_noPS; + +architecture BEHAVIORAL of DCM_25MHz_noPS is + +-- hds translate_off + + attribute CLK_FEEDBACK : string ; + attribute CLKDV_DIVIDE : string ; + attribute CLKFX_DIVIDE : string ; + attribute CLKFX_MULTIPLY : string ; + attribute CLKIN_DIVIDE_BY_2 : string ; + attribute CLKIN_PERIOD : string ; + attribute CLKOUT_PHASE_SHIFT : string ; + attribute DESKEW_ADJUST : string ; + attribute DFS_FREQUENCY_MODE : string ; + attribute DLL_FREQUENCY_MODE : string ; + attribute DUTY_CYCLE_CORRECTION : string ; + attribute FACTORY_JF : string ; + attribute PHASE_SHIFT : string ; + attribute STARTUP_WAIT : string ; + signal CLKDV_BUF : std_logic; + signal CLKFB_IN : std_logic; + signal CLKIN_IBUFG : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; + component BUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + component IBUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + component DCM_SP + -- synthesis translate_off + generic( CLK_FEEDBACK : string := "1X"; + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := FALSE; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DUTY_CYCLE_CORRECTION : boolean := TRUE; + FACTORY_JF : bit_vector := x"C080"; + PHASE_SHIFT : integer := 0; + STARTUP_WAIT : boolean := FALSE; + DSS_MODE : string := "NONE"); + -- synthesis translate_on + port ( CLKIN : in std_logic; + CLKFB : in std_logic; + RST : in std_logic; + PSEN : in std_logic; + PSINCDEC : in std_logic; + PSCLK : in std_logic; + DSSEN : in std_logic; + CLK0 : out std_logic; + CLK90 : out std_logic; + CLK180 : out std_logic; + CLK270 : out std_logic; + CLKDV : out std_logic; + CLK2X : out std_logic; + CLK2X180 : out std_logic; + CLKFX : out std_logic; + CLKFX180 : out std_logic; + STATUS : out std_logic_vector (7 downto 0); + LOCKED : out std_logic; + PSDONE : out std_logic); + end component; + + attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X"; + attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0"; + attribute CLKFX_DIVIDE of DCM_SP_INST : label is "1"; + attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "4"; + attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE"; + attribute CLKIN_PERIOD of DCM_SP_INST : label is "20.000"; + attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "NONE"; + attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS"; + attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; + attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; + attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE"; + attribute FACTORY_JF of DCM_SP_INST : label is "C080"; + attribute PHASE_SHIFT of DCM_SP_INST : label is "0"; + attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE"; + +-- hds translate_on + +begin + +-- hds translate_off + + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLK0_OUT <= CLKFB_IN; + CLKDV_BUFG_INST : BUFG + port map (I=>CLKDV_BUF, + O=>CLKDV_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + -- synthesis translate_off + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 4, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + -- synthesis translate_on + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>CLKDV_BUF, + CLKFX=>open, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + + +-- hds translate_on + +end BEHAVIORAL; + + + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/adc_buffer_beha.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/adc_buffer_beha.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/adc_buffer_beha.vhd (revision 9841) @@ -0,0 +1,47 @@ +-- +-- VHDL Architecture FACT_FAD_lib.adc_buffer.beha +-- +-- Created: +-- by - kai.UNKNOWN (E5PCXX) +-- at - 14:57:55 04.05.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use ieee.STD_LOGIC_UNSIGNED.all; + +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + +library UNISIM; +use UNISIM.VComponents.all; +USE IEEE.NUMERIC_STD.all; +USE IEEE.std_logic_signed.all; + +ENTITY adc_buffer IS + PORT( + clk_ps : IN std_logic; + adc_data_array : IN adc_data_array_type; + adc_otr_array : IN std_logic_vector (3 DOWNTO 0); + adc_data_array_int : OUT adc_data_array_type; + adc_otr : OUT std_logic_vector (3 DOWNTO 0) + ); + +-- Declarations + +END adc_buffer ; + +-- +ARCHITECTURE beha OF adc_buffer IS +BEGIN + adc_buf : process (clk_ps) + begin + if rising_edge (clk_ps) then + adc_data_array_int <= adc_data_array; + adc_otr <= adc_otr_array; + end if; + end process adc_buf; +END ARCHITECTURE beha; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/clock_generator_struct.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/clock_generator_struct.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/clock_generator_struct.vhd (revision 9841) @@ -0,0 +1,95 @@ +-- VHDL Entity FACT_FAD_lib.clock_generator.symbol +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 13:32:31 23.06.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +ENTITY clock_generator IS + PORT( + CLK : IN std_logic; + CLK_25 : OUT std_logic; + CLK_25_PS : OUT std_logic; + CLK_50 : OUT std_logic + ); + +-- Declarations + +END clock_generator ; + +-- +-- VHDL Architecture FACT_FAD_lib.clock_generator.struct +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 13:32:32 23.06.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.numeric_std.all; +LIBRARY UNISIM; +USE UNISIM.Vcomponents.all; + +LIBRARY FACT_FAD_lib; + +ARCHITECTURE struct OF clock_generator IS + + -- Architecture declarations + + -- Internal signal declarations + + -- Implicit buffer signal declarations + SIGNAL CLK_25_internal : std_logic; + + + -- Component Declarations + COMPONENT dcm_50_to_25 + PORT ( + CLKIN_IN : IN std_logic; + CLK0_OUT : OUT std_logic; + CLKFX_OUT : OUT std_logic; + CLKIN_IBUFG_OUT : OUT std_logic + ); + END COMPONENT; + COMPONENT dcm_ps_38ns + PORT ( + CLKIN_IN : IN std_logic; + CLK0_OUT : OUT std_logic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : dcm_50_to_25 USE ENTITY FACT_FAD_lib.dcm_50_to_25; + FOR ALL : dcm_ps_38ns USE ENTITY FACT_FAD_lib.dcm_ps_38ns; + -- pragma synthesis_on + + +BEGIN + + -- Instance port mappings. + U_0 : dcm_50_to_25 + PORT MAP ( + CLKIN_IN => CLK, + CLKFX_OUT => CLK_25_internal, + CLKIN_IBUFG_OUT => OPEN, + CLK0_OUT => CLK_50 + ); + U_1 : dcm_ps_38ns + PORT MAP ( + CLKIN_IN => CLK_25_internal, + CLK0_OUT => CLK_25_PS + ); + + -- Implicit buffered output assignments + CLK_25 <= CLK_25_internal; + +END struct; Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/controlRAM_16bit_x256_controlRAM_16bit_x256_a.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/controlRAM_16bit_x256_controlRAM_16bit_x256_a.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/controlRAM_16bit_x256_controlRAM_16bit_x256_a.vhd (revision 9841) @@ -0,0 +1,139 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file controlRAM_16bit_x256.vhd when simulating +-- the core, controlRAM_16bit_x256. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY controlRAM_16bit_x256 IS + port ( + clka: IN std_logic; + dina: IN std_logic_VECTOR(15 downto 0); + addra: IN std_logic_VECTOR(7 downto 0); + wea: IN std_logic_VECTOR(0 downto 0); + douta: OUT std_logic_VECTOR(15 downto 0)); +END controlRAM_16bit_x256; + +ARCHITECTURE controlRAM_16bit_x256_a OF controlRAM_16bit_x256 IS + +-- hds translate_off + +-- synthesis translate_off +component wrapped_controlRAM_16bit_x256 + port ( + clka: IN std_logic; + dina: IN std_logic_VECTOR(15 downto 0); + addra: IN std_logic_VECTOR(7 downto 0); + wea: IN std_logic_VECTOR(0 downto 0); + douta: OUT std_logic_VECTOR(15 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_controlRAM_16bit_x256 use entity XilinxCoreLib.blk_mem_gen_v2_8(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 0, + c_prim_type => 1, + c_sinita_val => "0", + c_read_width_b => 16, + c_family => "spartan3", + c_read_width_a => 16, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "WRITE_FIRST", + c_init_file_name => "no_coe_file_loaded", + c_write_mode_a => "WRITE_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 0, + c_xdevicefamily => "spartan3a", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 256, + c_write_depth_a => 256, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 8, + c_addrb_width => 8, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 16, + c_write_width_a => 16, + c_read_depth_b => 256, + c_read_depth_a => 256, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 0, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 0); +-- synthesis translate_on + +-- hds translate_on + +BEGIN + +-- hds translate_off + +-- synthesis translate_off +U0 : wrapped_controlRAM_16bit_x256 + port map ( + clka => clka, + dina => dina, + addra => addra, + wea => wea, + douta => douta); +-- synthesis translate_on + + +-- hds translate_on + +END controlRAM_16bit_x256_a; + + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd (revision 9841) @@ -0,0 +1,166 @@ +-- +-- VHDL Architecture FACT_FAD_lib.controlRAM_manager.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 14:35:46 14.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; +USE ieee.std_logic_unsigned.ALL; +LIBRARY FACT_FAD_LIB; +USE FACT_FAD_LIB.fad_definitions.ALL; + +ENTITY control_manager IS + GENERIC( + NO_OF_ROI : integer := 36; + NO_OF_DAC : integer := 8; + ADDR_WIDTH : integer := 8 + ); + PORT( + clk : IN std_logic; + ram_data_out : IN std_logic_vector (15 DOWNTO 0); + config_ready, config_started : OUT std_logic := '0'; + config_start : IN std_logic; + config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + config_addr : IN std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0); + config_wr_en : IN std_logic; + config_rd_en : IN std_logic; + config_data_valid : OUT std_logic := '0'; + config_busy : OUT std_logic := '0'; + ram_addr : OUT std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0); + ram_data_in : OUT std_logic_vector (15 DOWNTO 0); + ram_write_en : OUT std_logic_vector (0 DOWNTO 0); + dac_array : OUT dac_array_type; + roi_array : OUT roi_array_type; + drs_address : OUT std_logic_vector (3 DOWNTO 0); + drs_address_mode : OUT std_logic + ); + +-- Declarations + +END control_manager ; + +ARCHITECTURE beha OF control_manager IS + + type TYPE_CTRL_STATE is (CTRL_INIT, CTRL_IDLE, CTRL_WAIT_IDLE, CTRL_WRITE, + CTRL_LOAD_ADDR, CTRL_LOAD_WAIT, CTRL_LOAD_DATA, + CTRL_READ_ADDR, CTRL_READ_WAIT, CTRL_READ_DATA); + + signal ctrl_state : TYPE_CTRL_STATE := CTRL_INIT; + signal addr_cntr : integer range 0 to 2**ADDR_WIDTH - 1 := 0; + signal int_dac_array : dac_array_type := DEFAULT_DAC; + signal int_roi_array : roi_array_type := DEFAULT_ROI; + signal int_drs_address: std_logic_vector (3 DOWNTO 0) := DEFAULT_DRSADDR; + signal int_drs_address_mode: std_logic := DEFAULT_DRSADDR_MODE; + +BEGIN + + control_fsm_proc: process (clk) + begin + + if rising_edge(clk) then + + config_busy <= '1'; -- is always busy except in idle mode + + case ctrl_state is + + when CTRL_INIT => + -- WRITES DEFAULT VALUES IN config ram + addr_cntr <= addr_cntr + 1; + ram_addr <= conv_std_logic_vector(addr_cntr, ADDR_WIDTH); + config_data_valid <= '0'; + config_ready <= '0'; + ctrl_state <= CTRL_INIT; + ram_write_en <= "1"; + if (addr_cntr < NO_OF_ROI) then + ram_data_in <= conv_std_logic_vector(int_roi_array(addr_cntr ), 16); + elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then + ram_data_in <= conv_std_logic_vector(int_dac_array(addr_cntr - NO_OF_ROI), 16); + elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then + ram_data_in <= "0000" & "0000" + & "000" & conv_std_logic_vector(int_drs_address_mode, 1) + & int_drs_address; + else + ram_write_en <= "0"; + ctrl_state <= CTRL_IDLE; + end if; + + when CTRL_IDLE => + -- + addr_cntr <= 0; + ram_write_en <= "0"; + config_busy <= '0'; + if (config_start = '1') then + config_started <= '1'; + config_ready <= '0'; + config_data_valid <= '0'; + ctrl_state <= CTRL_LOAD_ADDR; + end if; + if (config_wr_en = '1') then + config_busy <= '1'; + config_data <= (others => 'Z'); + ctrl_state <= CTRL_WRITE; + end if; + if (config_rd_en = '1') then + ram_addr <= config_addr; + config_data_valid <= '0'; +-- ctrl_state <= CTRL_READ_ADDR; + ctrl_state <= CTRL_READ_WAIT; + end if; + + when CTRL_WAIT_IDLE => + ctrl_state <= CTRL_IDLE; + + when CTRL_LOAD_ADDR => + ram_addr <= conv_std_logic_vector(addr_cntr, ADDR_WIDTH); + ctrl_state <= CTRL_LOAD_WAIT; + when CTRL_LOAD_WAIT => + ctrl_state <= CTRL_LOAD_DATA; + when CTRL_LOAD_DATA => + addr_cntr <= addr_cntr + 1; + if (addr_cntr < NO_OF_ROI) then + roi_array(addr_cntr) <= conv_integer(ram_data_out); + ctrl_state <= CTRL_LOAD_ADDR; + elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then + dac_array(addr_cntr - NO_OF_ROI) <= conv_integer(ram_data_out); + ctrl_state <= CTRL_LOAD_ADDR; + elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then + drs_address <= ram_data_out(3 downto 0); + drs_address_mode <= ram_data_out(4); + ctrl_state <= CTRL_LOAD_ADDR; + else + addr_cntr <= 0; + config_started <= '0'; + config_ready <= '1'; + ctrl_state <= CTRL_WAIT_IDLE; + end if; + + when CTRL_WRITE => + ram_data_in <= config_data; + ram_addr <= config_addr; + ram_write_en <= "1"; + ctrl_state <= CTRL_IDLE; + + -- *** IMPORTANT *** + -- read address must remain two clock cycles + when CTRL_READ_ADDR => + ctrl_state <= CTRL_READ_WAIT; + when CTRL_READ_WAIT => + ctrl_state <= CTRL_READ_DATA; + when CTRL_READ_DATA => + config_data <= ram_data_out; + config_data_valid <= '1'; + ctrl_state <= CTRL_IDLE; + + end case; + + end if; + + end process control_fsm_proc; + +END ARCHITECTURE beha; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_unit_struct.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_unit_struct.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_unit_struct.vhd (revision 9841) @@ -0,0 +1,148 @@ +-- VHDL Entity FACT_FAD_lib.control_unit.symbol +-- +-- Created: +-- by - dneise.UNKNOWN (TU-CC4900F8C7D2) +-- at - 14:46:37 12.07.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; +LIBRARY FACT_FAD_LIB; +USE FACT_FAD_LIB.fad_definitions.ALL; + +ENTITY control_unit IS + PORT( + clk : IN STD_LOGIC; + config_addr : IN std_logic_vector (7 DOWNTO 0); + config_rd_en : IN std_logic; + config_start : IN std_logic; + config_wr_en : IN std_logic; + config_busy : OUT std_logic; + config_data_valid : OUT std_logic; + config_ready : OUT std_logic; + config_started : OUT std_logic := '0'; + dac_array : OUT dac_array_type; + drs_address : OUT std_logic_vector (3 DOWNTO 0); + drs_address_mode : OUT std_logic; + roi_array : OUT roi_array_type; + config_data : INOUT std_logic_vector (15 DOWNTO 0) + ); + +-- Declarations + +END control_unit ; + +-- +-- VHDL Architecture FACT_FAD_lib.control_unit.struct +-- +-- Created: +-- by - dneise.UNKNOWN (TU-CC4900F8C7D2) +-- at - 14:46:37 12.07.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; +LIBRARY FACT_FAD_LIB; +USE FACT_FAD_LIB.fad_definitions.ALL; + +LIBRARY FACT_FAD_lib; + +ARCHITECTURE struct OF control_unit IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL ram_addr : std_logic_VECTOR(7 DOWNTO 0); + SIGNAL ram_data_in : std_logic_VECTOR(15 DOWNTO 0); + SIGNAL ram_data_out : std_logic_VECTOR(15 DOWNTO 0); + SIGNAL ram_wren : std_logic_VECTOR(0 DOWNTO 0); + + + -- Component Declarations + COMPONENT controlRAM_16bit_x256 + PORT ( + clka : IN std_logic ; + dina : IN std_logic_VECTOR (15 DOWNTO 0); + addra : IN std_logic_VECTOR (7 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + douta : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + END COMPONENT; + COMPONENT control_manager + GENERIC ( + NO_OF_ROI : integer := 36; + NO_OF_DAC : integer := 8; + ADDR_WIDTH : integer := 8 + ); + PORT ( + clk : IN std_logic ; + ram_data_out : IN std_logic_vector (15 DOWNTO 0); + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0'; + config_start : IN std_logic ; + config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + config_addr : IN std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0); + config_wr_en : IN std_logic ; + config_rd_en : IN std_logic ; + config_data_valid : OUT std_logic := '0'; + config_busy : OUT std_logic := '0'; + ram_addr : OUT std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0); + ram_data_in : OUT std_logic_vector (15 DOWNTO 0); + ram_write_en : OUT std_logic_vector (0 DOWNTO 0); + dac_array : OUT dac_array_type ; + roi_array : OUT roi_array_type ; + drs_address : OUT std_logic_vector (3 DOWNTO 0); + drs_address_mode : OUT std_logic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : controlRAM_16bit_x256 USE ENTITY FACT_FAD_lib.controlRAM_16bit_x256; + FOR ALL : control_manager USE ENTITY FACT_FAD_lib.control_manager; + -- pragma synthesis_on + + +BEGIN + + -- Instance port mappings. + I_control_ram : controlRAM_16bit_x256 + PORT MAP ( + clka => clk, + dina => ram_data_in, + addra => ram_addr, + wea => ram_wren, + douta => ram_data_out + ); + I_control_manager : control_manager + GENERIC MAP ( + NO_OF_ROI => 36, + NO_OF_DAC => 8, + ADDR_WIDTH => 8 + ) + PORT MAP ( + clk => clk, + ram_data_out => ram_data_out, + config_ready => config_ready, + config_started => config_started, + config_start => config_start, + config_data => config_data, + config_addr => config_addr, + config_wr_en => config_wr_en, + config_rd_en => config_rd_en, + config_data_valid => config_data_valid, + config_busy => config_busy, + ram_addr => ram_addr, + ram_data_in => ram_data_in, + ram_write_en => ram_wren, + dac_array => dac_array, + roi_array => roi_array, + drs_address => drs_address, + drs_address_mode => drs_address_mode + ); + +END struct; Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/dataRAM_64b_16b_width14_5_dataRAM_64b_16b_width14_5_a.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/dataRAM_64b_16b_width14_5_dataRAM_64b_16b_width14_5_a.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/dataRAM_64b_16b_width14_5_dataRAM_64b_16b_width14_5_a.vhd (revision 9841) @@ -0,0 +1,153 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file dataRAM_64b_16b_width14_5.vhd when simulating +-- the core, dataRAM_64b_16b_width14_5. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +-- hds interface_start +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; + +-- synthesis translate_on +-- +ENTITY dataRAM_64b_16b_width14_5 IS + PORT( + clka : IN std_logic; + dina : IN std_logic_VECTOR (63 DOWNTO 0); + addra : IN std_logic_VECTOR (14 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + clkb : IN std_logic; + addrb : IN std_logic_VECTOR (16 DOWNTO 0); + doutb : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + +-- Declarations + +END dataRAM_64b_16b_width14_5 ; +-- hds interface_end + +ARCHITECTURE dataRAM_64b_16b_width14_5_a OF dataRAM_64b_16b_width14_5 IS + +-- hds translate_off + +-- synthesis translate_off +component wrapped_dataRAM_64b_16b_width14_5 + port ( + clka: IN std_logic; + dina: IN std_logic_VECTOR(63 downto 0); + addra: IN std_logic_VECTOR(14 downto 0); + wea: IN std_logic_VECTOR(0 downto 0); + clkb: IN std_logic; + addrb: IN std_logic_VECTOR(16 downto 0); + doutb: OUT std_logic_VECTOR(15 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_dataRAM_64b_16b_width14_5 use entity XilinxCoreLib.blk_mem_gen_v2_8(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 1, + c_prim_type => 1, + c_sinita_val => "0", + c_read_width_b => 16, + c_family => "spartan3", + c_read_width_a => 64, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "READ_FIRST", + c_init_file_name => "no_coe_file_loaded", + c_write_mode_a => "READ_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 0, + c_xdevicefamily => "spartan3adsp", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 98304, + c_write_depth_a => 24576, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 15, + c_addrb_width => 17, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 16, + c_write_width_a => 64, + c_read_depth_b => 98304, + c_read_depth_a => 24576, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 0, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 0); +-- synthesis translate_on + +-- hds translate_on + +BEGIN + +-- hds translate_off + +-- synthesis translate_off +U0 : wrapped_dataRAM_64b_16b_width14_5 + port map ( + clka => clka, + dina => dina, + addra => addra, + wea => wea, + clkb => clkb, + addrb => addrb, + doutb => doutb); +-- synthesis translate_on + + +-- hds translate_on + +END dataRAM_64b_16b_width14_5_a; + + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd (revision 9841) @@ -0,0 +1,153 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file dataRAM_64b_16b_width15.vhd when simulating +-- the core, dataRAM_64b_16b_width15. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +-- hds interface_start +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; + +-- synthesis translate_on +-- +ENTITY dataRAM_64b_16b_width15 IS + PORT( + clka : IN std_logic; + dina : IN std_logic_VECTOR (63 DOWNTO 0); + addra : IN std_logic_VECTOR (14 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + clkb : IN std_logic; + addrb : IN std_logic_VECTOR (16 DOWNTO 0); + doutb : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + +-- Declarations + +END dataRAM_64b_16b_width15 ; +-- hds interface_end + +ARCHITECTURE dataRAM_64b_16b_width15_a OF dataRAM_64b_16b_width15 IS + +-- hds translate_off + +-- synthesis translate_off +component wrapped_dataRAM_64b_16b_width15 + port ( + clka: IN std_logic; + dina: IN std_logic_VECTOR(63 downto 0); + addra: IN std_logic_VECTOR(14 downto 0); + wea: IN std_logic_VECTOR(0 downto 0); + clkb: IN std_logic; + addrb: IN std_logic_VECTOR(16 downto 0); + doutb: OUT std_logic_VECTOR(15 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_dataRAM_64b_16b_width15 use entity XilinxCoreLib.blk_mem_gen_v2_8(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 1, + c_prim_type => 1, + c_sinita_val => "0", + c_read_width_b => 16, + c_family => "spartan3", + c_read_width_a => 64, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "READ_FIRST", + c_init_file_name => "no_coe_file_loaded", + c_write_mode_a => "READ_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 0, + c_xdevicefamily => "spartan3adsp", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 131072, + c_write_depth_a => 32768, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 15, + c_addrb_width => 17, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 16, + c_write_width_a => 64, + c_read_depth_b => 131072, + c_read_depth_a => 32768, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 0, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 0); +-- synthesis translate_on + +-- hds translate_on + +BEGIN + +-- hds translate_off + +-- synthesis translate_off +U0 : wrapped_dataRAM_64b_16b_width15 + port map ( + clka => clka, + dina => dina, + addra => addra, + wea => wea, + clkb => clkb, + addrb => addrb, + doutb => doutb); +-- synthesis translate_on + + +-- hds translate_on + +END dataRAM_64b_16b_width15_a; + + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/dataRM_64b_16b_width14_dataRM_64b_16b_width14_a.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/dataRM_64b_16b_width14_dataRM_64b_16b_width14_a.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/dataRM_64b_16b_width14_dataRM_64b_16b_width14_a.vhd (revision 9841) @@ -0,0 +1,153 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file dataRM_64b_16b_width14.vhd when simulating +-- the core, dataRM_64b_16b_width14. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +-- hds interface_start +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; + +-- synthesis translate_on +-- +ENTITY dataRM_64b_16b_width14 IS + PORT( + clka : IN std_logic; + dina : IN std_logic_VECTOR (63 DOWNTO 0); + addra : IN std_logic_VECTOR (13 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + clkb : IN std_logic; + addrb : IN std_logic_VECTOR (15 DOWNTO 0); + doutb : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + +-- Declarations + +END dataRM_64b_16b_width14 ; +-- hds interface_end + +ARCHITECTURE dataRM_64b_16b_width14_a OF dataRM_64b_16b_width14 IS + +-- hds translate_off + +-- synthesis translate_off +component wrapped_dataRM_64b_16b_width14 + port ( + clka: IN std_logic; + dina: IN std_logic_VECTOR(63 downto 0); + addra: IN std_logic_VECTOR(13 downto 0); + wea: IN std_logic_VECTOR(0 downto 0); + clkb: IN std_logic; + addrb: IN std_logic_VECTOR(15 downto 0); + doutb: OUT std_logic_VECTOR(15 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_dataRM_64b_16b_width14 use entity XilinxCoreLib.blk_mem_gen_v2_8(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 1, + c_prim_type => 1, + c_sinita_val => "0", + c_read_width_b => 16, + c_family => "spartan3", + c_read_width_a => 64, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "READ_FIRST", + c_init_file_name => "no_coe_file_loaded", + c_write_mode_a => "READ_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 0, + c_xdevicefamily => "spartan3adsp", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 65536, + c_write_depth_a => 16384, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 14, + c_addrb_width => 16, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 16, + c_write_width_a => 64, + c_read_depth_b => 65536, + c_read_depth_a => 16384, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 0, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 0); +-- synthesis translate_on + +-- hds translate_on + +BEGIN + +-- hds translate_off + +-- synthesis translate_off +U0 : wrapped_dataRM_64b_16b_width14 + port map ( + clka => clka, + dina => dina, + addra => addra, + wea => wea, + clkb => clkb, + addrb => addrb, + doutb => doutb); +-- synthesis translate_on + + +-- hds translate_on + +END dataRM_64b_16b_width14_a; + + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/data_generator.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/data_generator.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/data_generator.vhd (revision 9841) @@ -0,0 +1,275 @@ +-- +-- VHDL Architecture FACT_FAD_lib.data_generator.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 14:36:14 10.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + +-- -- Uncomment the following library declaration if instantiating +-- -- any Xilinx primitives in this code. +-- library UNISIM; +-- use UNISIM.VComponents.all; + +entity data_generator is + generic( + RAM_ADDR_WIDTH : integer := 12 + ); + port( + clk : in std_logic; + data_out : out std_logic_vector (63 downto 0); + addr_out : out std_logic_vector (RAM_ADDR_WIDTH-1 downto 0); + write_ea : out std_logic_vector (0 downto 0) := "0"; + ram_start_addr : in std_logic_vector (RAM_ADDR_WIDTH-1 downto 0); + ram_write_ea : in std_logic; + ram_write_ready : out std_logic := '0'; + config_start_mm, config_start_cm, config_start_spi : out std_logic := '0'; + config_ready_mm, config_ready_cm, config_ready_spi : in std_logic; + config_started_mm, config_started_cm, config_started_spi : in std_logic; + roi_array : in roi_array_type; + roi_max : in roi_max_type; + sensor_array : in sensor_array_type; + sensor_ready : in std_logic; + dac_array : in dac_array_type; + package_length : in std_logic_vector (15 downto 0); + board_id : in std_logic_vector (3 downto 0); + crate_id : in std_logic_vector (1 downto 0); + trigger_id : in std_logic_vector (47 downto 0); + trigger : in std_logic; + s_trigger : in std_logic; + new_config : in std_logic; + config_started : out std_logic := '0'; + adc_data_array : in adc_data_array_type; + adc_oeb : out std_logic := '1'; + adc_otr : in std_logic_vector (3 downto 0); + drs_channel_id : out std_logic_vector (3 downto 0) := (others => '0'); + drs_dwrite : out std_logic := '1'; + drs_clk_en, drs_read_s_cell : out std_logic := '0'; + drs_read_s_cell_ready : in std_logic; + drs_s_cell_array : in drs_s_cell_array_type + ); +end data_generator ; + +architecture Behavioral of data_generator is + +type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES, + WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT, + WRITE_END_FLAG, WRITE_DATA_STOP, + WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING); + +signal state_generate : state_generate_type := INIT; +signal start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); + +signal data_cntr : integer range 0 to 1024 := 0; +signal evnt_cntr : std_logic_vector (31 downto 0) := (others => '0'); +signal addr_cntr : integer range 0 to RAM_SIZE_64B := 0; -- counts 64 bit words +signal channel_id : integer range 0 to 9 := 0; +signal adc_wait_cnt : integer range 0 to 7 := 0; + + +begin + + + generate_data : process (clk) + begin + if rising_edge (clk) then + + addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH); + + case state_generate is + when INIT => + state_generate <= CONFIG; + + when CONFIG => + config_started <= '1'; + -- config config manager + config_start_cm <= '1'; + if (config_started_cm = '1') then + state_generate <= CONFIG1; + end if; + when CONFIG1 => + if (config_ready_cm = '1') then + config_started <= '0'; + config_start_cm <= '0'; + config_start_mm <= '1'; + end if; + if (config_started_mm = '1') then + state_generate <= CONFIG2; + end if; + when CONFIG2 => + if (config_ready_mm = '1') then + config_start_mm <= '0'; + config_start_spi <= '1'; + end if; + if (config_started_spi = '1') then + state_generate <= CONFIG3; + end if; + when CONFIG3 => + if (config_ready_spi = '1') then + config_start_spi <= '0'; + state_generate <= WRITE_DATA_IDLE; + end if; + + when WRITE_DATA_IDLE => + if (new_config = '1') then + state_generate <= CONFIG; + end if; + if (ram_write_ea = '1' and (trigger = '1' or s_trigger = '1')) then + -- stop drs, dwrite low + drs_dwrite <= '0'; + -- start reading of drs stop cell + drs_read_s_cell <= '1'; + -- enable adc output + adc_oeb <= '0'; + start_addr <= ram_start_addr; + state_generate <= WRITE_HEADER; + evnt_cntr <= evnt_cntr + 1; + end if; + when WRITE_HEADER => + write_ea <= "1"; + data_out <= X"0000" & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01"; + addr_cntr <= addr_cntr + 3; + state_generate <= WRITE_BOARD_ID; + when WRITE_BOARD_ID => -- crate ID & board ID + data_out <= (63 downto 10 => '0') & crate_id & "1000" & board_id; + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_TEMPERATURES; + when WRITE_TEMPERATURES => -- temperatures + if (sensor_ready = '1') then + data_out <= conv_std_logic_vector (sensor_array (3), 16) + & conv_std_logic_vector (sensor_array (2), 16) + & conv_std_logic_vector (sensor_array (1), 16) + & conv_std_logic_vector (sensor_array (0), 16); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_DAC1; + end if; + + when WRITE_DAC1 => + data_out <= conv_std_logic_vector (dac_array (3), 16) + & conv_std_logic_vector (dac_array (2), 16) + & conv_std_logic_vector (dac_array (1), 16) + & conv_std_logic_vector (dac_array (0), 16); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_DAC2; + when WRITE_DAC2 => + data_out <= conv_std_logic_vector (dac_array (7), 16) + & conv_std_logic_vector (dac_array (6), 16) + & conv_std_logic_vector (dac_array (5), 16) + & conv_std_logic_vector (dac_array (4), 16); + addr_cntr <= addr_cntr + 1; + state_generate <= WAIT_FOR_STOP_CELL; + + when WAIT_FOR_STOP_CELL => + drs_read_s_cell <= '0'; + if (drs_read_s_cell_ready = '1') then + state_generate <= START_DRS_READING; + end if; + + when START_DRS_READING => + --drs channel number + drs_channel_id <= conv_std_logic_vector (channel_id, 4); + --starte drs-clocking + --adc_oeb <= '0'; -- nur für Emulator + drs_clk_en <= '1'; + adc_wait_cnt <= 0; + state_generate <= WRITE_CHANNEL_ID; + + when WRITE_CHANNEL_ID => -- write DRS and Channel IDs + data_out <= conv_std_logic_vector(0,10) & conv_std_logic_vector(3,2) & conv_std_logic_vector(channel_id,4) + & conv_std_logic_vector(0,10) & conv_std_logic_vector(2,2) & conv_std_logic_vector(channel_id,4) + & conv_std_logic_vector(0,10) & conv_std_logic_vector(1,2) & conv_std_logic_vector(channel_id,4) + & conv_std_logic_vector(0,10) & conv_std_logic_vector(0,2) & conv_std_logic_vector(channel_id,4); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_START_CELL; + when WRITE_START_CELL => -- write start cells + data_out <= "000000" & drs_s_cell_array (3) + & "000000" & drs_s_cell_array (2) + & "000000" & drs_s_cell_array (1) + & "000000" & drs_s_cell_array (0); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_ROI; + when WRITE_ROI => -- write ROI + data_out <= "00000" & conv_std_logic_vector (roi_array((3) * 9 + channel_id), 11) + & "00000" & conv_std_logic_vector (roi_array((2) * 9 + channel_id), 11) + & "00000" & conv_std_logic_vector (roi_array((1) * 9 + channel_id), 11) + & "00000" & conv_std_logic_vector (roi_array((0) * 9 + channel_id), 11); + addr_cntr <= addr_cntr + 1; + state_generate <= WAIT_FOR_ADC; + when WAIT_FOR_ADC => + -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + if (adc_wait_cnt < (4 + 3)) then -- anpassen!!!! -- 3 für Simulation, 4 für FPGA??? + adc_wait_cnt <= adc_wait_cnt + 1; + else + state_generate <= WRITE_ADC_DATA; + end if; + when WRITE_ADC_DATA => + if (data_cntr < roi_max (channel_id)) then + data_out <= "000" & adc_otr(3) & adc_data_array(3) + & "000" & adc_otr(2) & adc_data_array(2) + & "000" & adc_otr(1) & adc_data_array(1) + & "000" & adc_otr(0) & adc_data_array(0); +-- data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) +-- & "00010" & conv_std_logic_vector (data_cntr, 11) +-- & "00100" & conv_std_logic_vector (data_cntr, 11) +-- & "00110" & conv_std_logic_vector (data_cntr, 11) ; + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_ADC_DATA; + data_cntr <= data_cntr + 1; + else + drs_clk_en <= '0'; + --adc_oeb <= '1'; -- nur für Emulator + if (channel_id = 8) then + state_generate <= WRITE_EXTERNAL_TRIGGER; + adc_oeb <= '1'; + else + channel_id <= channel_id + 1; -- increment channel_id + state_generate <= START_DRS_READING; + data_cntr <= 0; + end if; + end if; + + + when WRITE_EXTERNAL_TRIGGER => -- external trigger ID + addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH); + data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16); + state_generate <= WRITE_INTERNAL_TRIGGER; + when WRITE_INTERNAL_TRIGGER => -- internal trigger ID + addr_out <= start_addr + conv_std_logic_vector(2, RAM_ADDR_WIDTH); + data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16); + state_generate <= WRITE_END_FLAG; + when WRITE_END_FLAG => + data_out <= (63 downto 32 => '0') & X"04FE" & X"4242"; + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_DATA_END; + when WRITE_DATA_END => + write_ea <= "0"; + ram_write_ready <= '1'; + state_generate <= WRITE_DATA_END_WAIT; + when WRITE_DATA_END_WAIT => + state_generate <= WRITE_DATA_STOP; + when WRITE_DATA_STOP => + drs_dwrite <= '1'; + data_cntr <= 0; + addr_cntr <= 0; + channel_id <= 0; + ram_write_ready <= '0'; + state_generate <= WRITE_DATA_IDLE; + + when others => + null; + + end case; -- state_generate + end if; -- rising_edge (clk) + end process generate_data; + +end Behavioral; + + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/data_generator.vhd.bak =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/data_generator.vhd.bak (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/data_generator.vhd.bak (revision 9841) @@ -0,0 +1,275 @@ +-- +-- VHDL Architecture FACT_FAD_lib.data_generator.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 14:36:14 10.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + +-- -- Uncomment the following library declaration if instantiating +-- -- any Xilinx primitives in this code. +-- library UNISIM; +-- use UNISIM.VComponents.all; + +entity data_generator is + generic( + RAM_ADDR_WIDTH : integer := 12 + ); + port( + clk : in std_logic; + data_out : out std_logic_vector (63 downto 0); + addr_out : out std_logic_vector (RAM_ADDR_WIDTH-1 downto 0); + write_ea : out std_logic_vector (0 downto 0) := "0"; + ram_start_addr : in std_logic_vector (RAM_ADDR_WIDTH-1 downto 0); + ram_write_ea : in std_logic; + ram_write_ready : out std_logic := '0'; + config_start_mm, config_start_cm, config_start_spi : out std_logic := '0'; + config_ready_mm, config_ready_cm, config_ready_spi : in std_logic; + config_started_mm, config_started_cm, config_started_spi : in std_logic; + roi_array : in roi_array_type; + roi_max : in roi_max_type; + sensor_array : in sensor_array_type; + sensor_ready : in std_logic; + dac_array : in dac_array_type; + package_length : in std_logic_vector (15 downto 0); + board_id : in std_logic_vector (3 downto 0); + crate_id : in std_logic_vector (1 downto 0); + trigger_id : in std_logic_vector (47 downto 0); + trigger : in std_logic; + s_trigger : in std_logic; + new_config : in std_logic; + config_started : out std_logic := '0'; + adc_data_array : in adc_data_array_type; + adc_oeb : out std_logic := '1'; + adc_otr : in std_logic_vector (3 downto 0); + drs_channel_id : out std_logic_vector (3 downto 0) := (others => '0'); + drs_dwrite : out std_logic := '1'; + drs_clk_en, drs_read_s_cell : out std_logic := '0'; + drs_read_s_cell_ready : in std_logic; + drs_s_cell_array : in drs_s_cell_array_type + ); +end data_generator ; + +architecture Behavioral of data_generator is + +type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES, + WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT, + WRITE_END_FLAG, WRITE_DATA_STOP, + WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING); + +signal state_generate : state_generate_type := INIT; +signal start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); + +signal data_cntr : integer range 0 to 1024 := 0; +signal evnt_cntr : std_logic_vector (31 downto 0) := (others => '0'); +signal addr_cntr : integer range 0 to RAM_SIZE_64B := 0; -- counts 64 bit words +signal channel_id : integer range 0 to 9 := 0; +signal adc_wait_cnt : integer range 0 to 7 := 0; + + +begin + + + generate_data : process (clk) + begin + if rising_edge (clk) then + + addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH); + + case state_generate is + when INIT => + state_generate <= CONFIG; + + when CONFIG => + config_started <= '1'; + -- config config manager + config_start_cm <= '1'; + if (config_started_cm = '1') then + state_generate <= CONFIG1; + end if; + when CONFIG1 => + if (config_ready_cm = '1') then + config_started <= '0'; + config_start_cm <= '0'; + config_start_mm <= '1'; + end if; + if (config_started_mm = '1') then + state_generate <= CONFIG2; + end if; + when CONFIG2 => + if (config_ready_mm = '1') then + config_start_mm <= '0'; + config_start_spi <= '1'; + end if; + if (config_started_spi = '1') then + state_generate <= CONFIG3; + end if; + when CONFIG3 => + if (config_ready_spi = '1') then + config_start_spi <= '0'; + state_generate <= WRITE_DATA_IDLE; + end if; + + when WRITE_DATA_IDLE => + if (new_config = '1') then + state_generate <= CONFIG; + end if; + if (ram_write_ea = '1' and (trigger = '1' or s_trigger = '1')) then + -- stop drs, dwrite low + drs_dwrite <= '0'; + -- start reading of drs stop cell + drs_read_s_cell <= '1'; + -- enable adc output + adc_oeb <= '0'; + start_addr <= ram_start_addr; + state_generate <= WRITE_HEADER; + evnt_cntr <= evnt_cntr + 1; + end if; + when WRITE_HEADER => + write_ea <= "1"; + data_out <= X"0000" & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01"; + addr_cntr <= addr_cntr + 3; + state_generate <= WRITE_BOARD_ID; + when WRITE_BOARD_ID => -- crate ID & board ID + data_out <= (63 downto 10 => '0') & crate_id & "1000" & board_id; + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_TEMPERATURES; + when WRITE_TEMPERATURES => -- temperatures + if (sensor_ready = '1') then + data_out <= conv_std_logic_vector (sensor_array (3), 16) + & conv_std_logic_vector (sensor_array (2), 16) + & conv_std_logic_vector (sensor_array (1), 16) + & conv_std_logic_vector (sensor_array (0), 16); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_DAC1; + end if; + + when WRITE_DAC1 => + data_out <= conv_std_logic_vector (dac_array (3), 16) + & conv_std_logic_vector (dac_array (2), 16) + & conv_std_logic_vector (dac_array (1), 16) + & conv_std_logic_vector (dac_array (0), 16); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_DAC2; + when WRITE_DAC2 => + data_out <= conv_std_logic_vector (dac_array (7), 16) + & conv_std_logic_vector (dac_array (6), 16) + & conv_std_logic_vector (dac_array (5), 16) + & conv_std_logic_vector (dac_array (4), 16); + addr_cntr <= addr_cntr + 1; + state_generate <= WAIT_FOR_STOP_CELL; + + when WAIT_FOR_STOP_CELL => + drs_read_s_cell <= '0'; + if (drs_read_s_cell_ready = '1') then + state_generate <= START_DRS_READING; + end if; + + when START_DRS_READING => + --drs channel number + drs_channel_id <= conv_std_logic_vector (channel_id, 4); + --starte drs-clocking + --adc_oeb <= '0'; -- nur für Emulator + drs_clk_en <= '1'; + adc_wait_cnt <= 0; + state_generate <= WRITE_CHANNEL_ID; + + when WRITE_CHANNEL_ID => -- write DRS and Channel IDs + data_out <= conv_std_logic_vector(0,10) & conv_std_logic_vector(3,2) & conv_std_logic_vector(channel_id,4) + & conv_std_logic_vector(0,10) & conv_std_logic_vector(2,2) & conv_std_logic_vector(channel_id,4) + & conv_std_logic_vector(0,10) & conv_std_logic_vector(1,2) & conv_std_logic_vector(channel_id,4) + & conv_std_logic_vector(0,10) & conv_std_logic_vector(0,2) & conv_std_logic_vector(channel_id,4); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_START_CELL; + when WRITE_START_CELL => -- write start cells + data_out <= "000000" & drs_s_cell_array (3) + & "000000" & drs_s_cell_array (2) + & "000000" & drs_s_cell_array (1) + & "000000" & drs_s_cell_array (0); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_ROI; + when WRITE_ROI => -- write ROI + data_out <= "00000" & conv_std_logic_vector (roi_array((3) * 9 + channel_id), 11) + & "00000" & conv_std_logic_vector (roi_array((2) * 9 + channel_id), 11) + & "00000" & conv_std_logic_vector (roi_array((1) * 9 + channel_id), 11) + & "00000" & conv_std_logic_vector (roi_array((0) * 9 + channel_id), 11); + addr_cntr <= addr_cntr + 1; + state_generate <= WAIT_FOR_ADC; + when WAIT_FOR_ADC => + -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + if (adc_wait_cnt < (4 + 3)) then -- anpassen!!!! -- 3 für Simulation, 4 für FPGA??? + adc_wait_cnt <= adc_wait_cnt + 1; + else + state_generate <= WRITE_ADC_DATA; + end if; + when WRITE_ADC_DATA => + if (data_cntr < roi_max (channel_id)) then +-- data_out <= "000" & adc_otr(3) & adc_data_array(3) +-- & "000" & adc_otr(2) & adc_data_array(2) +-- & "000" & adc_otr(1) & adc_data_array(1) +-- & "000" & adc_otr(0) & adc_data_array(0); + data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) + & "00010" & conv_std_logic_vector (data_cntr, 11) + & "00100" & conv_std_logic_vector (data_cntr, 11) + & "00110" & conv_std_logic_vector (data_cntr, 11) ; + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_ADC_DATA; + data_cntr <= data_cntr + 1; + else + drs_clk_en <= '0'; + --adc_oeb <= '1'; -- nur für Emulator + if (channel_id = 8) then + state_generate <= WRITE_EXTERNAL_TRIGGER; + adc_oeb <= '1'; + else + channel_id <= channel_id + 1; -- increment channel_id + state_generate <= START_DRS_READING; + data_cntr <= 0; + end if; + end if; + + + when WRITE_EXTERNAL_TRIGGER => -- external trigger ID + addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH); + data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16); + state_generate <= WRITE_INTERNAL_TRIGGER; + when WRITE_INTERNAL_TRIGGER => -- internal trigger ID + addr_out <= start_addr + conv_std_logic_vector(2, RAM_ADDR_WIDTH); + data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16); + state_generate <= WRITE_END_FLAG; + when WRITE_END_FLAG => + data_out <= (63 downto 32 => '0') & X"04FE" & X"4242"; + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_DATA_END; + when WRITE_DATA_END => + write_ea <= "0"; + ram_write_ready <= '1'; + state_generate <= WRITE_DATA_END_WAIT; + when WRITE_DATA_END_WAIT => + state_generate <= WRITE_DATA_STOP; + when WRITE_DATA_STOP => + drs_dwrite <= '1'; + data_cntr <= 0; + addr_cntr <= 0; + channel_id <= 0; + ram_write_ready <= '0'; + state_generate <= WRITE_DATA_IDLE; + + when others => + null; + + end case; -- state_generate + end if; -- rising_edge (clk) + end process generate_data; + +end Behavioral; + + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/dcm_50_to_25_BEHAVIORAL.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/dcm_50_to_25_BEHAVIORAL.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/dcm_50_to_25_BEHAVIORAL.vhd (revision 9841) @@ -0,0 +1,189 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 10.1.03 +-- \ \ Application : xaw2vhdl +-- / / Filename : dcm_50_to_25.vhd +-- /___/ /\ Timestamp : 04/19/2010 15:54:44 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st C:/DOKUME~1/kai/LOKALE~1/Temp/coregen_kai/coregen/project/dcm_50_to_25.xaw C:/DOKUME~1/kai/LOKALE~1/Temp/coregen_kai/coregen/project/dcm_50_to_25 +--Design Name: dcm_50_to_25 +--Device: xc3s50a-5tq144 +-- +-- Module dcm_50_to_25 +-- Written for synthesis tool: Precision + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity dcm_50_to_25 is + port ( CLKIN_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic); +end dcm_50_to_25; + +architecture BEHAVIORAL of dcm_50_to_25 is + +-- hds translate_off + + attribute CLK_FEEDBACK : string ; + attribute CLKDV_DIVIDE : string ; + attribute CLKFX_DIVIDE : string ; + attribute CLKFX_MULTIPLY : string ; + attribute CLKIN_DIVIDE_BY_2 : string ; + attribute CLKIN_PERIOD : string ; + attribute CLKOUT_PHASE_SHIFT : string ; + attribute DESKEW_ADJUST : string ; + attribute DFS_FREQUENCY_MODE : string ; + attribute DLL_FREQUENCY_MODE : string ; + attribute DUTY_CYCLE_CORRECTION : string ; + attribute FACTORY_JF : string ; + attribute PHASE_SHIFT : string ; + attribute STARTUP_WAIT : string ; + signal CLKFB_IN : std_logic; + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; + component BUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + component IBUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + -- Period Jitter (unit interval) for block DCM_SP_INST = 0.02 UI + -- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.18 ns + component DCM_SP + -- pragma synthesis_off + generic( CLK_FEEDBACK : string := "1X"; + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := FALSE; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DUTY_CYCLE_CORRECTION : boolean := TRUE; + FACTORY_JF : bit_vector := x"C080"; + PHASE_SHIFT : integer := 0; + STARTUP_WAIT : boolean := FALSE; + DSS_MODE : string := "NONE"); + -- pragma synthesis_on + port ( CLKIN : in std_logic; + CLKFB : in std_logic; + RST : in std_logic; + PSEN : in std_logic; + PSINCDEC : in std_logic; + PSCLK : in std_logic; + DSSEN : in std_logic; + CLK0 : out std_logic; + CLK90 : out std_logic; + CLK180 : out std_logic; + CLK270 : out std_logic; + CLKDV : out std_logic; + CLK2X : out std_logic; + CLK2X180 : out std_logic; + CLKFX : out std_logic; + CLKFX180 : out std_logic; + STATUS : out std_logic_vector (7 downto 0); + LOCKED : out std_logic; + PSDONE : out std_logic); + end component; + + attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X"; + attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0"; + attribute CLKFX_DIVIDE of DCM_SP_INST : label is "5"; + attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "2"; + attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE"; + attribute CLKIN_PERIOD of DCM_SP_INST : label is "20.000"; + attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "NONE"; + attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS"; + attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; + attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; + attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE"; + attribute FACTORY_JF of DCM_SP_INST : label is "C080"; + attribute PHASE_SHIFT of DCM_SP_INST : label is "0"; + attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE"; + +-- hds translate_on + +begin + +-- hds translate_off + + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLK0_OUT <= CLKFB_IN; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + -- pragma synthesis_off + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 5, + CLKFX_MULTIPLY => 2, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + -- pragma synthesis_on + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>GND_BIT, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>open, + PSDONE=>open, + STATUS=>open); + + +-- hds translate_on + +end BEHAVIORAL; + + + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/dcm_ps_38ns_BEHAVIORAL.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/dcm_ps_38ns_BEHAVIORAL.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/dcm_ps_38ns_BEHAVIORAL.vhd (revision 9841) @@ -0,0 +1,169 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 10.1.03 +-- \ \ Application : xaw2vhdl +-- / / Filename : dcm_ps_38ns.vhd +-- /___/ /\ Timestamp : 04/19/2010 15:55:48 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st C:/DOKUME~1/kai/LOKALE~1/Temp/coregen_kai/coregen/project/dcm_ps_38ns.xaw C:/DOKUME~1/kai/LOKALE~1/Temp/coregen_kai/coregen/project/dcm_ps_38ns +--Design Name: dcm_ps_38ns +--Device: xc3s50a-5tq144 +-- +-- Module dcm_ps_38ns +-- Written for synthesis tool: Precision + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity dcm_ps_38ns is + port ( CLKIN_IN : in std_logic; + CLK0_OUT : out std_logic); +end dcm_ps_38ns; + +architecture BEHAVIORAL of dcm_ps_38ns is + +-- hds translate_off + + attribute CLK_FEEDBACK : string ; + attribute CLKDV_DIVIDE : string ; + attribute CLKFX_DIVIDE : string ; + attribute CLKFX_MULTIPLY : string ; + attribute CLKIN_DIVIDE_BY_2 : string ; + attribute CLKIN_PERIOD : string ; + attribute CLKOUT_PHASE_SHIFT : string ; + attribute DESKEW_ADJUST : string ; + attribute DFS_FREQUENCY_MODE : string ; + attribute DLL_FREQUENCY_MODE : string ; + attribute DUTY_CYCLE_CORRECTION : string ; + attribute FACTORY_JF : string ; + attribute PHASE_SHIFT : string ; + attribute STARTUP_WAIT : string ; + signal CLKFB_IN : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; + component BUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + component DCM_SP + -- pragma synthesis_off + generic( CLK_FEEDBACK : string := "1X"; + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := FALSE; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DUTY_CYCLE_CORRECTION : boolean := TRUE; + FACTORY_JF : bit_vector := x"C080"; + PHASE_SHIFT : integer := 0; + STARTUP_WAIT : boolean := FALSE; + DSS_MODE : string := "NONE"); + -- pragma synthesis_on + port ( CLKIN : in std_logic; + CLKFB : in std_logic; + RST : in std_logic; + PSEN : in std_logic; + PSINCDEC : in std_logic; + PSCLK : in std_logic; + DSSEN : in std_logic; + CLK0 : out std_logic; + CLK90 : out std_logic; + CLK180 : out std_logic; + CLK270 : out std_logic; + CLKDV : out std_logic; + CLK2X : out std_logic; + CLK2X180 : out std_logic; + CLKFX : out std_logic; + CLKFX180 : out std_logic; + STATUS : out std_logic_vector (7 downto 0); + LOCKED : out std_logic; + PSDONE : out std_logic); + end component; + + attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X"; + attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0"; + attribute CLKFX_DIVIDE of DCM_SP_INST : label is "1"; + attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "4"; + attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE"; + attribute CLKIN_PERIOD of DCM_SP_INST : label is "50.000"; + attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "FIXED"; + attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS"; + attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; + attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; + attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE"; + attribute FACTORY_JF of DCM_SP_INST : label is "C080"; + attribute PHASE_SHIFT of DCM_SP_INST : label is "195"; + attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE"; + +-- hds translate_on + +begin + +-- hds translate_off + + GND_BIT <= '0'; + CLK0_OUT <= CLKFB_IN; + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + -- pragma synthesis_off + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 4, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 50.000, + CLKOUT_PHASE_SHIFT => "FIXED", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 195, + STARTUP_WAIT => FALSE) + -- pragma synthesis_on + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IN, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>GND_BIT, + CLKDV=>open, + CLKFX=>open, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>open, + PSDONE=>open, + STATUS=>open); + + +-- hds translate_on + +end BEHAVIORAL; + + + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/debouncer.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/debouncer.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/debouncer.vhd (revision 9841) @@ -0,0 +1,106 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:42:35 01/08/2010 +-- Design Name: +-- Module Name: debouncer - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +-- hds interface_start +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +-- -- Uncomment the following library declaration if instantiating +-- -- any Xilinx primitives in this code. +-- library UNISIM; +-- use UNISIM.VComponents.all; +-- +ENTITY debouncer IS + GENERIC( + WIDTH : INTEGER := 17 + ); + PORT( + clk : IN STD_LOGIC; + -- rst : in STD_LOGIC; + trigger_in : IN STD_LOGIC; + trigger_out : OUT STD_LOGIC := '0' + ); + +-- Declarations + +END debouncer ; +-- hds interface_end + +architecture Behavioral of debouncer is + + signal counter : STD_LOGIC_VECTOR(WIDTH-1 downto 0) := (others => '0'); + signal int_trigger : std_logic := '0'; + signal temp_trig : std_logic_vector(1 downto 0) := "00"; + signal trigger_flag : std_logic := '0'; + signal temp_signal : std_logic := '0'; + +begin + + debounce_proc: process (clk) + begin +-- if (rst = '1') then +-- counter <= (others => '0'); +-- trigger_out <= '0'; +-- elsif rising_edge(clk) then + if rising_edge(clk) then + if (trigger_in = '1') then + if (unsigned(counter) = 2**WIDTH-1) then + int_trigger <= '1'; + counter <= (others => '1'); + else + counter <= std_logic_vector(unsigned(counter) + to_unsigned(1,WIDTH)); + end if; + else + if (unsigned(counter) = 0) then + int_trigger <= '0'; + counter <= (others => '0'); + else + counter <= std_logic_vector(unsigned(counter) - to_unsigned(1,WIDTH)); + end if; + end if; + end if; + end process debounce_proc; + + shaping_proc : process (clk) + begin +-- if (rst = '1') then +-- trigger_out <= '0'; +-- trigger_flag <= '0'; +-- temp_signal <= '0'; +-- elsif rising_edge(clk) then + if rising_edge(clk) then +-- temp_trig <= temp_trig(2 downto 0) & trigger_in; +-- trigger_out <= not temp_trig(3) and temp_trig(2); + temp_trig <= temp_trig(0) & int_trigger; + temp_signal <= not temp_trig(1) and temp_trig(0); + trigger_out <= temp_signal and not trigger_flag; + if (int_trigger = '0') then + trigger_flag <= '0'; + end if; + if (temp_signal = '1') then + trigger_flag <= '1'; + end if; + end if; + end process shaping_proc; + + +end Behavioral; + + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/drs_pulser.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/drs_pulser.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/drs_pulser.vhd (revision 9841) @@ -0,0 +1,251 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.std_logic_signed.all; + +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + + +ENTITY drs_pulser is + port ( + -- input CLK; RSRLOAD and SRCLK are derived from this signal + CLK : in std_logic; + -- async reset; + reset : in std_logic; + + start_endless_mode : in std_logic; + start_read_stop_pos_mode : in std_logic; + + SROUT_in_0 : in std_logic; + SROUT_in_1 : in std_logic; + SROUT_in_2 : in std_logic; + SROUT_in_3 : in std_logic; + +-- stop_pos_0 : out std_logic_vector(9 downto 0); +-- stop_pos_1 : out std_logic_vector(9 downto 0); +-- stop_pos_2 : out std_logic_vector(9 downto 0); +-- stop_pos_3 : out std_logic_vector(9 downto 0); + stop_pos : out drs_s_cell_array_type; + stop_pos_valid : out std_logic; + + RSRLOAD : out std_logic; + SRCLK : out std_logic; + busy :out std_logic + ); +end drs_pulser; + + +ARCHITECTURE behavior of drs_pulser IS + +type states is (idle, started_endless, started_read_stop_pos , waiting_e, waiting_r, running_e, running_r); +signal current_state : states := idle; +signal next_state : states := idle; +signal CEN,LEN : std_logic; + + +signal local_roi : std_logic_vector (9 downto 0):= (others => '0'); + +signal flag_read_stop_pos : std_logic := '0'; + +signal cell_cntr : std_logic_vector (9 downto 0); +signal cc_en : std_logic; +signal cc_reset : std_logic; + +signal wait_cntr : std_logic_vector (2 downto 0); +signal wc_en : std_logic; +signal wc_reset : std_logic; + +signal int_stop_pos_0 : std_logic_vector(9 downto 0) := (others => '0'); +signal int_stop_pos_1 : std_logic_vector(9 downto 0) := (others => '0'); +signal int_stop_pos_2 : std_logic_vector(9 downto 0) := (others => '0'); +signal int_stop_pos_3 : std_logic_vector(9 downto 0) := (others => '0'); + +begin + RSRLOAD <= (LEN and CLK); + SRCLK <= (CEN and CLK); + stop_pos(0) <= int_stop_pos_0; + stop_pos(1) <= int_stop_pos_1; + stop_pos(2) <= int_stop_pos_2; + stop_pos(3) <= int_stop_pos_3; + + + + state_register: process(clk, reset) + begin + IF reset = '1' THEN + current_state <= idle ; + ELSIF clk = '0' and clk'event THEN -- ! falling edge ! + current_state <= next_state ; + END IF; + end process state_register; + + --Folgezustandsberechnung asynchron + transition: process(current_state, + start_endless_mode, + start_read_stop_pos_mode, + wait_cntr, + cell_cntr, + local_roi) + begin + CASE current_state IS + WHEN idle => + if start_endless_mode = '1' then + next_state <= started_endless ; + elsif start_read_stop_pos_mode = '1' then + next_state <= started_read_stop_pos ; + end if; + + WHEN started_endless => + if cell_cntr = conv_std_logic_vector(1,10) then + next_state <= waiting_e; + end if; + + + + WHEN started_read_stop_pos => + if cell_cntr = conv_std_logic_vector(1,10) then + next_state <= waiting_r; + end if; + + WHEN waiting_e => + if wait_cntr = conv_std_logic_vector(0,3) then + next_state <= running_e; + else + next_state <= waiting_e; + end if; + + WHEN waiting_r => + if wait_cntr = conv_std_logic_vector(0,3) then + next_state <= running_r; + end if; + + + WHEN running_e => + IF (start_endless_mode = '0') THEN + next_state <= idle; + END IF; + + WHEN running_r => + if cell_cntr >= local_roi THEN + next_state <= idle; + end if; + END CASE; + end process transition; + + output_proc: process(current_state) --Ausgangsberechnung synchron, da current_state sich nur synchron aendert + begin + case current_state is + + when idle => + local_roi <= (others => '0'); + flag_read_stop_pos <= '0'; + stop_pos_valid <= '1'; + LEN <= '0'; CEN <= '0'; + busy <= '0'; + cc_en <= '0'; cc_reset <= '1'; + wc_en <= '0'; wc_reset <= '0'; + + when started_endless => + local_roi <= "0111111111"; + flag_read_stop_pos <= '0'; + stop_pos_valid <= '0'; + LEN <= '1'; CEN <= '0'; + busy <= '1'; + cc_en <= '1'; cc_reset <= '0'; + wc_en <= '0'; wc_reset <= '1'; + + when started_read_stop_pos => + local_roi <= conv_std_logic_vector(11,10); + flag_read_stop_pos <= '1'; + stop_pos_valid <= '0'; + LEN <= '1'; CEN <= '0'; + busy <= '1'; + cc_en <= '1'; cc_reset <= '0'; + wc_en <= '0'; wc_reset <= '1'; + + when waiting_e | waiting_r => + local_roi <= local_roi; + stop_pos_valid <= '0'; + busy <= '1'; + LEN <= '0'; CEN <= '0'; + cc_en <= '0'; cc_reset <= '0'; + wc_en <= '1'; wc_reset <= '0'; + + when running_e => + flag_read_stop_pos <= '0'; + stop_pos_valid <= '0'; + LEN <= '0'; CEN <= '1'; + cc_en <= '1'; cc_reset <= '0'; + wc_en <= '0'; wc_reset <= '0'; + busy <= '1'; + + when running_r => + flag_read_stop_pos <= '1'; + stop_pos_valid <= '0'; + LEN <= '0'; CEN <= '1'; + cc_en <= '1'; cc_reset <= '0'; + wc_en <= '0'; wc_reset <= '0'; + busy <= '1'; + end case; + end process output_proc; + + + cellcounter: process (clk, cc_reset) begin + + if (cc_reset = '1') then + cell_cntr <= (others=>'0'); + elsif (rising_edge(clk)) then + if (cc_en = '1') then + cell_cntr <= cell_cntr + 1; + end if; + end if; + + end process cellcounter; + + + waitcounter: process (clk, wc_reset) begin + if (wc_reset = '1') then + wait_cntr <= "011"; -- RSRLOAD -> warte 3 -> SRCLK + elsif (rising_edge(clk)) then + if (wc_en = '1') then + wait_cntr <= wait_cntr - 1; + end if; + end if; + end process waitcounter; + + -- laut DRS4_rev09.pdf Seite 13 Figure 15 + -- funktioniert das auslesen der Stop bzw. Startadresse so: + -- Sende 1x RSRLOAD- und mind. 9 SRCLK- pulse und sample SROUT zur + -- steigenden Flanke von SRCLK. + -- MSB first LSB last, kommen dann die 10 bits, + -- die die Stopposition darstellen. + -- + -- diese Architecture liefert immer dann eine steigende Flanke + -- auf RSRCLK, wenn CLK eine steigende Flanke hat und CEN='1' ist. + -- Die an SROUT zur steigenden Flanke anliegenden Werte werden wie in einem Schieberegister + -- Schritt fuer Schritt in die stop_pos_x vectoren geschoben. + -- + -- wenn sie 10 schritte weit reingschoben wurden, ist der process fertig. + -- es gibt keinen eigenen counter fuer die 10 schritte, der cell counter kann hier + -- missbraucht werden. + -- + -- da der process eine steigende flanke auf SRCLK braucht um SROUT zu sampeln + -- wird im Prinzip ein Puls aud SRCLK *zuviel* erzeugt, das ist aber egal... + -- + stop_pos_reader: process (CEN, clk, flag_read_stop_pos) + begin + IF (flag_read_stop_pos = '1') THEN -- nur wenn ich im read_stop_mode bin, laeuft dieser process + IF (CEN = '1') THEN -- nur wenn CEN='1' ist kommen SRCLK pulse raus. + IF (rising_edge(CLK)) THEN -- wenn steigende Flanke, dann SROUT samplen. + int_stop_pos_0 <= int_stop_pos_0(8 downto 0) & SROUT_in_0; + int_stop_pos_1 <= int_stop_pos_1(8 downto 0) & SROUT_in_1; + int_stop_pos_2 <= int_stop_pos_2(8 downto 0) & SROUT_in_2; + int_stop_pos_3 <= int_stop_pos_3(8 downto 0) & SROUT_in_3; + + END IF; -- rising edge CLK + END IF; -- CEN ='1' + END IF; -- flag_read_stop_pos = '1' + end process stop_pos_reader; + +end behavior; Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd (revision 9841) @@ -0,0 +1,99 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.std_logic_signed.all; + +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + + +ENTITY drs_pulser is + port ( + CLK : in std_logic; + + start_endless_mode : in std_logic; + start_read_stop_pos_mode : in std_logic; + + SROUT_in_0 : in std_logic; + SROUT_in_1 : in std_logic; + SROUT_in_2 : in std_logic; + SROUT_in_3 : in std_logic; + + stop_pos : out drs_s_cell_array_type; + stop_pos_valid : out std_logic := '0'; + + RSRLOAD : out std_logic := '0'; + SRCLK : out std_logic := '0' + ); +end drs_pulser; + + +ARCHITECTURE behavior of drs_pulser IS + +type state_main_type is (MAIN, READ_STOP_POS, ENDLESS_MODE); +signal state_main : state_main_type := MAIN; +signal stop_pos_cntr, wait_cntr : integer range 0 to 31 := 0; + +signal stop_pos_int : drs_s_cell_array_type; +signal RSRLOAD_EN, SRCLK_EN : std_logic := '0'; + +begin + + + main_proc: process (clk) begin + + RSRLOAD <= (clk and RSRLOAD_EN); + SRCLK <= (clk and SRCLK_EN); + + if rising_edge(clk) then + case state_main is + when MAIN => + if (start_read_stop_pos_mode = '1') then + RSRLOAD_EN <= '1'; + stop_pos_valid <= '0'; + state_main <= READ_STOP_POS; + end if; + if (start_endless_mode = '1') then + RSRLOAD_EN <= '1'; + state_main <= ENDLESS_MODE; + end if; + + when ENDLESS_MODE => + RSRLOAD_EN <= '0'; + if (wait_cntr = 3) then + SRCLK_EN <= '1'; + else + wait_cntr <= wait_cntr + 1; + end if; + if (start_endless_mode = '0') then + SRCLK_EN <= '0'; + wait_cntr <= 0; + state_main <= MAIN; + end if; + + when READ_STOP_POS => + RSRLOAD_EN <= '0'; + if (stop_pos_cntr = 10) then + stop_pos (0) <= stop_pos_int (0); + stop_pos (1) <= stop_pos_int (1); + stop_pos (2) <= stop_pos_int (2); + stop_pos (3) <= stop_pos_int (3); + stop_pos_valid <= '1'; + stop_pos_cntr <= 0; + SRCLK_EN <= '0'; + state_main <= MAIN; + else + SRCLK_EN <= '1'; + stop_pos_int (0) <= stop_pos_int (0) (8 downto 0) & SROUT_in_0; + stop_pos_int (1) <= stop_pos_int (1) (8 downto 0) & SROUT_in_1; + stop_pos_int (2) <= stop_pos_int (2) (8 downto 0) & SROUT_in_2; + stop_pos_int (3) <= stop_pos_int (3) (8 downto 0) & SROUT_in_3; + stop_pos_cntr <= stop_pos_cntr + 1; + end if; + + end case; -- state_main + end if; + + end process main_proc; + +end behavior; Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board.ucf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board.ucf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board.ucf (revision 9841) @@ -0,0 +1,259 @@ +########################################################### +# Pin location constraints +########################################################### + +#CLOCK +NET X_50M LOC = AF13 | IOSTANDARD=LVCMOS33; #ok + +## single ended trigger input +NET TRG LOC = AC8 | IOSTANDARD=LVCMOS33; #ok + +#Test Trigger input on 'Testpoint near W5300' +#NET _TW<3> LOC = R19 | IOSTANDARD=LVCMOS33; #ok +NET TEST_TRG LOC = R19 | IOSTANDARD=LVCMOS33; + + + +## trigger veto: xilinx output +NET TRG_V LOC = AC9 | IOSTANDARD=LVCMOS33; #ok +## NET INIT_B LOC = AA15 | IOSTANDARD=LVCMOS33; #ok + + + +# RS485 Driver + +NET RS485_C_DE LOC = C5 | IOSTANDARD=LVCMOS33; #ok +NET RS485_C_RE LOC = C6 | IOSTANDARD=LVCMOS33; #ok +#NET RS485_C_DO LOC = C7 | IOSTANDARD=LVCMOS33; #ok +#NET RS485_C_DI LOC = C8 | IOSTANDARD=LVCMOS33; #ok + +NET RS485_E_DE LOC = D20 | IOSTANDARD=LVCMOS33; #ok +NET RS485_E_RE LOC = D21 | IOSTANDARD=LVCMOS33; #ok +#NET RS485_E_DO LOC = D22 | IOSTANDARD=LVCMOS33; #ok +#NET RS485_E_DI LOC = D23 | IOSTANDARD=LVCMOS33; #ok + + +# BOARD ID - inputs +#NET LINE<0> LOC = Y1 | IOSTANDARD=LVCMOS33; #ok +#NET LINE<1> LOC = Y2 | IOSTANDARD=LVCMOS33; #ok +#NET LINE<2> LOC = AB1 | IOSTANDARD=LVCMOS33; #ok +#NET LINE<3> LOC = AC1 | IOSTANDARD=LVCMOS33; #ok +#NET LINE<4> LOC = AD1 | IOSTANDARD=LVCMOS33; #ok +#NET LINE<5> LOC = AD2 | IOSTANDARD=LVCMOS33; #ok + +# W5300 +####################################################### +NET W_D<15> LOC = D24 | IOSTANDARD=LVCMOS33; #ok +NET W_D<14> LOC = D25 | IOSTANDARD=LVCMOS33; #ok +NET W_D<13> LOC = D26 | IOSTANDARD=LVCMOS33; #ok +NET W_D<12> LOC = E24 | IOSTANDARD=LVCMOS33; #ok +NET W_D<11> LOC = E26 | IOSTANDARD=LVCMOS33; #ok +NET W_D<10> LOC = F25 | IOSTANDARD=LVCMOS33; #ok +NET W_D<9> LOC = F24 | IOSTANDARD=LVCMOS33; #ok +NET W_D<8> LOC = G23 | IOSTANDARD=LVCMOS33; #ok +NET W_D<7> LOC = G24 | IOSTANDARD=LVCMOS33; #ok +NET W_D<6> LOC = J23 | IOSTANDARD=LVCMOS33; #ok +NET W_D<5> LOC = K25 | IOSTANDARD=LVCMOS33; #ok +NET W_D<4> LOC = K26 | IOSTANDARD=LVCMOS33; #ok +NET W_D<3> LOC = J22 | IOSTANDARD=LVCMOS33; #ok +NET W_D<2> LOC = K23 | IOSTANDARD=LVCMOS33; #ok +NET W_D<1> LOC = L22 | IOSTANDARD=LVCMOS33; #ok +NET W_D<0> LOC = M22 | IOSTANDARD=LVCMOS33; #ok + +NET W_A<9> LOC = V24 | IOSTANDARD=LVCMOS33; #ok +NET W_A<8> LOC = V25 | IOSTANDARD=LVCMOS33; #ok +NET W_A<7> LOC = W23 | IOSTANDARD=LVCMOS33; #ok +NET W_A<6> LOC = Y23 | IOSTANDARD=LVCMOS33; #ok +NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; #ok +NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; #ok +NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; #ok +NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; #ok +NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; #ok +NET W_A<0> LOC = Y22 | IOSTANDARD=LVCMOS33; #ok DUMMY + +NET W_WR LOC = P22 | IOSTANDARD=LVCMOS33; #ok +NET W_RD LOC = R20 | IOSTANDARD=LVCMOS33; #ok +NET W_CS LOC = T20 | IOSTANDARD=LVCMOS33; #ok +NET W_INT LOC = U22 | IOSTANDARD=LVCMOS33; #ok +NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; #ok + +#NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; #ok +#NET W_BRDY<2> LOC = AC26 | IOSTANDARD=LVCMOS33; #ok +#NET W_BRDY<1> LOC = AC25 | IOSTANDARD=LVCMOS33; #ok +#NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; #ok +# Testpoint near W5300 +#NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; #ok +#NET W_T<2> LOC = N21 | IOSTANDARD=LVCMOS33; #ok +#NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; #ok +#NET W_T<0> LOC = K21 | IOSTANDARD=LVCMOS33; #ok + +# Platform Flash - serial connection +####################################################### +##NET FL_CLK LOC = AE24 | IOSTANDARD=LVCMOS33; #ok +##NET FL_D0 LOC = AF24 | IOSTANDARD=LVCMOS33; #ok + +# DRS Signals +####################################################### +NET DENABLE LOC = B1 | IOSTANDARD=LVCMOS25; #ok +NET DWRITE LOC = R2 | IOSTANDARD=LVCMOS25; #ok + +NET SRIN LOC = E1 | IOSTANDARD=LVCMOS25; #ok -- nur fuer vollauslese noetig; auf Z legen. +#NET REFCLK LOC = AC11 | IOSTANDARD=LVCMOS25; #ok -- listen to REFCLK possible + + +NET D_A<3> LOC = N1 | IOSTANDARD=LVCMOS25; #ok +NET D_A<2> LOC = M2 | IOSTANDARD=LVCMOS25; #ok +NET D_A<1> LOC = K2 | IOSTANDARD=LVCMOS25; #ok +NET D_A<0> LOC = H2 | IOSTANDARD=LVCMOS25; #ok + + +# PLL-Lock input: high active +NET D_PLLLCK<0> LOC = L3 | IOSTANDARD=LVCMOS25 | PULLDOWN ; #ok +NET D_PLLLCK<1> LOC = N2 | IOSTANDARD=LVCMOS25 | PULLDOWN ; #ok +NET D_PLLLCK<2> LOC = AA2 | IOSTANDARD=LVCMOS25 | PULLDOWN ; #ok +NET D_PLLLCK<3> LOC = AC2 | IOSTANDARD=LVCMOS25 | PULLDOWN ; #ok + +# SROUT input: read stop position here +# bus?? +NET D0_SROUT LOC = B2 | IOSTANDARD=LVCMOS25; #ok +NET D1_SROUT LOC = E3 | IOSTANDARD=LVCMOS25; #ok +NET D2_SROUT LOC = N4 | IOSTANDARD=LVCMOS25; #ok +NET D3_SROUT LOC = U1 | IOSTANDARD=LVCMOS25; #ok + +# RSRLOAD & SRCLK output: clock out analog samples here +# SRCLK bus?? +NET RSRLOAD LOC = H1 | IOSTANDARD=LVCMOS25; #ok +# +NET D0_SRCLK LOC = F2 | IOSTANDARD=LVCMOS25; #ok +NET D1_SRCLK LOC = F3 | IOSTANDARD=LVCMOS25; #ok +NET D2_SRCLK LOC = R3 | IOSTANDARD=LVCMOS25; #ok +NET D3_SRCLK LOC = V1 | IOSTANDARD=LVCMOS25; #ok + +# Testpoints near DRS Chips +# oganized in 3 times 4x2 pins +NET D_T<0> LOC = D3 | IOSTANDARD=LVCMOS25; #ok +NET D_T<1> LOC = G3 | IOSTANDARD=LVCMOS25; #ok +NET D_T<2> LOC = G4 | IOSTANDARD=LVCMOS25; #ok +NET D_T<3> LOC = J4 | IOSTANDARD=LVCMOS25; #ok +NET D_T<4> LOC = K5 | IOSTANDARD=LVCMOS25; #ok +NET D_T<5> LOC = L4 | IOSTANDARD=LVCMOS25; #ok +NET D_T<6> LOC = M3 | IOSTANDARD=LVCMOS25; #ok +NET D_T<7> LOC = T3 | IOSTANDARD=LVCMOS25; #ok +NET D_T2<0> LOC = U2 | IOSTANDARD=LVCMOS25; #ok was D_T<8> +NET D_T2<1> LOC = V2 | IOSTANDARD=LVCMOS25; #ok was D_T<9> +NET D_T2<2> LOC = W3 | IOSTANDARD=LVCMOS25; #ok aka D_TA was D_T<10> +NET D_T2<3> LOC = AA3 | IOSTANDARD=LVCMOS25; #ok aka D_TB was D_T<11> + + + +# ADC Signals +####################################################### +NET OE_ADC LOC = D6 | IOSTANDARD=LVCMOS33; #ok FIXME was A-OEB + +NET A_CLK<0> LOC = B23 | IOSTANDARD=LVCMOS33; #ok aka A0_CLK +NET A_CLK<1> LOC = A3 | IOSTANDARD=LVCMOS33; #ok aka A1_CLK +NET A_CLK<2> LOC = AE3 | IOSTANDARD=LVCMOS33; #ok aka A2_CLK +NET A_CLK<3> LOC = AE25 | IOSTANDARD=LVCMOS33; #ok aka A3_CLK + +NET A_OTR<0> LOC = A22 | IOSTANDARD=LVCMOS33; #ok aka A0_OTR +NET A_OTR<1> LOC = B12 | IOSTANDARD=LVCMOS33; #ok aka A1_OTR +NET A_OTR<2> LOC = AF3 | IOSTANDARD=LVCMOS33; #ok aka A2_OTR +NET A_OTR<3> LOC = AE17 | IOSTANDARD=LVCMOS33; #ok aka A3_OTR + +# ADC data +NET A0_D<0> LOC = D13 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<1> LOC = A15 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<2> LOC = B15 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<3> LOC = B17 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<4> LOC = D16 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<5> LOC = A18 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<6> LOC = B18 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<7> LOC = A19 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<8> LOC = B19 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<9> LOC = A20 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<10> LOC = B21 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<11> LOC = C22 | IOSTANDARD=LVCMOS33; #ok + +NET A1_D<0> LOC = B3 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<1> LOC = A4 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<2> LOC = B4 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<3> LOC = B6 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<4> LOC = B7 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<5> LOC = A8 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<6> LOC = B8 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<7> LOC = A9 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<8> LOC = B9 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<9> LOC = A10 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<10> LOC = B10 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<11> LOC = A12 | IOSTANDARD=LVCMOS33; #ok + +NET A2_D<0> LOC = AD14 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<1> LOC = AD11 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<2> LOC = AD7 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<3> LOC = AE8 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<4> LOC = AF8 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<5> LOC = AE7 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<6> LOC = AC6 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<7> LOC = AE6 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<8> LOC = AF5 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<9> LOC = AD6 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<10> LOC = AF4 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<11> LOC = AE4 | IOSTANDARD=LVCMOS33; #ok + +NET A3_D<0> LOC = AF25 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<1> LOC = AE23 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<2> LOC = AF23 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<3> LOC = AD22 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<4> LOC = AE21 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<5> LOC = AD21 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<6> LOC = AF20 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<7> LOC = AE20 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<8> LOC = AF19 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<9> LOC = AC22 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<10> LOC = AE19 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<11> LOC = AD19 | IOSTANDARD=LVCMOS33; #ok + +# testpoints near ADC + +#NET A0_T<0> LOC = D8 | IOSTANDARD=LVCMOS33; #ok +#NET A0_T<1> LOC = D9 | IOSTANDARD=LVCMOS33; #ok +#NET A0_T<2> LOC = D10 | IOSTANDARD=LVCMOS33; #ok +#NET A0_T<3> LOC = E10 | IOSTANDARD=LVCMOS33; #ok +#NET A0_T<4> LOC = E12 | IOSTANDARD=LVCMOS33; #ok +#NET A0_T<5> LOC = E14 | IOSTANDARD=LVCMOS33; #ok +#NET A0_T<6> LOC = D17 | IOSTANDARD=LVCMOS33; #ok +#NET A0_T<7> LOC = D18 | IOSTANDARD=LVCMOS33; #ok + +NET A1_T<0> LOC = AB9 | IOSTANDARD=LVCMOS33; #ok +NET A1_T<1> LOC = AB12 | IOSTANDARD=LVCMOS33; #ok +NET A1_T<2> LOC = AC12 | IOSTANDARD=LVCMOS33; #ok +NET A1_T<3> LOC = AC14 | IOSTANDARD=LVCMOS33; #ok +NET A1_T<4> LOC = AC15 | IOSTANDARD=LVCMOS33; #ok +#NET A1_T<5> LOC = AB16 | IOSTANDARD=LVCMOS33; #ok +#NET A1_T<6> LOC = AC16 | IOSTANDARD=LVCMOS33; #ok +#NET A1_T<7> LOC = AB18 | IOSTANDARD=LVCMOS33; #ok + + + +# SPI bus +####################################################### +NET S_CLK LOC = C10 | IOSTANDARD=LVCMOS33; #ok +NET MOSI LOC = C11 | IOSTANDARD=LVCMOS33; #ok +NET MISO LOC = C12 | IOSTANDARD=LVCMOS33; #ok + +NET T0_CS LOC = C15 | IOSTANDARD=LVCMOS33; #ok +NET T1_CS LOC = C16 | IOSTANDARD=LVCMOS33; #ok +NET T2_CS LOC = C17 | IOSTANDARD=LVCMOS33; #ok +NET T3_CS LOC = C18 | IOSTANDARD=LVCMOS33; #ok +NET DAC_CS LOC = C20 | IOSTANDARD=LVCMOS33; #ok +NET EE_CS LOC = C21 | IOSTANDARD=LVCMOS33; #ok + + + +# LEDs +####################################################### +NET LED<0> LOC = T4 | IOSTANDARD=LVCMOS25 | DRIVE = 2; +NET LED<1> LOC = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 2; +NET LED<2> LOC = AD20 | IOSTANDARD=LVCMOS33 | DRIVE = 2; + + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 9841) @@ -0,0 +1,264 @@ +-- VHDL Entity FACT_FAD_lib.FAD_Board.symbol +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 11:40:21 21.07.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +ENTITY FAD_Board IS + PORT( + A0_D : IN std_logic_vector (11 DOWNTO 0); + A1_D : IN std_logic_vector (11 DOWNTO 0); + A2_D : IN std_logic_vector (11 DOWNTO 0); + A3_D : IN std_logic_vector (11 DOWNTO 0); + A_OTR : IN std_logic_vector (3 DOWNTO 0); + D0_SROUT : IN std_logic; + D1_SROUT : IN std_logic; + D2_SROUT : IN std_logic; + D3_SROUT : IN std_logic; + D_PLLLCK : IN std_logic_vector (3 DOWNTO 0); + TEST_TRG : IN std_logic; + TRG : IN STD_LOGIC; + W_INT : IN std_logic; + X_50M : IN STD_LOGIC; + A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + A_CLK : OUT std_logic_vector (3 DOWNTO 0); + D0_SRCLK : OUT STD_LOGIC; + D1_SRCLK : OUT STD_LOGIC; + D2_SRCLK : OUT STD_LOGIC; + D3_SRCLK : OUT STD_LOGIC; + DAC_CS : OUT std_logic; + DENABLE : OUT std_logic := '0'; + DWRITE : OUT std_logic := '0'; + D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + EE_CS : OUT std_logic; + LED : OUT std_logic_vector ( 2 DOWNTO 0 ) := (others => '1'); + MOSI : OUT std_logic := '0'; + OE_ADC : OUT STD_LOGIC; + RS485_C_DE : OUT std_logic; + RS485_C_RE : OUT std_logic; + RS485_E_DE : OUT std_logic; + RS485_E_RE : OUT std_logic; + RSRLOAD : OUT std_logic := '0'; + SRIN : OUT std_logic; + S_CLK : OUT std_logic; + T0_CS : OUT std_logic; + T1_CS : OUT std_logic; + T2_CS : OUT std_logic; + T3_CS : OUT std_logic; + TRG_V : OUT std_logic; + W_A : OUT std_logic_vector (9 DOWNTO 0); + W_CS : OUT std_logic := '1'; + W_RD : OUT std_logic := '1'; + W_RES : OUT std_logic := '1'; + W_WR : OUT std_logic := '1'; + MISO : INOUT std_logic; + W_D : INOUT std_logic_vector (15 DOWNTO 0) + ); + +-- Declarations + +END FAD_Board ; + +-- +-- VHDL Architecture FACT_FAD_lib.FAD_Board.struct +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 11:40:21 21.07.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE IEEE.NUMERIC_STD.all; +USE ieee.std_logic_unsigned.all; + +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +LIBRARY FACT_FAD_lib; + +ARCHITECTURE struct OF FAD_Board IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL CLK_25_PS : std_logic; + SIGNAL CLK_50 : std_logic; + SIGNAL SRCLK : std_logic := '0'; + SIGNAL TRG_OR : std_logic; + SIGNAL adc_data_array : adc_data_array_type; + SIGNAL board_id : std_logic_vector(3 DOWNTO 0); + SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); + SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0'); + SIGNAL dummy : std_logic; + SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); + + + -- Component Declarations + COMPONENT FAD_main + GENERIC ( + RAMADDRWIDTH64b : integer := 12 + ); + PORT ( + CLK : IN std_logic ; + SROUT_in_0 : IN std_logic ; + SROUT_in_1 : IN std_logic ; + SROUT_in_2 : IN std_logic ; + SROUT_in_3 : IN std_logic ; + adc_data_array : IN adc_data_array_type ; + adc_otr_array : IN std_logic_vector (3 DOWNTO 0); + board_id : IN std_logic_vector (3 DOWNTO 0); + crate_id : IN std_logic_vector (1 DOWNTO 0); + trigger : IN std_logic ; + wiz_int : IN std_logic ; + CLK_25_PS : OUT std_logic ; + CLK_50 : OUT std_logic ; + RSRLOAD : OUT std_logic := '0'; + SRCLK : OUT std_logic := '0'; + adc_oeb : OUT std_logic := '1'; + dac_cs : OUT std_logic ; + denable : OUT std_logic := '0'; -- default domino wave off + drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + drs_dwrite : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + mosi : OUT std_logic := '0'; + sclk : OUT std_logic ; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0); + wiz_addr : OUT std_logic_vector (9 DOWNTO 0); + wiz_cs : OUT std_logic := '1'; + wiz_rd : OUT std_logic := '1'; + wiz_reset : OUT std_logic := '1'; + wiz_wr : OUT std_logic := '1'; + sio : INOUT std_logic ; + wiz_data : INOUT std_logic_vector (15 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb_ID + -- hard-wired IDs + board_id <= "0101"; + crate_id <= "01"; + + -- HDL Embedded Text Block 2 ADC_CLK + -- ADC_CLK 2 + A_CLK (0) <= CLK_25_PS; + A_CLK (1) <= CLK_25_PS; + A_CLK (2) <= CLK_25_PS; + A_CLK (3) <= CLK_25_PS; + + -- HDL Embedded Text Block 3 ADC_DATA + -- ADC_DATA 3 + adc_data_array (0) <= A0_D; + adc_data_array (1) <= A1_D; + adc_data_array (2) <= A2_D; + adc_data_array (3) <= A3_D; + + -- HDL Embedded Text Block 4 SRCLK + -- SRCLK 4 + D0_SRCLK <= SRCLK; + D1_SRCLK <= SRCLK; + D2_SRCLK <= SRCLK; + D3_SRCLK <= SRCLK; + + -- HDL Embedded Text Block 5 T_CS + -- T_CS 5 + T0_CS <= sensor_cs (0); + T1_CS <= sensor_cs (1); + T2_CS <= sensor_cs (2); + T3_CS <= sensor_cs (3); + + -- HDL Embedded Text Block 6 MISC + -- MISC 6 + TRG_V <= '0'; + RS485_C_RE <= '1'; + RS485_C_DE <= '0'; + RS485_E_RE <= '1'; + RS485_E_DE <= '0'; + + -- DENABLE <= '0'; -- domino wave stopped + -- DENABLE <= '1'; -- domino wave running + + SRIN <= 'Z'; + EE_CS <= '1'; + -- LEDs are low active + LED(0) <= '1'; + LED(1) <= '0'; -- on + LED(2) <= '1'; + + + + + -- HDL Embedded Text Block 7 eb1 + D_T2 <= D_PLLLCK; + + -- HDL Embedded Text Block 8 eb2 + -- eb2 8 + A1_T(3 downto 0) <= drs_channel_id; + D_A <= drs_channel_id; + A1_T(4) <= TRG_OR; + + + -- ModuleWare code(v1.9) for instance 'I3' of 'assignment' + DAC_CS <= dummy; + + -- ModuleWare code(v1.9) for instance 'I2' of 'or' + TRG_OR <= TRG OR TEST_TRG; + + -- Instance port mappings. + I_board_main : FAD_main + GENERIC MAP ( + RAMADDRWIDTH64b => LOG2_OF_RAM_SIZE_64B + ) + PORT MAP ( + CLK => X_50M, + SROUT_in_0 => D0_SROUT, + SROUT_in_1 => D1_SROUT, + SROUT_in_2 => D2_SROUT, + SROUT_in_3 => D3_SROUT, + adc_data_array => adc_data_array, + adc_otr_array => A_OTR, + board_id => board_id, + crate_id => crate_id, + trigger => TRG_OR, + wiz_int => W_INT, + CLK_25_PS => CLK_25_PS, + CLK_50 => CLK_50, + RSRLOAD => RSRLOAD, + SRCLK => SRCLK, + adc_oeb => OE_ADC, + dac_cs => dummy, + denable => DENABLE, + drs_channel_id => drs_channel_id, + drs_dwrite => DWRITE, + led => D_T, + mosi => MOSI, + sclk => S_CLK, + sensor_cs => sensor_cs, + wiz_addr => W_A, + wiz_cs => W_CS, + wiz_rd => W_RD, + wiz_reset => W_RES, + wiz_wr => W_WR, + sio => MISO, + wiz_data => W_D + ); + +END struct; Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 9841) @@ -0,0 +1,135 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- use IEEE.NUMERIC_STD.ALL; + +package fad_definitions is + + +-- Declare constants + + type mac_type is array (0 to 2) of std_logic_vector (15 downto 0); + type ip_type is array (0 to 3) of integer; +-- Network Settings + + constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"97B4"); + + -- @ ETH zurich + -- constant NETMASK : ip_type := (255, 255, 248, 0); + -- constant IP_ADDRESS : ip_type := (192, 33, 99, 225); + -- constant GATEWAY : ip_type := (192, 33, 96, 1); + + -- @ TU Dortmund + constant NETMASK : ip_type := (255, 255, 255, 0); + constant IP_ADDRESS : ip_type := (129, 217, 160, 119); + constant GATEWAY : ip_type := (129, 217, 160, 1); + + constant FIRST_PORT : integer := 5000; +-- Network Settings End + + constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"01"; + constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"02"; + constant PACKAGE_HEADER_LENGTH : integer := 22; + constant PACKAGE_END_LENGTH : integer := 2; -- CRC and END-Flag + + constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset + +-- W5300 Registers + constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0'); + constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0"; + constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2"; + constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4"; + constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8"; + constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10"; + constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14"; + constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18"; + constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C"; + constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E"; + constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20"; + constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22"; + constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24"; + constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26"; + constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28"; + constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A"; + constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C"; + constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E"; + constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30"; + + constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0"; + constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2"; + constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4"; + constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6"; + constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8"; + constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A"; + constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12"; + constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14"; + constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20"; + constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24"; + constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28"; + constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E"; + constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30"; +-- End W5300 registers + +-- + constant W5300_TX_FIFO_SIZE : integer := (15360 / 2); -- Socket TX FIFO-Size in 16 Bit Words + + constant LOG2_OF_RAM_SIZE_64B : integer := 15; + --constant RAM_SIZE_64B : integer := 2**LOG2_OF_RAM_SIZE_64B; + constant RAM_SIZE_64B : integer := 24576; + constant RAM_SIZE_16B : integer := RAM_SIZE_64B * 4; + +-- TYPE definitions + type roi_max_type is array (0 to 8) of std_logic_vector (10 downto 0); + type roi_array_type is array (0 to 35) of integer range 0 to 1024; + type drs_s_cell_array_type is array (0 to 3) of std_logic_vector (9 downto 0); + type adc_data_array_type is array (0 to 3) of std_logic_vector (11 downto 0); + + type dac_array_type is array (0 to 7) of integer range 0 to 2**16 - 1; + type sensor_array_type is array (0 to 3) of integer range 0 to 2**16 - 1; + +-- constant DEFAULT_ROI : roi_array_type := (115, 125, 100, 102, 155, 101, 0, 101, 106, +-- 181, 121, 189, 101, 101, 187, 56, 187, 101, +-- 2, 141, 101, 100, 10, 100, 178, 101, 174, +-- 12, 181, 100, 102, 101, 102, 0, 101, 108); +-- constant DEFAULT_ROI : roi_array_type := (others => 100); + constant DEFAULT_ROI : roi_array_type := (others => 210); + + constant DEFAULT_DAC : dac_array_type := (20972, 34079, 20526, 0, 28836, 28836, 28836, 28836); + --constant DEFAULT_DAC : dac_array_type := (others => 0); + + constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= "0000"; + constant DEFAULT_DRSADDR_MODE : std_logic := '0'; + + + +-- Commands + constant CMD_START : std_logic_vector := X"C0"; + constant CMD_STOP : std_logic_vector := X"30"; + constant CMD_TRIGGER : std_logic_vector := X"A0"; + + constant CMD_TRIGGER_C : std_logic_vector := X"B0"; + constant CMD_TRIGGER_S : std_logic_vector := X"20"; + constant CMD_READ : std_logic_vector := X"0A"; + constant CMD_WRITE : std_logic_vector := X"05"; + + constant CMD_DENABLE : std_logic_vector := X"06"; + constant CMD_DDISABLE : std_logic_vector := X"07"; + constant CMD_DWRITE_RUN : std_logic_vector := X"08"; + constant CMD_DWRITE_STOP : std_logic_vector := X"09"; + constant CMD_SCLK_ON : std_logic_vector := X"10"; + constant CMD_SCLK_OFF : std_logic_vector := X"11"; + + +-- Declare functions and procedure + + +end fad_definitions; + + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd.bak =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd.bak (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd.bak (revision 9841) @@ -0,0 +1,135 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- use IEEE.NUMERIC_STD.ALL; + +package fad_definitions is + + +-- Declare constants + + type mac_type is array (0 to 2) of std_logic_vector (15 downto 0); + type ip_type is array (0 to 3) of integer; +-- Network Settings + + constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"97B4"); + + -- @ ETH zurich + -- constant NETMASK : ip_type := (255, 255, 248, 0); + -- constant IP_ADDRESS : ip_type := (192, 33, 99, 225); + -- constant GATEWAY : ip_type := (192, 33, 96, 1); + + -- @ TU Dortmund + constant NETMASK : ip_type := (255, 255, 255, 0); + constant IP_ADDRESS : ip_type := (129, 217, 160, 119); + constant GATEWAY : ip_type := (129, 217, 160, 1); + + constant FIRST_PORT : integer := 5000; +-- Network Settings End + + constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"01"; + constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"02"; + constant PACKAGE_HEADER_LENGTH : integer := 22; + constant PACKAGE_END_LENGTH : integer := 2; -- CRC and END-Flag + + constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset + +-- W5300 Registers + constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0'); + constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0"; + constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2"; + constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4"; + constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8"; + constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10"; + constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14"; + constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18"; + constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C"; + constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E"; + constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20"; + constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22"; + constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24"; + constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26"; + constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28"; + constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A"; + constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C"; + constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E"; + constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30"; + + constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0"; + constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2"; + constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4"; + constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6"; + constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8"; + constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A"; + constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12"; + constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14"; + constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20"; + constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24"; + constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28"; + constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E"; + constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30"; +-- End W5300 registers + +-- + constant W5300_TX_FIFO_SIZE : integer := (15360 / 2); -- Socket TX FIFO-Size in 16 Bit Words + + constant LOG2_OF_RAM_SIZE_64B : integer := 15; + --constant RAM_SIZE_64B : integer := 2**LOG2_OF_RAM_SIZE_64B; + constant RAM_SIZE_64B : integer := 24576; + constant RAM_SIZE_16B : integer := RAM_SIZE_64B * 4; + +-- TYPE definitions + type roi_max_type is array (0 to 8) of std_logic_vector (10 downto 0); + type roi_array_type is array (0 to 35) of integer range 0 to 1024; + type drs_s_cell_array_type is array (0 to 3) of std_logic_vector (9 downto 0); + type adc_data_array_type is array (0 to 3) of std_logic_vector (11 downto 0); + + type dac_array_type is array (0 to 7) of integer range 0 to 2**16 - 1; + type sensor_array_type is array (0 to 3) of integer range 0 to 2**16 - 1; + +-- constant DEFAULT_ROI : roi_array_type := (115, 125, 100, 102, 155, 101, 0, 101, 106, +-- 181, 121, 189, 101, 101, 187, 56, 187, 101, +-- 2, 141, 101, 100, 10, 100, 178, 101, 174, +-- 12, 181, 100, 102, 101, 102, 0, 101, 108); +-- constant DEFAULT_ROI : roi_array_type := (others => 100); + constant DEFAULT_ROI : roi_array_type := (others => 210); + + constant DEFAULT_DAC : dac_array_type := (20972, 34079, 20526, 0, 28836, 28836, 28836, 28836); + --constant DEFAULT_DAC : dac_array_type := (others => 0); + + constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= "0000"; + constant DEFAULT_DRSADDR_MODE : std_logic := '0'; + + + +-- Commands + constant CMD_START : std_logic_vector := X"C0"; + constant CMD_STOP : std_logic_vector := X"30"; + constant CMD_TRIGGER : std_logic_vector := X"A0"; + + constant CMD_TRIGGER_C : std_logic_vector := X"B0"; + constant CMD_TRIGGER_S : std_logic_vector := X"20"; + constant CMD_READ : std_logic_vector := X"0A"; + constant CMD_WRITE : std_logic_vector := X"05"; + + constant CMD_DENABLE : std_logic_vector := X"06"; + constant CMD_DDISABLE : std_logic_vector := X"07"; + constant CMD_DWRITE_RUN : std_logic_vector := X"08"; + constant CMD_DWRITE_STOP : std_logic_vector := X"09"; + constant CMD_SCLK_ON : std_logic_vector := X"10"; + constant CMD_SCLK_ON : std_logic_vector := X"11"; + + +-- Declare functions and procedure + + +end fad_definitions; + + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 9841) @@ -0,0 +1,563 @@ +-- VHDL Entity FACT_FAD_lib.FAD_main.symbol +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 11:40:17 21.07.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +ENTITY FAD_main IS + GENERIC( + RAMADDRWIDTH64b : integer := 12 + ); + PORT( + CLK : IN std_logic; + SROUT_in_0 : IN std_logic; + SROUT_in_1 : IN std_logic; + SROUT_in_2 : IN std_logic; + SROUT_in_3 : IN std_logic; + adc_data_array : IN adc_data_array_type; + adc_otr_array : IN std_logic_vector (3 DOWNTO 0); + board_id : IN std_logic_vector (3 DOWNTO 0); + crate_id : IN std_logic_vector (1 DOWNTO 0); + trigger : IN std_logic; + wiz_int : IN std_logic; + CLK_25_PS : OUT std_logic; + CLK_50 : OUT std_logic; + RSRLOAD : OUT std_logic := '0'; + SRCLK : OUT std_logic := '0'; + adc_oeb : OUT std_logic := '1'; + dac_cs : OUT std_logic; + denable : OUT std_logic := '0'; -- default domino wave off + drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + drs_dwrite : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + mosi : OUT std_logic := '0'; + sclk : OUT std_logic; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0); + wiz_addr : OUT std_logic_vector (9 DOWNTO 0); + wiz_cs : OUT std_logic := '1'; + wiz_rd : OUT std_logic := '1'; + wiz_reset : OUT std_logic := '1'; + wiz_wr : OUT std_logic := '1'; + sio : INOUT std_logic; + wiz_data : INOUT std_logic_vector (15 DOWNTO 0) + ); + +-- Declarations + +END FAD_main ; + +-- +-- VHDL Architecture FACT_FAD_lib.FAD_main.struct +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 11:40:18 21.07.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use ieee.STD_LOGIC_UNSIGNED.all; + +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + +library UNISIM; +use UNISIM.VComponents.all; +USE IEEE.NUMERIC_STD.all; +USE IEEE.std_logic_signed.all; + +LIBRARY FACT_FAD_lib; + +ARCHITECTURE struct OF FAD_main IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL CLK_25 : std_logic; + SIGNAL adc_data_array_int : adc_data_array_type; + SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0); + SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); + SIGNAL config_addr : std_logic_vector(7 DOWNTO 0); + SIGNAL config_busy : std_logic; + SIGNAL config_data : std_logic_vector(15 DOWNTO 0); + SIGNAL config_data_valid : std_logic; + SIGNAL config_rd_en : std_logic; + SIGNAL config_ready : std_logic; + SIGNAL config_ready_cm : std_logic; + SIGNAL config_ready_spi : std_logic; + SIGNAL config_start : std_logic := '0'; + SIGNAL config_start_cm : std_logic; + SIGNAL config_start_spi : std_logic := '0'; + SIGNAL config_started : std_logic; + SIGNAL config_started_cu : std_logic := '0'; + SIGNAL config_started_mm : std_logic; + SIGNAL config_started_spi : std_logic := '0'; + SIGNAL config_wr_en : std_logic; + SIGNAL dac_array : dac_array_type; + SIGNAL data_out : std_logic_vector(63 DOWNTO 0); + SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0'); + SIGNAL drs_address_mode : std_logic; + SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0'); + SIGNAL drs_clk_en : std_logic := '0'; + SIGNAL drs_read_s_cell : std_logic := '0'; + SIGNAL drs_read_s_cell_ready : std_logic; + SIGNAL drs_s_cell_array : drs_s_cell_array_type; + SIGNAL dwrite : std_logic := '1'; + SIGNAL dwrite_enable : std_logic := '1'; + SIGNAL new_config : std_logic := '0'; + SIGNAL package_length : std_logic_vector(15 DOWNTO 0); + SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0); + SIGNAL ram_data : std_logic_vector(15 DOWNTO 0); + SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); + SIGNAL ram_write_ea : std_logic; + SIGNAL ram_write_ready : std_logic := '0'; + SIGNAL roi_array : roi_array_type; + SIGNAL roi_max : roi_max_type; + SIGNAL s_trigger : std_logic := '0'; + SIGNAL sclk1 : std_logic; + SIGNAL sclk_enable : std_logic; + SIGNAL sensor_array : sensor_array_type; + SIGNAL sensor_ready : std_logic; + SIGNAL trigger_id : std_logic_vector(47 DOWNTO 0); + SIGNAL wiz_ack : std_logic; + SIGNAL wiz_busy : std_logic; + SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); + SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); + SIGNAL wiz_write_ea : std_logic := '0'; + SIGNAL wiz_write_end : std_logic := '0'; + SIGNAL wiz_write_header : std_logic := '0'; + SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0'); + SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0"; + + -- Implicit buffer signal declarations + SIGNAL CLK_25_PS_internal : std_logic; + SIGNAL CLK_50_internal : std_logic; + + + -- Component Declarations + COMPONENT adc_buffer + PORT ( + adc_data_array : IN adc_data_array_type; + adc_otr_array : IN std_logic_vector (3 DOWNTO 0); + clk_ps : IN std_logic; + adc_data_array_int : OUT adc_data_array_type; + adc_otr : OUT std_logic_vector (3 DOWNTO 0) + ); + END COMPONENT; + COMPONENT clock_generator + PORT ( + CLK : IN std_logic ; + CLK_25 : OUT std_logic ; + CLK_25_PS : OUT std_logic ; + CLK_50 : OUT std_logic + ); + END COMPONENT; + COMPONENT control_unit + PORT ( + clk : IN STD_LOGIC ; + config_addr : IN std_logic_vector (7 DOWNTO 0); + config_rd_en : IN std_logic ; + config_start : IN std_logic ; + config_wr_en : IN std_logic ; + config_busy : OUT std_logic ; + config_data_valid : OUT std_logic ; + config_ready : OUT std_logic ; + config_started : OUT std_logic := '0'; + dac_array : OUT dac_array_type ; + drs_address : OUT std_logic_vector (3 DOWNTO 0); + drs_address_mode : OUT std_logic ; + roi_array : OUT roi_array_type ; + config_data : INOUT std_logic_vector (15 DOWNTO 0) + ); + END COMPONENT; + COMPONENT dataRAM_64b_16b_width14_5 + PORT ( + clka : IN std_logic ; + dina : IN std_logic_VECTOR (63 DOWNTO 0); + addra : IN std_logic_VECTOR (14 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + clkb : IN std_logic ; + addrb : IN std_logic_VECTOR (16 DOWNTO 0); + doutb : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + END COMPONENT; + COMPONENT data_generator + GENERIC ( + RAM_ADDR_WIDTH : integer := 12 + ); + PORT ( + clk : IN std_logic ; + data_out : OUT std_logic_vector (63 DOWNTO 0); + addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + write_ea : OUT std_logic_vector (0 DOWNTO 0) := "0"; + ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + ram_write_ea : IN std_logic ; + ram_write_ready : OUT std_logic := '0'; + config_start_mm : OUT std_logic := '0'; + config_start_cm : OUT std_logic := '0'; + config_start_spi : OUT std_logic := '0'; + config_ready_mm : IN std_logic ; + config_ready_cm : IN std_logic ; + config_ready_spi : IN std_logic ; + config_started_mm : IN std_logic ; + config_started_cm : IN std_logic ; + config_started_spi : IN std_logic ; + roi_array : IN roi_array_type ; + roi_max : IN roi_max_type ; + sensor_array : IN sensor_array_type ; + sensor_ready : IN std_logic ; + dac_array : IN dac_array_type ; + package_length : IN std_logic_vector (15 DOWNTO 0); + board_id : IN std_logic_vector (3 DOWNTO 0); + crate_id : IN std_logic_vector (1 DOWNTO 0); + trigger_id : IN std_logic_vector (47 DOWNTO 0); + trigger : IN std_logic ; + s_trigger : IN std_logic ; + new_config : IN std_logic ; + config_started : OUT std_logic := '0'; + adc_data_array : IN adc_data_array_type ; + adc_oeb : OUT std_logic := '1'; + adc_otr : IN std_logic_vector (3 DOWNTO 0); + drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + drs_dwrite : OUT std_logic := '1'; + drs_clk_en : OUT std_logic := '0'; + drs_read_s_cell : OUT std_logic := '0'; + drs_read_s_cell_ready : IN std_logic ; + drs_s_cell_array : IN drs_s_cell_array_type + ); + END COMPONENT; + COMPONENT drs_pulser + PORT ( + CLK : IN std_logic; + SROUT_in_0 : IN std_logic; + SROUT_in_1 : IN std_logic; + SROUT_in_2 : IN std_logic; + SROUT_in_3 : IN std_logic; + start_endless_mode : IN std_logic; + start_read_stop_pos_mode : IN std_logic; + RSRLOAD : OUT std_logic := '0'; + SRCLK : OUT std_logic := '0'; + stop_pos : OUT drs_s_cell_array_type; + stop_pos_valid : OUT std_logic := '0' + ); + END COMPONENT; + COMPONENT memory_manager + GENERIC ( + RAM_ADDR_WIDTH_64B : integer := 12; + RAM_ADDR_WIDTH_16B : integer := 14 + ); + PORT ( + clk : IN std_logic ; + config_start : IN std_logic ; + ram_write_ready : IN std_logic ; + roi_array : IN roi_array_type ; + ram_write_ea : OUT std_logic := '0'; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0'; + roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); + package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 DOWNTO 0) := (others => '0'); + wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0'); + wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + wiz_write_ea : OUT std_logic := '0'; + wiz_write_header : OUT std_logic := '0'; + wiz_write_end : OUT std_logic := '0'; + wiz_busy : IN std_logic ; + wiz_ack : IN std_logic ; + ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') + ); + END COMPONENT; + COMPONENT spi_interface + PORT ( + clk_50MHz : IN std_logic ; + config_start : IN std_logic ; + dac_array : IN dac_array_type ; + config_ready : OUT std_logic ; + config_started : OUT std_logic := '0'; + dac_cs : OUT std_logic ; + mosi : OUT std_logic := '0'; + sclk : OUT std_logic ; + sensor_array : OUT sensor_array_type ; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0); + sensor_ready : OUT std_logic ; + miso : INOUT std_logic + ); + END COMPONENT; + COMPONENT trigger_counter + PORT ( + trigger_id : OUT std_logic_vector (47 DOWNTO 0); + trigger : IN std_logic ; + clk : IN std_logic + ); + END COMPONENT; + COMPONENT w5300_modul + GENERIC ( + RAM_ADDR_WIDTH : integer := 14 + ); + PORT ( + clk : IN std_logic ; + wiz_reset : OUT std_logic := '1'; + addr : OUT std_logic_vector (9 DOWNTO 0); + data : INOUT std_logic_vector (15 DOWNTO 0); + cs : OUT std_logic := '1'; + wr : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + rd : OUT std_logic := '1'; + int : IN std_logic ; + write_length : IN std_logic_vector (16 DOWNTO 0); + ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + ram_data : IN std_logic_vector (15 DOWNTO 0); + ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + data_valid : IN std_logic ; + data_valid_ack : OUT std_logic := '0'; + busy : OUT std_logic := '1'; + write_header_flag : IN std_logic ; + write_end_flag : IN std_logic ; + fifo_channels : IN std_logic_vector (3 DOWNTO 0); + s_trigger : OUT std_logic := '0'; + new_config : OUT std_logic := '0'; + config_started : IN std_logic ; + config_addr : OUT std_logic_vector (7 DOWNTO 0); + config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + config_wr_en : OUT std_logic := '0'; + config_rd_en : OUT std_logic := '0'; + config_busy : IN std_logic ; + denable : OUT std_logic := '0'; -- default domino wave off + dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. + sclk_enable : OUT std_logic := '1' -- default DWRITE HIGH. + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer; + FOR ALL : clock_generator USE ENTITY FACT_FAD_lib.clock_generator; + FOR ALL : control_unit USE ENTITY FACT_FAD_lib.control_unit; + FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5; + FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator; + FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser; + FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager; + FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface; + FOR ALL : trigger_counter USE ENTITY FACT_FAD_lib.trigger_counter; + FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul; + -- pragma synthesis_on + + +BEGIN + + -- ModuleWare code(v1.9) for instance 'I5' of 'and' + drs_dwrite <= dwrite AND dwrite_enable; + + -- ModuleWare code(v1.9) for instance 'U_1' of 'and' + sclk <= sclk_enable AND sclk1; + + -- ModuleWare code(v1.9) for instance 'U_0' of 'mux' + u_0combo_proc: PROCESS(drs_channel_internal, drs_address, + drs_address_mode) + BEGIN + CASE drs_address_mode IS + WHEN '0' => drs_channel_id <= drs_channel_internal; + WHEN '1' => drs_channel_id <= drs_address; + WHEN OTHERS => drs_channel_id <= (OTHERS => 'X'); + END CASE; + END PROCESS u_0combo_proc; + + -- Instance port mappings. + I_main_adc_buffer : adc_buffer + PORT MAP ( + clk_ps => CLK_25_PS_internal, + adc_data_array => adc_data_array, + adc_otr_array => adc_otr_array, + adc_data_array_int => adc_data_array_int, + adc_otr => adc_otr + ); + I_main_clock_gen : clock_generator + PORT MAP ( + CLK => CLK, + CLK_25 => CLK_25, + CLK_25_PS => CLK_25_PS_internal, + CLK_50 => CLK_50_internal + ); + I_main_control_unit : control_unit + PORT MAP ( + clk => CLK_50_internal, + config_addr => config_addr, + config_rd_en => config_rd_en, + config_start => config_start_cm, + config_wr_en => config_wr_en, + config_busy => config_busy, + config_data_valid => config_data_valid, + config_ready => config_ready_cm, + config_started => config_started_cu, + dac_array => dac_array, + drs_address => drs_address, + drs_address_mode => drs_address_mode, + roi_array => roi_array, + config_data => config_data + ); + U_4 : dataRAM_64b_16b_width14_5 + PORT MAP ( + clka => CLK_25, + dina => data_out, + addra => addr_out, + wea => write_ea, + clkb => CLK_50_internal, + addrb => ram_addr, + doutb => ram_data + ); + I_main_data_generator : data_generator + GENERIC MAP ( + RAM_ADDR_WIDTH => RAMADDRWIDTH64b + ) + PORT MAP ( + clk => CLK_25, + data_out => data_out, + addr_out => addr_out, + write_ea => write_ea, + ram_start_addr => ram_start_addr, + ram_write_ea => ram_write_ea, + ram_write_ready => ram_write_ready, + config_start_mm => config_start, + config_start_cm => config_start_cm, + config_start_spi => config_start_spi, + config_ready_mm => config_ready, + config_ready_cm => config_ready_cm, + config_ready_spi => config_ready_spi, + config_started_mm => config_started_mm, + config_started_cm => config_started_cu, + config_started_spi => config_started_spi, + roi_array => roi_array, + roi_max => roi_max, + sensor_array => sensor_array, + sensor_ready => sensor_ready, + dac_array => dac_array, + package_length => package_length, + board_id => board_id, + crate_id => crate_id, + trigger_id => trigger_id, + trigger => trigger, + s_trigger => s_trigger, + new_config => new_config, + config_started => config_started, + adc_data_array => adc_data_array_int, + adc_oeb => adc_oeb, + adc_otr => adc_otr, + drs_channel_id => drs_channel_internal, + drs_dwrite => dwrite, + drs_clk_en => drs_clk_en, + drs_read_s_cell => drs_read_s_cell, + drs_read_s_cell_ready => drs_read_s_cell_ready, + drs_s_cell_array => drs_s_cell_array + ); + I_main_drs_pulser : drs_pulser + PORT MAP ( + CLK => CLK_25, + start_endless_mode => drs_clk_en, + start_read_stop_pos_mode => drs_read_s_cell, + SROUT_in_0 => SROUT_in_0, + SROUT_in_1 => SROUT_in_1, + SROUT_in_2 => SROUT_in_2, + SROUT_in_3 => SROUT_in_3, + stop_pos => drs_s_cell_array, + stop_pos_valid => drs_read_s_cell_ready, + RSRLOAD => RSRLOAD, + SRCLK => SRCLK + ); + I_main_memory_manager : memory_manager + GENERIC MAP ( + RAM_ADDR_WIDTH_64B => RAMADDRWIDTH64b, + RAM_ADDR_WIDTH_16B => RAMADDRWIDTH64b+2 + ) + PORT MAP ( + clk => CLK_25, + config_start => config_start, + ram_write_ready => ram_write_ready, + roi_array => roi_array, + ram_write_ea => ram_write_ea, + config_ready => config_ready, + config_started => config_started_mm, + roi_max => roi_max, + package_length => package_length, + wiz_ram_start_addr => wiz_ram_start_addr, + wiz_write_length => wiz_write_length, + wiz_number_of_channels => wiz_number_of_channels, + wiz_write_ea => wiz_write_ea, + wiz_write_header => wiz_write_header, + wiz_write_end => wiz_write_end, + wiz_busy => wiz_busy, + wiz_ack => wiz_ack, + ram_start_addr => ram_start_addr + ); + I_main_SPI_interface : spi_interface + PORT MAP ( + clk_50MHz => CLK_50_internal, + config_start => config_start_spi, + dac_array => dac_array, + config_ready => config_ready_spi, + config_started => config_started_spi, + dac_cs => dac_cs, + mosi => mosi, + sclk => sclk1, + sensor_array => sensor_array, + sensor_cs => sensor_cs, + sensor_ready => sensor_ready, + miso => sio + ); + I_main_ext_trigger : trigger_counter + PORT MAP ( + trigger_id => trigger_id, + trigger => trigger, + clk => CLK_25_PS_internal + ); + I_main_ethernet : w5300_modul + GENERIC MAP ( + RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2 + ) + PORT MAP ( + clk => CLK_50_internal, + wiz_reset => wiz_reset, + addr => wiz_addr, + data => wiz_data, + cs => wiz_cs, + wr => wiz_wr, + led => led, + rd => wiz_rd, + int => wiz_int, + write_length => wiz_write_length, + ram_start_addr => wiz_ram_start_addr, + ram_data => ram_data, + ram_addr => ram_addr, + data_valid => wiz_write_ea, + data_valid_ack => wiz_ack, + busy => wiz_busy, + write_header_flag => wiz_write_header, + write_end_flag => wiz_write_end, + fifo_channels => wiz_number_of_channels, + s_trigger => s_trigger, + new_config => new_config, + config_started => config_started, + config_addr => config_addr, + config_data => config_data, + config_wr_en => config_wr_en, + config_rd_en => config_rd_en, + config_busy => config_busy, + denable => denable, + dwrite_enable => dwrite_enable, + sclk_enable => sclk_enable + ); + + -- Implicit buffered output assignments + CLK_25_PS <= CLK_25_PS_internal; + CLK_50 <= CLK_50_internal; + +END struct; Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/memory_manager_beha.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/memory_manager_beha.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/memory_manager_beha.vhd (revision 9841) @@ -0,0 +1,289 @@ +-- +-- VHDL Architecture FACT_FAD_lib.memory_manager.beha +-- +-- Created: +-- by - kai.UNKNOWN (E5PCXX) +-- at - 14:33:25 02.03.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use ieee.STD_LOGIC_UNSIGNED.all; + +library FACT_FAD_lib; +use FACT_FAD_lib.fad_definitions.all; + +-- library UNISIM; +-- use UNISIM.VComponents.all; +-- USE IEEE.NUMERIC_STD.all; + +-- RAM_ADDR_WIDTH_64B is used for +-- output ram_start_addr + +-- RAM_ADDR_WIDTH_16B is used for +-- output wiz_ram_start_addr + + +ENTITY memory_manager IS + generic( + RAM_ADDR_WIDTH_64B : integer := 12; + RAM_ADDR_WIDTH_16B : integer := 14 + ); + PORT( + clk : IN std_logic; + config_start : IN std_logic; + ram_write_ready : IN std_logic; + roi_array : IN roi_array_type; + ram_write_ea : OUT std_logic := '0'; + config_ready, config_started : OUT std_logic := '0'; + roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); + package_length : OUT std_logic_vector (15 downto 0) := (others => '0'); + wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0'); + wiz_write_length : OUT std_logic_vector (16 downto 0) := (others => '0'); + wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0'); + wiz_write_ea : OUT std_logic := '0'; + wiz_write_header : OUT std_logic := '0'; + wiz_write_end : OUT std_logic := '0'; + wiz_busy : IN std_logic; + wiz_ack : IN std_logic; + ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') + ); + +-- Declarations + +END memory_manager ; + +-- +ARCHITECTURE beha OF memory_manager IS + +type state_mm_type is (MM_CONFIG, MAX_ROI, MAX_ROI1, MAX_ROI2, FIFO_CALC, RAM_CALC, RAM_CALC1, RAM_CALC2, MM_MAIN, MM_MAIN1); +signal state_mm : state_mm_type := MM_CONFIG; + +--type roi_array_type is array (0 to 35) of integer range 0 to 1024; +type roi_max_array_type is array (0 to 8) of integer range 0 to 1024; +type channel_size_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE; +type fifo_write_length_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE; +type fifo_channels_array_type is array (0 to 8) of integer range 0 to 9; +type fifo_package_size_ram_type is array (0 to 8) of integer range 0 to RAM_SIZE_16B; + +signal roi_max_array : roi_max_array_type := (others => 0); + +-- size of channel groups (16 bit) +signal channel_size : channel_size_type := (others => 0); +-- write length of packages (16 bit) +signal fifo_write_length : fifo_write_length_type := (others => 0); +-- number of channels per package +signal fifo_channels_array : fifo_channels_array_type := (others => 0); +-- size of packages in ram (16 bit) +signal fifo_package_size_ram : fifo_package_size_ram_type := (others => 0); +-- +signal event_size_ram : integer range 0 to RAM_SIZE_16B := 0; +signal event_size_ram_64b : integer range 0 to RAM_SIZE_64B := 0; +signal event_size : integer range 0 to RAM_SIZE_16B := 0; + +signal drs_id : integer range 0 to 4 := 0; +signal channel_id : integer range 0 to 9 := 0; +signal channel_index : integer range 0 to 9 := 0; +signal package_index : integer range 0 to 9 := 0; +signal number_of_packages : integer range 0 to 9 := 0; +signal max_events_ram, events_in_ram : integer range 0 to 2048; +signal event_start_addr : integer range 0 to (RAM_SIZE_64B - 1); +signal write_start_addr : integer range 0 to (RAM_SIZE_16B - 1); +signal event_ready_flag : std_logic := '0'; +signal wiz_ack_flag : std_logic := '0'; + +signal roi_index : integer range 0 to 45 := 0; +signal temp_roi : integer range 0 to 1024 := 0; + +BEGIN + + mm : process (clk) + begin + if rising_edge (clk) then + case state_mm is + + when MM_CONFIG => + if (config_start = '1') then + config_started <= '1'; + roi_max_array <= (others => 0); + channel_size <= (others => 0); + fifo_write_length <= (others => 0); + fifo_channels_array <= (others => 0); + event_size <= 0; + ram_write_ea <= '0'; + state_mm <= MAX_ROI; + end if; + + -- calculate max ROIs and channel sizes + when MAX_ROI => + roi_index <= (drs_id * 9) + channel_id; + state_mm <= MAX_ROI1; + when MAX_ROI1 => + temp_roi <= roi_array (roi_index); + state_mm <= MAX_ROI2; + when MAX_ROI2 => + if (channel_id < 9) then + if ( temp_roi > roi_max_array (channel_id)) then + roi_max_array (channel_id) <= temp_roi; + end if; + channel_size (channel_id) <= channel_size (channel_id) + temp_roi + 3; + drs_id <= drs_id + 1; + state_mm <= MAX_ROI; + if (drs_id = 3) then + drs_id <= 0; + channel_id <= channel_id + 1; + end if; + else + drs_id <= 0; + channel_id <= 0; + channel_size (0) <= channel_size (0) + PACKAGE_HEADER_LENGTH; + channel_size (8) <= channel_size (8) + PACKAGE_END_LENGTH; + state_mm <= FIFO_CALC; + end if; + + -- calculate number of channels that fit in FIFO + when FIFO_CALC => + if (channel_id < 9) then + if ((fifo_write_length (package_index) + channel_size (channel_id)) <= W5300_TX_FIFO_SIZE) then + fifo_write_length (package_index) <= fifo_write_length (package_index) + channel_size (channel_id); + fifo_channels_array (package_index) <= fifo_channels_array (package_index) + 1; + channel_id <= channel_id + 1; + event_size <= event_size + channel_size (channel_id); + else + package_index <= package_index + 1; + end if; + else + number_of_packages <= package_index + 1; + package_index <= 0; + channel_index <= 0; + channel_id <= 0; + fifo_package_size_ram <= (others => 0); + fifo_package_size_ram (0) <= PACKAGE_HEADER_LENGTH + 6; + event_size_ram <= 0; + event_size_ram_64b <= 0; + max_events_ram <= 0; + state_mm <= RAM_CALC; + end if; + + when RAM_CALC => + if (package_index < number_of_packages) then + if (channel_index < fifo_channels_array (package_index)) then + fifo_package_size_ram (package_index) <= fifo_package_size_ram (package_index) + ((roi_max_array (channel_id) + 3) * 4); + channel_index <= channel_index + 1; + channel_id <= channel_id + 1; + else + package_index <= package_index + 1; + event_size_ram <= event_size_ram + fifo_package_size_ram (package_index); + channel_index <= 0; + end if; + else + fifo_package_size_ram (package_index - 1) <= fifo_package_size_ram (package_index - 1) + 4; + event_size_ram <= event_size_ram + 4; -- Size of Event in RAM (16 Bit), + CRC + Endflag + 2 Spare + state_mm <= RAM_CALC1; + end if; + when RAM_CALC1 => + max_events_ram <= max_events_ram + 1; + if ((max_events_ram * event_size_ram) <= RAM_SIZE_16B) then + state_mm <= RAM_CALC1; + else + max_events_ram <= max_events_ram - 1; + state_mm <= RAM_CALC2; + end if; + when RAM_CALC2 => + event_size_ram_64b <= (event_size_ram / 4); + events_in_ram <= 0; + event_start_addr <= 0; + write_start_addr <= 0; + package_index <= 0; + channel_id <= 0; + ram_start_addr <= (others => '0'); + ram_write_ea <= '1'; + config_started <= '0'; + config_ready <= '1'; + package_length <= conv_std_logic_vector (event_size, 16); + for i in 0 to 8 loop + roi_max(i) <= conv_std_logic_vector(roi_max_array(i), 11); + end loop; + state_mm <= MM_MAIN; + + when MM_MAIN => + state_mm <= MM_MAIN1; + if ((ram_write_ready = '1') and (event_ready_flag = '0')) then + ram_write_ea <= '0'; + events_in_ram <= events_in_ram + 1; + if ((event_start_addr + event_size_ram_64b) < (RAM_SIZE_64B - event_size_ram_64b)) then + event_start_addr <= event_start_addr + event_size_ram_64b; + else + event_start_addr <= 0; + end if; + event_ready_flag <= '1'; + end if; + + + when MM_MAIN1 => + state_mm <= MM_MAIN; + if (config_start = '1') then + config_ready <= '0'; + if (events_in_ram = 0) then + state_mm <= MM_CONFIG; + end if; + end if; + if (event_ready_flag = '1') then + if (events_in_ram < max_events_ram) then + ram_write_ea <= '1'; + ram_start_addr <= conv_std_logic_vector(event_start_addr, RAM_ADDR_WIDTH_64B); + event_ready_flag <= '0'; + end if; + end if; + + if ((events_in_ram > 0) and (wiz_busy = '0')) then + if (package_index < number_of_packages) then + wiz_ram_start_addr <= conv_std_logic_vector(write_start_addr, RAM_ADDR_WIDTH_16B); + wiz_write_length <= conv_std_logic_vector(fifo_write_length (package_index), 17); + wiz_number_of_channels <= conv_std_logic_vector(fifo_channels_array (package_index), 4); + wiz_write_ea <= '1'; + wiz_ack_flag <= '0'; + if (package_index = 0) then + -- first package -> write header + wiz_write_header <= '1'; + else + wiz_write_header <= '0'; + end if; + if (package_index = (number_of_packages - 1)) then + -- last package -> write end-flag + wiz_write_end <= '1'; + else + wiz_write_end <= '0'; + end if; + else + events_in_ram <= events_in_ram - 1; + package_index <= 0; + end if; + end if; + + if ((wiz_ack = '1') and (wiz_ack_flag = '0')) then + wiz_ack_flag <= '1'; + wiz_write_ea <= '0'; + package_index <= package_index + 1; + if (package_index = (number_of_packages - 1)) then + -- next address + if ((write_start_addr + fifo_package_size_ram (package_index)) < (RAM_SIZE_16B - event_size_ram)) then + write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); + else + write_start_addr <= 0; + end if; + else + write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); + end if; + end if; -- wiz_ack + + end case; -- state_mm + end if; + end process mm; + + + +END ARCHITECTURE beha; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/memory_manager_beha.vhd.bak =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/memory_manager_beha.vhd.bak (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/memory_manager_beha.vhd.bak (revision 9841) @@ -0,0 +1,281 @@ +-- +-- VHDL Architecture FACT_FAD_lib.memory_manager.beha +-- +-- Created: +-- by - kai.UNKNOWN (E5PCXX) +-- at - 14:33:25 02.03.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use ieee.STD_LOGIC_UNSIGNED.all; + +library FACT_FAD_lib; +use FACT_FAD_lib.fad_definitions.all; + +-- library UNISIM; +-- use UNISIM.VComponents.all; +-- USE IEEE.NUMERIC_STD.all; + +-- RAM_ADDR_WIDTH_64B is used for +-- output ram_start_addr + +-- RAM_ADDR_WIDTH_16B is used for +-- output wiz_ram_start_addr + + +ENTITY memory_manager IS + generic( + RAM_ADDR_WIDTH_64B : integer := 12; + RAM_ADDR_WIDTH_16B : integer := 14 + ); + PORT( + clk : IN std_logic; + config_start : IN std_logic; + ram_write_ready : IN std_logic; + roi_array : IN roi_array_type; + ram_write_ea : OUT std_logic := '0'; + config_ready, config_started : OUT std_logic := '0'; + roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); + package_length : OUT std_logic_vector (15 downto 0) := (others => '0'); + wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0'); + wiz_write_length : OUT std_logic_vector (16 downto 0) := (others => '0'); + wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0'); + wiz_write_ea : OUT std_logic := '0'; + wiz_write_header : OUT std_logic := '0'; + wiz_write_end : OUT std_logic := '0'; + wiz_busy : IN std_logic; + ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') + ); + +-- Declarations + +END memory_manager ; + +-- +ARCHITECTURE beha OF memory_manager IS + +type state_mm_type is (MM_CONFIG, MAX_ROI, MAX_ROI1, MAX_ROI2, FIFO_CALC, RAM_CALC, RAM_CALC1, RAM_CALC2, MM_MAIN, MM_MAIN1); +signal state_mm : state_mm_type := MM_CONFIG; + +--type roi_array_type is array (0 to 35) of integer range 0 to 1024; +type roi_max_array_type is array (0 to 8) of integer range 0 to 1024; +type channel_size_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE; +type fifo_write_length_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE; +type fifo_channels_array_type is array (0 to 8) of integer range 0 to 9; +type fifo_package_size_ram_type is array (0 to 8) of integer range 0 to RAM_SIZE_16B; + +signal roi_max_array : roi_max_array_type := (others => 0); + +-- size of channel groups (16 bit) +signal channel_size : channel_size_type := (others => 0); +-- write length of packages (16 bit) +signal fifo_write_length : fifo_write_length_type := (others => 0); +-- number of channels per package +signal fifo_channels_array : fifo_channels_array_type := (others => 0); +-- size of packages in ram (16 bit) +signal fifo_package_size_ram : fifo_package_size_ram_type := (others => 0); +-- +signal event_size_ram : integer range 0 to RAM_SIZE_16B := 0; +signal event_size_ram_64b : integer range 0 to RAM_SIZE_64B := 0; +signal event_size : integer range 0 to RAM_SIZE_16B := 0; + +signal drs_id : integer range 0 to 4 := 0; +signal channel_id : integer range 0 to 9 := 0; +signal channel_index : integer range 0 to 9 := 0; +signal package_index : integer range 0 to 9 := 0; +signal number_of_packages : integer range 0 to 9 := 0; +signal max_events_ram, events_in_ram : integer range 0 to 2048; +signal event_start_addr : integer range 0 to (RAM_SIZE_64B - 1); +signal write_start_addr : integer range 0 to (RAM_SIZE_16B - 1); +signal event_ready_flag : std_logic := '0'; + +signal roi_index : integer range 0 to 45 := 0; +signal temp_roi : integer range 0 to 1024 := 0; + +BEGIN + + mm : process (clk) + begin + if rising_edge (clk) then + case state_mm is + + when MM_CONFIG => + if (config_start = '1') then + config_started <= '1'; + roi_max_array <= (others => 0); + channel_size <= (others => 0); + fifo_write_length <= (others => 0); + fifo_channels_array <= (others => 0); + event_size <= 0; + ram_write_ea <= '0'; + state_mm <= MAX_ROI; + end if; + + -- calculate max ROIs and channel sizes + when MAX_ROI => + roi_index <= (drs_id * 9) + channel_id; + state_mm <= MAX_ROI1; + when MAX_ROI1 => + temp_roi <= roi_array (roi_index); + state_mm <= MAX_ROI2; + when MAX_ROI2 => + if (channel_id < 9) then + if ( temp_roi > roi_max_array (channel_id)) then + roi_max_array (channel_id) <= temp_roi; + end if; + channel_size (channel_id) <= channel_size (channel_id) + temp_roi + 3; + drs_id <= drs_id + 1; + state_mm <= MAX_ROI; + if (drs_id = 3) then + drs_id <= 0; + channel_id <= channel_id + 1; + end if; + else + drs_id <= 0; + channel_id <= 0; + channel_size (0) <= channel_size (0) + PACKAGE_HEADER_LENGTH; + channel_size (8) <= channel_size (8) + PACKAGE_END_LENGTH; + state_mm <= FIFO_CALC; + end if; + + -- calculate number of channels that fit in FIFO + when FIFO_CALC => + if (channel_id < 9) then + if ((fifo_write_length (package_index) + channel_size (channel_id)) <= W5300_TX_FIFO_SIZE) then + fifo_write_length (package_index) <= fifo_write_length (package_index) + channel_size (channel_id); + fifo_channels_array (package_index) <= fifo_channels_array (package_index) + 1; + channel_id <= channel_id + 1; + event_size <= event_size + channel_size (channel_id); + else + package_index <= package_index + 1; + end if; + else + number_of_packages <= package_index + 1; + package_index <= 0; + channel_index <= 0; + channel_id <= 0; + fifo_package_size_ram <= (others => 0); + fifo_package_size_ram (0) <= PACKAGE_HEADER_LENGTH + 6; + event_size_ram <= 0; + event_size_ram_64b <= 0; + max_events_ram <= 0; + state_mm <= RAM_CALC; + end if; + + when RAM_CALC => + if (package_index < number_of_packages) then + if (channel_index < fifo_channels_array (package_index)) then + fifo_package_size_ram (package_index) <= fifo_package_size_ram (package_index) + ((roi_max_array (channel_id) + 3) * 4); + channel_index <= channel_index + 1; + channel_id <= channel_id + 1; + else + package_index <= package_index + 1; + event_size_ram <= event_size_ram + fifo_package_size_ram (package_index); + channel_index <= 0; + end if; + else + fifo_package_size_ram (package_index - 1) <= fifo_package_size_ram (package_index - 1) + 4; + event_size_ram <= event_size_ram + 4; -- Size of Event in RAM (16 Bit), + CRC + Endflag + 2 Spare + state_mm <= RAM_CALC1; + end if; + when RAM_CALC1 => + max_events_ram <= max_events_ram + 1; + if ((max_events_ram * event_size_ram) <= RAM_SIZE_16B) then + state_mm <= RAM_CALC1; + else + max_events_ram <= max_events_ram - 1; + state_mm <= RAM_CALC2; + end if; + when RAM_CALC2 => + event_size_ram_64b <= (event_size_ram / 4); + events_in_ram <= 0; + event_start_addr <= 0; + write_start_addr <= 0; + package_index <= 0; + channel_id <= 0; + ram_start_addr <= (others => '0'); + ram_write_ea <= '1'; + config_started <= '0'; + config_ready <= '1'; + package_length <= conv_std_logic_vector (event_size, 16); + for i in 0 to 8 loop + roi_max(i) <= conv_std_logic_vector(roi_max_array(i), 11); + end loop; + state_mm <= MM_MAIN; + + when MM_MAIN => + state_mm <= MM_MAIN1; + if ((ram_write_ready = '1') and (event_ready_flag = '0')) then + ram_write_ea <= '0'; + events_in_ram <= events_in_ram + 1; + if ((event_start_addr + event_size_ram_64b) < (RAM_SIZE_64B - event_size_ram_64b)) then + event_start_addr <= event_start_addr + event_size_ram_64b; + else + event_start_addr <= 0; + end if; + event_ready_flag <= '1'; + end if; + wiz_write_ea <= '0'; -- ????? + + when MM_MAIN1 => + state_mm <= MM_MAIN; + if (config_start = '1') then + config_ready <= '0'; + if (events_in_ram = 0) then + state_mm <= MM_CONFIG; + end if; + end if; + if (event_ready_flag = '1') then + if (events_in_ram < max_events_ram) then + ram_write_ea <= '1'; + -- ram_start_addr <= conv_std_logic_vector(event_start_addr, 12); + ram_start_addr <= conv_std_logic_vector(event_start_addr, RAM_ADDR_WIDTH_64B); + event_ready_flag <= '0'; + end if; + end if; + if ((events_in_ram > 0) and (wiz_busy = '0')) then + if (package_index < number_of_packages) then + -- wiz_ram_start_addr <= conv_std_logic_vector(write_start_addr, 14); + wiz_ram_start_addr <= conv_std_logic_vector(write_start_addr, RAM_ADDR_WIDTH_16B); + wiz_write_length <= conv_std_logic_vector(fifo_write_length (package_index), 17); + wiz_number_of_channels <= conv_std_logic_vector(fifo_channels_array (package_index), 4); + wiz_write_ea <= '1'; + package_index <= package_index + 1; + if (package_index = 0) then + -- first package -> write header + wiz_write_header <= '1'; + else + wiz_write_header <= '0'; + end if; + if (package_index = (number_of_packages - 1)) then + -- last package -> write end-flag + wiz_write_end <= '1'; + -- next address + if ((write_start_addr + event_size_ram + fifo_package_size_ram (package_index) ) < (RAM_SIZE_16B - event_size_ram)) then + --write_start_addr <= write_start_addr + event_size_ram; + write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); + else + write_start_addr <= 0; + end if; + else + write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); + wiz_write_end <= '0'; + end if; + else + events_in_ram <= events_in_ram - 1; + package_index <= 0; + end if; + end if; + + + end case; -- state_mm + end if; + end process mm; + + + +END ARCHITECTURE beha; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/spi_clock_gen_beha.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/spi_clock_gen_beha.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/spi_clock_gen_beha.vhd (revision 9841) @@ -0,0 +1,47 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_clock_generator.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 14:49:19 01.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY spi_clock_generator IS + GENERIC( + CLK_DIVIDER : integer := 25 --2 MHz @ 50 MHz + ); + PORT( + clk : IN std_logic; + sclk : OUT std_logic := '0' + ); +END spi_clock_generator ; + +ARCHITECTURE beha OF spi_clock_generator IS + +BEGIN + + spi_clk_proc: process (clk) + variable Z: integer range 0 to clk_divider - 1; + begin + if rising_edge(clk) then + if (Z < clk_divider - 1) then + Z := Z + 1; + else + Z := 0; + end if; + if (Z = 0) then + sclk <= '1'; + end if; + if (Z = clk_divider / 2) then + sclk <= '0'; + end if; + end if; + end process spi_clk_proc; + +END ARCHITECTURE beha; Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/spi_controller_beha.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/spi_controller_beha.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/spi_controller_beha.vhd (revision 9841) @@ -0,0 +1,117 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_controller.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 10:37:20 12.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY spi_controller IS + PORT( + clk : IN std_logic; + miso : INOUT std_logic := 'Z'; + mosi : OUT std_logic := '0'; + dac_id : IN std_logic_vector (2 DOWNTO 0); + sensor_id : IN std_logic_vector (1 downto 0); + data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + dac_cs : OUT std_logic := '1'; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0) := (others => '1'); + dac_start : IN std_logic; + dac_ready : OUT std_logic := '0'; + sensor_start : IN std_logic; + sensor_valid : OUT std_logic := '0' + ); +END spi_controller ; + +ARCHITECTURE beha OF spi_controller IS + + type TYPE_SPI_STATE is (SPI_IDLE, SPI_LOAD_DAC, SPI_LOAD_COMMAND, SPI_GET_TEMP); + + signal spi_state : TYPE_SPI_STATE := SPI_IDLE; + signal spi_cycle_cnt : integer range 0 to 25 := 0; + signal shift_reg : std_logic_vector (23 downto 0) := (others => '0'); + signal data_reg : std_logic_vector (15 downto 0) := (others => '0'); + +BEGIN + + spi_write_proc: process (clk) + begin + if falling_edge(clk) then + dac_cs <= '1'; + sensor_cs <= (others => '1'); + miso <= 'Z'; + mosi <= '0'; + data <= (others => 'Z'); + case spi_state is + when SPI_IDLE => + if (dac_start = '1') then + dac_ready <= '0'; + spi_state <= SPI_LOAD_COMMAND; + elsif (sensor_start = '1') then + sensor_valid <= '0'; + spi_state <= SPI_LOAD_COMMAND; + end if; + + when SPI_LOAD_COMMAND => + spi_cycle_cnt <= 0; + if (sensor_start = '1') then + shift_reg <= X"C1" & X"0000"; -- command: Temperature register read + spi_state <= SPI_GET_TEMP; + elsif (dac_start = '1') then + shift_reg <= "0011" & '0' & dac_id & data; + spi_state <= SPI_LOAD_DAC; + end if; + + -- start temperature sensor read + when SPI_GET_TEMP => + if (spi_cycle_cnt < 24) then -- must be on more cause MAX6662 provides data on falling edge + sensor_cs(conv_integer(sensor_id)) <= '0'; + sensor_valid <= '0'; + spi_cycle_cnt <= spi_cycle_cnt + 1; + if (spi_cycle_cnt < 9) then -- send data + miso <= shift_reg(23); + shift_reg <= shift_reg(22 downto 0) & shift_reg(23); + end if; + else + data <= data_reg; + sensor_valid <= '1'; + spi_state <= SPI_IDLE; + end if; + + -- start loading DACs + when SPI_LOAD_DAC => + dac_cs <= '0'; + if (spi_cycle_cnt < 24) then + mosi <= shift_reg(23); + shift_reg <= shift_reg(22 downto 0) & shift_reg(23); + dac_ready <= '0'; + spi_cycle_cnt <= spi_cycle_cnt + 1; + spi_state <= SPI_LOAD_DAC; + else + dac_cs <= '1'; + dac_ready <= '1'; + spi_state <= SPI_IDLE; + end if; + end case; + end if; + end process spi_write_proc; + + -- MAX6662 input must be read with rising edge + spi_read_proc: process (clk) + begin + if rising_edge(clk) then + if (spi_state = SPI_GET_TEMP and spi_cycle_cnt >= 9) then + data_reg(0) <= miso; + data_reg(15 downto 1) <= data_reg(14 downto 0); + end if; + end if; + end process spi_read_proc; + +END ARCHITECTURE beha; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/spi_distributor_beha.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/spi_distributor_beha.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/spi_distributor_beha.vhd (revision 9841) @@ -0,0 +1,150 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_distributor.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 09:24:21 23.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +ENTITY spi_distributor IS + +-- TEMP_MEASUREMENT_BEAT * clk ist the measurement period of the +-- Temperature measurement +-- e.g. 5*10**6 means every second + + GENERIC( + TEMP_MEASUREMENT_BEAT : integer := 5*10**6 + ); + + PORT( + clk : IN std_logic; -- 50MHz + config_start : IN std_logic; + config_ready, config_started : OUT std_logic := '0'; + sensor_valid : OUT std_logic := '0'; + dac_array : IN dac_array_type; + sensor_array : OUT sensor_array_type; + dac_config_start : OUT std_logic := '0'; + dac_config_ready : IN std_logic; + sensor_read_start : OUT std_logic := '0'; + sensor_read_valid : IN std_logic; + dac_id : OUT std_logic_vector(2 downto 0) := (others => '0'); + sensor_id : OUT std_logic_vector(1 downto 0) := (others => '0'); + data : INOUT std_logic_vector(15 downto 0) := (others => 'Z') + ); +END ENTITY spi_distributor; + +ARCHITECTURE beha OF spi_distributor IS + + type TYPE_SPI_DISTRIBUTION_STATE is (INIT, IDLE, READ_SENSOR, CONFIG_DAC); + + signal spi_distr_state : TYPE_SPI_DISTRIBUTION_STATE := INIT; + signal int_sensor_read_start : std_logic := '0'; + signal int_sensor_valid : std_logic := '0'; + signal int_sensor_array : sensor_array_type; + signal sensor_id_cnt : integer range 0 to 4 := 0; + signal dac_id_cnt : integer range 0 to 7 := 0; + + +BEGIN + + spi_distribute_proc: process (clk) + begin + + if rising_edge(clk) then + data <= (others => 'Z'); + case spi_distr_state is + when INIT => + data <= (others => 'Z'); + int_sensor_valid <= '0'; + spi_distr_state <= READ_SENSOR; + when IDLE => + if (int_sensor_valid = '1') then + sensor_array <= int_sensor_array; + sensor_valid <= '1'; + end if; + data <= (others => 'Z'); + -- start DAC configuration + if (config_start = '1' AND int_sensor_valid = '1') then + config_started <= '1'; + config_ready <= '0'; + dac_config_start <= '1'; + dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); + data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); + spi_distr_state <= CONFIG_DAC; + -- start temperature sensor reading + elsif (dac_config_ready <= '1' AND int_sensor_read_start = '1') then + int_sensor_valid <= '0'; + sensor_read_start <= '1'; + sensor_id <= conv_std_logic_vector(sensor_id_cnt, sensor_id'length); + spi_distr_state <= READ_SENSOR; + end if; + + -- sensor reading + when READ_SENSOR => + sensor_read_start <= '1'; + sensor_id <= conv_std_logic_vector(sensor_id_cnt, sensor_id'length); + if (sensor_read_valid = '1') then + int_sensor_array(sensor_id_cnt) <= conv_integer(data); + sensor_read_start <= '0'; + if (sensor_id_cnt < 3) then + sensor_id_cnt <= sensor_id_cnt + 1; + sensor_read_start <= '1'; + spi_distr_state <= READ_SENSOR; + else + sensor_id_cnt <= 0; + sensor_valid <= '0'; + int_sensor_valid <= '1'; + spi_distr_state <= IDLE; + end if; + end if; + + -- DAC configuration + when CONFIG_DAC => + dac_config_start <= '1'; + dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); + data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); + if (dac_config_ready = '1') then + dac_config_start <= '0'; + if (dac_id_cnt < 7) then + dac_id_cnt <= dac_id_cnt + 1; + dac_config_start <= '1'; + spi_distr_state <= CONFIG_DAC; + else + dac_id_cnt <= 0; + config_started <= '0'; + config_ready <= '1'; + spi_distr_state <= IDLE; + end if; + end if; + end case; + end if; + + end process spi_distribute_proc; + + sensor_tmr_proc: process (clk) + variable Z: integer range 0 to (TEMP_MEASUREMENT_BEAT - 1); + begin + if rising_edge(clk) then + int_sensor_read_start <= '0'; + if (Z < TEMP_MEASUREMENT_BEAT - 1) then + Z := Z + 1; + else + Z := 0; + end if; + if (Z = 0) then + int_sensor_read_start <= '1'; + end if; + end if; + end process sensor_tmr_proc; + + +END ARCHITECTURE beha; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/spi_interface_struct.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/spi_interface_struct.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/spi_interface_struct.vhd (revision 9841) @@ -0,0 +1,177 @@ +-- VHDL Entity FACT_FAD_lib.spi_interface.symbol +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 12:04:03 23.06.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +ENTITY spi_interface IS + PORT( + clk_50MHz : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + config_ready : OUT std_logic; + config_started : OUT std_logic := '0'; + dac_cs : OUT std_logic; + mosi : OUT std_logic := '0'; + sclk : OUT std_logic; + sensor_array : OUT sensor_array_type; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0); + sensor_ready : OUT std_logic; + miso : INOUT std_logic + ); + +-- Declarations + +END spi_interface ; + +-- +-- VHDL Architecture FACT_FAD_lib.spi_interface.struct +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 12:04:03 23.06.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; +USE IEEE.NUMERIC_STD.ALL; + +LIBRARY FACT_FAD_lib; + +ARCHITECTURE struct OF spi_interface IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL dac_config_ready : std_logic; + SIGNAL dac_config_start : std_logic; + SIGNAL dac_id : std_logic_vector(2 DOWNTO 0); + SIGNAL data : std_logic_vector(15 DOWNTO 0); + SIGNAL sensor_id : std_logic_vector(1 DOWNTO 0); + SIGNAL sensor_start : std_logic; + SIGNAL sensor_valid : std_logic; + + -- Implicit buffer signal declarations + SIGNAL sclk_internal : std_logic; + + + -- Component Declarations + COMPONENT spi_clock_generator + GENERIC ( + CLK_DIVIDER : integer := 25 --2 MHz @ 50 MHz + ); + PORT ( + clk : IN std_logic; + sclk : OUT std_logic := '0' + ); + END COMPONENT; + COMPONENT spi_controller + PORT ( + clk : IN std_logic; + dac_id : IN std_logic_vector (2 DOWNTO 0); + dac_start : IN std_logic; + sensor_id : IN std_logic_vector (1 DOWNTO 0); + sensor_start : IN std_logic; + dac_cs : OUT std_logic := '1'; + dac_ready : OUT std_logic := '0'; + mosi : OUT std_logic := '0'; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0) := (others => '1'); + sensor_valid : OUT std_logic := '0'; + data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + miso : INOUT std_logic := 'Z' + ); + END COMPONENT; + COMPONENT spi_distributor + GENERIC ( + TEMP_MEASUREMENT_BEAT : integer := 5*10**6 + ); + PORT ( + clk : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + dac_config_ready : IN std_logic; + sensor_read_valid : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0'; + dac_config_start : OUT std_logic := '0'; + dac_id : OUT std_logic_vector (2 DOWNTO 0) := (others => '0'); + sensor_array : OUT sensor_array_type; + sensor_id : OUT std_logic_vector (1 DOWNTO 0) := (others => '0'); + sensor_read_start : OUT std_logic := '0'; + sensor_valid : OUT std_logic := '0'; + data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z') + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : spi_clock_generator USE ENTITY FACT_FAD_lib.spi_clock_generator; + FOR ALL : spi_controller USE ENTITY FACT_FAD_lib.spi_controller; + FOR ALL : spi_distributor USE ENTITY FACT_FAD_lib.spi_distributor; + -- pragma synthesis_on + + +BEGIN + + -- Instance port mappings. + I_spi_clkgen : spi_clock_generator + GENERIC MAP ( + CLK_DIVIDER => 25 --2 MHz @ 50 MHz + ) + PORT MAP ( + clk => clk_50MHz, + sclk => sclk_internal + ); + I_spi_controller : spi_controller + PORT MAP ( + clk => sclk_internal, + miso => miso, + mosi => mosi, + dac_id => dac_id, + sensor_id => sensor_id, + data => data, + dac_cs => dac_cs, + sensor_cs => sensor_cs, + dac_start => dac_config_start, + dac_ready => dac_config_ready, + sensor_start => sensor_start, + sensor_valid => sensor_valid + ); + I_spi_distributor : spi_distributor + GENERIC MAP ( + TEMP_MEASUREMENT_BEAT => 5*10**6 + ) + PORT MAP ( + clk => sclk_internal, + config_start => config_start, + config_ready => config_ready, + config_started => config_started, + sensor_valid => sensor_ready, + dac_array => dac_array, + sensor_array => sensor_array, + dac_config_start => dac_config_start, + dac_config_ready => dac_config_ready, + sensor_read_start => sensor_start, + sensor_read_valid => sensor_valid, + dac_id => dac_id, + sensor_id => sensor_id, + data => data + ); + + -- Implicit buffered output assignments + sclk <= sclk_internal; + +END struct; Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/trigger_counter_beha.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/trigger_counter_beha.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/trigger_counter_beha.vhd (revision 9841) @@ -0,0 +1,43 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.trigger_counter.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 14:36:14 10.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +entity trigger_counter is + port( + trigger_id : out std_logic_vector(47 downto 0); + trigger : in std_logic; + clk : in std_logic + ); + +end entity trigger_counter; + +architecture beha of trigger_counter is + + signal temp_id : integer := 0; + +begin + + trigger_id <= X"AA55" & conv_std_logic_vector(temp_id, 32); + + trigger_incr_proc: process(clk) + begin + if rising_edge(clk) then + if (trigger = '1') then + temp_id <= temp_id + 1; + end if; + end if; + end process trigger_incr_proc; + +end architecture beha; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/trigger_shaper_beha.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/trigger_shaper_beha.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/trigger_shaper_beha.vhd (revision 9841) @@ -0,0 +1,51 @@ +-- +-- VHDL Architecture FACT_FAD_test_devices_lib.trigger_shaper.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 11:59:20 28.01.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.NUMERIC_STD.all; + +entity trigger_shaper is + port( + trigger_in : in std_logic; + trigger_out : out std_logic; + clk : in std_logic; + rst : in std_logic + ); +end entity trigger_shaper; + +architecture beha of trigger_shaper is + +-- signal temp_trig : std_logic_vector(3 downto 0); + signal temp_trig : std_logic_vector(1 downto 0); + signal trigger_flag : std_logic; + signal temp_signal : std_logic; + +begin + + test_proc : process (clk, rst) + begin + if (rst = '1') then + trigger_out <= '0'; + trigger_flag <= '0'; + temp_signal <= '0'; + elsif rising_edge(clk) then +-- temp_trig <= temp_trig(2 downto 0) & trigger_in; +-- trigger_out <= not temp_trig(3) and temp_trig(2); + temp_trig <= temp_trig(0) & trigger_in; + temp_signal <= not temp_trig(1) and temp_trig(0); + trigger_out <= temp_signal and not trigger_flag; + if (temp_signal = '1') then + trigger_flag <= '1'; + end if; + end if; + end process test_proc; + +end architecture beha; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 9841) @@ -0,0 +1,818 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11:48:48 11/10/2009 +-- Design Name: +-- Module Name: w5300_modul - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library FACT_FAD_lib; +use FACT_FAD_lib.fad_definitions.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +ENTITY w5300_modul IS + generic( + RAM_ADDR_WIDTH : integer := 14 + ); + PORT( + clk : IN std_logic; + wiz_reset : OUT std_logic := '1'; + addr : OUT std_logic_vector (9 DOWNTO 0); + data : INOUT std_logic_vector (15 DOWNTO 0); + cs : OUT std_logic := '1'; + wr : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + rd : OUT std_logic := '1'; + int : IN std_logic; + write_length : IN std_logic_vector (16 DOWNTO 0); + ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + ram_data : IN std_logic_vector (15 DOWNTO 0); + ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + data_valid : IN std_logic; + data_valid_ack : OUT std_logic := '0'; + busy : OUT std_logic := '1'; + write_header_flag, write_end_flag : IN std_logic; + fifo_channels : IN std_logic_vector (3 downto 0); + s_trigger : OUT std_logic := '0'; + new_config : OUT std_logic := '0'; + config_started : in std_logic; + config_addr : out std_logic_vector (7 downto 0); + config_data : inout std_logic_vector (15 downto 0) := (others => 'Z'); + config_wr_en : out std_logic := '0'; + config_rd_en : out std_logic := '0'; + config_busy : in std_logic; + + + + denable : out std_logic := '0'; -- default domino wave off + dwrite_enable : out std_logic := '0'; -- default DWRITE low. + sclk_enable : out std_logic := '1' -- default DWRITE HIGH. + ); + +-- Declarations + +END w5300_modul ; + +architecture Behavioral of w5300_modul is + +type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, + INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, + SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, CHK_RECEIVED, READ_DATA); +type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, + WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3); +type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); +type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); +type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END); + +signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; + +signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0'); +signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0'); +signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0'); +signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + +signal state_init, next_state , next_state_tmp : state_init_type := RESET; +signal count : std_logic_vector (2 downto 0) := "000"; +signal state_write : state_write_type := WR_START; +signal state_interrupt_1 : state_interrupt_1_type := IR1_01; +signal state_interrupt_2 : state_interrupt_2_type := IR2_01; +signal state_read_data : state_read_data_type := RD_1; + +signal interrupt_ignore : std_logic := '1'; +signal int_flag : std_logic := '0'; +signal ram_access : std_logic := '0'; + +signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0'); +signal data_cnt : integer := 0; +signal drs_cnt : integer :=0; +signal channel_cnt : integer range 0 to 9 :=0; +signal socket_cnt : std_logic_vector (2 downto 0) := "000"; +signal roi_max : std_logic_vector (10 downto 0); +signal data_end : integer := 0; + +signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0'); +signal write_length_bytes : std_logic_vector (16 downto 0); + +signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0'); +signal chk_recv_cntr : integer range 0 to 10000 := 0; +signal rx_packets_cnt : std_logic_vector (15 downto 0); +signal next_packet_data : std_logic := '0'; +signal new_config_flag : std_logic := '0'; + +signal trigger_stop : std_logic := '1'; + +signal local_write_length : std_logic_vector (16 DOWNTO 0); +signal local_ram_start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); +signal local_ram_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0); +signal local_socket_nr : std_logic_vector (2 DOWNTO 0); +signal local_write_header_flag, local_write_end_flag : std_logic; +signal local_fifo_channels : std_logic_vector (3 downto 0); + +begin + + --synthesis translate_off + RST_TIME <= X"00120"; + --synthesis translate_on + + w5300_init_proc : process (clk, int) + begin + + if rising_edge (clk) then + + -- Interrupt low + if (int = '0') and (interrupt_ignore = '0') then + case state_interrupt_1 is + when IR1_01 => + int_flag <= '1'; + busy <= '1'; + state_interrupt_1 <= IR1_02; + when IR1_02 => + state_interrupt_1 <= IR1_03; + when IR1_03 => + state_init <= INTERRUPT; + socket_cnt <= "000"; + ram_access <= '0'; + zaehler <= X"00000"; + count <= "000"; + int_flag <= '0'; + interrupt_ignore <= '1'; + state_interrupt_1 <= IR1_04; + when others => + null; + end case; + end if; -- int = '0' + + if int_flag = '0' then + case state_init is + -- Interrupt + when INTERRUPT => + case state_interrupt_2 is + when IR2_01 => + par_addr <= W5300_IR; + state_init <= READ_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_02; + when IR2_02 => + if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt + state_interrupt_2 <= IR2_03; + else + socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then + state_interrupt_2 <= IR2_06; + else + state_interrupt_2 <= IR2_02; + end if; + end if; + when IR2_03 => + par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register + state_init <= READ_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_04; + when IR2_04 => + par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; + par_data <= data_read; -- clear Interrupts + state_init <= WRITE_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_05; + when IR2_05 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0010"; -- CLOSE + state_init <= WRITE_REG; + next_state <= INTERRUPT; + socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then + state_interrupt_2 <= IR2_06; + else + state_interrupt_2 <= IR2_01; + end if; + + when IR2_06 => + state_interrupt_1 <= IR1_01; + state_interrupt_2 <= IR2_01; + socket_cnt <= "000"; + state_init <= RESET; + end case; + + -- reset W5300 + when RESET => + zaehler <= zaehler + 1; + wiz_reset <= '0'; + led <= X"FF"; + if (zaehler >= X"00064") then -- wait 2µs + wiz_reset <= '1'; + end if; + if (zaehler = RST_TIME) then -- wait 10ms + zaehler <= X"00000"; + socket_cnt <= "000"; + count <= "000"; + ram_access <= '0'; + interrupt_ignore <= '0'; + rd <= '1'; + wr <= '1'; + cs <= '1'; + state_write <= WR_START; + state_init <= INIT; + end if; + + -- Init + when INIT => + par_addr <= W5300_MR; + par_data <= X"0000"; + state_init <= WRITE_REG; + next_state <= IM; + + -- Interrupt Mask + when IM => + par_addr <= W5300_IMR; + par_data <= X"00FF"; -- S0-S7 Interrupts + state_init <= WRITE_REG; + next_state <= MT; + + -- Memory Type + when MT => + par_addr <= W5300_MTYPER; + par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer + state_init <= WRITE_REG; + next_state <= STX; + + -- Socket TX Memory Size + when STX => + par_data <= X"0F0F"; -- 15K TX + + par_addr <= W5300_TMS01R; + state_init <=WRITE_REG; + next_state <= STX1; + when STX1 => + par_addr <= W5300_TMS23R; + state_init <=WRITE_REG; + next_state <= STX2; + when STX2 => + par_addr <= W5300_TMS45R; + state_init <=WRITE_REG; + next_state <= STX3; + when STX3 => + par_addr <= W5300_TMS67R; + state_init <=WRITE_REG; + next_state <= SRX; + + -- Socket RX Memory Size + when SRX => + par_data <= X"0101"; -- 1K RX + + par_addr <= W5300_RMS01R; + state_init <=WRITE_REG; + next_state <= SRX1; + when SRX1 => + par_addr <= W5300_RMS23R; + state_init <=WRITE_REG; + next_state <= SRX2; + when SRX2 => + par_addr <= W5300_RMS45R; + state_init <=WRITE_REG; + next_state <= SRX3; + when SRX3 => + par_addr <= W5300_RMS67R; + state_init <=WRITE_REG; + next_state <= MAC; + + -- MAC + when MAC => + par_addr <= W5300_SHAR; + par_data <= MAC_ADDRESS (0); + state_init <= WRITE_REG; + next_state <= MAC1; + when MAC1 => + par_addr <= W5300_SHAR + 2; + par_data <= MAC_ADDRESS (1); + state_init <= WRITE_REG; + next_state <= MAC2; + when MAC2 => + par_addr <= W5300_SHAR + 4; + par_data <= MAC_ADDRESS (2); + state_init <= WRITE_REG; + next_state <= GW; + + -- Gateway + when GW => + par_addr <= W5300_GAR; + par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8); + par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8); + state_init <= WRITE_REG; + next_state <= GW1; + when GW1 => + par_addr <= W5300_GAR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8); + par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8); + state_init <= WRITE_REG; + next_state <= SNM; + + -- Subnet Mask + when SNM => + par_addr <= W5300_SUBR; + par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8); + par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8); + state_init <= WRITE_REG; + next_state <= SNM1; + when SNM1 => + par_addr <= W5300_SUBR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8); + par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8); + state_init <= WRITE_REG; + next_state <= IP; + -- Own IP-Address + when IP => + par_addr <= W5300_SIPR; + par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8); + par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8); + state_init <= WRITE_REG; + next_state <= IP1; + when IP1 => + par_addr <= W5300_SIPR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8); + par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8); + state_init <= WRITE_REG; + next_state <= TIMEOUT; + when TIMEOUT => + par_addr <= W5300_RTR; + par_data <= X"07D0"; -- 0x07D0 = 200ms + state_init <= WRITE_REG; + next_state <= RETRY; + when RETRY => + par_addr <= W5300_RCR; + par_data <= X"0008"; + state_init <= WRITE_REG; + next_state <= SI; + + -- Socket Init + when SI => + par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC; + par_data <= X"0101"; -- ALIGN, TCP + state_init <= WRITE_REG; + next_state <= SI1; + -- Sx Interrupt Mask + when SI1 => + par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC; + par_data <= X"000A"; -- TIMEOUT, DISCON + state_init <= WRITE_REG; + next_state <= SI2; + when SI2 => + par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC; + par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16); + state_init <= WRITE_REG; + next_state <= SI3; + when SI3 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0001"; -- OPEN + state_init <= WRITE_REG; + next_state <= SI4; + when SI4 => + par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; + state_init <= READ_REG; + next_state <= SI5; + when SI5 => + if (data_read (7 downto 0) = X"13") then -- is open? + state_init <= SI6; + else + state_init <= SI4; + end if; + when SI6 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0002"; -- LISTEN + state_init <= WRITE_REG; + socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then + socket_cnt <= "000"; + next_state <= ESTABLISH; -- All Sockets open + else + next_state <= SI; -- Next Socket + end if; + -- End Socket Init + + when ESTABLISH => + par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; + state_init <= READ_REG; + next_state <= EST1; + when EST1 => + led <= data_read (7 downto 0); + case data_read (7 downto 0) is + when X"17" => -- established + if (socket_cnt = 7) then + socket_cnt <= "000"; + busy <= '0'; + state_init <= MAIN; + else + socket_cnt <= socket_cnt + 1; + state_init <= ESTABLISH; + end if; + when others => + state_init <= ESTABLISH; + end case; + + when CONFIG => + led <= X"F0"; + new_config <= '1'; + if (config_started = '1') then + led <= X"0F"; + new_config <= '0'; + busy <= '0'; + state_init <= MAIN; + end if; + + -- main "loop" + when MAIN => + if (trigger_stop = '1') then + s_trigger <= '0'; + end if; + if (chk_recv_cntr = 1000) then + chk_recv_cntr <= 0; + state_read_data <= RD_1; + state_init <= READ_DATA; + busy <= '1'; + else + busy <= '0'; + data_valid_ack <= '0'; + chk_recv_cntr <= chk_recv_cntr + 1; + if (data_valid = '1') then + data_valid_ack <= '1'; + local_write_length <= write_length; + local_ram_start_addr <= ram_start_addr; + local_ram_addr <= (others => '0'); + local_write_header_flag <= write_header_flag; + local_write_end_flag <= write_end_flag; + local_fifo_channels <= fifo_channels; + next_state <= MAIN; + state_init <= WRITE_DATA; + busy <= '1'; + end if; + end if; + + -- read data from socket 0 + when READ_DATA => + case state_read_data is + when RD_1 => + par_addr <= W5300_S0_RX_RSR; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_2; + when RD_2 => + socket_rx_received (31 downto 16) <= data_read; + par_addr <= W5300_S0_RX_RSR + X"2"; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_3; + when RD_3 => + socket_rx_received (15 downto 0) <= data_read; + state_read_data <= RD_4; + when RD_4 => + if (socket_rx_received (16 downto 0) > ('0' & X"000")) then + rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2 + state_read_data <= RD_5; + else + busy <= '0'; + state_init <= MAIN; + end if; + when RD_5 => + if (rx_packets_cnt > 0) then + rx_packets_cnt <= rx_packets_cnt - '1'; + par_addr <= W5300_S0_RX_FIFOR; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_6; + else + state_read_data <= RD_END; +-- if (new_config_flag = '1') then +-- new_config_flag <= '0'; +-- state_init <= CONFIG; +-- else +-- busy <= '0'; +-- state_init <= MAIN; +-- end if; + end if; + when RD_6 => + led <= data_read (15 downto 8); + -- read command + if (next_packet_data = '0') then + case data_read (15 downto 8) is + when CMD_TRIGGER => + trigger_stop <= '1'; + s_trigger <= '1'; + state_read_data <= RD_WAIT; + when CMD_DWRITE_RUN => + dwrite_enable <= '1'; + state_read_data <= RD_WAIT; + when CMD_DWRITE_STOP => + dwrite_enable <= '0'; + state_read_data <= RD_WAIT; + when CMD_SCLK_ON => + sclk_enable <= '1'; + state_read_data <= RD_WAIT; + when CMD_SCLK_OFF => + sclk_enable <= '0'; + state_read_data <= RD_WAIT; + when CMD_DENABLE => + denable <= '1'; + state_read_data <= RD_WAIT; + when CMD_DDISABLE => + denable <= '0'; + state_read_data <= RD_WAIT; + when CMD_TRIGGER_C => + trigger_stop <= '0'; + s_trigger <= '1'; + state_read_data <= RD_WAIT; + when CMD_TRIGGER_S => + trigger_stop <= '1'; + state_read_data <= RD_WAIT; + when CMD_WRITE => + next_packet_data <= '1'; + config_addr <= data_read (7 downto 0); + state_read_data <= RD_5; + when others => + state_read_data <= RD_5; + end case; + -- read data + else + if (config_busy = '0') then + config_data <= data_read; + config_wr_en <= '1'; + new_config_flag <= '1'; + next_packet_data <= '0'; + state_read_data <= RD_WAIT; + end if; + end if; + when RD_WAIT => + state_read_data <= RD_WAIT1; + when RD_WAIT1 => + config_data <= (others => 'Z'); + config_wr_en <= '0'; + state_read_data <= RD_5; + when RD_END => + par_addr <= W5300_S0_CR; + par_data <= X"0040"; -- RECV + state_init <= WRITE_REG; + if (new_config_flag = '1') then + new_config_flag <= '0'; + next_state <= CONFIG; + else +-- busy <= '0'; + next_state <= MAIN; + end if; + + end case; -- state_data_read + + + + when WRITE_DATA => + case state_write is + when WR_START => + if (local_write_header_flag = '1') then + ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ???? + end if; + state_write <= WR_WAIT1; + when WR_WAIT1 => + state_write <= WR_LENGTH; + when WR_LENGTH => + if (local_write_header_flag = '1') then + local_socket_nr <= ram_data (2 downto 0); + end if; + next_state_tmp <= next_state; + write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2) + data_cnt <= 0; + state_write <= WR_01; + -- Check FIFO Size + when WR_01 => + par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC; + state_init <= READ_REG; + next_state <= WRITE_DATA; + state_write <= WR_02; + when WR_02 => + socket_tx_free (31 downto 16) <= data_read; + par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2"; + state_init <= READ_REG; + next_state <= WRITE_DATA; + state_write <= WR_03; + when WR_03 => + socket_tx_free (15 downto 0) <= data_read; + state_write <= WR_04; + when WR_04 => + if (socket_tx_free (16 downto 0) < write_length_bytes) then + state_write <= WR_01; + else + if (local_write_header_flag = '1') then + state_write <= WR_FIFO; + else + state_write <= WR_ADC; + end if; + end if; + + -- Fill FIFO + + -- Write Header + when WR_FIFO => + ram_addr <= local_ram_start_addr + local_ram_addr; + state_write <= WR_FIFO1; + when WR_FIFO1 => + data_cnt <= data_cnt + 1; + if (data_cnt < PACKAGE_HEADER_LENGTH) then --??? + local_ram_addr <= local_ram_addr + 1; + if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words + local_ram_addr <= local_ram_addr + 2; + end if; + if (data_cnt = 9) then -- skip empty words + local_ram_addr <= local_ram_addr + 4; + end if; + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + ram_access <= '1'; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_FIFO; + else + state_write <= WR_ADC; + end if; + -- End Write Header + + -- Write ADC-Data + ---- Start... + when WR_ADC => + adc_data_addr <= local_ram_start_addr + local_ram_addr; + drs_cnt <= 0; + channel_cnt <= 1; + data_cnt <= 0; + roi_max <= (others => '0'); + data_end <= 3; + state_write <= WR_ADC1; + + ---- Write Channel + when WR_ADC1 => + -- read ROI and set end of Channel-Data + if (data_cnt = 3) then + data_end <= conv_integer (ram_data) + 3; + if (ram_data > roi_max) then + roi_max <= ram_data (10 downto 0); + end if; + end if; + ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4); + state_write <= WR_ADC2; + when WR_ADC2 => + if (data_cnt < data_end) then + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + ram_access <= '1'; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + data_cnt <= data_cnt + 1; + state_write <= WR_ADC1; + else + -- Next DRS + if (drs_cnt < 3) then + drs_cnt <= drs_cnt + 1; + data_cnt <= 0; + data_end <= 3; + state_write <= WR_ADC1; + else + -- Next Channel + if (channel_cnt < local_fifo_channels) then + channel_cnt <= channel_cnt + 1; + roi_max <= (others => '0'); + drs_cnt <= 0; + data_cnt <= 0; + data_end <= 3; + adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4); + state_write <= WR_ADC1; + else + -- Ready + if (local_write_end_flag = '1') then + state_write <= WR_ENDFLAG; + else + state_write <= WR_05; + end if; + end if; + end if; + end if; + -- End Write ADC-Data + + -- Write End Package Flag + when WR_ENDFLAG => + ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4); + state_write <= WR_ENDFLAG1; + when WR_ENDFLAG1 => + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + ram_access <= '1'; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_ENDFLAG2; + when WR_ENDFLAG2 => + ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1; + state_write <= WR_ENDFLAG3; + when WR_ENDFLAG3 => + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_05; + + -- End Write End Package Flag + + --Send FIFO + when WR_05 => + ram_access <= '0'; + par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC; + par_data <= (0 => write_length_bytes (16), others => '0'); + state_init <= WRITE_REG; + state_write <= WR_06; + when WR_06 => + par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2"; + par_data <= write_length_bytes (15 downto 0); + state_init <= WRITE_REG; + state_write <= WR_07; + when WR_07 => + par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC; + par_data <= X"0020"; -- Send + state_init <= WRITE_REG; + state_write <= WR_08; + when others => +-- busy <= '0'; + state_init <= next_state_tmp; + state_write <= WR_START; + end case; + -- End WRITE_DATA + + when READ_REG => + case count is + when "000" => + cs <= '0'; + rd <= '0'; + wr <= '1'; + data <= (others => 'Z'); -- !!!!!!!!!! + count <= "001"; + addr <= par_addr; + when "001" => + count <= "010"; + when "010" => + count <= "100"; + when "100" => + data_read <= data; + count <= "110"; + when "110" => + count <= "111"; + when "111" => + cs <= '1'; + rd <= '1'; + count <= "000"; + state_init <= next_state; + when others => + null; + end case; + + when WRITE_REG => + case count is + when "000" => + cs <= '0'; + wr <= '0'; + rd <= '1'; + addr <= par_addr; + if (ram_access = '1') then + data <= ram_data; + else + data <= par_data; + end if; + count <= "100"; + when "100" => + count <= "101"; + when "101" => + count <= "110"; + when "110" => + cs <= '1'; + wr <= '1'; + state_init <= next_state; + count <= "000"; + when others => + null; + end case; + + when others => + null; + end case; + end if; -- int_flag = '0' + + end if; -- rising_edge (clk) + + end process w5300_init_proc; + +end Behavioral; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd.bak =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd.bak (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd.bak (revision 9841) @@ -0,0 +1,812 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11:48:48 11/10/2009 +-- Design Name: +-- Module Name: w5300_modul - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library FACT_FAD_lib; +use FACT_FAD_lib.fad_definitions.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +ENTITY w5300_modul IS + generic( + RAM_ADDR_WIDTH : integer := 14 + ); + PORT( + clk : IN std_logic; + wiz_reset : OUT std_logic := '1'; + addr : OUT std_logic_vector (9 DOWNTO 0); + data : INOUT std_logic_vector (15 DOWNTO 0); + cs : OUT std_logic := '1'; + wr : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + rd : OUT std_logic := '1'; + int : IN std_logic; + write_length : IN std_logic_vector (16 DOWNTO 0); + ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + ram_data : IN std_logic_vector (15 DOWNTO 0); + ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + data_valid : IN std_logic; + data_valid_ack : OUT std_logic := '0'; + busy : OUT std_logic := '1'; + write_header_flag, write_end_flag : IN std_logic; + fifo_channels : IN std_logic_vector (3 downto 0); + s_trigger : OUT std_logic := '0'; + new_config : OUT std_logic := '0'; + config_started : in std_logic; + config_addr : out std_logic_vector (7 downto 0); + config_data : inout std_logic_vector (15 downto 0) := (others => 'Z'); + config_wr_en : out std_logic := '0'; + config_rd_en : out std_logic := '0'; + config_busy : in std_logic; + + + + denable : out std_logic := '0'; -- default domino wave off + dwrite_enable : out std_logic := '0'; -- default DWRITE low. + sclk_enable : out std_logic := '1' -- default DWRITE HIGH. + ); + +-- Declarations + +END w5300_modul ; + +architecture Behavioral of w5300_modul is + +type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, + INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, + SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, CHK_RECEIVED, READ_DATA); +type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, + WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3); +type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); +type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); +type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END); + +signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; + +signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0'); +signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0'); +signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0'); +signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + +signal state_init, next_state , next_state_tmp : state_init_type := RESET; +signal count : std_logic_vector (2 downto 0) := "000"; +signal state_write : state_write_type := WR_START; +signal state_interrupt_1 : state_interrupt_1_type := IR1_01; +signal state_interrupt_2 : state_interrupt_2_type := IR2_01; +signal state_read_data : state_read_data_type := RD_1; + +signal interrupt_ignore : std_logic := '1'; +signal int_flag : std_logic := '0'; +signal ram_access : std_logic := '0'; + +signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0'); +signal data_cnt : integer := 0; +signal drs_cnt : integer :=0; +signal channel_cnt : integer range 0 to 9 :=0; +signal socket_cnt : std_logic_vector (2 downto 0) := "000"; +signal roi_max : std_logic_vector (10 downto 0); +signal data_end : integer := 0; + +signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0'); +signal write_length_bytes : std_logic_vector (16 downto 0); + +signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0'); +signal chk_recv_cntr : integer range 0 to 10000 := 0; +signal rx_packets_cnt : std_logic_vector (15 downto 0); +signal next_packet_data : std_logic := '0'; +signal new_config_flag : std_logic := '0'; + +signal trigger_stop : std_logic := '1'; + +signal local_write_length : std_logic_vector (16 DOWNTO 0); +signal local_ram_start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); +signal local_ram_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0); +signal local_socket_nr : std_logic_vector (2 DOWNTO 0); +signal local_write_header_flag, local_write_end_flag : std_logic; +signal local_fifo_channels : std_logic_vector (3 downto 0); + +begin + + --synthesis translate_off + RST_TIME <= X"00120"; + --synthesis translate_on + + w5300_init_proc : process (clk, int) + begin + + if rising_edge (clk) then + + -- Interrupt low + if (int = '0') and (interrupt_ignore = '0') then + case state_interrupt_1 is + when IR1_01 => + int_flag <= '1'; + busy <= '1'; + state_interrupt_1 <= IR1_02; + when IR1_02 => + state_interrupt_1 <= IR1_03; + when IR1_03 => + state_init <= INTERRUPT; + socket_cnt <= "000"; + ram_access <= '0'; + zaehler <= X"00000"; + count <= "000"; + int_flag <= '0'; + interrupt_ignore <= '1'; + state_interrupt_1 <= IR1_04; + when others => + null; + end case; + end if; -- int = '0' + + if int_flag = '0' then + case state_init is + -- Interrupt + when INTERRUPT => + case state_interrupt_2 is + when IR2_01 => + par_addr <= W5300_IR; + state_init <= READ_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_02; + when IR2_02 => + if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt + state_interrupt_2 <= IR2_03; + else + socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then + state_interrupt_2 <= IR2_06; + else + state_interrupt_2 <= IR2_02; + end if; + end if; + when IR2_03 => + par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register + state_init <= READ_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_04; + when IR2_04 => + par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; + par_data <= data_read; -- clear Interrupts + state_init <= WRITE_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_05; + when IR2_05 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0010"; -- CLOSE + state_init <= WRITE_REG; + next_state <= INTERRUPT; + socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then + state_interrupt_2 <= IR2_06; + else + state_interrupt_2 <= IR2_01; + end if; + + when IR2_06 => + state_interrupt_1 <= IR1_01; + state_interrupt_2 <= IR2_01; + socket_cnt <= "000"; + state_init <= RESET; + end case; + + -- reset W5300 + when RESET => + zaehler <= zaehler + 1; + wiz_reset <= '0'; + led <= X"FF"; + if (zaehler >= X"00064") then -- wait 2µs + wiz_reset <= '1'; + end if; + if (zaehler = RST_TIME) then -- wait 10ms + zaehler <= X"00000"; + socket_cnt <= "000"; + count <= "000"; + ram_access <= '0'; + interrupt_ignore <= '0'; + rd <= '1'; + wr <= '1'; + cs <= '1'; + state_write <= WR_START; + state_init <= INIT; + end if; + + -- Init + when INIT => + par_addr <= W5300_MR; + par_data <= X"0000"; + state_init <= WRITE_REG; + next_state <= IM; + + -- Interrupt Mask + when IM => + par_addr <= W5300_IMR; + par_data <= X"00FF"; -- S0-S7 Interrupts + state_init <= WRITE_REG; + next_state <= MT; + + -- Memory Type + when MT => + par_addr <= W5300_MTYPER; + par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer + state_init <= WRITE_REG; + next_state <= STX; + + -- Socket TX Memory Size + when STX => + par_data <= X"0F0F"; -- 15K TX + + par_addr <= W5300_TMS01R; + state_init <=WRITE_REG; + next_state <= STX1; + when STX1 => + par_addr <= W5300_TMS23R; + state_init <=WRITE_REG; + next_state <= STX2; + when STX2 => + par_addr <= W5300_TMS45R; + state_init <=WRITE_REG; + next_state <= STX3; + when STX3 => + par_addr <= W5300_TMS67R; + state_init <=WRITE_REG; + next_state <= SRX; + + -- Socket RX Memory Size + when SRX => + par_data <= X"0101"; -- 1K RX + + par_addr <= W5300_RMS01R; + state_init <=WRITE_REG; + next_state <= SRX1; + when SRX1 => + par_addr <= W5300_RMS23R; + state_init <=WRITE_REG; + next_state <= SRX2; + when SRX2 => + par_addr <= W5300_RMS45R; + state_init <=WRITE_REG; + next_state <= SRX3; + when SRX3 => + par_addr <= W5300_RMS67R; + state_init <=WRITE_REG; + next_state <= MAC; + + -- MAC + when MAC => + par_addr <= W5300_SHAR; + par_data <= MAC_ADDRESS (0); + state_init <= WRITE_REG; + next_state <= MAC1; + when MAC1 => + par_addr <= W5300_SHAR + 2; + par_data <= MAC_ADDRESS (1); + state_init <= WRITE_REG; + next_state <= MAC2; + when MAC2 => + par_addr <= W5300_SHAR + 4; + par_data <= MAC_ADDRESS (2); + state_init <= WRITE_REG; + next_state <= GW; + + -- Gateway + when GW => + par_addr <= W5300_GAR; + par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8); + par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8); + state_init <= WRITE_REG; + next_state <= GW1; + when GW1 => + par_addr <= W5300_GAR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8); + par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8); + state_init <= WRITE_REG; + next_state <= SNM; + + -- Subnet Mask + when SNM => + par_addr <= W5300_SUBR; + par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8); + par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8); + state_init <= WRITE_REG; + next_state <= SNM1; + when SNM1 => + par_addr <= W5300_SUBR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8); + par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8); + state_init <= WRITE_REG; + next_state <= IP; + -- Own IP-Address + when IP => + par_addr <= W5300_SIPR; + par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8); + par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8); + state_init <= WRITE_REG; + next_state <= IP1; + when IP1 => + par_addr <= W5300_SIPR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8); + par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8); + state_init <= WRITE_REG; + next_state <= TIMEOUT; + when TIMEOUT => + par_addr <= W5300_RTR; + par_data <= X"07D0"; -- 0x07D0 = 200ms + state_init <= WRITE_REG; + next_state <= RETRY; + when RETRY => + par_addr <= W5300_RCR; + par_data <= X"0008"; + state_init <= WRITE_REG; + next_state <= SI; + + -- Socket Init + when SI => + par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC; + par_data <= X"0101"; -- ALIGN, TCP + state_init <= WRITE_REG; + next_state <= SI1; + -- Sx Interrupt Mask + when SI1 => + par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC; + par_data <= X"000A"; -- TIMEOUT, DISCON + state_init <= WRITE_REG; + next_state <= SI2; + when SI2 => + par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC; + par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16); + state_init <= WRITE_REG; + next_state <= SI3; + when SI3 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0001"; -- OPEN + state_init <= WRITE_REG; + next_state <= SI4; + when SI4 => + par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; + state_init <= READ_REG; + next_state <= SI5; + when SI5 => + if (data_read (7 downto 0) = X"13") then -- is open? + state_init <= SI6; + else + state_init <= SI4; + end if; + when SI6 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0002"; -- LISTEN + state_init <= WRITE_REG; + socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then + socket_cnt <= "000"; + next_state <= ESTABLISH; -- All Sockets open + else + next_state <= SI; -- Next Socket + end if; + -- End Socket Init + + when ESTABLISH => + par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; + state_init <= READ_REG; + next_state <= EST1; + when EST1 => + led <= data_read (7 downto 0); + case data_read (7 downto 0) is + when X"17" => -- established + if (socket_cnt = 7) then + socket_cnt <= "000"; + busy <= '0'; + state_init <= MAIN; + else + socket_cnt <= socket_cnt + 1; + state_init <= ESTABLISH; + end if; + when others => + state_init <= ESTABLISH; + end case; + + when CONFIG => + led <= X"F0"; + new_config <= '1'; + if (config_started = '1') then + led <= X"0F"; + new_config <= '0'; + busy <= '0'; + state_init <= MAIN; + end if; + + -- main "loop" + when MAIN => + if (trigger_stop = '1') then + s_trigger <= '0'; + end if; + if (chk_recv_cntr = 1000) then + chk_recv_cntr <= 0; + state_read_data <= RD_1; + state_init <= READ_DATA; + busy <= '1'; + else + busy <= '0'; + data_valid_ack <= '0'; + chk_recv_cntr <= chk_recv_cntr + 1; + if (data_valid = '1') then + data_valid_ack <= '1'; + local_write_length <= write_length; + local_ram_start_addr <= ram_start_addr; + local_ram_addr <= (others => '0'); + local_write_header_flag <= write_header_flag; + local_write_end_flag <= write_end_flag; + local_fifo_channels <= fifo_channels; + next_state <= MAIN; + state_init <= WRITE_DATA; + busy <= '1'; + end if; + end if; + + -- read data from socket 0 + when READ_DATA => + case state_read_data is + when RD_1 => + par_addr <= W5300_S0_RX_RSR; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_2; + when RD_2 => + socket_rx_received (31 downto 16) <= data_read; + par_addr <= W5300_S0_RX_RSR + X"2"; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_3; + when RD_3 => + socket_rx_received (15 downto 0) <= data_read; + state_read_data <= RD_4; + when RD_4 => + if (socket_rx_received (16 downto 0) > ('0' & X"000")) then + rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2 + state_read_data <= RD_5; + else + busy <= '0'; + state_init <= MAIN; + end if; + when RD_5 => + if (rx_packets_cnt > 0) then + rx_packets_cnt <= rx_packets_cnt - '1'; + par_addr <= W5300_S0_RX_FIFOR; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_6; + else + state_read_data <= RD_END; +-- if (new_config_flag = '1') then +-- new_config_flag <= '0'; +-- state_init <= CONFIG; +-- else +-- busy <= '0'; +-- state_init <= MAIN; +-- end if; + end if; + when RD_6 => + led <= data_read (15 downto 8); + -- read command + if (next_packet_data = '0') then + case data_read (15 downto 8) is + when CMD_TRIGGER => + trigger_stop <= '1'; + s_trigger <= '1'; + state_read_data <= RD_WAIT; + when CMD_DWRITE_RUN => + dwrite_enable <= '1'; + state_read_data <= RD_WAIT; + when CMD_DWRITE_STOP => + dwrite_enable <= '0'; + state_read_data <= RD_WAIT; + when CMD_DENABLE => + denable <= '1'; + state_read_data <= RD_WAIT; + when CMD_DDISABLE => + denable <= '0'; + state_read_data <= RD_WAIT; + when CMD_TRIGGER_C => + trigger_stop <= '0'; + s_trigger <= '1'; + state_read_data <= RD_WAIT; + when CMD_TRIGGER_S => + trigger_stop <= '1'; + state_read_data <= RD_WAIT; + when CMD_WRITE => + next_packet_data <= '1'; + config_addr <= data_read (7 downto 0); + state_read_data <= RD_5; + when others => + state_read_data <= RD_5; + end case; + -- read data + else + if (config_busy = '0') then + config_data <= data_read; + config_wr_en <= '1'; + new_config_flag <= '1'; + next_packet_data <= '0'; + state_read_data <= RD_WAIT; + end if; + end if; + when RD_WAIT => + state_read_data <= RD_WAIT1; + when RD_WAIT1 => + config_data <= (others => 'Z'); + config_wr_en <= '0'; + state_read_data <= RD_5; + when RD_END => + par_addr <= W5300_S0_CR; + par_data <= X"0040"; -- RECV + state_init <= WRITE_REG; + if (new_config_flag = '1') then + new_config_flag <= '0'; + next_state <= CONFIG; + else +-- busy <= '0'; + next_state <= MAIN; + end if; + + end case; -- state_data_read + + + + when WRITE_DATA => + case state_write is + when WR_START => + if (local_write_header_flag = '1') then + ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ???? + end if; + state_write <= WR_WAIT1; + when WR_WAIT1 => + state_write <= WR_LENGTH; + when WR_LENGTH => + if (local_write_header_flag = '1') then + local_socket_nr <= ram_data (2 downto 0); + end if; + next_state_tmp <= next_state; + write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2) + data_cnt <= 0; + state_write <= WR_01; + -- Check FIFO Size + when WR_01 => + par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC; + state_init <= READ_REG; + next_state <= WRITE_DATA; + state_write <= WR_02; + when WR_02 => + socket_tx_free (31 downto 16) <= data_read; + par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2"; + state_init <= READ_REG; + next_state <= WRITE_DATA; + state_write <= WR_03; + when WR_03 => + socket_tx_free (15 downto 0) <= data_read; + state_write <= WR_04; + when WR_04 => + if (socket_tx_free (16 downto 0) < write_length_bytes) then + state_write <= WR_01; + else + if (local_write_header_flag = '1') then + state_write <= WR_FIFO; + else + state_write <= WR_ADC; + end if; + end if; + + -- Fill FIFO + + -- Write Header + when WR_FIFO => + ram_addr <= local_ram_start_addr + local_ram_addr; + state_write <= WR_FIFO1; + when WR_FIFO1 => + data_cnt <= data_cnt + 1; + if (data_cnt < PACKAGE_HEADER_LENGTH) then --??? + local_ram_addr <= local_ram_addr + 1; + if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words + local_ram_addr <= local_ram_addr + 2; + end if; + if (data_cnt = 9) then -- skip empty words + local_ram_addr <= local_ram_addr + 4; + end if; + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + ram_access <= '1'; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_FIFO; + else + state_write <= WR_ADC; + end if; + -- End Write Header + + -- Write ADC-Data + ---- Start... + when WR_ADC => + adc_data_addr <= local_ram_start_addr + local_ram_addr; + drs_cnt <= 0; + channel_cnt <= 1; + data_cnt <= 0; + roi_max <= (others => '0'); + data_end <= 3; + state_write <= WR_ADC1; + + ---- Write Channel + when WR_ADC1 => + -- read ROI and set end of Channel-Data + if (data_cnt = 3) then + data_end <= conv_integer (ram_data) + 3; + if (ram_data > roi_max) then + roi_max <= ram_data (10 downto 0); + end if; + end if; + ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4); + state_write <= WR_ADC2; + when WR_ADC2 => + if (data_cnt < data_end) then + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + ram_access <= '1'; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + data_cnt <= data_cnt + 1; + state_write <= WR_ADC1; + else + -- Next DRS + if (drs_cnt < 3) then + drs_cnt <= drs_cnt + 1; + data_cnt <= 0; + data_end <= 3; + state_write <= WR_ADC1; + else + -- Next Channel + if (channel_cnt < local_fifo_channels) then + channel_cnt <= channel_cnt + 1; + roi_max <= (others => '0'); + drs_cnt <= 0; + data_cnt <= 0; + data_end <= 3; + adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4); + state_write <= WR_ADC1; + else + -- Ready + if (local_write_end_flag = '1') then + state_write <= WR_ENDFLAG; + else + state_write <= WR_05; + end if; + end if; + end if; + end if; + -- End Write ADC-Data + + -- Write End Package Flag + when WR_ENDFLAG => + ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4); + state_write <= WR_ENDFLAG1; + when WR_ENDFLAG1 => + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + ram_access <= '1'; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_ENDFLAG2; + when WR_ENDFLAG2 => + ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1; + state_write <= WR_ENDFLAG3; + when WR_ENDFLAG3 => + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_05; + + -- End Write End Package Flag + + --Send FIFO + when WR_05 => + ram_access <= '0'; + par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC; + par_data <= (0 => write_length_bytes (16), others => '0'); + state_init <= WRITE_REG; + state_write <= WR_06; + when WR_06 => + par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2"; + par_data <= write_length_bytes (15 downto 0); + state_init <= WRITE_REG; + state_write <= WR_07; + when WR_07 => + par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC; + par_data <= X"0020"; -- Send + state_init <= WRITE_REG; + state_write <= WR_08; + when others => +-- busy <= '0'; + state_init <= next_state_tmp; + state_write <= WR_START; + end case; + -- End WRITE_DATA + + when READ_REG => + case count is + when "000" => + cs <= '0'; + rd <= '0'; + wr <= '1'; + data <= (others => 'Z'); -- !!!!!!!!!! + count <= "001"; + addr <= par_addr; + when "001" => + count <= "010"; + when "010" => + count <= "100"; + when "100" => + data_read <= data; + count <= "110"; + when "110" => + count <= "111"; + when "111" => + cs <= '1'; + rd <= '1'; + count <= "000"; + state_init <= next_state; + when others => + null; + end case; + + when WRITE_REG => + case count is + when "000" => + cs <= '0'; + wr <= '0'; + rd <= '1'; + addr <= par_addr; + if (ram_access = '1') then + data <= ram_data; + else + data <= par_data; + end if; + count <= "100"; + when "100" => + count <= "101"; + when "101" => + count <= "110"; + when "110" => + cs <= '1'; + wr <= '1'; + state_init <= next_state; + count <= "000"; + when others => + null; + end case; + + when others => + null; + end case; + end if; -- int_flag = '0' + + end if; -- rising_edge (clk) + + end process w5300_init_proc; + +end Behavioral; + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Coregen/DCM_25MHz_38nsPS.xaw =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Coregen/DCM_25MHz_38nsPS.xaw (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Coregen/DCM_25MHz_38nsPS.xaw (revision 9841) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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/firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Synthesis/Constraints/DCM_25MHz_38nsPS_arwz.ucf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Synthesis/Constraints/DCM_25MHz_38nsPS_arwz.ucf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Synthesis/Constraints/DCM_25MHz_38nsPS_arwz.ucf (revision 9841) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = 1X; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 1; +INST DCM_SP_INST CLKFX_MULTIPLY = 4; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 40.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = FIXED; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 243; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Synthesis/Constraints/DCM_25MHz_noPS_arwz.ucf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Synthesis/Constraints/DCM_25MHz_noPS_arwz.ucf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Synthesis/Constraints/DCM_25MHz_noPS_arwz.ucf (revision 9841) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = 1X; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 1; +INST DCM_SP_INST CLKFX_MULTIPLY = 4; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 20.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_noPS_BEHAVIORAL.vhd.info/Coregen/DCM_25MHz_noPS.xaw =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_noPS_BEHAVIORAL.vhd.info/Coregen/DCM_25MHz_noPS.xaw (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_noPS_BEHAVIORAL.vhd.info/Coregen/DCM_25MHz_noPS.xaw (revision 9841) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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~j02603:1=vF88e9~j02613:1=vF88e9~j026i3:1=vF88e9~j026j3:1=vF88e9~yx{GHJq>5auIJIw=sO@Qy~DE Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Coregen/dataRAM_64b_16b_width15.xco =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Coregen/dataRAM_64b_16b_width15.xco (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Coregen/dataRAM_64b_16b_width15.xco (revision 9841) @@ -0,0 +1,78 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Mon Jun 21 14:26:28 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatParenNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3sd3400a +SET devicefamily = spartan3adsp +SET flowvendor = MentorHDL +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg676 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator family Xilinx,_Inc. 2.8 +# END Select +# BEGIN Parameters +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=dataRAM_64b_16b_width15 +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET fill_remaining_memory_locations=false +CSET load_init_file=false +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=READ_FIRST +CSET operating_mode_b=READ_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET primitive=8kx2 +CSET read_width_a=64 +CSET read_width_b=16 +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET remaining_memory_locations=0 +CSET single_bit_ecc=false +CSET use_byte_write_enable=false +CSET use_ramb16bwer_reset_behavior=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_ssra_pin=false +CSET use_ssrb_pin=false +CSET write_depth_a=32768 +CSET write_width_a=64 +CSET write_width_b=16 +# END Parameters +GENERATE +# CRC: 66fba8fa + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/Constraints/dataRAM_64b_16b_width15.ctr =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/Constraints/dataRAM_64b_16b_width15.ctr (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/Constraints/dataRAM_64b_16b_width15.ctr (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3adsp +# set_device 3sd3400a +# set_package fg676 +# set_speed -4 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/Constraints/dataRAM_64b_16b_width15.sdc =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/Constraints/dataRAM_64b_16b_width15.sdc (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/Constraints/dataRAM_64b_16b_width15.sdc (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3adsp +# set_device 3sd3400a +# set_package fg676 +# set_speed -4 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/dataRAM_64b_16b_width15.ngc =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/dataRAM_64b_16b_width15.ngc (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/dataRAM_64b_16b_width15.ngc (revision 9841) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$`764g<,[o}e~g`n;"2*413&;$>"9 > %384<=789:;<=>?4193456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0127?567<=1;<=6=;130?4(7:2;;=95>4;KMTPR=IMNYM%?<:1+20>732@D[YY4NDEPA,45=8 ;?7<;5IORVP?gcl{k#=94?)018535/6=2;=6B[[PTV9`jssj!;>6='>4:34>LHW]]0jhi|m(0494,77380BB][[:vgb,5<7!8:0=7GAPTV9s`d/83:">6<5OTVSQQ&12906?IR\Y__6IAM(2394,`<;zn88=>nff442(233=:;<4?)0380?OIX\^1HD^M(283-46<<3CE\XZ5WDC+7?6.991?6D@_UU8TAG.429#:>6:5OTVSQQ&1397>JSSX\^1HB^M(283-45<>=0BB][[:ekme-0429#:968;:NWWTPR=lfm%8<:1+1?=6331:;<55NDEPB,5/?3HNO^L&>)89B@ATF 8:"56OKDSC+54/>3HNO^L&>2(;8EABUI!;8%o5NDEPB,45=8 20MIJ]A)0*<>GCL[K#?$64AEFQE-2.02KOH_O'5(:8EABUI!<"46OKDSC+3,>GCL[H#=$74AEFQF-77!01JHI\M(03*=>GCL[H#=?'6;@FGVG.6; h0MIJ]B)30>5/?3HNO^O&=)99B@ATE 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3?=?110e;j50;&5e?>63-<26:64;h6`>5<#>h03=6*99;5;?>i5>3:1(;o5809'2f<002.:h7<;;%3f>05<3f8n6=4+6`8;5>=h:h0;6)8n:938?j4e290/:l471:9l6c<72-i5l3:1(;o58098k65=83.=m76>;%4`>2><,8i1>954o2694?"1i32:76a85;29 3g=0;1/:5488:9l1c<72-5<#>h03=65rb2f94?4=83:p(;l5589j1=<72-207pl=8;296?6=8r.=n7<;;h7;>5<#>h03=6*9c;5;?>i1=3:1(;o5809'2f<0021vn>850;094?6|,?h1>95f5983>!0f21;0(;m57998k33=83.=m76>;%4`>2><3ty8o7>52z?73?5f349o6;;4$0`97`=z{:81<7b;0:?xu5?3:1>v3;7;05?84?2<20q~=::1818202:901>85599~w6`=83;p1>j5599'37<202wx?44?:0y>73<1=2.<>78:;|q0a?6=8r.<>78:;|q1=?6=8r.<>78:;|m6<<728qvb?o50;3xyk4e290:wp`=c;295~{i:m0;6{|l04?6=9rwvqpNOCz1:>d15:oknqMNM{1CDU}zHI Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25.ctr =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25.ctr (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25.ctr (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700a +# set_package fg484 +# set_speed -4 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25.sdc =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25.sdc (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25.sdc (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700a +# set_package fg484 +# set_speed -4 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25_arwz.ucf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25_arwz.ucf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25_arwz.ucf (revision 9841) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = 1X; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 5; +INST DCM_SP_INST CLKFX_MULTIPLY = 2; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 20.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_ps_38ns_BEHAVIORAL.vhd.info/Coregen/dcm_ps_38ns.xaw =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_ps_38ns_BEHAVIORAL.vhd.info/Coregen/dcm_ps_38ns.xaw (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_ps_38ns_BEHAVIORAL.vhd.info/Coregen/dcm_ps_38ns.xaw (revision 9841) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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"library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "07" +) +(vvPair +variable "module_name" +value "FAD_Board" +) +(vvPair +variable "month" +value "Jul" +) +(vvPair +variable "month_long" +value "Juli" +) +(vvPair +variable "p" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "15:25:08" +) +(vvPair +variable "unit" +value "FAD_Board" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 52,0 +optionalChildren [ +*1 (Grouping +uid 9,0 +optionalChildren [ +*2 (CommentText +uid 11,0 +shape (Rectangle +uid 12,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "99000,4000,116000,5000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 13,0 +va (VaSet +fg "0,0,32768" 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65,0 +) +) +) +*41 (CptPort +uid 2981,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 2982,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "80000,98625,80750,99375" +) +tg (CPTG +uid 2983,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2984,0 +va (VaSet +) +xt "77600,98500,79000,99500" +st "sio" +ju 2 +blo "79000,99300" +) +) +thePort (LogicalPort +m 2 +decl (Decl +n "sio" +t "std_logic" +preAdd 0 +posAdd 0 +o 30 +suid 63,0 +) +) +) +*42 (CptPort +uid 3670,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3671,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "80000,99625,80750,100375" +) +tg (CPTG +uid 3672,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3673,0 +va (VaSet +) +xt "77000,99500,79000,100500" +st "mosi" +ju 2 +blo "79000,100300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "mosi" +t "std_logic" +o 22 +suid 66,0 +i "'0'" +) +) +) +*43 (CptPort +uid 6427,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6428,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "80000,120625,80750,121375" +) +tg (CPTG +uid 6429,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6430,0 +va (VaSet +) +xt "76000,120500,79000,121500" +st "denable" +ju 2 +blo "79000,121300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "denable" +t "std_logic" +eolc "-- default domino wave off" +posAdd 0 +o 18 +suid 67,0 +i "'0'" +) +) +) +] +shape (Rectangle +uid 170,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "52000,66000,80000,123000" +) +oxt "15000,-1000,43000,27000" +ttg (MlTextGroup +uid 171,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*44 (Text +uid 172,0 +va (VaSet +font "Arial,8,1" +) +xt "52200,123000,58400,124000" +st "FACT_FAD_lib" +blo "52200,123800" +tm "BdLibraryNameMgr" +) +*45 (Text +uid 173,0 +va (VaSet +font "Arial,8,1" +) +xt "52200,124000,56400,125000" +st "FAD_main" +blo "52200,124800" +tm "CptNameMgr" +) +*46 (Text +uid 174,0 +va (VaSet +font "Arial,8,1" +) +xt "52200,125000,58000,126000" +st "I_board_main" +blo "52200,125800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 175,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 176,0 +text (MLText +uid 177,0 +va (VaSet +font "Courier New,8,0" +) +xt "52000,65200,81500,66000" +st "RAMADDRWIDTH64b = LOG2_OF_RAM_SIZE_64B ( integer ) " +) +header "" +) +elements [ +(GiElement +name "RAMADDRWIDTH64b" +type "integer" +value "LOG2_OF_RAM_SIZE_64B" +) +] +) +viewicon (ZoomableIcon +uid 178,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "52250,121250,53750,122750" +iconName "BlockDiagram.png" +iconMaskName "BlockDiagram.msk" +ftype 1 +) +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*47 (PortIoIn +uid 231,0 +shape (CompositeShape +uid 232,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 233,0 +sl 0 +ro 270 +xt "9000,76625,10500,77375" +) +(Line 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"111500,73625,113000,74375" +) +(Line +uid 499,0 +sl 0 +ro 90 +xt "111000,74000,111500,74000" +pts [ +"111500,74000" +"111000,74000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 500,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 501,0 +va (VaSet +) +xt "114000,73500,116800,74500" +st "W_INT" +blo "114000,74300" +tm "WireNameMgr" +) +) +) +*60 (PortIoOut +uid 502,0 +shape (CompositeShape +uid 503,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 504,0 +sl 0 +ro 270 +xt "111500,71625,113000,72375" +) +(Line +uid 505,0 +sl 0 +ro 270 +xt "111000,72000,111500,72000" +pts [ +"111000,72000" +"111500,72000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 506,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 507,0 +va (VaSet +) +xt "114000,71500,116700,72500" +st "W_RD" +blo "114000,72300" +tm "WireNameMgr" +) +) +) +*61 (PortIoOut +uid 508,0 +shape (CompositeShape +uid 509,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 510,0 +sl 0 +ro 270 +xt "111500,72625,113000,73375" +) +(Line +uid 511,0 +sl 0 +ro 270 +xt "111000,73000,111500,73000" +pts [ +"111000,73000" +"111500,73000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 512,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 513,0 +va (VaSet +) +xt "114000,72500,116800,73500" +st "W_WR" +blo "114000,73300" +tm "WireNameMgr" +) +) +) +*62 (Net +uid 1465,0 +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 54 +suid 29,0 +) +declText (MLText +uid 1466,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,47200,62500,48000" +st "SIGNAL adc_data_array : adc_data_array_type +" +) +) +*63 (Net +uid 2407,0 +decl (Decl +n "RSRLOAD" +t "std_logic" +o 35 +suid 57,0 +i "'0'" +) +declText (MLText +uid 2408,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,31000,68000,31800" +st "RSRLOAD : std_logic := '0' +" +) +) +*64 (PortIoOut +uid 2415,0 +shape (CompositeShape +uid 2416,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2417,0 +sl 0 +ro 90 +xt "19000,110625,20500,111375" +) +(Line +uid 2418,0 +sl 0 +ro 90 +xt "20500,111000,21000,111000" +pts [ +"21000,111000" +"20500,111000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2419,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2420,0 +va (VaSet +) +xt "13800,110500,18000,111500" +st "RSRLOAD" +ju 2 +blo "18000,111300" +tm "WireNameMgr" +) +) +) +*65 (Net +uid 2421,0 +decl (Decl +n "SRCLK" +t "std_logic" +o 52 +suid 58,0 +i "'0'" +) +declText (MLText +uid 2422,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,45600,71500,46400" +st "SIGNAL SRCLK : std_logic := '0' +" +) +) +*66 (Net +uid 3019,0 +decl (Decl +n "sensor_cs" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 59 +suid 65,0 +) +declText (MLText +uid 3020,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,51200,67000,52000" +st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0) +" +) +) +*67 (Net +uid 3025,0 +decl (Decl +n "DAC_CS" +t "std_logic" +o 21 +suid 66,0 +) +declText (MLText +uid 3026,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,19800,53500,20600" +st "DAC_CS : std_logic +" +) +) +*68 (PortIoOut +uid 3153,0 +shape (CompositeShape +uid 3154,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3155,0 +sl 0 +ro 90 +xt "19000,69625,20500,70375" +) +(Line +uid 3156,0 +sl 0 +ro 90 +xt "20500,70000,21000,70000" +pts [ +"21000,70000" +"20500,70000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3157,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3158,0 +va (VaSet +) +xt "15200,69500,18000,70500" +st "A_CLK" +ju 2 +blo "18000,70300" +tm "WireNameMgr" +) +) +) +*69 (Net +uid 3216,0 +decl (Decl +n "X_50M" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 14 +suid 67,0 +) +declText (MLText +uid 3217,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,14200,53500,15000" +st "X_50M : STD_LOGIC +" +) +) +*70 (Net +uid 3226,0 +decl (Decl +n "TRG" +t "STD_LOGIC" +o 12 +suid 68,0 +) +declText (MLText +uid 3227,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,12600,53500,13400" +st "TRG : STD_LOGIC +" +) +) +*71 (HdlText +uid 3248,0 +optionalChildren [ +*72 (EmbeddedText +uid 3254,0 +commentText (CommentText +uid 3255,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3256,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "32000,71000,44000,77000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3257,0 +va (VaSet +) +xt "32200,71200,44100,77200" +st " +-- ADC_CLK 2 +A_CLK (0) <= CLK_25_PS; +A_CLK (1) <= CLK_25_PS; +A_CLK (2) <= CLK_25_PS; +A_CLK (3) <= CLK_25_PS; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 3249,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "24000,69000,32000,77000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3250,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*73 (Text +uid 3251,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,70000,31350,71000" +st "ADC_CLK" +blo "27150,70800" +tm "HdlTextNameMgr" +) +*74 (Text +uid 3252,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,71000,27950,72000" +st "2" +blo "27150,71800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3253,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "24250,75250,25750,76750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*75 (Net +uid 3266,0 +decl (Decl +n "A_CLK" +t "std_logic_vector" +b "(3 downto 0)" +o 16 +suid 71,0 +) +declText (MLText +uid 3267,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,15800,63500,16600" +st "A_CLK : std_logic_vector(3 downto 0) +" +) +) +*76 (Net +uid 3268,0 +decl (Decl +n "CLK_25_PS" +t "std_logic" +o 50 +suid 72,0 +) +declText (MLText +uid 3269,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,44000,57000,44800" +st "SIGNAL CLK_25_PS : std_logic +" +) +) +*77 (PortIoOut +uid 3284,0 +shape (CompositeShape +uid 3285,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3286,0 +sl 0 +ro 90 +xt "19000,89625,20500,90375" +) +(Line +uid 3287,0 +sl 0 +ro 90 +xt "20500,90000,21000,90000" +pts [ +"21000,90000" +"20500,90000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3288,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3289,0 +va (VaSet +) +xt "14400,89500,18000,90500" +st "OE_ADC" +ju 2 +blo "18000,90300" +tm "WireNameMgr" +) +) +) +*78 (Net +uid 3290,0 +decl (Decl +n "OE_ADC" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 30 +suid 73,0 +) +declText (MLText +uid 3291,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,27000,53500,27800" +st "OE_ADC : STD_LOGIC +" +) +) +*79 (PortIoIn +uid 3292,0 +shape (CompositeShape +uid 3293,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3294,0 +sl 0 +ro 270 +xt "19000,88625,20500,89375" +) +(Line +uid 3295,0 +sl 0 +ro 270 +xt "20500,89000,21000,89000" +pts [ +"20500,89000" +"21000,89000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3296,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3297,0 +va (VaSet +) +xt "15000,88500,18000,89500" +st "A_OTR" +ju 2 +blo "18000,89300" +tm "WireNameMgr" +) +) +) +*80 (Net +uid 3298,0 +decl (Decl +n "A_OTR" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 5 +suid 74,0 +) +declText (MLText +uid 3299,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,7000,63500,7800" +st "A_OTR : std_logic_vector(3 DOWNTO 0) +" +) +) +*81 (HdlText +uid 3300,0 +optionalChildren [ +*82 (EmbeddedText +uid 3306,0 +commentText (CommentText +uid 3307,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3308,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "32000,96000,44000,102000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3309,0 +va (VaSet +) +xt "32200,96200,44200,102200" +st " +-- ADC_DATA 3 +adc_data_array (0) <= A0_D; +adc_data_array (1) <= A1_D; +adc_data_array (2) <= A2_D; +adc_data_array (3) <= A3_D; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 3301,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "24000,94000,32000,102000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3302,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*83 (Text +uid 3303,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,95000,31750,96000" +st "ADC_DATA" +blo "27150,95800" +tm "HdlTextNameMgr" +) +*84 (Text +uid 3304,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,96000,27950,97000" +st "3" +blo "27150,96800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3305,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "24250,100250,25750,101750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*85 (PortIoIn +uid 3310,0 +shape (CompositeShape +uid 3311,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3312,0 +sl 0 +ro 270 +xt "19000,94625,20500,95375" +) +(Line +uid 3313,0 +sl 0 +ro 270 +xt "20500,95000,21000,95000" +pts [ +"20500,95000" +"21000,95000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3314,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3315,0 +va (VaSet +) +xt "15700,94500,18000,95500" +st "A0_D" +ju 2 +blo "18000,95300" +tm "WireNameMgr" +) +) +) +*86 (PortIoIn +uid 3332,0 +shape (CompositeShape +uid 3333,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3334,0 +sl 0 +ro 270 +xt "19000,95625,20500,96375" +) +(Line +uid 3335,0 +sl 0 +ro 270 +xt "20500,96000,21000,96000" +pts [ +"20500,96000" +"21000,96000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3336,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3337,0 +va (VaSet +) +xt "15700,95500,18000,96500" +st "A1_D" +ju 2 +blo "18000,96300" +tm "WireNameMgr" +) +) +) +*87 (PortIoIn +uid 3338,0 +shape (CompositeShape +uid 3339,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3340,0 +sl 0 +ro 270 +xt "19000,96625,20500,97375" +) +(Line +uid 3341,0 +sl 0 +ro 270 +xt "20500,97000,21000,97000" +pts [ +"20500,97000" +"21000,97000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3342,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3343,0 +va (VaSet +) +xt "15700,96500,18000,97500" +st "A2_D" +ju 2 +blo "18000,97300" +tm "WireNameMgr" +) +) +) +*88 (PortIoIn +uid 3344,0 +shape (CompositeShape +uid 3345,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3346,0 +sl 0 +ro 270 +xt "19000,97625,20500,98375" +) +(Line +uid 3347,0 +sl 0 +ro 270 +xt "20500,98000,21000,98000" +pts [ +"20500,98000" +"21000,98000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3348,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3349,0 +va (VaSet +) +xt "15700,97500,18000,98500" +st "A3_D" +ju 2 +blo "18000,98300" +tm "WireNameMgr" +) +) +) +*89 (Net +uid 3374,0 +decl (Decl +n "A0_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 1 +suid 79,0 +) +declText (MLText +uid 3375,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,3800,64000,4600" +st "A0_D : std_logic_vector(11 DOWNTO 0) +" +) +) +*90 (Net +uid 3376,0 +decl (Decl +n "A1_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 2 +suid 80,0 +) +declText (MLText +uid 3377,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,4600,64000,5400" +st "A1_D : std_logic_vector(11 DOWNTO 0) +" +) +) +*91 (Net +uid 3378,0 +decl (Decl +n "A2_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 3 +suid 81,0 +) +declText (MLText +uid 3379,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,5400,64000,6200" +st "A2_D : std_logic_vector(11 DOWNTO 0) +" +) +) +*92 (Net +uid 3380,0 +decl (Decl +n "A3_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 4 +suid 82,0 +) +declText (MLText +uid 3381,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,6200,64000,7000" +st "A3_D : std_logic_vector(11 DOWNTO 0) +" +) +) +*93 (HdlText +uid 3394,0 +optionalChildren [ +*94 (EmbeddedText +uid 3400,0 +commentText (CommentText +uid 3401,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3402,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "32000,114000,44000,120000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3403,0 +va (VaSet +) +xt "32200,114200,44200,120200" +st " +-- SRCLK 4 +D0_SRCLK <= SRCLK; +D1_SRCLK <= SRCLK; +D2_SRCLK <= SRCLK; +D3_SRCLK <= SRCLK; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 3395,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "24000,112000,32000,120000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3396,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*95 (Text +uid 3397,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,113000,30350,114000" +st "SRCLK" +blo "27150,113800" +tm "HdlTextNameMgr" +) +*96 (Text +uid 3398,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,114000,27950,115000" +st "4" +blo "27150,114800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3399,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "24250,118250,25750,119750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*97 (Net +uid 3460,0 +decl (Decl +n "D0_SRCLK" +t "STD_LOGIC" +o 17 +suid 87,0 +) +declText (MLText +uid 3461,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,16600,53500,17400" +st "D0_SRCLK : STD_LOGIC +" +) +) +*98 (Net +uid 3462,0 +decl (Decl +n "D1_SRCLK" +t "STD_LOGIC" +o 18 +suid 88,0 +) +declText (MLText +uid 3463,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,17400,53500,18200" +st "D1_SRCLK : STD_LOGIC +" +) +) +*99 (Net +uid 3464,0 +decl (Decl +n "D2_SRCLK" +t "STD_LOGIC" +o 19 +suid 89,0 +) +declText (MLText +uid 3465,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,18200,53500,19000" +st "D2_SRCLK : STD_LOGIC +" +) +) +*100 (Net +uid 3466,0 +decl (Decl +n "D3_SRCLK" +t "STD_LOGIC" +o 20 +suid 90,0 +) +declText (MLText +uid 3467,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,19000,53500,19800" +st "D3_SRCLK : STD_LOGIC +" +) +) +*101 (PortIoIn +uid 3476,0 +shape (CompositeShape +uid 3477,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3478,0 +sl 0 +ro 270 +xt "19000,104625,20500,105375" +) +(Line +uid 3479,0 +sl 0 +ro 270 +xt "20500,105000,21000,105000" +pts [ +"20500,105000" +"21000,105000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3480,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3481,0 +va (VaSet +) +xt "13400,104500,18000,105500" +st "D0_SROUT" +ju 2 +blo "18000,105300" +tm "WireNameMgr" +) +) +) +*102 (PortIoIn +uid 3482,0 +shape (CompositeShape +uid 3483,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3484,0 +sl 0 +ro 270 +xt "19000,105625,20500,106375" +) +(Line +uid 3485,0 +sl 0 +ro 270 +xt "20500,106000,21000,106000" +pts [ +"20500,106000" +"21000,106000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3486,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3487,0 +va (VaSet +) +xt "13400,105500,18000,106500" +st "D1_SROUT" +ju 2 +blo "18000,106300" +tm "WireNameMgr" +) +) +) +*103 (PortIoIn +uid 3488,0 +shape (CompositeShape +uid 3489,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3490,0 +sl 0 +ro 270 +xt "19000,106625,20500,107375" +) +(Line +uid 3491,0 +sl 0 +ro 270 +xt "20500,107000,21000,107000" +pts [ +"20500,107000" +"21000,107000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3492,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3493,0 +va (VaSet +) +xt "13400,106500,18000,107500" +st "D2_SROUT" +ju 2 +blo "18000,107300" +tm "WireNameMgr" +) +) +) +*104 (PortIoIn +uid 3494,0 +shape (CompositeShape +uid 3495,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3496,0 +sl 0 +ro 270 +xt "19000,107625,20500,108375" +) +(Line +uid 3497,0 +sl 0 +ro 270 +xt "20500,108000,21000,108000" +pts [ +"20500,108000" +"21000,108000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3498,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3499,0 +va (VaSet +) +xt "13400,107500,18000,108500" +st "D3_SROUT" +ju 2 +blo "18000,108300" +tm "WireNameMgr" +) +) +) +*105 (Net +uid 3500,0 +decl (Decl +n "D0_SROUT" +t "std_logic" +o 6 +suid 91,0 +) +declText (MLText +uid 3501,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,7800,53500,8600" +st "D0_SROUT : std_logic +" +) +) +*106 (Net +uid 3502,0 +decl (Decl +n "D1_SROUT" +t "std_logic" +o 7 +suid 92,0 +) +declText (MLText +uid 3503,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,8600,53500,9400" +st "D1_SROUT : std_logic +" +) +) +*107 (Net +uid 3504,0 +decl (Decl +n "D2_SROUT" +t "std_logic" +o 8 +suid 93,0 +) +declText (MLText +uid 3505,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,9400,53500,10200" +st "D2_SROUT : std_logic +" +) +) +*108 (Net +uid 3506,0 +decl (Decl +n "D3_SROUT" +t "std_logic" +o 9 +suid 94,0 +) +declText (MLText +uid 3507,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,10200,53500,11000" +st "D3_SROUT : std_logic +" +) +) +*109 (PortIoOut +uid 3508,0 +shape (CompositeShape +uid 3509,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3510,0 +sl 0 +ro 90 +xt "4000,133625,5500,134375" +) +(Line +uid 3511,0 +sl 0 +ro 90 +xt "5500,134000,6000,134000" +pts [ +"6000,134000" +"5500,134000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3512,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3513,0 +va (VaSet +) +xt "1100,133500,3000,134500" +st "D_A" +ju 2 +blo "3000,134300" +tm "WireNameMgr" +) +) +) +*110 (Net +uid 3514,0 +decl (Decl +n "D_A" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 24 +suid 95,0 +i "(others => '0')" +) +declText (MLText +uid 3515,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,22200,74000,23000" +st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0') +" +) +) +*111 (PortIoOut +uid 3516,0 +shape (CompositeShape +uid 3517,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3518,0 +sl 0 +ro 90 +xt "19000,109625,20500,110375" +) +(Line +uid 3519,0 +sl 0 +ro 90 +xt "20500,110000,21000,110000" +pts [ +"21000,110000" +"20500,110000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3520,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3521,0 +va (VaSet +) +xt "14500,109500,18000,110500" +st "DWRITE" +ju 2 +blo "18000,110300" +tm "WireNameMgr" +) +) +) +*112 (Net +uid 3522,0 +decl (Decl +n "DWRITE" +t "std_logic" +o 23 +suid 96,0 +i "'0'" +) +declText (MLText +uid 3523,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,21400,68000,22200" +st "DWRITE : std_logic := '0' +" +) +) +*113 (PortIoOut +uid 3536,0 +shape (CompositeShape +uid 3537,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3538,0 +sl 0 +ro 270 +xt "111500,86625,113000,87375" +) +(Line +uid 3539,0 +sl 0 +ro 270 +xt "111000,87000,111500,87000" +pts [ +"111000,87000" +"111500,87000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3540,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3541,0 +va (VaSet +) +xt "114000,86500,117600,87500" +st "DAC_CS" +blo "114000,87300" +tm "WireNameMgr" +) +) +) +*114 (HdlText +uid 3542,0 +optionalChildren [ +*115 (EmbeddedText +uid 3612,0 +commentText (CommentText +uid 3613,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3614,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "88000,90000,100000,96000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3615,0 +va (VaSet +) +xt "88200,90200,100100,96200" +st " +-- T_CS 5 +T0_CS <= sensor_cs (0); +T1_CS <= sensor_cs (1); +T2_CS <= sensor_cs (2); +T3_CS <= sensor_cs (3); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 3543,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "100000,88000,108000,96000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3544,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*116 (Text +uid 3545,0 +va (VaSet +font "Arial,8,1" +) +xt "103150,89000,105550,90000" +st "T_CS" +blo "103150,89800" +tm "HdlTextNameMgr" +) +*117 (Text +uid 3546,0 +va (VaSet +font "Arial,8,1" +) +xt "103150,90000,103950,91000" +st "5" +blo "103150,90800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3547,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "100250,94250,101750,95750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*118 (PortIoOut +uid 3548,0 +shape (CompositeShape +uid 3549,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3550,0 +sl 0 +ro 270 +xt "111500,88625,113000,89375" +) +(Line +uid 3551,0 +sl 0 +ro 270 +xt "111000,89000,111500,89000" +pts [ +"111000,89000" +"111500,89000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3552,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3553,0 +va (VaSet +) +xt "114000,88500,116800,89500" +st "T0_CS" +blo "114000,89300" +tm "WireNameMgr" +) +) +) +*119 (PortIoOut +uid 3554,0 +shape (CompositeShape +uid 3555,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3556,0 +sl 0 +ro 270 +xt "111500,89625,113000,90375" +) +(Line +uid 3557,0 +sl 0 +ro 270 +xt "111000,90000,111500,90000" +pts [ +"111000,90000" +"111500,90000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3558,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3559,0 +va (VaSet +) +xt "114000,89500,116800,90500" +st "T1_CS" +blo "114000,90300" +tm "WireNameMgr" +) +) +) +*120 (PortIoOut +uid 3560,0 +shape (CompositeShape +uid 3561,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3562,0 +sl 0 +ro 270 +xt "111500,90625,113000,91375" +) +(Line +uid 3563,0 +sl 0 +ro 270 +xt "111000,91000,111500,91000" +pts [ +"111000,91000" +"111500,91000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3564,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3565,0 +va (VaSet +) +xt "114000,90500,116800,91500" +st "T2_CS" +blo "114000,91300" +tm "WireNameMgr" +) +) +) +*121 (PortIoOut +uid 3566,0 +shape (CompositeShape +uid 3567,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3568,0 +sl 0 +ro 270 +xt "111500,91625,113000,92375" +) +(Line +uid 3569,0 +sl 0 +ro 270 +xt "111000,92000,111500,92000" +pts [ +"111000,92000" +"111500,92000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3570,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3571,0 +va (VaSet +) +xt "114000,91500,116800,92500" +st "T3_CS" +blo "114000,92300" +tm "WireNameMgr" +) +) +) +*122 (Net +uid 3604,0 +decl (Decl +n "T0_CS" +t "std_logic" +o 38 +suid 101,0 +) +declText (MLText +uid 3605,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,33400,53500,34200" +st "T0_CS : std_logic +" +) +) +*123 (Net +uid 3606,0 +decl (Decl +n "T1_CS" +t "std_logic" +o 39 +suid 102,0 +) +declText (MLText +uid 3607,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,34200,53500,35000" +st "T1_CS : std_logic +" +) +) +*124 (Net +uid 3608,0 +decl (Decl +n "T2_CS" +t "std_logic" +o 40 +suid 103,0 +) +declText (MLText +uid 3609,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,35000,53500,35800" +st "T2_CS : std_logic +" +) +) +*125 (Net +uid 3610,0 +decl (Decl +n "T3_CS" +t "std_logic" +o 41 +suid 104,0 +) +declText (MLText +uid 3611,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,35800,53500,36600" +st "T3_CS : std_logic +" +) +) +*126 (PortIoOut +uid 3624,0 +shape (CompositeShape +uid 3625,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3626,0 +sl 0 +ro 270 +xt "111500,97625,113000,98375" +) +(Line +uid 3627,0 +sl 0 +ro 270 +xt "111000,98000,111500,98000" +pts [ +"111000,98000" +"111500,98000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3628,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3629,0 +va (VaSet +) +xt "113750,97500,116550,98500" +st "S_CLK" +blo "113750,98300" +tm "WireNameMgr" +) +) +) +*127 (Net +uid 3630,0 +decl (Decl +n "S_CLK" +t "std_logic" +o 37 +suid 105,0 +) +declText (MLText +uid 3631,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,32600,53500,33400" +st "S_CLK : std_logic +" +) +) +*128 (Net +uid 3632,0 +decl (Decl +n "W_A" +t "std_logic_vector" +b "(9 DOWNTO 0)" +o 43 +suid 106,0 +) +declText (MLText +uid 3633,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,37400,63500,38200" +st "W_A : std_logic_vector(9 DOWNTO 0) +" +) +) +*129 (Net +uid 3634,0 +decl (Decl +n "W_D" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 49 +suid 107,0 +) +declText (MLText +uid 3635,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,42200,64000,43000" +st "W_D : std_logic_vector(15 DOWNTO 0) +" +) +) +*130 (Net +uid 3636,0 +decl (Decl +n "W_RES" +t "std_logic" +o 46 +suid 108,0 +i "'1'" +) +declText (MLText +uid 3637,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,39800,68000,40600" +st "W_RES : std_logic := '1' +" +) +) +*131 (Net +uid 3638,0 +decl (Decl +n "W_RD" +t "std_logic" +o 45 +suid 109,0 +i "'1'" +) +declText (MLText +uid 3639,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,39000,68000,39800" +st "W_RD : std_logic := '1' +" +) +) +*132 (Net +uid 3640,0 +decl (Decl +n "W_WR" +t "std_logic" +o 47 +suid 110,0 +i "'1'" +) +declText (MLText +uid 3641,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,40600,68000,41400" +st "W_WR : std_logic := '1' +" +) +) +*133 (Net +uid 3642,0 +decl (Decl +n "W_INT" +t "std_logic" +o 13 +suid 111,0 +) +declText (MLText +uid 3643,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,13400,53500,14200" +st "W_INT : std_logic +" +) +) +*134 (Net +uid 3644,0 +decl (Decl +n "W_CS" +t "std_logic" +o 44 +suid 112,0 +i "'1'" +) +declText (MLText +uid 3645,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,38200,68000,39000" +st "W_CS : std_logic := '1' +" +) +) +*135 (PortIoInOut +uid 3674,0 +shape (CompositeShape +uid 3675,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Hexagon +uid 3676,0 +sl 0 +xt "111500,98625,113000,99375" +) +(Line +uid 3677,0 +sl 0 +xt "111000,99000,111500,99000" +pts [ +"111000,99000" +"111500,99000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3678,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3679,0 +va (VaSet +) +xt "114000,98500,116400,99500" +st "MISO" +blo "114000,99300" +tm "WireNameMgr" +) +) +) +*136 (Net +uid 3680,0 +decl (Decl +n "MOSI" +t "std_logic" +o 29 +suid 113,0 +i "'0'" +) +declText (MLText +uid 3681,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,26200,68000,27000" +st "MOSI : std_logic := '0' +" +) +) +*137 (PortIoOut +uid 3688,0 +shape (CompositeShape +uid 3689,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3690,0 +sl 0 +ro 270 +xt "111500,99625,113000,100375" +) +(Line +uid 3691,0 +sl 0 +ro 270 +xt "111000,100000,111500,100000" +pts [ +"111000,100000" +"111500,100000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3692,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3693,0 +va (VaSet +) +xt "114000,99500,116400,100500" +st "MOSI" +blo "114000,100300" +tm "WireNameMgr" +) +) +) +*138 (Net +uid 3694,0 +decl (Decl +n "MISO" +t "std_logic" +preAdd 0 +posAdd 0 +o 48 +suid 114,0 +) +declText (MLText +uid 3695,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,41400,53500,42200" +st "MISO : std_logic +" +) +) +*139 (HdlText +uid 3700,0 +optionalChildren [ +*140 (EmbeddedText +uid 3706,0 +commentText (CommentText +uid 3707,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3708,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "82000,102000,100000,118000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3709,0 +va (VaSet +) +xt "82200,102200,98600,118200" +st " +-- MISC 6 +TRG_V <= '0'; +RS485_C_RE <= '1'; +RS485_C_DE <= '0'; +RS485_E_RE <= '1'; +RS485_E_DE <= '0'; + +-- DENABLE <= '0'; -- domino wave stopped +-- DENABLE <= '1'; -- domino wave running + +SRIN <= 'Z'; +EE_CS <= '1'; +-- LEDs are low active +LED(0) <= '1'; +LED(1) <= '0'; -- on +LED(2) <= '1'; + + + + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 16000 +visibleWidth 18000 +) +) +) +] +shape (Rectangle +uid 3701,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "100000,102000,108000,115000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3702,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*141 (Text +uid 3703,0 +va (VaSet +font "Arial,8,1" +) +xt "103150,106000,105550,107000" +st "MISC" +blo "103150,106800" +tm "HdlTextNameMgr" +) +*142 (Text +uid 3704,0 +va (VaSet +font "Arial,8,1" +) +xt "103150,107000,103950,108000" +st "6" +blo "103150,107800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3705,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "100250,113250,101750,114750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*143 (PortIoOut +uid 3710,0 +shape (CompositeShape +uid 3711,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3712,0 +sl 0 +ro 270 +xt "111500,102625,113000,103375" +) +(Line +uid 3713,0 +sl 0 +ro 270 +xt "111000,103000,111500,103000" +pts [ +"111000,103000" +"111500,103000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3714,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3715,0 +va (VaSet +) +xt "114000,102500,117000,103500" +st "TRG_V" +blo "114000,103300" +tm "WireNameMgr" +) +) +) +*144 (PortIoOut +uid 3716,0 +shape (CompositeShape +uid 3717,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3718,0 +sl 0 +ro 270 +xt "111500,103625,113000,104375" +) +(Line +uid 3719,0 +sl 0 +ro 270 +xt "111000,104000,111500,104000" +pts [ +"111000,104000" +"111500,104000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3720,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3721,0 +va (VaSet +) +xt "114000,103500,119600,104500" +st "RS485_C_RE" +blo "114000,104300" +tm "WireNameMgr" +) +) +) +*145 (PortIoOut +uid 3722,0 +shape (CompositeShape +uid 3723,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3724,0 +sl 0 +ro 270 +xt "111500,104625,113000,105375" +) +(Line +uid 3725,0 +sl 0 +ro 270 +xt "111000,105000,111500,105000" +pts [ +"111000,105000" +"111500,105000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3726,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3727,0 +va (VaSet +) +xt "114000,104500,119600,105500" +st "RS485_C_DE" +blo "114000,105300" +tm "WireNameMgr" +) +) +) +*146 (PortIoOut +uid 3728,0 +shape (CompositeShape +uid 3729,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3730,0 +sl 0 +ro 270 +xt "111500,105625,113000,106375" +) +(Line +uid 3731,0 +sl 0 +ro 270 +xt "111000,106000,111500,106000" +pts [ +"111000,106000" +"111500,106000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3732,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3733,0 +va (VaSet +) +xt "114000,105500,119500,106500" +st "RS485_E_RE" +blo "114000,106300" +tm "WireNameMgr" +) +) +) +*147 (PortIoOut +uid 3734,0 +shape (CompositeShape +uid 3735,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3736,0 +sl 0 +ro 270 +xt "111500,106625,113000,107375" +) +(Line +uid 3737,0 +sl 0 +ro 270 +xt "111000,107000,111500,107000" +pts [ +"111000,107000" +"111500,107000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3738,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3739,0 +va (VaSet +) +xt "114000,106500,119500,107500" +st "RS485_E_DE" +blo "114000,107300" +tm "WireNameMgr" +) +) +) +*148 (PortIoOut +uid 3740,0 +shape (CompositeShape +uid 3741,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3742,0 +sl 0 +ro 270 +xt "111500,120625,113000,121375" +) +(Line +uid 3743,0 +sl 0 +ro 270 +xt "111000,121000,111500,121000" +pts [ +"111000,121000" +"111500,121000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3744,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3745,0 +va (VaSet +) +xt "114000,120500,118000,121500" +st "DENABLE" +blo "114000,121300" +tm "WireNameMgr" +) +) +) +*149 (PortIoOut +uid 3746,0 +shape (CompositeShape +uid 3747,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3748,0 +sl 0 +ro 270 +xt "111500,108625,113000,109375" +) +(Line +uid 3749,0 +sl 0 +ro 270 +xt "111000,109000,111500,109000" +pts [ +"111000,109000" +"111500,109000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3750,0 +ps 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"D_T" +blo "114000,120300" +tm "WireNameMgr" +) +) +) +*166 (Net +uid 5320,0 +decl (Decl +n "D_T" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 25 +suid 141,0 +i "(OTHERS => '0')" +) +declText (MLText +uid 5321,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,23000,74000,23800" +st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') +" +) +) +*167 (PortIoIn +uid 5650,0 +shape (CompositeShape +uid 5651,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5652,0 +sl 0 +ro 270 +xt "9000,78625,10500,79375" +) +(Line +uid 5653,0 +sl 0 +ro 270 +xt "10500,79000,11000,79000" +pts [ +"10500,79000" +"11000,79000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 5654,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5655,0 +va (VaSet +) +xt "3500,78500,8000,79500" +st "TEST_TRG" +ju 2 +blo "8000,79300" +tm "WireNameMgr" +) +) +) +*168 (Net +uid 5662,0 +decl (Decl +n "TEST_TRG" +t "std_logic" +o 11 +suid 142,0 +) +declText (MLText +uid 5663,0 +va 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"23000,112800" +tm "WireNameMgr" +) +) +on &97 +) +*256 (Wire +uid 3438,0 +shape (OrthoPolyLine +uid 3439,0 +va (VaSet +vasetType 3 +) +xt "21000,114000,24000,114000" +pts [ +"21000,114000" +"24000,114000" +] +) +start &162 +end &93 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3442,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3443,0 +va (VaSet +isHidden 1 +) +xt "23000,113000,27400,114000" +st "D1_SRCLK" +blo "23000,113800" +tm "WireNameMgr" +) +) +on &98 +) +*257 (Wire +uid 3446,0 +shape (OrthoPolyLine +uid 3447,0 +va (VaSet +vasetType 3 +) +xt "21000,115000,24000,115000" +pts [ +"21000,115000" +"24000,115000" +] +) +start &163 +end &93 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3450,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3451,0 +va (VaSet +isHidden 1 +) +xt "23000,114000,27400,115000" +st "D2_SRCLK" +blo "23000,114800" +tm "WireNameMgr" +) +) +on &99 +) +*258 (Wire +uid 3454,0 +shape (OrthoPolyLine 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+"108000,90000" +] +) +start &119 +end &114 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3586,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3587,0 +va (VaSet +isHidden 1 +) +xt "108000,89000,110800,90000" +st "T1_CS" +blo "108000,89800" +tm "WireNameMgr" +) +) +on &123 +) +*261 (Wire +uid 3590,0 +shape (OrthoPolyLine +uid 3591,0 +va (VaSet +vasetType 3 +) +xt "108000,91000,111000,91000" +pts [ +"111000,91000" +"108000,91000" +] +) +start &120 +end &114 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3594,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3595,0 +va (VaSet +isHidden 1 +) +xt "108000,90000,110800,91000" +st "T2_CS" +blo "108000,90800" +tm "WireNameMgr" +) +) +on &124 +) +*262 (Wire +uid 3598,0 +shape (OrthoPolyLine +uid 3599,0 +va (VaSet +vasetType 3 +) +xt "108000,92000,111000,92000" +pts [ +"111000,92000" +"108000,92000" +] +) +start &121 +end &114 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3602,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3603,0 +va (VaSet +isHidden 1 +) +xt "108000,91000,110800,92000" +st "T3_CS" +blo "108000,91800" +tm "WireNameMgr" +) +) +on &125 +) +*263 (Wire +uid 3682,0 +shape (OrthoPolyLine +uid 3683,0 +va (VaSet +vasetType 3 +) +xt "80750,100000,111000,100000" +pts [ +"80750,100000" +"111000,100000" +] +) +start &42 +end &137 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3686,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3687,0 +va (VaSet +isHidden 1 +) +xt "82000,99000,84400,100000" +st "MOSI" +blo "82000,99800" +tm "WireNameMgr" +) +) +on &136 +) +*264 (Wire +uid 3778,0 +shape (OrthoPolyLine +uid 3779,0 +va (VaSet +vasetType 3 +) +xt "108000,103000,111000,103000" +pts [ +"111000,103000" +"108000,103000" +] +) +start &143 +end &139 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3782,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3783,0 +va (VaSet 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"108000,104800" +tm "WireNameMgr" +) +) +on &154 +) +*267 (Wire +uid 3802,0 +shape (OrthoPolyLine +uid 3803,0 +va (VaSet +vasetType 3 +) +xt "108000,106000,111000,106000" +pts [ +"111000,106000" +"108000,106000" +] +) +start &146 +end &139 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3806,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3807,0 +va (VaSet +isHidden 1 +) +xt "108000,105000,113500,106000" +st "RS485_E_RE" +blo "108000,105800" +tm "WireNameMgr" +) +) +on &155 +) +*268 (Wire +uid 3810,0 +shape (OrthoPolyLine +uid 3811,0 +va (VaSet +vasetType 3 +) +xt "108000,107000,111000,107000" +pts [ +"111000,107000" +"108000,107000" +] +) +start &147 +end &139 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3814,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3815,0 +va (VaSet +isHidden 1 +) +xt "108000,106000,113500,107000" +st "RS485_E_DE" +blo "108000,106800" +tm "WireNameMgr" +) +) +on &156 +) +*269 (Wire +uid 3826,0 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+) +stc 0 +sf 1 +tg (WTG +uid 482,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 483,0 +va (VaSet +) +xt "114000,67500,116000,68500" +st "W_A" +blo "114000,68300" +tm "WireNameMgr" +) +) +) +*57 (PortIoOut +uid 484,0 +shape (CompositeShape +uid 485,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 486,0 +sl 0 +ro 270 +xt "111500,74625,113000,75375" +) +(Line +uid 487,0 +sl 0 +ro 270 +xt "111000,75000,111500,75000" +pts [ +"111000,75000" +"111500,75000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 488,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 489,0 +va (VaSet +) +xt "114000,74500,116600,75500" +st "W_CS" +blo "114000,75300" +tm "WireNameMgr" +) +) +) +*58 (PortIoInOut +uid 490,0 +shape (CompositeShape +uid 491,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Hexagon +uid 492,0 +sl 0 +xt "111500,68625,113000,69375" +) +(Line +uid 493,0 +sl 0 +xt "111000,69000,111500,69000" +pts [ +"111000,69000" +"111500,69000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 494,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 495,0 +va (VaSet +) +xt "114000,68500,116100,69500" +st "W_D" +blo "114000,69300" +tm "WireNameMgr" +) +) +) +*59 (PortIoIn +uid 496,0 +shape (CompositeShape +uid 497,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 498,0 +sl 0 +ro 90 +xt "111500,73625,113000,74375" +) +(Line +uid 499,0 +sl 0 +ro 90 +xt "111000,74000,111500,74000" +pts [ +"111500,74000" +"111000,74000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 500,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 501,0 +va (VaSet +) +xt "114000,73500,116800,74500" +st "W_INT" +blo "114000,74300" +tm "WireNameMgr" +) +) +) +*60 (PortIoOut +uid 502,0 +shape (CompositeShape +uid 503,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 504,0 +sl 0 +ro 270 +xt "111500,71625,113000,72375" +) +(Line +uid 505,0 +sl 0 +ro 270 +xt "111000,72000,111500,72000" +pts [ +"111000,72000" +"111500,72000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 506,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 507,0 +va (VaSet +) +xt "114000,71500,116700,72500" +st "W_RD" +blo "114000,72300" +tm "WireNameMgr" +) +) +) +*61 (PortIoOut +uid 508,0 +shape (CompositeShape +uid 509,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 510,0 +sl 0 +ro 270 +xt "111500,72625,113000,73375" +) +(Line +uid 511,0 +sl 0 +ro 270 +xt "111000,73000,111500,73000" +pts [ +"111000,73000" +"111500,73000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 512,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 513,0 +va (VaSet +) +xt "114000,72500,116800,73500" +st "W_WR" +blo "114000,73300" +tm "WireNameMgr" +) +) +) +*62 (Net +uid 1465,0 +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 55 +suid 29,0 +) +declText (MLText +uid 1466,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,48000,62500,48800" +st "SIGNAL adc_data_array : adc_data_array_type" +) +) +*63 (Net +uid 2407,0 +decl (Decl +n "RSRLOAD" +t "std_logic" +o 36 +suid 57,0 +i "'0'" +) +declText (MLText +uid 2408,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,31800,68000,32600" +st "RSRLOAD : std_logic := '0'" +) +) +*64 (PortIoOut +uid 2415,0 +shape (CompositeShape +uid 2416,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2417,0 +sl 0 +ro 90 +xt "19000,110625,20500,111375" +) +(Line +uid 2418,0 +sl 0 +ro 90 +xt "20500,111000,21000,111000" +pts [ +"21000,111000" +"20500,111000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2419,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2420,0 +va (VaSet +) +xt "13800,110500,18000,111500" +st "RSRLOAD" +ju 2 +blo "18000,111300" +tm "WireNameMgr" +) +) +) +*65 (Net +uid 2421,0 +decl (Decl +n "SRCLK" +t "std_logic" +o 53 +suid 58,0 +i "'0'" +) +declText (MLText +uid 2422,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,46400,71500,47200" +st "SIGNAL SRCLK : std_logic := '0'" +) +) +*66 (Net +uid 3019,0 +decl (Decl +n "sensor_cs" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 60 +suid 65,0 +) +declText (MLText +uid 3020,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,52000,67000,52800" +st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" +) +) +*67 (Net +uid 3025,0 +decl (Decl +n "DAC_CS" +t "std_logic" +o 22 +suid 66,0 +) +declText (MLText +uid 3026,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,20600,53500,21400" +st "DAC_CS : std_logic" +) +) +*68 (PortIoOut +uid 3153,0 +shape (CompositeShape +uid 3154,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3155,0 +sl 0 +ro 90 +xt "19000,69625,20500,70375" +) +(Line +uid 3156,0 +sl 0 +ro 90 +xt "20500,70000,21000,70000" +pts [ +"21000,70000" +"20500,70000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3157,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3158,0 +va (VaSet +) +xt "15200,69500,18000,70500" +st "A_CLK" +ju 2 +blo "18000,70300" +tm "WireNameMgr" +) +) +) +*69 (Net +uid 3216,0 +decl (Decl +n "X_50M" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 14 +suid 67,0 +) +declText (MLText +uid 3217,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,14200,53500,15000" +st "X_50M : STD_LOGIC" +) +) +*70 (Net +uid 3226,0 +decl (Decl +n "TRG" +t "STD_LOGIC" +o 12 +suid 68,0 +) +declText (MLText +uid 3227,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,12600,53500,13400" +st "TRG : STD_LOGIC" +) +) +*71 (HdlText +uid 3248,0 +optionalChildren [ +*72 (EmbeddedText +uid 3254,0 +commentText (CommentText +uid 3255,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3256,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "32000,71000,44000,77000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3257,0 +va (VaSet +) +xt "32200,71200,44100,77200" +st " +-- ADC_CLK 2 +A_CLK (0) <= CLK_25_PS; +A_CLK (1) <= CLK_25_PS; +A_CLK (2) <= CLK_25_PS; +A_CLK (3) <= CLK_25_PS; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 3249,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "24000,69000,32000,77000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3250,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*73 (Text +uid 3251,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,70000,31350,71000" +st "ADC_CLK" +blo "27150,70800" +tm "HdlTextNameMgr" +) +*74 (Text +uid 3252,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,71000,27950,72000" +st "2" +blo "27150,71800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3253,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "24250,75250,25750,76750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*75 (Net +uid 3266,0 +decl (Decl +n "A_CLK" +t "std_logic_vector" +b "(3 downto 0)" +o 17 +suid 71,0 +) +declText (MLText +uid 3267,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,16600,63500,17400" +st "A_CLK : std_logic_vector(3 downto 0)" +) +) +*76 (Net +uid 3268,0 +decl (Decl +n "CLK_25_PS" +t "std_logic" +o 51 +suid 72,0 +) +declText (MLText +uid 3269,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,44800,57000,45600" +st "SIGNAL CLK_25_PS : std_logic" +) +) +*77 (PortIoOut +uid 3284,0 +shape (CompositeShape +uid 3285,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3286,0 +sl 0 +ro 90 +xt "19000,89625,20500,90375" +) +(Line +uid 3287,0 +sl 0 +ro 90 +xt "20500,90000,21000,90000" +pts [ +"21000,90000" +"20500,90000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3288,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3289,0 +va (VaSet +) +xt "14400,89500,18000,90500" +st "OE_ADC" +ju 2 +blo "18000,90300" +tm "WireNameMgr" +) +) +) +*78 (Net +uid 3290,0 +decl (Decl +n "OE_ADC" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 31 +suid 73,0 +) +declText (MLText +uid 3291,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,27800,53500,28600" +st "OE_ADC : STD_LOGIC" +) +) +*79 (PortIoIn +uid 3292,0 +shape (CompositeShape +uid 3293,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3294,0 +sl 0 +ro 270 +xt "19000,88625,20500,89375" +) +(Line +uid 3295,0 +sl 0 +ro 270 +xt "20500,89000,21000,89000" +pts [ +"20500,89000" +"21000,89000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3296,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3297,0 +va (VaSet +) +xt "15000,88500,18000,89500" +st "A_OTR" +ju 2 +blo "18000,89300" +tm "WireNameMgr" +) +) +) +*80 (Net +uid 3298,0 +decl (Decl +n "A_OTR" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 5 +suid 74,0 +) +declText (MLText +uid 3299,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,7000,63500,7800" +st "A_OTR : std_logic_vector(3 DOWNTO 0)" +) +) +*81 (HdlText +uid 3300,0 +optionalChildren [ +*82 (EmbeddedText +uid 3306,0 +commentText (CommentText +uid 3307,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3308,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "32000,96000,44000,102000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3309,0 +va (VaSet +) +xt "32200,96200,44200,102200" +st " +-- ADC_DATA 3 +adc_data_array (0) <= A0_D; +adc_data_array (1) <= A1_D; +adc_data_array (2) <= A2_D; +adc_data_array (3) <= A3_D; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 3301,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "24000,94000,32000,102000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3302,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*83 (Text +uid 3303,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,95000,31750,96000" +st "ADC_DATA" +blo "27150,95800" +tm "HdlTextNameMgr" +) +*84 (Text +uid 3304,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,96000,27950,97000" +st "3" +blo "27150,96800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3305,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "24250,100250,25750,101750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*85 (PortIoIn +uid 3310,0 +shape (CompositeShape +uid 3311,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3312,0 +sl 0 +ro 270 +xt "19000,94625,20500,95375" +) +(Line +uid 3313,0 +sl 0 +ro 270 +xt "20500,95000,21000,95000" +pts [ +"20500,95000" +"21000,95000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3314,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3315,0 +va (VaSet +) +xt "15700,94500,18000,95500" +st "A0_D" +ju 2 +blo "18000,95300" +tm "WireNameMgr" +) +) +) +*86 (PortIoIn +uid 3332,0 +shape (CompositeShape +uid 3333,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3334,0 +sl 0 +ro 270 +xt "19000,95625,20500,96375" +) +(Line +uid 3335,0 +sl 0 +ro 270 +xt "20500,96000,21000,96000" +pts [ +"20500,96000" +"21000,96000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3336,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3337,0 +va (VaSet +) +xt "15700,95500,18000,96500" +st "A1_D" +ju 2 +blo "18000,96300" +tm "WireNameMgr" +) +) +) +*87 (PortIoIn +uid 3338,0 +shape (CompositeShape +uid 3339,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3340,0 +sl 0 +ro 270 +xt "19000,96625,20500,97375" +) +(Line +uid 3341,0 +sl 0 +ro 270 +xt "20500,97000,21000,97000" +pts [ +"20500,97000" +"21000,97000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3342,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3343,0 +va (VaSet +) +xt "15700,96500,18000,97500" +st "A2_D" +ju 2 +blo "18000,97300" +tm "WireNameMgr" +) +) +) +*88 (PortIoIn +uid 3344,0 +shape (CompositeShape +uid 3345,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3346,0 +sl 0 +ro 270 +xt "19000,97625,20500,98375" +) +(Line +uid 3347,0 +sl 0 +ro 270 +xt "20500,98000,21000,98000" +pts [ +"20500,98000" +"21000,98000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3348,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3349,0 +va (VaSet +) +xt "15700,97500,18000,98500" +st "A3_D" +ju 2 +blo "18000,98300" +tm "WireNameMgr" +) +) +) +*89 (Net +uid 3374,0 +decl (Decl +n "A0_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 1 +suid 79,0 +) +declText (MLText +uid 3375,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,3800,64000,4600" +st "A0_D : std_logic_vector(11 DOWNTO 0)" +) +) +*90 (Net +uid 3376,0 +decl (Decl +n "A1_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 2 +suid 80,0 +) +declText (MLText +uid 3377,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,4600,64000,5400" +st "A1_D : std_logic_vector(11 DOWNTO 0)" +) +) +*91 (Net +uid 3378,0 +decl (Decl +n "A2_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 3 +suid 81,0 +) +declText (MLText +uid 3379,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,5400,64000,6200" +st "A2_D : std_logic_vector(11 DOWNTO 0)" +) +) +*92 (Net +uid 3380,0 +decl (Decl +n "A3_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 4 +suid 82,0 +) +declText (MLText +uid 3381,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,6200,64000,7000" +st "A3_D : std_logic_vector(11 DOWNTO 0)" +) +) +*93 (HdlText +uid 3394,0 +optionalChildren [ +*94 (EmbeddedText +uid 3400,0 +commentText (CommentText +uid 3401,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3402,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "32000,114000,44000,120000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3403,0 +va (VaSet +) +xt "32200,114200,44200,120200" +st " +-- SRCLK 4 +D0_SRCLK <= SRCLK; +D1_SRCLK <= SRCLK; +D2_SRCLK <= SRCLK; +D3_SRCLK <= SRCLK; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 3395,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "24000,112000,32000,120000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3396,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*95 (Text +uid 3397,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,113000,30350,114000" +st "SRCLK" +blo "27150,113800" +tm "HdlTextNameMgr" +) +*96 (Text +uid 3398,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,114000,27950,115000" +st "4" +blo "27150,114800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3399,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "24250,118250,25750,119750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*97 (Net +uid 3460,0 +decl (Decl +n "D0_SRCLK" +t "STD_LOGIC" +o 18 +suid 87,0 +) +declText (MLText +uid 3461,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,17400,53500,18200" +st "D0_SRCLK : STD_LOGIC" +) +) +*98 (Net +uid 3462,0 +decl (Decl +n "D1_SRCLK" +t "STD_LOGIC" +o 19 +suid 88,0 +) +declText (MLText +uid 3463,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,18200,53500,19000" +st "D1_SRCLK : STD_LOGIC" +) +) +*99 (Net +uid 3464,0 +decl (Decl +n "D2_SRCLK" +t "STD_LOGIC" +o 20 +suid 89,0 +) +declText (MLText +uid 3465,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,19000,53500,19800" +st "D2_SRCLK : STD_LOGIC" +) +) +*100 (Net +uid 3466,0 +decl (Decl +n "D3_SRCLK" +t "STD_LOGIC" +o 21 +suid 90,0 +) +declText (MLText +uid 3467,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,19800,53500,20600" +st "D3_SRCLK : STD_LOGIC" +) +) +*101 (PortIoIn +uid 3476,0 +shape (CompositeShape +uid 3477,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3478,0 +sl 0 +ro 270 +xt "19000,104625,20500,105375" +) +(Line +uid 3479,0 +sl 0 +ro 270 +xt "20500,105000,21000,105000" +pts [ +"20500,105000" +"21000,105000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3480,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3481,0 +va (VaSet +) +xt "13400,104500,18000,105500" +st "D0_SROUT" +ju 2 +blo "18000,105300" +tm "WireNameMgr" +) +) +) +*102 (PortIoIn +uid 3482,0 +shape (CompositeShape +uid 3483,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3484,0 +sl 0 +ro 270 +xt "19000,105625,20500,106375" +) +(Line +uid 3485,0 +sl 0 +ro 270 +xt "20500,106000,21000,106000" +pts [ +"20500,106000" +"21000,106000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3486,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3487,0 +va (VaSet +) +xt "13400,105500,18000,106500" +st "D1_SROUT" +ju 2 +blo "18000,106300" +tm "WireNameMgr" +) +) +) +*103 (PortIoIn +uid 3488,0 +shape (CompositeShape +uid 3489,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3490,0 +sl 0 +ro 270 +xt "19000,106625,20500,107375" +) +(Line +uid 3491,0 +sl 0 +ro 270 +xt "20500,107000,21000,107000" +pts [ +"20500,107000" +"21000,107000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3492,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3493,0 +va (VaSet +) +xt "13400,106500,18000,107500" +st "D2_SROUT" +ju 2 +blo "18000,107300" +tm "WireNameMgr" +) +) +) +*104 (PortIoIn +uid 3494,0 +shape (CompositeShape +uid 3495,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3496,0 +sl 0 +ro 270 +xt "19000,107625,20500,108375" +) +(Line +uid 3497,0 +sl 0 +ro 270 +xt "20500,108000,21000,108000" +pts [ +"20500,108000" +"21000,108000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3498,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3499,0 +va (VaSet +) +xt "13400,107500,18000,108500" +st "D3_SROUT" +ju 2 +blo "18000,108300" +tm "WireNameMgr" +) +) +) +*105 (Net +uid 3500,0 +decl (Decl +n "D0_SROUT" +t "std_logic" +o 6 +suid 91,0 +) +declText (MLText +uid 3501,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,7800,53500,8600" +st "D0_SROUT : std_logic" +) +) +*106 (Net +uid 3502,0 +decl (Decl +n "D1_SROUT" +t "std_logic" +o 7 +suid 92,0 +) +declText (MLText +uid 3503,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,8600,53500,9400" +st "D1_SROUT : std_logic" +) +) +*107 (Net +uid 3504,0 +decl (Decl +n "D2_SROUT" +t "std_logic" +o 8 +suid 93,0 +) +declText (MLText +uid 3505,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,9400,53500,10200" +st "D2_SROUT : std_logic" +) +) +*108 (Net +uid 3506,0 +decl (Decl +n "D3_SROUT" +t "std_logic" +o 9 +suid 94,0 +) +declText (MLText +uid 3507,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,10200,53500,11000" +st "D3_SROUT : std_logic" +) +) +*109 (PortIoOut +uid 3508,0 +shape (CompositeShape +uid 3509,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3510,0 +sl 0 +ro 90 +xt "4000,133625,5500,134375" +) +(Line +uid 3511,0 +sl 0 +ro 90 +xt "5500,134000,6000,134000" +pts [ +"6000,134000" +"5500,134000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3512,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3513,0 +va (VaSet +) +xt "1100,133500,3000,134500" +st "D_A" +ju 2 +blo "3000,134300" +tm "WireNameMgr" +) +) +) +*110 (Net +uid 3514,0 +decl (Decl +n "D_A" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 25 +suid 95,0 +i "(others => '0')" +) +declText (MLText +uid 3515,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,23000,74000,23800" +st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0')" +) +) +*111 (PortIoOut +uid 3516,0 +shape (CompositeShape +uid 3517,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3518,0 +sl 0 +ro 90 +xt "19000,109625,20500,110375" +) +(Line +uid 3519,0 +sl 0 +ro 90 +xt "20500,110000,21000,110000" +pts [ +"21000,110000" +"20500,110000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3520,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3521,0 +va (VaSet +) +xt "14500,109500,18000,110500" +st "DWRITE" +ju 2 +blo "18000,110300" +tm "WireNameMgr" +) +) +) +*112 (Net +uid 3522,0 +decl (Decl +n "DWRITE" +t "std_logic" +o 24 +suid 96,0 +i "'0'" +) +declText (MLText +uid 3523,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,22200,68000,23000" +st "DWRITE : std_logic := '0'" +) +) +*113 (PortIoOut +uid 3536,0 +shape (CompositeShape +uid 3537,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3538,0 +sl 0 +ro 270 +xt "111500,86625,113000,87375" +) +(Line +uid 3539,0 +sl 0 +ro 270 +xt "111000,87000,111500,87000" +pts [ +"111000,87000" +"111500,87000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3540,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3541,0 +va (VaSet +) +xt "114000,86500,117600,87500" +st "DAC_CS" +blo "114000,87300" +tm "WireNameMgr" +) +) +) +*114 (HdlText +uid 3542,0 +optionalChildren [ +*115 (EmbeddedText +uid 3612,0 +commentText (CommentText +uid 3613,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3614,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "88000,90000,100000,96000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3615,0 +va (VaSet +) +xt "88200,90200,100100,96200" +st " +-- T_CS 5 +T0_CS <= sensor_cs (0); +T1_CS <= sensor_cs (1); +T2_CS <= sensor_cs (2); +T3_CS <= sensor_cs (3); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 3543,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "100000,88000,108000,96000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3544,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*116 (Text +uid 3545,0 +va (VaSet +font "Arial,8,1" +) +xt "103150,89000,105550,90000" +st "T_CS" +blo "103150,89800" +tm "HdlTextNameMgr" +) +*117 (Text +uid 3546,0 +va (VaSet +font "Arial,8,1" +) +xt "103150,90000,103950,91000" +st "5" +blo "103150,90800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3547,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "100250,94250,101750,95750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*118 (PortIoOut +uid 3548,0 +shape (CompositeShape +uid 3549,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3550,0 +sl 0 +ro 270 +xt "111500,88625,113000,89375" +) +(Line +uid 3551,0 +sl 0 +ro 270 +xt "111000,89000,111500,89000" +pts [ +"111000,89000" +"111500,89000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3552,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3553,0 +va (VaSet +) +xt "114000,88500,116800,89500" +st "T0_CS" +blo "114000,89300" +tm "WireNameMgr" +) +) +) +*119 (PortIoOut +uid 3554,0 +shape (CompositeShape +uid 3555,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3556,0 +sl 0 +ro 270 +xt "111500,89625,113000,90375" +) +(Line +uid 3557,0 +sl 0 +ro 270 +xt "111000,90000,111500,90000" +pts [ +"111000,90000" +"111500,90000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3558,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3559,0 +va (VaSet +) +xt "114000,89500,116800,90500" +st "T1_CS" +blo "114000,90300" +tm "WireNameMgr" +) +) +) +*120 (PortIoOut +uid 3560,0 +shape (CompositeShape +uid 3561,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3562,0 +sl 0 +ro 270 +xt "111500,90625,113000,91375" +) +(Line +uid 3563,0 +sl 0 +ro 270 +xt "111000,91000,111500,91000" +pts [ +"111000,91000" +"111500,91000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3564,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3565,0 +va (VaSet +) +xt "114000,90500,116800,91500" +st "T2_CS" +blo "114000,91300" +tm "WireNameMgr" +) +) +) +*121 (PortIoOut +uid 3566,0 +shape (CompositeShape +uid 3567,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3568,0 +sl 0 +ro 270 +xt "111500,91625,113000,92375" +) +(Line +uid 3569,0 +sl 0 +ro 270 +xt "111000,92000,111500,92000" +pts [ +"111000,92000" +"111500,92000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3570,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3571,0 +va (VaSet +) +xt "114000,91500,116800,92500" +st "T3_CS" +blo "114000,92300" +tm "WireNameMgr" +) +) +) +*122 (Net +uid 3604,0 +decl (Decl +n "T0_CS" +t "std_logic" +o 39 +suid 101,0 +) +declText (MLText +uid 3605,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,34200,53500,35000" +st "T0_CS : std_logic" +) +) +*123 (Net +uid 3606,0 +decl (Decl +n "T1_CS" +t "std_logic" +o 40 +suid 102,0 +) +declText (MLText +uid 3607,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,35000,53500,35800" +st "T1_CS : std_logic" +) +) +*124 (Net +uid 3608,0 +decl (Decl +n "T2_CS" +t "std_logic" +o 41 +suid 103,0 +) +declText (MLText +uid 3609,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,35800,53500,36600" +st "T2_CS : std_logic" +) +) +*125 (Net +uid 3610,0 +decl (Decl +n "T3_CS" +t "std_logic" +o 42 +suid 104,0 +) +declText (MLText +uid 3611,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,36600,53500,37400" +st "T3_CS : std_logic" +) +) +*126 (PortIoOut +uid 3624,0 +shape (CompositeShape +uid 3625,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3626,0 +sl 0 +ro 270 +xt "111500,97625,113000,98375" +) +(Line +uid 3627,0 +sl 0 +ro 270 +xt "111000,98000,111500,98000" +pts [ +"111000,98000" +"111500,98000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3628,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3629,0 +va (VaSet +) +xt "113750,97500,116550,98500" +st "S_CLK" +blo "113750,98300" +tm "WireNameMgr" +) +) +) +*127 (Net +uid 3630,0 +decl (Decl +n "S_CLK" +t "std_logic" +o 38 +suid 105,0 +) +declText (MLText +uid 3631,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,33400,53500,34200" +st "S_CLK : std_logic" +) +) +*128 (Net +uid 3632,0 +decl (Decl +n "W_A" +t "std_logic_vector" +b "(9 DOWNTO 0)" +o 44 +suid 106,0 +) +declText (MLText +uid 3633,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,38200,63500,39000" +st "W_A : std_logic_vector(9 DOWNTO 0)" +) +) +*129 (Net +uid 3634,0 +decl (Decl +n "W_D" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 50 +suid 107,0 +) +declText (MLText +uid 3635,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,43000,64000,43800" +st "W_D : std_logic_vector(15 DOWNTO 0)" +) +) +*130 (Net +uid 3636,0 +decl (Decl +n "W_RES" +t "std_logic" +o 47 +suid 108,0 +i "'1'" +) +declText (MLText +uid 3637,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,40600,68000,41400" +st "W_RES : std_logic := '1'" +) +) +*131 (Net +uid 3638,0 +decl (Decl +n "W_RD" +t "std_logic" +o 46 +suid 109,0 +i "'1'" +) +declText (MLText +uid 3639,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,39800,68000,40600" +st "W_RD : std_logic := '1'" +) +) +*132 (Net +uid 3640,0 +decl (Decl +n "W_WR" +t "std_logic" +o 48 +suid 110,0 +i "'1'" +) +declText (MLText +uid 3641,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,41400,68000,42200" +st "W_WR : std_logic := '1'" +) +) +*133 (Net +uid 3642,0 +decl (Decl +n "W_INT" +t "std_logic" +o 13 +suid 111,0 +) +declText (MLText +uid 3643,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,13400,53500,14200" +st "W_INT : std_logic" +) +) +*134 (Net +uid 3644,0 +decl (Decl +n "W_CS" +t "std_logic" +o 45 +suid 112,0 +i "'1'" +) +declText (MLText +uid 3645,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,39000,68000,39800" +st "W_CS : std_logic := '1'" +) +) +*135 (PortIoInOut +uid 3674,0 +shape (CompositeShape +uid 3675,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Hexagon +uid 3676,0 +sl 0 +xt "111500,98625,113000,99375" +) +(Line +uid 3677,0 +sl 0 +xt "111000,99000,111500,99000" +pts [ +"111000,99000" +"111500,99000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3678,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3679,0 +va (VaSet +) +xt "114000,98500,116400,99500" +st "MISO" +blo "114000,99300" +tm "WireNameMgr" +) +) +) +*136 (Net +uid 3680,0 +decl (Decl +n "MOSI" +t "std_logic" +o 30 +suid 113,0 +i "'0'" +) +declText (MLText +uid 3681,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,27000,68000,27800" +st "MOSI : std_logic := '0'" +) +) +*137 (PortIoOut +uid 3688,0 +shape (CompositeShape +uid 3689,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3690,0 +sl 0 +ro 270 +xt "111500,99625,113000,100375" +) +(Line +uid 3691,0 +sl 0 +ro 270 +xt "111000,100000,111500,100000" +pts [ +"111000,100000" +"111500,100000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3692,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3693,0 +va (VaSet +) +xt "114000,99500,116400,100500" +st "MOSI" +blo "114000,100300" +tm "WireNameMgr" +) +) +) +*138 (Net +uid 3694,0 +decl (Decl +n "MISO" +t "std_logic" +preAdd 0 +posAdd 0 +o 49 +suid 114,0 +) +declText (MLText +uid 3695,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,42200,53500,43000" +st "MISO : std_logic" +) +) +*139 (HdlText +uid 3700,0 +optionalChildren [ +*140 (EmbeddedText +uid 3706,0 +commentText (CommentText +uid 3707,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3708,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "82000,102000,100000,118000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3709,0 +va (VaSet +) +xt "82200,102200,98600,118200" +st " +-- MISC 6 +TRG_V <= '0'; +RS485_C_RE <= '1'; +RS485_C_DE <= '0'; +RS485_E_RE <= '1'; +RS485_E_DE <= '0'; + +-- DENABLE <= '0'; -- domino wave stopped +-- DENABLE <= '1'; -- domino wave running + +SRIN <= 'Z'; +EE_CS <= '1'; +-- LEDs are low active +LED(0) <= '1'; +LED(1) <= '0'; -- on +LED(2) <= '1'; + + + + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 16000 +visibleWidth 18000 +) +) +) +] +shape (Rectangle +uid 3701,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "100000,102000,108000,115000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3702,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*141 (Text +uid 3703,0 +va (VaSet +font "Arial,8,1" +) +xt "103150,106000,105550,107000" +st "MISC" +blo "103150,106800" +tm "HdlTextNameMgr" +) +*142 (Text +uid 3704,0 +va (VaSet +font "Arial,8,1" +) +xt "103150,107000,103950,108000" +st "6" +blo "103150,107800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3705,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "100250,113250,101750,114750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*143 (PortIoOut +uid 3710,0 +shape (CompositeShape +uid 3711,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3712,0 +sl 0 +ro 270 +xt "111500,102625,113000,103375" +) +(Line +uid 3713,0 +sl 0 +ro 270 +xt "111000,103000,111500,103000" +pts [ +"111000,103000" +"111500,103000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3714,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3715,0 +va (VaSet +) +xt "114000,102500,117000,103500" +st "TRG_V" +blo "114000,103300" +tm "WireNameMgr" +) +) +) +*144 (PortIoOut +uid 3716,0 +shape (CompositeShape +uid 3717,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3718,0 +sl 0 +ro 270 +xt "111500,103625,113000,104375" +) +(Line +uid 3719,0 +sl 0 +ro 270 +xt "111000,104000,111500,104000" +pts [ +"111000,104000" +"111500,104000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3720,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3721,0 +va (VaSet +) +xt "114000,103500,119600,104500" +st "RS485_C_RE" +blo "114000,104300" +tm "WireNameMgr" +) +) +) +*145 (PortIoOut +uid 3722,0 +shape (CompositeShape +uid 3723,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3724,0 +sl 0 +ro 270 +xt "111500,104625,113000,105375" +) +(Line +uid 3725,0 +sl 0 +ro 270 +xt "111000,105000,111500,105000" +pts [ +"111000,105000" +"111500,105000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3726,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3727,0 +va (VaSet +) +xt "114000,104500,119600,105500" +st "RS485_C_DE" +blo "114000,105300" +tm "WireNameMgr" +) +) +) +*146 (PortIoOut +uid 3728,0 +shape (CompositeShape +uid 3729,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3730,0 +sl 0 +ro 270 +xt "111500,105625,113000,106375" +) +(Line +uid 3731,0 +sl 0 +ro 270 +xt "111000,106000,111500,106000" +pts [ +"111000,106000" +"111500,106000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3732,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3733,0 +va (VaSet +) +xt "114000,105500,119500,106500" +st "RS485_E_RE" +blo "114000,106300" +tm "WireNameMgr" +) +) +) +*147 (PortIoOut +uid 3734,0 +shape (CompositeShape +uid 3735,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ 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132,0 +) +declText (MLText +uid 3877,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,32600,53500,33400" +st "SRIN : std_logic" +) +) +*159 (Net +uid 3878,0 +decl (Decl +n "EE_CS" +t "std_logic" +o 28 +suid 133,0 +) +declText (MLText +uid 3879,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,25400,53500,26200" +st "EE_CS : std_logic" +) +) +*160 (Net +uid 3880,0 +decl (Decl +n "LED" +t "std_logic_vector" +b "( 2 DOWNTO 0 )" +o 29 +suid 134,0 +i "(others => '1')" +) +declText (MLText +uid 3881,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,26200,74000,27000" +st "LED : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')" +) +) +*161 (PortIoOut +uid 3995,0 +shape (CompositeShape +uid 3996,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3997,0 +sl 0 +ro 90 +xt "19000,112625,20500,113375" +) +(Line +uid 3998,0 +sl 0 +ro 90 +xt "20500,113000,21000,113000" +pts [ +"21000,113000" +"20500,113000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3999,0 +ps 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5654,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5655,0 +va (VaSet +) +xt "3500,78500,8000,79500" +st "TEST_TRG" +ju 2 +blo "8000,79300" +tm "WireNameMgr" +) +) +) +*168 (Net +uid 5662,0 +decl (Decl +n "TEST_TRG" +t "std_logic" +o 11 +suid 142,0 +) +declText (MLText +uid 5663,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,11800,53500,12600" +st "TEST_TRG : std_logic" +) +) +*169 (Net +uid 6138,0 +decl (Decl +n "TRG_OR" +t "std_logic" +o 54 +suid 146,0 +) +declText (MLText +uid 6139,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,47200,57000,48000" +st "SIGNAL TRG_OR : std_logic" +) +) +*170 (MWC +uid 6586,0 +optionalChildren [ +*171 (CptPort +uid 6550,0 +optionalChildren [ +*172 (Line +uid 6554,0 +layer 5 +sl 0 +va (VaSet +vasetType 3 +) +xt "13000,79000,14589,79000" +pts [ +"13000,79000" +"14589,79000" +] +) +] +ps "OnEdgeStrategy" +shape (Triangle +uid 6551,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,65535" +) +xt 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"7000,6003,11000,8000" +) +*179 (CommentGraphic +uid 6568,0 +shape (Arc2D +pts [ +"18000,78005" +"16449,79394" +"13996,79998" +] +uid 6569,0 +layer 0 +sl 0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +bg "0,65535,65535" +lineColor "26368,26368,26368" +) +xt "13996,78005,18000,80000" +) +oxt "6996,8005,11000,10000" +) +*180 (Grouping +uid 6570,0 +optionalChildren [ +*181 (CommentGraphic +uid 6572,0 +optionalChildren [ +*182 (Property +uid 6574,0 +pclass "_MW_GEOM_" +pname "arc" +ptn "String" +) +] +shape (CustomPolygon +pts [ +"14000,79998" +"14000,76000" +"15183,76211" +"16952,77156" +"18000,78000" +"16048,79132" +"14000,79998" +] +uid 6573,0 +layer 0 +sl 0 +va (VaSet +vasetType 1 +transparent 1 +fg "0,65535,65535" +lineColor "32768,0,32768" +fillStyle 1 +) +xt "14000,76000,18000,79998" +) +oxt "7000,6000,11000,9998" +) +*183 (CommentGraphic +uid 6575,0 +optionalChildren [ +*184 (Property +uid 6577,0 +pclass "_MW_GEOM_" +pname "arc" +ptn "String" +) +] +shape (Arc2D +pts [ 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+blo "90000,132300" +tm "WireNameMgr" +) +) +) +*194 (Net +uid 6793,0 +decl (Decl +n "D_PLLLCK" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 10 +suid 152,0 +) +declText (MLText +uid 6794,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,11000,63500,11800" +st "D_PLLLCK : std_logic_vector(3 DOWNTO 0)" +) +) +*195 (PortIoOut +uid 6874,0 +shape (CompositeShape +uid 6875,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 6876,0 +sl 0 +ro 270 +xt "109500,131625,111000,132375" +) +(Line +uid 6877,0 +sl 0 +ro 270 +xt "109000,132000,109500,132000" +pts [ +"109000,132000" +"109500,132000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 6878,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6879,0 +va (VaSet +) +xt "112000,131500,114300,132500" +st "D_T2" +blo "112000,132300" +tm "WireNameMgr" +) +) +) +*196 (Net +uid 6886,0 +decl (Decl +n "D_T2" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 27 +suid 154,0 +i "(others => '0')" +) +declText (MLText +uid 6887,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,24600,74000,25400" +st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0')" +) +) +*197 (HdlText +uid 6888,0 +optionalChildren [ +*198 (EmbeddedText +uid 6894,0 +commentText (CommentText +uid 6895,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 6896,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "96000,128000,106000,131000" +) +oxt "0,0,18000,5000" +text (MLText +uid 6897,0 +va (VaSet +) +xt "96200,128200,104300,129200" +st " +D_T2 <= D_PLLLCK; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 3000 +visibleWidth 10000 +) +) +) +] +shape (Rectangle +uid 6889,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "99000,131000,102000,134000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 6890,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*199 (Text +uid 6891,0 +va (VaSet +font "Arial,8,1" +) +xt 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1734,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1735,0 +va (VaSet +isHidden 1 +) +xt "22000,88000,25000,89000" +st "A_OTR" +blo "22000,88800" +tm "WireNameMgr" +) +) +on &80 +) +*238 (Wire +uid 1833,0 +shape (OrthoPolyLine +uid 1834,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "6000,134000,31000,134000" +pts [ +"31000,134000" +"6000,134000" +] +) +start &201 +end &109 +sat 2 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1837,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1838,0 +va (VaSet +isHidden 1 +) +xt "7000,133000,8900,134000" +st "D_A" +blo "7000,133800" +tm "WireNameMgr" +) +) +on &110 +) +*239 (Wire +uid 1841,0 +shape (OrthoPolyLine +uid 1842,0 +va (VaSet +vasetType 3 +) +xt "21000,110000,51250,110000" +pts [ +"51250,110000" +"21000,110000" +] +) +start &31 +end &111 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1845,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1846,0 +va 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(VaSet +vasetType 3 +) +xt "21000,111000,51250,111000" +pts [ +"51250,111000" +"21000,111000" +] +) +start &36 +end &64 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2413,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2414,0 +va (VaSet +isHidden 1 +) +xt "22000,110000,26200,111000" +st "RSRLOAD" +blo "22000,110800" +tm "WireNameMgr" +) +) +on &63 +) +*245 (Wire +uid 2423,0 +shape (OrthoPolyLine +uid 2424,0 +va (VaSet +vasetType 3 +) +xt "32000,113000,51250,113000" +pts [ +"51250,113000" +"32000,113000" +] +) +start &37 +end &93 +sat 32 +eat 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2427,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2428,0 +va (VaSet +isHidden 1 +) +xt "66250,109000,69250,110000" +st "SRCLK" +blo "66250,109800" +tm "WireNameMgr" +) +) +on &65 +) +*246 (Wire +uid 3009,0 +shape (OrthoPolyLine +uid 3010,0 +va (VaSet +vasetType 3 +) +xt "80750,98000,111000,98000" +pts [ +"80750,98000" +"111000,98000" +] +) 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"ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3024,0 +va (VaSet +) +xt "92000,88000,98500,89000" +st "sensor_cs : (3:0)" +blo "92000,88800" +tm "WireNameMgr" +) +) +on &66 +) +*249 (Wire +uid 3027,0 +shape (OrthoPolyLine +uid 3028,0 +va (VaSet +vasetType 3 +) +xt "94000,87000,111000,87000" +pts [ +"94000,87000" +"111000,87000" +] +) +start &211 +end &113 +ss 0 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3031,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3032,0 +va (VaSet +isHidden 1 +) +xt "95000,86000,98600,87000" +st "DAC_CS" +blo "95000,86800" +tm "WireNameMgr" +) +) +on &67 +) +*250 (Wire +uid 3218,0 +shape (OrthoPolyLine +uid 3219,0 +va (VaSet +vasetType 3 +) +xt "11000,77000,13000,77000" +pts [ +"11000,77000" +"13000,77000" +] +) +start &47 +end &176 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3220,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3221,0 +va (VaSet +isHidden 1 +) +xt "22000,76000,24100,77000" +st "TRG" +blo "22000,76800" +tm "WireNameMgr" +) +) +on &70 +) +*251 (Wire +uid 3260,0 +shape (OrthoPolyLine +uid 3261,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "21000,70000,24000,70000" +pts [ +"21000,70000" +"24000,70000" +] +) +start &68 +end &71 +sat 32 +eat 2 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3264,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3265,0 +va (VaSet +isHidden 1 +) +xt "23000,69000,25800,70000" +st "A_CLK" +blo "23000,69800" +tm "WireNameMgr" +) +) +on &75 +) +*252 (Wire +uid 3270,0 +shape (OrthoPolyLine +uid 3271,0 +va (VaSet +vasetType 3 +) +xt "32000,70000,51250,70000" +pts [ +"51250,70000" +"32000,70000" +] +) +start &25 +end &71 +sat 32 +eat 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 3274,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3275,0 +va (VaSet +) +xt "46000,69000,50500,70000" +st "CLK_25_PS" +blo "46000,69800" +tm "WireNameMgr" +) +) +on &76 +) +*253 (Wire +uid 3318,0 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"21000,97000,24000,97000" +pts [ +"21000,97000" +"24000,97000" +] +) +start &87 +end &81 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3364,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3365,0 +va (VaSet +isHidden 1 +) +xt "23000,96000,25300,97000" +st "A2_D" +blo "23000,96800" +tm "WireNameMgr" +) +) +on &91 +) +*256 (Wire +uid 3368,0 +shape (OrthoPolyLine +uid 3369,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "21000,98000,24000,98000" +pts [ +"21000,98000" +"24000,98000" +] +) +start &88 +end &81 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3372,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3373,0 +va (VaSet +isHidden 1 +) +xt "23000,97000,25300,98000" +st "A3_D" +blo "23000,97800" +tm "WireNameMgr" +) +) +on &92 +) +*257 (Wire +uid 3430,0 +shape (OrthoPolyLine +uid 3431,0 +va (VaSet +vasetType 3 +) +xt "21000,113000,24000,113000" +pts [ +"21000,113000" +"24000,113000" +] +) +start &161 +end &93 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"STSignalDisplayStrategy" +f (Text +uid 3451,0 +va (VaSet +isHidden 1 +) +xt "23000,114000,27400,115000" +st "D2_SRCLK" +blo "23000,114800" +tm "WireNameMgr" +) +) +on &99 +) +*260 (Wire +uid 3454,0 +shape (OrthoPolyLine +uid 3455,0 +va (VaSet +vasetType 3 +) +xt "21000,116000,24000,116000" +pts [ +"21000,116000" +"24000,116000" +] +) +start &164 +end &93 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3458,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3459,0 +va (VaSet +isHidden 1 +) +xt "23000,115000,27400,116000" +st "D3_SRCLK" +blo "23000,115800" +tm "WireNameMgr" +) +) +on &100 +) +*261 (Wire +uid 3574,0 +shape (OrthoPolyLine +uid 3575,0 +va (VaSet +vasetType 3 +) +xt "108000,89000,111000,89000" +pts [ +"111000,89000" +"108000,89000" +] +) +start &118 +end &114 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3578,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3579,0 +va (VaSet +isHidden 1 +) +xt "108000,88000,110800,89000" +st "T0_CS" +blo "108000,88800" +tm "WireNameMgr" +) +) +on &122 +) +*262 (Wire +uid 3582,0 +shape (OrthoPolyLine +uid 3583,0 +va (VaSet +vasetType 3 +) +xt "108000,90000,111000,90000" +pts [ +"111000,90000" +"108000,90000" +] +) +start &119 +end &114 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3586,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3587,0 +va (VaSet +isHidden 1 +) +xt "108000,89000,110800,90000" +st "T1_CS" +blo "108000,89800" +tm "WireNameMgr" +) +) +on &123 +) +*263 (Wire +uid 3590,0 +shape (OrthoPolyLine +uid 3591,0 +va (VaSet +vasetType 3 +) +xt "108000,91000,111000,91000" +pts [ +"111000,91000" +"108000,91000" +] +) +start &120 +end &114 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3594,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3595,0 +va (VaSet +isHidden 1 +) +xt "108000,90000,110800,91000" +st "T2_CS" +blo "108000,90800" +tm "WireNameMgr" +) +) +on &124 +) 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"108000,103000,111000,103000" +pts [ +"111000,103000" +"108000,103000" +] +) +start &143 +end &139 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3782,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3783,0 +va (VaSet +isHidden 1 +) +xt "108000,102000,111000,103000" +st "TRG_V" +blo "108000,102800" +tm "WireNameMgr" +) +) +on &152 +) +*267 (Wire +uid 3786,0 +shape (OrthoPolyLine +uid 3787,0 +va (VaSet +vasetType 3 +) +xt "108000,104000,111000,104000" +pts [ +"111000,104000" +"108000,104000" +] +) +start &144 +end &139 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3790,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3791,0 +va (VaSet +isHidden 1 +) +xt "108000,103000,113600,104000" +st "RS485_C_RE" +blo "108000,103800" +tm "WireNameMgr" +) +) +on &153 +) +*268 (Wire +uid 3794,0 +shape (OrthoPolyLine +uid 3795,0 +va (VaSet +vasetType 3 +) +xt "108000,105000,111000,105000" +pts [ +"111000,105000" +"108000,105000" +] +) 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(LogicalDM +emptyRow *464 (LEmptyRow +) +uid 83,0 +optionalChildren [ +*465 (RefLabelRowHdr +) +*466 (TitleRowHdr +) +*467 (FilterRowHdr +) +*468 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*469 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*470 (GroupColHdr +tm "GroupColHdrMgr" +) +*471 (NameColHdr +tm "GenericNameColHdrMgr" +) +*472 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*473 (InitColHdr +tm "GenericValueColHdrMgr" +) +*474 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*475 (EolColHdr +tm "GenericEolColHdrMgr" +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 95,0 +optionalChildren [ +*476 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *477 (MRCItem +litem &464 +pos 0 +dimension 20 +) +uid 97,0 +optionalChildren [ +*478 (MRCItem +litem &465 +pos 0 +dimension 20 +uid 98,0 +) +*479 (MRCItem +litem &466 +pos 1 +dimension 23 +uid 99,0 +) +*480 (MRCItem +litem &467 +pos 2 +hidden 1 +dimension 20 +uid 100,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 101,0 +optionalChildren [ +*481 (MRCItem +litem &468 +pos 0 +dimension 20 +uid 102,0 +) +*482 (MRCItem +litem &470 +pos 1 +dimension 50 +uid 103,0 +) +*483 (MRCItem +litem &471 +pos 2 +dimension 100 +uid 104,0 +) +*484 (MRCItem +litem &472 +pos 3 +dimension 100 +uid 105,0 +) +*485 (MRCItem +litem &473 +pos 4 +dimension 50 +uid 106,0 +) +*486 (MRCItem +litem &474 +pos 5 +dimension 50 +uid 107,0 +) +*487 (MRCItem +litem &475 +pos 6 +dimension 80 +uid 108,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 96,0 +vaOverrides [ +] +) +] +) +uid 82,0 +type 1 +) +activeModelName "BlockDiag" +) Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.info/Synthesis/Constraints/FAD_Testboard.ctr =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.info/Synthesis/Constraints/FAD_Testboard.ctr (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.info/Synthesis/Constraints/FAD_Testboard.ctr (revision 9841) @@ -0,0 +1,7 @@ +# set_vendor xilinx +# set_family spartan3adsp +# set_device 3sd3400a +# set_package fg676 +# set_speed -4 + + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.info/Synthesis/Constraints/FAD_Testboard.sdc =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.info/Synthesis/Constraints/FAD_Testboard.sdc (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.info/Synthesis/Constraints/FAD_Testboard.sdc (revision 9841) @@ -0,0 +1,7 @@ +# set_vendor xilinx +# set_family spartan3adsp +# set_device 3sd3400a +# set_package fg676 +# set_speed -4 + + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb (revision 9841) @@ -0,0 +1,4521 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +] +libraryRefs [ +"ieee" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 67,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 53,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "RSRLOAD" +t "std_logic" +o 35 +suid 11,0 +i "'0'" +) +) +uid 690,0 +) +*15 (LogPort +port (LogicalPort +decl (Decl +n "X_50M" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 14 +suid 15,0 +) +) +uid 1111,0 +) +*16 (LogPort +port (LogicalPort +decl (Decl +n "TRG" +t "STD_LOGIC" +o 12 +suid 16,0 +) +) +uid 1113,0 +) +*17 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "A_CLK" +t "std_logic_vector" +b "(3 downto 0)" +o 16 +suid 17,0 +) +) +uid 1115,0 +) +*18 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "OE_ADC" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 30 +suid 18,0 +) +) +uid 1155,0 +) +*19 (LogPort +port (LogicalPort +decl (Decl +n "A_OTR" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 5 +suid 19,0 +) +) +uid 1157,0 +) +*20 (LogPort +port (LogicalPort +decl (Decl +n "A0_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 1 +suid 20,0 +) +) +uid 1159,0 +) +*21 (LogPort +port (LogicalPort +decl (Decl +n "A1_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 2 +suid 21,0 +) +) +uid 1161,0 +) +*22 (LogPort +port (LogicalPort +decl (Decl +n "A2_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 3 +suid 22,0 +) +) +uid 1163,0 +) +*23 (LogPort +port (LogicalPort +decl (Decl +n "A3_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 4 +suid 23,0 +) +) +uid 1165,0 +) +*24 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "D0_SRCLK" +t "STD_LOGIC" +o 17 +suid 24,0 +) +) +uid 1220,0 +) +*25 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "D1_SRCLK" +t "STD_LOGIC" +o 18 +suid 25,0 +) +) +uid 1222,0 +) +*26 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "D2_SRCLK" +t "STD_LOGIC" +o 19 +suid 26,0 +) +) +uid 1224,0 +) +*27 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "D3_SRCLK" +t "STD_LOGIC" +o 20 +suid 27,0 +) +) +uid 1226,0 +) +*28 (LogPort +port (LogicalPort +decl (Decl +n "D0_SROUT" +t "std_logic" +o 6 +suid 28,0 +) +) +uid 1271,0 +) +*29 (LogPort +port (LogicalPort +decl (Decl +n "D1_SROUT" +t "std_logic" +o 7 +suid 29,0 +) +) +uid 1273,0 +) +*30 (LogPort +port (LogicalPort +decl (Decl +n "D2_SROUT" +t "std_logic" +o 8 +suid 30,0 +) +) +uid 1275,0 +) +*31 (LogPort +port (LogicalPort +decl (Decl +n "D3_SROUT" +t "std_logic" +o 9 +suid 31,0 +) +) +uid 1277,0 +) +*32 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "D_A" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 24 +suid 32,0 +i "(others => '0')" +) +) +uid 1279,0 +) +*33 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "DWRITE" +t "std_logic" +o 23 +suid 33,0 +i "'0'" +) +) +uid 1281,0 +) +*34 (LogPort +port (LogicalPort +m 1 +decl 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"0,65535,0" +) +xt "14250,21625,15000,22375" +) +tg (CPTG +uid 1188,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1189,0 +va (VaSet +) +xt "16000,21500,21300,22500" +st "A2_D : (11:0)" +blo "16000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1190,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3600,72000,4400" +st "A2_D : IN std_logic_vector (11 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "A2_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 3 +suid 22,0 +) +) +) +*159 (CptPort +uid 1191,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1192,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,23625,15000,24375" +) +tg (CPTG +uid 1193,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1194,0 +va (VaSet +) +xt "16000,23500,21300,24500" +st "A3_D : (11:0)" +blo "16000,24300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1195,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,4400,72000,5200" +st "A3_D : IN std_logic_vector (11 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "A3_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 4 +suid 23,0 +) +) +) +*160 (CptPort +uid 1227,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1777,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,83625,33750,84375" +) +tg (CPTG +uid 1229,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1230,0 +va (VaSet +) +xt "27600,83500,32000,84500" +st "D0_SRCLK" +ju 2 +blo "32000,84300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1231,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,14800,61500,15600" +st "D0_SRCLK : OUT STD_LOGIC ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "D0_SRCLK" +t "STD_LOGIC" +o 17 +suid 24,0 +) +) +) +*161 (CptPort +uid 1232,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1778,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,85625,33750,86375" +) +tg (CPTG +uid 1234,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1235,0 +va (VaSet +) +xt "27600,85500,32000,86500" +st "D1_SRCLK" +ju 2 +blo "32000,86300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1236,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,15600,61500,16400" +st "D1_SRCLK : OUT STD_LOGIC ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "D1_SRCLK" +t "STD_LOGIC" +o 18 +suid 25,0 +) +) +) +*162 (CptPort +uid 1237,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1779,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,87625,33750,88375" +) +tg (CPTG +uid 1239,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1240,0 +va (VaSet +) +xt "27600,87500,32000,88500" +st "D2_SRCLK" +ju 2 +blo "32000,88300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1241,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,16400,61500,17200" +st "D2_SRCLK : OUT STD_LOGIC ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "D2_SRCLK" +t "STD_LOGIC" +o 19 +suid 26,0 +) +) +) +*163 (CptPort +uid 1242,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1780,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,89625,33750,90375" +) +tg (CPTG +uid 1244,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1245,0 +va (VaSet +) +xt "27600,89500,32000,90500" +st "D3_SRCLK" +ju 2 +blo "32000,90300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1246,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,17200,61500,18000" +st "D3_SRCLK : OUT STD_LOGIC ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "D3_SRCLK" +t "STD_LOGIC" +o 20 +suid 27,0 +) +) +) +*164 (CptPort +uid 1282,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1283,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,33625,15000,34375" +) +tg (CPTG +uid 1284,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1285,0 +va (VaSet +) +xt "16000,33500,20600,34500" +st "D0_SROUT" +blo "16000,34300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1286,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6000,61500,6800" +st "D0_SROUT : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "D0_SROUT" +t "std_logic" +o 6 +suid 28,0 +) +) +) +*165 (CptPort +uid 1287,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1288,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,35625,15000,36375" +) +tg (CPTG +uid 1289,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1290,0 +va (VaSet +) +xt "16000,35500,20600,36500" +st "D1_SROUT" +blo "16000,36300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1291,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6800,61500,7600" +st "D1_SROUT : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "D1_SROUT" +t "std_logic" +o 7 +suid 29,0 +) +) +) +*166 (CptPort +uid 1292,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1293,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,37625,15000,38375" +) +tg (CPTG +uid 1294,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1295,0 +va (VaSet +) +xt "16000,37500,20600,38500" +st "D2_SROUT" +blo "16000,38300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1296,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,7600,61500,8400" +st "D2_SROUT : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "D2_SROUT" +t "std_logic" +o 8 +suid 30,0 +) +) +) +*167 (CptPort +uid 1297,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1298,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,39625,15000,40375" +) +tg (CPTG +uid 1299,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1300,0 +va (VaSet +) +xt "16000,39500,20600,40500" +st "D3_SROUT" +blo "16000,40300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1301,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,8400,61500,9200" +st "D3_SROUT : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "D3_SROUT" +t "std_logic" +o 9 +suid 31,0 +) +) +) +*168 (CptPort +uid 1302,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1303,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,29625,33750,30375" +) +tg (CPTG +uid 1304,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1305,0 +va (VaSet +) +xt "27500,29500,32000,30500" +st "D_A : (3:0)" +ju 2 +blo "32000,30300" +tm "CptPortNameMgr" +) +t (Text +uid 1306,0 +va (VaSet +) +xt "26300,30500,32000,31500" +st "(others => '0')" +ju 2 +blo "32000,31300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 1307,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,20400,82000,21200" +st "D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "D_A" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 24 +suid 32,0 +i "(others => '0')" +) +) +) +*169 (CptPort +uid 1308,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1309,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,31625,33750,32375" +) +tg (CPTG +uid 1310,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1311,0 +va (VaSet +) +xt "28500,31500,32000,32500" +st "DWRITE" +ju 2 +blo "32000,32300" +tm "CptPortNameMgr" +) +t (Text +uid 1312,0 +va (VaSet +) +xt "30800,32500,32000,33500" +st "'0'" +ju 2 +blo "32000,33300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 1313,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,19600,76000,20400" +st "DWRITE : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "DWRITE" +t "std_logic" +o 23 +suid 33,0 +i "'0'" +) +) +) +*170 (CptPort +uid 1363,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1364,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,33625,33750,34375" +) +tg (CPTG +uid 1365,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1366,0 +va (VaSet +) +xt "28400,33500,32000,34500" +st "DAC_CS" +ju 2 +blo "32000,34300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1367,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,18000,61500,18800" +st "DAC_CS : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "DAC_CS" +t "std_logic" +o 21 +suid 34,0 +) +) +) +*171 (CptPort +uid 1368,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1369,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,35625,33750,36375" +) +tg (CPTG +uid 1370,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1371,0 +va (VaSet +) +xt "29200,35500,32000,36500" +st "T0_CS" +ju 2 +blo "32000,36300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1372,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,31600,61500,32400" +st "T0_CS : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "T0_CS" +t "std_logic" +o 38 +suid 35,0 +) +) +) +*172 (CptPort +uid 1373,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1374,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,37625,33750,38375" +) +tg (CPTG +uid 1375,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1376,0 +va (VaSet +) +xt "29200,37500,32000,38500" +st "T1_CS" +ju 2 +blo "32000,38300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1377,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,32400,61500,33200" +st "T1_CS : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "T1_CS" +t "std_logic" +o 39 +suid 36,0 +) +) +) +*173 (CptPort +uid 1378,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1379,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,39625,33750,40375" +) +tg (CPTG +uid 1380,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1381,0 +va (VaSet +) +xt "29200,39500,32000,40500" +st "T2_CS" +ju 2 +blo "32000,40300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1382,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,33200,61500,34000" +st "T2_CS : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "T2_CS" +t "std_logic" +o 40 +suid 37,0 +) +) +) +*174 (CptPort +uid 1383,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1384,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,41625,33750,42375" +) +tg (CPTG +uid 1385,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1386,0 +va (VaSet +) +xt "29200,41500,32000,42500" +st "T3_CS" +ju 2 +blo "32000,42300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1387,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,34000,61500,34800" +st "T3_CS : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "T3_CS" +t "std_logic" +o 41 +suid 38,0 +) +) +) +*175 (CptPort +uid 1388,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1389,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,43625,33750,44375" +) +tg (CPTG +uid 1390,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1391,0 +va (VaSet +) +xt "29200,43500,32000,44500" +st "S_CLK" +ju 2 +blo "32000,44300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1392,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,30800,61500,31600" +st "S_CLK : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "S_CLK" +t "std_logic" +o 37 +suid 39,0 +) +) +) +*176 (CptPort +uid 1393,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1394,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,45625,33750,46375" +) +tg (CPTG +uid 1395,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1396,0 +va (VaSet +) +xt "27400,45500,32000,46500" +st "W_A : (9:0)" +ju 2 +blo "32000,46300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1397,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,35600,71500,36400" +st "W_A : OUT std_logic_vector (9 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "W_A" +t "std_logic_vector" +b "(9 DOWNTO 0)" +o 43 +suid 40,0 +) +) +) +*177 (CptPort +uid 1398,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 1399,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,47625,33750,48375" +) +tg (CPTG +uid 1400,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1401,0 +va (VaSet +) +xt "26900,47500,32000,48500" +st "W_D : (15:0)" +ju 2 +blo "32000,48300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1402,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,40400,71000,41200" +st "W_D : INOUT std_logic_vector (15 DOWNTO 0) +" +) +thePort (LogicalPort +m 2 +decl (Decl +n "W_D" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 49 +suid 41,0 +) +) +) +*178 (CptPort +uid 1403,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1404,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,49625,33750,50375" +) +tg (CPTG +uid 1405,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1406,0 +va (VaSet +) +xt "28900,49500,32000,50500" +st "W_RES" +ju 2 +blo "32000,50300" +tm "CptPortNameMgr" +) +t (Text +uid 1407,0 +va (VaSet +) +xt "30800,50500,32000,51500" +st "'1'" +ju 2 +blo "32000,51300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 1408,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,38000,76000,38800" +st "W_RES : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "W_RES" +t "std_logic" +o 46 +suid 42,0 +i "'1'" +) +) +) +*179 (CptPort +uid 1409,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1410,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,51625,33750,52375" +) +tg (CPTG +uid 1411,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1412,0 +va (VaSet +) +xt "29300,51500,32000,52500" +st "W_RD" +ju 2 +blo "32000,52300" +tm "CptPortNameMgr" +) +t (Text +uid 1413,0 +va (VaSet +) +xt "30800,52500,32000,53500" +st "'1'" +ju 2 +blo "32000,53300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 1414,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,37200,76000,38000" +st "W_RD : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "W_RD" +t "std_logic" +o 45 +suid 43,0 +i "'1'" +) +) +) +*180 (CptPort +uid 1415,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1416,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,53625,33750,54375" +) +tg (CPTG +uid 1417,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1418,0 +va (VaSet +) +xt "29200,53500,32000,54500" +st "W_WR" +ju 2 +blo "32000,54300" +tm "CptPortNameMgr" +) +t (Text +uid 1419,0 +va (VaSet +) +xt "30800,54500,32000,55500" +st "'1'" +ju 2 +blo "32000,55300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 1420,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,38800,76000,39600" +st "W_WR : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "W_WR" +t "std_logic" +o 47 +suid 44,0 +i "'1'" +) +) +) +*181 (CptPort +uid 1421,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1422,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,41625,15000,42375" +) +tg (CPTG +uid 1423,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1424,0 +va (VaSet +) +xt "16000,41500,18800,42500" +st "W_INT" +blo "16000,42300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1425,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,11600,61500,12400" +st "W_INT : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "W_INT" +t "std_logic" +o 13 +suid 45,0 +) +) +) +*182 (CptPort +uid 1426,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1427,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,55625,33750,56375" +) +tg (CPTG +uid 1428,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1429,0 +va (VaSet +) +xt "29400,55500,32000,56500" +st "W_CS" +ju 2 +blo "32000,56300" +tm "CptPortNameMgr" +) +t (Text +uid 1430,0 +va (VaSet +) +xt "30800,56500,32000,57500" +st "'1'" +ju 2 +blo "32000,57300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 1431,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,36400,76000,37200" +st "W_CS : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "W_CS" +t "std_logic" +o 44 +suid 46,0 +i "'1'" +) +) +) +*183 (CptPort +uid 1620,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1621,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,57625,33750,58375" +) +tg (CPTG +uid 1622,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1623,0 +va (VaSet +) +xt "29600,57500,32000,58500" +st "MOSI" +ju 2 +blo "32000,58300" +tm "CptPortNameMgr" +) +t (Text +uid 1624,0 +va (VaSet +) +xt "30800,58500,32000,59500" +st "'0'" +ju 2 +blo "32000,59300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 1625,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,24400,76000,25200" +st "MOSI : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "MOSI" +t "std_logic" +o 29 +suid 47,0 +i "'0'" +) +) +) +*184 (CptPort +uid 1626,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 1627,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,59625,33750,60375" +) +tg (CPTG +uid 1628,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1629,0 +va (VaSet +) +xt "29600,59500,32000,60500" +st "MISO" +ju 2 +blo "32000,60300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1630,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,39600,61500,40400" +st "MISO : INOUT std_logic ; +" +) +thePort (LogicalPort +m 2 +decl (Decl +n "MISO" +t "std_logic" +preAdd 0 +posAdd 0 +o 48 +suid 48,0 +) +) +) +*185 (CptPort +uid 1676,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1677,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,61625,33750,62375" +) +tg (CPTG +uid 1678,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1679,0 +va (VaSet +) +xt "29000,61500,32000,62500" +st "TRG_V" +ju 2 +blo "32000,62300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1680,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,34800,61500,35600" +st "TRG_V : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "TRG_V" +t "std_logic" +o 42 +suid 49,0 +) +) +) +*186 (CptPort +uid 1681,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1682,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,63625,33750,64375" +) +tg (CPTG +uid 1683,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1684,0 +va (VaSet +) +xt "26400,63500,32000,64500" +st "RS485_C_RE" +ju 2 +blo "32000,64300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1685,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,26800,61500,27600" +st "RS485_C_RE : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "RS485_C_RE" +t "std_logic" +o 32 +suid 50,0 +) +) +) +*187 (CptPort +uid 1686,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1687,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,65625,33750,66375" +) +tg (CPTG +uid 1688,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1689,0 +va (VaSet +) +xt "26400,65500,32000,66500" +st "RS485_C_DE" +ju 2 +blo "32000,66300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1690,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,26000,61500,26800" +st "RS485_C_DE : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "RS485_C_DE" +t "std_logic" +o 31 +suid 51,0 +) +) +) +*188 (CptPort +uid 1691,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1692,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,67625,33750,68375" +) +tg (CPTG +uid 1693,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1694,0 +va (VaSet +) +xt "26500,67500,32000,68500" +st "RS485_E_RE" +ju 2 +blo "32000,68300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1695,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,28400,61500,29200" +st "RS485_E_RE : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "RS485_E_RE" +t "std_logic" +o 34 +suid 52,0 +) +) +) +*189 (CptPort +uid 1696,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1697,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,69625,33750,70375" +) +tg (CPTG +uid 1698,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1699,0 +va (VaSet +) +xt "26500,69500,32000,70500" +st "RS485_E_DE" +ju 2 +blo "32000,70300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1700,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,27600,61500,28400" +st "RS485_E_DE : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "RS485_E_DE" +t "std_logic" +o 33 +suid 53,0 +) +) +) +*190 (CptPort +uid 1701,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1702,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,71625,33750,72375" +) +tg (CPTG +uid 1703,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1704,0 +va (VaSet +) +xt "28000,71500,32000,72500" +st "DENABLE" +ju 2 +blo "32000,72300" +tm "CptPortNameMgr" +) +t (Text +uid 1919,0 +va (VaSet +) +xt "30800,72500,32000,73500" +st "'0'" +ju 2 +blo "32000,73300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 1705,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,18800,76000,19600" +st "DENABLE : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "DENABLE" +t "std_logic" +o 22 +suid 54,0 +i "'0'" +) +) +) +*191 (CptPort +uid 1706,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1707,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,73625,33750,74375" +) +tg (CPTG +uid 1708,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1709,0 +va (VaSet +) +xt "29700,73500,32000,74500" +st "SRIN" +ju 2 +blo "32000,74300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1710,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,30000,61500,30800" +st "SRIN : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "SRIN" +t "std_logic" +o 36 +suid 55,0 +) +) +) +*192 (CptPort +uid 1711,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1712,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,75625,33750,76375" +) +tg (CPTG +uid 1713,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1714,0 +va (VaSet +) +xt "29100,75500,32000,76500" +st "EE_CS" +ju 2 +blo "32000,76300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1715,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,22800,61500,23600" +st "EE_CS : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "EE_CS" +t "std_logic" +o 27 +suid 56,0 +) +) +) +*193 (CptPort +uid 2068,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2069,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,91625,33750,92375" +) +tg (CPTG +uid 2070,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2071,0 +va (VaSet +) +xt "27500,91500,32000,92500" +st "D_T : (7:0)" +ju 2 +blo "32000,92300" +tm "CptPortNameMgr" +) +t (Text +uid 2072,0 +va (VaSet +) +xt "25100,92500,32000,93500" +st "(OTHERS => '0')" +ju 2 +blo "32000,93300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 2073,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,21200,82000,22000" +st "D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "D_T" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 25 +suid 61,0 +i "(OTHERS => '0')" +) +) +) +*194 (CptPort +uid 2375,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2376,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,93625,33750,94375" +) +tg (CPTG +uid 2377,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2378,0 +va (VaSet +) +xt "27500,93500,32000,94500" +st "LED : (2:0)" +ju 2 +blo "32000,94300" +tm "CptPortNameMgr" +) +t (Text +uid 2379,0 +va (VaSet +) +xt "26300,94500,32000,95500" +st "(others => '1')" +ju 2 +blo "32000,95300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 2380,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,23600,82000,24400" +st "LED : OUT std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "LED" +t "std_logic_vector" +b "( 2 DOWNTO 0 )" +o 28 +suid 62,0 +i "(others => '1')" +) +) +) +*195 (CptPort +uid 2567,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2568,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,43625,15000,44375" +) +tg (CPTG +uid 2569,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2570,0 +va (VaSet +) +xt "16000,43500,20500,44500" +st "TEST_TRG" +blo "16000,44300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2571,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10000,61500,10800" +st "TEST_TRG : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "TEST_TRG" +t "std_logic" +o 11 +suid 63,0 +) +) +) +*196 (CptPort +uid 2919,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2920,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,45625,15000,46375" +) +tg (CPTG +uid 2921,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2922,0 +va (VaSet +) +xt "16000,45500,22800,46500" +st "D_PLLLCK : (3:0)" +blo "16000,46300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2923,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,9200,71500,10000" +st "D_PLLLCK : IN std_logic_vector (3 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "D_PLLLCK" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 10 +suid 64,0 +) +) +) +*197 (CptPort +uid 2949,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2950,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,95625,33750,96375" +) +tg (CPTG +uid 2951,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2952,0 +va (VaSet +) +xt "27100,95500,32000,96500" +st "D_T2 : (3:0)" +ju 2 +blo "32000,96300" +tm "CptPortNameMgr" +) +t (Text +uid 2953,0 +va (VaSet +) +xt "26300,96500,32000,97500" +st "(others => '0')" +ju 2 +blo "32000,97300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 2954,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,22000,82000,22800" +st "D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "D_T2" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 26 +suid 65,0 +i "(others => '0')" +) +) +) +*198 (CptPort +uid 3026,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3027,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,97625,33750,98375" +) +tg (CPTG +uid 3028,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3029,0 +va (VaSet +) +xt "27200,97500,32000,98500" +st "A1_T : (7:0)" +ju 2 +blo "32000,98300" +tm "CptPortNameMgr" +) +t (Text +uid 3123,0 +va (VaSet +) +xt "25100,98500,32000,99500" +st "(OTHERS => '0')" +ju 2 +blo "32000,99300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 3030,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,13200,82000,14000" +st "A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "A1_T" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 15 +suid 66,0 +i "(OTHERS => '0')" +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,101000" +) +oxt "15000,6000,33000,26000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,28400,16000" +st "FACT_FAD_lib" +blo "22200,15800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,26900,17000" +st "FAD_Board" +blo "22200,16800" +) +) +gi *199 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +*200 (Grouping +uid 16,0 +optionalChildren [ +*201 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48000,45500,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*202 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,44000,56200,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*203 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,46000,46200,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*204 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,46000,34300,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*205 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,45200,62400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*206 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,44000,61700,45000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*207 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "39700,44000,45300,46000" +st " +TU Dortmund +Physik / EE +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*208 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,47000,34300,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 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=================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd (revision 9841) @@ -0,0 +1,18171 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "IEEE" +unitName "STD_LOGIC_ARITH" +) +(DmPackageRef +library "ieee" +unitName "STD_LOGIC_UNSIGNED" +) +(DmPackageRef +library "fact_fad_lib" +unitName "fad_definitions" +) +(DmPackageRef +library "UNISIM" +unitName "VComponents" +) +(DmPackageRef +library "IEEE" +unitName "NUMERIC_STD" +) +(DmPackageRef +library "IEEE" +unitName "std_logic_signed" +) +] +instances [ +(Instance +name "I_main_data_generator" +duLibraryName "FACT_FAD_lib" +duName "data_generator" +elements [ +(GiElement +name "RAM_ADDR_WIDTH" +type "integer" +value "RAMADDRWIDTH64b" +) +] +mwi 0 +uid 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"CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5177,0 +va (VaSet +) +xt "32500,82500,39000,83500" +st "config_ready_cm" +ju 2 +blo "39000,83300" +) +) +thePort (LogicalPort +decl (Decl +n "config_ready_cm" +t "std_logic" +o 12 +suid 39,0 +) +) +) +*47 (CptPort +uid 5178,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5179,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40000,80625,40750,81375" +) +tg (CPTG +uid 5180,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5181,0 +va (VaSet +) +xt "32800,80500,39000,81500" +st "config_start_cm" +ju 2 +blo "39000,81300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_start_cm" +t "std_logic" +o 9 +suid 40,0 +i "'0'" +) +) +) +*48 (CptPort +uid 5271,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5272,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40000,52625,40750,53375" +) +tg (CPTG +uid 5273,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f 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"CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*61 (Text +uid 1402,0 +va (VaSet +font "Arial,8,1" +) +xt "19300,91000,25500,92000" +st "FACT_FAD_lib" +blo "19300,91800" +tm "BdLibraryNameMgr" +) +*62 (Text +uid 1403,0 +va (VaSet +font "Arial,8,1" +) +xt "19300,92000,25700,93000" +st "data_generator" +blo "19300,92800" +tm "CptNameMgr" +) +*63 (Text +uid 1404,0 +va (VaSet +font "Arial,8,1" +) +xt "19300,93000,28900,94000" +st "I_main_data_generator" +blo "19300,93800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1405,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1406,0 +text (MLText +uid 1407,0 +va (VaSet +font "Courier New,8,0" +) +xt "19000,46200,45500,47000" +st "RAM_ADDR_WIDTH = RAMADDRWIDTH64b ( integer ) " +) +header "" +) +elements [ +(GiElement +name "RAM_ADDR_WIDTH" +type "integer" +value "RAMADDRWIDTH64b" +) +] +) +viewicon (ZoomableIcon +uid 1408,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "19250,89250,20750,90750" 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"145800,53500,147000,54500" +st "wr" +ju 2 +blo "147000,54300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "wr" +t "std_logic" +preAdd 0 +posAdd 0 +o 6 +suid 6,0 +i "'1'" +) +) +) +*74 (CptPort +uid 1570,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1571,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,54625,148750,55375" +) +tg (CPTG +uid 1572,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1573,0 +va (VaSet +) +xt "145900,54500,147000,55500" +st "rd" +ju 2 +blo "147000,55300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "rd" +t "std_logic" +preAdd 0 +posAdd 0 +o 8 +suid 8,0 +i "'1'" +) +) +) +*75 (CptPort +uid 1574,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1575,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,55625,148750,56375" +) +tg (CPTG +uid 1576,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1577,0 +va (VaSet +) +xt "145800,55500,147000,56500" +st "int" +ju 2 +blo "147000,56300" +) +) +thePort (LogicalPort +decl (Decl +n "int" +t "std_logic" +preAdd 0 +posAdd 0 +o 9 +suid 9,0 +) +) +) +*76 (CptPort +uid 1578,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1579,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,69625,127000,70375" +) +tg (CPTG +uid 1580,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1581,0 +va (VaSet +) +xt "128000,69500,135900,70500" +st "write_length : (16:0)" +blo "128000,70300" +) +) +thePort (LogicalPort +decl (Decl +n "write_length" +t "std_logic_vector" +b "(16 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 10 +suid 10,0 +) +) +) +*77 (CptPort +uid 1582,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1583,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,70625,127000,71375" +) +tg (CPTG +uid 1584,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1585,0 +va (VaSet +) +xt "128000,70500,144300,71500" +st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)" +blo "128000,71300" +) +) +thePort (LogicalPort +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 11 +suid 11,0 +) +) +) +*78 (CptPort +uid 1586,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1587,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,54625,127000,55375" +) +tg (CPTG +uid 1588,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1589,0 +va (VaSet +) +xt "128000,54500,134500,55500" +st "ram_data : (15:0)" +blo "128000,55300" +) +) +thePort (LogicalPort +decl (Decl +n "ram_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 12 +suid 12,0 +) +) +) +*79 (CptPort +uid 1590,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1591,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,53625,127000,54375" +) +tg (CPTG +uid 1592,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1593,0 +va (VaSet +) +xt "128000,53500,142400,54500" +st "ram_addr : (RAM_ADDR_WIDTH-1:0)" +blo "128000,54300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "ram_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 13 +suid 13,0 +) +) +) +*80 (CptPort +uid 1594,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1595,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,68625,127000,69375" +) +tg (CPTG +uid 1596,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1597,0 +va (VaSet +) +xt "128000,68500,132100,69500" +st "data_valid" +blo "128000,69300" +) +) +thePort (LogicalPort +decl (Decl +n "data_valid" +t "std_logic" +preAdd 0 +posAdd 0 +o 14 +suid 14,0 +) +) +) +*81 (CptPort +uid 1598,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1599,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,67625,127000,68375" +) +tg (CPTG +uid 1600,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1601,0 +va (VaSet +) +xt "128000,67500,129900,68500" +st "busy" +blo "128000,68300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "busy" +t "std_logic" +preAdd 0 +posAdd 0 +o 16 +suid 15,0 +i "'1'" +) +) +) +*82 (CptPort +uid 2218,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2219,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,71625,127000,72375" +) +tg (CPTG +uid 2220,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2221,0 +va (VaSet +) +xt "128000,71500,135800,72500" +st "fifo_channels : (3:0)" +blo "128000,72300" +) +) +thePort (LogicalPort +decl (Decl +n "fifo_channels" +t "std_logic_vector" +b "(3 downto 0)" +o 19 +suid 20,0 +) +) +) +*83 (CptPort +uid 2222,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2223,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,72625,127000,73375" +) +tg (CPTG +uid 2224,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2225,0 +va (VaSet +) +xt "128000,72500,133700,73500" +st "write_end_flag" +blo "128000,73300" +) +) +thePort (LogicalPort +decl (Decl +n "write_end_flag" +t "std_logic" +o 18 +suid 18,0 +) +) +) +*84 (CptPort +uid 2226,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2227,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,73625,127000,74375" +) +tg (CPTG +uid 2228,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2229,0 +va (VaSet +) +xt "128000,73500,134800,74500" +st "write_header_flag" +blo "128000,74300" +) +) +thePort (LogicalPort +decl (Decl +n "write_header_flag" +t "std_logic" +o 17 +suid 19,0 +) +) +) +*85 (CptPort +uid 5216,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5217,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,70625,148750,71375" +) +tg (CPTG +uid 5218,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5219,0 +va (VaSet +) +xt "143000,70500,147000,71500" +st "led : (7:0)" +ju 2 +blo "147000,71300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 DOWNTO 0)" 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"OnEdgeStrategy" +shape (Triangle +uid 5937,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,60625,127000,61375" +) +tg (CPTG +uid 5938,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5939,0 +va (VaSet +) +xt "128000,60500,133600,61500" +st "config_started" +blo "128000,61300" +) +) +thePort (LogicalPort +decl (Decl +n "config_started" +t "std_logic" +o 22 +suid 27,0 +) +) +) +*91 (CptPort +uid 5940,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5941,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,81625,127000,82375" +) +tg (CPTG +uid 5942,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5943,0 +va (VaSet +) +xt "128000,81500,133300,82500" +st "config_wr_en" +blo "128000,82300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_wr_en" +t "std_logic" +o 25 +suid 28,0 +i "'0'" +) +) +) +*92 (CptPort +uid 5944,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5945,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,59625,127000,60375" +) +tg (CPTG +uid 5946,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5947,0 +va (VaSet +) +xt "128000,59500,132600,60500" +st "new_config" +blo "128000,60300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "new_config" +t "std_logic" +o 21 +suid 29,0 +i "'0'" +) +) +) +*93 (CptPort +uid 5970,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5971,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,82625,127000,83375" +) +tg (CPTG +uid 5972,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5973,0 +va (VaSet +) +xt "128000,82500,133200,83500" +st "config_rd_en" +blo "128000,83300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_rd_en" +t "std_logic" +o 26 +suid 30,0 +i "'0'" +) +) +) +*94 (CptPort +uid 6356,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6357,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,74625,148750,75375" +) +tg (CPTG +uid 6358,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6359,0 +va (VaSet +) +xt "144000,74500,147000,75500" +st "denable" +ju 2 +blo "147000,75300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "denable" +t "std_logic" +eolc "-- default domino wave off" +posAdd 0 +o 28 +suid 31,0 +i "'0'" +) +) +) +*95 (CptPort +uid 6446,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6447,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,75625,148750,76375" +) +tg (CPTG +uid 6448,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6449,0 +va (VaSet +) +xt "141600,75500,147000,76500" +st "dwrite_enable" +ju 2 +blo "147000,76300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "dwrite_enable" +t "std_logic" +eolc "-- default DWRITE low." +preAdd 0 +posAdd 0 +o 29 +suid 32,0 +i "'0'" +) +) +) +*96 (CptPort +uid 8406,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8407,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,74625,127000,75375" +) +tg (CPTG +uid 8408,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8409,0 +va (VaSet +) +xt "128000,74500,133600,75500" +st "data_valid_ack" +blo "128000,75300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "data_valid_ack" +t "std_logic" +o 15 +suid 34,0 +i "'0'" +) +) +) +*97 (CptPort +uid 8748,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8749,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,76625,148750,77375" +) +tg (CPTG +uid 8750,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8751,0 +va (VaSet +) +xt "142300,76500,147000,77500" +st "sclk_enable" +ju 2 +blo "147000,77300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sclk_enable" +t "std_logic" +eolc "-- default DWRITE HIGH." +posAdd 0 +o 30 +suid 35,0 +i "'1'" +) +) +) +] +shape (Rectangle +uid 1607,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "127000,51000,148000,87000" +) +oxt "43000,2000,56000,22000" +ttg (MlTextGroup +uid 1608,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*98 (Text +uid 1609,0 +va (VaSet +font "Arial,8,1" +) +xt "126700,87000,132900,88000" +st "FACT_FAD_lib" +blo "126700,87800" +tm "BdLibraryNameMgr" +) +*99 (Text +uid 1610,0 +va (VaSet +font "Arial,8,1" +) +xt "126700,88000,132400,89000" +st "w5300_modul" +blo "126700,88800" +tm "CptNameMgr" +) +*100 (Text +uid 1611,0 +va (VaSet +font "Arial,8,1" +) +xt "126700,89000,133400,90000" +st "I_main_ethernet" +blo "126700,89800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1612,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1613,0 +text (MLText +uid 1614,0 +va (VaSet +font "Courier New,8,0" +) +xt "127000,50200,154500,51000" +st "RAM_ADDR_WIDTH = RAMADDRWIDTH64b+2 ( integer ) " +) +header "" +) +elements [ +(GiElement +name "RAM_ADDR_WIDTH" +type "integer" +value "RAMADDRWIDTH64b+2" +) +] +) +viewicon (ZoomableIcon +uid 1615,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "127250,85250,128750,86750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*101 (Net +uid 1680,0 +decl (Decl +n "crate_id" +t "std_logic_vector" +b "(1 downto 0)" +o 9 +suid 30,0 +) +declText (MLText +uid 1681,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,24600,-56500,25400" +st "crate_id : std_logic_vector(1 downto 0) +" +) +) +*102 (SaComponent +uid 1768,0 +optionalChildren [ +*103 (CptPort +uid 1760,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1761,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-7000,63625,-6250,64375" +) +tg (CPTG +uid 1762,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1763,0 +va (VaSet +) +xt "-14800,63500,-8000,64500" +st "trigger_id : (47:0)" +ju 2 +blo "-8000,64300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "trigger_id" +t "std_logic_vector" +b "(47 downto 0)" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*104 (CptPort +uid 1764,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1765,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-18750,63625,-18000,64375" +) +tg (CPTG +uid 1766,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1767,0 +va (VaSet +) +xt "-17000,63500,-14200,64500" +st "trigger" +blo "-17000,64300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "trigger" +t "std_logic" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +) +) +) +*105 (CptPort +uid 6207,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6208,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-18750,62625,-18000,63375" +) +tg (CPTG +uid 6209,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6210,0 +va (VaSet +) +xt "-17000,62500,-15700,63500" +st "clk" +blo "-17000,63300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "clk" +t "std_logic" +o 3 +suid 3,0 +) +) +) +] +shape (Rectangle +uid 1769,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "-18000,62000,-7000,67000" +) +oxt "32000,2000,43000,12000" +ttg (MlTextGroup +uid 1770,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*106 (Text +uid 1771,0 +va (VaSet +font "Arial,8,1" +) +xt "-6300,65000,300,66000" +st "FACT_FAD_LIB" +blo "-6300,65800" +tm "BdLibraryNameMgr" +) +*107 (Text +uid 1772,0 +va (VaSet +font "Arial,8,1" +) +xt "-6300,66000,300,67000" +st "trigger_counter" +blo "-6300,66800" +tm "CptNameMgr" +) +*108 (Text +uid 1773,0 +va (VaSet +font "Arial,8,1" +) +xt "-6300,67000,1300,68000" +st "I_main_ext_trigger" +blo "-6300,67800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1774,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1775,0 +text (MLText +uid 1776,0 +va (VaSet +font "Courier New,8,0" +) +xt "-18000,61000,-18000,61000" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 1777,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "-17750,65250,-16250,66750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sIVOD 1 +) +archFileType "UNKNOWN" +) +*109 (Net +uid 1981,0 +lang 2 +decl (Decl +n "trigger_id" +t "std_logic_vector" +b "(47 downto 0)" +preAdd 0 +posAdd 0 +o 72 +suid 34,0 +) +declText (MLText +uid 1982,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,81000,-52500,81800" +st "SIGNAL trigger_id : std_logic_vector(47 downto 0) +" +) +) +*110 (Net +uid 2297,0 +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAMADDRWIDTH64b-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 64 +suid 36,0 +) +declText (MLText +uid 2298,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,73000,-45000,73800" +st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) +" +) +) +*111 (SaComponent +uid 2311,0 +optionalChildren [ +*112 (CptPort +uid 2307,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2308,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,69625,72000,70375" +) +tg (CPTG +uid 2309,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2310,0 +va (VaSet +font "arial,8,0" +) +xt "73000,69500,91400,70500" +st "ram_start_addr : (RAM_ADDR_WIDTH_64B-1:0)" +blo "73000,70300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH_64B-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 18 +suid 1,0 +i "(others => '0')" +) +) +) +*113 (CptPort +uid 2351,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2352,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,67625,72000,68375" +) +tg (CPTG +uid 2353,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2354,0 +va (VaSet +font "arial,8,0" +) +xt "73000,67500,74300,68500" +st "clk" +blo "73000,68300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "clk" +t "std_logic" +o 1 +suid 2,0 +) +) +) +*114 (CptPort +uid 2361,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2362,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,76625,72000,77375" +) +tg (CPTG +uid 2363,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2364,0 +va (VaSet +font "arial,8,0" +) +xt "73000,76500,78100,77500" +st "config_ready" +blo "73000,77300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "config_ready" +t "std_logic" +o 6 +suid 5,0 +i "'0'" +) +) +) +*115 (CptPort +uid 2365,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2366,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,74625,72000,75375" +) +tg (CPTG +uid 2367,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2368,0 +va (VaSet +font "arial,8,0" +) +xt "73000,74500,77800,75500" +st "config_start" +blo "73000,75300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "config_start" +t "std_logic" +o 2 +suid 3,0 +) +) +) +*116 (CptPort +uid 2369,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2370,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,70625,72000,71375" +) +tg (CPTG +uid 2371,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2372,0 +va (VaSet +font "arial,8,0" +) +xt "73000,70500,78300,71500" +st "ram_write_ea" +blo "73000,71300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "ram_write_ea" +t "std_logic" +o 5 +suid 4,0 +i "'0'" +) +) +) +*117 (CptPort +uid 2373,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2374,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,71625,72000,72375" +) +tg (CPTG +uid 2375,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2376,0 +va (VaSet +font "arial,8,0" +) +xt "73000,71500,79300,72500" +st "ram_write_ready" +blo "73000,72300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "ram_write_ready" +t "std_logic" +o 3 +suid 12,0 +) +) +) +*118 (CptPort +uid 2377,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2378,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,77625,72000,78375" +) +tg (CPTG +uid 2379,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2380,0 +va (VaSet +font "arial,8,0" +) +xt "73000,77500,76000,78500" +st "roi_max" +blo "73000,78300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "roi_max" +t "roi_max_type" +posAdd 0 +o 8 +suid 14,0 +i "(others => conv_std_logic_vector (0, 11))" +) +) +) +*119 (CptPort +uid 2381,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2382,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,67625,103750,68375" +) +tg (CPTG +uid 2383,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2384,0 +va (VaSet +font "arial,8,0" +) +xt "98600,67500,102000,68500" +st "wiz_busy" +ju 2 +blo "102000,68300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "wiz_busy" +t "std_logic" +o 16 +suid 13,0 +) +) +) +*120 (CptPort +uid 2385,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2386,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,71625,103750,72375" +) +tg (CPTG +uid 2387,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2388,0 +va (VaSet +font "arial,8,0" +) +xt "90200,71500,102000,72500" +st "wiz_number_of_channels : (3:0)" +ju 2 +blo "102000,72300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_number_of_channels" +t "std_logic_vector" +b "(3 downto 0)" +o 12 +suid 6,0 +i "(others => '0')" +) +) +) +*121 (CptPort +uid 2389,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2390,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,70625,103750,71375" +) +tg (CPTG +uid 2391,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2392,0 +va (VaSet +font "arial,8,0" +) +xt "82100,70500,102000,71500" +st "wiz_ram_start_addr : (RAM_ADDR_WIDTH_16B-1:0)" +ju 2 +blo "102000,71300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH_16B-1 downto 0)" +preAdd 0 +o 10 +suid 7,0 +i "(others => '0')" +) +) +) +*122 (CptPort +uid 2393,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2394,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,68625,103750,69375" +) +tg (CPTG +uid 2395,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2396,0 +va (VaSet +font "arial,8,0" +) +xt "96900,68500,102000,69500" +st "wiz_write_ea" +ju 2 +blo "102000,69300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_ea" +t "std_logic" +o 13 +suid 8,0 +i "'0'" +) +) +) +*123 (CptPort +uid 2397,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2398,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,72625,103750,73375" +) +tg (CPTG +uid 2399,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2400,0 +va (VaSet +font "arial,8,0" +) +xt "96500,72500,102000,73500" +st "wiz_write_end" +ju 2 +blo "102000,73300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_end" +t "std_logic" +o 15 +suid 9,0 +i "'0'" +) +) +) +*124 (CptPort +uid 2401,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2402,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,73625,103750,74375" +) +tg (CPTG +uid 2403,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2404,0 +va (VaSet +font "arial,8,0" +) +xt "95400,73500,102000,74500" +st "wiz_write_header" +ju 2 +blo "102000,74300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_header" +t "std_logic" +o 14 +suid 10,0 +i "'0'" +) +) +) +*125 (CptPort +uid 2405,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2406,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,69625,103750,70375" +) +tg (CPTG +uid 2407,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2408,0 +va (VaSet +font "arial,8,0" +) +xt "92600,69500,102000,70500" +st "wiz_write_length : (16:0)" +ju 2 +blo "102000,70300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_length" +t "std_logic_vector" +b "(16 downto 0)" +o 11 +suid 11,0 +i "(others => '0')" +) +) +) +*126 (CptPort +uid 2454,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2455,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,84625,72000,85375" +) +tg (CPTG +uid 2456,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2457,0 +va (VaSet +font "arial,8,0" +) +xt "73000,84500,76400,85500" +st "roi_array" +blo "73000,85300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "roi_array" +t "roi_array_type" +o 4 +suid 15,0 +) +) +) +*127 (CptPort +uid 2628,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2629,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,78625,72000,79375" +) +tg (CPTG +uid 2630,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2631,0 +va (VaSet +font "arial,8,0" +) +xt "73000,78500,82100,79500" +st "package_length : (15:0)" +blo "73000,79300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "package_length" +t "std_logic_vector" +b "(15 downto 0)" +o 9 +suid 18,0 +i "(others => '0')" +) +) +) +*128 (CptPort +uid 5991,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5992,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,75625,72000,76375" +) +tg (CPTG +uid 5993,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5994,0 +va (VaSet +font "arial,8,0" +) +xt "73000,75500,78600,76500" +st "config_started" +blo "73000,76300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "config_started" +t "std_logic" +o 7 +suid 21,0 +i "'0'" +) +) +) +*129 (CptPort +uid 8410,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8411,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,74625,103750,75375" +) +tg (CPTG +uid 8412,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8413,0 +va (VaSet +font "arial,8,0" +) +xt "99000,74500,102000,75500" +st "wiz_ack" +ju 2 +blo "102000,75300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "wiz_ack" +t "std_logic" +o 17 +suid 22,0 +) +) +) +] +shape (Rectangle +uid 2312,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "72000,67000,103000,87000" +) +oxt "15000,6000,23000,16000" +ttg (MlTextGroup +uid 2313,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*130 (Text +uid 2314,0 +va (VaSet +font "arial,8,1" +) +xt "72350,87000,78550,88000" +st "FACT_FAD_lib" +blo "72350,87800" +tm "BdLibraryNameMgr" +) +*131 (Text +uid 2315,0 +va (VaSet +font "arial,8,1" +) +xt "72350,88000,79650,89000" +st "memory_manager" +blo "72350,88800" +tm "CptNameMgr" +) +*132 (Text +uid 2316,0 +va (VaSet +font "arial,8,1" +) +xt "72350,89000,82850,90000" +st "I_main_memory_manager" +blo "72350,89800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 2317,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 2318,0 +text (MLText +uid 2319,0 +va (VaSet +font "Courier New,8,0" +) +xt "72000,65400,101500,67000" +st "RAM_ADDR_WIDTH_64B = RAMADDRWIDTH64b ( integer ) +RAM_ADDR_WIDTH_16B = RAMADDRWIDTH64b+2 ( integer ) " +) +header "" +) +elements [ +(GiElement +name "RAM_ADDR_WIDTH_64B" +type "integer" +value "RAMADDRWIDTH64b" +) +(GiElement +name "RAM_ADDR_WIDTH_16B" +type "integer" +value "RAMADDRWIDTH64b+2" +) +] +) +viewicon (ZoomableIcon +uid 2320,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "72250,85250,73750,86750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*133 (Net +uid 2468,0 +lang 2 +decl (Decl +n "wiz_busy" +t "std_logic" +o 73 +suid 38,0 +) +declText (MLText +uid 2469,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,82600,-62500,83400" +st "SIGNAL wiz_busy : std_logic +" +) +) +*134 (Net +uid 2474,0 +lang 2 +decl (Decl +n "wiz_write_ea" +t "std_logic" +o 76 +suid 39,0 +i "'0'" +) +declText (MLText +uid 2475,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,85000,-41500,85800" +st "SIGNAL wiz_write_ea : std_logic := '0' +" +) +) +*135 (Net +uid 2480,0 +lang 2 +decl (Decl +n "wiz_write_length" +t "std_logic_vector" +b "(16 downto 0)" +o 79 +suid 40,0 +i "(others => '0')" +) +declText (MLText +uid 2481,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,87400,-35500,88200" +st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0') +" +) +) +*136 (Net +uid 2486,0 +lang 2 +decl (Decl +n "wiz_ram_start_addr" +t "std_logic_vector" +b "(RAMADDRWIDTH64b+1 DOWNTO 0)" +preAdd 0 +o 75 +suid 41,0 +i "(others => '0')" +) +declText (MLText +uid 2487,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,84200,-35500,85000" +st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0') +" +) +) +*137 (Net +uid 2492,0 +lang 2 +decl (Decl +n "wiz_number_of_channels" +t "std_logic_vector" +b "(3 downto 0)" +o 74 +suid 42,0 +i "(others => '0')" +) +declText (MLText +uid 2493,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,83400,-35500,84200" +st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0') +" +) +) +*138 (Net +uid 2498,0 +lang 2 +decl (Decl +n "wiz_write_end" +t "std_logic" +o 77 +suid 43,0 +i "'0'" +) +declText (MLText +uid 2499,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,85800,-41500,86600" +st "SIGNAL wiz_write_end : std_logic := '0' +" +) +) +*139 (Net +uid 2504,0 +lang 2 +decl (Decl +n "wiz_write_header" +t "std_logic" +o 78 +suid 44,0 +i "'0'" +) +declText (MLText +uid 2505,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,86600,-41500,87400" +st "SIGNAL wiz_write_header : std_logic := '0' +" +) +) +*140 (Net +uid 2574,0 +decl (Decl +n "ram_write_ea" +t "std_logic" +o 65 +suid 48,0 +) +declText (MLText +uid 2575,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,73800,-62500,74600" +st "SIGNAL ram_write_ea : std_logic +" +) +) +*141 (Net +uid 2580,0 +decl (Decl +n "ram_write_ready" +t "std_logic" +o 66 +suid 49,0 +i "'0'" +) +declText (MLText +uid 2581,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,74600,-41500,75400" +st "SIGNAL ram_write_ready : std_logic := '0' +" +) +) +*142 (Net +uid 2586,0 +decl (Decl +n "config_start" +t "std_logic" +o 44 +suid 50,0 +i "'0'" +) +declText (MLText +uid 2587,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,54600,-41500,55400" +st "SIGNAL config_start : std_logic := '0' +" +) +) +*143 (Net +uid 2592,0 +decl (Decl +n "config_ready" +t "std_logic" +o 41 +suid 51,0 +) +declText (MLText +uid 2593,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,52200,-62500,53000" +st "SIGNAL config_ready : std_logic +" +) +) +*144 (Net +uid 2598,0 +decl (Decl +n "roi_max" +t "roi_max_type" +o 68 +suid 52,0 +) +declText (MLText +uid 2599,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,76200,-61000,77000" +st "SIGNAL roi_max : roi_max_type +" +) +) +*145 (Net +uid 2640,0 +decl (Decl +n "package_length" +t "std_logic_vector" +b "(15 downto 0)" +o 61 +suid 54,0 +) +declText (MLText +uid 2641,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,70600,-52500,71400" +st "SIGNAL package_length : std_logic_vector(15 downto 0) +" +) +) +*146 (Net +uid 2776,0 +decl (Decl +n "adc_oeb" +t "std_logic" +o 16 +suid 57,0 +i "'1'" +) +declText (MLText +uid 2777,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,30200,-45000,31000" +st "adc_oeb : std_logic := '1' +" +) +) +*147 (PortIoOut +uid 2798,0 +shape (CompositeShape +uid 2799,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2800,0 +sl 0 +ro 90 +xt "-28000,81625,-26500,82375" +) +(Line +uid 2801,0 +sl 0 +ro 90 +xt "-26500,82000,-26000,82000" +pts [ +"-26000,82000" +"-26500,82000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2802,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2803,0 +va (VaSet +) +xt "-32200,81500,-29000,82500" +st "adc_oeb" +ju 2 +blo "-29000,82300" +tm "WireNameMgr" +) +) +) +*148 (PortIoIn +uid 2804,0 +shape (CompositeShape +uid 2805,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2806,0 +sl 0 +ro 270 +xt "-28000,76625,-26500,77375" +) +(Line +uid 2807,0 +sl 0 +ro 270 +xt "-26500,77000,-26000,77000" +pts [ +"-26500,77000" +"-26000,77000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2808,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2809,0 +va (VaSet +) +xt "-34400,76500,-29000,77500" +st "adc_otr_array" +ju 2 +blo "-29000,77300" +tm "WireNameMgr" +) +) +) +*149 (Net +uid 2924,0 +decl (Decl +n "roi_array" +t "roi_array_type" +o 67 +suid 65,0 +) +declText (MLText +uid 2925,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,75400,-60000,76200" +st "SIGNAL roi_array : roi_array_type +" +) +) +*150 (PortIoIn +uid 2950,0 +shape (CompositeShape +uid 2951,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2952,0 +sl 0 +ro 270 +xt "-28000,85625,-26500,86375" +) +(Line +uid 2953,0 +sl 0 +ro 270 +xt "-26500,86000,-26000,86000" +pts [ +"-26500,86000" +"-26000,86000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2954,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2955,0 +va (VaSet +) +xt "-32300,85500,-29000,86500" +st "board_id" +ju 2 +blo "-29000,86300" +tm "WireNameMgr" +) +) +) +*151 (PortIoIn +uid 2956,0 +shape (CompositeShape +uid 2957,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2958,0 +sl 0 +ro 270 +xt "-28000,86625,-26500,87375" +) +(Line +uid 2959,0 +sl 0 +ro 270 +xt "-26500,87000,-26000,87000" +pts [ +"-26500,87000" +"-26000,87000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2960,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2961,0 +va (VaSet +) +xt "-32100,86500,-29000,87500" +st "crate_id" +ju 2 +blo "-29000,87300" +tm "WireNameMgr" +) +) +) +*152 (Grouping +uid 3137,0 +optionalChildren [ +*153 (CommentText +uid 3139,0 +shape (Rectangle +uid 3140,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "125000,175000,142000,176000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 3141,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "125200,175000,134500,176000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*154 (CommentText +uid 3142,0 +shape (Rectangle +uid 3143,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "142000,171000,146000,172000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 3144,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "142200,171000,145200,172000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*155 (CommentText +uid 3145,0 +shape (Rectangle +uid 3146,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "125000,173000,142000,174000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 3147,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "125200,173000,135200,174000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*156 (CommentText +uid 3148,0 +shape (Rectangle +uid 3149,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "121000,173000,125000,174000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 3150,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "121200,173000,123300,174000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*157 (CommentText +uid 3151,0 +shape (Rectangle +uid 3152,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "142000,172000,162000,176000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 3153,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "142200,172200,151400,173200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*158 (CommentText +uid 3154,0 +shape (Rectangle +uid 3155,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "146000,171000,162000,172000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 3156,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "146200,171000,150700,172000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*159 (CommentText +uid 3157,0 +shape (Rectangle +uid 3158,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "121000,171000,142000,173000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 3159,0 +va (VaSet +fg "32768,0,0" +) +xt "128700,171000,134300,173000" +st " +TU Dortmund +Physik / EE +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*160 (CommentText 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"-13800,28000,-6500,29000" +st "I_main_clock_gen" +blo "-13800,28800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 4200,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 4201,0 +text (MLText +uid 4202,0 +va (VaSet +font "Courier New,8,0" +) +xt "-35000,24000,-35000,24000" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 4203,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "-19750,23250,-18250,24750" +iconName "BlockDiagram.png" +iconMaskName "BlockDiagram.msk" +ftype 1 +) +viewiconposition 0 +portVis (PortSigDisplay +sIVOD 1 +) +archFileType "UNKNOWN" +) +*174 (Net +uid 4204,0 +decl (Decl +n "CLK_25" +t "std_logic" +o 32 +suid 91,0 +) +declText (MLText +uid 4205,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,45000,-62500,45800" +st "SIGNAL CLK_25 : std_logic +" +) +) +*175 (PortIoOut +uid 4220,0 +shape (CompositeShape +uid 4221,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4222,0 +sl 0 +ro 90 +xt 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4551,0 +shape (CompositeShape +uid 4552,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4553,0 +sl 0 +ro 90 +xt "-39000,99625,-37500,100375" +) +(Line +uid 4554,0 +sl 0 +ro 90 +xt "-37500,100000,-37000,100000" +pts [ +"-37000,100000" +"-37500,100000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 4555,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4556,0 +va (VaSet +) +xt "-45900,99500,-40000,100500" +st "drs_channel_id" +ju 2 +blo "-40000,100300" +tm "WireNameMgr" +) +) +) +*186 (PortIoOut +uid 4557,0 +shape (CompositeShape +uid 4558,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4559,0 +sl 0 +ro 90 +xt "-28000,59625,-26500,60375" +) +(Line +uid 4560,0 +sl 0 +ro 90 +xt "-26500,60000,-26000,60000" +pts [ +"-26000,60000" +"-26500,60000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 4561,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4562,0 +va (VaSet +) +xt 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"-17400,56000,-9900,57000" +st "I_main_drs_pulser" +blo "-17400,56800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 4909,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 4910,0 +text (MLText +uid 4911,0 +va (VaSet +font "Courier New,8,0" +) +xt "-8500,46000,-8500,46000" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 4912,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "-17750,52250,-16250,53750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*211 (Net +uid 4946,0 +decl (Decl +n "RSRLOAD" +t "std_logic" +o 14 +suid 117,0 +i "'0'" +) +declText (MLText +uid 4947,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,28600,-45000,29400" +st "RSRLOAD : std_logic := '0' +" +) +) +*212 (PortIoOut +uid 4954,0 +shape (CompositeShape +uid 4955,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4956,0 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"91000,100300" +) +) +thePort (LogicalPort +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 2 +suid 2,0 +) +) +) +*218 (CptPort +uid 5036,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5037,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92000,101625,92750,102375" +) +tg (CPTG +uid 5038,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5039,0 +va (VaSet +) +xt "84400,101500,91000,102500" +st "config_data_valid" +ju 2 +blo "91000,102300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_data_valid" +t "std_logic" +o 7 +suid 3,0 +) +) +) +*219 (CptPort +uid 5040,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5041,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92000,105625,92750,106375" +) +tg (CPTG +uid 5042,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5043,0 +va (VaSet +) +xt "86200,105500,91000,106500" +st "config_busy" +ju 2 +blo "91000,106300" +) +) +thePort (LogicalPort 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(Triangle +uid 5061,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92000,104625,92750,105375" +) +tg (CPTG +uid 5062,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5063,0 +va (VaSet +) +xt "85800,104500,91000,105500" +st "config_rd_en" +ju 2 +blo "91000,105300" +) +) +thePort (LogicalPort +decl (Decl +n "config_rd_en" +t "std_logic" +o 3 +suid 9,0 +) +) +) +*225 (CptPort +uid 5064,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5065,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "73250,102625,74000,103375" +) +tg (CPTG +uid 5066,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5067,0 +va (VaSet +) +xt "75000,102500,79800,103500" +st "config_start" +blo "75000,103300" +) +) +thePort (LogicalPort +decl (Decl +n "config_start" +t "std_logic" +o 4 +suid 10,0 +) +) +) +*226 (CptPort +uid 5068,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5069,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "73250,104625,74000,105375" +) +tg (CPTG +uid 5070,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5071,0 +va (VaSet +) +xt "75000,104500,80100,105500" +st "config_ready" +blo "75000,105300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_ready" +t "std_logic" +o 8 +suid 11,0 +) +) +) +*227 (CptPort +uid 5995,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5996,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "73250,103625,74000,104375" +) +tg (CPTG +uid 5997,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5998,0 +va (VaSet +) +xt "75000,103500,80600,104500" +st "config_started" +blo "75000,104300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_started" +t "std_logic" +o 9 +suid 12,0 +i "'0'" +) +) +) +*228 (CptPort +uid 8500,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8501,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92000,109625,92750,110375" +) +tg (CPTG +uid 8502,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8503,0 +va (VaSet +) +xt "83800,109500,91000,110500" +st "drs_address : (3:0)" +ju 2 +blo "91000,110300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 11 +suid 13,0 +) +) +) +*229 (CptPort +uid 8504,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8505,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92000,110625,92750,111375" +) +tg (CPTG +uid 8506,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8507,0 +va (VaSet +) +xt "83800,110500,91000,111500" +st "drs_address_mode" +ju 2 +blo "91000,111300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 12 +suid 14,0 +) +) +) +] +shape (Rectangle +uid 5073,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "74000,99000,92000,112000" +) +oxt "15000,13000,33000,26000" +ttg (MlTextGroup +uid 5074,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*230 (Text +uid 5075,0 +va (VaSet +font "Arial,8,1" +) +xt "74200,112000,80400,113000" +st "FACT_FAD_lib" +blo "74200,112800" +tm "BdLibraryNameMgr" +) +*231 (Text +uid 5076,0 +va (VaSet +font "Arial,8,1" +) +xt "74200,113000,79600,114000" +st "control_unit" +blo "74200,113800" +tm "CptNameMgr" +) +*232 (Text +uid 5077,0 +va (VaSet +font "Arial,8,1" +) +xt "74200,114000,82400,115000" +st "I_main_control_unit" +blo "74200,114800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 5078,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 5079,0 +text (MLText +uid 5080,0 +va (VaSet +font "Courier New,8,0" +) +xt "59000,98800,59000,98800" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 5081,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "74250,110250,75750,111750" +iconName "BlockDiagram.png" +iconMaskName "BlockDiagram.msk" +ftype 1 +) +viewiconposition 0 +portVis (PortSigDisplay +) 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"SIGNAL config_data : std_logic_vector(15 DOWNTO 0) +" +) +) +*237 (Net +uid 5120,0 +decl (Decl +n "config_wr_en" +t "std_logic" +o 51 +suid 123,0 +) +declText (MLText +uid 5121,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,60200,-62500,61000" +st "SIGNAL config_wr_en : std_logic +" +) +) +*238 (Net +uid 5128,0 +decl (Decl +n "config_rd_en" +t "std_logic" +o 40 +suid 124,0 +) +declText (MLText +uid 5129,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,51400,-62500,52200" +st "SIGNAL config_rd_en : std_logic +" +) +) +*239 (Net +uid 5144,0 +decl (Decl +n "dac_array" +t "dac_array_type" +o 52 +suid 126,0 +) +declText (MLText +uid 5145,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,61000,-60000,61800" +st "SIGNAL dac_array : dac_array_type +" +) +) +*240 (Net +uid 5194,0 +decl (Decl +n "config_start_cm" +t "std_logic" +o 45 +suid 131,0 +) +declText (MLText +uid 5195,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,55400,-62500,56200" +st "SIGNAL config_start_cm : std_logic +" +) +) +*241 (Net +uid 5196,0 +decl (Decl +n "config_ready_cm" +t "std_logic" +o 42 +suid 132,0 +) +declText (MLText +uid 5197,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,53000,-62500,53800" +st "SIGNAL config_ready_cm : std_logic +" +) +) +*242 (Net +uid 5220,0 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 DOWNTO 0)" +posAdd 0 +o 21 +suid 133,0 +i "(OTHERS => '0')" +) +declText (MLText +uid 5221,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,34200,-39000,35000" +st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') +" +) +) +*243 (Net +uid 5279,0 +decl (Decl +n "s_trigger" +t "std_logic" +o 69 +suid 134,0 +i "'0'" +) +declText (MLText +uid 5280,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,77000,-41500,77800" +st "SIGNAL s_trigger : std_logic := '0' +" +) +) +*244 (Net +uid 5472,0 +decl (Decl +n "sensor_ready" +t "std_logic" +o 71 +suid 140,0 +) +declText (MLText +uid 5473,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,80200,-62500,81000" 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"-85000,45800,-57500,46600" +st "SIGNAL adc_data_array_int : adc_data_array_type +" +) +) +*249 (SaComponent +uid 5678,0 +optionalChildren [ +*250 (CptPort +uid 5658,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5659,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-18750,75625,-18000,76375" +) +tg (CPTG +uid 5660,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5661,0 +va (VaSet +font "arial,8,0" +) +xt "-17000,75500,-11100,76500" +st "adc_data_array" +blo "-17000,76300" +) +) +thePort (LogicalPort +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 2 +suid 5,0 +) +) +) +*251 (CptPort +uid 5662,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5663,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,75625,750,76375" +) +tg (CPTG +uid 5664,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5665,0 +va (VaSet +font "arial,8,0" +) +xt "-8100,75500,-1000,76500" +st "adc_data_array_int" +ju 2 +blo "-1000,76300" +) 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5856,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5857,0 +sl 0 +ro 90 +xt "10000,104625,11500,105375" +) +(Line +uid 5858,0 +sl 0 +ro 90 +xt "11500,105000,12000,105000" +pts [ +"12000,105000" +"11500,105000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 5859,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5860,0 +va (VaSet +) +xt "6200,104500,9000,105500" +st "dac_cs" +ju 2 +blo "9000,105300" +tm "WireNameMgr" +) +) +) +*282 (PortIoOut +uid 5861,0 +shape (CompositeShape +uid 5862,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5863,0 +sl 0 +ro 90 +xt "10000,103625,11500,104375" +) +(Line +uid 5864,0 +sl 0 +ro 90 +xt "11500,104000,12000,104000" +pts [ +"12000,104000" +"11500,104000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 5865,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5866,0 +va (VaSet +) +xt "5100,103500,9000,104500" +st "sensor_cs" +ju 2 +blo "9000,104300" +tm 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"ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5119,0 +va (VaSet +) +xt "94000,100000,101700,101000" +st "config_data : (15:0)" +blo "94000,100800" +tm "WireNameMgr" +) +) +on &236 +) +*429 (Wire +uid 5122,0 +shape (OrthoPolyLine +uid 5123,0 +va (VaSet +vasetType 3 +) +xt "92750,82000,126250,104000" +pts [ +"126250,82000" +"119000,82000" +"119000,104000" +"92750,104000" +] +) +start &91 +end &222 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5126,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5127,0 +va (VaSet +) +xt "121000,81000,126300,82000" +st "config_wr_en" +blo "121000,81800" +tm "WireNameMgr" +) +) +on &237 +) +*430 (Wire +uid 5130,0 +shape (OrthoPolyLine +uid 5131,0 +va (VaSet +vasetType 3 +) +xt "92750,83000,126250,105000" +pts [ +"126250,83000" +"120000,83000" +"120000,105000" +"92750,105000" +] +) +start &93 +end &224 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5134,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5135,0 +va (VaSet +) +xt "121000,82000,126200,83000" +st "config_rd_en" +blo "121000,82800" +tm "WireNameMgr" +) +) +on &238 +) +*431 (Wire +uid 5138,0 +optionalChildren [ +*432 (BdJunction +uid 5400,0 +ps "OnConnectorStrategy" +shape (Circle +uid 5401,0 +va (VaSet +vasetType 1 +) +xt "57600,84600,58400,85400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 5139,0 +va (VaSet +vasetType 3 +) +xt "40750,80000,73250,102000" +pts [ +"73250,102000" +"58000,102000" +"58000,80000" +"40750,80000" +] +) +start &221 +end &35 +ss 0 +es 0 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5142,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5143,0 +va (VaSet +) +xt "42000,79000,45400,80000" +st "roi_array" +blo "42000,79800" +tm "WireNameMgr" +) +) +on &149 +) +*433 (Wire +uid 5146,0 +shape (OrthoPolyLine +uid 5147,0 +va (VaSet +vasetType 3 +) +xt "37750,109000,73250,109000" +pts [ +"73250,109000" +"37750,109000" +] +) +start &223 +end &261 +es 0 +sat 32 +eat 32 +st 0 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(VaSet +) +xt "66000,102000,72200,103000" +st "config_start_cm" +blo "66000,102800" +tm "WireNameMgr" +) +) +on &240 +) +*436 (Wire +uid 5190,0 +shape (OrthoPolyLine +uid 5191,0 +va (VaSet +vasetType 3 +) +xt "40750,83000,73250,105000" +pts [ +"73250,105000" +"55000,105000" +"55000,83000" +"40750,83000" +] +) +start &226 +end &46 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5192,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5193,0 +va (VaSet +) +xt "66000,104000,72500,105000" +st "config_ready_cm" +blo "66000,104800" +tm "WireNameMgr" +) +) +on &241 +) +*437 (Wire +uid 5222,0 +shape (OrthoPolyLine +uid 5223,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "148750,71000,153000,71000" +pts [ +"148750,71000" +"153000,71000" +] +) +start &85 +end &19 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5224,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5225,0 +va (VaSet +isHidden 1 +) +xt "150750,70000,152150,71000" +st "led" +blo "150750,70800" +tm "WireNameMgr" +) +) +on &242 +) +*438 (Wire +uid 5281,0 +shape (OrthoPolyLine +uid 5282,0 +va (VaSet +vasetType 3 +) +xt "40750,53000,126250,59000" +pts [ +"126250,59000" +"73000,59000" +"73000,53000" +"40750,53000" +] +) +start &86 +end &48 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5283,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5284,0 +va (VaSet +) +xt "121250,58000,124850,59000" +st "s_trigger" +blo "121250,58800" +tm "WireNameMgr" +) +) +on &243 +) +*439 (Wire +uid 5404,0 +shape (OrthoPolyLine +uid 5405,0 +va (VaSet +vasetType 3 +) +xt "37750,85000,48000,107000" +pts [ +"37750,107000" +"48000,107000" +"48000,85000" +"40750,85000" +] +) +start &262 +end &50 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5406,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5407,0 +va (VaSet +) +xt "39000,106000,45500,107000" +st "config_ready_spi" +blo "39000,106800" +tm "WireNameMgr" +) +) +on &246 +) +*440 (Wire +uid 5474,0 +shape (OrthoPolyLine +uid 5475,0 +va (VaSet +vasetType 3 +) +xt "37750,90000,44000,101000" +pts [ +"37750,101000" +"44000,101000" +"44000,90000" +"40750,90000" +] +) +start &265 +end &52 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5476,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5477,0 +va (VaSet +) +xt "39750,100000,45050,101000" +st "sensor_ready" +blo "39750,100800" +tm "WireNameMgr" +) +) +on &244 +) +*441 (Wire +uid 5480,0 +shape (OrthoPolyLine +uid 5481,0 +va (VaSet +vasetType 3 +) +xt "37750,89000,45000,102000" +pts [ +"37750,102000" +"45000,102000" +"45000,89000" +"40750,89000" +] +) +start &264 +end &51 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5482,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5483,0 +va (VaSet +) +xt "39750,101000,44950,102000" +st "sensor_array" +blo "39750,101800" +tm "WireNameMgr" +) +) +on &245 +) +*442 (Wire +uid 5582,0 +shape (OrthoPolyLine +uid 5583,0 +va (VaSet +vasetType 3 +lineColor "0,0,65535" +) +xt "69000,100000,73250,100000" +pts [ +"69000,100000" +"73250,100000" +] +) +end &216 +sat 16 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5586,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5587,0 +va (VaSet +) +xt "70000,99000,73100,100000" +st "CLK_50" +blo "70000,99800" +tm "WireNameMgr" +) +) +on &165 +) +*443 (Wire +uid 5602,0 +optionalChildren [ +&422 +*444 (BdJunction +uid 6086,0 +ps "OnConnectorStrategy" +shape (Circle +uid 6087,0 +va (VaSet +vasetType 1 +) +xt "67600,43600,68400,44400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 5603,0 +va (VaSet +vasetType 3 +lineColor "0,32896,0" +) +xt "15000,38000,76250,48000" +pts [ +"18250,48000" +"15000,48000" +"15000,38000" +"68000,38000" +"68000,44000" +"76250,44000" +] +) +start &23 +end &313 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5604,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5605,0 +va (VaSet +) +xt "15000,47000,18100,48000" +st "CLK_25" +blo "15000,47800" +tm "WireNameMgr" +) +) +on &174 +) +*445 (Wire +uid 5626,0 +shape (OrthoPolyLine +uid 5627,0 +va (VaSet +vasetType 3 +) +xt "750,76000,18250,76000" +pts [ +"18250,76000" +"750,76000" +] +) +start &45 +end &251 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5630,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5631,0 +va (VaSet +) +xt "11250,75000,18350,76000" +st "adc_data_array_int" +blo "11250,75800" +tm "WireNameMgr" +) +) +on &248 +) +*446 (Wire +uid 5634,0 +shape (OrthoPolyLine +uid 5635,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "750,77000,18250,77000" +pts [ +"18250,77000" +"750,77000" +] +) +start &38 +end &252 +sat 32 +eat 32 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 5638,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5639,0 +va (VaSet +) +xt "11250,76000,16750,77000" +st "adc_otr : (3:0)" +blo "11250,76800" +tm "WireNameMgr" +) +) +on &247 +) +*447 (Wire +uid 5646,0 +shape (OrthoPolyLine +uid 5647,0 +va (VaSet +vasetType 3 +lineColor "49152,0,0" +) +xt "-26000,74000,-18750,74000" +pts [ +"-26000,74000" +"-18750,74000" +] +) +end &254 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5652,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5653,0 +va (VaSet +) +xt "-25000,73000,-20500,74000" +st "CLK_25_PS" +blo "-25000,73800" +tm "WireNameMgr" +) +) +on &163 +) +*448 (Wire +uid 5745,0 +shape (OrthoPolyLine +uid 5746,0 +va (VaSet +vasetType 3 +) +xt "37750,87000,46000,105000" +pts [ +"40750,87000" +"46000,87000" +"46000,105000" +"37750,105000" +] +) +start &54 +end &263 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5749,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5750,0 +va (VaSet +) +xt "39000,104000,45200,105000" +st "config_start_spi" +blo "39000,104800" +tm "WireNameMgr" +) +) +on &258 +) +*449 (Wire +uid 5805,0 +shape (OrthoPolyLine +uid 5806,0 +va (VaSet +vasetType 3 +) +xt "16000,101000,20250,101000" +pts [ +"16000,101000" +"20250,101000" +] +) +end &268 +sat 16 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5809,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5810,0 +va (VaSet +) +xt "17000,100000,20100,101000" +st "CLK_50" +blo "17000,100800" +tm "WireNameMgr" +) +) +on &165 +) +*450 (Wire +uid 5813,0 +shape (OrthoPolyLine +uid 5814,0 +va (VaSet +vasetType 3 +) +xt "-18000,112000,-13000,112000" +pts [ +"-13000,112000" +"-18000,112000" +] +) +start &349 +end &279 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5817,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5818,0 +va (VaSet +isHidden 1 +) +xt "-17000,111000,-15300,112000" +st "sclk" +blo "-17000,111800" +tm "WireNameMgr" +) +) +on &275 +) +*451 (Wire +uid 5821,0 +shape (OrthoPolyLine +uid 5822,0 +va (VaSet +vasetType 3 +) +xt "12000,108000,20250,108000" +pts [ +"20250,108000" +"12000,108000" +] +) +start &271 +end &280 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5825,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5826,0 +va (VaSet +isHidden 1 +) +xt "13000,107000,14400,108000" +st "sio" +blo "13000,107800" +tm "WireNameMgr" +) +) +on &276 +) +*452 (Wire +uid 5829,0 +shape (OrthoPolyLine +uid 5830,0 +va (VaSet +vasetType 3 +) +xt "12000,105000,20250,105000" +pts [ +"20250,105000" +"12000,105000" +] +) +start &266 +end &281 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5833,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5834,0 +va (VaSet +isHidden 1 +) +xt "13000,104000,15800,105000" +st "dac_cs" +blo "13000,104800" +tm "WireNameMgr" +) +) +on &277 +) +*453 (Wire +uid 5837,0 +shape (OrthoPolyLine +uid 5838,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "12000,104000,20250,104000" +pts [ +"20250,104000" +"12000,104000" +] +) +start &267 +end &282 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5841,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5842,0 +va (VaSet +isHidden 1 +) +xt "13000,103000,16900,104000" +st "sensor_cs" +blo "13000,103800" +tm "WireNameMgr" +) +) +on &278 +) +*454 (Wire +uid 5950,0 +shape (OrthoPolyLine +uid 5951,0 +va (VaSet +vasetType 3 +) +xt "40750,54000,126250,60000" +pts [ +"126250,60000" +"72000,60000" +"72000,54000" +"40750,54000" +] +) +start &92 +end &56 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5952,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5953,0 +va (VaSet +) +xt "120250,59000,124850,60000" +st "new_config" +blo "120250,59800" +tm "WireNameMgr" +) +) +on &283 +) +*455 (Wire +uid 5962,0 +shape (OrthoPolyLine +uid 5963,0 +va (VaSet +vasetType 3 +) +xt "40750,55000,126250,61000" +pts [ +"126250,61000" +"71000,61000" +"71000,55000" +"40750,55000" +] +) +start &90 +end &55 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5964,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5965,0 +va (VaSet +) +xt "119250,60000,124850,61000" +st "config_started" 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+library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "IEEE" +unitName "STD_LOGIC_ARITH" +) +(DmPackageRef +library "ieee" +unitName "STD_LOGIC_UNSIGNED" +) +(DmPackageRef +library "fact_fad_lib" +unitName "fad_definitions" +) +(DmPackageRef +library "UNISIM" +unitName "VComponents" +) +(DmPackageRef +library "IEEE" +unitName "NUMERIC_STD" +) +(DmPackageRef +library "IEEE" +unitName "std_logic_signed" +) +] +instances [ +(Instance +name "I_main_data_generator" +duLibraryName "FACT_FAD_lib" +duName "data_generator" +elements [ +(GiElement +name "RAM_ADDR_WIDTH" +type "integer" +value "RAMADDRWIDTH64b" +) +] +mwi 0 +uid 1399,0 +) +(Instance +name "I_main_ethernet" +duLibraryName "FACT_FAD_lib" +duName "w5300_modul" +elements [ +(GiElement +name "RAM_ADDR_WIDTH" +type "integer" +value "RAMADDRWIDTH64b+2" +) +] +mwi 0 +uid 1606,0 +) +(Instance +name "I_main_ext_trigger" +duLibraryName "FACT_FAD_LIB" +duName "trigger_counter" +elements [ +] +mwi 0 +uid 1768,0 +) +(Instance +name "I_main_memory_manager" +duLibraryName "FACT_FAD_lib" +duName "memory_manager" +elements [ +(GiElement +name "RAM_ADDR_WIDTH_64B" +type "integer" +value "RAMADDRWIDTH64b" +) +(GiElement +name "RAM_ADDR_WIDTH_16B" +type "integer" +value "RAMADDRWIDTH64b+2" +) +] +mwi 0 +uid 2311,0 +) +(Instance +name "I_main_clock_gen" +duLibraryName "FACT_FAD_lib" +duName "clock_generator" +elements [ +] +mwi 0 +uid 4194,0 +) +(Instance +name "I_main_drs_pulser" +duLibraryName "FACT_FAD_LIB" +duName "drs_pulser" +elements [ +] +mwi 0 +uid 4903,0 +) +(Instance +name "I_main_control_unit" +duLibraryName "FACT_FAD_lib" +duName "control_unit" +elements [ +] +mwi 0 +uid 5072,0 +) +(Instance +name "I_main_adc_buffer" +duLibraryName "FACT_FAD_lib" +duName "adc_buffer" +elements [ +] +mwi 0 +uid 5678,0 +) +(Instance +name "I_main_SPI_interface" +duLibraryName "FACT_FAD_lib" +duName "spi_interface" +elements [ +] +mwi 0 +uid 5793,0 +) +(Instance +name "I5" +duLibraryName "moduleware" +duName "and" +elements [ +] +mwi 1 +uid 6529,0 +) +(Instance +name "U_4" +duLibraryName "FACT_FAD_lib" +duName "dataRAM_64b_16b_width14_5" +elements [ +] +mwi 0 +uid 8277,0 +) +(Instance +name "U_0" +duLibraryName "moduleware" +duName "mux" +elements [ +] +mwi 1 +uid 8562,0 +) +] +libraryRefs [ +"ieee" +"fact_fad_lib" +"UNISIM" +] +) +version "29.1" +appVersion "2009.2 (Build 10)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main" +) +(vvPair +variable "d_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main" +) +(vvPair +variable "date" +value "12.07.2010" +) +(vvPair +variable "day" +value "Mo" +) +(vvPair +variable "day_long" +value "Montag" +) +(vvPair +variable "dd" +value "12" +) +(vvPair +variable "entity_name" +value "FAD_main" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "TU-CC4900F8C7D2" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_PrecisionSynthesisDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "07" +) +(vvPair +variable "module_name" +value "FAD_main" +) +(vvPair +variable "month" +value "Jul" +) +(vvPair +variable "month_long" +value "Juli" +) +(vvPair +variable "p" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "14:21:30" +) +(vvPair +variable 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"142500,59500,147000,60500" +st "addr : (9:0)" +ju 2 +blo "147000,60300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "addr" +t "std_logic_vector" +b "(9 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +) +) +) +*71 (CptPort +uid 1554,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 1555,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,60625,148750,61375" +) +tg (CPTG +uid 1556,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1557,0 +va (VaSet +) +xt "142200,60500,147000,61500" +st "data : (15:0)" +ju 2 +blo "147000,61300" +) +) +thePort (LogicalPort +m 2 +decl (Decl +n "data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 4 +suid 4,0 +) +) +) +*72 (CptPort +uid 1558,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1559,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,52625,148750,53375" +) +tg (CPTG +uid 1560,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1561,0 +va (VaSet +) +xt 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"write_length" +t "std_logic_vector" +b "(16 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 10 +suid 10,0 +) +) +) +*77 (CptPort +uid 1582,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1583,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,70625,127000,71375" +) +tg (CPTG +uid 1584,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1585,0 +va (VaSet +) +xt "128000,70500,144300,71500" +st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)" +blo "128000,71300" +) +) +thePort (LogicalPort +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 11 +suid 11,0 +) +) +) +*78 (CptPort +uid 1586,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1587,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,54625,127000,55375" +) +tg (CPTG +uid 1588,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1589,0 +va (VaSet +) +xt "128000,54500,134500,55500" +st "ram_data : (15:0)" +blo "128000,55300" +) +) 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"126250,81625,127000,82375" +) +tg (CPTG +uid 5942,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5943,0 +va (VaSet +) +xt "128000,81500,133300,82500" +st "config_wr_en" +blo "128000,82300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_wr_en" +t "std_logic" +o 25 +suid 28,0 +i "'0'" +) +) +) +*92 (CptPort +uid 5944,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5945,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,59625,127000,60375" +) +tg (CPTG +uid 5946,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5947,0 +va (VaSet +) +xt "128000,59500,132600,60500" +st "new_config" +blo "128000,60300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "new_config" +t "std_logic" +o 21 +suid 29,0 +i "'0'" +) +) +) +*93 (CptPort +uid 5970,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5971,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,82625,127000,83375" +) +tg (CPTG +uid 5972,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5973,0 +va (VaSet +) +xt "128000,82500,133200,83500" +st "config_rd_en" +blo "128000,83300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_rd_en" +t "std_logic" +o 26 +suid 30,0 +i "'0'" +) +) +) +*94 (CptPort +uid 6356,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6357,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,74625,148750,75375" +) +tg (CPTG +uid 6358,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6359,0 +va (VaSet +) +xt "144000,74500,147000,75500" +st "denable" +ju 2 +blo "147000,75300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "denable" +t "std_logic" +eolc "-- default domino wave off" +posAdd 0 +o 28 +suid 31,0 +i "'0'" +) +) +) +*95 (CptPort +uid 6446,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6447,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,75625,148750,76375" +) +tg (CPTG +uid 6448,0 +ps "CptPortTextPlaceStrategy" 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"CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*97 (Text +uid 1609,0 +va (VaSet +font "Arial,8,1" +) +xt "126700,87000,132900,88000" +st "FACT_FAD_lib" +blo "126700,87800" +tm "BdLibraryNameMgr" +) +*98 (Text +uid 1610,0 +va (VaSet +font "Arial,8,1" +) +xt "126700,88000,132400,89000" +st "w5300_modul" +blo "126700,88800" +tm "CptNameMgr" +) +*99 (Text +uid 1611,0 +va (VaSet +font "Arial,8,1" +) +xt "126700,89000,133400,90000" +st "I_main_ethernet" +blo "126700,89800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1612,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1613,0 +text (MLText +uid 1614,0 +va (VaSet +font "Courier New,8,0" +) +xt "127000,50200,154500,51000" +st "RAM_ADDR_WIDTH = RAMADDRWIDTH64b+2 ( integer ) " +) +header "" +) +elements [ +(GiElement +name "RAM_ADDR_WIDTH" +type "integer" +value "RAMADDRWIDTH64b+2" +) +] +) +viewicon (ZoomableIcon +uid 1615,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "127250,85250,128750,86750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*100 (Net +uid 1680,0 +decl (Decl +n "crate_id" +t "std_logic_vector" +b "(1 downto 0)" +o 9 +suid 30,0 +) +declText (MLText +uid 1681,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,24600,-56500,25400" +st "crate_id : std_logic_vector(1 downto 0) +" +) +) +*101 (SaComponent +uid 1768,0 +optionalChildren [ +*102 (CptPort +uid 1760,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1761,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-7000,63625,-6250,64375" +) +tg (CPTG +uid 1762,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1763,0 +va (VaSet +) +xt "-14800,63500,-8000,64500" +st "trigger_id : (47:0)" +ju 2 +blo "-8000,64300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "trigger_id" +t "std_logic_vector" +b "(47 downto 0)" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*103 (CptPort +uid 1764,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1765,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-18750,63625,-18000,64375" +) +tg (CPTG +uid 1766,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1767,0 +va (VaSet +) +xt "-17000,63500,-14200,64500" +st "trigger" +blo "-17000,64300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "trigger" +t "std_logic" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +) +) +) +*104 (CptPort +uid 6207,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6208,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-18750,62625,-18000,63375" +) +tg (CPTG +uid 6209,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6210,0 +va (VaSet +) +xt "-17000,62500,-15700,63500" +st "clk" +blo "-17000,63300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "clk" +t "std_logic" +o 3 +suid 3,0 +) +) +) +] +shape (Rectangle +uid 1769,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "-18000,62000,-7000,67000" +) +oxt "32000,2000,43000,12000" +ttg (MlTextGroup +uid 1770,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*105 (Text +uid 1771,0 +va (VaSet +font "Arial,8,1" +) +xt "-6300,65000,300,66000" +st "FACT_FAD_LIB" +blo "-6300,65800" +tm "BdLibraryNameMgr" +) +*106 (Text +uid 1772,0 +va (VaSet +font "Arial,8,1" +) +xt "-6300,66000,300,67000" +st "trigger_counter" +blo "-6300,66800" +tm "CptNameMgr" +) +*107 (Text +uid 1773,0 +va (VaSet +font "Arial,8,1" +) +xt "-6300,67000,1300,68000" +st "I_main_ext_trigger" +blo "-6300,67800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1774,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1775,0 +text (MLText +uid 1776,0 +va (VaSet +font "Courier New,8,0" +) +xt "-18000,61000,-18000,61000" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 1777,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "-17750,65250,-16250,66750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sIVOD 1 +) +archFileType "UNKNOWN" +) +*108 (Net +uid 1981,0 +lang 2 +decl (Decl +n "trigger_id" +t "std_logic_vector" +b "(47 downto 0)" +preAdd 0 +posAdd 0 +o 72 +suid 34,0 +) +declText (MLText +uid 1982,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,79400,-52500,80200" +st "SIGNAL trigger_id : std_logic_vector(47 downto 0) +" +) +) +*109 (Net +uid 2297,0 +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAMADDRWIDTH64b-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 64 +suid 36,0 +) +declText (MLText +uid 2298,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,73000,-45000,73800" +st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) +" +) +) +*110 (SaComponent +uid 2311,0 +optionalChildren [ +*111 (CptPort +uid 2307,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2308,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,69625,72000,70375" +) +tg (CPTG +uid 2309,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2310,0 +va (VaSet +font "arial,8,0" +) +xt "73000,69500,91400,70500" +st "ram_start_addr : (RAM_ADDR_WIDTH_64B-1:0)" +blo "73000,70300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH_64B-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 18 +suid 1,0 +i "(others => '0')" +) +) +) +*112 (CptPort +uid 2351,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2352,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,67625,72000,68375" +) +tg (CPTG +uid 2353,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2354,0 +va (VaSet +font "arial,8,0" +) +xt "73000,67500,74300,68500" +st "clk" +blo "73000,68300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "clk" +t "std_logic" +o 1 +suid 2,0 +) +) +) +*113 (CptPort +uid 2361,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2362,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,76625,72000,77375" +) +tg (CPTG +uid 2363,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2364,0 +va (VaSet +font "arial,8,0" +) +xt "73000,76500,78100,77500" +st "config_ready" +blo "73000,77300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "config_ready" +t "std_logic" +o 6 +suid 5,0 +i "'0'" +) +) +) +*114 (CptPort +uid 2365,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2366,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,74625,72000,75375" +) +tg (CPTG +uid 2367,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2368,0 +va (VaSet +font "arial,8,0" +) +xt "73000,74500,77800,75500" +st "config_start" +blo "73000,75300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "config_start" +t "std_logic" +o 2 +suid 3,0 +) +) +) +*115 (CptPort +uid 2369,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2370,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,70625,72000,71375" +) +tg (CPTG +uid 2371,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2372,0 +va (VaSet +font "arial,8,0" +) +xt "73000,70500,78300,71500" +st "ram_write_ea" +blo "73000,71300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "ram_write_ea" +t "std_logic" +o 5 +suid 4,0 +i "'0'" +) +) +) +*116 (CptPort +uid 2373,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2374,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,71625,72000,72375" +) +tg (CPTG +uid 2375,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2376,0 +va (VaSet +font "arial,8,0" +) +xt "73000,71500,79300,72500" +st "ram_write_ready" +blo "73000,72300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "ram_write_ready" +t "std_logic" +o 3 +suid 12,0 +) +) +) +*117 (CptPort +uid 2377,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2378,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,77625,72000,78375" +) +tg (CPTG +uid 2379,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2380,0 +va (VaSet +font "arial,8,0" +) +xt "73000,77500,76000,78500" +st "roi_max" +blo "73000,78300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "roi_max" +t "roi_max_type" +posAdd 0 +o 8 +suid 14,0 +i "(others => conv_std_logic_vector (0, 11))" +) +) +) +*118 (CptPort +uid 2381,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2382,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,67625,103750,68375" +) +tg (CPTG +uid 2383,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2384,0 +va (VaSet +font "arial,8,0" +) +xt "98600,67500,102000,68500" +st "wiz_busy" +ju 2 +blo "102000,68300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "wiz_busy" +t "std_logic" +o 16 +suid 13,0 +) +) +) +*119 (CptPort +uid 2385,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2386,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,71625,103750,72375" +) +tg (CPTG +uid 2387,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2388,0 +va (VaSet +font "arial,8,0" +) +xt "90200,71500,102000,72500" +st "wiz_number_of_channels : (3:0)" +ju 2 +blo "102000,72300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_number_of_channels" +t "std_logic_vector" +b "(3 downto 0)" +o 12 +suid 6,0 +i "(others => '0')" +) +) +) +*120 (CptPort +uid 2389,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2390,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,70625,103750,71375" +) +tg (CPTG +uid 2391,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2392,0 +va (VaSet +font "arial,8,0" +) +xt "82100,70500,102000,71500" +st "wiz_ram_start_addr : (RAM_ADDR_WIDTH_16B-1:0)" +ju 2 +blo "102000,71300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH_16B-1 downto 0)" +preAdd 0 +o 10 +suid 7,0 +i "(others => '0')" +) +) +) +*121 (CptPort +uid 2393,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2394,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,68625,103750,69375" +) +tg (CPTG +uid 2395,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2396,0 +va (VaSet +font "arial,8,0" +) +xt "96900,68500,102000,69500" +st "wiz_write_ea" +ju 2 +blo "102000,69300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_ea" +t "std_logic" +o 13 +suid 8,0 +i "'0'" +) +) +) +*122 (CptPort +uid 2397,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2398,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,72625,103750,73375" +) +tg (CPTG +uid 2399,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2400,0 +va (VaSet +font "arial,8,0" +) +xt "96500,72500,102000,73500" +st "wiz_write_end" +ju 2 +blo "102000,73300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_end" +t "std_logic" +o 15 +suid 9,0 +i "'0'" +) +) +) +*123 (CptPort +uid 2401,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2402,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,73625,103750,74375" +) +tg (CPTG +uid 2403,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2404,0 +va (VaSet +font "arial,8,0" +) +xt "95400,73500,102000,74500" +st "wiz_write_header" +ju 2 +blo "102000,74300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_header" +t "std_logic" +o 14 +suid 10,0 +i "'0'" +) +) +) +*124 (CptPort +uid 2405,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2406,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,69625,103750,70375" +) +tg (CPTG +uid 2407,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2408,0 +va (VaSet +font "arial,8,0" +) +xt "92600,69500,102000,70500" +st "wiz_write_length : (16:0)" +ju 2 +blo "102000,70300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_length" +t "std_logic_vector" +b "(16 downto 0)" +o 11 +suid 11,0 +i "(others => '0')" +) +) +) +*125 (CptPort +uid 2454,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2455,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,84625,72000,85375" +) +tg (CPTG +uid 2456,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2457,0 +va (VaSet +font "arial,8,0" +) +xt "73000,84500,76400,85500" +st "roi_array" +blo "73000,85300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "roi_array" +t "roi_array_type" +o 4 +suid 15,0 +) +) +) +*126 (CptPort +uid 2628,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2629,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,78625,72000,79375" +) +tg (CPTG +uid 2630,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2631,0 +va (VaSet +font "arial,8,0" +) +xt "73000,78500,82100,79500" +st "package_length : (15:0)" +blo "73000,79300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "package_length" +t "std_logic_vector" +b "(15 downto 0)" +o 9 +suid 18,0 +i "(others => '0')" +) +) +) +*127 (CptPort +uid 5991,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5992,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,75625,72000,76375" +) +tg (CPTG +uid 5993,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5994,0 +va (VaSet +font "arial,8,0" +) +xt "73000,75500,78600,76500" +st "config_started" +blo "73000,76300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "config_started" +t "std_logic" +o 7 +suid 21,0 +i "'0'" +) +) +) +*128 (CptPort +uid 8410,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8411,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,74625,103750,75375" +) +tg (CPTG +uid 8412,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8413,0 +va (VaSet +font "arial,8,0" +) +xt "99000,74500,102000,75500" +st "wiz_ack" +ju 2 +blo "102000,75300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "wiz_ack" +t "std_logic" +o 17 +suid 22,0 +) +) +) +] +shape (Rectangle +uid 2312,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "72000,67000,103000,87000" +) +oxt "15000,6000,23000,16000" +ttg (MlTextGroup +uid 2313,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*129 (Text +uid 2314,0 +va (VaSet +font "arial,8,1" +) +xt "72350,87000,78550,88000" +st "FACT_FAD_lib" +blo "72350,87800" +tm "BdLibraryNameMgr" +) +*130 (Text +uid 2315,0 +va (VaSet +font "arial,8,1" +) +xt "72350,88000,79650,89000" +st "memory_manager" +blo "72350,88800" +tm "CptNameMgr" +) +*131 (Text +uid 2316,0 +va (VaSet +font "arial,8,1" +) +xt "72350,89000,82850,90000" +st "I_main_memory_manager" +blo "72350,89800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 2317,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 2318,0 +text (MLText +uid 2319,0 +va (VaSet +font "Courier New,8,0" +) +xt "72000,65400,101500,67000" +st "RAM_ADDR_WIDTH_64B = RAMADDRWIDTH64b ( integer ) +RAM_ADDR_WIDTH_16B = RAMADDRWIDTH64b+2 ( integer ) " +) +header "" +) +elements [ +(GiElement +name "RAM_ADDR_WIDTH_64B" +type "integer" +value "RAMADDRWIDTH64b" +) +(GiElement +name "RAM_ADDR_WIDTH_16B" +type "integer" +value "RAMADDRWIDTH64b+2" +) +] +) +viewicon (ZoomableIcon +uid 2320,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "72250,85250,73750,86750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*132 (Net +uid 2468,0 +lang 2 +decl (Decl +n "wiz_busy" +t "std_logic" +o 73 +suid 38,0 +) +declText (MLText +uid 2469,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,81000,-62500,81800" +st "SIGNAL wiz_busy : std_logic +" +) +) +*133 (Net +uid 2474,0 +lang 2 +decl (Decl +n "wiz_write_ea" +t "std_logic" +o 76 +suid 39,0 +i "'0'" +) +declText (MLText +uid 2475,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,83400,-41500,84200" +st "SIGNAL wiz_write_ea : std_logic := '0' +" +) +) +*134 (Net +uid 2480,0 +lang 2 +decl (Decl +n "wiz_write_length" +t "std_logic_vector" +b "(16 downto 0)" +o 79 +suid 40,0 +i "(others => '0')" +) +declText (MLText +uid 2481,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,85800,-35500,86600" +st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0') +" +) +) +*135 (Net +uid 2486,0 +lang 2 +decl (Decl +n "wiz_ram_start_addr" +t "std_logic_vector" +b "(RAMADDRWIDTH64b+1 DOWNTO 0)" +preAdd 0 +o 75 +suid 41,0 +i "(others => '0')" +) +declText (MLText +uid 2487,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,82600,-35500,83400" +st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0') +" +) +) +*136 (Net +uid 2492,0 +lang 2 +decl (Decl +n "wiz_number_of_channels" +t "std_logic_vector" +b "(3 downto 0)" +o 74 +suid 42,0 +i "(others => '0')" +) +declText (MLText +uid 2493,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,81800,-35500,82600" +st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0') +" +) +) +*137 (Net +uid 2498,0 +lang 2 +decl (Decl +n "wiz_write_end" +t "std_logic" +o 77 +suid 43,0 +i "'0'" +) +declText (MLText +uid 2499,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,84200,-41500,85000" +st "SIGNAL wiz_write_end : std_logic := '0' +" +) +) +*138 (Net +uid 2504,0 +lang 2 +decl (Decl +n "wiz_write_header" +t "std_logic" +o 78 +suid 44,0 +i "'0'" +) +declText (MLText +uid 2505,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,85000,-41500,85800" +st "SIGNAL wiz_write_header : std_logic := '0' +" +) +) +*139 (Net +uid 2574,0 +decl (Decl +n "ram_write_ea" +t "std_logic" +o 65 +suid 48,0 +) +declText (MLText +uid 2575,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,73800,-62500,74600" +st "SIGNAL ram_write_ea : std_logic +" +) +) +*140 (Net +uid 2580,0 +decl (Decl +n "ram_write_ready" +t "std_logic" +o 66 +suid 49,0 +i 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8503,0 +va (VaSet +) +xt "83800,109500,91000,110500" +st "drs_address : (3:0)" +ju 2 +blo "91000,110300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 11 +suid 13,0 +) +) +) +*228 (CptPort +uid 8504,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8505,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92000,110625,92750,111375" +) +tg (CPTG +uid 8506,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8507,0 +va (VaSet +) +xt "83800,110500,91000,111500" +st "drs_address_mode" +ju 2 +blo "91000,111300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 12 +suid 14,0 +) +) +) +] +shape (Rectangle +uid 5073,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "74000,99000,92000,112000" +) +oxt "15000,13000,33000,26000" +ttg (MlTextGroup +uid 5074,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*229 (Text +uid 5075,0 +va (VaSet +font "Arial,8,1" +) +xt "74200,112000,80400,113000" +st "FACT_FAD_lib" +blo "74200,112800" +tm "BdLibraryNameMgr" +) +*230 (Text +uid 5076,0 +va (VaSet +font "Arial,8,1" +) +xt "74200,113000,79600,114000" +st "control_unit" +blo "74200,113800" +tm "CptNameMgr" +) +*231 (Text +uid 5077,0 +va (VaSet +font "Arial,8,1" +) +xt "74200,114000,82400,115000" +st "I_main_control_unit" +blo "74200,114800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 5078,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 5079,0 +text (MLText +uid 5080,0 +va (VaSet +font "Courier New,8,0" +) +xt "59000,98800,59000,98800" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 5081,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "74250,110250,75750,111750" +iconName "BlockDiagram.png" +iconMaskName "BlockDiagram.msk" +ftype 1 +) +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*232 (Net +uid 5088,0 +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 36 +suid 119,0 +) +declText (MLText +uid 5089,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,48200,-53000,49000" +st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0) +" +) +) +*233 (Net +uid 5096,0 +decl (Decl +n "config_data_valid" +t "std_logic" +o 39 +suid 120,0 +) +declText (MLText +uid 5097,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,50600,-62500,51400" +st "SIGNAL config_data_valid : std_logic +" +) +) +*234 (Net +uid 5104,0 +decl (Decl +n "config_busy" +t "std_logic" +o 37 +suid 121,0 +) +declText (MLText +uid 5105,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,49000,-62500,49800" +st "SIGNAL config_busy : std_logic +" +) +) +*235 (Net +uid 5112,0 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 38 +suid 122,0 +) +declText (MLText +uid 5113,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,49800,-52500,50600" +st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0) +" +) +) +*236 (Net +uid 5120,0 +decl (Decl +n "config_wr_en" +t "std_logic" +o 51 +suid 123,0 +) +declText (MLText +uid 5121,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,60200,-62500,61000" +st "SIGNAL config_wr_en : std_logic +" +) +) +*237 (Net +uid 5128,0 +decl (Decl +n "config_rd_en" +t "std_logic" +o 40 +suid 124,0 +) +declText (MLText +uid 5129,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,51400,-62500,52200" +st "SIGNAL config_rd_en : std_logic +" +) +) +*238 (Net +uid 5144,0 +decl (Decl +n "dac_array" +t "dac_array_type" +o 52 +suid 126,0 +) +declText (MLText +uid 5145,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,61000,-60000,61800" +st "SIGNAL dac_array : dac_array_type +" +) +) +*239 (Net +uid 5194,0 +decl (Decl +n "config_start_cm" +t "std_logic" +o 45 +suid 131,0 +) +declText (MLText +uid 5195,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,55400,-62500,56200" +st "SIGNAL config_start_cm : std_logic +" +) +) +*240 (Net +uid 5196,0 +decl (Decl +n "config_ready_cm" +t "std_logic" +o 42 +suid 132,0 +) +declText (MLText +uid 5197,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,53000,-62500,53800" +st "SIGNAL config_ready_cm : std_logic +" +) +) +*241 (Net +uid 5220,0 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 DOWNTO 0)" +posAdd 0 +o 21 +suid 133,0 +i "(OTHERS => '0')" +) +declText (MLText +uid 5221,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,34200,-39000,35000" +st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') +" +) +) +*242 (Net +uid 5279,0 +decl (Decl +n "s_trigger" +t "std_logic" +o 69 +suid 134,0 +i "'0'" +) +declText (MLText +uid 5280,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,77000,-41500,77800" +st "SIGNAL s_trigger : std_logic := '0' +" +) +) +*243 (Net +uid 5472,0 +decl (Decl +n "sensor_ready" +t "std_logic" +o 71 +suid 140,0 +) +declText (MLText +uid 5473,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,78600,-62500,79400" +st "SIGNAL sensor_ready : std_logic +" +) +) +*244 (Net +uid 5478,0 +decl (Decl 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+) +*248 (SaComponent +uid 5678,0 +optionalChildren [ +*249 (CptPort +uid 5658,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5659,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-18750,75625,-18000,76375" +) +tg (CPTG +uid 5660,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5661,0 +va (VaSet +font "arial,8,0" +) +xt "-17000,75500,-11100,76500" +st "adc_data_array" +blo "-17000,76300" +) +) +thePort (LogicalPort +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 2 +suid 5,0 +) +) +) +*250 (CptPort +uid 5662,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5663,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,75625,750,76375" +) +tg (CPTG +uid 5664,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5665,0 +va (VaSet +font "arial,8,0" +) +xt "-8100,75500,-1000,76500" +st "adc_data_array_int" +ju 2 +blo "-1000,76300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "adc_data_array_int" +t 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DOWNTO 0)" +o 3 +suid 8,0 +) +) +) +*253 (CptPort +uid 5674,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5675,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-18750,73625,-18000,74375" +) +tg (CPTG +uid 5676,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5677,0 +va (VaSet +font "arial,8,0" +) +xt "-17000,73500,-14500,74500" +st "clk_ps" +blo "-17000,74300" +) +) +thePort (LogicalPort +lang 10 +decl (Decl +n "clk_ps" +t "std_logic" +o 1 +suid 9,0 +) +) +) +] +shape (Rectangle +uid 5679,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "-18000,73000,0,80000" +) +oxt "15000,6000,23000,11000" +ttg (MlTextGroup +uid 5680,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*254 (Text +uid 5681,0 +va (VaSet +font "arial,8,1" +) +xt "900,77500,7100,78500" +st "FACT_FAD_lib" +blo "900,78300" +tm "BdLibraryNameMgr" +) +*255 (Text +uid 5682,0 +va (VaSet +font "arial,8,1" +) +xt "900,78500,5700,79500" +st "adc_buffer" +blo "900,79300" +tm "CptNameMgr" +) +*256 (Text +uid 5683,0 +va (VaSet +font "arial,8,1" +) +xt "900,79500,8500,80500" +st "I_main_adc_buffer" +blo "900,80300" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 5684,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 5685,0 +text (MLText +uid 5686,0 +va (VaSet +font "Courier New,8,0" +) +xt "-38000,73300,-38000,73300" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 5687,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "-17750,78250,-16250,79750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*257 (Net +uid 5743,0 +decl (Decl +n "config_start_spi" +t "std_logic" +o 46 +suid 149,0 +i "'0'" +) +declText (MLText +uid 5744,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,56200,-41500,57000" +st "SIGNAL config_start_spi : std_logic := '0' +" +) +) +*258 (SaComponent +uid 5793,0 +optionalChildren [ +*259 (CptPort +uid 5753,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5754,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "20250,106625,21000,107375" +) +tg (CPTG +uid 5755,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5756,0 +va (VaSet +) +xt "22000,106500,23700,107500" +st "sclk" +blo "22000,107300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sclk" +t "std_logic" +o 8 +suid 1,0 +) +) +) +*260 (CptPort +uid 5761,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5762,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37000,108625,37750,109375" +) +tg (CPTG +uid 5763,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5764,0 +va (VaSet +) +xt "32300,108500,36000,109500" +st "dac_array" +ju 2 +blo "36000,109300" +) +) +thePort (LogicalPort +decl (Decl +n "dac_array" +t "dac_array_type" +o 3 +suid 10,0 +) +) +) +*261 (CptPort +uid 5765,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5766,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37000,106625,37750,107375" +) +tg (CPTG +uid 5767,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5768,0 +va (VaSet +) +xt "30900,106500,36000,107500" +st "config_ready" +ju 2 +blo "36000,107300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_ready" +t "std_logic" +o 4 +suid 11,0 +) +) +) +*262 (CptPort +uid 5769,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5770,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37000,104625,37750,105375" +) +tg (CPTG +uid 5771,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5772,0 +va (VaSet +) +xt "31200,104500,36000,105500" +st "config_start" +ju 2 +blo "36000,105300" +) +) +thePort (LogicalPort +decl (Decl +n "config_start" +t "std_logic" +o 2 +suid 12,0 +) +) +) +*263 (CptPort +uid 5773,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5774,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) 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"11250,75000,18350,76000" +st "adc_data_array_int" +blo "11250,75800" +tm "WireNameMgr" +) +) +on &247 +) +*425 (Wire +uid 5634,0 +shape (OrthoPolyLine +uid 5635,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "750,77000,18250,77000" +pts [ +"18250,77000" +"750,77000" +] +) +start &38 +end &251 +sat 32 +eat 32 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 5638,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5639,0 +va (VaSet +) +xt "11250,76000,16750,77000" +st "adc_otr : (3:0)" +blo "11250,76800" +tm "WireNameMgr" +) +) +on &246 +) +*426 (Wire +uid 5646,0 +shape (OrthoPolyLine +uid 5647,0 +va (VaSet +vasetType 3 +lineColor "49152,0,0" +) +xt "-26000,74000,-18750,74000" +pts [ +"-26000,74000" +"-18750,74000" +] +) +end &253 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5652,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5653,0 +va (VaSet +) +xt "-25000,73000,-20500,74000" +st "CLK_25_PS" +blo "-25000,73800" +tm "WireNameMgr" +) +) +on &162 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"7000,60000,12400,61000" +st "dwrite_enable" +blo "7000,60800" +tm "WireNameMgr" +) +) +on &291 +) +*447 (Wire +uid 8416,0 +shape (OrthoPolyLine +uid 8417,0 +va (VaSet +vasetType 3 +) +xt "103750,75000,126250,75000" +pts [ +"103750,75000" +"126250,75000" +] +) +start &128 +end &96 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 8418,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8419,0 +va (VaSet +) +xt "104000,74000,107000,75000" +st "wiz_ack" +blo "104000,74800" +tm "WireNameMgr" +) +) +on &322 +) +*448 (Wire +uid 8510,0 +shape (OrthoPolyLine +uid 8511,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "92750,110000,102000,110000" +pts [ +"92750,110000" +"102000,110000" +] +) +start &227 +sat 32 +eat 16 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 8514,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8515,0 +va (VaSet +) +xt "94000,109000,101200,110000" +st "drs_address : (3:0)" +blo "94000,109800" +tm "WireNameMgr" +) +) +on &323 +) +*449 (Wire +uid 8518,0 +shape (OrthoPolyLine +uid 8519,0 +va (VaSet +vasetType 3 +) +xt "92750,111000,102000,111000" +pts [ +"92750,111000" +"102000,111000" +] +) +start &228 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 8522,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8523,0 +va (VaSet +) +xt "94000,110000,101200,111000" +st "drs_address_mode" +blo "94000,110800" +tm "WireNameMgr" +) +) +on &324 +) +*450 (Wire +uid 8577,0 +shape (OrthoPolyLine +uid 8578,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "7000,57000,18250,57000" +pts [ +"18250,57000" +"7000,57000" +] +) +start &39 +sat 32 +eat 16 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 8581,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8582,0 +va (VaSet +) +xt "8000,56000,18400,57000" +st "drs_channel_internal : (3:0)" +blo "8000,56800" +tm "WireNameMgr" +) +) +on &346 +) +*451 (Wire +uid 8587,0 +shape (OrthoPolyLine +uid 8588,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "-29000,101000,-20000,101000" +pts [ +"-20000,101000" +"-29000,101000" +] +) +end &326 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 8591,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8592,0 +va (VaSet +) +xt "-29000,100000,-20800,101000" +st "drs_channel_internal" +blo "-29000,100800" +tm "WireNameMgr" +) +) +on &346 +) +*452 (Wire +uid 8595,0 +shape (OrthoPolyLine +uid 8596,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "-29000,99000,-20000,99000" +pts [ +"-20000,99000" +"-29000,99000" +] +) +end &331 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 8599,0 +ps "ConnStartEndStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8600,0 +va (VaSet +) +xt "-29000,98000,-24000,99000" +st "drs_address" +blo "-29000,98800" +tm "WireNameMgr" +) +) +on &323 +) +*453 (Wire +uid 8603,0 +shape (OrthoPolyLine +uid 8604,0 +va (VaSet +vasetType 3 +) +xt "-31000,103000,-20000,107000" +pts [ +"-20000,107000" +"-31000,107000" +"-31000,103000" +] +) +end &333 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 8607,0 +ps "ConnStartEndStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8608,0 +va (VaSet +) +xt "-29000,106000,-21800,107000" +st "drs_address_mode" +blo "-29000,106800" +tm "WireNameMgr" +) +) +on &324 +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *454 (PackageList +uid 41,0 +stg "VerticalLayoutStrategy" +textVec [ +*455 (Text +uid 42,0 +va (VaSet +font "arial,8,1" +) +xt "-87000,1000,-81600,2000" +st "Package List" +blo "-87000,1800" +) +*456 (MLText +uid 43,0 +va (VaSet +) +xt "-87000,2000,-72600,14000" +st "library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use ieee.STD_LOGIC_UNSIGNED.all; + +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + +library UNISIM; +use UNISIM.VComponents.all; +USE IEEE.NUMERIC_STD.all; +USE IEEE.std_logic_signed.all;" +tm "PackageList" +) +] +) +compDirBlock (MlTextGroup +uid 44,0 +stg "VerticalLayoutStrategy" +textVec [ +*457 (Text +uid 45,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "20000,0,28100,1000" +st "Compiler Directives" +blo "20000,800" +) +*458 (Text +uid 46,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "20000,1000,29600,2000" +st "Pre-module directives:" +blo "20000,1800" +) +*459 (MLText +uid 47,0 +va (VaSet +isHidden 1 +) +xt "20000,2000,27500,4000" +st "`resetall +`timescale 1ns/10ps" +tm "BdCompilerDirectivesTextMgr" +) +*460 (Text +uid 48,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "20000,4000,30100,5000" +st "Post-module directives:" +blo "20000,4800" +) +*461 (MLText +uid 49,0 +va (VaSet +isHidden 1 +) +xt "20000,0,20000,0" +tm "BdCompilerDirectivesTextMgr" +) +*462 (Text +uid 50,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "20000,5000,29900,6000" +st "End-module directives:" +blo "20000,5800" +) +*463 (MLText +uid 51,0 +va (VaSet +isHidden 1 +) +xt "20000,6000,20000,6000" +tm "BdCompilerDirectivesTextMgr" +) +] +associable 1 +) +windowSize "0,0,1281,1024" +viewArea "-73966,37109,33461,125703" +cachedDiagramExtent "-100999,0,162300,301700" +pageSetupInfo (PageSetupInfo +ptrCmd "eDocPrintPro,winspool," +fileName "eDocPort" +toPrinter 1 +colour 1 +xMargin 0 +yMargin 0 +paperWidth 1523 +paperHeight 1077 +windowsPaperWidth 1523 +windowsPaperHeight 1077 +paperType "A3" +windowsPaperName "A3" +windowsPaperType 8 +useAdjustTo 0 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +boundaryWidth 0 +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +hasePageBreakOrigin 1 +pageBreakOrigin "-73000,0" +lastUid 8614,0 +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +defaultBlk (Blk +shape (Rectangle +va (VaSet +vasetType 1 +fg "39936,56832,65280" +lineColor "0,0,32768" +lineWidth 2 +) +xt "0,0,8000,10000" +) +ttg (MlTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*464 (Text +va (VaSet +font "Arial,8,1" +) +xt "2200,3500,5800,4500" +st "" +blo "2200,4300" +tm "BdLibraryNameMgr" +) +*465 (Text +va (VaSet +font "Arial,8,1" +) +xt "2200,4500,5600,5500" +st "" +blo "2200,5300" +tm "BlkNameMgr" +) +*466 (Text +va (VaSet +font "Arial,8,1" +) +xt "2200,5500,4000,6500" +st "U_0" +blo "2200,6300" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +ps "EdgeToEdgeStrategy" +matrix (Matrix +text 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4234,0 +) +*534 (LeafLogPort +port (LogicalPort +decl (Decl +n "adc_otr_array" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 7 +suid 95,0 +) +) +uid 4262,0 +) +*535 (LeafLogPort +port (LogicalPort +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 6 +suid 96,0 +) +) +uid 4276,0 +) +*536 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "drs_clk_en" +t "std_logic" +o 54 +suid 97,0 +i "'0'" +) +) +uid 4563,0 +) +*537 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "drs_s_cell_array" +t "drs_s_cell_array_type" +o 57 +suid 98,0 +) +) +uid 4565,0 +) +*538 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "drs_read_s_cell" +t "std_logic" +o 55 +suid 100,0 +i "'0'" +) +) +uid 4569,0 +) +*539 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "drs_channel_id" +t "std_logic_vector" +b "(3 downto 0)" +o 19 +suid 109,0 +i "(others => '0')" +) +) +uid 4585,0 +) +*540 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "drs_dwrite" +t "std_logic" +o 20 +suid 110,0 +i "'1'" +) +) +uid 4587,0 +) +*541 (LeafLogPort +port (LogicalPort +decl (Decl +n "SROUT_in_0" +t "std_logic" +o 2 +suid 112,0 +) +) +uid 4733,0 +) +*542 (LeafLogPort +port (LogicalPort +decl (Decl +n "SROUT_in_1" +t "std_logic" +o 3 +suid 113,0 +) +) +uid 4735,0 +) +*543 (LeafLogPort +port (LogicalPort +decl (Decl +n "SROUT_in_2" +t "std_logic" +o 4 +suid 114,0 +) +) +uid 4737,0 +) +*544 (LeafLogPort +port (LogicalPort +decl (Decl +n "SROUT_in_3" +t "std_logic" +o 5 +suid 115,0 +) +) +uid 4739,0 +) +*545 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "drs_read_s_cell_ready" +t "std_logic" +o 56 +suid 116,0 +) +) +uid 4749,0 +) +*546 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "RSRLOAD" +t "std_logic" +o 14 +suid 117,0 +i "'0'" +) +) +uid 4974,0 +) +*547 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "SRCLK" +t "std_logic" +o 15 +suid 118,0 +i "'0'" +) +) +uid 4976,0 +) +*548 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 36 +suid 119,0 +) +) +uid 5198,0 +) +*549 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "config_data_valid" +t "std_logic" +o 39 +suid 120,0 +) +) +uid 5200,0 +) +*550 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "config_busy" +t "std_logic" +o 37 +suid 121,0 +) +) +uid 5202,0 +) +*551 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 38 +suid 122,0 +) +) +uid 5204,0 +) +*552 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "config_wr_en" +t "std_logic" +o 51 +suid 123,0 +) +) +uid 5206,0 +) +*553 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "config_rd_en" +t "std_logic" +o 40 +suid 124,0 +) +) +uid 5208,0 +) +*554 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "dac_array" +t "dac_array_type" +o 52 +suid 126,0 +) +) +uid 5210,0 +) +*555 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "config_start_cm" +t "std_logic" +o 45 +suid 131,0 +) +) +uid 5212,0 +) +*556 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "config_ready_cm" +t "std_logic" +o 42 +suid 132,0 +) +) +uid 5214,0 +) +*557 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 DOWNTO 0)" +posAdd 0 +o 21 +suid 133,0 +i "(OTHERS => '0')" +) +) +uid 5226,0 +) +*558 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "s_trigger" +t "std_logic" +o 69 +suid 134,0 +i "'0'" +) +) +uid 5285,0 +) +*559 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "sensor_ready" +t "std_logic" +o 71 +suid 140,0 +) +) +uid 5502,0 +) +*560 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "sensor_array" +t "sensor_array_type" +o 70 +suid 141,0 +) +) +uid 5504,0 +) +*561 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "config_ready_spi" +t "std_logic" +o 43 +suid 144,0 +) +) +uid 5600,0 +) +*562 (LeafLogPort +port (LogicalPort +lang 10 +m 4 +decl (Decl +n "adc_otr" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 34 +suid 146,0 +) +) +uid 5642,0 +) +*563 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "adc_data_array_int" +t "adc_data_array_type" +o 33 +suid 147,0 +) +) +uid 5644,0 +) +*564 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "config_start_spi" +t "std_logic" +o 46 +suid 149,0 +i "'0'" +) +) +uid 5751,0 +) +*565 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "sclk" +t "std_logic" +o 23 +suid 151,0 +) +) +uid 5867,0 +) +*566 (LeafLogPort +port (LogicalPort +m 2 +decl (Decl +n "sio" +t "std_logic" +preAdd 0 +posAdd 0 +o 30 +suid 152,0 +) +) +uid 5869,0 +) +*567 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "dac_cs" +t "std_logic" +o 17 +suid 153,0 +) +) +uid 5871,0 +) +*568 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "sensor_cs" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 24 +suid 154,0 +) +) +uid 5873,0 +) +*569 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "new_config" +t "std_logic" +o 60 +suid 155,0 +i "'0'" +) +) +uid 5966,0 +) +*570 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "config_started" +t "std_logic" +o 47 +suid 156,0 +) +) +uid 5968,0 +) +*571 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "config_started_spi" +t "std_logic" +o 50 +suid 159,0 +i "'0'" +) +) +uid 6022,0 +) +*572 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "config_started_cu" +t "std_logic" +o 48 +suid 160,0 +i "'0'" +) +) +uid 6024,0 +) +*573 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "config_started_mm" +t "std_logic" +o 49 +suid 161,0 +) +) +uid 6026,0 +) +*574 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "mosi" +t "std_logic" +o 22 +suid 162,0 +i "'0'" +) +) +uid 6172,0 +) +*575 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "denable" +t "std_logic" +eolc "-- default domino wave off" +posAdd 0 +o 18 +suid 166,0 +i "'0'" +) +) +uid 6374,0 +) +*576 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "dwrite_enable" +t "std_logic" +o 59 +suid 167,0 +i "'1'" +) +) +uid 6464,0 +) +*577 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "dwrite" +t "std_logic" +o 58 +suid 169,0 +i "'1'" +) +) +uid 6554,0 +) +*578 (LeafLogPort +port (LogicalPort +lang 2 +m 4 +decl (Decl +n "wiz_ack" +t "std_logic" +o 81 +suid 183,0 +) +) +uid 8420,0 +) +*579 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 82 +suid 184,0 +i "(others => '0')" +) +) +uid 8609,0 +) +*580 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 83 +suid 185,0 +) +) +uid 8611,0 +) +*581 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "drs_channel_internal" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 84 +suid 187,0 +i "(others => '0')" +) +) +uid 8613,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 67,0 +optionalChildren [ +*582 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *583 (MRCItem +litem &485 +pos 84 +dimension 20 +) +uid 69,0 +optionalChildren [ +*584 (MRCItem +litem &486 +pos 0 +dimension 20 +uid 70,0 +) +*585 (MRCItem +litem &487 +pos 1 +dimension 23 +uid 71,0 +) +*586 (MRCItem +litem &488 +pos 2 +hidden 1 +dimension 20 +uid 72,0 +) +*587 (MRCItem +litem &498 +pos 31 +dimension 20 +uid 517,0 +) +*588 (MRCItem +litem &499 +pos 32 +dimension 20 +uid 519,0 +) +*589 (MRCItem +litem &500 +pos 33 +dimension 20 +uid 521,0 +) +*590 (MRCItem +litem &501 +pos 34 +dimension 20 +uid 531,0 +) +*591 (MRCItem +litem &502 +pos 35 +dimension 20 +uid 533,0 +) +*592 (MRCItem +litem &503 +pos 0 +dimension 20 +uid 535,0 +) +*593 (MRCItem +litem &504 +pos 1 +dimension 20 +uid 537,0 +) +*594 (MRCItem +litem &505 +pos 2 +dimension 20 +uid 539,0 +) +*595 (MRCItem +litem &506 +pos 3 +dimension 20 +uid 541,0 +) +*596 (MRCItem +litem &507 +pos 4 +dimension 20 +uid 543,0 +) +*597 (MRCItem +litem &508 +pos 5 +dimension 20 +uid 547,0 +) +*598 (MRCItem +litem &509 +pos 6 +dimension 20 +uid 549,0 +) +*599 (MRCItem +litem &510 +pos 8 +dimension 20 +uid 1456,0 +) +*600 (MRCItem +litem &511 +pos 7 +dimension 20 +uid 1458,0 +) +*601 (MRCItem +litem &512 +pos 9 +dimension 20 +uid 1695,0 +) +*602 (MRCItem +litem &513 +pos 36 +dimension 20 +uid 1994,0 +) +*603 (MRCItem +litem &514 +pos 37 +dimension 20 +uid 2306,0 +) +*604 (MRCItem +litem &515 +pos 38 +dimension 20 +uid 2511,0 +) +*605 (MRCItem +litem &516 +pos 39 +dimension 20 +uid 2513,0 +) +*606 (MRCItem +litem &517 +pos 40 +dimension 20 +uid 2515,0 +) +*607 (MRCItem +litem &518 +pos 41 +dimension 20 +uid 2517,0 +) +*608 (MRCItem +litem &519 +pos 42 +dimension 20 +uid 2519,0 +) +*609 (MRCItem +litem &520 +pos 43 +dimension 20 +uid 2521,0 +) +*610 (MRCItem +litem &521 +pos 44 +dimension 20 +uid 2523,0 +) +*611 (MRCItem +litem &522 +pos 45 +dimension 20 +uid 2605,0 +) +*612 (MRCItem +litem &523 +pos 46 +dimension 20 +uid 2607,0 +) +*613 (MRCItem +litem &524 +pos 47 +dimension 20 +uid 2609,0 +) +*614 (MRCItem +litem &525 +pos 48 +dimension 20 +uid 2611,0 +) +*615 (MRCItem +litem &526 +pos 49 +dimension 20 +uid 2613,0 +) +*616 (MRCItem +litem &527 +pos 50 +dimension 20 +uid 2647,0 +) +*617 (MRCItem +litem &528 +pos 10 +dimension 20 +uid 2813,0 +) +*618 (MRCItem +litem &529 +pos 51 +dimension 20 +uid 2963,0 +) +*619 (MRCItem +litem &530 +pos 11 +dimension 20 +uid 3903,0 +) +*620 (MRCItem +litem &531 +pos 12 +dimension 20 +uid 4071,0 +) +*621 (MRCItem +litem &532 +pos 52 +dimension 20 +uid 4213,0 +) +*622 (MRCItem +litem &533 +pos 13 +dimension 20 +uid 4235,0 +) +*623 (MRCItem +litem &534 +pos 14 +dimension 20 +uid 4263,0 +) +*624 (MRCItem +litem &535 +pos 15 +dimension 20 +uid 4277,0 +) +*625 (MRCItem +litem &536 +pos 53 +dimension 20 +uid 4564,0 +) +*626 (MRCItem +litem &537 +pos 54 +dimension 20 +uid 4566,0 +) +*627 (MRCItem +litem &538 +pos 55 +dimension 20 +uid 4570,0 +) +*628 (MRCItem +litem &539 +pos 16 +dimension 20 +uid 4586,0 +) +*629 (MRCItem +litem &540 +pos 17 +dimension 20 +uid 4588,0 +) +*630 (MRCItem +litem &541 +pos 18 +dimension 20 +uid 4734,0 +) +*631 (MRCItem +litem &542 +pos 19 +dimension 20 +uid 4736,0 +) +*632 (MRCItem +litem &543 +pos 20 +dimension 20 +uid 4738,0 +) +*633 (MRCItem +litem &544 +pos 21 +dimension 20 +uid 4740,0 +) +*634 (MRCItem +litem &545 +pos 56 +dimension 20 +uid 4750,0 +) +*635 (MRCItem +litem &546 +pos 22 +dimension 20 +uid 4975,0 +) +*636 (MRCItem +litem &547 +pos 23 +dimension 20 +uid 4977,0 +) +*637 (MRCItem +litem &548 +pos 57 +dimension 20 +uid 5199,0 +) +*638 (MRCItem +litem &549 +pos 58 +dimension 20 +uid 5201,0 +) +*639 (MRCItem +litem &550 +pos 59 +dimension 20 +uid 5203,0 +) +*640 (MRCItem +litem &551 +pos 60 +dimension 20 +uid 5205,0 +) +*641 (MRCItem +litem &552 +pos 61 +dimension 20 +uid 5207,0 +) +*642 (MRCItem +litem &553 +pos 62 +dimension 20 +uid 5209,0 +) +*643 (MRCItem +litem &554 +pos 63 +dimension 20 +uid 5211,0 +) +*644 (MRCItem +litem &555 +pos 64 +dimension 20 +uid 5213,0 +) +*645 (MRCItem +litem &556 +pos 65 +dimension 20 +uid 5215,0 +) +*646 (MRCItem +litem &557 +pos 24 +dimension 20 +uid 5227,0 +) +*647 (MRCItem +litem &558 +pos 66 +dimension 20 +uid 5286,0 +) +*648 (MRCItem +litem &559 +pos 67 +dimension 20 +uid 5503,0 +) +*649 (MRCItem +litem &560 +pos 68 +dimension 20 +uid 5505,0 +) +*650 (MRCItem +litem &561 +pos 69 +dimension 20 +uid 5601,0 +) +*651 (MRCItem +litem &562 +pos 70 +dimension 20 +uid 5643,0 +) +*652 (MRCItem +litem &563 +pos 71 +dimension 20 +uid 5645,0 +) +*653 (MRCItem +litem &564 +pos 72 +dimension 20 +uid 5752,0 +) +*654 (MRCItem +litem &565 +pos 25 +dimension 20 +uid 5868,0 +) +*655 (MRCItem +litem &566 +pos 26 +dimension 20 +uid 5870,0 +) +*656 (MRCItem +litem &567 +pos 27 +dimension 20 +uid 5872,0 +) +*657 (MRCItem +litem &568 +pos 28 +dimension 20 +uid 5874,0 +) +*658 (MRCItem +litem &569 +pos 73 +dimension 20 +uid 5967,0 +) +*659 (MRCItem +litem &570 +pos 74 +dimension 20 +uid 5969,0 +) +*660 (MRCItem +litem &571 +pos 75 +dimension 20 +uid 6023,0 +) +*661 (MRCItem +litem &572 +pos 76 +dimension 20 +uid 6025,0 +) +*662 (MRCItem +litem &573 +pos 77 +dimension 20 +uid 6027,0 +) +*663 (MRCItem +litem &574 +pos 29 +dimension 20 +uid 6173,0 +) +*664 (MRCItem +litem &575 +pos 30 +dimension 20 +uid 6375,0 +) +*665 (MRCItem +litem &576 +pos 78 +dimension 20 +uid 6465,0 +) +*666 (MRCItem +litem &577 +pos 79 +dimension 20 +uid 6555,0 +) +*667 (MRCItem +litem &578 +pos 80 +dimension 20 +uid 8421,0 +) +*668 (MRCItem +litem &579 +pos 81 +dimension 20 +uid 8610,0 +) +*669 (MRCItem +litem &580 +pos 82 +dimension 20 +uid 8612,0 +) +*670 (MRCItem +litem &581 +pos 83 +dimension 20 +uid 8614,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 73,0 +optionalChildren [ +*671 (MRCItem +litem &489 +pos 0 +dimension 20 +uid 74,0 +) +*672 (MRCItem +litem &491 +pos 1 +dimension 50 +uid 75,0 +) +*673 (MRCItem +litem &492 +pos 2 +dimension 100 +uid 76,0 +) +*674 (MRCItem +litem &493 +pos 3 +dimension 50 +uid 77,0 +) +*675 (MRCItem +litem &494 +pos 4 +dimension 100 +uid 78,0 +) +*676 (MRCItem +litem &495 +pos 5 +dimension 100 +uid 79,0 +) +*677 (MRCItem +litem &496 +pos 6 +dimension 50 +uid 80,0 +) +*678 (MRCItem +litem &497 +pos 7 +dimension 80 +uid 81,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 68,0 +vaOverrides [ +] +) +] +) +uid 53,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *679 (LEmptyRow +) +uid 83,0 +optionalChildren [ +*680 (RefLabelRowHdr +) +*681 (TitleRowHdr +) +*682 (FilterRowHdr +) +*683 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*684 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*685 (GroupColHdr +tm "GroupColHdrMgr" +) +*686 (NameColHdr +tm "GenericNameColHdrMgr" +) +*687 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*688 (InitColHdr +tm "GenericValueColHdrMgr" +) +*689 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*690 (EolColHdr +tm "GenericEolColHdrMgr" +) +*691 (LogGeneric +generic (GiElement +name "RAMADDRWIDTH64b" +type "integer" +value "12" +) +uid 6712,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 95,0 +optionalChildren [ +*692 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *693 (MRCItem +litem &679 +pos 1 +dimension 20 +) +uid 97,0 +optionalChildren [ +*694 (MRCItem +litem &680 +pos 0 +dimension 20 +uid 98,0 +) +*695 (MRCItem +litem &681 +pos 1 +dimension 23 +uid 99,0 +) +*696 (MRCItem +litem &682 +pos 2 +hidden 1 +dimension 20 +uid 100,0 +) +*697 (MRCItem +litem &691 +pos 0 +dimension 20 +uid 6713,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 101,0 +optionalChildren [ +*698 (MRCItem +litem &683 +pos 0 +dimension 20 +uid 102,0 +) +*699 (MRCItem +litem &685 +pos 1 +dimension 50 +uid 103,0 +) +*700 (MRCItem +litem &686 +pos 2 +dimension 186 +uid 104,0 +) +*701 (MRCItem +litem &687 +pos 3 +dimension 96 +uid 105,0 +) +*702 (MRCItem +litem &688 +pos 4 +dimension 50 +uid 106,0 +) +*703 (MRCItem +litem &689 +pos 5 +dimension 50 +uid 107,0 +) +*704 (MRCItem +litem &690 +pos 6 +dimension 80 +uid 108,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 96,0 +vaOverrides [ +] +) +] +) +uid 82,0 +type 1 +) +activeModelName "BlockDiag" +) Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.info/Synthesis/Constraints/FAD_main.ctr =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.info/Synthesis/Constraints/FAD_main.ctr (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.info/Synthesis/Constraints/FAD_main.ctr (revision 9841) @@ -0,0 +1,6 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700an +# set_package fgg484 +# set_speed -4 + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.info/Synthesis/Constraints/FAD_main.sdc =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.info/Synthesis/Constraints/FAD_main.sdc (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.info/Synthesis/Constraints/FAD_main.sdc (revision 9841) @@ -0,0 +1,6 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700an +# set_package fgg484 +# set_speed -4 + Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb (revision 9841) @@ -0,0 +1,3236 @@ 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+(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\FPGA_projects\\FACT_FAD_21062010\\FACT_FAD_lib\\hds\\@f@a@d_main" +) +(vvPair +variable "d_logical" +value "C:\\FPGA_projects\\FACT_FAD_21062010\\FACT_FAD_lib\\hds\\FAD_main" +) +(vvPair +variable "date" +value "21.06.2010" +) +(vvPair +variable "day" +value "Mo" +) +(vvPair +variable "day_long" +value "Montag" +) +(vvPair +variable "dd" +value "21" +) +(vvPair +variable "entity_name" +value "FAD_main" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "TU-CC4900F8C7D2" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_HdsLintPlugin" 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+] +) +LanguageMgr "VhdlLangMgr" +uid 51,0 +optionalChildren [ +*115 (SymbolBody +uid 8,0 +optionalChildren [ +*116 (CptPort +uid 135,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 136,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,-3375,43750,-2625" +) +tg (CPTG +uid 137,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 138,0 +va (VaSet +) +xt "38400,-3500,42000,-2500" +st "wiz_reset" +ju 2 +blo "42000,-2700" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 140,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,23600,77000,24400" +st "wiz_reset : OUT std_logic := '1' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_reset" +t "std_logic" +o 28 +suid 2,0 +i "'1'" +) +) +) +*117 (CptPort +uid 163,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 164,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,42625,43750,43375" +) +tg (CPTG +uid 165,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 166,0 +va (VaSet +) +xt "38000,42500,42000,43500" +st "led : (7:0)" +ju 2 +blo "42000,43300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 168,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,18000,83000,18800" +st "led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 DOWNTO 0)" +posAdd 0 +o 21 +suid 7,0 +i "(OTHERS => '0')" +) +) +) +*118 (CptPort +uid 464,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 465,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,4625,15000,5375" +) +tg (CPTG +uid 466,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 467,0 +va (VaSet +) +xt "16000,4500,18800,5500" +st "trigger" +blo "16000,5300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 468,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,9200,63500,10000" +st "trigger : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "trigger" +t "std_logic" +preAdd 0 +posAdd 0 +o 10 +suid 18,0 +) +) +) +*119 (CptPort +uid 833,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 834,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,15625,15000,16375" +) +tg (CPTG +uid 835,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 836,0 +va (VaSet +) +xt "16000,15500,19200,16500" +st "adc_oeb" +blo "16000,16300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 837,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,14000,77000,14800" +st "adc_oeb : OUT std_logic := '1' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "adc_oeb" +t "std_logic" +o 16 +suid 21,0 +i "'1'" +) +) +) +*120 (CptPort +uid 923,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 924,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,6625,15000,7375" +) +tg (CPTG +uid 925,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 926,0 +va (VaSet +) +xt "16000,6500,21900,7500" +st "board_id : (3:0)" +blo "16000,7300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 927,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,7600,73500,8400" +st "board_id : IN std_logic_vector (3 downto 0) ;" +) +thePort (LogicalPort +decl (Decl +n "board_id" +t "std_logic_vector" +b "(3 downto 0)" +preAdd 0 +posAdd 0 +o 8 +suid 24,0 +) +) +) +*121 (CptPort +uid 928,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 929,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,7625,15000,8375" +) +tg (CPTG +uid 930,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 931,0 +va (VaSet +) +xt "16000,7500,21700,8500" +st "crate_id : (1:0)" +blo "16000,8300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 932,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,8400,73500,9200" +st "crate_id : IN std_logic_vector (1 downto 0) ;" +) +thePort (LogicalPort +decl (Decl +n "crate_id" +t "std_logic_vector" +b "(1 downto 0)" +o 9 +suid 25,0 +) +) +) +*122 (CptPort +uid 1037,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1038,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,-6375,43750,-5625" +) +tg (CPTG +uid 1039,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1040,0 +va (VaSet +) +xt "36000,-6500,42000,-5500" +st "wiz_addr : (9:0)" +ju 2 +blo "42000,-5700" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1041,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,21200,73500,22000" +st "wiz_addr : OUT std_logic_vector (9 DOWNTO 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_addr" +t "std_logic_vector" +b "(9 DOWNTO 0)" +o 25 +suid 26,0 +) +) +) +*123 (CptPort +uid 1042,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 1043,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,-5375,43750,-4625" +) +tg (CPTG +uid 1044,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1045,0 +va (VaSet +) +xt "35700,-5500,42000,-4500" +st "wiz_data : (15:0)" +ju 2 +blo "42000,-4700" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1046,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,26000,73000,26800" +st "wiz_data : INOUT std_logic_vector (15 DOWNTO 0)" +) +thePort (LogicalPort +m 2 +decl (Decl +n "wiz_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 31 +suid 27,0 +) +) +) +*124 (CptPort +uid 1047,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1048,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,625,43750,1375" +) +tg (CPTG +uid 1049,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1050,0 +va (VaSet +) +xt "39300,500,42000,1500" +st "wiz_cs" +ju 2 +blo "42000,1300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1051,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,22000,77000,22800" +st "wiz_cs : OUT std_logic := '1' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_cs" +t "std_logic" +o 26 +suid 28,0 +i "'1'" +) +) +) +*125 (CptPort +uid 1052,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1053,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,-1375,43750,-625" +) +tg (CPTG +uid 1054,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1055,0 +va (VaSet +) +xt "39300,-1500,42000,-500" +st "wiz_wr" +ju 2 +blo "42000,-700" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1056,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,24400,77000,25200" +st "wiz_wr : OUT std_logic := '1' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_wr" +t "std_logic" +o 29 +suid 29,0 +i "'1'" +) +) +) +*126 (CptPort +uid 1057,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1058,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,-2375,43750,-1625" +) +tg (CPTG +uid 1059,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1060,0 +va (VaSet +) +xt "39400,-2500,42000,-1500" +st "wiz_rd" +ju 2 +blo "42000,-1700" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1061,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,22800,77000,23600" +st "wiz_rd : OUT std_logic := '1' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_rd" +t "std_logic" +o 27 +suid 30,0 +i "'1'" +) +) +) +*127 (CptPort +uid 1062,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1063,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,-375,43750,375" +) +tg (CPTG +uid 1064,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1065,0 +va (VaSet +) +xt "39300,-500,42000,500" +st "wiz_int" +ju 2 +blo "42000,300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1066,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10000,63500,10800" +st "wiz_int : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "wiz_int" +t "std_logic" +o 11 +suid 31,0 +) +) +) +*128 (CptPort +uid 1389,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1390,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,-4375,15000,-3625" +) +tg (CPTG +uid 1391,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1392,0 +va (VaSet +) +xt "16000,-4500,20500,-3500" +st "CLK_25_PS" +blo "16000,-3700" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1393,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10800,63500,11600" +st "CLK_25_PS : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "CLK_25_PS" +t "std_logic" +o 12 +suid 35,0 +) +) +) +*129 (CptPort +uid 1725,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1726,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,-5375,15000,-4625" +) +tg (CPTG +uid 1727,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1728,0 +va (VaSet +) +xt "16000,-5500,19100,-4500" +st "CLK_50" +blo "16000,-4700" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1729,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,11600,63500,12400" +st "CLK_50 : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "CLK_50" +t "std_logic" +o 13 +suid 37,0 +) +) +) +*130 (CptPort +uid 1755,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1756,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,-6375,15000,-5625" +) +tg (CPTG +uid 1757,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1758,0 +va (VaSet +) +xt "16000,-6500,17900,-5500" +st "CLK" +blo "16000,-5700" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1759,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2000,63500,2800" +st "CLK : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "CLK" +t "std_logic" +o 1 +suid 38,0 +) +) +) +*131 (CptPort +uid 1976,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1977,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,14625,15000,15375" +) +tg (CPTG +uid 1978,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1979,0 +va (VaSet +) +xt "16000,14500,24000,15500" +st "adc_otr_array : (3:0)" +blo "16000,15300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1980,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6800,73500,7600" +st "adc_otr_array : IN std_logic_vector (3 DOWNTO 0) ;" +) +thePort (LogicalPort +decl (Decl +n "adc_otr_array" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 7 +suid 40,0 +) +) +) +*132 (CptPort +uid 2282,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2283,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,20625,15000,21375" +) +tg (CPTG +uid 2284,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2285,0 +va (VaSet +) +xt "16000,20500,21900,21500" +st "adc_data_array" +blo "16000,21300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2286,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6000,69000,6800" +st "adc_data_array : IN adc_data_array_type ;" +) +thePort (LogicalPort +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 6 +suid 41,0 +) +) +) +*133 (CptPort +uid 2448,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2449,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,34625,15000,35375" +) +tg (CPTG +uid 2450,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2451,0 +va (VaSet +) +xt "16000,34500,24500,35500" +st "drs_channel_id : (3:0)" +blo "16000,35300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2452,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,16400,83000,17200" +st "drs_channel_id : OUT std_logic_vector (3 downto 0) := (others => '0') ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_channel_id" +t "std_logic_vector" +b "(3 downto 0)" +o 19 +suid 48,0 +i "(others => '0')" +) +) +) +*134 (CptPort +uid 2453,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2454,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,35625,15000,36375" +) +tg (CPTG +uid 2455,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2456,0 +va (VaSet +) +xt "16000,35500,20300,36500" +st "drs_dwrite" +blo "16000,36300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2457,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,17200,77000,18000" +st "drs_dwrite : OUT std_logic := '1' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_dwrite" +t "std_logic" +o 20 +suid 49,0 +i "'1'" +) +) +) +*135 (CptPort +uid 2710,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2711,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,30625,15000,31375" +) +tg (CPTG +uid 2712,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2713,0 +va (VaSet +) +xt "16000,30500,21400,31500" +st "SROUT_in_0" +blo "16000,31300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2714,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2800,63500,3600" +st "SROUT_in_0 : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "SROUT_in_0" +t "std_logic" +o 2 +suid 52,0 +) +) +) +*136 (CptPort +uid 2715,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2716,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,31625,15000,32375" +) +tg (CPTG +uid 2717,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2718,0 +va (VaSet +) +xt "16000,31500,21400,32500" +st "SROUT_in_1" +blo "16000,32300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2719,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3600,63500,4400" +st "SROUT_in_1 : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "SROUT_in_1" +t "std_logic" +o 3 +suid 53,0 +) +) +) +*137 (CptPort +uid 2720,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2721,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,32625,15000,33375" +) +tg (CPTG +uid 2722,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2723,0 +va (VaSet +) +xt "16000,32500,21400,33500" +st "SROUT_in_2" +blo "16000,33300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2724,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,4400,63500,5200" +st "SROUT_in_2 : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "SROUT_in_2" +t "std_logic" +o 4 +suid 54,0 +) +) +) +*138 (CptPort +uid 2725,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2726,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,33625,15000,34375" +) +tg (CPTG +uid 2727,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2728,0 +va (VaSet +) +xt "16000,33500,21400,34500" +st "SROUT_in_3" +blo "16000,34300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2729,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,5200,63500,6000" +st "SROUT_in_3 : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "SROUT_in_3" +t "std_logic" +o 5 +suid 55,0 +) +) +) +*139 (CptPort +uid 2987,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2988,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,36625,15000,37375" +) +tg (CPTG +uid 2989,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2990,0 +va (VaSet +) +xt "16000,36500,20200,37500" +st "RSRLOAD" +blo "16000,37300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2991,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,12400,77000,13200" +st "RSRLOAD : OUT std_logic := '0' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "RSRLOAD" +t "std_logic" +o 14 +suid 56,0 +i "'0'" +) +) +) +*140 (CptPort +uid 2992,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2993,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,38625,15000,39375" +) +tg (CPTG +uid 2994,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2995,0 +va (VaSet +) +xt "16000,38500,19000,39500" +st "SRCLK" +blo "16000,39300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2996,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,13200,77000,14000" +st "SRCLK : OUT std_logic := '0' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "SRCLK" +t "std_logic" +o 15 +suid 57,0 +i "'0'" +) +) +) +*141 (CptPort +uid 3631,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3632,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,23625,43750,24375" +) +tg (CPTG +uid 3633,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3634,0 +va (VaSet +) +xt "40300,23500,42000,24500" +st "sclk" +ju 2 +blo "42000,24300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 3635,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,19600,63500,20400" +st "sclk : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sclk" +t "std_logic" +o 23 +suid 62,0 +) +) +) +*142 (CptPort +uid 3636,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 3637,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,24625,43750,25375" +) +tg (CPTG +uid 3638,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3639,0 +va (VaSet +) +xt "40600,24500,42000,25500" +st "sio" +ju 2 +blo "42000,25300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 3640,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,25200,63500,26000" +st "sio : INOUT std_logic ;" +) +thePort (LogicalPort +m 2 +decl (Decl +n "sio" +t "std_logic" +preAdd 0 +posAdd 0 +o 30 +suid 63,0 +) +) +) +*143 (CptPort +uid 3641,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3642,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,12625,43750,13375" +) +tg (CPTG +uid 3643,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3644,0 +va (VaSet +) +xt "39200,12500,42000,13500" +st "dac_cs" +ju 2 +blo "42000,13300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 3645,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,14800,63500,15600" +st "dac_cs : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "dac_cs" +t "std_logic" +o 17 +suid 64,0 +) +) +) +*144 (CptPort +uid 3646,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3647,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,14625,43750,15375" +) +tg (CPTG +uid 3648,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3649,0 +va (VaSet +) +xt "35500,14500,42000,15500" +st "sensor_cs : (3:0)" +ju 2 +blo "42000,15300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 3650,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,20400,73500,21200" +st "sensor_cs : OUT std_logic_vector (3 DOWNTO 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sensor_cs" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 24 +suid 65,0 +) +) +) +*145 (CptPort +uid 4067,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4068,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,25625,43750,26375" +) +tg (CPTG +uid 4069,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4070,0 +va (VaSet +) +xt "40000,25500,42000,26500" +st "mosi" +ju 2 +blo "42000,26300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 4071,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,18800,77000,19600" +st "mosi : OUT std_logic := '0' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "mosi" +t "std_logic" +o 22 +suid 66,0 +i "'0'" +) +) +) +*146 (CptPort +uid 4144,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4145,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,43625,43750,44375" +) +tg (CPTG +uid 4146,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4147,0 +va (VaSet +) +xt "39000,43500,42000,44500" +st "denable" +ju 2 +blo "42000,44300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 4148,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,15600,90500,16400" +st "denable : OUT std_logic := '0' ; -- default domino wave off" +) +thePort (LogicalPort +m 1 +decl (Decl +n "denable" +t "std_logic" +eolc "-- default domino wave off" +posAdd 0 +o 18 +suid 67,0 +i "'0'" +) +) +) +] +shape (Rectangle +uid 4141,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,-8000,43000,46000" +) +oxt "15000,-8000,43000,45000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "15200,45000,21400,46000" +st "FACT_FAD_lib" +blo "15200,45800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "15200,46000,19400,47000" +st "FAD_main" +blo "15200,46800" +) +) +gi *147 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,15500,14400" +st "Generic Declarations + +RAMADDRWIDTH64b integer 12 +" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "RAMADDRWIDTH64b" +type "integer" +value "12" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +) +portVis (PortSigDisplay +) +) +*148 (Grouping +uid 16,0 +optionalChildren [ +*149 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48000,45700,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*150 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,44000,56200,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*151 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,46000,46200,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*152 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,46000,34300,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*153 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,45200,62400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*154 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,44000,61700,45000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*155 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "39150,44500,45850,45500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*156 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,47000,34300,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*157 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,48000,34900,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*158 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,47000,49000,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *159 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*160 (Text +uid 49,0 +va (VaSet +font "arial,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*161 (MLText +uid 50,0 +va (VaSet +) +xt "0,1000,14500,6000" +st "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all;" +tm "PackageList" +) +] +) +windowSize "0,0,1553,1028" +viewArea "-12542,-31642,130863,66614" +cachedDiagramExtent "0,-1000,83000,49000" +hasePageBreakOrigin 1 +pageBreakOrigin "0,-2000" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *162 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *163 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,26800,44400,27800" +st "User:" +blo "42000,27600" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,27800,44000,27800" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 4297,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb.bak =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb.bak (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb.bak (revision 9841) @@ -0,0 +1,2320 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +] +libraryRefs [ +"ieee" +] +) +version "24.1" +appVersion "2009.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 41,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 53,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "wiz_reset" +t "std_logic" +o 15 +suid 2,0 +i "'1'" +) +) +uid 111,0 +) +*15 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 downto 0)" +o 11 +suid 7,0 +i "(OTHERS => '0')" +) +) +uid 121,0 +) +*16 (LogPort +port (LogicalPort +decl (Decl +n "trigger" +t "std_logic" +preAdd 0 +posAdd 0 +o 6 +suid 18,0 +) +) +uid 453,0 +) +*17 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "adc_oeb" +t "std_logic" +o 10 +suid 21,0 +i "'1'" +) +) +uid 825,0 +) +*18 (LogPort +port (LogicalPort +decl (Decl +n "board_id" +t "std_logic_vector" +b "(3 downto 0)" +preAdd 0 +posAdd 0 +o 4 +suid 24,0 +) +) +uid 920,0 +) +*19 (LogPort +port (LogicalPort +decl (Decl +n "crate_id" +t "std_logic_vector" +b "(1 downto 0)" +o 5 +suid 25,0 +) +) +uid 922,0 +) +*20 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "wiz_addr" +t "std_logic_vector" +b "(9 DOWNTO 0)" +o 12 +suid 26,0 +) +) +uid 1026,0 +) +*21 (LogPort +port (LogicalPort +m 2 +decl (Decl +n "wiz_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 17 +suid 27,0 +) +) +uid 1028,0 +) +*22 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "wiz_cs" +t "std_logic" +o 13 +suid 28,0 +i "'1'" +) +) +uid 1030,0 +) +*23 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "wiz_wr" +t "std_logic" +o 16 +suid 29,0 +i "'1'" +) +) +uid 1032,0 +) +*24 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "wiz_rd" +t "std_logic" +o 14 +suid 30,0 +i "'1'" +) +) +uid 1034,0 +) +*25 (LogPort +port (LogicalPort +decl (Decl +n "wiz_int" +t "std_logic" +o 7 +suid 31,0 +) +) +uid 1036,0 +) +*26 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "CLK_25_PS" +t "std_logic" +o 8 +suid 35,0 +) +) +uid 1388,0 +) +*27 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "CLK_50" +t "std_logic" +preAdd 0 +posAdd 0 +o 9 +suid 37,0 +) +) +uid 1724,0 +) +*28 (LogPort +port (LogicalPort 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"SideDataUserDir" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main" +) +(vvPair +variable "d_logical" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main" +) +(vvPair +variable "date" +value "13.04.2010" +) +(vvPair +variable "day" +value "Di" +) +(vvPair +variable "day_long" +value "Dienstag" +) +(vvPair +variable "dd" +value "13" +) +(vvPair +variable "entity_name" +value "FAD_main" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "E5PCXX" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_PrecisionSynthesisDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "FAD_main" +) +(vvPair +variable "month" +value "Apr" +) +(vvPair +variable "month_long" +value "April" +) +(vvPair +variable "p" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\symbol.sb" +) +(vvPair +variable "p_logical" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "$HDS_HOME/../Exemplar/bin/win32" +) +(vvPair +variable "task_ModelSimPath" +value "D:\\Programme\\FPGAdv82LSPS\\Modeltech\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "$HDS_HOME/../Precision/Mgc_home/bin" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "15:16:53" +) +(vvPair +variable "unit" +value "FAD_main" +) +(vvPair +variable "user" +value "kai" +) +(vvPair +variable "version" +value "2009.1 (Build 12)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 51,0 +optionalChildren [ +*85 (SymbolBody +uid 8,0 +optionalChildren [ +*86 (CptPort +uid 135,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 136,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,18625,43750,19375" +) +tg (CPTG +uid 137,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 138,0 +va (VaSet +) +xt "38400,18500,42000,19500" +st "wiz_reset" +ju 2 +blo "42000,19300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 140,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,13200,77000,14000" +st "wiz_reset : OUT std_logic := '1' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_reset" +t "std_logic" +o 15 +suid 2,0 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"44000,5200,73500,6000" +st "crate_id : IN std_logic_vector (1 downto 0) ;" +) +thePort (LogicalPort +decl (Decl +n "crate_id" +t "std_logic_vector" +b "(1 downto 0)" +o 5 +suid 25,0 +) +) +) +*92 (CptPort +uid 1037,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1038,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,26625,43750,27375" +) +tg (CPTG +uid 1039,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1040,0 +va (VaSet +) +xt "36000,26500,42000,27500" +st "wiz_addr : (9:0)" +ju 2 +blo "42000,27300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1041,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10800,73500,11600" +st "wiz_addr : OUT std_logic_vector (9 DOWNTO 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_addr" +t "std_logic_vector" +b "(9 DOWNTO 0)" +o 12 +suid 26,0 +) +) +) +*93 (CptPort +uid 1042,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 1043,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,27625,43750,28375" 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'1' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_cs" +t "std_logic" +o 13 +suid 28,0 +i "'1'" +) +) +) +*95 (CptPort +uid 1052,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1053,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,29625,43750,30375" +) +tg (CPTG +uid 1054,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1055,0 +va (VaSet +) +xt "39300,29500,42000,30500" +st "wiz_wr" +ju 2 +blo "42000,30300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1056,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,14000,77000,14800" +st "wiz_wr : OUT std_logic := '1' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_wr" +t "std_logic" +o 16 +suid 29,0 +i "'1'" +) +) +) +*96 (CptPort +uid 1057,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1058,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,30625,43750,31375" +) +tg (CPTG +uid 1059,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1060,0 +va (VaSet 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(VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,31625,43750,32375" +) +tg (CPTG +uid 1391,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1392,0 +va (VaSet +) +xt "37500,31500,42000,32500" +st "CLK_25_PS" +ju 2 +blo "42000,32300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1393,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,7600,63500,8400" +st "CLK_25_PS : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "CLK_25_PS" +t "std_logic" +o 8 +suid 35,0 +) +) +) +*99 (CptPort +uid 1725,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1726,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,32625,43750,33375" +) +tg (CPTG +uid 1727,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1728,0 +va (VaSet +) +xt "38900,32500,42000,33500" +st "CLK_50" +ju 2 +blo "42000,33300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1729,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,8400,63500,9200" +st "CLK_50 : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "CLK_50" +t "std_logic" +preAdd 0 +posAdd 0 +o 9 +suid 37,0 +) +) +) +*100 (CptPort +uid 1755,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1756,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,19625,15000,20375" +) +tg (CPTG +uid 1757,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1758,0 +va (VaSet +) +xt "16000,19500,17900,20500" +st "CLK" +blo "16000,20300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1759,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2000,63500,2800" +st "CLK : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "CLK" +t "std_logic" +o 1 +suid 38,0 +) +) +) +*101 (CptPort +uid 1976,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1977,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,21625,15000,22375" +) +tg (CPTG +uid 1978,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1979,0 +va (VaSet +) +xt "16000,21500,24000,22500" +st "adc_otr_array : (3:0)" +blo "16000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1980,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3600,73500,4400" +st "adc_otr_array : IN std_logic_vector (3 DOWNTO 0) ;" +) +thePort (LogicalPort +decl (Decl +n "adc_otr_array" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 3 +suid 40,0 +) +) +) +*102 (CptPort +uid 2282,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2283,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,22625,15000,23375" +) +tg (CPTG +uid 2284,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2285,0 +va (VaSet +) +xt "16000,22500,21900,23500" +st "adc_data_array" +blo "16000,23300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2286,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2800,69000,3600" +st "adc_data_array : IN adc_data_array_type ;" +) +thePort (LogicalPort +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 2 +suid 41,0 +) +) +) +] +shape (Rectangle +uid 584,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,-1000,43000,34000" +) +oxt "15000,-1000,43000,26000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "22200,8000,28400,9000" +st "FACT_FAD_lib" +blo "22200,8800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "22200,9000,26400,10000" +st "FAD_main" +blo "22200,9800" +) +) +gi *103 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +) +portVis (PortSigDisplay +) +) +*104 (Grouping +uid 16,0 +optionalChildren [ +*105 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48000,44400,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*106 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,44000,56200,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*107 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,46000,46200,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*108 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,46000,34300,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*109 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,45200,62400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*110 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,44000,61700,45000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*111 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "39150,44500,45850,45500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*112 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,47000,34300,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*113 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,48000,34900,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*114 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,47000,49000,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *115 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*116 (Text +uid 49,0 +va (VaSet +font "arial,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*117 (MLText +uid 50,0 +va (VaSet +) +xt "0,1000,10900,4000" +st "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all;" +tm "PackageList" +) +] +) +windowSize "0,0,1015,690" +viewArea "0,0,0,0" +cachedDiagramExtent "0,0,0,0" +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *118 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *119 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,15600,44400,16600" +st "User:" +blo "42000,16400" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,16600,44000,16600" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 2355,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol:CDM" +) Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_adc_buffer._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_adc_buffer._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_adc_buffer._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom beha +DEFAULT_FILE atom adc_buffer_beha.vhd Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_clock_generator._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_clock_generator._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_clock_generator._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom clock_generator/struct.bd Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_control_manager._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_control_manager._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_control_manager._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom control_manager_beha.vhd +DEFAULT_ARCHITECTURE atom beha Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_control_unit._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_control_unit._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_control_unit._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom control_unit/struct.bd +DEFAULT_ARCHITECTURE atom struct Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_controlram_16bit_x256._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_controlram_16bit_x256._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_controlram_16bit_x256._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom controlRAM_16bit_x256_controlRAM_16bit_x256_a.vhd +DEFAULT_ARCHITECTURE atom controlRAM_16bit_x256_a Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_data_generator._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_data_generator._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_data_generator._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom Behavioral +DEFAULT_FILE atom data_generator.vhd Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_dcm_50_to_25._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_dcm_50_to_25._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_dcm_50_to_25._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom BEHAVIORAL +DEFAULT_FILE atom dcm_50_to_25_BEHAVIORAL.vhd Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_debouncer._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_debouncer._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_debouncer._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom debouncer.vhd +DEFAULT_ARCHITECTURE atom Behavioral Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_drs_pulser._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_drs_pulser._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_drs_pulser._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom drs_pulser_dummy.vhd +DEFAULT_ARCHITECTURE atom behavior Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_fad_board._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_fad_board._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_fad_board._epf (revision 9841) @@ -0,0 +1,3 @@ +DEFAULT_FILE atom @f@a@d_@board/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_fad_main._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_fad_main._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_fad_main._epf (revision 9841) @@ -0,0 +1,3 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom @f@a@d_main/struct.bd +TOP_MARKER atom 0 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_memory_manager._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_memory_manager._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_memory_manager._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom beha +DEFAULT_FILE atom memory_manager_beha.vhd Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_spi_clock_generator._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_spi_clock_generator._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_spi_clock_generator._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom spi_clock_gen_beha.vhd +DEFAULT_ARCHITECTURE atom beha Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_spi_controller._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_spi_controller._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_spi_controller._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom spi_controller_beha.vhd +DEFAULT_ARCHITECTURE atom beha Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_spi_distributor._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_spi_distributor._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_spi_distributor._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom spi_distributor_beha.vhd +DEFAULT_ARCHITECTURE atom beha Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_spi_interface._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_spi_interface._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_spi_interface._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom spi_interface/struct.bd +DEFAULT_ARCHITECTURE atom struct Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_trigger_counter._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_trigger_counter._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_trigger_counter._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom trigger_counter_beha.vhd +DEFAULT_ARCHITECTURE atom beha Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_w5300_modul._epf =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_w5300_modul._epf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/_w5300_modul._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom Behavioral +DEFAULT_FILE atom w5300_modul.vhd Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd (revision 9841) @@ -0,0 +1,2979 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "UNISIM" +unitName "Vcomponents" +) +] +instances [ +(Instance +name "U_1" +duLibraryName "FACT_FAD_lib" +duName "dcm_ps_38ns" +elements [ +] +mwi 0 +uid 354,0 +) +(Instance +name "U_0" +duLibraryName "FACT_FAD_lib" +duName "dcm_50_to_25" +elements [ +] +mwi 0 +uid 403,0 +) +] +libraryRefs [ +"ieee" +"UNISIM" +] +) +version "29.1" +appVersion "2009.1 (Build 12)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator" +) +(vvPair +variable "d_logical" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator" +) +(vvPair +variable "date" +value "26.05.2010" +) +(vvPair +variable "day" +value "Mi" +) +(vvPair +variable "day_long" +value "Mittwoch" +) +(vvPair +variable "dd" +value "26" +) +(vvPair +variable "entity_name" +value "clock_generator" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "IHP110" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "05" +) +(vvPair +variable "module_name" +value "clock_generator" +) +(vvPair +variable "month" +value "Mai" +) +(vvPair +variable "month_long" +value "Mai" +) +(vvPair +variable "p" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator\\struct.bd" +) +(vvPair +variable "p_logical" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "D:\\modeltech_6.5e\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair 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=================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd.bak (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd.bak (revision 9841) @@ -0,0 +1,2979 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "UNISIM" +unitName "Vcomponents" +) +] +instances [ +(Instance +name "U_1" +duLibraryName "FACT_FAD_lib" +duName "dcm_ps_38ns" +elements [ +] +mwi 0 +uid 354,0 +) +(Instance +name "U_0" +duLibraryName "FACT_FAD_lib" +duName "dcm_50_to_25" +elements [ +] +mwi 0 +uid 403,0 +) +] +libraryRefs [ +"ieee" +"UNISIM" +] +) +version "29.1" +appVersion "2009.1 (Build 12)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator" +) +(vvPair +variable "d_logical" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator" +) +(vvPair +variable "date" +value "16.04.2010" +) +(vvPair +variable "day" +value "Fr" +) +(vvPair +variable "day_long" +value "Freitag" +) +(vvPair +variable "dd" +value "16" +) +(vvPair +variable "entity_name" +value "clock_generator" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "E5PCXX" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "clock_generator" +) +(vvPair +variable "month" +value "Apr" +) +(vvPair +variable "month_long" +value "April" +) +(vvPair +variable "p" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator\\struct.bd" +) +(vvPair +variable "p_logical" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "$HDS_HOME/../Exemplar/bin/win32" +) +(vvPair +variable "task_ModelSimPath" +value "D:\\Programme\\FPGAdv82LSPS\\Modeltech\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "$HDS_HOME/../Precision/Mgc_home/bin" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "14:43:14" +) +(vvPair +variable "unit" +value "clock_generator" +) +(vvPair +variable "user" +value "kai" +) +(vvPair +variable "version" +value "2009.1 (Build 12)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 52,0 +optionalChildren [ +*1 (Grouping +uid 9,0 +optionalChildren [ +*2 (CommentText +uid 11,0 +shape (Rectangle +uid 12,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 13,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48000,44400,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*3 (CommentText +uid 14,0 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/firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd.info/Synthesis/Constraints/clock_generator.ctr =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd.info/Synthesis/Constraints/clock_generator.ctr (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd.info/Synthesis/Constraints/clock_generator.ctr (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700a +# set_package fg484 +# set_speed -4 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd.info/Synthesis/Constraints/clock_generator.sdc =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd.info/Synthesis/Constraints/clock_generator.sdc (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd.info/Synthesis/Constraints/clock_generator.sdc (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700a +# set_package fg484 +# set_speed -4 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/clock_generator/symbol.sb =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/clock_generator/symbol.sb (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/clock_generator/symbol.sb (revision 9841) @@ -0,0 +1,1490 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +] +libraryRefs [ +"ieee" +] +) +version "24.1" +appVersion "2009.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 6,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 53,0 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/firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control@r@a@m_16bit_x256/symbol.sb =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control@r@a@m_16bit_x256/symbol.sb (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control@r@a@m_16bit_x256/symbol.sb (revision 9841) @@ -0,0 +1,1623 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +itemName "ALL" +) +] +libraryRefs [ +"ieee" +"XilinxCoreLib" +] +) +version "24.1" +appVersion "2009.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 5,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 94,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm 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"group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "EEPC8" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "import_lib" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "controlRAM_16bit_x256" +) +(vvPair +variable "month" +value "Apr" +) +(vvPair +variable "month_long" +value "April" +) +(vvPair +variable "p" +value "D:\\E5b\\E5b_09_189\\FPGA\\import_lib\\hds\\control@r@a@m_16bit_x256\\symbol.sb" +) +(vvPair +variable "p_logical" +value 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+textAngle 90 +) +uid 221,0 +optionalChildren [ +*86 (MRCItem +litem &67 +pos 0 +dimension 20 +uid 222,0 +) +*87 (MRCItem +litem &69 +pos 1 +dimension 50 +uid 223,0 +) +*88 (MRCItem +litem &70 +pos 2 +dimension 100 +uid 224,0 +) +*89 (MRCItem +litem &71 +pos 3 +dimension 100 +uid 225,0 +) +*90 (MRCItem +litem &72 +pos 4 +dimension 50 +uid 226,0 +) +*91 (MRCItem +litem &73 +pos 5 +dimension 50 +uid 227,0 +) +*92 (MRCItem +litem &74 +pos 6 +dimension 80 +uid 228,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 216,0 +vaOverrides [ +] +) +] +) +uid 202,0 +type 1 +) +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager" +) +(vvPair +variable "d_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager" +) +(vvPair +variable "date" +value "12.07.2010" +) +(vvPair +variable "day" +value "Mo" +) +(vvPair +variable "day_long" +value "Montag" +) +(vvPair +variable "dd" +value "12" +) +(vvPair +variable "entity_name" +value "control_manager" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "TU-CC4900F8C7D2" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "07" +) +(vvPair +variable "module_name" +value "control_manager" +) +(vvPair +variable "month" +value "Jul" +) +(vvPair +variable "month_long" +value "Juli" +) +(vvPair +variable "p" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "14:11:44" +) +(vvPair +variable "unit" +value "control_manager" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 172,0 +optionalChildren [ +*93 (SymbolBody +uid 8,0 +optionalChildren [ +*94 (CptPort +uid 48,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 49,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41250,14625,42000,15375" +) +tg (CPTG +uid 50,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 51,0 +va (VaSet +) +xt "43000,14500,44300,15500" +st "clk" +blo "43000,15300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 52,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,11000,23000,11800" +st "clk : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "clk" +t "std_logic" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*95 (CptPort +uid 58,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 59,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,19625,67750,20375" +) +tg (CPTG +uid 60,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 61,0 +va (VaSet +) +xt "60900,19500,66000,20500" +st "config_ready" +ju 2 +blo "66000,20300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 62,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,12600,37000,13400" +st "config_ready : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_ready" +t "std_logic" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +i "'0'" +) +) +) +*96 (CptPort +uid 63,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 64,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,20625,67750,21375" +) +tg (CPTG +uid 65,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 66,0 +va (VaSet +) +xt "61200,20500,66000,21500" +st "config_start" +ju 2 +blo "66000,21300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 67,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,14200,23000,15000" +st "config_start : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_start" +t "std_logic" +preAdd 0 +posAdd 0 +o 5 +suid 4,0 +) +) +) +*97 (CptPort +uid 68,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 69,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,15625,67750,16375" +) +tg (CPTG +uid 70,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 71,0 +va (VaSet +) +xt "58300,15500,66000,16500" +st "config_data : (15:0)" +ju 2 +blo "66000,16300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 72,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,15000,43000,15800" +st "config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z') ; +" +) +thePort (LogicalPort +m 2 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 6 +suid 5,0 +i "(others => 'Z')" +) +) +) +*98 (CptPort +uid 73,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 74,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,14625,67750,15375" +) +tg (CPTG +uid 75,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 76,0 +va (VaSet +) +xt "52600,14500,66000,15500" +st "config_addr : (ADDR_WIDTH - 1:0)" +ju 2 +blo "66000,15300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 77,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,15800,39500,16600" +st "config_addr : IN std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(ADDR_WIDTH - 1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 7 +suid 6,0 +) +) +) +*99 (CptPort +uid 78,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 79,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,17625,67750,18375" +) +tg (CPTG +uid 80,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 81,0 +va (VaSet +) +xt "60700,17500,66000,18500" +st "config_wr_en" +ju 2 +blo "66000,18300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 82,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,16600,23000,17400" +st "config_wr_en : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_wr_en" +t "std_logic" +preAdd 0 +posAdd 0 +o 8 +suid 7,0 +) +) +) +*100 (CptPort +uid 83,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 84,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,18625,67750,19375" +) +tg (CPTG +uid 85,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 86,0 +va (VaSet +) +xt "60800,18500,66000,19500" +st "config_rd_en" +ju 2 +blo "66000,19300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 87,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,17400,23000,18200" +st "config_rd_en : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_rd_en" +t "std_logic" +preAdd 0 +posAdd 0 +o 9 +suid 8,0 +) +) +) +*101 (CptPort +uid 88,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 89,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,21625,67750,22375" +) +tg (CPTG +uid 90,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 91,0 +va (VaSet +) +xt "59400,21500,66000,22500" +st "config_data_valid" +ju 2 +blo "66000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 92,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,18200,37000,19000" +st "config_data_valid : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_data_valid" +t "std_logic" +preAdd 0 +posAdd 0 +o 10 +suid 9,0 +i "'0'" +) +) +) +*102 (CptPort +uid 93,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 94,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,22625,67750,23375" +) +tg (CPTG +uid 95,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 96,0 +va (VaSet +) +xt "61200,22500,66000,23500" +st "config_busy" +ju 2 +blo "66000,23300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 97,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,19000,37000,19800" +st "config_busy : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_busy" +t "std_logic" +preAdd 0 +posAdd 0 +o 11 +suid 10,0 +i "'0'" +) +) +) +*103 (CptPort +uid 118,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 119,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,24625,67750,25375" +) +tg (CPTG +uid 120,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 121,0 +va (VaSet +) +xt "62300,24500,66000,25500" +st "dac_array" +ju 2 +blo "66000,25300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 122,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22200,26000,23000" +st "dac_array : OUT dac_array_type ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "dac_array" +t "dac_array_type" +preAdd 0 +posAdd 0 +o 15 +suid 15,0 +) +) +) +*104 (CptPort +uid 123,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 124,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,25625,67750,26375" +) +tg (CPTG +uid 125,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 126,0 +va (VaSet +) +xt "62600,25500,66000,26500" +st "roi_array" +ju 2 +blo "66000,26300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 127,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,23000,26000,23800" +st "roi_array : OUT roi_array_type ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "roi_array" +t "roi_array_type" +preAdd 0 +posAdd 0 +o 16 +suid 16,0 +) +) +) +*105 (CptPort +uid 263,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 264,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,28625,67750,29375" +) +tg (CPTG +uid 265,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 266,0 +va (VaSet +) +xt "58100,28500,66000,29500" +st "ram_data_in : (15:0)" +ju 2 +blo "66000,29300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 267,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,20600,33500,21400" +st "ram_data_in : OUT std_logic_vector (15 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "ram_data_in" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 13 +suid 19,0 +) +) +) +*106 (CptPort +uid 268,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 269,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,29625,67750,30375" +) +tg (CPTG +uid 270,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 271,0 +va (VaSet +) +xt "58100,29500,66000,30500" +st "ram_write_en : (0:0)" +ju 2 +blo "66000,30300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 272,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,21400,33000,22200" +st "ram_write_en : OUT std_logic_vector (0 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "ram_write_en" +t "std_logic_vector" +b "(0 DOWNTO 0)" +o 14 +suid 20,0 +) +) +) +*107 (CptPort +uid 310,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 311,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41250,15625,42000,16375" +) +tg (CPTG +uid 312,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 313,0 +va (VaSet +) +xt "43000,15500,51300,16500" +st "ram_data_out : (15:0)" +blo "43000,16300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 314,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,11800,33500,12600" +st "ram_data_out : IN std_logic_vector (15 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "ram_data_out" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 2 +suid 21,0 +) +) +) +*108 (CptPort +uid 346,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 347,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,30625,67750,31375" +) +tg (CPTG +uid 348,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 349,0 +va (VaSet +) +xt "53400,30500,66000,31500" +st "ram_addr : (ADDR_WIDTH - 1:0)" +ju 2 +blo "66000,31300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 350,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,19800,39500,20600" +st "ram_addr : OUT std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "ram_addr" +t "std_logic_vector" +b "(ADDR_WIDTH - 1 DOWNTO 0)" +o 12 +suid 22,0 +) +) +) +*109 (CptPort +uid 492,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 493,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,31625,67750,32375" +) +tg (CPTG +uid 494,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 495,0 +va (VaSet +) +xt "60400,31500,66000,32500" +st "config_started" +ju 2 +blo "66000,32300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 496,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,13400,37000,14200" +st "config_started : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_started" +t "std_logic" +o 4 +suid 23,0 +i "'0'" +) +) +) +*110 (CptPort +uid 528,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 529,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,32625,67750,33375" +) +tg (CPTG +uid 530,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 531,0 +va (VaSet +) +xt "58800,32500,66000,33500" +st "drs_address : (3:0)" +ju 2 +blo "66000,33300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 532,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,23800,33000,24600" +st "drs_address : OUT std_logic_vector (3 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 17 +suid 24,0 +) +) +) +*111 (CptPort +uid 533,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 534,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,33625,67750,34375" +) +tg (CPTG +uid 535,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 536,0 +va (VaSet +) +xt "58800,33500,66000,34500" +st "drs_address_mode" +ju 2 +blo "66000,34300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 537,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,24600,22000,25400" +st "drs_address_mode : OUT std_logic +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 18 +suid 25,0 +) +) +) +] +shape (Rectangle +uid 252,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "42000,14000,67000,35000" +) +oxt "42000,14000,66000,27000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "41950,27000,48150,28000" +st "FACT_FAD_lib" +blo "41950,27800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "41950,28000,49050,29000" +st "control_manager" +blo "41950,28800" +) +) +gi *112 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "41500,0,54500,4000" +st "Generic Declarations + +NO_OF_ROI integer 36 +NO_OF_DAC integer 8 +ADDR_WIDTH integer 8 +" +) +header "Generic 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328,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,2200,45000,3000" +st "clk : STD_LOGIC +" +) +) +*13 (Net +uid 329,0 +decl (Decl +n "ram_wren" +t "std_logic_VECTOR" +b "(0 DOWNTO 0)" +o 15 +suid 2,0 +) +declText (MLText +uid 330,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,16800,58500,17600" +st "SIGNAL ram_wren : std_logic_VECTOR(0 DOWNTO 0) +" +) +) +*14 (Net +uid 331,0 +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 2 +suid 3,0 +) +declText (MLText +uid 332,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,3000,55000,3800" +st "config_addr : std_logic_vector(7 DOWNTO 0) +" +) +) +*15 (Net +uid 333,0 +decl (Decl +n "ram_data_in" +t "std_logic_VECTOR" +b "(15 DOWNTO 0)" +o 13 +suid 4,0 +) +declText (MLText +uid 334,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,15200,59000,16000" +st "SIGNAL ram_data_in : std_logic_VECTOR(15 DOWNTO 0) +" +) +) +*16 (Net +uid 335,0 +decl (Decl +n "config_data_valid" +t "std_logic" +o 7 +suid 5,0 +) +declText (MLText +uid 336,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,7000,45000,7800" +st "config_data_valid : std_logic +" +) +) +*17 (Net +uid 337,0 +decl (Decl +n "config_busy" +t "std_logic" +o 6 +suid 6,0 +) +declText (MLText +uid 338,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,6200,45000,7000" +st "config_busy : std_logic +" +) +) +*18 (Net +uid 339,0 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 11 +suid 7,0 +) +declText (MLText +uid 340,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,12600,55500,13400" +st "config_data : std_logic_vector(15 DOWNTO 0) +" +) +) +*19 (Net +uid 341,0 +decl (Decl +n "roi_array" +t "roi_array_type" +o 10 +suid 8,0 +) +declText (MLText +uid 342,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,11800,47500,12600" +st "roi_array : roi_array_type +" +) +) +*20 (Net +uid 345,0 +decl (Decl +n "ram_addr" +t "std_logic_VECTOR" +b "(7 DOWNTO 0)" +o 12 +suid 10,0 +) +declText (MLText +uid 346,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,14400,58500,15200" +st "SIGNAL ram_addr : std_logic_VECTOR(7 DOWNTO 0) +" +) +) +*21 (Net +uid 347,0 +decl (Decl +n "config_wr_en" +t "std_logic" +o 5 +suid 11,0 +) +declText (MLText +uid 348,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,5400,45000,6200" +st "config_wr_en : std_logic +" +) +) +*22 (Net +uid 349,0 +decl (Decl +n "ram_data_out" +t "std_logic_VECTOR" +b "(15 DOWNTO 0)" +o 14 +suid 12,0 +) +declText (MLText +uid 350,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,16000,59000,16800" +st "SIGNAL ram_data_out : std_logic_VECTOR(15 DOWNTO 0) +" +) +) +*23 (Net +uid 351,0 +decl (Decl +n "dac_array" +t "dac_array_type" +o 9 +suid 13,0 +) +declText (MLText +uid 352,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,9400,47500,10200" +st "dac_array : dac_array_type +" +) +) +*24 (Net +uid 353,0 +decl (Decl +n "config_rd_en" +t "std_logic" +o 3 +suid 14,0 +) +declText (MLText +uid 354,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,3800,45000,4600" +st "config_rd_en : std_logic +" +) +) +*25 (Net +uid 355,0 +decl (Decl +n "config_start" +t "std_logic" +o 4 +suid 15,0 +) +declText (MLText +uid 356,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,4600,45000,5400" +st "config_start : std_logic +" +) +) +*26 (Net +uid 359,0 +decl (Decl +n "config_ready" +t "std_logic" +o 8 +suid 17,0 +) +declText (MLText +uid 360,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,7800,45000,8600" +st "config_ready : std_logic +" +) +) +*27 (PortIoIn +uid 361,0 +shape (CompositeShape +uid 362,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 363,0 +sl 0 +ro 270 +xt "2000,19625,3500,20375" +) +(Line +uid 364,0 +sl 0 +ro 270 +xt "3500,20000,4000,20000" +pts [ +"3500,20000" +"4000,20000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 365,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 366,0 +va (VaSet +) +xt "700,19500,2000,20500" +st "clk" +ju 2 +blo "2000,20300" +tm "WireNameMgr" +) +) +) +*28 (PortIoOut +uid 367,0 +shape (CompositeShape +uid 368,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 369,0 +sl 0 +ro 270 +xt "36500,28625,38000,29375" +) +(Line +uid 370,0 +sl 0 +ro 270 +xt "36000,29000,36500,29000" +pts [ +"36000,29000" +"36500,29000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 371,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 372,0 +va (VaSet +) +xt "39000,28500,44100,29500" +st "config_ready" +blo "39000,29300" +tm "WireNameMgr" +) +) +) +*29 (PortIoIn +uid 373,0 +shape (CompositeShape +uid 374,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 375,0 +sl 0 +ro 90 +xt "36500,29625,38000,30375" +) +(Line +uid 376,0 +sl 0 +ro 90 +xt "36000,30000,36500,30000" +pts [ +"36500,30000" +"36000,30000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 377,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 378,0 +va (VaSet +) +xt "39000,29500,43800,30500" +st "config_start" +blo "39000,30300" +tm "WireNameMgr" +) +) +) +*30 (PortIoInOut +uid 379,0 +shape (CompositeShape +uid 380,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Hexagon +uid 381,0 +sl 0 +xt "36500,24625,38000,25375" +) +(Line +uid 382,0 +sl 0 +xt "36000,25000,36500,25000" +pts [ +"36000,25000" +"36500,25000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 383,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 384,0 +va (VaSet +) +xt "39000,24500,43700,25500" +st "config_data" +blo "39000,25300" +tm "WireNameMgr" +) +) +) +*31 (PortIoIn +uid 385,0 +shape (CompositeShape +uid 386,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 387,0 +sl 0 +ro 90 +xt "36500,23625,38000,24375" +) +(Line +uid 388,0 +sl 0 +ro 90 +xt "36000,24000,36500,24000" +pts [ +"36500,24000" +"36000,24000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 389,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 390,0 +va (VaSet +) +xt "39000,23500,43800,24500" +st "config_addr" +blo "39000,24300" +tm "WireNameMgr" +) +) +) +*32 (PortIoIn +uid 391,0 +shape (CompositeShape +uid 392,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 393,0 +sl 0 +ro 90 +xt "36500,26625,38000,27375" +) +(Line +uid 394,0 +sl 0 +ro 90 +xt "36000,27000,36500,27000" +pts [ +"36500,27000" +"36000,27000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 395,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 396,0 +va (VaSet +) +xt "39000,26500,44300,27500" +st "config_wr_en" +blo "39000,27300" +tm "WireNameMgr" +) +) +) +*33 (PortIoIn +uid 397,0 +shape (CompositeShape +uid 398,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 399,0 +sl 0 +ro 90 +xt "36500,27625,38000,28375" +) +(Line +uid 400,0 +sl 0 +ro 90 +xt "36000,28000,36500,28000" +pts [ +"36500,28000" +"36000,28000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 401,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 402,0 +va (VaSet +) +xt "39000,27500,44200,28500" +st "config_rd_en" +blo "39000,28300" +tm "WireNameMgr" +) +) +) +*34 (PortIoOut +uid 403,0 +shape (CompositeShape +uid 404,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 405,0 +sl 0 +ro 270 +xt "36500,33625,38000,34375" +) +(Line +uid 406,0 +sl 0 +ro 270 +xt "36000,34000,36500,34000" +pts [ +"36000,34000" +"36500,34000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 407,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 408,0 +va (VaSet +) +xt "39000,33500,42700,34500" +st "dac_array" +blo "39000,34300" +tm "WireNameMgr" +) +) +) +*35 (PortIoOut +uid 409,0 +shape (CompositeShape +uid 410,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 411,0 +sl 0 +ro 270 +xt "36500,34625,38000,35375" +) +(Line +uid 412,0 +sl 0 +ro 270 +xt "36000,35000,36500,35000" +pts [ +"36000,35000" +"36500,35000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 413,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 414,0 +va (VaSet +) +xt "39000,34500,42400,35500" +st "roi_array" +blo "39000,35300" +tm "WireNameMgr" +) +) +) +*36 (PortIoOut +uid 415,0 +shape (CompositeShape +uid 416,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 417,0 +sl 0 +ro 270 +xt "36500,31625,38000,32375" +) +(Line +uid 418,0 +sl 0 +ro 270 +xt "36000,32000,36500,32000" +pts [ +"36000,32000" +"36500,32000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 419,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 420,0 +va (VaSet +) +xt "39000,31500,45600,32500" +st "config_data_valid" +blo "39000,32300" +tm "WireNameMgr" +) +) +) +*37 (PortIoOut +uid 421,0 +shape (CompositeShape +uid 422,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 423,0 +sl 0 +ro 270 +xt "36500,32625,38000,33375" +) +(Line +uid 424,0 +sl 0 +ro 270 +xt "36000,33000,36500,33000" +pts [ +"36000,33000" +"36500,33000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 425,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 426,0 +va (VaSet +) +xt "39000,32500,43800,33500" +st "config_busy" +blo "39000,33300" +tm "WireNameMgr" +) +) +) +*38 (SaComponent +uid 960,0 +optionalChildren [ +*39 (CptPort +uid 900,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 901,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "6250,23625,7000,24375" +) +tg (CPTG +uid 902,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 903,0 +va (VaSet +) +xt "8000,23500,9300,24500" +st "clk" +blo "8000,24300" +) +) +thePort (LogicalPort +decl (Decl +n "clk" +t "std_logic" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*40 (CptPort +uid 904,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 905,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,28625,32750,29375" +) +tg (CPTG +uid 906,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 907,0 +va (VaSet +) +xt "25900,28500,31000,29500" +st "config_ready" +ju 2 +blo "31000,29300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_ready" +t "std_logic" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +i "'0'" +) +) +) +*41 (CptPort +uid 908,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 909,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,29625,32750,30375" +) +tg (CPTG +uid 910,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 911,0 +va (VaSet +) +xt "26200,29500,31000,30500" +st "config_start" +ju 2 +blo "31000,30300" +) +) +thePort (LogicalPort +decl (Decl +n "config_start" +t "std_logic" +preAdd 0 +posAdd 0 +o 5 +suid 4,0 +) +) +) +*42 (CptPort +uid 912,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 913,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,24625,32750,25375" +) +tg (CPTG +uid 914,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 915,0 +va (VaSet +) +xt "23300,24500,31000,25500" +st "config_data : (15:0)" +ju 2 +blo "31000,25300" +) +) +thePort (LogicalPort +m 2 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 6 +suid 5,0 +i "(others => 'Z')" +) +) +) +*43 (CptPort +uid 916,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 917,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,23625,32750,24375" +) +tg (CPTG +uid 918,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 919,0 +va (VaSet +) +xt "17600,23500,31000,24500" +st "config_addr : (ADDR_WIDTH - 1:0)" +ju 2 +blo "31000,24300" +) +) +thePort (LogicalPort +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(ADDR_WIDTH - 1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 7 +suid 6,0 +) +) +) +*44 (CptPort +uid 920,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 921,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,26625,32750,27375" +) +tg (CPTG +uid 922,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 923,0 +va (VaSet +) +xt "25700,26500,31000,27500" +st "config_wr_en" +ju 2 +blo "31000,27300" +) +) +thePort (LogicalPort +decl (Decl +n "config_wr_en" +t "std_logic" +preAdd 0 +posAdd 0 +o 8 +suid 7,0 +) +) +) +*45 (CptPort +uid 924,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 925,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,27625,32750,28375" +) +tg (CPTG +uid 926,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 927,0 +va (VaSet +) +xt "25800,27500,31000,28500" +st "config_rd_en" +ju 2 +blo "31000,28300" +) +) +thePort (LogicalPort +decl (Decl +n "config_rd_en" +t "std_logic" +preAdd 0 +posAdd 0 +o 9 +suid 8,0 +) +) +) +*46 (CptPort +uid 928,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 929,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,31625,32750,32375" +) +tg (CPTG +uid 930,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 931,0 +va (VaSet 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8 ( integer ) +ADDR_WIDTH = 8 ( integer ) " +) +header "" +) +elements [ +(GiElement +name "NO_OF_ROI" +type "integer" +value "36" +) +(GiElement +name "NO_OF_DAC" +type "integer" +value "8" +) +(GiElement +name "ADDR_WIDTH" +type "integer" +value "8" +) +] +) +viewicon (ZoomableIcon +uid 969,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "7250,39250,8750,40750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*60 (SaComponent +uid 993,0 +optionalChildren [ +*61 (CptPort +uid 970,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 971,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42625,41250,43375,42000" +) +tg (CPTG +uid 972,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 973,0 +ro 270 +va (VaSet +) +xt "42500,43000,43500,44700" +st "clka" +ju 2 +blo "43300,43000" +) +) +thePort (LogicalPort +decl (Decl +n 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"ieee" +unitName "std_logic_1164" +itemName "ALL" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +itemName "ALL" +) +(DmPackageRef +library "FACT_FAD_LIB" +unitName "fad_definitions" +itemName "ALL" +) +] +instances [ +(Instance +name "I_control_manager" +duLibraryName "FACT_FAD_lib" +duName "control_manager" +elements [ +(GiElement +name "NO_OF_ROI" +type "integer" +value "36" +) +(GiElement +name "NO_OF_DAC" +type "integer" +value "8" +) +(GiElement +name "ADDR_WIDTH" +type "integer" +value "8" +) +] +mwi 0 +uid 960,0 +) +(Instance +name "I_control_ram" +duLibraryName "FACT_FAD_lib" +duName "controlRAM_16bit_x256" +elements [ +] +mwi 0 +uid 993,0 +) +] +libraryRefs [ +"ieee" +"FACT_FAD_LIB" +] +) +version "29.1" +appVersion "2009.2 (Build 10)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" +) +(vvPair +variable "d_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" +) +(vvPair +variable "date" +value "12.07.2010" +) +(vvPair +variable "day" +value "Mo" +) +(vvPair +variable "day_long" +value "Montag" +) +(vvPair +variable "dd" +value "12" +) +(vvPair +variable "entity_name" +value "control_unit" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "TU-CC4900F8C7D2" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "07" +) +(vvPair +variable "module_name" +value "control_unit" +) +(vvPair +variable "month" +value "Jul" +) +(vvPair +variable "month_long" +value "Juli" +) +(vvPair +variable "p" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "13:47:38" +) +(vvPair +variable "unit" +value "control_unit" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 52,0 +optionalChildren [ +*1 (Grouping +uid 9,0 +optionalChildren [ +*2 (CommentText +uid 11,0 +shape (Rectangle +uid 12,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "16000,76000,33000,77000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 13,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "16200,76000,25500,77000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 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"14000,68000,18000,69000" +text (MLText +uid 22,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "12200,74000,14300,75000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*6 (CommentText +uid 23,0 +shape (Rectangle +uid 24,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "33000,73000,53000,77000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 25,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "33200,73200,49900,75200" +st " +receive commands from Ethernet and provide necessary data (ROIs, DAC values etc.) +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*7 (CommentText +uid 26,0 +shape (Rectangle +uid 27,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "37000,72000,53000,73000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 28,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "37200,72000,41700,73000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*8 (CommentText +uid 29,0 +shape (Rectangle +uid 30,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "12000,72000,33000,74000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 31,0 +va (VaSet +fg "32768,0,0" +) +xt "19700,72000,25300,74000" +st " +TU Dortmund +Physik / EE +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*9 (CommentText +uid 32,0 +shape (Rectangle +uid 33,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "12000,75000,16000,76000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 34,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "12200,75000,14300,76000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*10 (CommentText +uid 35,0 +shape (Rectangle +uid 36,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "12000,76000,16000,77000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 37,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "12200,76000,14900,77000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*11 (CommentText +uid 38,0 +shape (Rectangle +uid 39,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "16000,75000,33000,76000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 40,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "16200,75000,28900,76000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 10,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "12000,72000,53000,77000" +) +oxt "14000,66000,55000,71000" +) +*12 (Net +uid 327,0 +decl (Decl +n "clk" +t "STD_LOGIC" +o 1 +suid 1,0 +) +declText (MLText +uid 328,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,2200,45000,3000" +st "clk : STD_LOGIC" +) +) +*13 (Net +uid 329,0 +decl (Decl +n "ram_wren" +t "std_logic_VECTOR" +b "(0 DOWNTO 0)" +o 15 +suid 2,0 +) +declText (MLText +uid 330,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,15200,58500,16000" +st "SIGNAL ram_wren : std_logic_VECTOR(0 DOWNTO 0)" +) +) +*14 (Net +uid 331,0 +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 2 +suid 3,0 +) +declText (MLText +uid 332,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,3000,55000,3800" +st "config_addr : std_logic_vector(7 DOWNTO 0)" +) +) +*15 (Net +uid 333,0 +decl (Decl +n "ram_data_in" +t "std_logic_VECTOR" +b "(15 DOWNTO 0)" +o 13 +suid 4,0 +) +declText (MLText +uid 334,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,13600,59000,14400" +st "SIGNAL ram_data_in : std_logic_VECTOR(15 DOWNTO 0)" +) +) +*16 (Net +uid 335,0 +decl (Decl +n "config_data_valid" +t "std_logic" +o 7 +suid 5,0 +) +declText (MLText +uid 336,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,7000,45000,7800" +st "config_data_valid : std_logic" +) +) +*17 (Net +uid 337,0 +decl (Decl +n "config_busy" +t "std_logic" +o 6 +suid 6,0 +) +declText (MLText +uid 338,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,6200,45000,7000" +st "config_busy : std_logic" +) +) +*18 (Net +uid 339,0 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 11 +suid 7,0 +) +declText (MLText +uid 340,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,11000,55500,11800" +st "config_data : std_logic_vector(15 DOWNTO 0)" +) +) +*19 (Net +uid 341,0 +decl (Decl +n "roi_array" +t "roi_array_type" +o 10 +suid 8,0 +) +declText (MLText +uid 342,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,10200,47500,11000" +st "roi_array : roi_array_type" +) +) +*20 (Net +uid 345,0 +decl (Decl +n "ram_addr" +t "std_logic_VECTOR" +b "(7 DOWNTO 0)" +o 12 +suid 10,0 +) +declText (MLText +uid 346,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,12800,58500,13600" +st "SIGNAL ram_addr : std_logic_VECTOR(7 DOWNTO 0)" +) +) +*21 (Net +uid 347,0 +decl (Decl +n "config_wr_en" +t "std_logic" +o 5 +suid 11,0 +) +declText (MLText +uid 348,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,5400,45000,6200" +st "config_wr_en : std_logic" +) +) +*22 (Net +uid 349,0 +decl (Decl +n "ram_data_out" +t "std_logic_VECTOR" +b "(15 DOWNTO 0)" +o 14 +suid 12,0 +) +declText (MLText +uid 350,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,14400,59000,15200" +st "SIGNAL ram_data_out : std_logic_VECTOR(15 DOWNTO 0)" +) +) +*23 (Net +uid 351,0 +decl (Decl +n "dac_array" +t "dac_array_type" +o 9 +suid 13,0 +) +declText (MLText +uid 352,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,9400,47500,10200" +st "dac_array : dac_array_type" +) +) +*24 (Net +uid 353,0 +decl (Decl +n "config_rd_en" +t "std_logic" +o 3 +suid 14,0 +) +declText (MLText +uid 354,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,3800,45000,4600" +st "config_rd_en : std_logic" +) +) +*25 (Net +uid 355,0 +decl (Decl +n "config_start" +t "std_logic" +o 4 +suid 15,0 +) +declText (MLText +uid 356,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,4600,45000,5400" +st "config_start : std_logic" +) +) +*26 (Net +uid 359,0 +decl (Decl +n "config_ready" +t "std_logic" +o 8 +suid 17,0 +) +declText (MLText +uid 360,0 +va (VaSet +font "Courier New,8,0" +) +xt "29000,7800,45000,8600" +st "config_ready : std_logic" +) +) +*27 (PortIoIn +uid 361,0 +shape (CompositeShape +uid 362,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 363,0 +sl 0 +ro 270 +xt "2000,19625,3500,20375" +) +(Line +uid 364,0 +sl 0 +ro 270 +xt "3500,20000,4000,20000" +pts [ +"3500,20000" +"4000,20000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 365,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 366,0 +va (VaSet +) +xt "700,19500,2000,20500" +st "clk" +ju 2 +blo "2000,20300" +tm "WireNameMgr" +) +) +) +*28 (PortIoOut +uid 367,0 +shape (CompositeShape +uid 368,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 369,0 +sl 0 +ro 270 +xt "36500,28625,38000,29375" +) +(Line +uid 370,0 +sl 0 +ro 270 +xt "36000,29000,36500,29000" +pts [ +"36000,29000" +"36500,29000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 371,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 372,0 +va (VaSet +) +xt "39000,28500,44100,29500" +st "config_ready" +blo "39000,29300" +tm "WireNameMgr" +) +) +) +*29 (PortIoIn +uid 373,0 +shape (CompositeShape +uid 374,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 375,0 +sl 0 +ro 90 +xt "36500,29625,38000,30375" +) +(Line +uid 376,0 +sl 0 +ro 90 +xt "36000,30000,36500,30000" +pts [ +"36500,30000" +"36000,30000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 377,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 378,0 +va (VaSet +) +xt "39000,29500,43800,30500" +st "config_start" +blo "39000,30300" +tm "WireNameMgr" +) +) +) +*30 (PortIoInOut +uid 379,0 +shape (CompositeShape +uid 380,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Hexagon +uid 381,0 +sl 0 +xt "36500,24625,38000,25375" +) +(Line +uid 382,0 +sl 0 +xt "36000,25000,36500,25000" +pts [ +"36000,25000" +"36500,25000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 383,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 384,0 +va (VaSet +) +xt "39000,24500,43700,25500" +st "config_data" +blo "39000,25300" +tm "WireNameMgr" +) +) +) +*31 (PortIoIn +uid 385,0 +shape (CompositeShape +uid 386,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 387,0 +sl 0 +ro 90 +xt "36500,23625,38000,24375" +) +(Line +uid 388,0 +sl 0 +ro 90 +xt "36000,24000,36500,24000" +pts [ +"36500,24000" +"36000,24000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 389,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 390,0 +va (VaSet +) +xt "39000,23500,43800,24500" +st "config_addr" +blo "39000,24300" +tm "WireNameMgr" +) +) +) +*32 (PortIoIn +uid 391,0 +shape (CompositeShape +uid 392,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 393,0 +sl 0 +ro 90 +xt "36500,26625,38000,27375" +) +(Line +uid 394,0 +sl 0 +ro 90 +xt "36000,27000,36500,27000" +pts [ +"36500,27000" +"36000,27000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 395,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 396,0 +va (VaSet +) +xt "39000,26500,44300,27500" +st "config_wr_en" +blo "39000,27300" +tm "WireNameMgr" +) +) +) +*33 (PortIoIn +uid 397,0 +shape (CompositeShape +uid 398,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 399,0 +sl 0 +ro 90 +xt "36500,27625,38000,28375" +) +(Line +uid 400,0 +sl 0 +ro 90 +xt "36000,28000,36500,28000" +pts [ +"36500,28000" +"36000,28000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 401,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 402,0 +va (VaSet +) +xt "39000,27500,44200,28500" +st "config_rd_en" +blo "39000,28300" +tm "WireNameMgr" +) +) +) +*34 (PortIoOut +uid 403,0 +shape (CompositeShape +uid 404,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 405,0 +sl 0 +ro 270 +xt "36500,33625,38000,34375" +) +(Line +uid 406,0 +sl 0 +ro 270 +xt "36000,34000,36500,34000" +pts [ +"36000,34000" +"36500,34000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 407,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 408,0 +va (VaSet +) +xt "39000,33500,42700,34500" +st "dac_array" +blo "39000,34300" +tm "WireNameMgr" +) +) +) +*35 (PortIoOut +uid 409,0 +shape (CompositeShape +uid 410,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 411,0 +sl 0 +ro 270 +xt "36500,34625,38000,35375" +) +(Line +uid 412,0 +sl 0 +ro 270 +xt "36000,35000,36500,35000" +pts [ +"36000,35000" +"36500,35000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 413,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 414,0 +va (VaSet +) +xt "39000,34500,42400,35500" +st "roi_array" +blo "39000,35300" +tm "WireNameMgr" +) +) +) +*36 (PortIoOut +uid 415,0 +shape (CompositeShape +uid 416,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 417,0 +sl 0 +ro 270 +xt "36500,31625,38000,32375" +) +(Line +uid 418,0 +sl 0 +ro 270 +xt "36000,32000,36500,32000" +pts [ +"36000,32000" +"36500,32000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 419,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 420,0 +va (VaSet +) +xt "39000,31500,45600,32500" +st "config_data_valid" +blo "39000,32300" +tm "WireNameMgr" +) +) +) +*37 (PortIoOut +uid 421,0 +shape (CompositeShape +uid 422,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 423,0 +sl 0 +ro 270 +xt "36500,32625,38000,33375" +) +(Line +uid 424,0 +sl 0 +ro 270 +xt "36000,33000,36500,33000" +pts [ +"36000,33000" +"36500,33000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 425,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 426,0 +va (VaSet +) +xt "39000,32500,43800,33500" +st "config_busy" +blo "39000,33300" +tm "WireNameMgr" +) +) +) +*38 (SaComponent +uid 960,0 +optionalChildren [ +*39 (CptPort +uid 900,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 901,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "6250,23625,7000,24375" +) +tg (CPTG +uid 902,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 903,0 +va (VaSet +) +xt "8000,23500,9300,24500" +st "clk" +blo "8000,24300" +) +) +thePort (LogicalPort +decl (Decl +n "clk" +t "std_logic" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*40 (CptPort +uid 904,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 905,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,28625,32750,29375" +) +tg (CPTG +uid 906,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 907,0 +va (VaSet +) +xt "25900,28500,31000,29500" +st "config_ready" +ju 2 +blo "31000,29300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_ready" +t "std_logic" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +i "'0'" +) +) +) +*41 (CptPort +uid 908,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 909,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,29625,32750,30375" +) +tg (CPTG +uid 910,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 911,0 +va (VaSet +) +xt "26200,29500,31000,30500" +st "config_start" +ju 2 +blo "31000,30300" +) +) +thePort (LogicalPort +decl (Decl +n "config_start" +t "std_logic" +preAdd 0 +posAdd 0 +o 5 +suid 4,0 +) +) +) +*42 (CptPort +uid 912,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 913,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,24625,32750,25375" +) +tg (CPTG +uid 914,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 915,0 +va (VaSet +) +xt "23300,24500,31000,25500" +st "config_data : (15:0)" +ju 2 +blo "31000,25300" +) +) +thePort (LogicalPort +m 2 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 6 +suid 5,0 +i "(others => 'Z')" +) +) +) +*43 (CptPort +uid 916,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 917,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,23625,32750,24375" +) +tg (CPTG +uid 918,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 919,0 +va (VaSet +) +xt "17600,23500,31000,24500" +st "config_addr : (ADDR_WIDTH - 1:0)" +ju 2 +blo "31000,24300" +) +) +thePort (LogicalPort +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(ADDR_WIDTH - 1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 7 +suid 6,0 +) +) +) +*44 (CptPort +uid 920,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 921,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,26625,32750,27375" +) +tg (CPTG +uid 922,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 923,0 +va (VaSet +) +xt "25700,26500,31000,27500" +st "config_wr_en" +ju 2 +blo "31000,27300" +) +) +thePort (LogicalPort +decl (Decl +n "config_wr_en" +t "std_logic" +preAdd 0 +posAdd 0 +o 8 +suid 7,0 +) +) +) +*45 (CptPort +uid 924,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 925,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,27625,32750,28375" +) +tg (CPTG +uid 926,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 927,0 +va (VaSet +) +xt "25800,27500,31000,28500" +st "config_rd_en" +ju 2 +blo "31000,28300" +) +) +thePort (LogicalPort +decl (Decl +n "config_rd_en" +t "std_logic" +preAdd 0 +posAdd 0 +o 9 +suid 8,0 +) +) +) +*46 (CptPort +uid 928,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 929,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,31625,32750,32375" +) +tg (CPTG +uid 930,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 931,0 +va (VaSet +) +xt "24400,31500,31000,32500" +st "config_data_valid" +ju 2 +blo "31000,32300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_data_valid" +t "std_logic" +preAdd 0 +posAdd 0 +o 10 +suid 9,0 +i "'0'" +) +) +) +*47 (CptPort +uid 932,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 933,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,32625,32750,33375" +) +tg (CPTG +uid 934,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 935,0 +va (VaSet +) +xt "26200,32500,31000,33500" +st "config_busy" +ju 2 +blo "31000,33300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_busy" +t "std_logic" +preAdd 0 +posAdd 0 +o 11 +suid 10,0 +i "'0'" +) +) +) +*48 (CptPort +uid 936,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 937,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,33625,32750,34375" +) +tg (CPTG +uid 938,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 939,0 +va (VaSet +) +xt "27300,33500,31000,34500" +st "dac_array" +ju 2 +blo "31000,34300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "dac_array" +t "dac_array_type" +preAdd 0 +posAdd 0 +o 15 +suid 15,0 +) +) +) +*49 (CptPort +uid 940,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 941,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,34625,32750,35375" +) +tg (CPTG +uid 942,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 943,0 +va (VaSet +) +xt "27600,34500,31000,35500" +st "roi_array" +ju 2 +blo "31000,35300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "roi_array" +t "roi_array_type" +preAdd 0 +posAdd 0 +o 16 +suid 16,0 +) +) +) +*50 (CptPort +uid 944,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 945,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,37625,32750,38375" +) +tg (CPTG +uid 946,0 +ps "CptPortTextPlaceStrategy" +stg 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1081,0 +va (VaSet +) +xt "25400,30500,31000,31500" +st "config_started" +ju 2 +blo "31000,31300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_started" +t "std_logic" +o 4 +suid 23,0 +i "'0'" +) +) +) +] +shape (Rectangle +uid 961,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "7000,23000,32000,42000" +) +oxt "42000,14000,67000,32000" +ttg (MlTextGroup +uid 962,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*55 (Text +uid 963,0 +va (VaSet +font "Arial,8,1" +) +xt "6950,42000,13150,43000" +st "FACT_FAD_lib" +blo "6950,42800" +tm "BdLibraryNameMgr" +) +*56 (Text +uid 964,0 +va (VaSet +font "Arial,8,1" +) +xt "6950,43000,14050,44000" +st "control_manager" +blo "6950,43800" +tm "CptNameMgr" +) +*57 (Text +uid 965,0 +va (VaSet +font "Arial,8,1" +) +xt "6950,44000,14650,45000" +st "I_control_manager" +blo "6950,44800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 966,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 967,0 +text (MLText +uid 968,0 +va (VaSet +font "Courier New,8,0" +) +xt "10000,20600,27500,23000" +st "NO_OF_ROI = 36 ( integer ) +NO_OF_DAC = 8 ( integer ) +ADDR_WIDTH = 8 ( integer ) " +) +header "" +) +elements [ +(GiElement +name "NO_OF_ROI" +type "integer" +value "36" +) +(GiElement +name "NO_OF_DAC" +type "integer" +value "8" +) +(GiElement +name "ADDR_WIDTH" +type "integer" +value "8" +) +] +) +viewicon (ZoomableIcon +uid 969,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "7250,40250,8750,41750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*58 (SaComponent +uid 993,0 +optionalChildren [ +*59 (CptPort +uid 970,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 971,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42625,41250,43375,42000" +) +tg (CPTG +uid 972,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 973,0 +ro 270 +va (VaSet +) +xt "42500,43000,43500,44700" +st "clka" +ju 2 +blo "43300,43000" +) +) +thePort (LogicalPort +decl (Decl +n "clka" +t "std_logic" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*60 (CptPort +uid 974,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 975,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "39250,45625,40000,46375" +) +tg (CPTG +uid 976,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 977,0 +va (VaSet +) +xt "41000,45500,45800,46500" +st "dina : (15:0)" +blo "41000,46300" +) +) +thePort (LogicalPort +decl (Decl +n "dina" +t "std_logic_VECTOR" +b "(15 downto 0)" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +) +) +) +*61 (CptPort +uid 978,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 979,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "39250,47625,40000,48375" +) +tg (CPTG +uid 980,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 981,0 +va (VaSet +) +xt "41000,47500,45900,48500" +st "addra : (7:0)" +blo "41000,48300" +) +) +thePort (LogicalPort +decl (Decl +n "addra" +t "std_logic_VECTOR" +b "(7 downto 0)" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +) +) +) +*62 (CptPort +uid 982,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 983,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "39250,46625,40000,47375" +) +tg (CPTG +uid 984,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 985,0 +va (VaSet +) +xt "41000,46500,45300,47500" +st "wea : (0:0)" +blo "41000,47300" +) +) +thePort (LogicalPort +decl (Decl +n "wea" +t "std_logic_VECTOR" +b "(0 downto 0)" +preAdd 0 +posAdd 0 +o 4 +suid 4,0 +) +) +) +*63 (CptPort +uid 986,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 987,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "50000,43625,50750,44375" +) +tg (CPTG +uid 988,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 989,0 +va (VaSet +) +xt "43800,43500,49000,44500" +st "douta : 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(FilterRowHdr +) +*179 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*180 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*181 (GroupColHdr +tm "GroupColHdrMgr" +) +*182 (NameColHdr +tm "GenericNameColHdrMgr" +) +*183 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*184 (InitColHdr +tm "GenericValueColHdrMgr" +) +*185 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*186 (EolColHdr +tm "GenericEolColHdrMgr" +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 95,0 +optionalChildren [ +*187 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *188 (MRCItem +litem &175 +pos 0 +dimension 20 +) +uid 97,0 +optionalChildren [ +*189 (MRCItem +litem &176 +pos 0 +dimension 20 +uid 98,0 +) +*190 (MRCItem +litem &177 +pos 1 +dimension 23 +uid 99,0 +) +*191 (MRCItem +litem &178 +pos 2 +hidden 1 +dimension 20 +uid 100,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 101,0 +optionalChildren [ +*192 (MRCItem +litem &179 +pos 0 +dimension 20 +uid 102,0 +) +*193 (MRCItem +litem &181 +pos 1 +dimension 50 +uid 103,0 +) +*194 (MRCItem +litem &182 +pos 2 +dimension 100 +uid 104,0 +) +*195 (MRCItem +litem &183 +pos 3 +dimension 100 +uid 105,0 +) +*196 (MRCItem +litem &184 +pos 4 +dimension 50 +uid 106,0 +) +*197 (MRCItem +litem &185 +pos 5 +dimension 50 +uid 107,0 +) +*198 (MRCItem +litem &186 +pos 6 +dimension 80 +uid 108,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 96,0 +vaOverrides [ +] +) +] +) +uid 82,0 +type 1 +) +activeModelName "BlockDiag" +) Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.info/Synthesis/Constraints/control_unit.ctr =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.info/Synthesis/Constraints/control_unit.ctr (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.info/Synthesis/Constraints/control_unit.ctr (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700a +# set_package fg484 +# set_speed -4 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.info/Synthesis/Constraints/control_unit.sdc =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.info/Synthesis/Constraints/control_unit.sdc (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.info/Synthesis/Constraints/control_unit.sdc (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700a +# set_package fg484 +# set_speed -4 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/symbol.sb =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/symbol.sb (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/symbol.sb (revision 9841) @@ -0,0 +1,2143 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +itemName "ALL" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +itemName "ALL" +) +(DmPackageRef +library "FACT_FAD_LIB" +unitName "fad_definitions" +itemName "ALL" +) +] +libraryRefs [ +"ieee" +"FACT_FAD_LIB" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 14,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 53,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +decl (Decl +n "clk" +t "STD_LOGIC" +o 1 +suid 1,0 +) +) +uid 109,0 +) +*15 (LogPort +port (LogicalPort +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 2 +suid 2,0 +) +) +uid 111,0 +) +*16 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "config_data_valid" +t "std_logic" +o 7 +suid 3,0 +) +) +uid 113,0 +) +*17 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "config_busy" +t "std_logic" +o 6 +suid 4,0 +) +) +uid 115,0 +) +*18 (LogPort +port (LogicalPort +m 2 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 14 +suid 5,0 +) +) +uid 117,0 +) +*19 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "roi_array" +t "roi_array_type" +o 13 +suid 6,0 +) +) +uid 119,0 +) +*20 (LogPort +port (LogicalPort +decl (Decl +n "config_wr_en" +t "std_logic" +o 5 +suid 7,0 +) +) +uid 121,0 +) +*21 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "dac_array" +t "dac_array_type" +o 10 +suid 8,0 +) +) +uid 123,0 +) +*22 (LogPort +port (LogicalPort +decl (Decl +n "config_rd_en" +t "std_logic" +o 3 +suid 9,0 +) +) +uid 125,0 +) +*23 (LogPort +port (LogicalPort +decl (Decl +n "config_start" +t "std_logic" +o 4 +suid 10,0 +) +) +uid 127,0 +) +*24 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "config_ready" +t "std_logic" +o 8 +suid 11,0 +) +) +uid 129,0 +) +*25 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "config_started" +t "std_logic" +o 9 +suid 12,0 +i "'0'" +) +) +uid 349,0 +) +*26 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 11 +suid 13,0 +) +) +uid 518,0 +) +*27 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 12 +suid 14,0 +) +) +uid 520,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 66,0 +optionalChildren [ +*28 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *29 (MRCItem +litem &1 +pos 11 +dimension 20 +) +uid 68,0 +optionalChildren [ +*30 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 69,0 +) +*31 (MRCItem +litem &3 +pos 1 +dimension 23 +uid 70,0 +) +*32 (MRCItem +litem &4 +pos 2 +hidden 1 +dimension 20 +uid 71,0 +) +*33 (MRCItem +litem &14 +pos 0 +dimension 20 +uid 108,0 +) +*34 (MRCItem +litem &15 +pos 1 +dimension 20 +uid 110,0 +) +*35 (MRCItem +litem &16 +pos 2 +dimension 20 +uid 112,0 +) +*36 (MRCItem +litem &17 +pos 3 +dimension 20 +uid 114,0 +) +*37 (MRCItem +litem &18 +pos 4 +dimension 20 +uid 116,0 +) +*38 (MRCItem +litem &19 +pos 5 +dimension 20 +uid 118,0 +) +*39 (MRCItem +litem &20 +pos 6 +dimension 20 +uid 120,0 +) +*40 (MRCItem +litem &21 +pos 7 +dimension 20 +uid 122,0 +) +*41 (MRCItem +litem &22 +pos 8 +dimension 20 +uid 124,0 +) +*42 (MRCItem +litem &23 +pos 9 +dimension 20 +uid 126,0 +) +*43 (MRCItem +litem &24 +pos 10 +dimension 20 +uid 128,0 +) +*44 (MRCItem +litem &25 +pos 11 +dimension 20 +uid 348,0 +) +*45 (MRCItem +litem &26 +pos 12 +dimension 20 +uid 517,0 +) +*46 (MRCItem +litem &27 +pos 13 +dimension 20 +uid 519,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 72,0 +optionalChildren [ +*47 (MRCItem +litem &5 +pos 0 +dimension 20 +uid 73,0 +) +*48 (MRCItem +litem &7 +pos 1 +dimension 50 +uid 74,0 +) +*49 (MRCItem +litem &8 +pos 2 +dimension 100 +uid 75,0 +) +*50 (MRCItem +litem &9 +pos 3 +dimension 50 +uid 76,0 +) +*51 (MRCItem +litem &10 +pos 4 +dimension 100 +uid 77,0 +) +*52 (MRCItem +litem &11 +pos 5 +dimension 100 +uid 78,0 +) +*53 (MRCItem +litem &12 +pos 6 +dimension 50 +uid 79,0 +) +*54 (MRCItem +litem &13 +pos 7 +dimension 80 +uid 80,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 67,0 +vaOverrides [ +] +) +] +) +uid 52,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *55 (LEmptyRow +) +uid 82,0 +optionalChildren [ +*56 (RefLabelRowHdr +) +*57 (TitleRowHdr +) +*58 (FilterRowHdr +) +*59 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*60 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*61 (GroupColHdr +tm "GroupColHdrMgr" +) +*62 (NameColHdr +tm "GenericNameColHdrMgr" +) +*63 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*64 (InitColHdr +tm "GenericValueColHdrMgr" +) +*65 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*66 (EolColHdr +tm "GenericEolColHdrMgr" +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 94,0 +optionalChildren [ +*67 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *68 (MRCItem +litem &55 +pos 0 +dimension 20 +) +uid 96,0 +optionalChildren [ +*69 (MRCItem +litem &56 +pos 0 +dimension 20 +uid 97,0 +) +*70 (MRCItem +litem &57 +pos 1 +dimension 23 +uid 98,0 +) +*71 (MRCItem +litem &58 +pos 2 +hidden 1 +dimension 20 +uid 99,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 100,0 +optionalChildren [ +*72 (MRCItem +litem &59 +pos 0 +dimension 20 +uid 101,0 +) +*73 (MRCItem +litem &61 +pos 1 +dimension 50 +uid 102,0 +) +*74 (MRCItem +litem &62 +pos 2 +dimension 100 +uid 103,0 +) +*75 (MRCItem +litem &63 +pos 3 +dimension 100 +uid 104,0 +) +*76 (MRCItem +litem &64 +pos 4 +dimension 50 +uid 105,0 +) +*77 (MRCItem +litem &65 +pos 5 +dimension 50 +uid 106,0 +) +*78 (MRCItem +litem &66 +pos 6 +dimension 80 +uid 107,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 95,0 +vaOverrides [ +] +) +] +) +uid 81,0 +type 1 +) +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" +) +(vvPair +variable "d_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" +) +(vvPair +variable "date" +value "12.07.2010" +) +(vvPair +variable "day" +value "Mo" +) +(vvPair +variable "day_long" +value "Montag" +) +(vvPair +variable "dd" +value "12" +) +(vvPair +variable "entity_name" +value "control_unit" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "TU-CC4900F8C7D2" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "07" +) +(vvPair +variable "module_name" +value "control_unit" +) +(vvPair +variable "month" +value "Jul" +) +(vvPair +variable "month_long" +value "Juli" +) +(vvPair +variable "p" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "14:13:34" +) +(vvPair +variable "unit" +value "control_unit" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 51,0 +optionalChildren [ +*79 (SymbolBody +uid 8,0 +optionalChildren [ +*80 (CptPort +uid 130,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 131,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,13625,15000,14375" +) +tg (CPTG +uid 132,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 133,0 +va (VaSet +) +xt "16000,13500,17300,14500" +st "clk" +blo "16000,14300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 134,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2000,65000,2800" +st "clk : IN STD_LOGIC ; +" +) +thePort (LogicalPort +decl (Decl +n "clk" +t "STD_LOGIC" +o 1 +suid 1,0 +) +) +) +*81 (CptPort +uid 135,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 136,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,13625,33750,14375" +) +tg (CPTG +uid 137,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 138,0 +va (VaSet +) +xt "25000,13500,32000,14500" +st "config_addr : (7:0)" +ju 2 +blo "32000,14300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 139,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2800,75000,3600" +st "config_addr : IN std_logic_vector (7 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 2 +suid 2,0 +) +) +) +*82 (CptPort +uid 140,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 141,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,20625,33750,21375" +) +tg (CPTG +uid 142,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 143,0 +va (VaSet +) +xt "25400,20500,32000,21500" +st "config_data_valid" +ju 2 +blo "32000,21300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 144,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6800,65000,7600" +st "config_data_valid : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_data_valid" +t "std_logic" +o 7 +suid 3,0 +) +) +) +*83 (CptPort +uid 145,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 146,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,21625,33750,22375" +) +tg (CPTG +uid 147,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 148,0 +va (VaSet +) +xt "27200,21500,32000,22500" +st "config_busy" +ju 2 +blo "32000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 149,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6000,65000,6800" +st "config_busy : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_busy" +t "std_logic" +o 6 +suid 4,0 +) +) +) +*84 (CptPort +uid 150,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 151,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,14625,33750,15375" +) +tg (CPTG +uid 152,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 153,0 +va (VaSet +) +xt "24300,14500,32000,15500" +st "config_data : (15:0)" +ju 2 +blo "32000,15300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 154,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,12400,74500,13200" +st "config_data : INOUT std_logic_vector (15 DOWNTO 0) +" +) +thePort (LogicalPort +m 2 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 14 +suid 5,0 +) +) +) +*85 (CptPort +uid 155,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 156,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,24625,33750,25375" +) +tg (CPTG +uid 157,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 158,0 +va (VaSet +) +xt "28600,24500,32000,25500" +st "roi_array" +ju 2 +blo "32000,25300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 159,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,11600,68000,12400" +st "roi_array : OUT roi_array_type ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "roi_array" +t "roi_array_type" +o 13 +suid 6,0 +) +) +) +*86 (CptPort +uid 160,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 161,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,16625,33750,17375" +) +tg (CPTG +uid 162,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 163,0 +va (VaSet +) +xt "26700,16500,32000,17500" +st "config_wr_en" +ju 2 +blo "32000,17300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 164,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,5200,65000,6000" +st "config_wr_en : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_wr_en" +t "std_logic" +o 5 +suid 7,0 +) +) +) +*87 (CptPort +uid 165,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 166,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,23625,33750,24375" +) +tg (CPTG +uid 167,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 168,0 +va (VaSet +) +xt "28300,23500,32000,24500" +st "dac_array" +ju 2 +blo "32000,24300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 169,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,9200,68000,10000" +st "dac_array : OUT dac_array_type ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "dac_array" +t "dac_array_type" +o 10 +suid 8,0 +) +) +) +*88 (CptPort +uid 170,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 171,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,17625,33750,18375" +) +tg (CPTG +uid 172,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 173,0 +va (VaSet +) +xt "26800,17500,32000,18500" +st "config_rd_en" +ju 2 +blo "32000,18300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 174,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3600,65000,4400" +st "config_rd_en : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_rd_en" +t "std_logic" +o 3 +suid 9,0 +) +) +) +*89 (CptPort +uid 175,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 176,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,19625,33750,20375" +) +tg (CPTG +uid 177,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 178,0 +va (VaSet +) +xt "27200,19500,32000,20500" +st "config_start" +ju 2 +blo "32000,20300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 179,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,4400,65000,5200" +st "config_start : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_start" +t "std_logic" +o 4 +suid 10,0 +) +) +) +*90 (CptPort +uid 180,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 181,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,18625,33750,19375" +) +tg (CPTG +uid 182,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 183,0 +va (VaSet +) +xt "26900,18500,32000,19500" +st "config_ready" +ju 2 +blo "32000,19300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 184,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,7600,65000,8400" +st "config_ready : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_ready" +t "std_logic" +o 8 +suid 11,0 +) +) +) +*91 (CptPort +uid 350,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 351,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,26625,33750,27375" +) +tg (CPTG +uid 352,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 353,0 +va (VaSet +) +xt "26400,26500,32000,27500" +st "config_started" +ju 2 +blo "32000,27300" +tm "CptPortNameMgr" +) +t (Text +uid 354,0 +va (VaSet +) +xt "30800,27500,32000,28500" +st "'0'" +ju 2 +blo "32000,28300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 355,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,8400,69000,9200" +st "config_started : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_started" +t "std_logic" +o 9 +suid 12,0 +i "'0'" +) +) +) +*92 (CptPort +uid 521,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 522,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,28625,33750,29375" +) +tg (CPTG +uid 523,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 524,0 +va (VaSet +) +xt "24800,28500,32000,29500" +st "drs_address : (3:0)" +ju 2 +blo "32000,29300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 525,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10000,75000,10800" +st "drs_address : OUT std_logic_vector (3 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 11 +suid 13,0 +) +) +) +*93 (CptPort +uid 526,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 527,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,30625,33750,31375" +) +tg (CPTG +uid 528,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 529,0 +va (VaSet +) +xt "24800,30500,32000,31500" +st "drs_address_mode" +ju 2 +blo "32000,31300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 530,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10800,65000,11600" +st "drs_address_mode : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 12 +suid 14,0 +) +) +) +] +shape (Rectangle +uid 301,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,13000,33000,32000" +) +oxt "15000,13000,33000,26000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "15200,26000,21400,27000" +st "FACT_FAD_lib" +blo "15200,26800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "15200,27000,20600,28000" +st "control_unit" +blo "15200,27800" +) +) +gi *94 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +*95 (Grouping +uid 16,0 +optionalChildren [ +*96 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48000,45500,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*97 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,44000,56200,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*98 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,46000,46200,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*99 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,46000,34300,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*100 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,45200,62400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*101 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,44000,61700,45000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*102 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "39700,44000,45300,46000" +st " +TU Dortmund +Physik / EE +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*103 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,47000,34300,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*104 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,48000,34900,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*105 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,47000,49300,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 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"dac_array" +ju 2 +blo "32000,24300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 169,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,8400,68000,9200" +st "dac_array : OUT dac_array_type ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "dac_array" +t "dac_array_type" +o 9 +suid 8,0 +) +) +) +*82 (CptPort +uid 170,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 171,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,17625,33750,18375" +) +tg (CPTG +uid 172,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 173,0 +va (VaSet +) +xt "26800,17500,32000,18500" +st "config_rd_en" +ju 2 +blo "32000,18300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 174,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3600,65000,4400" +st "config_rd_en : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "config_rd_en" +t "std_logic" +o 3 +suid 9,0 +) +) +) +*83 (CptPort +uid 175,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 176,0 +ro 270 +va (VaSet +vasetType 1 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New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *101 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,10800,44400,11800" +st "User:" +blo "42000,11600" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,11800,44000,11800" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 301,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol:CDM" +) Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/data@r@a@m_64b_16b_width14_5/symbol.sb =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/data@r@a@m_64b_16b_width14_5/symbol.sb (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/data@r@a@m_64b_16b_width14_5/symbol.sb (revision 9841) @@ -0,0 +1,1760 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr 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9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/data@r@m_64b_16b_width14/symbol.sb (revision 9841) @@ -0,0 +1,1758 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +itemName "ALL" +) +] +libraryRefs [ +"ieee" +"XilinxCoreLib" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 7,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 108,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +decl 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+(vvPair +variable "day" +value "Mo" +) +(vvPair +variable "day_long" +value "Montag" +) +(vvPair +variable "dd" +value "21" +) +(vvPair +variable "entity_name" +value "data_generator" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "TU-CC4900F8C7D2" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_PrecisionSynthesisDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "06" +) +(vvPair +variable "module_name" +value "data_generator" +) +(vvPair +variable "month" +value "Jun" +) +(vvPair +variable "month_long" +value "Juni" +) +(vvPair +variable "p" +value "C:\\FPGA_projects\\FACT_FAD_21062010\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\FPGA_projects\\FACT_FAD_21062010\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "14:50:41" +) +(vvPair +variable "unit" +value "data_generator" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 134,0 +optionalChildren [ +*129 (SymbolBody +uid 8,0 +optionalChildren [ +*130 (CptPort +uid 48,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 49,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,1625,37000,2375" +) +tg (CPTG +uid 50,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 51,0 +va (VaSet +) +xt "38000,1500,39300,2500" +st "clk" +blo "38000,2300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 52,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,12000,25500,12800" +st "clk : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "clk" +t "std_logic" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*131 (CptPort +uid 53,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 54,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,3625,58750,4375" +) +tg (CPTG +uid 55,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 56,0 +va (VaSet +) +xt "50800,3500,57000,4500" +st "data_out : (63:0)" +ju 2 +blo "57000,4300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 57,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,12800,35500,13600" +st "data_out : OUT std_logic_vector (63 downto 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "data_out" +t "std_logic_vector" +b "(63 downto 0)" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +) +) +) +*132 (CptPort +uid 58,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 59,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,2625,58750,3375" +) +tg (CPTG +uid 60,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 61,0 +va (VaSet +) +xt "42900,2500,57000,3500" +st "addr_out : (RAM_ADDR_WIDTH-1:0)" +ju 2 +blo "57000,3300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 62,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,13600,42500,14400" +st "addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "addr_out" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH-1 downto 0)" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +) +) +) +*133 (CptPort +uid 73,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 74,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,1625,58750,2375" +) +tg (CPTG +uid 75,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 76,0 +va (VaSet +) +xt "51200,1500,57000,2500" +st "write_ea : (0:0)" +ju 2 +blo "57000,2300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 77,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,14400,38500,15200" +st "write_ea : OUT std_logic_vector (0 downto 0) := \"0\" ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "write_ea" +t "std_logic_vector" +b "(0 downto 0)" +preAdd 0 +posAdd 0 +o 4 +suid 6,0 +i "\"0\"" +) +) +) +*134 (CptPort +uid 78,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 391,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,18625,58750,19375" +) +tg (CPTG +uid 80,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 81,0 +va (VaSet +) +xt "40700,18500,57000,19500" +st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)" +ju 2 +blo "57000,19300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 82,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,15200,42500,16000" +st "ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH-1 downto 0)" +preAdd 0 +posAdd 0 +o 5 +suid 7,0 +) +) +) +*135 (CptPort +uid 88,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 89,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,10625,37000,11375" +) +tg (CPTG +uid 90,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 91,0 +va (VaSet +) +xt "38000,10500,43900,11500" +st "board_id : (3:0)" +blo "38000,11300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 92,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,29600,35000,30400" +st "board_id : IN std_logic_vector (3 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "board_id" +t "std_logic_vector" +b "(3 downto 0)" +preAdd 0 +posAdd 0 +o 23 +suid 9,0 +) +) +) +*136 (CptPort +uid 93,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 94,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,11625,37000,12375" +) +tg (CPTG +uid 95,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 96,0 +va (VaSet +) +xt "38000,11500,44800,12500" +st "trigger_id : (47:0)" +blo "38000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 97,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,31200,35500,32000" +st "trigger_id : IN std_logic_vector (47 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "trigger_id" +t "std_logic_vector" +b "(47 downto 0)" +preAdd 0 +posAdd 0 +o 25 +suid 10,0 +) +) +) +*137 (CptPort +uid 98,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 99,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,6625,37000,7375" +) +tg (CPTG +uid 100,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 101,0 +va (VaSet +) +xt "38000,6500,40800,7500" +st "trigger" +blo "38000,7300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 102,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,32000,25500,32800" +st "trigger : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "trigger" +t "std_logic" +preAdd 0 +posAdd 0 +o 26 +suid 11,0 +) +) +) +*138 (CommentText +uid 106,0 +ps "EdgeToEdgeStrategy" +shape (Rectangle +uid 107,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "37000,2000,52000,6400" +) +oxt "37000,2000,52000,6000" +text (MLText +uid 108,0 +va (VaSet +fg "0,0,32768" +) +xt "37200,2200,51100,6200" +st " +-- -- Uncomment the following library declaration if instantiating +-- -- any Xilinx primitives in this code. +-- library UNISIM; +-- use UNISIM.VComponents.all; +" +tm "CommentText" +wrapOption 3 +visibleHeight 4400 +visibleWidth 15000 +) +included 1 +excludeCommentLeader 1 +) +*139 (CptPort +uid 285,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 286,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,12625,37000,13375" +) +tg (CPTG +uid 287,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 288,0 +va (VaSet +) +xt "38000,12500,43700,13500" +st "crate_id : (1:0)" +blo "38000,13300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 289,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,30400,35000,31200" +st "crate_id : IN std_logic_vector (1 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "crate_id" +t "std_logic_vector" +b "(1 downto 0)" +o 24 +suid 12,0 +) +) +) +*140 (CptPort +uid 402,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 403,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,14625,37000,15375" +) +tg (CPTG +uid 404,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 405,0 +va (VaSet +) +xt "38000,14500,43300,15500" +st "ram_write_ea" +blo "38000,15300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 406,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,16000,25500,16800" +st "ram_write_ea : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "ram_write_ea" +t "std_logic" +o 6 +suid 16,0 +) +) +) +*141 (CptPort +uid 407,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 408,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,20625,58750,21375" +) +tg (CPTG +uid 409,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 410,0 +va (VaSet +) +xt "50700,20500,57000,21500" +st "ram_write_ready" +ju 2 +blo "57000,21300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 411,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,16800,38500,17600" +st "ram_write_ready : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "ram_write_ready" +t "std_logic" +o 7 +suid 17,0 +i "'0'" +) +) +) +*142 (CptPort +uid 412,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 413,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,15625,37000,16375" +) +tg (CPTG +uid 414,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 415,0 +va (VaSet +) +xt "38000,15500,41000,16500" +st "roi_max" +blo "38000,16300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 416,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,25600,27000,26400" +st "roi_max : IN roi_max_type ; +" +) +thePort (LogicalPort +decl (Decl +n "roi_max" +t "roi_max_type" +o 18 +suid 18,0 +) +) +) +*143 (CptPort +uid 473,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 474,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,16625,37000,17375" +) +tg (CPTG +uid 475,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 476,0 +va (VaSet +) +xt "38000,16500,41400,17500" +st "roi_array" +blo "38000,17300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 477,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,24800,28000,25600" +st "roi_array : IN roi_array_type ; +" +) +thePort (LogicalPort +decl (Decl +n "roi_array" +t "roi_array_type" +o 17 +suid 19,0 +) +) +) +*144 (CptPort +uid 526,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 527,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,17625,37000,18375" +) +tg (CPTG +uid 528,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 529,0 +va (VaSet +) +xt "38000,17500,47100,18500" +st "package_length : (15:0)" +blo "38000,18300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 530,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,28800,35500,29600" +st "package_length : IN std_logic_vector (15 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "package_length" +t "std_logic_vector" +b "(15 downto 0)" +o 22 +suid 20,0 +) +) +) +*145 (CptPort +uid 637,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 638,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,21625,58750,22375" +) +tg (CPTG +uid 639,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 640,0 +va (VaSet +) +xt "53800,21500,57000,22500" +st "adc_oeb" +ju 2 +blo "57000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 641,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,36000,38500,36800" +st "adc_oeb : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "adc_oeb" +t "std_logic" +o 31 +suid 23,0 +i "'1'" +) +) +) +*146 (CptPort +uid 642,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 643,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,19625,37000,20375" +) +tg (CPTG +uid 644,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 645,0 +va (VaSet +) +xt "38000,19500,43500,20500" +st "adc_otr : (3:0)" +blo "38000,20300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 646,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,36800,35000,37600" +st "adc_otr : IN std_logic_vector (3 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "adc_otr" +t "std_logic_vector" +b "(3 downto 0)" +o 32 +suid 24,0 +) +) +) +*147 (CptPort +uid 676,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 677,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,22625,58750,23375" +) +tg (CPTG +uid 678,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 679,0 +va (VaSet +) +xt "48500,22500,57000,23500" +st "drs_channel_id : (3:0)" +ju 2 +blo "57000,23300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 680,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,37600,44500,38400" +st "drs_channel_id : OUT std_logic_vector (3 downto 0) := (others => '0') ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_channel_id" +t "std_logic_vector" +b "(3 downto 0)" +o 33 +suid 25,0 +i "(others => '0')" +) +) +) +*148 (CptPort +uid 681,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 682,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,23625,58750,24375" +) +tg (CPTG +uid 683,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 684,0 +va (VaSet +) +xt "52600,23500,57000,24500" +st "drs_clk_en" +ju 2 +blo "57000,24300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 685,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,39200,38500,40000" +st "drs_clk_en : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_clk_en" +t "std_logic" +o 35 +suid 26,0 +i "'0'" +) +) +) +*149 (CptPort +uid 801,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 802,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,24625,58750,25375" +) +tg (CPTG +uid 803,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 804,0 +va (VaSet +) +xt "50800,24500,57000,25500" +st "drs_read_s_cell" +ju 2 +blo "57000,25300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 805,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,40000,38500,40800" +st "drs_read_s_cell : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_read_s_cell" +t "std_logic" +o 36 +suid 33,0 +i "'0'" +) +) +) +*150 (CptPort +uid 806,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 807,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,20625,37000,21375" +) +tg (CPTG +uid 808,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 809,0 +va (VaSet +) +xt "38000,20500,46800,21500" +st "drs_read_s_cell_ready" +blo "38000,21300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 810,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,40800,25500,41600" +st "drs_read_s_cell_ready : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "drs_read_s_cell_ready" +t "std_logic" +o 37 +suid 34,0 +) +) +) +*151 (CptPort +uid 811,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 812,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,21625,37000,22375" +) +tg (CPTG +uid 813,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 814,0 +va (VaSet +) +xt "38000,21500,44400,22500" +st "drs_s_cell_array" +blo "38000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 815,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,41600,30500,42400" +st "drs_s_cell_array : IN drs_s_cell_array_type +" +) +thePort (LogicalPort +decl (Decl +n "drs_s_cell_array" +t "drs_s_cell_array_type" +o 38 +suid 35,0 +) +) +) +*152 (CptPort +uid 845,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 846,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,25625,58750,26375" +) +tg (CPTG +uid 847,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 848,0 +va (VaSet +) +xt "52700,25500,57000,26500" +st "drs_dwrite" +ju 2 +blo "57000,26300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 849,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,38400,38500,39200" +st "drs_dwrite : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_dwrite" +t "std_logic" +o 34 +suid 36,0 +i "'1'" +) +) +) +*153 (CptPort +uid 898,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 899,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,22625,37000,23375" +) +tg (CPTG +uid 900,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 901,0 +va (VaSet +) +xt "38000,22500,43900,23500" +st "adc_data_array" +blo "38000,23300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 902,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,35200,30500,36000" +st "adc_data_array : IN adc_data_array_type ; +" +) +thePort (LogicalPort +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 30 +suid 37,0 +) +) +) +*154 (CptPort +uid 958,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 959,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,23625,37000,24375" +) +tg (CPTG +uid 960,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 961,0 +va (VaSet +) +xt "38000,23500,44500,24500" +st "config_ready_cm" +blo "38000,24300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 962,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,20800,25500,21600" +st "config_ready_cm : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_ready_cm" +t "std_logic" +o 12 +suid 39,0 +) +) +) +*155 (CptPort +uid 963,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 964,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,27625,58750,28375" +) +tg (CPTG +uid 965,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 966,0 +va (VaSet +) +xt "50800,27500,57000,28500" +st "config_start_cm" +ju 2 +blo "57000,28300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 967,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,18400,38500,19200" +st "config_start_cm : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_start_cm" +t "std_logic" +o 9 +suid 40,0 +i "'0'" +) +) +) +*156 (CptPort +uid 1018,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1019,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,24625,37000,25375" +) +tg (CPTG +uid 1020,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1021,0 +va (VaSet +) +xt "38000,24500,41600,25500" +st "s_trigger" +blo "38000,25300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1022,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,32800,25500,33600" +st "s_trigger : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "s_trigger" +t "std_logic" +o 27 +suid 41,0 +) +) +) +*157 (CptPort +uid 1048,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1049,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,25625,37000,26375" +) +tg (CPTG +uid 1050,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1051,0 +va (VaSet +) +xt "38000,25500,44700,26500" +st "config_ready_mm" +blo "38000,26300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1052,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,20000,25500,20800" +st "config_ready_mm : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_ready_mm" +t "std_logic" +o 11 +suid 42,0 +) +) +) +*158 (CptPort +uid 1053,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1054,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,26625,37000,27375" +) +tg (CPTG +uid 1055,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1056,0 +va (VaSet +) +xt "38000,26500,44500,27500" +st "config_ready_spi" +blo "38000,27300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1057,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,21600,25500,22400" +st "config_ready_spi : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_ready_spi" +t "std_logic" +o 13 +suid 43,0 +) +) +) +*159 (CptPort +uid 1085,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1086,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,27625,37000,28375" +) +tg (CPTG +uid 1087,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1088,0 +va (VaSet +) +xt "38000,27500,43200,28500" +st "sensor_array" +blo "38000,28300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1089,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,26400,29500,27200" +st "sensor_array : IN sensor_array_type ; +" +) +thePort (LogicalPort +decl (Decl +n "sensor_array" +t "sensor_array_type" +o 19 +suid 44,0 +) +) +) +*160 (CptPort +uid 1090,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1091,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,28625,37000,29375" +) +tg (CPTG +uid 1092,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1093,0 +va (VaSet +) +xt "38000,28500,43300,29500" +st "sensor_ready" +blo "38000,29300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1094,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,27200,25500,28000" +st "sensor_ready : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "sensor_ready" +t "std_logic" +o 20 +suid 45,0 +) +) +) +*161 (CptPort +uid 1122,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1123,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,28625,58750,29375" +) +tg (CPTG +uid 1124,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1125,0 +va (VaSet +) +xt "50600,28500,57000,29500" +st "config_start_mm" +ju 2 +blo "57000,29300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1126,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,17600,38500,18400" +st "config_start_mm : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_start_mm" +t "std_logic" +o 8 +suid 46,0 +i "'0'" +) +) +) +*162 (CptPort +uid 1127,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1128,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,29625,58750,30375" +) +tg (CPTG +uid 1129,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1130,0 +va (VaSet +) +xt "50800,29500,57000,30500" +st "config_start_spi" +ju 2 +blo "57000,30300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1131,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,19200,38500,20000" +st "config_start_spi : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_start_spi" +t "std_logic" +o 10 +suid 47,0 +i "'0'" +) +) +) +*163 (CptPort +uid 1159,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1160,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,30625,58750,31375" +) +tg (CPTG +uid 1161,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1162,0 +va (VaSet +) +xt "51400,30500,57000,31500" +st "config_started" +ju 2 +blo "57000,31300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1163,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,34400,38500,35200" +st "config_started : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_started" +t "std_logic" +o 29 +suid 48,0 +i "'0'" +) +) +) +*164 (CptPort +uid 1164,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1165,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,29625,37000,30375" +) +tg (CPTG +uid 1166,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1167,0 +va (VaSet +) +xt "38000,29500,42600,30500" +st "new_config" +blo "38000,30300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1168,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,33600,25500,34400" +st "new_config : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "new_config" +t "std_logic" +o 28 +suid 49,0 +) +) +) +*165 (CptPort +uid 1196,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1197,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,30625,37000,31375" +) +tg (CPTG +uid 1198,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1199,0 +va (VaSet +) +xt "38000,30500,45000,31500" +st "config_started_cm" +blo "38000,31300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1200,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,23200,25500,24000" +st "config_started_cm : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_started_cm" +t "std_logic" +o 15 +suid 50,0 +) +) +) +*166 (CptPort +uid 1201,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1202,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,31625,37000,32375" +) +tg (CPTG +uid 1203,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1204,0 +va (VaSet +) +xt "38000,31500,45200,32500" +st "config_started_mm" +blo "38000,32300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1205,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22400,25500,23200" +st "config_started_mm : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_started_mm" +t "std_logic" +o 14 +suid 51,0 +) +) +) +*167 (CptPort +uid 1206,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1207,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,32625,37000,33375" +) +tg (CPTG +uid 1208,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1209,0 +va (VaSet +) +xt "38000,32500,45000,33500" +st "config_started_spi" +blo "38000,33300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1210,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,24000,25500,24800" +st "config_started_spi : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_started_spi" +t "std_logic" +o 16 +suid 52,0 +) +) +) +*168 (CptPort +uid 1240,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1241,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,33625,37000,34375" +) +tg (CPTG +uid 1242,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1243,0 +va (VaSet +) +xt "38000,33500,41700,34500" +st "dac_array" +blo "38000,34300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1244,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,28000,28000,28800" +st "dac_array : IN dac_array_type ; +" +) +thePort (LogicalPort +decl (Decl +n "dac_array" +t "dac_array_type" +o 21 +suid 53,0 +) +) +) +] +shape (Rectangle +uid 238,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "37000,1000,58000,35000" +) +oxt "37000,1000,51000,21000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "38300,21000,44500,22000" +st "FACT_FAD_lib" +blo "38300,21800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "38300,22000,44700,23000" +st "data_generator" +blo "38300,22800" +) +) +gi *169 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "37000,5200,52000,7600" +st "Generic Declarations + +RAM_ADDR_WIDTH integer 12 +" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "RAM_ADDR_WIDTH" +type "integer" +value "12" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +) +portVis (PortSigDisplay +) +) +*170 (Grouping +uid 16,0 +optionalChildren [ +*171 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "41000,29000,58000,30000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "41200,29000,50700,30000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*172 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "58000,25000,62000,26000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "58200,25000,61200,26000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*173 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "41000,27000,58000,28000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "41200,27000,51200,28000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*174 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "37000,27000,41000,28000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "37200,27000,39300,28000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*175 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "58000,26000,78000,30000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "58200,26200,67400,27200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*176 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "62000,25000,78000,26000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "62200,25000,66700,26000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*177 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "37000,25000,58000,27000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "44150,25500,50850,26500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*178 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "37000,28000,41000,29000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "37200,28000,39300,29000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*179 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "37000,29000,41000,30000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "37200,29000,39900,30000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*180 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "41000,28000,58000,29000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "41200,28000,55500,29000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "37000,25000,78000,30000" +) +oxt "14000,66000,55000,71000" +) +*181 (CommentText +uid 103,0 +shape (Rectangle +uid 104,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,-6000,33000,0" +) +text (MLText +uid 105,0 +va (VaSet +fg "0,0,32768" +font "Arial,10,0" +) +xt "200,-5800,32200,-600" +st " +Created using Mentor Graphics HDL2Graphics(TM) Technology +on - 16:03:02 10.02.2010 +from - D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hdl\\data_generator.vhd + +" +tm "CommentText" +wrapOption 3 +visibleHeight 5600 +visibleWidth 32600 +) +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *182 (PackageList +uid 131,0 +stg "VerticalLayoutStrategy" +textVec [ +*183 (Text +uid 132,0 +va (VaSet +font "arial,8,1" +) +xt "0,1000,5400,2000" +st "Package List" +blo "0,1800" +) +*184 (MLText +uid 133,0 +va (VaSet +) +xt "0,2000,15200,8000" +st "library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all;" +tm "PackageList" +) +] +) +windowSize "0,0,1015,690" +viewArea "0,0,0,0" +cachedDiagramExtent "0,0,0,0" +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) 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"C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\debouncer\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\debouncer" +) +(vvPair +variable "d_logical" +value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\debouncer" +) +(vvPair +variable "date" +value "22.06.2010" +) +(vvPair +variable "day" +value "Di" +) +(vvPair +variable "day_long" +value "Dienstag" +) +(vvPair +variable "dd" +value "22" +) +(vvPair +variable "entity_name" +value "debouncer" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable 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+) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "10:22:23" +) +(vvPair +variable "unit" +value "debouncer" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" 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"%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager" +) +(vvPair +variable "d_logical" +value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager" +) +(vvPair +variable "date" +value "02.07.2010" +) +(vvPair +variable "day" +value "Fr" +) +(vvPair +variable "day_long" +value "Freitag" +) +(vvPair +variable "dd" +value "02" +) +(vvPair +variable "entity_name" +value "memory_manager" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "TU-CC4900F8C7D2" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_PrecisionSynthesisDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "07" +) +(vvPair +variable "module_name" +value "memory_manager" +) +(vvPair +variable "month" +value "Jul" +) +(vvPair +variable "month_long" +value "Juli" +) +(vvPair +variable "p" +value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "10:38:11" +) +(vvPair +variable "unit" +value "memory_manager" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 58,0 +optionalChildren [ +*91 (SymbolBody +uid 8,0 +optionalChildren [ +*92 (CptPort +uid 51,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 52,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,7625,15000,8375" +) +tg (CPTG +uid 53,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 54,0 +va (VaSet +font "arial,8,0" +) +xt "16000,7500,21900,8500" +st "ram_start_addr" +blo "16000,8300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 55,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,15600,95500,16400" +st "ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH_64B-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 18 +suid 1,0 +i "(others => '0')" +) +) +) +*93 (CptPort +uid 138,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 139,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,8625,15000,9375" +) +tg (CPTG +uid 140,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 141,0 +va (VaSet +font "arial,8,0" +) +xt "16000,8500,17300,9500" +st "clk" +blo "16000,9300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 142,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2000,68000,2800" +st "clk : IN std_logic ; +" +) +thePort (LogicalPort +lang 2 +decl (Decl +n "clk" +t "std_logic" +o 1 +suid 2,0 +) +) +) +*94 (CommentText +uid 168,0 +ps "EdgeToEdgeStrategy" +shape (Rectangle +uid 169,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "42000,5600,57000,10600" +) +oxt "0,0,15000,5000" +text (MLText +uid 170,0 +va (VaSet +fg "0,0,32768" +font "arial,8,0" +) +xt "42200,5800,54900,9800" +st " +-- library UNISIM; +-- use UNISIM.VComponents.all; +-- USE IEEE.NUMERIC_STD.all; + +-- RAM_ADDR_WIDTH_64B is used for +-- output ram_start_addr + +-- RAM_ADDR_WIDTH_16B is used for +-- output wiz_ram_start_addr +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +included 1 +excludeCommentLeader 1 +) +*95 (CptPort +uid 194,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 195,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,9625,15000,10375" +) +tg (CPTG +uid 196,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 197,0 +va (VaSet +font "arial,8,0" +) +xt "16000,9500,20800,10500" +st "config_start" +blo "16000,10300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 198,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2800,68000,3600" +st "config_start : IN std_logic ; +" +) +thePort (LogicalPort +lang 2 +decl (Decl +n "config_start" +t "std_logic" +o 2 +suid 3,0 +) +) +) +*96 (CptPort +uid 224,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 225,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,6625,43750,7375" +) +tg (CPTG +uid 226,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 227,0 +va (VaSet +font "arial,8,0" +) +xt "36700,6500,42000,7500" +st "ram_write_ea" +ju 2 +blo "42000,7300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 228,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,5200,90500,6000" +st "ram_write_ea : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "ram_write_ea" +t "std_logic" +o 5 +suid 4,0 +i "'0'" +) +) +) +*97 (CptPort +uid 254,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 255,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,7625,43750,8375" +) +tg (CPTG +uid 256,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 257,0 +va (VaSet +font "arial,8,0" +) +xt "36900,7500,42000,8500" +st "config_ready" +ju 2 +blo "42000,8300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 258,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6000,90500,6800" +st "config_ready : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "config_ready" +t "std_logic" +o 6 +suid 5,0 +i "'0'" +) +) +) +*98 (CptPort +uid 284,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 409,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,10625,15000,11375" +) +tg (CPTG +uid 286,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 287,0 +va (VaSet +font "arial,8,0" +) +xt "16000,10500,25600,11500" +st "wiz_number_of_channels" +blo "16000,11300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 288,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10800,96500,11600" +st "wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0') ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_number_of_channels" +t "std_logic_vector" +b "(3 downto 0)" +o 12 +suid 6,0 +i "(others => '0')" +) +) +) +*99 (CptPort +uid 289,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 290,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,8625,43750,9375" +) +tg (CPTG +uid 291,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 292,0 +va (VaSet +font "arial,8,0" +) +xt "34600,8500,42000,9500" +st "wiz_ram_start_addr" +ju 2 +blo "42000,9300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 293,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,9200,96500,10000" +st "wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0') ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH_16B-1 downto 0)" +preAdd 0 +o 10 +suid 7,0 +i "(others => '0')" +) +) +) +*100 (CptPort +uid 294,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 295,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,9625,43750,10375" +) +tg (CPTG +uid 296,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 297,0 +va (VaSet +font "arial,8,0" +) +xt "36900,9500,42000,10500" +st "wiz_write_ea" +ju 2 +blo "42000,10300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 298,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,11600,90500,12400" +st "wiz_write_ea : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_ea" +t "std_logic" +o 13 +suid 8,0 +i "'0'" +) +) +) +*101 (CptPort +uid 299,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 300,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,10625,43750,11375" +) +tg (CPTG +uid 301,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 302,0 +va (VaSet +font "arial,8,0" +) +xt "36500,10500,42000,11500" +st "wiz_write_end" +ju 2 +blo "42000,11300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 303,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,13200,90500,14000" +st "wiz_write_end : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_end" +t "std_logic" +o 15 +suid 9,0 +i "'0'" +) +) +) +*102 (CptPort +uid 304,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 305,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,11625,43750,12375" +) +tg (CPTG +uid 306,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 307,0 +va (VaSet +font "arial,8,0" +) +xt "35400,11500,42000,12500" +st "wiz_write_header" +ju 2 +blo "42000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 308,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,12400,90500,13200" +st "wiz_write_header : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_header" +t "std_logic" +o 14 +suid 10,0 +i "'0'" +) +) +) +*103 (CptPort +uid 309,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 310,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,12625,43750,13375" +) +tg (CPTG +uid 311,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 312,0 +va (VaSet +font "arial,8,0" +) +xt "35600,12500,42000,13500" +st "wiz_write_length" +ju 2 +blo "42000,13300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 313,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10000,96500,10800" +st "wiz_write_length : OUT std_logic_vector (16 downto 0) := (others => '0') ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_length" +t "std_logic_vector" +b "(16 downto 0)" +o 11 +suid 11,0 +i "(others => '0')" +) +) +) +*104 (CptPort +uid 349,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 350,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,11625,15000,12375" +) +tg (CPTG +uid 351,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 352,0 +va (VaSet +font "arial,8,0" +) +xt "16000,11500,22300,12500" +st "ram_write_ready" +blo "16000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 353,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3600,68000,4400" +st "ram_write_ready : IN std_logic ; +" +) +thePort (LogicalPort +lang 2 +decl (Decl +n "ram_write_ready" +t "std_logic" +o 3 +suid 12,0 +) +) +) +*105 (CptPort +uid 379,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 380,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,12625,15000,13375" +) +tg (CPTG +uid 381,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 382,0 +va (VaSet +font "arial,8,0" +) +xt "16000,12500,19400,13500" +st "wiz_busy" +blo "16000,13300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 383,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,14000,68000,14800" +st "wiz_busy : IN std_logic ; +" +) +thePort (LogicalPort +lang 2 +decl (Decl +n "wiz_busy" +t "std_logic" +o 16 +suid 13,0 +) +) +) +*106 (CptPort +uid 433,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 434,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,13625,43750,14375" +) +tg (CPTG +uid 435,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 436,0 +va (VaSet +font "arial,8,0" +) +xt "39000,13500,42000,14500" +st "roi_max" +ju 2 +blo "42000,14300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 437,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,7600,109500,8400" +st "roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)) ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "roi_max" +t "roi_max_type" +posAdd 0 +o 8 +suid 14,0 +i "(others => conv_std_logic_vector (0, 11))" +) +) +) +*107 (CptPort +uid 569,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 570,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,13625,15000,14375" +) +tg (CPTG +uid 571,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 572,0 +va (VaSet +font "arial,8,0" +) +xt "16000,13500,19400,14500" +st "roi_array" +blo "16000,14300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 573,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,4400,70500,5200" +st "roi_array : IN roi_array_type ; +" +) +thePort (LogicalPort +lang 2 +decl (Decl +n "roi_array" +t "roi_array_type" +o 4 +suid 17,0 +) +) +) +*108 (CptPort +uid 622,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 623,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,14625,43750,15375" +) +tg (CPTG +uid 624,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 625,0 +va (VaSet +font "arial,8,0" +) +xt "35900,14500,42000,15500" +st "package_length" +ju 2 +blo "42000,15300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 626,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,8400,96500,9200" +st "package_length : OUT std_logic_vector (15 downto 0) := (others => '0') ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "package_length" +t "std_logic_vector" +b "(15 downto 0)" +o 9 +suid 18,0 +i "(others => '0')" +) +) +) +*109 (CptPort +uid 804,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 805,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,15625,43750,16375" +) +tg (CPTG +uid 806,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 807,0 +va (VaSet +font "arial,8,0" +) +xt "36400,15500,42000,16500" +st "config_started" +ju 2 +blo "42000,16300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 808,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6800,90500,7600" +st "config_started : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "config_started" +t "std_logic" +o 7 +suid 21,0 +i "'0'" +) +) +) +*110 (CptPort +uid 915,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 916,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,14625,15000,15375" +) +tg (CPTG +uid 917,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 918,0 +va (VaSet +font "arial,8,0" +) +xt "16000,14500,19000,15500" +st "wiz_ack" +blo "16000,15300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 919,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,14800,68000,15600" +st "wiz_ack : IN std_logic ; +" +) +thePort (LogicalPort +lang 2 +decl (Decl +n "wiz_ack" +t "std_logic" +o 17 +suid 22,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,43000,17000" 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+) +) +) +*85 (CptPort +uid 2410,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2411,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "250,14625,1000,15375" +) +tg (CPTG +uid 2412,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2413,0 +va (VaSet +) +xt "2000,14500,6200,15500" +st "trigger_in" +blo "2000,15300" +) +) +thePort (LogicalPort +decl (Decl +n "trigger_in" +t "STD_LOGIC" +prec "-- rst : in STD_LOGIC;" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +) +) +) +*86 (CptPort +uid 2414,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2415,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "13000,14625,13750,15375" +) +tg (CPTG +uid 2416,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2417,0 +va (VaSet +) +xt "7400,14500,12000,15500" +st "trigger_out" +ju 2 +blo "12000,15300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "trigger_out" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +i "'0'" +) +) +) +*87 (CommentText +uid 2418,0 +ps "EdgeToEdgeStrategy" +shape (Rectangle +uid 2419,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "500,3000,15500,7000" +) +oxt "24500,3000,39500,7000" +text (MLText +uid 2420,0 +va (VaSet +fg "0,0,32768" +) +xt "700,3200,13600,7200" +st " +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 15000 +) +included 1 +) +] +shape (Rectangle +uid 2422,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "1000,13000,13000,18000" +) +oxt "25000,13000,37000,18000" +ttg (MlTextGroup +uid 2423,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*88 (Text +uid 2424,0 +va (VaSet +font "Arial,8,1" +) +xt "1200,18000,12800,19000" +st "FACT_FAD_test_devices_lib" +blo "1200,18800" +tm "BdLibraryNameMgr" +) +*89 (Text +uid 2425,0 +va (VaSet +font "Arial,8,1" +) +xt "1200,19000,5600,20000" +st "debouncer" +blo "1200,19800" +tm "CptNameMgr" +) +*90 (Text +uid 2426,0 +va (VaSet +font "Arial,8,1" +) +xt "1200,20000,2200,21000" +st "I0" +blo "1200,20800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 2427,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 2428,0 +text (MLText +uid 2429,0 +va (VaSet +font "Courier New,8,0" +) +xt "500,6200,15500,7000" +st "WIDTH = 17 ( INTEGER ) +" +) +header "" +) +elements [ +(GiElement +name "WIDTH" +type "INTEGER" +value "17" +) +] +) +viewicon (ZoomableIcon +uid 2430,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "1250,16250,2750,17750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*91 (Net +uid 2431,0 +decl (Decl +n "trigger_out" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 20 +suid 48,0 +i "'0'" +) +declText (MLText +uid 2432,0 +va (VaSet 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"38000,39000,39700,40000" +st "sclk" +blo "38000,39800" +tm "WireNameMgr" +) +) +on &12 +) +*95 (Wire +uid 222,0 +shape (OrthoPolyLine +uid 223,0 +va (VaSet +vasetType 3 +) +xt "10000,40000,12250,40000" +pts [ +"12250,40000" +"10000,40000" +] +) +start &73 +end &14 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 226,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 227,0 +va (VaSet +isHidden 1 +) +xt "12000,39000,16200,40000" +st "clk_50MHz" +blo "12000,39800" +tm "WireNameMgr" +) +) +on &13 +) +*96 (Wire +uid 244,0 +shape (OrthoPolyLine +uid 245,0 +va (VaSet +vasetType 3 +) +xt "53750,22000,55000,22000" +pts [ +"53750,22000" +"55000,22000" +] +) +start &68 +end &17 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 248,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 249,0 +va (VaSet +isHidden 1 +) +xt "55000,21000,57000,22000" +st "miso" +blo "55000,21800" +tm "WireNameMgr" +) +) +on &82 +) +*97 (Wire +uid 252,0 +shape (OrthoPolyLine +uid 253,0 +va (VaSet +vasetType 3 +) +xt "53750,24000,55000,24000" +pts [ +"53750,24000" +"55000,24000" +] +) +start &61 +end &18 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 256,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 257,0 +va (VaSet +isHidden 1 +) +xt "55000,23000,57800,24000" +st "dac_cs" +blo "55000,23800" +tm "WireNameMgr" +) +) +on &15 +) +*98 (Wire +uid 260,0 +shape (OrthoPolyLine +uid 261,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "53750,29000,55000,29000" +pts [ +"53750,29000" +"55000,29000" +] +) +start &62 +end &19 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 264,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 265,0 +va (VaSet +isHidden 1 +) +xt "57000,28000,60900,29000" +st "sensor_cs" +blo "57000,28800" +tm "WireNameMgr" +) +) +on &16 +) +*99 (Wire +uid 451,0 +shape (OrthoPolyLine +uid 452,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "26750,28000,36250,29000" +pts [ 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0 +sf 1 +si 0 +tg (WTG +uid 1229,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1230,0 +va (VaSet +isHidden 1 +) +xt "7250,31000,12050,32000" +st "config_start" +blo "7250,31800" +tm "WireNameMgr" +) +) +on &26 +) +*102 (Wire +uid 1233,0 +shape (OrthoPolyLine +uid 1234,0 +va (VaSet +vasetType 3 +) +xt "4000,27000,8250,27000" +pts [ +"8250,27000" +"4000,27000" +] +) +start &41 +end &25 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1235,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1236,0 +va (VaSet +isHidden 1 +) +xt "10250,36000,15350,37000" +st "config_ready" +blo "10250,36800" +tm "WireNameMgr" +) +) +on &27 +) +*103 (Wire +uid 1245,0 +shape (OrthoPolyLine +uid 1246,0 +va (VaSet +vasetType 3 +) +xt "26750,30000,36250,32000" +pts [ +"26750,32000" +"32000,32000" +"32000,30000" +"36250,30000" +] +) +start &46 +end &64 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1247,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1248,0 +va (VaSet +) +xt "47000,25000,53700,26000" +st "dac_config_ready" +blo "47000,25800" +tm "WireNameMgr" +) +) +on &28 +) +*104 (Wire +uid 1251,0 +shape (OrthoPolyLine +uid 1252,0 +va (VaSet +vasetType 3 +) +xt "26750,25000,36250,26000" +pts [ +"26750,26000" +"29000,26000" +"29000,25000" +"36250,25000" +] +) +start &45 +end &63 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1253,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1254,0 +va (VaSet +) +xt "29000,24000,35400,25000" +st "dac_config_start" +blo "29000,24800" +tm "WireNameMgr" +) +) +on &29 +) +*105 (Wire +uid 1328,0 +shape (OrthoPolyLine +uid 1329,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "26750,23000,36250,23000" +pts [ +"36250,23000" +"26750,23000" +] +) +start &58 +end &49 +sat 32 +eat 32 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 1332,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1333,0 +va (VaSet +) +xt "29000,22000,34200,23000" +st "dac_id : (2:0)" +blo "29000,22800" +tm "WireNameMgr" +) +) +on &30 +) +*106 (Wire +uid 1336,0 +shape (OrthoPolyLine +uid 1337,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "26750,24000,36250,24000" +pts [ +"36250,24000" +"26750,24000" +] +) +start &59 +end &50 +sat 32 +eat 32 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 1340,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1341,0 +va (VaSet +) +xt "29000,23000,35300,24000" +st "sensor_id : (1:0)" +blo "29000,23800" +tm "WireNameMgr" +) +) +on &31 +) +*107 (Wire +uid 1344,0 +shape (OrthoPolyLine +uid 1345,0 +va (VaSet +vasetType 3 +) +xt "26750,26000,36250,27000" +pts [ +"26750,27000" +"32000,27000" +"32000,26000" +"36250,26000" +] +) +start &47 +end &65 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1348,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1349,0 +va (VaSet +) +xt "29000,25000,34000,26000" +st "sensor_start" +blo "29000,25800" +tm "WireNameMgr" +) +) +on &32 +) +*108 (Wire +uid 1352,0 +shape (OrthoPolyLine +uid 1353,0 +va (VaSet +vasetType 3 +) +xt "26750,31000,36250,33000" +pts [ +"36250,31000" +"33000,31000" +"33000,33000" +"26750,33000" +] +) +start &66 +end &48 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1356,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1357,0 +va (VaSet +) +xt "47000,26000,52000,27000" +st "sensor_valid" +blo "47000,26800" +tm "WireNameMgr" +) +) +on &33 +) +*109 (Wire +uid 1469,0 +shape (OrthoPolyLine +uid 1470,0 +va (VaSet +vasetType 3 +) +xt "4000,23000,8250,23000" +pts [ +"8250,23000" +"4000,23000" +] +) +start &39 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 1473,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1474,0 +va (VaSet +) +xt "5000,22000,6700,23000" +st "sclk" +blo "5000,22800" +tm "WireNameMgr" +) +) +on &12 +) +*110 (Wire +uid 1598,0 +shape (OrthoPolyLine +uid 1599,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "4000,29000,8250,29000" +pts [ +"8250,29000" +"4000,29000" +] +) +start &44 +end &34 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1600,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1601,0 +va (VaSet +isHidden 1 +) +xt "3250,32000,8450,33000" +st "sensor_array" +blo "3250,32800" +tm "WireNameMgr" +) +) +on &36 +) +*111 (Wire +uid 1604,0 +shape (OrthoPolyLine +uid 1605,0 +va (VaSet +vasetType 3 +) +xt "4000,28000,8250,28000" +pts [ +"8250,28000" +"4000,28000" +] +) +start &42 +end &35 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1606,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1607,0 +va (VaSet +isHidden 1 +) +xt "2250,35000,7550,36000" +st "sensor_ready" +blo "2250,35800" +tm "WireNameMgr" +) +) +on &37 +) +*112 (Wire +uid 2002,0 +shape (OrthoPolyLine +uid 2003,0 +va (VaSet +vasetType 3 +) +xt "32000,22000,36250,22000" +pts [ +"32000,22000" +"36250,22000" +] +) +end &57 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2004,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2005,0 +va (VaSet +) +xt "33000,21000,34700,22000" +st "sclk" +blo "33000,21800" +tm "WireNameMgr" +) +) +on &12 +) +*113 (Wire +uid 2310,0 +shape (OrthoPolyLine +uid 2311,0 +va (VaSet +vasetType 3 +) +xt "4000,25000,8250,25000" +pts [ +"8250,25000" +"4000,25000" +] +) +start &52 +end &79 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2314,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2315,0 +va (VaSet +isHidden 1 +) +xt "5000,24000,10600,25000" +st "config_started" +blo "5000,24800" +tm "WireNameMgr" +) +) +on &78 +) +*114 (Wire +uid 2357,0 +shape (OrthoPolyLine +uid 2358,0 +va (VaSet +vasetType 3 +) +xt "53750,23000,55000,23000" +pts [ +"53750,23000" +"55000,23000" +] +) +start &67 +end &81 +es 0 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2361,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2362,0 +va (VaSet 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+] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 95,0 +optionalChildren [ +*231 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *232 (MRCItem +litem &219 +pos 0 +dimension 20 +) +uid 97,0 +optionalChildren [ +*233 (MRCItem +litem &220 +pos 0 +dimension 20 +uid 98,0 +) +*234 (MRCItem +litem &221 +pos 1 +dimension 23 +uid 99,0 +) +*235 (MRCItem +litem &222 +pos 2 +hidden 1 +dimension 20 +uid 100,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 101,0 +optionalChildren [ +*236 (MRCItem +litem &223 +pos 0 +dimension 20 +uid 102,0 +) +*237 (MRCItem +litem &225 +pos 1 +dimension 50 +uid 103,0 +) +*238 (MRCItem +litem &226 +pos 2 +dimension 100 +uid 104,0 +) +*239 (MRCItem +litem &227 +pos 3 +dimension 100 +uid 105,0 +) +*240 (MRCItem +litem &228 +pos 4 +dimension 50 +uid 106,0 +) +*241 (MRCItem +litem &229 +pos 5 +dimension 50 +uid 107,0 +) +*242 (MRCItem +litem &230 +pos 6 +dimension 80 +uid 108,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 96,0 +vaOverrides [ +] +) +] +) +uid 82,0 +type 1 +) +activeModelName "BlockDiag" +) Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd.info/Synthesis/Constraints/spi_unit.ctr =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd.info/Synthesis/Constraints/spi_unit.ctr (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd.info/Synthesis/Constraints/spi_unit.ctr (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700a +# set_package fg484 +# set_speed -4 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd.info/Synthesis/Constraints/spi_unit.sdc =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd.info/Synthesis/Constraints/spi_unit.sdc (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd.info/Synthesis/Constraints/spi_unit.sdc (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700a +# set_package fg484 +# set_speed -4 Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/spi_interface/symbol.sb =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/spi_interface/symbol.sb (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/spi_interface/symbol.sb (revision 9841) @@ -0,0 +1,2014 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "FACT_FAD_lib" +unitName "fad_definitions" +) +] +libraryRefs [ +"ieee" +"FACT_FAD_lib" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 20,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 53,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "sclk" +t "std_logic" +o 8 +suid 1,0 +) +) +uid 109,0 +) +*15 (LogPort +port (LogicalPort +decl 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(MRCItem +litem &59 +pos 3 +dimension 100 +uid 104,0 +) +*72 (MRCItem +litem &60 +pos 4 +dimension 50 +uid 105,0 +) +*73 (MRCItem +litem &61 +pos 5 +dimension 50 +uid 106,0 +) +*74 (MRCItem +litem &62 +pos 6 +dimension 80 +uid 107,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 95,0 +vaOverrides [ +] +) +] +) +uid 81,0 +type 1 +) +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\spi_interface\\symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\spi_interface\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\spi_interface" +) +(vvPair +variable "d_logical" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\spi_interface" +) +(vvPair +variable "date" +value "16.06.2010" +) +(vvPair +variable "day" +value "Mi" +) +(vvPair +variable "day_long" +value "Mittwoch" +) +(vvPair +variable "dd" +value "16" +) +(vvPair +variable "entity_name" +value "spi_interface" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "TU-CC4900F8C7D2" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "06" +) +(vvPair +variable "module_name" +value "spi_interface" +) +(vvPair +variable "month" +value "Jun" +) +(vvPair +variable "month_long" +value "Juni" +) +(vvPair +variable "p" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\spi_interface\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\spi_interface\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "14:19:06" +) +(vvPair +variable "unit" +value "spi_interface" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 51,0 +optionalChildren [ +*75 (SymbolBody +uid 8,0 +optionalChildren [ +*76 (CptPort +uid 126,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 127,0 +ro 90 +va (VaSet +vasetType 1 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"16000,21300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 330,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2800,63500,3600" +st "config_start : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "config_start" +t "std_logic" +o 2 +suid 12,0 +) +) +) +*80 (CptPort +uid 819,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 820,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,16625,15000,17375" +) +tg (CPTG +uid 821,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 822,0 +va (VaSet +) +xt "16000,16500,21200,17500" +st "sensor_array" +blo "16000,17300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 823,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,8400,68000,9200" +st "sensor_array : OUT sensor_array_type ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sensor_array" +t "sensor_array_type" +o 9 +suid 13,0 +) +) +) +*81 (CptPort +uid 824,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 825,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt 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"14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "39700,44000,45300,46000" +st " +TU Dortmund +Physik / EE +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*97 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,47000,34300,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*98 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,48000,34900,49000" +st " +Edited: +" +tm "CommentText" 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+xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*102 (MLText +uid 50,0 +va (VaSet +) +xt "0,1000,14500,6000" +st "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all;" +tm "PackageList" +) +] +) +windowSize "264,255,1282,945" +viewArea "-9965,-7607,56352,40201" +cachedDiagramExtent "0,0,73000,49000" +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *103 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *104 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,11600,44400,12600" +st "User:" +blo "42000,12400" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,12600,44000,12600" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 1333,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/spi_interface/symbol.sb.bak =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/spi_interface/symbol.sb.bak (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/spi_interface/symbol.sb.bak (revision 9841) @@ -0,0 +1,1863 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "FACT_FAD_lib" +unitName "fad_definitions" +) +] +libraryRefs [ +"ieee" +"FACT_FAD_lib" +] +) +version "24.1" +appVersion "2009.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 17,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 53,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "sclk" +t "std_logic" +o 6 +suid 1,0 +) +) +uid 109,0 +) +*15 (LogPort +port (LogicalPort +m 2 +decl (Decl +n "sio" +t "std_logic" +preAdd 0 +posAdd 0 +o 10 +suid 3,0 +) +) +uid 113,0 +) +*16 (LogPort +port (LogicalPort +decl (Decl +n "dac_array" +t "dac_array_type" +o 3 +suid 10,0 +) +) +uid 196,0 +) +*17 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "config_ready" +t "std_logic" +o 4 +suid 11,0 +) +) +uid 318,0 +) +*18 (LogPort +port (LogicalPort +decl (Decl +n "config_start" +t "std_logic" +o 2 +suid 12,0 +) +) +uid 320,0 +) +*19 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "sensor_array" +t "sensor_array_type" +o 7 +suid 13,0 +) +) +uid 816,0 +) +*20 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "sensor_ready" +t "std_logic" +o 9 +suid 14,0 +) +) +uid 818,0 +) +*21 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "dac_cs" +t "std_logic" +o 5 +suid 15,0 +) +) +uid 1014,0 +) +*22 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "sensor_cs" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 8 +suid 16,0 +) +) +uid 1016,0 +) +*23 (LogPort +port (LogicalPort +decl (Decl +n "clk_50MHz" +t "std_logic" +preAdd 0 +posAdd 0 +o 1 +suid 17,0 +) +) +uid 1120,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 66,0 +optionalChildren [ +*24 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *25 (MRCItem +litem &1 +pos 10 +dimension 20 +) +uid 68,0 +optionalChildren [ +*26 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 69,0 +) +*27 (MRCItem +litem &3 +pos 1 +dimension 23 +uid 70,0 +) +*28 (MRCItem +litem &4 +pos 2 +hidden 1 +dimension 20 +uid 71,0 +) +*29 (MRCItem +litem &14 +pos 0 +dimension 20 +uid 108,0 +) +*30 (MRCItem +litem &15 +pos 2 +dimension 20 +uid 112,0 +) +*31 (MRCItem +litem &16 +pos 5 +dimension 20 +uid 195,0 +) +*32 (MRCItem +litem &17 +pos 7 +dimension 20 +uid 317,0 +) +*33 (MRCItem +litem &18 +pos 6 +dimension 20 +uid 319,0 +) +*34 (MRCItem +litem &19 +pos 8 +dimension 20 +uid 815,0 +) +*35 (MRCItem +litem &20 +pos 9 +dimension 20 +uid 817,0 +) +*36 (MRCItem +litem &21 +pos 3 +dimension 20 +uid 1013,0 +) +*37 (MRCItem +litem &22 +pos 4 +dimension 20 +uid 1015,0 +) +*38 (MRCItem +litem &23 +pos 1 +dimension 20 +uid 1119,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 72,0 +optionalChildren [ +*39 (MRCItem +litem &5 +pos 0 +dimension 20 +uid 73,0 +) +*40 (MRCItem +litem &7 +pos 1 +dimension 50 +uid 74,0 +) +*41 (MRCItem +litem &8 +pos 2 +dimension 100 +uid 75,0 +) +*42 (MRCItem +litem &9 +pos 3 +dimension 50 +uid 76,0 +) +*43 (MRCItem +litem &10 +pos 4 +dimension 100 +uid 77,0 +) +*44 (MRCItem +litem &11 +pos 5 +dimension 100 +uid 78,0 +) +*45 (MRCItem +litem &12 +pos 6 +dimension 50 +uid 79,0 +) +*46 (MRCItem +litem &13 +pos 7 +dimension 80 +uid 80,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 67,0 +vaOverrides [ +] +) +] +) +uid 52,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *47 (LEmptyRow +) +uid 82,0 +optionalChildren [ +*48 (RefLabelRowHdr +) +*49 (TitleRowHdr +) +*50 (FilterRowHdr +) +*51 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*52 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*53 (GroupColHdr +tm "GroupColHdrMgr" +) +*54 (NameColHdr +tm "GenericNameColHdrMgr" +) +*55 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*56 (InitColHdr +tm "GenericValueColHdrMgr" +) +*57 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*58 (EolColHdr +tm "GenericEolColHdrMgr" +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 94,0 +optionalChildren [ +*59 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *60 (MRCItem +litem &47 +pos 0 +dimension 20 +) +uid 96,0 +optionalChildren [ +*61 (MRCItem +litem &48 +pos 0 +dimension 20 +uid 97,0 +) +*62 (MRCItem +litem &49 +pos 1 +dimension 23 +uid 98,0 +) +*63 (MRCItem +litem &50 +pos 2 +hidden 1 +dimension 20 +uid 99,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 100,0 +optionalChildren [ +*64 (MRCItem +litem &51 +pos 0 +dimension 20 +uid 101,0 +) +*65 (MRCItem +litem &53 +pos 1 +dimension 50 +uid 102,0 +) +*66 (MRCItem +litem &54 +pos 2 +dimension 100 +uid 103,0 +) +*67 (MRCItem +litem &55 +pos 3 +dimension 100 +uid 104,0 +) +*68 (MRCItem +litem &56 +pos 4 +dimension 50 +uid 105,0 +) +*69 (MRCItem +litem &57 +pos 5 +dimension 50 +uid 106,0 +) +*70 (MRCItem +litem &58 +pos 6 +dimension 80 +uid 107,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 95,0 +vaOverrides [ +] +) +] +) +uid 81,0 +type 1 +) +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\spi_unit\\symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\spi_unit\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\spi_unit" +) +(vvPair +variable "d_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\spi_unit" +) +(vvPair +variable "date" +value "30.04.2010" +) +(vvPair +variable "day" +value "Fr" +) +(vvPair +variable "day_long" +value "Freitag" +) +(vvPair +variable "dd" +value "30" +) +(vvPair +variable "entity_name" +value "spi_unit" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "EEPC8" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "spi_unit" +) +(vvPair +variable "month" +value "Apr" +) +(vvPair +variable "month_long" +value "April" +) +(vvPair +variable "p" +value "D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\spi_unit\\symbol.sb" +) +(vvPair +variable "p_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\spi_unit\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$HDS_HOME/../Modeltech/win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "$HDS_HOME/../Precision/Mgc_home/bin" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "13:54:34" +) +(vvPair +variable "unit" +value "spi_unit" +) +(vvPair +variable "user" +value "Benjamin Krumm" +) +(vvPair +variable "version" +value "2009.1 (Build 12)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 51,0 +optionalChildren [ +*71 (SymbolBody +uid 8,0 +optionalChildren [ +*72 (CptPort +uid 126,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 127,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "30000,12625,30750,13375" +) +tg (CPTG +uid 128,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 129,0 +va (VaSet +) +xt "27300,12500,29000,13500" +st "sclk" +ju 2 +blo "29000,13300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 131,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6000,62500,6800" +st "sclk : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sclk" +t "std_logic" +o 6 +suid 1,0 +) +) +) +*73 (CptPort +uid 137,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 138,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "30000,13625,30750,14375" +) +tg (CPTG +uid 139,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 140,0 +va (VaSet +) +xt "27600,13500,29000,14500" +st "sio" +ju 2 +blo "29000,14300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 141,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,9200,61500,10000" +st "sio : INOUT std_logic " +) +thePort (LogicalPort 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(LogicalPort +m 1 +decl (Decl +n "sensor_ready" +t "std_logic" +o 9 +suid 14,0 +) +) +) +*79 (CptPort +uid 1017,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1018,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "30000,15625,30750,16375" +) +tg (CPTG +uid 1019,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1020,0 +va (VaSet +) +xt "26200,15500,29000,16500" +st "dac_cs" +ju 2 +blo "29000,16300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1021,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,5200,62500,6000" +st "dac_cs : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "dac_cs" +t "std_logic" +o 5 +suid 15,0 +) +) +) +*80 (CptPort +uid 1022,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1023,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "30000,16625,30750,17375" +) +tg (CPTG +uid 1024,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1025,0 +va (VaSet +) +xt "22500,16500,29000,17500" +st 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"C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "10:22:01" +) +(vvPair +variable "unit" +value "trigger_counter" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable 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/firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/w5300_modul/_symbol.sb._fpf (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/w5300_modul/_symbol.sb._fpf (revision 9841) @@ -0,0 +1,3 @@ +INCLUDE list { + DEFAULT atom 1 +} Index: /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/w5300_modul/symbol.sb =================================================================== --- /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/w5300_modul/symbol.sb (revision 9841) +++ /firmware/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/w5300_modul/symbol.sb (revision 9841) @@ -0,0 +1,3348 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "IEEE" +unitName "STD_LOGIC_1164" +itemName "ALL" +) +(DmPackageRef +library "IEEE" +unitName "STD_LOGIC_ARITH" +itemName "ALL" +) +(DmPackageRef +library "IEEE" +unitName "STD_LOGIC_UNSIGNED" +itemName "ALL" +) +(DmPackageRef +library "FACT_FAD_lib" +unitName "fad_definitions" +itemName "ALL" +) +] +libraryRefs [ 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"int" +blo "44000,6300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 92,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22400,23000,23200" +st "int : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "int" +t "std_logic" +preAdd 0 +posAdd 0 +o 9 +suid 9,0 +) +) +) +*122 (CptPort +uid 93,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 94,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,7625,43000,8375" +) +tg (CPTG +uid 95,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 96,0 +va (VaSet +) +xt "44000,7500,48900,8500" +st "write_length" +blo "44000,8300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 97,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,23200,33500,24000" +st "write_length : IN std_logic_vector (16 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "write_length" +t "std_logic_vector" +b "(16 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 10 +suid 10,0 +) +) +) +*123 (CptPort +uid 98,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 99,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,9625,43000,10375" +) +tg (CPTG +uid 100,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 101,0 +va (VaSet +) +xt "44000,9500,49900,10500" +st "ram_start_addr" +blo "44000,10300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 102,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,24000,40500,24800" +st "ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 11 +suid 11,0 +) +) +) +*124 (CptPort +uid 103,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 104,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,11625,43000,12375" +) +tg (CPTG +uid 105,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 106,0 +va (VaSet +) +xt "44000,11500,47500,12500" +st "ram_data" +blo "44000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 107,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,24800,33500,25600" +st "ram_data : IN std_logic_vector (15 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "ram_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 12 +suid 12,0 +) +) +) +*125 (CptPort +uid 108,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 109,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,17625,77750,18375" +) +tg (CPTG +uid 110,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 111,0 +va (VaSet +) +xt "72400,17500,76000,18500" +st "ram_addr" +ju 2 +blo "76000,18300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 112,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,25600,40500,26400" +st "ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "ram_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 13 +suid 13,0 +) +) +) +*126 (CptPort +uid 113,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 114,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,13625,43000,14375" +) +tg (CPTG +uid 115,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 116,0 +va (VaSet +) +xt "44000,13500,48100,14500" +st "data_valid" +blo "44000,14300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 117,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,26400,23000,27200" +st "data_valid : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "data_valid" +t "std_logic" +preAdd 0 +posAdd 0 +o 14 +suid 14,0 +) +) +) +*127 (CptPort +uid 118,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 119,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,19625,77750,20375" +) +tg (CPTG +uid 120,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 121,0 +va (VaSet +) +xt "74100,19500,76000,20500" +st "busy" +ju 2 +blo "76000,20300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 122,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,28000,37000,28800" +st "busy : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "busy" +t "std_logic" +preAdd 0 +posAdd 0 +o 16 +suid 15,0 +i "'1'" +) +) +) +*128 (CommentText +uid 299,0 +ps "EdgeToEdgeStrategy" +shape (Rectangle +uid 300,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,30800,15000,35800" +) +oxt "0,0,15000,5000" +text (MLText +uid 301,0 +va (VaSet +fg "0,0,32768" +) +xt "200,31000,13900,35000" +st " +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +included 1 +excludeCommentLeader 1 +) +*129 (CptPort +uid 348,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 349,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,14625,43000,15375" +) +tg (CPTG +uid 350,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 351,0 +va (VaSet +) +xt "44000,14500,49700,15500" +st "write_end_flag" +blo "44000,15300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 352,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,29600,23000,30400" +st "write_end_flag : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "write_end_flag" +t "std_logic" +o 18 +suid 18,0 +) +) +) +*130 (CptPort +uid 353,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 354,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,15625,43000,16375" +) +tg (CPTG +uid 355,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 356,0 +va (VaSet +) +xt "44000,15500,50800,16500" +st "write_header_flag" +blo "44000,16300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 357,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,28800,23000,29600" +st "write_header_flag : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "write_header_flag" +t "std_logic" +o 17 +suid 19,0 +) +) +) +*131 (CptPort +uid 385,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 386,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,16625,43000,17375" +) +tg (CPTG +uid 387,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 388,0 +va (VaSet +) +xt "44000,16500,49200,17500" +st "fifo_channels" +blo "44000,17300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 389,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,30400,33000,31200" +st "fifo_channels : IN std_logic_vector (3 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "fifo_channels" +t "std_logic_vector" +b "(3 downto 0)" +o 19 +suid 20,0 +) +) +) +*132 (CptPort +uid 491,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 492,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,20625,77750,21375" +) +tg (CPTG +uid 493,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 494,0 +va (VaSet +) +xt "74600,20500,76000,21500" +st "led" +ju 2 +blo "76000,21300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 495,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,20800,43000,21600" +st "led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 DOWNTO 0)" +posAdd 0 +o 7 +suid 22,0 +i "(OTHERS => '0')" +) +) +) +*133 (CptPort +uid 521,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 522,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,21625,77750,22375" +) +tg (CPTG +uid 523,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 524,0 +va (VaSet +) +xt "72400,21500,76000,22500" +st "s_trigger" +ju 2 +blo "76000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 525,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,31200,37000,32000" +st "s_trigger : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "s_trigger" +t "std_logic" +o 20 +suid 23,0 +i "'0'" +) +) +) +*134 (CptPort +uid 551,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 552,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,22625,77750,23375" +) +tg (CPTG +uid 553,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 554,0 +va (VaSet +) +xt "71200,22500,76000,23500" +st "config_addr" +ju 2 +blo "76000,23300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 555,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,33600,33000,34400" +st "config_addr : OUT std_logic_vector (7 downto 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(7 downto 0)" +o 23 +suid 24,0 +) +) +) +*135 (CptPort +uid 556,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 557,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,17625,43000,18375" +) +tg (CPTG +uid 558,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 559,0 +va (VaSet +) +xt "44000,17500,48800,18500" +st "config_busy" +blo "44000,18300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 560,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,36800,23000,37600" +st "config_busy : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_busy" +t "std_logic" +o 27 +suid 25,0 +) +) +) +*136 (CptPort +uid 561,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 639,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,23625,77750,24375" +) +tg (CPTG +uid 563,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 564,0 +va (VaSet +) +xt "71300,23500,76000,24500" +st "config_data" +ju 2 +blo "76000,24300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 565,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,34400,43000,35200" +st "config_data : INOUT std_logic_vector (15 downto 0) := (others => 'Z') ; +" +) +thePort (LogicalPort +m 2 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 downto 0)" +o 24 +suid 26,0 +i "(others => 'Z')" +) +) +) +*137 (CptPort +uid 566,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 567,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,18625,43000,19375" +) +tg (CPTG +uid 568,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 569,0 +va (VaSet +) +xt "44000,18500,49600,19500" +st "config_started" +blo "44000,19300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 570,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,32800,23000,33600" +st "config_started : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_started" +t "std_logic" +o 22 +suid 27,0 +) +) +) +*138 (CptPort +uid 571,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 572,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,24625,77750,25375" +) +tg (CPTG +uid 573,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 574,0 +va (VaSet +) +xt "70700,24500,76000,25500" +st "config_wr_en" +ju 2 +blo "76000,25300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 575,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,35200,37000,36000" +st "config_wr_en : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_wr_en" +t "std_logic" +o 25 +suid 28,0 +i "'0'" +) +) +) +*139 (CptPort +uid 576,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 577,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,25625,77750,26375" +) +tg (CPTG +uid 578,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 579,0 +va (VaSet +) +xt "71400,25500,76000,26500" +st "new_config" +ju 2 +blo "76000,26300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 580,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,32000,37000,32800" +st "new_config : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "new_config" +t "std_logic" +o 21 +suid 29,0 +i "'0'" +) +) +) +*140 (CptPort +uid 640,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 641,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,26625,77750,27375" +) +tg (CPTG +uid 642,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 643,0 +va (VaSet +) +xt "70800,26500,76000,27500" +st "config_rd_en" +ju 2 +blo "76000,27300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 644,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,36000,37000,36800" +st "config_rd_en : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_rd_en" +t "std_logic" +o 26 +suid 30,0 +i "'0'" +) +) +) +*141 (CptPort +uid 670,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 671,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,27625,77750,28375" +) +tg (CPTG +uid 672,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 673,0 +va (VaSet +) +xt "73000,27500,76000,28500" +st "denable" +ju 2 +blo "76000,28300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 674,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,37600,50500,38400" +st "denable : OUT std_logic := '0' ; -- default domino wave off +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "denable" +t "std_logic" +eolc "-- default domino wave off" +posAdd 0 +o 28 +suid 31,0 +i "'0'" +) +) +) +*142 (CptPort +uid 723,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 724,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,28625,77750,29375" +) +tg (CPTG +uid 725,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 726,0 +va (VaSet +) +xt "70600,28500,76000,29500" +st "dwrite_enable" +ju 2 +blo "76000,29300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 727,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,38400,48500,39200" +st "dwrite_enable : OUT std_logic := '0' ; -- default DWRITE low. +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "dwrite_enable" +t "std_logic" +eolc "-- default DWRITE low." +preAdd 0 +posAdd 0 +o 29 +suid 32,0 +i "'0'" +) +) +) +*143 (CptPort +uid 885,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 886,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,29625,77750,30375" +) +tg (CPTG +uid 887,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 888,0 +va (VaSet +) +xt "70400,29500,76000,30500" +st "data_valid_ack" +ju 2 +blo "76000,30300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 889,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,27200,37000,28000" +st "data_valid_ack : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "data_valid_ack" +t "std_logic" +o 15 +suid 34,0 +i "'0'" +) +) +) +*144 (CptPort +uid 917,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 918,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,30625,77750,31375" +) +tg (CPTG +uid 919,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 920,0 +va (VaSet +) +xt "71300,30500,76000,31500" +st "sclk_enable" +ju 2 +blo "76000,31300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 921,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,39200,48000,40000" +st "sclk_enable : OUT std_logic := '1' -- default DWRITE HIGH. +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sclk_enable" +t "std_logic" +eolc "-- default DWRITE HIGH." +posAdd 0 +o 30 +suid 35,0 +i "'1'" +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "43000,2000,77000,32000" +) +oxt "43000,2000,56000,22000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "47700,11000,53900,12000" +st "FACT_FAD_lib" +blo "47700,11800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "47700,12000,53400,13000" +st "w5300_modul" +blo "47700,12800" +) +) +gi *145 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "43000,200,58000,2600" +st "Generic Declarations + +RAM_ADDR_WIDTH integer 14 +" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "RAM_ADDR_WIDTH" +type "integer" +value "14" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*146 (Grouping +uid 16,0 +optionalChildren [ +*147 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "47000,30000,64000,31000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "47200,30000,56500,31000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*148 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "64000,26000,68000,27000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "64200,26000,67200,27000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*149 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "47000,28000,64000,29000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "47200,28000,57200,29000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*150 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "43000,28000,47000,29000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "43200,28000,45300,29000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*151 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "64000,27000,84000,31000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va 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+font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st 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"0,14000,0,14000" +tm "SyDeclarativeTextMgr" +) +) +lastUid 925,0 +activeModelName "Symbol:CDM" +) Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD.hdp =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD.hdp (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD.hdp (revision 9841) @@ -0,0 +1,50 @@ +[DesignChecker] +FACT_FAD_lib = $HDS_PROJECT_DIR\FACT_FAD_lib\designcheck +[ModelSim] +FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/work +FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/work +secureip = C:/FPGAdv82PS/Xilinx_Lib/secureip +simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim +unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro +unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim +XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib +[QuestaSim] +secureip = C:/FPGAdv82PS/Xilinx_Lib/secureip +simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim +unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro +unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim +XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib +[XilinxISE] +FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/ise +[hdl] +FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hdl +FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/hdl +unisim = $HDS_PROJECT_DIR/unisim/hdl +[hdl_vm] +FACT_FAD_TB_lib = $HDS_HOME/examples/hds_scratch/hds_repository/FACT_FAD_TB_lib/hdl_vm +[hds] +FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hds +FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/hds +unisim = $HDS_PROJECT_DIR/unisim/hds +[hds_settings] +default_library = FACT_FAD_lib +design_root = FACT_FAD_lib.FAD_Board(struct)@f@a@d_@board/struct.bd +project_description = FPGA design for data acquisition from FACT +version = 1 +[hds_vm] +FACT_FAD_TB_lib = $HDS_HOME/examples/hds_scratch/hds_repository/FACT_FAD_TB_lib/hds_vm +[library_files_inclusion] +FACT_FAD_lib = specify +FACT_FAD_TB_lib = all +[library_type] +FACT_FAD_lib = regular +FACT_FAD_TB_lib = regular +secureip = downstream_only +simprim = downstream_only +unimacro = downstream_only +unisim = standard +XilinxCoreLib = downstream_only +[protected_library_traversal] +unisim = no +[shared] +others = $HDS_TEAM_HOME/shared.hdp Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD.info/xilinxcorelib.lpf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD.info/xilinxcorelib.lpf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD.info/xilinxcorelib.lpf (revision 9841) @@ -0,0 +1,3 @@ +version "1.0" +pathExcludes [ +] Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_beha.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_beha.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_beha.vhd (revision 9841) @@ -0,0 +1,106 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:44:52 01/07/2010 +-- Design Name: +-- Module Name: adc_emulator - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +-- hds interface_start +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_unsigned.all; +USE ieee.std_logic_textio.all; +LIBRARY std; +USE std.textio.all; + +ENTITY adc_emulator IS + GENERIC( + INPUT_FILE : string := "filename" + ); + PORT( + clk : IN std_logic; + data : OUT std_logic_vector (11 downto 0); + otr : OUT std_logic; + oeb : IN std_logic + ); + +-- Declarations + +END adc_emulator ; + +architecture Behavioral of adc_emulator is + + -- type_rom_type has to be a multiple of 4 bit because HREAD is used + type type_shift_reg is array (0 to 7) of std_logic_vector(12 downto 0); + type type_rom_array is array (0 to 1024) of std_logic_vector(15 downto 0); + + -- 'InitRomFromFile' reads one column of 'rom_filename' and puts the returned value to 'rom(i)' + impure function InitRomFromFile (rom_filename : in string) return type_rom_array is + file rom_file : text open read_mode is rom_filename; + variable rom_file_line: line; + variable rom : type_rom_array; + begin + for i in 0 to 1023 loop + readline(rom_file, rom_file_line); + hread(rom_file_line, rom(i)); + end loop; + return rom; + end function InitRomFromFile; + + signal rom : type_rom_array := InitRomFromFile(INPUT_FILE); + signal rom_reg : type_shift_reg; + signal rom_addr : std_logic_vector(9 downto 0) := (others => '0'); + signal rom_data : std_logic_vector(12 downto 0); + +begin + + rom_data <= rom(conv_integer(rom_addr))(12 downto 0); + data <= rom_reg(7)(11 downto 0) when oeb = '0' else (others => 'Z'); + otr <= rom_reg(7)(12); + + fetch_data_proc: process(clk) + begin + if rising_edge(clk) then + if (oeb = '0') then + rom_addr <= rom_addr + 1; + else + rom_addr <= (others => '0'); + end if; + end if; + end process fetch_data_proc; + + + ad_conv_proc: process(clk) + begin + if rising_edge(clk) then + if (oeb = '0') then + if (conv_integer(rom_data) > 2**12-1) then + rom_reg(0) <= '1' & X"FFF"; -- set OTR flag when rom_data is too high and set adc value to max + else + rom_reg(0) <= rom_data; -- shifting input cause output is shifted 7 cycles + end if; + rom_reg(1) <= rom_reg(0); + rom_reg(2) <= rom_reg(1); + rom_reg(3) <= rom_reg(2); + rom_reg(4) <= rom_reg(3); + rom_reg(5) <= rom_reg(4); + rom_reg(6) <= rom_reg(5); + rom_reg(7) <= rom_reg(6); + end if; + end if; + end process ad_conv_proc; + +end Behavioral; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_beha.vhd.bak =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_beha.vhd.bak (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_beha.vhd.bak (revision 9841) @@ -0,0 +1,106 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:44:52 01/07/2010 +-- Design Name: +-- Module Name: adc_emulator - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +-- hds interface_start +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_unsigned.all; +USE ieee.std_logic_textio.all; +LIBRARY std; +USE std.textio.all; + +ENTITY adc_emulator IS + GENERIC( + INPUT_FILE : string := "filename" + ); + PORT( + clk : IN STD_LOGIC; + data : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); + otr : OUT STD_LOGIC; + oeb : IN STD_LOGIC + ); + +-- Declarations + +END adc_emulator ; + +architecture Behavioral of adc_emulator is + + -- type_rom_type has to be a multiple of 4 bit because HREAD is used + type type_shift_reg is array (0 to 7) of std_logic_vector(12 downto 0); + type type_rom_array is array (0 to 1024) of std_logic_vector(15 downto 0); + + -- 'InitRomFromFile' reads one column of 'rom_filename' and puts the returned value to 'rom(i)' + impure function InitRomFromFile (rom_filename : in string) return type_rom_array is + file rom_file : text open read_mode is rom_filename; + variable rom_file_line: line; + variable rom : type_rom_array; + begin + for i in 0 to 1023 loop + readline(rom_file, rom_file_line); + hread(rom_file_line, rom(i)); + end loop; + return rom; + end function InitRomFromFile; + + signal rom : type_rom_array := InitRomFromFile(INPUT_FILE); + signal rom_reg : type_shift_reg; + signal rom_addr : std_logic_vector(9 downto 0) := (others => '0'); + signal rom_data : std_logic_vector(12 downto 0); + +begin + + rom_data <= rom(conv_integer(rom_addr))(12 downto 0); + data <= rom_reg(7)(11 downto 0) when oeb = '0' else (others => 'Z'); + otr <= rom_reg(7)(12); + + fetch_data_proc: process(clk) + begin + if rising_edge(clk) then + if (oeb = '0') then + rom_addr <= rom_addr + 1; + else + rom_addr <= (others => '0'); + end if; + end if; + end process fetch_data_proc; + + + ad_conv_proc: process(clk) + begin + if rising_edge(clk) then + if (oeb = '0') then + if (conv_integer(rom_data) > 2**12-1) then + rom_reg(0) <= '1' & X"FFF"; -- set OTR flag when rom_data is too high and set adc value to max + else + rom_reg(0) <= rom_data; -- shifting input cause output is shifted 7 cycles + end if; + rom_reg(1) <= rom_reg(0); + rom_reg(2) <= rom_reg(1); + rom_reg(3) <= rom_reg(2); + rom_reg(4) <= rom_reg(3); + rom_reg(5) <= rom_reg(4); + rom_reg(6) <= rom_reg(5); + rom_reg(7) <= rom_reg(6); + end if; + end if; + end process ad_conv_proc; + +end Behavioral; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_tb_struct.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_tb_struct.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/adc_emulator_tb_struct.vhd (revision 9841) @@ -0,0 +1,112 @@ +-- VHDL Entity FACT_FAD_TB_lib.adc_emulator_tb.symbol +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 14:21:48 24.06.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +ENTITY adc_emulator_tb IS +-- Declarations + +END adc_emulator_tb ; + +-- +-- VHDL Architecture FACT_FAD_TB_lib.adc_emulator_tb.struct +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 14:21:48 24.06.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +USE ieee.std_logic_textio.all; +LIBRARY std; +USE std.textio.all; + +LIBRARY FACT_FAD_TB_lib; + +ARCHITECTURE struct OF adc_emulator_tb IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL clk : std_logic := '0'; + SIGNAL data : std_logic_vector(11 DOWNTO 0); + SIGNAL oeb : std_logic; + SIGNAL otr : std_logic; + + + -- Component Declarations + COMPONENT adc_emulator + GENERIC ( + INPUT_FILE : string := "filename" + ); + PORT ( + clk : IN STD_LOGIC ; + data : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); + otr : OUT STD_LOGIC ; + oeb : IN STD_LOGIC + ); + END COMPONENT; + COMPONENT clock_generator + GENERIC ( + clock_period : time := 20 ns; + reset_time : time := 50 ns + ); + PORT ( + clk : OUT std_logic := '0'; + rst : OUT std_logic := '0' + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : adc_emulator USE ENTITY FACT_FAD_TB_lib.adc_emulator; + FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb_adcTB_oeb + -- eb_adcTB_oeb 1: enable ADC + enable_proc: process + begin + oeb <= '1'; + wait for 1 us; + oeb <= '0'; + wait; + end process enable_proc; + + + -- Instance port mappings. + I_adcTB_adc : adc_emulator + GENERIC MAP ( + INPUT_FILE => "../memory_files/analog_input_ch0.txt" + ) + PORT MAP ( + clk => clk, + data => data, + otr => otr, + oeb => oeb + ); + I_adcTB_clock : clock_generator + GENERIC MAP ( + clock_period => 20 ns, + reset_time => 50 ns + ) + PORT MAP ( + clk => clk, + rst => OPEN + ); + +END struct; Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd (revision 9841) @@ -0,0 +1,60 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:40:20 01/07/2010 +-- Design Name: +-- Module Name: clock_generator - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +-- hds interface_start +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_unsigned.all; + +-- synthesis translate_off +ENTITY clock_generator IS + GENERIC( + clock_period : time := 20 ns; + reset_time : time := 50 ns + ); + PORT( + clk : out std_logic := '0'; + rst : out std_logic := '0' + ); +END clock_generator ; +-- hds interface_end + +architecture Behavioral of clock_generator is + +begin + + clock_gen_proc: process + begin + clk <= '0'; + wait for clock_period / 2; + clk <= '1'; + wait for clock_period / 2; + end process clock_gen_proc; + + reset_gen_proc: process + begin + rst <= '1'; + wait for reset_time; + rst <= '0'; + wait; + end process reset_gen_proc; + + +end Behavioral; +--synthesis translate_on Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd.bak =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd.bak (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd.bak (revision 9841) @@ -0,0 +1,64 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:40:20 01/07/2010 +-- Design Name: +-- Module Name: clock_generator - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +-- hds interface_start +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- synthesis translate_off +-- +ENTITY clock_generator IS + GENERIC( + clock_period : time := 20 ns; + reset_time : time := 50 ns + ); + PORT( + clk : OUT STD_LOGIC := '0'; + rst : OUT STD_LOGIC := '0' + ); + +-- Declarations + +END clock_generator ; +-- hds interface_end + +architecture Behavioral of clock_generator is + +begin + + clock_gen_proc: process + begin + clk <= '0'; + wait for clock_period / 2; + clk <= '1'; + wait for clock_period / 2; + end process clock_gen_proc; + + reset_gen_proc: process + begin + rst <= '1'; + wait for reset_time; + rst <= '0'; + wait; + end process reset_gen_proc; + + +end Behavioral; +--synthesis translate_on Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd (revision 9841) @@ -0,0 +1,281 @@ +-- VHDL Entity FACT_FAD_TB_lib.fad_main_tb.symbol +-- +-- Created: +-- by - dneise.UNKNOWN (TU-CC4900F8C7D2) +-- at - 15:53:42 30.06.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +ENTITY fad_main_tb IS +-- Declarations + +END fad_main_tb ; + +-- +-- VHDL Architecture FACT_FAD_TB_lib.fad_main_tb.struct +-- +-- Created: +-- by - dneise.UNKNOWN (TU-CC4900F8C7D2) +-- at - 15:53:42 30.06.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; +USE ieee.std_logic_textio.all; +LIBRARY std; +USE std.textio.all; + +LIBRARY FACT_FAD_lib; +LIBRARY FACT_FAD_TB_lib; + +ARCHITECTURE struct OF fad_main_tb IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL CLK_25_PS : std_logic; + SIGNAL CLK_50 : std_logic; + SIGNAL RSRLOAD : std_logic := '0'; + SIGNAL SRCLK : std_logic := '0'; + SIGNAL SROUT_in_0 : std_logic; + SIGNAL SROUT_in_1 : std_logic; + SIGNAL SROUT_in_2 : std_logic; + SIGNAL SROUT_in_3 : std_logic; + SIGNAL adc_data : std_logic_vector(11 DOWNTO 0); + SIGNAL adc_data_array : adc_data_array_type; + SIGNAL adc_oeb : std_logic; + SIGNAL adc_otr : STD_LOGIC; + SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0); + SIGNAL board_id : std_logic_vector(3 DOWNTO 0); + SIGNAL clk : STD_LOGIC; + SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); + SIGNAL dac_cs : std_logic; + SIGNAL denable : std_logic := '0'; -- default domino wave off + SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0'); + SIGNAL drs_dwrite : std_logic := '1'; + SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL mosi : std_logic := '0'; + SIGNAL sclk : std_logic; + SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); + SIGNAL sio : std_logic; + SIGNAL trigger : std_logic; + SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0); + SIGNAL wiz_cs : std_logic := '1'; + SIGNAL wiz_data : std_logic_vector(15 DOWNTO 0); + SIGNAL wiz_int : std_logic; + SIGNAL wiz_rd : std_logic := '1'; + SIGNAL wiz_reset : std_logic := '1'; + SIGNAL wiz_wr : std_logic := '1'; + + + -- Component Declarations + COMPONENT FAD_main + GENERIC ( + RAMADDRWIDTH64b : integer := 12 + ); + PORT ( + CLK : IN std_logic ; + SROUT_in_0 : IN std_logic ; + SROUT_in_1 : IN std_logic ; + SROUT_in_2 : IN std_logic ; + SROUT_in_3 : IN std_logic ; + adc_data_array : IN adc_data_array_type ; + adc_otr_array : IN std_logic_vector (3 DOWNTO 0); + board_id : IN std_logic_vector (3 DOWNTO 0); + crate_id : IN std_logic_vector (1 DOWNTO 0); + trigger : IN std_logic ; + wiz_int : IN std_logic ; + CLK_25_PS : OUT std_logic ; + CLK_50 : OUT std_logic ; + RSRLOAD : OUT std_logic := '0'; + SRCLK : OUT std_logic := '0'; + adc_oeb : OUT std_logic := '1'; + dac_cs : OUT std_logic ; + denable : OUT std_logic := '0'; -- default domino wave off + drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + drs_dwrite : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + mosi : OUT std_logic := '0'; + sclk : OUT std_logic ; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0); + wiz_addr : OUT std_logic_vector (9 DOWNTO 0); + wiz_cs : OUT std_logic := '1'; + wiz_rd : OUT std_logic := '1'; + wiz_reset : OUT std_logic := '1'; + wiz_wr : OUT std_logic := '1'; + sio : INOUT std_logic ; + wiz_data : INOUT std_logic_vector (15 DOWNTO 0) + ); + END COMPONENT; + COMPONENT adc_emulator + GENERIC ( + INPUT_FILE : string := "filename" + ); + PORT ( + clk : IN STD_LOGIC ; + data : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); + otr : OUT STD_LOGIC ; + oeb : IN STD_LOGIC + ); + END COMPONENT; + COMPONENT clock_generator + GENERIC ( + clock_period : time := 20 ns; + reset_time : time := 50 ns + ); + PORT ( + clk : OUT std_logic := '0'; + rst : OUT std_logic := '0' + ); + END COMPONENT; + COMPONENT max6662_emulator + GENERIC ( + DRS_TEMPERATURE : integer := 51 + ); + PORT ( + sclk : IN std_logic ; + sio : INOUT std_logic ; + sensor_cs : IN std_logic_vector (3 DOWNTO 0) + ); + END COMPONENT; + COMPONENT trigger_generator + GENERIC ( + TRIGGER_RATE : time := 1 ms; + PULSE_WIDTH : time := 20 ns + ); + PORT ( + trigger : OUT std_logic + ); + END COMPONENT; + COMPONENT w5300_emulator + PORT ( + addr : IN std_logic_vector (9 DOWNTO 0); + data : INOUT std_logic_vector (15 DOWNTO 0); + rd : IN std_logic ; + wr : IN std_logic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main; + FOR ALL : adc_emulator USE ENTITY FACT_FAD_TB_lib.adc_emulator; + FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator; + FOR ALL : max6662_emulator USE ENTITY FACT_FAD_TB_lib.max6662_emulator; + FOR ALL : trigger_generator USE ENTITY FACT_FAD_TB_lib.trigger_generator; + FOR ALL : w5300_emulator USE ENTITY FACT_FAD_TB_lib.w5300_emulator; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb_mainTB_ID + -- eb_ID 1: hard-wired IDs + board_id <= "0101"; + crate_id <= "01"; + + -- HDL Embedded Text Block 2 eb_mainTB_adc + -- eb_adc 2: ADC routing + adc_data_array(0) <= adc_data; + adc_data_array(1) <= adc_data; + adc_data_array(2) <= adc_data; + adc_data_array(3) <= adc_data; + adc_otr_array(0) <= adc_otr; + adc_otr_array(1) <= adc_otr; + adc_otr_array(2) <= adc_otr; + adc_otr_array(3) <= adc_otr; + + + -- Instance port mappings. + I_mainTB_FPGA : FAD_main + GENERIC MAP ( + RAMADDRWIDTH64b => 15 + ) + PORT MAP ( + CLK => clk, + SROUT_in_0 => SROUT_in_0, + SROUT_in_1 => SROUT_in_1, + SROUT_in_2 => SROUT_in_2, + SROUT_in_3 => SROUT_in_3, + adc_data_array => adc_data_array, + adc_otr_array => adc_otr_array, + board_id => board_id, + crate_id => crate_id, + trigger => trigger, + wiz_int => wiz_int, + CLK_25_PS => CLK_25_PS, + CLK_50 => CLK_50, + RSRLOAD => RSRLOAD, + SRCLK => SRCLK, + adc_oeb => adc_oeb, + dac_cs => dac_cs, + denable => denable, + drs_channel_id => drs_channel_id, + drs_dwrite => drs_dwrite, + led => led, + mosi => mosi, + sclk => sclk, + sensor_cs => sensor_cs, + wiz_addr => wiz_addr, + wiz_cs => wiz_cs, + wiz_rd => wiz_rd, + wiz_reset => wiz_reset, + wiz_wr => wiz_wr, + sio => sio, + wiz_data => wiz_data + ); + I_mainTB_adc : adc_emulator + GENERIC MAP ( + INPUT_FILE => "../memory_files/analog_input_ch0.txt" + ) + PORT MAP ( + clk => clk, + data => adc_data, + otr => adc_otr, + oeb => adc_oeb + ); + I_mainTB_clock : clock_generator + GENERIC MAP ( + clock_period => 20 ns, + reset_time => 50 ns + ) + PORT MAP ( + clk => clk, + rst => OPEN + ); + I_mainTB_max6662 : max6662_emulator + GENERIC MAP ( + DRS_TEMPERATURE => 51 + ) + PORT MAP ( + sclk => sclk, + sio => sio, + sensor_cs => sensor_cs + ); + I_mainTB_trigger : trigger_generator + GENERIC MAP ( + TRIGGER_RATE => 1 ms, + PULSE_WIDTH => 20 ns + ) + PORT MAP ( + trigger => trigger + ); + I_mainTB_w5300 : w5300_emulator + PORT MAP ( + addr => wiz_addr, + data => wiz_data, + rd => wiz_rd, + wr => wiz_wr + ); + +END struct; Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/max6662_emulator_beha.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/max6662_emulator_beha.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/max6662_emulator_beha.vhd (revision 9841) @@ -0,0 +1,65 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.spi_devices_emulator.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 09:26:11 28.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +ENTITY max6662_emulator IS + GENERIC( + DRS_TEMPERATURE : integer := 51 + ); + PORT( + sclk : in std_logic; + sio : inout std_logic; + sensor_cs : in std_logic_vector (3 DOWNTO 0) + ); + +-- Declarations + +END max6662_emulator ; + +ARCHITECTURE beha OF max6662_emulator IS + + signal data : std_logic_vector(15 downto 0) := (others => '0'); + signal spi_cycle_cnt : integer := 0; + signal temperature : integer range -55 to 150 := DRS_TEMPERATURE; + +BEGIN + + spi_cnt_proc: process (sclk) + begin + if rising_edge(sclk) then + if (sensor_cs /= "1111") then + spi_cycle_cnt <= spi_cycle_cnt + 1; + else + spi_cycle_cnt <= 0; + end if; + end if; + end process spi_cnt_proc; + + sensor_data_proc: process (spi_cycle_cnt, sclk) + begin + if falling_edge(sclk) then + sio <= 'Z'; + if (spi_cycle_cnt = 1) then + data <= '0' & conv_std_logic_vector(temperature + conv_integer(sensor_cs), 12) & "000"; + end if; + if (spi_cycle_cnt > 7) then + sio <= data(15); + data(15 downto 1) <= data(14 downto 0); + end if; + end if; + end process sensor_data_proc; + +END ARCHITECTURE beha; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/max6662_emulator_beha.vhd.bak =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/max6662_emulator_beha.vhd.bak (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/max6662_emulator_beha.vhd.bak (revision 9841) @@ -0,0 +1,65 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.spi_devices_emulator.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 09:26:11 28.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +ENTITY max6662_emulator IS + GENERIC( + DRS_TEMPERATURE : integer := 51 + ); + PORT( + sclk : IN std_logic; + sio : INOUT std_logic; + sensor_cs : IN std_logic_vector (3 DOWNTO 0) + ); + +-- Declarations + +END max6662_emulator ; + +ARCHITECTURE beha OF max6662_emulator IS + + signal data : std_logic_vector(15 downto 0) := (others => '0'); + signal spi_cycle_cnt : integer := 0; + signal temperature : integer range -55 to 150 := DRS_TEMPERATURE; + +BEGIN + + spi_cnt_proc: process (sclk) + begin + if rising_edge(sclk) then + if (sensor_cs /= "1111") then + spi_cycle_cnt <= spi_cycle_cnt + 1; + else + spi_cycle_cnt <= 0; + end if; + end if; + end process spi_cnt_proc; + + sensor_data_proc: process (spi_cycle_cnt, sclk) + begin + if falling_edge(sclk) then + sio <= 'Z'; + if (spi_cycle_cnt = 1) then + data <= '0' & conv_std_logic_vector(temperature + conv_integer(sensor_cs), 12) & "000"; + end if; + if (spi_cycle_cnt > 7) then + sio <= data(15); + data(15 downto 1) <= data(14 downto 0); + end if; + end if; + end process sensor_data_proc; + +END ARCHITECTURE beha; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/trigger__generator_beha.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/trigger__generator_beha.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/trigger__generator_beha.vhd (revision 9841) @@ -0,0 +1,42 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.simple_trigger.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 14:01:15 10.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +--USE ieee.NUMERIC_STD.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library FACT_FAD_lib; +use FACT_FAD_lib.fad_definitions.all; + +entity trigger_generator is + generic( + TRIGGER_RATE : time := 1 ms; + PULSE_WIDTH : time := 20 ns + ); + port( + trigger : out std_logic + ); +end trigger_generator ; + +architecture beha of trigger_generator is +begin + + trigger_proc: process + begin + trigger <= '0'; + wait for TRIGGER_RATE; + --trigger <= '1'; + wait for PULSE_WIDTH; + trigger <= '0'; + --wait; + end process trigger_proc; +end architecture beha; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/trigger__generator_beha.vhd.bak =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/trigger__generator_beha.vhd.bak (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/trigger__generator_beha.vhd.bak (revision 9841) @@ -0,0 +1,42 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.simple_trigger.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 14:01:15 10.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +--USE ieee.NUMERIC_STD.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library FACT_FAD_lib; +use FACT_FAD_lib.fad_definitions.all; + +entity trigger_generator is + generic( + TRIGGER_RATE : time := 1 ms; + PULSE_WIDTH : time := 20 ns + ); + port( + trigger : out std_logic + ); +end trigger_generator ; + +architecture beha of trigger_generator is +begin + + trigger_proc: process + begin + trigger <= '0'; + wait for TRIGGER_RATE; + trigger <= '1'; + wait for PULSE_WIDTH; + trigger <= '0'; + --wait; + end process trigger_proc; +end architecture beha; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd (revision 9841) @@ -0,0 +1,89 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.w5300_emulator.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 07:51:36 04.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +ENTITY w5300_emulator IS + PORT( + addr : in std_logic_vector (9 DOWNTO 0); + data : inout std_logic_vector (15 DOWNTO 0); + rd : in std_logic; + wr : in std_logic + ); + +-- Declarations + +END w5300_emulator ; + +architecture beha of w5300_emulator is + + signal open_done : std_logic_vector(7 downto 0) := (others => '0'); + signal data_temp : std_logic_vector(15 downto 0); + + signal RSR_0, RSR_1 : std_logic_vector (15 downto 0); + signal FIFOR_CNT : integer := 0; + +begin + + data <= data_temp when (rd = '0') else (others => 'Z'); + data_temp <= data when (wr = '0') else (others => 'Z'); + + set_proc : process + begin + RSR_0 <= X"0000"; + RSR_1 <= X"0000"; + wait for 250 us; + RSR_1 <= X"0001"; + wait for 200 us; + RSR_1 <= X"0002"; + wait; + end process set_proc; + + w5300_proc : process (addr) + begin + for i in 0 to 7 loop + if (addr = conv_integer(W5300_S0_SSR) + i * 64) then + if (open_done(i) = '0') then + data_temp <= X"0013"; + open_done(i) <= '1'; + else + data_temp <= X"0017"; + end if; + elsif (addr = conv_integer(W5300_S0_TX_FSR) + i * conv_integer(W5300_S_INC)) then + data_temp <= X"0000"; + elsif (addr = conv_integer(W5300_S0_TX_FSR + 2) + i * conv_integer(W5300_S_INC)) then + data_temp <= X"3C00"; + elsif (addr = conv_integer(W5300_S0_RX_RSR)) then + data_temp <= RSR_0; + elsif (addr = conv_integer(W5300_S0_RX_RSR) + 2) then + data_temp <= RSR_1; + elsif (addr = conv_integer(W5300_S0_RX_FIFOR)) then + if (FIFOR_CNT = 0) then + data_temp <= X"B000"; +-- FIFOR_CNT <= 1; + elsif (FIFOR_CNT = 1) then + data_temp <= X"0500"; + FIFOR_CNT <= 2; + elsif (FIFOR_CNT = 2) then + data_temp <= X"0000"; + end if; + else + null; + end if; + end loop; + end process w5300_proc; + + +end architecture beha; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd.bak =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd.bak (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd.bak (revision 9841) @@ -0,0 +1,89 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.w5300_emulator.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 07:51:36 04.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +ENTITY w5300_emulator IS + PORT( + addr : in std_logic_vector (9 DOWNTO 0); + data : inout std_logic_vector (15 DOWNTO 0); + rd : in std_logic; + wr : in std_logic + ); + +-- Declarations + +END w5300_emulator ; + +architecture beha of w5300_emulator is + + signal open_done : std_logic_vector(7 downto 0) := (others => '0'); + signal data_temp : std_logic_vector(15 downto 0); + + signal RSR_0, RSR_1 : std_logic_vector (15 downto 0); + signal FIFOR_CNT : integer := 0; + +begin + + data <= data_temp when (rd = '0') else (others => 'Z'); + data_temp <= data when (wr = '0') else (others => 'Z'); + + set_proc : process + begin + RSR_0 <= X"0000"; + RSR_1 <= X"0000"; + wait for 250 us; + RSR_1 <= X"0001"; + wait for 200 us; + RSR_1 <= X"0002"; + wait; + end process set_proc; + + w5300_proc : process (addr) + begin + for i in 0 to 7 loop + if (addr = conv_integer(W5300_S0_SSR) + i * 64) then + if (open_done(i) = '0') then + data_temp <= X"0013"; + open_done(i) <= '1'; + else + data_temp <= X"0017"; + end if; + elsif (addr = conv_integer(W5300_S0_TX_FSR) + i * conv_integer(W5300_S_INC)) then + data_temp <= X"0000"; + elsif (addr = conv_integer(W5300_S0_TX_FSR + 2) + i * conv_integer(W5300_S_INC)) then + data_temp <= X"3C00"; + elsif (addr = conv_integer(W5300_S0_RX_RSR)) then + data_temp <= RSR_0; + elsif (addr = conv_integer(W5300_S0_RX_RSR) + 2) then + data_temp <= RSR_1; + elsif (addr = conv_integer(W5300_S0_RX_FIFOR)) then + if (FIFOR_CNT = 0) then + data_temp <= X"A000"; +-- FIFOR_CNT <= 1; + elsif (FIFOR_CNT = 1) then + data_temp <= X"0500"; + FIFOR_CNT <= 2; + elsif (FIFOR_CNT = 2) then + data_temp <= X"0000"; + end if; + else + null; + end if; + end loop; + end process w5300_proc; + + +end architecture beha; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_adc_emulator_beha.vhd._fpf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_adc_emulator_beha.vhd._fpf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_adc_emulator_beha.vhd._fpf (revision 9841) @@ -0,0 +1,3 @@ +INCLUDE list { + DEFAULT atom 1 +} Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_clock_generator_beha.vhd._fpf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_clock_generator_beha.vhd._fpf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_clock_generator_beha.vhd._fpf (revision 9841) @@ -0,0 +1,3 @@ +INCLUDE list { + DEFAULT atom 1 +} Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_max6662_emulator_beha.vhd._fpf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_max6662_emulator_beha.vhd._fpf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_max6662_emulator_beha.vhd._fpf (revision 9841) @@ -0,0 +1,3 @@ +INCLUDE list { + DEFAULT atom 1 +} Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_trigger__generator_beha.vhd._fpf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_trigger__generator_beha.vhd._fpf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_trigger__generator_beha.vhd._fpf (revision 9841) @@ -0,0 +1,3 @@ +INCLUDE list { + DEFAULT atom 1 +} Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_w5300_emulator_beha.vhd._fpf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_w5300_emulator_beha.vhd._fpf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.hdlsidedata/_w5300_emulator_beha.vhd._fpf (revision 9841) @@ -0,0 +1,3 @@ +INCLUDE list { + DEFAULT atom 1 +} Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.xrf/adc_emulator_tb_struct.xrf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.xrf/adc_emulator_tb_struct.xrf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.xrf/adc_emulator_tb_struct.xrf (revision 9841) @@ -0,0 +1,125 @@ +DESIGN adc_emulator_tb +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN adc_emulator_tb +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN adc_emulator_tb +VIEW symbol.sb +GRAPHIC 1,0 13 0 +DESIGN adc_emulator_tb +VIEW symbol.sb +GRAPHIC 1,0 14 0 +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 17 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 41,0 26 0 +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 33 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 0,0 36 2 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 185,0 41 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 191,0 42 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 207,0 43 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 199,0 44 0 +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 45 +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 46 +LIBRARY FACT_FAD_TB_lib +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 138,0 48 0 +DESIGN adc_emulator +VIEW symbol.sb +GRAPHIC 14,0 49 1 +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 48,0 53 0 +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 53,0 54 0 +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 58,0 55 0 +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 63,0 56 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 175,0 59 0 +DESIGN clock_generator +VIEW symbol.sb +GRAPHIC 14,0 60 1 +DESIGN clock_generator +VIEW @behavioral +GRAPHIC 48,0 65 0 +DESIGN clock_generator +VIEW @behavioral +GRAPHIC 53,0 66 0 +LIBRARY FACT_FAD_TB_lib +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 69 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 138,0 72 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 175,0 73 0 +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 76 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 223,0 79 0 +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 88 +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 89 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 138,0 91 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 145,0 92 1 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 187,0 96 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 193,0 97 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 201,0 98 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 209,0 99 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 175,0 101 0 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 182,0 102 1 +DESIGN adc_emulator_tb +VIEW struct.bd +GRAPHIC 187,0 107 0 +DESIGN adc_emulator_tb +VIEW struct.bd +NO_GRAPHIC 111 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.xrf/fad_main_tb_struct.xrf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.xrf/fad_main_tb_struct.xrf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/.xrf/fad_main_tb_struct.xrf (revision 9841) @@ -0,0 +1,507 @@ +DESIGN fad_main_tb +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN fad_main_tb +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN fad_main_tb +VIEW symbol.sb +GRAPHIC 1,0 13 0 +DESIGN fad_main_tb +VIEW symbol.sb +GRAPHIC 1,0 14 0 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 17 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 41,0 26 0 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 36 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 0,0 40 2 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 823,0 45 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 831,0 46 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 855,0 47 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 863,0 48 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 871,0 49 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 879,0 50 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 887,0 51 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 895,0 52 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 568,0 53 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 536,0 54 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 544,0 55 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 560,0 56 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 528,0 57 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 440,0 58 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 284,0 59 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 448,0 60 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 799,0 61 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 815,0 62 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 839,0 63 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 847,0 64 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 775,0 65 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 807,0 66 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 378,0 67 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 372,0 68 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 384,0 69 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 424,0 70 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 316,0 71 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 783,0 72 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 322,0 73 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 791,0 74 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 328,0 75 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 767,0 76 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 334,0 77 0 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 78 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 79 +LIBRARY FACT_FAD_lib +DESIGN @f@a@d_main +VIEW struct +GRAPHIC 233,0 81 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 14,0 82 1 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1755,0 86 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2710,0 87 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2715,0 88 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2720,0 89 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2725,0 90 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2282,0 91 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1976,0 92 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 923,0 93 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 928,0 94 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 464,0 95 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1062,0 96 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1389,0 97 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1725,0 98 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2987,0 99 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2992,0 100 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 833,0 101 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 3641,0 102 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 4144,0 103 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2448,0 104 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 2453,0 105 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 163,0 106 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 4067,0 107 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 3631,0 108 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 3646,0 109 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1037,0 110 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1047,0 111 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1057,0 112 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 135,0 113 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1052,0 114 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 3636,0 115 0 +DESIGN @f@a@d_main +VIEW symbol.sb +GRAPHIC 1042,0 116 0 +LIBRARY FACT_FAD_TB_lib +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 508,0 119 0 +DESIGN adc_emulator +VIEW symbol.sb +GRAPHIC 14,0 120 1 +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 48,0 124 0 +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 53,0 125 0 +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 58,0 126 0 +DESIGN adc_emulator +VIEW @behavioral +GRAPHIC 63,0 127 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 274,0 130 0 +DESIGN clock_generator +VIEW symbol.sb +GRAPHIC 14,0 131 1 +DESIGN clock_generator +VIEW @behavioral +GRAPHIC 48,0 136 0 +DESIGN clock_generator +VIEW @behavioral +GRAPHIC 53,0 137 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 362,0 140 0 +DESIGN max6662_emulator +VIEW symbol.sb +GRAPHIC 14,0 141 1 +DESIGN max6662_emulator +VIEW beha +GRAPHIC 48,0 145 0 +DESIGN max6662_emulator +VIEW beha +GRAPHIC 53,0 146 0 +DESIGN max6662_emulator +VIEW beha +GRAPHIC 58,0 147 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 414,0 150 0 +DESIGN trigger_generator +VIEW symbol.sb +GRAPHIC 14,0 151 1 +DESIGN trigger_generator +VIEW beha +GRAPHIC 48,0 156 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 306,0 159 0 +DESIGN w5300_emulator +VIEW beha +GRAPHIC 48,0 161 0 +DESIGN w5300_emulator +VIEW beha +GRAPHIC 53,0 162 0 +DESIGN w5300_emulator +VIEW beha +GRAPHIC 58,0 163 0 +DESIGN w5300_emulator +VIEW beha +GRAPHIC 63,0 164 0 +LIBRARY FACT_FAD_TB_lib +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 167 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 233,0 170 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 508,0 171 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 274,0 172 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 362,0 173 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 414,0 174 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 306,0 175 0 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 178 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 430,0 181 0 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 185 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 518,0 186 0 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 196 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 197 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 233,0 199 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 240,0 200 1 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 286,0 204 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 873,0 205 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 881,0 206 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 889,0 207 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 897,0 208 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 538,0 209 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 530,0 210 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 442,0 211 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 450,0 212 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 426,0 213 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 793,0 214 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 825,0 215 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 833,0 216 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 857,0 217 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 865,0 218 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 546,0 219 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 801,0 220 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 817,0 221 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 841,0 222 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 849,0 223 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 777,0 224 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 809,0 225 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 380,0 226 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 374,0 227 0 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struct.bd +GRAPHIC 369,0 256 1 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 380,0 260 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 386,0 261 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 374,0 262 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 414,0 264 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 421,0 265 1 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 426,0 270 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 306,0 272 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 318,0 274 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 324,0 275 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 330,0 276 0 +DESIGN fad_main_tb +VIEW struct.bd +GRAPHIC 336,0 277 0 +DESIGN fad_main_tb +VIEW struct.bd +NO_GRAPHIC 280 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_adc_emulator._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_adc_emulator._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_adc_emulator._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom Behavioral +DEFAULT_FILE atom adc_emulator_beha.vhd Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_adc_emulator_tb._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_adc_emulator_tb._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_adc_emulator_tb._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom adc_emulator_tb/struct.bd Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_clock_generator._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_clock_generator._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_clock_generator._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom clock_generator_beha.vhd +DEFAULT_ARCHITECTURE atom Behavioral Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_fad_main_tb._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_fad_main_tb._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_fad_main_tb._epf (revision 9841) @@ -0,0 +1,3 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom fad_main_tb/struct.bd +TOP_MARKER atom 1 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_max6662_emulator._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_max6662_emulator._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_max6662_emulator._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom max6662_emulator_beha.vhd +DEFAULT_ARCHITECTURE atom beha Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_trigger_generator._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_trigger_generator._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_trigger_generator._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom trigger__generator_beha.vhd +DEFAULT_ARCHITECTURE atom beha Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_w5300_emulator._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_w5300_emulator._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/_w5300_emulator._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom w5300_emulator_beha.vhd +DEFAULT_ARCHITECTURE atom beha Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/adc_emulator/symbol.sb =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/adc_emulator/symbol.sb (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/adc_emulator/symbol.sb (revision 9841) @@ -0,0 +1,1573 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_unsigned" +) +(DmPackageRef +library "ieee" +unitName "std_logic_textio" +) +(DmPackageRef +library "std" +unitName "textio" +) +] +libraryRefs [ +"ieee" +"std" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model 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"HDSDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator\\symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator" +) +(vvPair +variable "d_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator" +) +(vvPair +variable "date" +value "23.06.2010" +) +(vvPair +variable "day" +value "Mi" +) +(vvPair +variable "day_long" +value "Mittwoch" +) +(vvPair +variable "dd" +value "23" +) +(vvPair +variable "entity_name" +value "adc_emulator" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "EEPC8" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_TB_lib" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR\\FACT_FAD_TB_lib\\work" +) +(vvPair +variable "mm" +value "06" +) +(vvPair +variable "module_name" +value "adc_emulator" +) +(vvPair +variable "month" +value "Jun" +) +(vvPair +variable "month_long" +value "Juni" +) +(vvPair +variable "p" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator\\symbol.sb" +) +(vvPair +variable "p_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$HDS_HOME/../Modeltech/win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "$HDS_HOME/../Precision/Mgc_home/bin" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "11:49:58" +) +(vvPair +variable "unit" +value "adc_emulator" +) +(vvPair +variable "user" +value "Benjamin Krumm" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 85,0 +optionalChildren [ +*61 (SymbolBody +uid 8,0 +optionalChildren [ +*62 (CptPort +uid 48,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 49,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "28250,11625,29000,12375" +) +tg (CPTG +uid 50,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 51,0 +va (VaSet +) +xt "30000,11500,31300,12500" +st "clk" +blo "30000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 52,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,7000,16500,7800" +st "clk : IN STD_LOGIC ;" +) +thePort (LogicalPort +decl (Decl +n "clk" +t "STD_LOGIC" +preAdd 0 +posAdd 0 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time ) +reset_time = 50 ns ( time ) " +) +header "" +) +elements [ +(GiElement +name "clock_period" +type "time" +value "20 ns" +) +(GiElement +name "reset_time" +type "time" +value "50 ns" +) +] +) +viewicon (ZoomableIcon +uid 184,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "14250,22250,15750,23750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*26 (Net +uid 185,0 +decl (Decl +n "clk" +t "std_logic" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +i "'0'" +) +declText (MLText +uid 186,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,3000,38500,3800" +st "SIGNAL clk : std_logic := '0' +" +) +) +*27 (Net +uid 191,0 +decl (Decl +n "data" +t "std_logic_vector" +b "(11 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +) +declText (MLText +uid 192,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,3800,45500,4600" +st "SIGNAL data : std_logic_vector(11 DOWNTO 0) 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(DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "ieee" +unitName "std_logic_unsigned" +) +(DmPackageRef +library "ieee" +unitName "std_logic_textio" +) +(DmPackageRef +library "std" +unitName "textio" +) +] +instances [ +(Instance +name "I_adcTB_adc" +duLibraryName "FACT_FAD_TB_lib" +duName "adc_emulator" +elements [ +(GiElement +name "INPUT_FILE" +type "string" +value "\"../memory_files/analog_input_ch0.txt\"" +) +] +mwi 0 +uid 138,0 +) +(Instance +name "I_adcTB_clock" +duLibraryName "FACT_FAD_TB_lib" +duName "clock_generator" +elements [ +(GiElement +name "clock_period" +type "time" +value "20 ns" +) +(GiElement +name "reset_time" +type "time" +value "50 ns" +) +] +mwi 0 +uid 175,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb_adcTB_oeb" +number "1" +) +] +libraryRefs [ +"ieee" +"std" +] +) +version "29.1" +appVersion "2009.2 (Build 10)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb" +) +(vvPair +variable "d_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb" +) +(vvPair +variable "date" +value "23.06.2010" +) +(vvPair +variable "day" +value "Mi" +) +(vvPair +variable "day_long" +value "Mittwoch" +) +(vvPair +variable "dd" +value "23" +) +(vvPair +variable "entity_name" +value "adc_emulator_tb" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "EEPC8" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_TB_lib" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR\\FACT_FAD_TB_lib\\work" +) +(vvPair +variable "mm" +value "06" +) +(vvPair +variable "module_name" +value "adc_emulator_tb" +) +(vvPair +variable "month" +value "Jun" +) +(vvPair +variable "month_long" +value "Juni" +) +(vvPair +variable "p" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb\\struct.bd" +) +(vvPair +variable "p_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\adc_emulator_tb\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$HDS_HOME/../Modeltech/win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "$HDS_HOME/../Precision/Mgc_home/bin" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "12:01:28" +) +(vvPair +variable "unit" +value "adc_emulator_tb" +) +(vvPair +variable "user" +value "Benjamin Krumm" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 52,0 +optionalChildren [ +*1 (Grouping +uid 9,0 +optionalChildren [ +*2 (CommentText +uid 11,0 +shape (Rectangle +uid 12,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 13,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48000,49200,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 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+iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*86 (Net +uid 440,0 +decl (Decl +n "board_id" +t "std_logic_vector" +b "(3 downto 0)" +preAdd 0 +posAdd 0 +o 10 +suid 10,0 +) +declText (MLText +uid 441,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,26000,30000,26800" +st "SIGNAL board_id : std_logic_vector(3 downto 0)" +) +) +*87 (Net +uid 448,0 +decl (Decl +n "crate_id" +t "std_logic_vector" +b "(1 downto 0)" +o 11 +suid 11,0 +) +declText (MLText +uid 449,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,27600,30000,28400" +st "SIGNAL crate_id : std_logic_vector(1 downto 0)" +) +) +*88 (SaComponent +uid 508,0 +optionalChildren [ +*89 (CptPort +uid 489,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 490,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "29250,52625,30000,53375" +) +tg (CPTG +uid 491,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 492,0 +va (VaSet +) +xt "31000,52500,32300,53500" +st "clk" +blo "31000,53300" +) +) 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"STD_LOGIC" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +) +) +) +*92 (CptPort +uid 501,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 502,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40000,53625,40750,54375" +) +tg (CPTG +uid 503,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 504,0 +va (VaSet +) +xt "37400,53500,39000,54500" +st "oeb" +ju 2 +blo "39000,54300" +) +) +thePort (LogicalPort +decl (Decl +n "oeb" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 4 +suid 4,0 +) +) +) +] +shape (Rectangle +uid 509,0 +va (VaSet +vasetType 1 +fg "0,49152,49152" +lineColor "0,0,50000" +lineWidth 2 +) +xt "30000,51000,40000,58000" +) +oxt "29000,7000,39000,17000" +ttg (MlTextGroup +uid 510,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*93 (Text +uid 511,0 +va (VaSet +font "Arial,8,1" +) +xt "30200,58000,37900,59000" +st "FACT_FAD_TB_lib" +blo "30200,58800" +tm "BdLibraryNameMgr" +) +*94 (Text +uid 512,0 +va (VaSet +font "Arial,8,1" +) +xt "30200,59000,36000,60000" +st "adc_emulator" +blo "30200,59800" +tm "CptNameMgr" +) +*95 (Text +uid 513,0 +va (VaSet +font "Arial,8,1" +) +xt "30200,60000,36200,61000" +st "I_mainTB_adc" +blo "30200,60800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 514,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 515,0 +text (MLText +uid 516,0 +va (VaSet +font "Courier New,8,0" +) +xt "30000,50200,65500,51000" +st "INPUT_FILE = \"../memory_files/analog_input_ch0.txt\" ( string ) " +) +header "" +) +elements [ +(GiElement +name "INPUT_FILE" +type "string" +value "\"../memory_files/analog_input_ch0.txt\"" +) +] +) +viewicon (ZoomableIcon +uid 517,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "30250,56250,31750,57750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sIVOD 1 +) +archFileType "UNKNOWN" +) +*96 (HdlText +uid 518,0 +optionalChildren [ +*97 (EmbeddedText +uid 524,0 +commentText (CommentText +uid 525,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 526,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "50000,57000,62000,67000" +) +oxt "0,0,18000,5000" +text (MLText +uid 527,0 +va (VaSet +) +xt "50200,57200,62100,66200" +st " +-- eb_adc 2: ADC routing +adc_data_array(0) <= adc_data; +adc_data_array(1) <= adc_data; +adc_data_array(2) <= adc_data; +adc_data_array(3) <= adc_data; +adc_otr_array(0) <= adc_otr; +adc_otr_array(1) <= adc_otr; +adc_otr_array(2) <= adc_otr; +adc_otr_array(3) <= adc_otr; + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 10000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 519,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "50000,51000,58000,57000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 520,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*98 (Text +uid 521,0 +va (VaSet +font "Arial,8,1" +) +xt "51150,52000,57850,53000" +st "eb_mainTB_adc" +blo "51150,52800" +tm "HdlTextNameMgr" +) +*99 (Text +uid 522,0 +va (VaSet +font "Arial,8,1" +) +xt "51150,53000,51950,54000" +st "2" +blo "51150,53800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 523,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "50250,55250,51750,56750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*100 (Net +uid 528,0 +decl (Decl +n "adc_otr_array" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 12 +suid 12,0 +) +declText (MLText +uid 529,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,25200,30000,26000" +st "SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0)" +) +) +*101 (Net +uid 536,0 +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 13 +suid 13,0 +) +declText (MLText +uid 537,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22800,25500,23600" +st "SIGNAL adc_data_array : adc_data_array_type" +) +) +*102 (Net +uid 544,0 +decl (Decl +n "adc_oeb" +t "std_logic" +preAdd 0 +posAdd 0 +o 14 +suid 14,0 +) +declText (MLText +uid 545,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,23600,20000,24400" +st "SIGNAL adc_oeb : std_logic" +) +) +*103 (Net +uid 560,0 +decl (Decl +n "adc_otr" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 16 +suid 16,0 +) +declText (MLText +uid 561,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,24400,20000,25200" +st "SIGNAL adc_otr : STD_LOGIC" +) +) +*104 (Net +uid 568,0 +decl (Decl +n "adc_data" +t "std_logic_vector" +b "(11 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 17 +suid 17,0 +) +declText (MLText +uid 569,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22000,30500,22800" +st "SIGNAL adc_data : std_logic_vector(11 DOWNTO 0)" +) +) +*105 (Net +uid 767,0 +decl (Decl +n "wiz_reset" +t "std_logic" +o 21 +suid 23,0 +i "'1'" +) +declText (MLText +uid 768,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,40400,33500,41200" +st "SIGNAL wiz_reset : std_logic := '1'" +) +) +*106 (Net +uid 775,0 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 DOWNTO 0)" +posAdd 0 +o 22 +suid 24,0 +i "(OTHERS => '0')" +) +declText (MLText +uid 776,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,31600,39500,32400" +st "SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" +) +) +*107 (Net +uid 783,0 +decl (Decl +n "wiz_cs" +t "std_logic" +o 23 +suid 25,0 +i "'1'" +) +declText (MLText +uid 784,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,37200,33500,38000" +st "SIGNAL wiz_cs : std_logic := '1'" +) +) +*108 (Net +uid 791,0 +decl (Decl +n "wiz_int" +t "std_logic" +o 24 +suid 26,0 +) +declText (MLText +uid 792,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,38800,20000,39600" +st "SIGNAL wiz_int : std_logic" +) +) +*109 (Net +uid 799,0 +decl (Decl +n "dac_cs" +t "std_logic" +o 25 +suid 27,0 +) +declText (MLText +uid 800,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,28400,20000,29200" +st "SIGNAL dac_cs : std_logic" +) +) +*110 (Net +uid 807,0 +decl (Decl +n "mosi" +t "std_logic" +o 26 +suid 28,0 +i "'0'" +) +declText (MLText +uid 808,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,32400,33500,33200" +st "SIGNAL mosi : std_logic := '0'" +) +) +*111 (Net +uid 815,0 +decl (Decl +n "denable" +t "std_logic" +eolc "-- default domino wave off" +posAdd 0 +o 27 +suid 29,0 +i "'0'" +) +declText (MLText +uid 816,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,29200,47000,30000" +st "SIGNAL denable : std_logic := '0' -- default domino wave off" +) +) +*112 (Net +uid 823,0 +decl (Decl +n "CLK_25_PS" +t "std_logic" +o 28 +suid 30,0 +) +declText (MLText +uid 824,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,15600,20000,16400" +st "SIGNAL CLK_25_PS : std_logic" +) +) +*113 (Net +uid 831,0 +decl (Decl +n "CLK_50" +t "std_logic" +o 29 +suid 31,0 +) +declText (MLText +uid 832,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,16400,20000,17200" +st "SIGNAL CLK_50 : std_logic" +) +) +*114 (Net +uid 839,0 +decl (Decl +n "drs_channel_id" +t "std_logic_vector" +b "(3 downto 0)" +o 30 +suid 32,0 +i "(others => '0')" +) +declText (MLText +uid 840,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,30000,39500,30800" +st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" +) +) +*115 (Net +uid 847,0 +decl (Decl +n "drs_dwrite" +t "std_logic" +o 31 +suid 33,0 +i "'1'" +) +declText (MLText +uid 848,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,30800,33500,31600" +st "SIGNAL drs_dwrite : std_logic := '1'" +) +) +*116 (Net +uid 855,0 +decl (Decl +n "RSRLOAD" +t "std_logic" +o 32 +suid 34,0 +i "'0'" +) +declText (MLText +uid 856,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,17200,33500,18000" +st "SIGNAL RSRLOAD : std_logic := '0'" +) +) +*117 (Net +uid 863,0 +decl (Decl +n "SRCLK" +t "std_logic" +o 33 +suid 35,0 +i "'0'" +) +declText (MLText +uid 864,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,18000,33500,18800" +st "SIGNAL SRCLK : std_logic := '0'" +) +) +*118 (Net +uid 871,0 +decl (Decl +n "SROUT_in_0" +t "std_logic" +o 30 +suid 36,0 +) +declText (MLText +uid 872,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,18800,20000,19600" +st "SIGNAL SROUT_in_0 : std_logic" +) +) +*119 (Net +uid 879,0 +decl (Decl +n "SROUT_in_1" +t "std_logic" +o 31 +suid 37,0 +) +declText (MLText +uid 880,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,19600,20000,20400" +st "SIGNAL SROUT_in_1 : std_logic" +) +) +*120 (Net +uid 887,0 +decl (Decl +n "SROUT_in_2" +t "std_logic" +o 32 +suid 38,0 +) +declText (MLText +uid 888,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,20400,20000,21200" +st "SIGNAL SROUT_in_2 : std_logic" +) +) +*121 (Net +uid 895,0 +decl (Decl +n "SROUT_in_3" +t "std_logic" +o 33 +suid 39,0 +) +declText (MLText +uid 896,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,21200,20000,22000" +st "SIGNAL SROUT_in_3 : std_logic" +) +) +*122 (Wire +uid 286,0 +shape (OrthoPolyLine +uid 287,0 +va (VaSet +vasetType 3 +) +xt "58750,21000,80250,21000" +pts [ +"58750,21000" +"80250,21000" +] +) +start &48 +end &27 +sat 32 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+uid 82,0 +type 1 +) +activeModelName "BlockDiag" +) Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak (revision 9841) @@ -0,0 +1,7015 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "ieee" +unitName "std_logic_unsigned" +) +(DmPackageRef +library "FACT_FAD_lib" +unitName "fad_definitions" +) +(DmPackageRef +library "ieee" +unitName "std_logic_textio" +) +(DmPackageRef +library "std" +unitName "textio" +) +] +instances [ +(Instance +name "I_mainTB_FPGA" +duLibraryName "FACT_FAD_lib" +duName "FAD_main" +elements [ +(GiElement +name "RAMADDRWIDTH64b" +type "integer" +value "15" +) +] +mwi 0 +uid 233,0 +) +(Instance +name "I_mainTB_clock" +duLibraryName "FACT_FAD_TB_lib" +duName "clock_generator" +elements [ +(GiElement +name "clock_period" +type "time" +value "20 ns" +) +(GiElement +name "reset_time" +type "time" +value "50 ns" +) +] +mwi 0 +uid 274,0 +) +(Instance +name "I_mainTB_w5300" +duLibraryName "FACT_FAD_TB_lib" +duName "w5300_emulator" +elements [ +] +mwi 0 +uid 306,0 +) +(Instance +name "I_mainTB_max6662" +duLibraryName "FACT_FAD_TB_lib" +duName "max6662_emulator" +elements [ +(GiElement +name "DRS_TEMPERATURE" +type "integer" +value "51" +) +] +mwi 0 +uid 362,0 +) +(Instance +name "I_mainTB_trigger" +duLibraryName "FACT_FAD_TB_lib" +duName "trigger_generator" +elements [ +(GiElement +name "TRIGGER_RATE" +type "time" +value "1 ms" +) +(GiElement +name "PULSE_WIDTH" +type "time" +value "20 ns" +) +] +mwi 0 +uid 414,0 +) +(Instance +name "I_mainTB_adc" +duLibraryName "FACT_FAD_TB_lib" +duName "adc_emulator" +elements [ +(GiElement +name "INPUT_FILE" +type "string" +value "\"../memory_files/analog_input_ch0.txt\"" +) +] +mwi 0 +uid 508,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb_mainTB_ID" +number "1" +) +(EmbeddedInstance +name "eb_mainTB_adc" +number "2" +) +] +libraryRefs [ +"ieee" +"FACT_FAD_lib" +"std" +] +) +version "29.1" +appVersion "2009.2 (Build 10)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb" +) +(vvPair +variable "d_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb" +) +(vvPair +variable "date" +value "25.06.2010" +) +(vvPair +variable "day" +value "Fr" +) +(vvPair +variable "day_long" +value "Freitag" +) +(vvPair +variable "dd" +value "25" +) +(vvPair +variable "entity_name" +value "fad_main_tb" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "EEPC8" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_TB_lib" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work" +) +(vvPair +variable "mm" +value "06" +) +(vvPair +variable "module_name" +value "fad_main_tb" +) +(vvPair +variable "month" +value "Jun" +) +(vvPair +variable "month_long" +value "Juni" +) +(vvPair +variable "p" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd" +) +(vvPair +variable "p_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$HDS_HOME/../Modeltech/win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "$HDS_HOME/../Precision/Mgc_home/bin" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "08:17:47" +) +(vvPair +variable "unit" +value "fad_main_tb" +) +(vvPair +variable "user" +value "Benjamin Krumm" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 52,0 +optionalChildren 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+) +xt "124000,20500,128500,21500" +st "addr : (9:0)" +blo "124000,21300" +) +) +thePort (LogicalPort +decl (Decl +n "addr" +t "std_logic_vector" +b "(9 downto 0)" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*56 (CptPort +uid 294,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 295,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "122250,21625,123000,22375" +) +tg (CPTG +uid 296,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 297,0 +va (VaSet +) +xt "124000,21500,128800,22500" +st "data : (15:0)" +blo "124000,22300" +) +) +thePort (LogicalPort +m 2 +decl (Decl +n "data" +t "std_logic_vector" +b "(15 downto 0)" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +) +) +) +*57 (CptPort +uid 298,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 299,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "122250,24625,123000,25375" +) +tg (CPTG +uid 300,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 301,0 +va (VaSet +) +xt "124000,24500,125100,25500" +st "rd" +blo "124000,25300" +) +) +thePort (LogicalPort +decl (Decl +n "rd" +t "std_logic" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +) +) +) +*58 (CptPort +uid 302,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 303,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "122250,25625,123000,26375" +) +tg (CPTG +uid 304,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 305,0 +va (VaSet +) +xt "124000,25500,125200,26500" +st "wr" +blo "124000,26300" +) +) +thePort (LogicalPort +decl (Decl +n "wr" +t "std_logic" +preAdd 0 +posAdd 0 +o 4 +suid 4,0 +) +) +) +] +shape (Rectangle +uid 307,0 +va (VaSet +vasetType 1 +fg "0,49152,49152" +lineColor "0,0,50000" +lineWidth 2 +) +xt "123000,19000,133000,31000" +) +oxt "29000,2000,39000,12000" +ttg (MlTextGroup +uid 308,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*59 (Text +uid 309,0 +va (VaSet +font "Arial,8,1" +) +xt "123200,31000,130900,32000" +st "FACT_FAD_TB_lib" +blo "123200,31800" +tm "BdLibraryNameMgr" +) +*60 (Text +uid 310,0 +va (VaSet +font "Arial,8,1" +) +xt "123200,32000,129800,33000" +st "w5300_emulator" +blo "123200,32800" +tm "CptNameMgr" +) +*61 (Text +uid 311,0 +va (VaSet +font "Arial,8,1" +) +xt "123200,33000,130000,34000" +st "I_mainTB_w5300" +blo "123200,33800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 312,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 313,0 +text (MLText +uid 314,0 +va (VaSet +font "Courier New,8,0" +) +xt "123000,18000,123000,18000" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 315,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "123250,29250,124750,30750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sIVOD 1 +) +archFileType "UNKNOWN" +) +*62 (Net +uid 316,0 +decl (Decl +n "wiz_addr" +t "std_logic_vector" +b "(9 DOWNTO 0)" +o 2 +suid 2,0 +) +declText (MLText +uid 317,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,36400,30000,37200" +st "SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0)" +) +) +*63 (Net +uid 322,0 +decl (Decl +n "wiz_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 3 +suid 3,0 +) +declText (MLText +uid 323,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,38000,30500,38800" +st "SIGNAL wiz_data : std_logic_vector(15 DOWNTO 0)" +) +) +*64 (Net +uid 328,0 +decl (Decl +n "wiz_rd" +t "std_logic" +o 4 +suid 4,0 +i "'1'" +) +declText (MLText +uid 329,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,39600,33500,40400" +st "SIGNAL wiz_rd : std_logic := '1'" +) +) +*65 (Net +uid 334,0 +decl (Decl +n "wiz_wr" +t "std_logic" +o 5 +suid 5,0 +i "'1'" +) +declText (MLText +uid 335,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,41200,33500,42000" +st "SIGNAL wiz_wr : std_logic := '1'" +) +) +*66 (SaComponent +uid 362,0 +optionalChildren [ +*67 (CptPort +uid 350,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 351,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "122250,50625,123000,51375" +) +tg (CPTG +uid 352,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 353,0 +va (VaSet +) +xt "124000,50500,125700,51500" +st "sclk" +blo "124000,51300" +) +) +thePort (LogicalPort +decl (Decl +n "sclk" +t "std_logic" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*68 (CptPort +uid 354,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 355,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "122250,51625,123000,52375" +) +tg (CPTG +uid 356,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 357,0 +va (VaSet +) +xt "124000,51500,125400,52500" +st "sio" +blo "124000,52300" +) +) +thePort (LogicalPort +m 2 +decl (Decl +n "sio" +t "std_logic" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +) +) +) +*69 (CptPort +uid 358,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 359,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "122250,47625,123000,48375" +) +tg (CPTG +uid 360,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 361,0 +va (VaSet +) +xt "124000,47500,130500,48500" +st "sensor_cs : (3:0)" +blo "124000,48300" +) +) +thePort (LogicalPort +decl (Decl +n "sensor_cs" +t "std_logic_vector" +b "(3 downto 0)" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +) +) +) +] +shape (Rectangle +uid 363,0 +va (VaSet +vasetType 1 +fg "0,49152,49152" +lineColor "0,0,50000" +lineWidth 2 +) +xt "123000,46000,133000,56000" +) +oxt "30000,3000,40000,13000" +ttg (MlTextGroup +uid 364,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*70 (Text +uid 365,0 +va (VaSet +font "Arial,8,1" +) +xt "123200,56000,130900,57000" +st "FACT_FAD_TB_lib" +blo "123200,56800" +tm "BdLibraryNameMgr" +) +*71 (Text +uid 366,0 +va (VaSet +font "Arial,8,1" +) +xt "123200,57000,130800,58000" +st "max6662_emulator" +blo "123200,57800" +tm "CptNameMgr" +) +*72 (Text +uid 367,0 +va (VaSet +font "Arial,8,1" +) +xt "123200,58000,131000,59000" +st "I_mainTB_max6662" +blo "123200,58800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 368,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 369,0 +text (MLText +uid 370,0 +va (VaSet +font "Courier New,8,0" +) +xt "123000,45200,143000,46000" +st "DRS_TEMPERATURE = 51 ( integer ) " +) +header "" +) +elements [ +(GiElement +name "DRS_TEMPERATURE" +type "integer" +value "51" +) +] +) +viewicon (ZoomableIcon +uid 371,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "123250,54250,124750,55750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sIVOD 1 +) +archFileType "UNKNOWN" +) +*73 (Net +uid 372,0 +decl (Decl +n "sensor_cs" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 6 +suid 6,0 +) +declText (MLText +uid 373,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,34000,30000,34800" +st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" +) +) +*74 (Net +uid 378,0 +decl (Decl +n "sclk" +t "std_logic" +o 7 +suid 7,0 +) +declText (MLText +uid 379,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,33200,20000,34000" +st "SIGNAL sclk : std_logic" +) +) +*75 (Net +uid 384,0 +decl (Decl +n "sio" +t "std_logic" +preAdd 0 +posAdd 0 +o 8 +suid 8,0 +) +declText (MLText +uid 385,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,34800,20000,35600" +st "SIGNAL sio : std_logic" +) +) +*76 (SaComponent +uid 414,0 +optionalChildren [ +*77 (CptPort +uid 410,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 411,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,31625,58750,32375" +) +tg (CPTG +uid 412,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 413,0 +va (VaSet +) +xt "54200,31500,57000,32500" +st "trigger" +ju 2 +blo "57000,32300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "trigger" +t "std_logic" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +] +shape (Rectangle +uid 415,0 +va (VaSet +vasetType 1 +fg "0,49152,49152" +lineColor "0,0,50000" +lineWidth 2 +) +xt "50000,30000,58000,36000" +) +oxt "19000,4000,29000,14000" +ttg (MlTextGroup +uid 416,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*78 (Text +uid 417,0 +va (VaSet +font "Arial,8,1" +) +xt "50200,36000,57900,37000" +st "FACT_FAD_TB_lib" +blo "50200,36800" +tm "BdLibraryNameMgr" +) +*79 (Text +uid 418,0 +va (VaSet +font "Arial,8,1" +) +xt "50200,37000,57500,38000" +st "trigger_generator" +blo "50200,37800" +tm "CptNameMgr" +) +*80 (Text +uid 419,0 +va (VaSet +font "Arial,8,1" +) +xt "50200,38000,57400,39000" +st "I_mainTB_trigger" +blo "50200,38800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 420,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 421,0 +text (MLText +uid 422,0 +va (VaSet +font "Courier New,8,0" +) +xt "50000,28400,68500,30000" +st "TRIGGER_RATE = 1 ms ( time ) +PULSE_WIDTH = 20 ns ( time ) " +) +header "" +) +elements [ +(GiElement +name "TRIGGER_RATE" +type "time" +value "1 ms" +) +(GiElement +name "PULSE_WIDTH" +type "time" +value "20 ns" +) +] +) +viewicon (ZoomableIcon +uid 423,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "50250,34250,51750,35750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sIVOD 1 +) +archFileType "UNKNOWN" +) +*81 (Net +uid 424,0 +decl (Decl +n "trigger" +t "std_logic" +preAdd 0 +posAdd 0 +o 9 +suid 9,0 +) +declText (MLText +uid 425,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,35600,20000,36400" +st "SIGNAL trigger : std_logic" +) +) +*82 (HdlText +uid 430,0 +optionalChildren [ +*83 (EmbeddedText +uid 436,0 +commentText (CommentText +uid 437,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 438,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "50000,45000,60000,49000" +) +oxt "0,0,18000,5000" +text (MLText +uid 439,0 +va (VaSet +) +xt "50200,45200,60200,48200" +st " +-- eb_ID 1: hard-wired IDs +board_id <= \"0101\"; +crate_id <= \"01\"; + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 4000 +visibleWidth 10000 +) +) +) +] +shape (Rectangle +uid 431,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "50000,40000,58000,45000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 432,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*84 (Text +uid 433,0 +va (VaSet +font "Arial,8,1" +) +xt "51150,41000,57350,42000" +st "eb_mainTB_ID" +blo "51150,41800" +tm "HdlTextNameMgr" +) +*85 (Text +uid 434,0 +va (VaSet +font "Arial,8,1" +) +xt "51150,42000,51950,43000" +st "1" +blo "51150,42800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 435,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "50250,43250,51750,44750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*86 (Net +uid 440,0 +decl (Decl +n "board_id" +t "std_logic_vector" +b "(3 downto 0)" +preAdd 0 +posAdd 0 +o 10 +suid 10,0 +) +declText (MLText +uid 441,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,26000,30000,26800" +st "SIGNAL board_id : std_logic_vector(3 downto 0)" +) +) +*87 (Net +uid 448,0 +decl (Decl +n "crate_id" +t "std_logic_vector" +b "(1 downto 0)" +o 11 +suid 11,0 +) +declText (MLText +uid 449,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,27600,30000,28400" +st "SIGNAL crate_id : std_logic_vector(1 downto 0)" +) +) +*88 (SaComponent +uid 508,0 +optionalChildren [ +*89 (CptPort +uid 489,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 490,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "29250,52625,30000,53375" +) +tg (CPTG +uid 491,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 492,0 +va (VaSet +) +xt "31000,52500,32300,53500" +st "clk" +blo "31000,53300" +) +) +thePort (LogicalPort +decl (Decl +n "clk" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*90 (CptPort +uid 493,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 494,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40000,54625,40750,55375" +) +tg (CPTG +uid 495,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 496,0 +va (VaSet +) +xt "34200,54500,39000,55500" +st "data : (11:0)" +ju 2 +blo "39000,55300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "data" +t "STD_LOGIC_VECTOR" +b "(11 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +) +) +) +*91 (CptPort +uid 497,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 498,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40000,52625,40750,53375" +) +tg (CPTG +uid 499,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 500,0 +va (VaSet +) +xt "37700,52500,39000,53500" +st "otr" +ju 2 +blo "39000,53300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "otr" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +) +) +) +*92 (CptPort +uid 501,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 502,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40000,53625,40750,54375" +) +tg (CPTG +uid 503,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 504,0 +va (VaSet +) +xt "37400,53500,39000,54500" +st "oeb" +ju 2 +blo "39000,54300" +) +) +thePort (LogicalPort +decl (Decl +n "oeb" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 4 +suid 4,0 +) +) +) +] +shape (Rectangle +uid 509,0 +va (VaSet +vasetType 1 +fg "0,49152,49152" +lineColor "0,0,50000" +lineWidth 2 +) +xt "30000,51000,40000,58000" +) +oxt "29000,7000,39000,17000" +ttg (MlTextGroup +uid 510,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*93 (Text +uid 511,0 +va (VaSet +font "Arial,8,1" +) +xt "30200,58000,37900,59000" +st "FACT_FAD_TB_lib" +blo "30200,58800" +tm "BdLibraryNameMgr" +) +*94 (Text +uid 512,0 +va (VaSet +font "Arial,8,1" +) +xt "30200,59000,36000,60000" +st "adc_emulator" +blo "30200,59800" +tm "CptNameMgr" +) +*95 (Text +uid 513,0 +va (VaSet +font "Arial,8,1" +) +xt "30200,60000,36200,61000" +st "I_mainTB_adc" +blo "30200,60800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 514,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 515,0 +text (MLText +uid 516,0 +va (VaSet +font "Courier New,8,0" +) +xt "30000,50200,65500,51000" +st "INPUT_FILE = \"../memory_files/analog_input_ch0.txt\" ( string ) " +) +header "" +) +elements [ +(GiElement +name "INPUT_FILE" +type "string" +value "\"../memory_files/analog_input_ch0.txt\"" +) +] +) +viewicon (ZoomableIcon +uid 517,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "30250,56250,31750,57750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sIVOD 1 +) +archFileType "UNKNOWN" +) +*96 (HdlText +uid 518,0 +optionalChildren [ +*97 (EmbeddedText +uid 524,0 +commentText (CommentText +uid 525,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 526,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "50000,57000,62000,67000" +) +oxt "0,0,18000,5000" +text (MLText +uid 527,0 +va (VaSet +) +xt "50200,57200,62100,66200" +st " +-- eb_adc 2: ADC routing +adc_data_array(0) <= adc_data; +adc_data_array(1) <= adc_data; +adc_data_array(2) <= adc_data; +adc_data_array(3) <= adc_data; +adc_otr_array(0) <= adc_otr; +adc_otr_array(1) <= adc_otr; +adc_otr_array(2) <= adc_otr; +adc_otr_array(3) <= adc_otr; + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 10000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 519,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "50000,51000,58000,57000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 520,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*98 (Text +uid 521,0 +va (VaSet +font "Arial,8,1" +) +xt "51150,52000,57850,53000" +st "eb_mainTB_adc" +blo "51150,52800" +tm "HdlTextNameMgr" +) +*99 (Text +uid 522,0 +va (VaSet +font "Arial,8,1" +) +xt "51150,53000,51950,54000" +st "2" +blo "51150,53800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 523,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "50250,55250,51750,56750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*100 (Net +uid 528,0 +decl (Decl +n "adc_otr_array" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 12 +suid 12,0 +) +declText (MLText +uid 529,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,25200,30000,26000" +st "SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0)" +) +) +*101 (Net +uid 536,0 +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 13 +suid 13,0 +) +declText (MLText +uid 537,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22800,25500,23600" +st "SIGNAL adc_data_array : adc_data_array_type" +) +) +*102 (Net +uid 544,0 +decl (Decl +n "adc_oeb" +t "std_logic" +preAdd 0 +posAdd 0 +o 14 +suid 14,0 +) +declText (MLText +uid 545,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,23600,20000,24400" +st "SIGNAL adc_oeb : std_logic" +) +) +*103 (Net +uid 560,0 +decl (Decl +n "adc_otr" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 16 +suid 16,0 +) +declText (MLText +uid 561,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,24400,20000,25200" +st "SIGNAL adc_otr : STD_LOGIC" +) +) +*104 (Net +uid 568,0 +decl (Decl +n "adc_data" +t "std_logic_vector" +b "(11 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 17 +suid 17,0 +) +declText (MLText +uid 569,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22000,30500,22800" +st "SIGNAL adc_data : std_logic_vector(11 DOWNTO 0)" +) +) +*105 (Net +uid 767,0 +decl (Decl +n "wiz_reset" +t "std_logic" +o 21 +suid 23,0 +i "'1'" +) +declText (MLText +uid 768,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,40400,33500,41200" +st "SIGNAL wiz_reset : std_logic := '1'" +) +) +*106 (Net +uid 775,0 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 DOWNTO 0)" +posAdd 0 +o 22 +suid 24,0 +i "(OTHERS => '0')" +) +declText (MLText +uid 776,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,31600,39500,32400" +st "SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" +) +) +*107 (Net +uid 783,0 +decl (Decl +n "wiz_cs" +t "std_logic" +o 23 +suid 25,0 +i "'1'" +) +declText (MLText +uid 784,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,37200,33500,38000" +st "SIGNAL wiz_cs : std_logic := '1'" +) +) +*108 (Net +uid 791,0 +decl (Decl +n "wiz_int" +t "std_logic" +o 24 +suid 26,0 +) +declText (MLText +uid 792,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,38800,20000,39600" +st "SIGNAL wiz_int : std_logic" +) +) +*109 (Net +uid 799,0 +decl (Decl +n "dac_cs" +t "std_logic" +o 25 +suid 27,0 +) +declText (MLText +uid 800,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,28400,20000,29200" +st "SIGNAL dac_cs : std_logic" +) +) +*110 (Net +uid 807,0 +decl (Decl +n "mosi" +t "std_logic" +o 26 +suid 28,0 +i "'0'" +) +declText (MLText +uid 808,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,32400,33500,33200" +st "SIGNAL mosi : std_logic := '0'" +) +) +*111 (Net +uid 815,0 +decl (Decl +n "denable" +t "std_logic" +eolc "-- default domino wave off" +posAdd 0 +o 27 +suid 29,0 +i "'0'" +) +declText (MLText +uid 816,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,29200,47000,30000" +st "SIGNAL denable : std_logic := '0' -- default domino wave off" +) +) +*112 (Net +uid 823,0 +decl (Decl +n "CLK_25_PS" +t "std_logic" +o 28 +suid 30,0 +) +declText (MLText +uid 824,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,15600,20000,16400" +st "SIGNAL CLK_25_PS : std_logic" +) +) +*113 (Net +uid 831,0 +decl (Decl +n "CLK_50" +t "std_logic" +o 29 +suid 31,0 +) +declText (MLText +uid 832,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,16400,20000,17200" +st "SIGNAL CLK_50 : std_logic" +) +) +*114 (Net +uid 839,0 +decl (Decl +n "drs_channel_id" +t "std_logic_vector" +b "(3 downto 0)" +o 30 +suid 32,0 +i "(others => '0')" +) +declText (MLText +uid 840,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,30000,39500,30800" +st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" +) +) +*115 (Net +uid 847,0 +decl (Decl +n "drs_dwrite" +t "std_logic" +o 31 +suid 33,0 +i "'1'" +) +declText (MLText +uid 848,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,30800,33500,31600" +st "SIGNAL drs_dwrite : std_logic := '1'" +) +) +*116 (Net +uid 855,0 +decl (Decl +n "RSRLOAD" +t "std_logic" +o 32 +suid 34,0 +i "'0'" +) +declText (MLText +uid 856,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,17200,33500,18000" +st "SIGNAL RSRLOAD : std_logic := '0'" +) +) +*117 (Net +uid 863,0 +decl (Decl +n "SRCLK" +t "std_logic" +o 33 +suid 35,0 +i "'0'" +) +declText (MLText +uid 864,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,18000,33500,18800" +st "SIGNAL SRCLK : std_logic := '0'" +) +) +*118 (Net +uid 871,0 +decl (Decl +n "SROUT_in_0" +t "std_logic" +o 30 +suid 36,0 +) +declText (MLText +uid 872,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,18800,20000,19600" +st "SIGNAL SROUT_in_0 : std_logic" +) +) +*119 (Net +uid 879,0 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/firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/fad_main_tb/symbol.sb =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/fad_main_tb/symbol.sb (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/fad_main_tb/symbol.sb (revision 9841) @@ -0,0 +1,1174 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +] +libraryRefs [ +"ieee" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +usingSuid 1 +emptyRow *1 (LEmptyRow +) +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm 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=================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/max6662_emulator/symbol.sb (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/max6662_emulator/symbol.sb (revision 9841) @@ -0,0 +1,1443 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "ieee" +unitName "std_logic_unsigned" +) +(DmPackageRef +library "FACT_FAD_lib" +unitName "fad_definitions" +) +] +libraryRefs [ +"ieee" +"FACT_FAD_lib" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 3,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 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/firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/w5300_emulator/symbol.sb =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/w5300_emulator/symbol.sb (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/hds/w5300_emulator/symbol.sb (revision 9841) @@ -0,0 +1,1515 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "ieee" +unitName "std_logic_unsigned" +) +(DmPackageRef +library "FACT_FAD_lib" +unitName "fad_definitions" +) +] +libraryRefs [ +"ieee" +"FACT_FAD_lib" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 4,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 84,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 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+value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\w5300_emulator\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\w5300_emulator" +) +(vvPair +variable "d_logical" +value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\w5300_emulator" +) +(vvPair +variable "date" +value "23.06.2010" +) +(vvPair +variable "day" +value "Mi" +) +(vvPair +variable "day_long" +value "Mittwoch" +) +(vvPair +variable "dd" +value "23" +) +(vvPair +variable "entity_name" +value "w5300_emulator" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair 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+xt "50200,16000,53200,17000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*68 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "33000,18000,50000,19000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "33200,18000,43200,19000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*69 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "29000,18000,33000,19000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "29200,18000,31300,19000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*70 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "50000,17000,70000,21000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "50200,17200,59400,18200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*71 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "54000,16000,70000,17000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "54200,16000,58700,17000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*72 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "29000,16000,50000,18000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "36700,16000,42300,18000" +st " +TU Dortmund +Physik / EE +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*73 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "29000,19000,33000,20000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "29200,19000,31300,20000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*74 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "29000,20000,33000,21000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "29200,20000,31900,21000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*75 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "33000,19000,50000,20000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "33200,19000,49200,20000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "29000,16000,70000,21000" +) +oxt "14000,66000,55000,71000" +) +*76 (CommentText +uid 68,0 +shape (Rectangle +uid 69,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,-6000,33000,0" +) +text (MLText +uid 70,0 +va (VaSet +fg "0,0,32768" +font "Arial,10,0" +) +xt "200,-5800,32300,-600" +st " +Created using Mentor Graphics HDL2Graphics(TM) Technology +on - 10:43:29 23.06.2010 +from - D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hdl\\w5300_emulator_beha.vhd + +" +tm "CommentText" +wrapOption 3 +visibleHeight 5600 +visibleWidth 32600 +) +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *77 (PackageList +uid 79,0 +stg "VerticalLayoutStrategy" +textVec [ +*78 (Text +uid 80,0 +va (VaSet +font "Arial,8,1" +) +xt "0,1000,5400,2000" +st "Package List" +blo "0,1800" +) +*79 (MLText +uid 81,0 +va (VaSet +) +xt "0,2000,14500,8000" +st "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all;" +tm "PackageList" +) +] +) +windowSize "0,0,1015,690" +viewArea "0,0,0,0" +cachedDiagramExtent "0,0,0,0" +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *80 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *81 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "0,9000,5400,10000" +st "Declarations" +blo "0,9800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "0,10000,2700,11000" +st "Ports:" +blo "0,10800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "0,14200,2400,15200" +st "User:" +blo "0,15000" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "0,9000,5800,10000" +st "Internal User:" +blo "0,9800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,15200,2000,15200" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,9000,0,9000" +tm "SyDeclarativeTextMgr" +) +) +lastUid 138,0 +activeModelName "Symbol:CDM" +) Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/memory_files/analog_input_ch0.txt =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/memory_files/analog_input_ch0.txt (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/memory_files/analog_input_ch0.txt (revision 9841) @@ -0,0 +1,1024 @@ +11ac -- 0 +0816 -- 1 +0629 -- 2 +0113 -- 3 +169c -- 4 +0b71 -- 5 +035e -- 6 +15d6 -- 7 +1929 -- 8 +14f6 -- 9 +122d -- 10 +09c5 +0fd6 +076b +0451 +1809 +1059 +1730 +0c14 +1be4 +0ffc -- 20 +131f +18e6 +10aa +1447 +1a73 +095d +1a12 +1a02 +0259 +0025 -- 30 +0221 +1fbc +0515 +17ba +1541 +0fe5 +1895 +0132 +1eac +058a -- 40 +1d7f +0cd3 +054f +16f0 +05d3 +0d35 +1f00 +030d +137c +1727 -- 50 +02dd +0020 +05c7 +051e +1e8c +0f30 +157e +0ccb +1c29 +0213 -- 60 +094c +1bd4 +16cf +14d1 +100b +0a08 +0ac1 +0fb0 +0f10 +0824 -- 70 +17c3 +15fe +0d68 +1659 +127d +064c +1397 +19ba +0e74 +0d3e -- 80 +0a5c +1704 +0686 +0b32 +1d47 +0201 +19f5 +1ff6 +192d +0611 -- 90 +1a67 +0bc9 +0509 +1c98 +1c3e +01aa +1604 +107e +06e4 +1bca -- 100 +0273 +0f50 +13fd +0b58 +1f63 +0cde +12b7 +0f6d +12a1 +1840 -- 110 +1b98 +1bc3 +1e57 +0eea +17b7 +1247 +154e +0b9d +1789 +0e0a -- 120 +1013 +0aca +1682 +08ff +0dbd +0bf9 +10f5 +10d0 +1a1b +10d2 +1047 +0318 +12d6 +12aa +0aca +1b0c +0306 +1b2e +0bcf +1069 +0f49 +0a87 +0d55 +00ed +0a78 +1ea3 +0d72 +161e +04e1 +09f6 +0c5c +0a66 +18f5 +18da +0bb6 +17a9 +18cd +0afe +1d9a +1369 +1be9 +01e7 +1552 +01ce +07f8 +1880 +08ed +0bad +0420 +1caa +0f41 +1a20 +1fce +0720 +1ec0 +058c +1d75 +1595 +1e86 +0f19 +1e87 +1ad7 +0bef +1025 +0475 +05e0 +0a23 +19fc +06f3 +1320 +023f +1808 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/firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/memory_files/analog_input_ch4.txt (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/memory_files/analog_input_ch4.txt (revision 9841) @@ -0,0 +1,1024 @@ +0e3d +1f6d +1e38 +137d +1f25 +1918 +0d7e +0fc2 +0f75 +07ca +044e +15d0 +0140 +08d5 +13ac +1501 +127d +1ed3 +006e +1e10 +0ec1 +0382 +041a +0013 +006d +0df9 +0ef6 +1cda +0edf +09f3 +1889 +162c +108f +073d +1b7f +0c16 +0f6f +09ae +0361 +00cc +0d18 +1d87 +0220 +0bef +0868 +1728 +1a29 +173a +03f3 +0032 +0b20 +03f5 +0062 +0261 +1fce +0aba +1b52 +1e24 +130f +112c +0a21 +10a3 +00e3 +0582 +0f40 +0e21 +0540 +1a02 +0d56 +0796 +0592 +08cf +1b72 +1fa2 +10f7 +113a +0161 +182a +17ab +0945 +13cf +17bc +18e6 +0ead +1ed3 +1494 +15ca +0e2e +076e +10c4 +10c3 +114a +169e +1235 +16aa +1c74 +1ca4 +1c9e +1cae +1a46 +11e7 +0027 +09e4 +1c5d +1a9f +0250 +0883 +00c0 +1169 +0e94 +0959 +0327 +0679 +09ca +1d5c +1265 +17bd +1236 +06ae +1aac +1857 +1711 +1293 +1c91 +16d2 +1448 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/firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/memory_files/analog_input_ch6.txt =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/memory_files/analog_input_ch6.txt (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/memory_files/analog_input_ch6.txt (revision 9841) @@ -0,0 +1,1024 @@ +1f61 +01c1 +0139 +0630 +1f1b +1f0e +038e +09f0 +14ac +1dc8 +1c6a +1a59 +07c0 +122c +166a +19b9 +1a8a +1311 +0e34 +195b +1c81 +005c +0812 +1ca0 +1ddc +0279 +1860 +052d +0a1f +1939 +070e +0f2a +017d +0a16 +1c40 +119a +19a0 +003b +0a9f +10ab +0377 +18a9 +02dc +1485 +1161 +0774 +18a6 +17d9 +11d8 +1346 +09b6 +0b2c +0b1b +0390 +1eb6 +1f04 +19af +0498 +0853 +1ca1 +06ae +1e60 +1fd1 +1b72 +16b9 +0d40 +18dc +1daa +15eb +04d0 +0019 +1a4e +0871 +1d88 +15e4 +03d7 +1d7f +138d +0b3f +1668 +09d2 +0087 +1355 +16d9 +0f83 +1be2 +040e +1dec +0b60 +1d3b +17ea +1507 +17e7 +0dfe +09fd +0516 +18d8 +0769 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/firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/memory_files/drs_stop_cells.txt (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/memory_files/drs_stop_cells.txt (revision 9841) @@ -0,0 +1,1024 @@ +08e +3f6 +315 +39a +075 +1d7 +2e4 +179 +087 +033 +004 +39b +01f +30d +228 +2b5 +3d9 +11e +0c4 +132 +16b +2f9 +156 +121 +263 +0eb +15e +29e +0b6 +2a2 +170 +255 +3b6 +065 +15f +15f +256 +007 +0bb +181 +1ca +1da +3d1 +130 +2b8 +03f +379 +2a2 +393 +266 +31a +032 +0fd +28d +169 +195 +29f +1f4 +136 +389 +079 +045 +0c2 +1e5 +2c3 +1af +3e5 +3b9 +1ae +0c9 +05f +3d1 +063 +343 +367 +391 +327 +026 +268 +224 +172 +2bb +30a +250 +387 +13d +157 +128 +2fb +3ca +2bf +061 +2d0 +131 +107 +184 +117 +1eb +26d +108 +059 +3bf +0f4 +2ca +207 +348 +3cf +1ba +325 +1d8 +26d +279 +38b +312 +216 +1bd +13a +272 +25e +185 +057 +2bc +0be +1e4 +209 +3fd +101 +331 +23b +1e3 +279 +13c +1b8 +160 +1ca +1b3 +1c7 +03f +049 +03e +16e +39d +203 +122 +15c +045 +0d6 +3be +31a +349 +049 +2a5 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+1e5 +0fe +113 +3b9 +1b7 +314 +100 +2e6 +1b0 +230 +026 +2a2 +0f8 +28c +08b +357 +2b3 +385 +39a +1fe +1b3 +10a +1fb +053 +0df +393 +179 +13d +149 +16c +1f6 +001 +38f +30b +34f +152 +32d +11b +39d +0d9 +0c5 +393 +3e3 +057 +28d +0dc +2cf +111 +1e8 +1de +017 +1da +3bc +1d6 +05c +0db +303 +0c0 +2da +224 +19b +3c3 +19d +044 +03a +024 +313 +1ed +33d +338 +02a +197 +3e7 +2c1 +139 +21f +126 +1a3 +1c5 +002 +0c3 +067 +355 +36a +155 +01c +044 +1b8 +2af +273 +24f +26d +241 +179 +33e +101 +1f6 +39f +01d +268 +1c9 +0e2 +1d4 +2af +1b4 +280 +1f2 +0fb +09d +23c +3b5 +15f +2fa +2d7 +160 +134 +06e +233 +2ee +01e +3df +15a +33e +0c9 +0e8 +1bc +355 +26e +382 +037 +029 +186 +186 +35c +238 +3e1 +292 +0a5 +1b6 +2d5 +229 +348 +11b +072 +2bd +0ef +373 +36a +018 +20a +093 +3c2 +0b0 +3ff +288 +06f +1a3 +10a +1c7 +3f8 +32a +384 +179 +065 +212 +22e +3d9 +39d +09e +17f +2a1 +3c8 +07c +019 +1f4 +097 +03e +2cb +20c +3f8 +248 +3eb +255 +178 +3a4 +066 +0d6 +187 +0d4 +1c9 +23d +188 +2de +1be +3aa +2a4 +1cf +0b5 +25f +08e +116 +3d5 +2cc +299 +369 +0ca +346 +096 +20a +1f1 +031 +2d8 +2fe +1ce +1af +33f +12f +000 +0c1 +1ac +158 +252 +2c9 +2d5 +341 +118 +0ea +2be +06f +350 +2c7 +389 +06b +17d +2e2 +272 +11e +3bb +20f +2d9 +120 +03f +37c +2e2 +198 +365 +28a +110 +00e +06b +175 +1ce +3f3 +0b3 +335 +2c4 +10c +3f7 +357 +250 +3e0 +087 +027 +2ba +329 +0a8 +26c +180 +2ec +33c +220 +173 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/memory_files/simple_counter.txt =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/memory_files/simple_counter.txt (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/memory_files/simple_counter.txt (revision 9841) @@ -0,0 +1,1024 @@ +0000 -- 0 +0001 -- 1 +0002 -- 2 +0003 -- 3 +0004 -- 4 +0005 -- 5 +0006 -- 6 +0007 -- 7 +0008 -- 8 +0009 -- 9 +000a -- 10 +000b -- 11 +000c -- 12 +000d -- 13 +000e -- 14 +000f -- 15 +0010 -- 16 +0011 -- 17 +0012 -- 18 +0013 -- 19 +0014 -- 20 +0015 -- 21 +0016 -- 22 +0017 -- 23 +0018 -- 24 +0019 -- 25 +001a -- 26 +001b -- 27 +001c -- 28 +001d -- 29 +001e -- 30 +001f -- 31 +0020 -- 32 +0021 -- 33 +0022 -- 34 +0023 -- 35 +0024 -- 36 +0025 -- 37 +0026 -- 38 +0027 -- 39 +0028 -- 40 +0029 -- 41 +002a -- 42 +002b -- 43 +002c -- 44 +002d -- 45 +002e -- 46 +002f -- 47 +0030 -- 48 +0031 -- 49 +0032 -- 50 +0033 -- 51 +0034 -- 52 +0035 -- 53 +0036 -- 54 +0037 -- 55 +0038 -- 56 +0039 -- 57 +003a -- 58 +003b -- 59 +003c -- 60 +003d -- 61 +003e -- 62 +003f -- 63 +0040 -- 64 +0041 -- 65 +0042 -- 66 +0043 -- 67 +0044 -- 68 +0045 -- 69 +0046 -- 70 +0047 -- 71 +0048 -- 72 +0049 -- 73 +004a -- 74 +004b -- 75 +004c -- 76 +004d -- 77 +004e -- 78 +004f -- 79 +0050 -- 80 +0051 -- 81 +0052 -- 82 +0053 -- 83 +0054 -- 84 +0055 -- 85 +0056 -- 86 +0057 -- 87 +0058 -- 88 +0059 -- 89 +005a -- 90 +005b -- 91 +005c -- 92 +005d -- 93 +005e -- 94 +005f -- 95 +0060 -- 96 +0061 -- 97 +0062 -- 98 +0063 -- 99 +0064 -- 100 +0065 -- 101 +0066 -- 102 +0067 -- 103 +0068 -- 104 +0069 -- 105 +006a -- 106 +006b -- 107 +006c -- 108 +006d -- 109 +006e -- 110 +006f -- 111 +0070 -- 112 +0071 -- 113 +0072 -- 114 +0073 -- 115 +0074 -- 116 +0075 -- 117 +0076 -- 118 +0077 -- 119 +0078 -- 120 +0079 -- 121 +007a -- 122 +007b -- 123 +007c -- 124 +007d -- 125 +007e -- 126 +007f -- 127 +0080 -- 128 +0081 -- 129 +0082 -- 130 +0083 -- 131 +0084 -- 132 +0085 -- 133 +0086 -- 134 +0087 -- 135 +0088 -- 136 +0089 -- 137 +008a -- 138 +008b -- 139 +008c -- 140 +008d -- 141 +008e -- 142 +008f -- 143 +0090 -- 144 +0091 -- 145 +0092 -- 146 +0093 -- 147 +0094 -- 148 +0095 -- 149 +0096 -- 150 +0097 -- 151 +0098 -- 152 +0099 -- 153 +009a -- 154 +009b -- 155 +009c -- 156 +009d -- 157 +009e -- 158 +009f -- 159 +00a0 -- 160 +00a1 -- 161 +00a2 -- 162 +00a3 -- 163 +00a4 -- 164 +00a5 -- 165 +00a6 -- 166 +00a7 -- 167 +00a8 -- 168 +00a9 -- 169 +00aa -- 170 +00ab -- 171 +00ac -- 172 +00ad -- 173 +00ae -- 174 +00af -- 175 +00b0 -- 176 +00b1 -- 177 +00b2 -- 178 +00b3 -- 179 +00b4 -- 180 +00b5 -- 181 +00b6 -- 182 +00b7 -- 183 +00b8 -- 184 +00b9 -- 185 +00ba -- 186 +00bb -- 187 +00bc -- 188 +00bd -- 189 +00be -- 190 +00bf -- 191 +00c0 -- 192 +00c1 -- 193 +00c2 -- 194 +00c3 -- 195 +00c4 -- 196 +00c5 -- 197 +00c6 -- 198 +00c7 -- 199 +00c8 -- 200 +00c9 -- 201 +00ca -- 202 +00cb -- 203 +00cc -- 204 +00cd -- 205 +00ce -- 206 +00cf -- 207 +00d0 -- 208 +00d1 -- 209 +00d2 -- 210 +00d3 -- 211 +00d4 -- 212 +00d5 -- 213 +00d6 -- 214 +00d7 -- 215 +00d8 -- 216 +00d9 -- 217 +00da -- 218 +00db -- 219 +00dc -- 220 +00dd -- 221 +00de -- 222 +00df -- 223 +00e0 -- 224 +00e1 -- 225 +00e2 -- 226 +00e3 -- 227 +00e4 -- 228 +00e5 -- 229 +00e6 -- 230 +00e7 -- 231 +00e8 -- 232 +00e9 -- 233 +00ea -- 234 +00eb -- 235 +00ec -- 236 +00ed -- 237 +00ee -- 238 +00ef -- 239 +00f0 -- 240 +00f1 -- 241 +00f2 -- 242 +00f3 -- 243 +00f4 -- 244 +00f5 -- 245 +00f6 -- 246 +00f7 -- 247 +00f8 -- 248 +00f9 -- 249 +00fa -- 250 +00fb -- 251 +00fc -- 252 +00fd -- 253 +00fe -- 254 +00ff -- 255 +0100 -- 256 +0101 -- 257 +0102 -- 258 +0103 -- 259 +0104 -- 260 +0105 -- 261 +0106 -- 262 +0107 -- 263 +0108 -- 264 +0109 -- 265 +010a -- 266 +010b -- 267 +010c -- 268 +010d -- 269 +010e -- 270 +010f -- 271 +0110 -- 272 +0111 -- 273 +0112 -- 274 +0113 -- 275 +0114 -- 276 +0115 -- 277 +0116 -- 278 +0117 -- 279 +0118 -- 280 +0119 -- 281 +011a -- 282 +011b -- 283 +011c -- 284 +011d -- 285 +011e -- 286 +011f -- 287 +0120 -- 288 +0121 -- 289 +0122 -- 290 +0123 -- 291 +0124 -- 292 +0125 -- 293 +0126 -- 294 +0127 -- 295 +0128 -- 296 +0129 -- 297 +012a -- 298 +012b -- 299 +012c -- 300 +012d -- 301 +012e -- 302 +012f -- 303 +0130 -- 304 +0131 -- 305 +0132 -- 306 +0133 -- 307 +0134 -- 308 +0135 -- 309 +0136 -- 310 +0137 -- 311 +0138 -- 312 +0139 -- 313 +013a -- 314 +013b -- 315 +013c -- 316 +013d -- 317 +013e -- 318 +013f -- 319 +0140 -- 320 +0141 -- 321 +0142 -- 322 +0143 -- 323 +0144 -- 324 +0145 -- 325 +0146 -- 326 +0147 -- 327 +0148 -- 328 +0149 -- 329 +014a -- 330 +014b -- 331 +014c -- 332 +014d -- 333 +014e -- 334 +014f -- 335 +0150 -- 336 +0151 -- 337 +0152 -- 338 +0153 -- 339 +0154 -- 340 +0155 -- 341 +0156 -- 342 +0157 -- 343 +0158 -- 344 +0159 -- 345 +015a -- 346 +015b -- 347 +015c -- 348 +015d -- 349 +015e -- 350 +015f -- 351 +0160 -- 352 +0161 -- 353 +0162 -- 354 +0163 -- 355 +0164 -- 356 +0165 -- 357 +0166 -- 358 +0167 -- 359 +0168 -- 360 +0169 -- 361 +016a -- 362 +016b -- 363 +016c -- 364 +016d -- 365 +016e -- 366 +016f -- 367 +0170 -- 368 +0171 -- 369 +0172 -- 370 +0173 -- 371 +0174 -- 372 +0175 -- 373 +0176 -- 374 +0177 -- 375 +0178 -- 376 +0179 -- 377 +017a -- 378 +017b -- 379 +017c -- 380 +017d -- 381 +017e -- 382 +017f -- 383 +0180 -- 384 +0181 -- 385 +0182 -- 386 +0183 -- 387 +0184 -- 388 +0185 -- 389 +0186 -- 390 +0187 -- 391 +0188 -- 392 +0189 -- 393 +018a -- 394 +018b -- 395 +018c -- 396 +018d -- 397 +018e -- 398 +018f -- 399 +0190 -- 400 +0191 -- 401 +0192 -- 402 +0193 -- 403 +0194 -- 404 +0195 -- 405 +0196 -- 406 +0197 -- 407 +0198 -- 408 +0199 -- 409 +019a -- 410 +019b -- 411 +019c -- 412 +019d -- 413 +019e -- 414 +019f -- 415 +01a0 -- 416 +01a1 -- 417 +01a2 -- 418 +01a3 -- 419 +01a4 -- 420 +01a5 -- 421 +01a6 -- 422 +01a7 -- 423 +01a8 -- 424 +01a9 -- 425 +01aa -- 426 +01ab -- 427 +01ac -- 428 +01ad -- 429 +01ae -- 430 +01af -- 431 +01b0 -- 432 +01b1 -- 433 +01b2 -- 434 +01b3 -- 435 +01b4 -- 436 +01b5 -- 437 +01b6 -- 438 +01b7 -- 439 +01b8 -- 440 +01b9 -- 441 +01ba -- 442 +01bb -- 443 +01bc -- 444 +01bd -- 445 +01be -- 446 +01bf -- 447 +01c0 -- 448 +01c1 -- 449 +01c2 -- 450 +01c3 -- 451 +01c4 -- 452 +01c5 -- 453 +01c6 -- 454 +01c7 -- 455 +01c8 -- 456 +01c9 -- 457 +01ca -- 458 +01cb -- 459 +01cc -- 460 +01cd -- 461 +01ce -- 462 +01cf -- 463 +01d0 -- 464 +01d1 -- 465 +01d2 -- 466 +01d3 -- 467 +01d4 -- 468 +01d5 -- 469 +01d6 -- 470 +01d7 -- 471 +01d8 -- 472 +01d9 -- 473 +01da -- 474 +01db -- 475 +01dc -- 476 +01dd -- 477 +01de -- 478 +01df -- 479 +01e0 -- 480 +01e1 -- 481 +01e2 -- 482 +01e3 -- 483 +01e4 -- 484 +01e5 -- 485 +01e6 -- 486 +01e7 -- 487 +01e8 -- 488 +01e9 -- 489 +01ea -- 490 +01eb -- 491 +01ec -- 492 +01ed -- 493 +01ee -- 494 +01ef -- 495 +01f0 -- 496 +01f1 -- 497 +01f2 -- 498 +01f3 -- 499 +01f4 -- 500 +01f5 -- 501 +01f6 -- 502 +01f7 -- 503 +01f8 -- 504 +01f9 -- 505 +01fa -- 506 +01fb -- 507 +01fc -- 508 +01fd -- 509 +01fe -- 510 +01ff -- 511 +0200 -- 512 +0201 -- 513 +0202 -- 514 +0203 -- 515 +0204 -- 516 +0205 -- 517 +0206 -- 518 +0207 -- 519 +0208 -- 520 +0209 -- 521 +020a -- 522 +020b -- 523 +020c -- 524 +020d -- 525 +020e -- 526 +020f -- 527 +0210 -- 528 +0211 -- 529 +0212 -- 530 +0213 -- 531 +0214 -- 532 +0215 -- 533 +0216 -- 534 +0217 -- 535 +0218 -- 536 +0219 -- 537 +021a -- 538 +021b -- 539 +021c -- 540 +021d -- 541 +021e -- 542 +021f -- 543 +0220 -- 544 +0221 -- 545 +0222 -- 546 +0223 -- 547 +0224 -- 548 +0225 -- 549 +0226 -- 550 +0227 -- 551 +0228 -- 552 +0229 -- 553 +022a -- 554 +022b -- 555 +022c -- 556 +022d -- 557 +022e -- 558 +022f -- 559 +0230 -- 560 +0231 -- 561 +0232 -- 562 +0233 -- 563 +0234 -- 564 +0235 -- 565 +0236 -- 566 +0237 -- 567 +0238 -- 568 +0239 -- 569 +023a -- 570 +023b -- 571 +023c -- 572 +023d -- 573 +023e -- 574 +023f -- 575 +0240 -- 576 +0241 -- 577 +0242 -- 578 +0243 -- 579 +0244 -- 580 +0245 -- 581 +0246 -- 582 +0247 -- 583 +0248 -- 584 +0249 -- 585 +024a -- 586 +024b -- 587 +024c -- 588 +024d -- 589 +024e -- 590 +024f -- 591 +0250 -- 592 +0251 -- 593 +0252 -- 594 +0253 -- 595 +0254 -- 596 +0255 -- 597 +0256 -- 598 +0257 -- 599 +0258 -- 600 +0259 -- 601 +025a -- 602 +025b -- 603 +025c -- 604 +025d -- 605 +025e -- 606 +025f -- 607 +0260 -- 608 +0261 -- 609 +0262 -- 610 +0263 -- 611 +0264 -- 612 +0265 -- 613 +0266 -- 614 +0267 -- 615 +0268 -- 616 +0269 -- 617 +026a -- 618 +026b -- 619 +026c -- 620 +026d -- 621 +026e -- 622 +026f -- 623 +0270 -- 624 +0271 -- 625 +0272 -- 626 +0273 -- 627 +0274 -- 628 +0275 -- 629 +0276 -- 630 +0277 -- 631 +0278 -- 632 +0279 -- 633 +027a -- 634 +027b -- 635 +027c -- 636 +027d -- 637 +027e -- 638 +027f -- 639 +0280 -- 640 +0281 -- 641 +0282 -- 642 +0283 -- 643 +0284 -- 644 +0285 -- 645 +0286 -- 646 +0287 -- 647 +0288 -- 648 +0289 -- 649 +028a -- 650 +028b -- 651 +028c -- 652 +028d -- 653 +028e -- 654 +028f -- 655 +0290 -- 656 +0291 -- 657 +0292 -- 658 +0293 -- 659 +0294 -- 660 +0295 -- 661 +0296 -- 662 +0297 -- 663 +0298 -- 664 +0299 -- 665 +029a -- 666 +029b -- 667 +029c -- 668 +029d -- 669 +029e -- 670 +029f -- 671 +02a0 -- 672 +02a1 -- 673 +02a2 -- 674 +02a3 -- 675 +02a4 -- 676 +02a5 -- 677 +02a6 -- 678 +02a7 -- 679 +02a8 -- 680 +02a9 -- 681 +02aa -- 682 +02ab -- 683 +02ac -- 684 +02ad -- 685 +02ae -- 686 +02af -- 687 +02b0 -- 688 +02b1 -- 689 +02b2 -- 690 +02b3 -- 691 +02b4 -- 692 +02b5 -- 693 +02b6 -- 694 +02b7 -- 695 +02b8 -- 696 +02b9 -- 697 +02ba -- 698 +02bb -- 699 +02bc -- 700 +02bd -- 701 +02be -- 702 +02bf -- 703 +02c0 -- 704 +02c1 -- 705 +02c2 -- 706 +02c3 -- 707 +02c4 -- 708 +02c5 -- 709 +02c6 -- 710 +02c7 -- 711 +02c8 -- 712 +02c9 -- 713 +02ca -- 714 +02cb -- 715 +02cc -- 716 +02cd -- 717 +02ce -- 718 +02cf -- 719 +02d0 -- 720 +02d1 -- 721 +02d2 -- 722 +02d3 -- 723 +02d4 -- 724 +02d5 -- 725 +02d6 -- 726 +02d7 -- 727 +02d8 -- 728 +02d9 -- 729 +02da -- 730 +02db -- 731 +02dc -- 732 +02dd -- 733 +02de -- 734 +02df -- 735 +02e0 -- 736 +02e1 -- 737 +02e2 -- 738 +02e3 -- 739 +02e4 -- 740 +02e5 -- 741 +02e6 -- 742 +02e7 -- 743 +02e8 -- 744 +02e9 -- 745 +02ea -- 746 +02eb -- 747 +02ec -- 748 +02ed -- 749 +02ee -- 750 +02ef -- 751 +02f0 -- 752 +02f1 -- 753 +02f2 -- 754 +02f3 -- 755 +02f4 -- 756 +02f5 -- 757 +02f6 -- 758 +02f7 -- 759 +02f8 -- 760 +02f9 -- 761 +02fa -- 762 +02fb -- 763 +02fc -- 764 +02fd -- 765 +02fe -- 766 +02ff -- 767 +0300 -- 768 +0301 -- 769 +0302 -- 770 +0303 -- 771 +0304 -- 772 +0305 -- 773 +0306 -- 774 +0307 -- 775 +0308 -- 776 +0309 -- 777 +030a -- 778 +030b -- 779 +030c -- 780 +030d -- 781 +030e -- 782 +030f -- 783 +0310 -- 784 +0311 -- 785 +0312 -- 786 +0313 -- 787 +0314 -- 788 +0315 -- 789 +0316 -- 790 +0317 -- 791 +0318 -- 792 +0319 -- 793 +031a -- 794 +031b -- 795 +031c -- 796 +031d -- 797 +031e -- 798 +031f -- 799 +0320 -- 800 +0321 -- 801 +0322 -- 802 +0323 -- 803 +0324 -- 804 +0325 -- 805 +0326 -- 806 +0327 -- 807 +0328 -- 808 +0329 -- 809 +032a -- 810 +032b -- 811 +032c -- 812 +032d -- 813 +032e -- 814 +032f -- 815 +0330 -- 816 +0331 -- 817 +0332 -- 818 +0333 -- 819 +0334 -- 820 +0335 -- 821 +0336 -- 822 +0337 -- 823 +0338 -- 824 +0339 -- 825 +033a -- 826 +033b -- 827 +033c -- 828 +033d -- 829 +033e -- 830 +033f -- 831 +0340 -- 832 +0341 -- 833 +0342 -- 834 +0343 -- 835 +0344 -- 836 +0345 -- 837 +0346 -- 838 +0347 -- 839 +0348 -- 840 +0349 -- 841 +034a -- 842 +034b -- 843 +034c -- 844 +034d -- 845 +034e -- 846 +034f -- 847 +0350 -- 848 +0351 -- 849 +0352 -- 850 +0353 -- 851 +0354 -- 852 +0355 -- 853 +0356 -- 854 +0357 -- 855 +0358 -- 856 +0359 -- 857 +035a -- 858 +035b -- 859 +035c -- 860 +035d -- 861 +035e -- 862 +035f -- 863 +0360 -- 864 +0361 -- 865 +0362 -- 866 +0363 -- 867 +0364 -- 868 +0365 -- 869 +0366 -- 870 +0367 -- 871 +0368 -- 872 +0369 -- 873 +036a -- 874 +036b -- 875 +036c -- 876 +036d -- 877 +036e -- 878 +036f -- 879 +0370 -- 880 +0371 -- 881 +0372 -- 882 +0373 -- 883 +0374 -- 884 +0375 -- 885 +0376 -- 886 +0377 -- 887 +0378 -- 888 +0379 -- 889 +037a -- 890 +037b -- 891 +037c -- 892 +037d -- 893 +037e -- 894 +037f -- 895 +0380 -- 896 +0381 -- 897 +0382 -- 898 +0383 -- 899 +0384 -- 900 +0385 -- 901 +0386 -- 902 +0387 -- 903 +0388 -- 904 +0389 -- 905 +038a -- 906 +038b -- 907 +038c -- 908 +038d -- 909 +038e -- 910 +038f -- 911 +0390 -- 912 +0391 -- 913 +0392 -- 914 +0393 -- 915 +0394 -- 916 +0395 -- 917 +0396 -- 918 +0397 -- 919 +0398 -- 920 +0399 -- 921 +039a -- 922 +039b -- 923 +039c -- 924 +039d -- 925 +039e -- 926 +039f -- 927 +03a0 -- 928 +03a1 -- 929 +03a2 -- 930 +03a3 -- 931 +03a4 -- 932 +03a5 -- 933 +03a6 -- 934 +03a7 -- 935 +03a8 -- 936 +03a9 -- 937 +03aa -- 938 +03ab -- 939 +03ac -- 940 +03ad -- 941 +03ae -- 942 +03af -- 943 +03b0 -- 944 +03b1 -- 945 +03b2 -- 946 +03b3 -- 947 +03b4 -- 948 +03b5 -- 949 +03b6 -- 950 +03b7 -- 951 +03b8 -- 952 +03b9 -- 953 +03ba -- 954 +03bb -- 955 +03bc -- 956 +03bd -- 957 +03be -- 958 +03bf -- 959 +03c0 -- 960 +03c1 -- 961 +03c2 -- 962 +03c3 -- 963 +03c4 -- 964 +03c5 -- 965 +03c6 -- 966 +03c7 -- 967 +03c8 -- 968 +03c9 -- 969 +03ca -- 970 +03cb -- 971 +03cc -- 972 +03cd -- 973 +03ce -- 974 +03cf -- 975 +03d0 -- 976 +03d1 -- 977 +03d2 -- 978 +03d3 -- 979 +03d4 -- 980 +03d5 -- 981 +03d6 -- 982 +03d7 -- 983 +03d8 -- 984 +03d9 -- 985 +03da -- 986 +03db -- 987 +03dc -- 988 +03dd -- 989 +03de -- 990 +03df -- 991 +03e0 -- 992 +03e1 -- 993 +03e2 -- 994 +03e3 -- 995 +03e4 -- 996 +03e5 -- 997 +03e6 -- 998 +03e7 -- 999 +03e8 -- 1000 +03e9 -- 1001 +03ea -- 1002 +03eb -- 1003 +03ec -- 1004 +03ed -- 1005 +03ee -- 1006 +03ef -- 1007 +03f0 -- 1008 +03f1 -- 1009 +03f2 -- 1010 +03f3 -- 1011 +03f4 -- 1012 +03f5 -- 1013 +03f6 -- 1014 +03f7 -- 1015 +03f8 -- 1016 +03f9 -- 1017 +03fa -- 1018 +03fb -- 1019 +03fc -- 1020 +03fd -- 1021 +03fe -- 1022 +03ff -- 1023 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/simulation_files/adcTB_complete.do =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/simulation_files/adcTB_complete.do (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/simulation_files/adcTB_complete.do (revision 9841) @@ -0,0 +1,30 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider {ADC EMULATOR} +add wave -noupdate /adc_emulator_tb/clk +add wave -noupdate /adc_emulator_tb/otr +add wave -noupdate /adc_emulator_tb/oeb +add wave -noupdate -radix hexadecimal /adc_emulator_tb/data +add wave -noupdate -divider {ADC ROM} +add wave -noupdate -expand -group {adc rom} -radix hexadecimal /adc_emulator_tb/i_adctb_adc/rom_addr +add wave -noupdate -expand -group {adc rom} -radix hexadecimal /adc_emulator_tb/i_adctb_adc/rom_data +add wave -noupdate -expand -group {adc rom} -radix hexadecimal /adc_emulator_tb/i_adctb_adc/rom_reg +add wave -noupdate -expand -group {adc rom} -radix hexadecimal -subitemconfig {/adc_emulator_tb/i_adctb_adc/rom(0) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(2) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(3) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(4) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(5) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(6) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(7) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(8) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(9) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(10) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(11) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(12) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(13) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(14) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(15) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(16) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(17) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(18) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(19) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(20) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(21) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(22) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(23) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(24) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(25) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(26) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(27) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(28) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(29) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(30) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(31) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(32) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(33) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(34) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(35) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(36) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(37) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(38) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(39) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(40) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(41) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(42) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(43) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(44) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(45) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(46) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(47) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(48) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(49) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(50) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(51) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(52) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(53) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(54) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(55) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(56) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(57) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(58) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(59) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(60) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(61) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(62) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(63) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(64) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(65) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(66) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(67) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(68) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(69) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(70) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(71) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(72) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(73) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(74) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(75) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(76) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(77) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(78) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(79) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(80) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(81) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(82) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(83) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(84) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(85) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(86) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(87) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(88) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(89) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(90) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(91) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(92) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(93) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(94) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(95) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(96) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(97) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(98) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(99) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(100) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(101) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(102) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(103) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(104) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(105) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(106) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(107) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(108) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(109) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(110) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(111) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(112) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(113) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(114) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(115) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(116) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(117) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(118) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(119) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(120) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(121) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(122) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(123) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(124) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(125) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(126) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(127) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(128) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(129) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(130) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(131) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(132) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(133) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(134) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(135) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(136) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(137) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(138) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(139) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(140) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(141) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(142) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(143) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(144) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(145) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(146) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(147) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(148) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(149) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(150) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(151) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(152) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(153) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(154) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(155) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(156) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(157) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(158) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(159) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(160) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(161) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(162) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(163) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(164) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(165) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(166) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(167) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(168) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(169) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(170) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(171) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(172) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(173) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(174) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(175) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(176) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(177) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(178) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(179) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(180) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(181) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(182) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(183) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(184) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(185) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(186) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(187) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(188) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(189) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(190) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(191) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(192) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(193) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(194) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(195) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(196) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(197) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(198) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(199) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(200) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(201) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(202) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(203) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(204) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(205) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(206) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(207) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(208) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(209) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(210) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(211) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(212) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(213) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(214) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(215) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(216) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(217) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(218) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(219) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(220) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(221) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(222) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(223) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(224) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(225) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(226) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(227) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(228) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(229) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(230) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(231) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(232) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(233) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(234) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(235) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(236) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(237) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(238) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(239) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(240) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(241) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(242) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(243) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(244) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(245) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(246) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(247) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(248) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(249) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(250) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(251) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(252) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(253) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(254) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(255) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(256) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(257) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(258) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(259) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(260) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(261) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(262) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(263) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(264) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(265) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(266) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(267) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(268) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(269) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(270) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(271) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(272) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(273) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(274) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(275) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(276) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(277) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(278) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(279) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(280) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(281) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(282) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(283) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(284) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(285) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(286) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(287) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(288) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(289) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(290) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(291) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(292) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(293) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(294) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(295) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(296) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(297) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(298) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(299) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(300) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(301) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(302) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(303) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(304) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(305) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(306) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(307) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(308) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(309) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(310) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(311) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(312) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(313) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(314) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(315) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(316) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(317) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(318) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(319) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(320) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(321) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(322) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(323) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(324) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(325) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(326) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(327) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(328) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(329) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(330) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(331) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(332) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(333) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(334) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(335) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(336) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(337) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(338) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(339) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(340) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(341) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(342) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(343) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(344) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(345) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(346) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(347) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(348) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(349) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(350) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(351) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(352) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(353) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(354) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(355) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(356) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(357) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(358) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(359) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(360) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(361) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(362) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(363) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(364) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(365) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(366) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(367) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(368) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(369) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(370) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(371) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(372) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(373) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(374) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(375) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(376) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(377) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(378) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(379) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(380) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(381) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(382) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(383) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(384) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(385) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(386) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(387) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(388) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(389) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(390) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(391) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(392) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(393) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(394) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(395) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(396) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(397) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(398) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(399) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(400) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(401) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(402) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(403) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(404) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(405) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(406) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(407) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(408) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(409) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(410) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(411) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(412) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(413) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(414) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(415) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(416) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(417) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(418) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(419) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(420) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(421) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(422) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(423) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(424) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(425) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(426) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(427) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(428) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(429) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(430) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(431) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(432) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(433) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(434) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(435) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(436) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(437) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(438) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(439) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(440) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(441) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(442) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(443) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(444) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(445) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(446) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(447) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(448) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(449) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(450) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(451) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(452) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(453) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(454) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(455) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(456) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(457) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(458) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(459) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(460) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(461) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(462) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(463) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(464) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(465) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(466) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(467) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(468) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(469) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(470) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(471) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(472) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(473) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(474) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(475) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(476) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(477) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(478) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(479) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(480) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(481) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(482) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(483) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(484) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(485) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(486) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(487) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(488) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(489) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(490) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(491) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(492) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(493) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(494) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(495) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(496) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(497) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(498) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(499) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(500) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(501) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(502) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(503) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(504) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(505) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(506) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(507) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(508) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(509) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(510) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(511) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(512) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(513) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(514) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(515) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(516) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(517) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(518) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(519) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(520) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(521) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(522) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(523) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(524) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(525) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(526) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(527) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(528) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(529) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(530) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(531) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(532) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(533) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(534) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(535) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(536) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(537) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(538) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(539) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(540) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(541) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(542) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(543) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(544) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(545) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(546) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(547) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(548) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(549) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(550) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(551) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(552) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(553) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(554) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(555) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(556) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(557) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(558) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(559) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(560) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(561) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(562) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(563) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(564) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(565) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(566) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(567) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(568) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(569) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(570) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(571) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(572) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(573) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(574) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(575) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(576) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(577) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(578) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(579) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(580) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(581) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(582) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(583) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(584) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(585) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(586) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(587) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(588) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(589) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(590) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(591) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(592) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(593) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(594) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(595) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(596) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(597) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(598) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(599) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(600) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(601) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(602) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(603) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(604) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(605) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(606) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(607) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(608) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(609) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(610) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(611) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(612) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(613) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(614) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(615) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(616) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(617) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(618) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(619) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(620) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(621) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(622) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(623) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(624) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(625) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(626) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(627) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(628) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(629) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(630) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(631) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(632) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(633) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(634) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(635) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(636) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(637) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(638) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(639) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(640) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(641) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(642) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(643) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(644) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(645) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(646) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(647) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(648) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(649) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(650) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(651) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(652) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(653) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(654) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(655) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(656) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(657) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(658) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(659) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(660) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(661) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(662) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(663) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(664) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(665) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(666) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(667) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(668) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(669) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(670) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(671) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(672) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(673) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(674) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(675) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(676) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(677) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(678) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(679) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(680) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(681) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(682) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(683) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(684) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(685) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(686) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(687) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(688) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(689) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(690) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(691) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(692) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(693) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(694) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(695) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(696) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(697) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(698) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(699) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(700) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(701) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(702) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(703) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(704) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(705) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(706) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(707) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(708) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(709) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(710) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(711) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(712) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(713) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(714) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(715) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(716) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(717) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(718) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(719) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(720) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(721) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(722) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(723) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(724) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(725) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(726) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(727) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(728) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(729) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(730) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(731) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(732) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(733) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(734) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(735) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(736) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(737) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(738) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(739) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(740) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(741) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(742) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(743) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(744) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(745) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(746) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(747) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(748) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(749) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(750) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(751) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(752) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(753) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(754) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(755) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(756) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(757) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(758) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(759) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(760) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(761) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(762) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(763) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(764) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(765) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(766) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(767) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(768) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(769) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(770) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(771) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(772) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(773) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(774) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(775) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(776) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(777) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(778) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(779) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(780) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(781) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(782) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(783) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(784) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(785) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(786) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(787) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(788) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(789) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(790) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(791) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(792) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(793) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(794) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(795) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(796) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(797) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(798) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(799) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(800) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(801) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(802) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(803) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(804) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(805) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(806) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(807) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(808) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(809) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(810) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(811) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(812) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(813) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(814) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(815) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(816) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(817) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(818) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(819) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(820) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(821) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(822) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(823) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(824) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(825) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(826) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(827) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(828) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(829) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(830) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(831) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(832) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(833) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(834) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(835) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(836) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(837) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(838) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(839) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(840) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(841) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(842) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(843) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(844) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(845) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(846) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(847) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(848) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(849) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(850) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(851) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(852) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(853) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(854) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(855) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(856) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(857) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(858) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(859) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(860) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(861) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(862) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(863) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(864) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(865) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(866) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(867) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(868) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(869) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(870) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(871) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(872) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(873) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(874) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(875) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(876) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(877) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(878) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(879) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(880) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(881) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(882) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(883) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(884) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(885) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(886) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(887) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(888) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(889) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(890) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(891) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(892) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(893) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(894) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(895) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(896) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(897) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(898) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(899) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(900) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(901) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(902) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(903) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(904) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(905) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(906) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(907) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(908) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(909) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(910) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(911) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(912) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(913) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(914) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(915) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(916) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(917) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(918) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(919) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(920) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(921) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(922) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(923) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(924) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(925) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(926) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(927) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(928) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(929) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(930) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(931) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(932) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(933) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(934) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(935) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(936) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(937) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(938) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(939) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(940) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(941) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(942) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(943) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(944) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(945) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(946) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(947) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(948) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(949) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(950) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(951) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(952) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(953) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(954) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(955) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(956) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(957) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(958) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(959) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(960) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(961) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(962) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(963) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(964) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(965) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(966) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(967) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(968) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(969) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(970) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(971) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(972) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(973) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(974) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(975) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(976) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(977) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(978) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(979) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(980) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(981) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(982) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(983) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(984) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(985) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(986) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(987) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(988) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(989) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(990) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(991) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(992) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(993) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(994) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(995) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(996) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(997) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(998) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(999) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1000) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1001) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1002) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1003) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1004) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1005) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1006) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1007) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1008) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1009) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1010) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1011) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1012) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1013) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1014) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1015) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1016) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1017) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1018) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1019) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1020) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1021) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1022) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1023) {-radix hexadecimal} /adc_emulator_tb/i_adctb_adc/rom(1024) {-radix hexadecimal}} /adc_emulator_tb/i_adctb_adc/rom +add wave -noupdate -expand -group {adc rom} -radix hexadecimal /adc_emulator_tb/i_adctb_adc/input_file +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {1010000 ps} 0} +configure wave -namecolwidth 115 +configure wave -valuecolwidth 152 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {2067988 ps} Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/simulation_files/boardTB_complete.do =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/simulation_files/boardTB_complete.do (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_TB_lib/simulation_files/boardTB_complete.do (revision 9841) @@ -0,0 +1,65 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fad_main_tb/clk +add wave -noupdate /fad_main_tb/clk_50 +add wave -noupdate /fad_main_tb/clk_25_ps +add wave -noupdate /fad_main_tb/trigger +add wave -noupdate -divider ADC +add wave -noupdate -radix hexadecimal /fad_main_tb/adc_data +add wave -noupdate /fad_main_tb/adc_otr +add wave -noupdate -radix hexadecimal /fad_main_tb/adc_data_array +add wave -noupdate /fad_main_tb/adc_oeb +add wave -noupdate /fad_main_tb/adc_otr_array +add wave -noupdate -divider {DRS4 INTERFACE} +add wave -noupdate /fad_main_tb/denable +add wave -noupdate /fad_main_tb/drs_dwrite +add wave -noupdate -radix unsigned /fad_main_tb/drs_channel_id +add wave -noupdate /fad_main_tb/rsrload +add wave -noupdate /fad_main_tb/srclk +add wave -noupdate /fad_main_tb/srout_in_0 +add wave -noupdate /fad_main_tb/srout_in_1 +add wave -noupdate /fad_main_tb/srout_in_2 +add wave -noupdate /fad_main_tb/srout_in_3 +add wave -noupdate -divider {SPI INTERFACE} +add wave -noupdate /fad_main_tb/sclk +add wave -noupdate /fad_main_tb/mosi +add wave -noupdate /fad_main_tb/sio +add wave -noupdate /fad_main_tb/dac_cs +add wave -noupdate /fad_main_tb/sensor_cs +add wave -noupdate -divider RAM +add wave -noupdate -radix hexadecimal /fad_main_tb/i_maintb_fpga/ram_data +add wave -noupdate -radix hexadecimal /fad_main_tb/i_maintb_fpga/ram_addr +add wave -noupdate -radix hexadecimal /fad_main_tb/i_maintb_fpga/i_main_ethernet/local_ram_start_addr +add wave -noupdate -radix hexadecimal /fad_main_tb/i_maintb_fpga/i_main_ethernet/local_ram_addr +add wave -noupdate -divider {ETHERNET INTERFACE} +add wave -noupdate /fad_main_tb/wiz_reset +add wave -noupdate -radix hexadecimal /fad_main_tb/wiz_addr +add wave -noupdate -radix hexadecimal /fad_main_tb/wiz_data +add wave -noupdate /fad_main_tb/wiz_cs +add wave -noupdate /fad_main_tb/wiz_rd +add wave -noupdate /fad_main_tb/wiz_wr +add wave -noupdate /fad_main_tb/wiz_int +add wave -noupdate -divider {FAD ID} +add wave -noupdate /fad_main_tb/board_id +add wave -noupdate /fad_main_tb/crate_id +add wave -noupdate -divider +add wave -noupdate /fad_main_tb/led +add wave -noupdate /fad_main_tb/i_maintb_fpga/i_main_ethernet/s_trigger +add wave -noupdate /fad_main_tb/i_maintb_fpga/i_main_ethernet/chk_recv_cntr +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {3394736453 ps} 1} {{Cursor 2} {3394460449 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {3390161132 ps} {3397338868 ps} Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/DCM_25MHz_38nsPS_BEHAVIORAL.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/DCM_25MHz_38nsPS_BEHAVIORAL.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/DCM_25MHz_38nsPS_BEHAVIORAL.vhd (revision 9841) @@ -0,0 +1,183 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 10.1.03 +-- \ \ Application : xaw2vhdl +-- / / Filename : DCM_25MHz_38nsPS.vhd +-- /___/ /\ Timestamp : 03/29/2010 10:34:42 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st C:\DOKUME~1\FPGA_D~1\LOKALE~1\Temp\coregen_FPGA_Developer\coregen\project\DCM_25MHz_38nsPS.xaw C:\DOKUME~1\FPGA_D~1\LOKALE~1\Temp\coregen_FPGA_Developer\coregen\project\DCM_25MHz_38nsPS +--Design Name: DCM_25MHz_38nsPS +--Device: xc3s700a-4fg484 +-- +-- Module DCM_25MHz_38nsPS +-- Written for synthesis tool: Precision + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity DCM_25MHz_38nsPS is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end DCM_25MHz_38nsPS; + +architecture BEHAVIORAL of DCM_25MHz_38nsPS is + +-- hds translate_off + + attribute CLK_FEEDBACK : string ; + attribute CLKDV_DIVIDE : string ; + attribute CLKFX_DIVIDE : string ; + attribute CLKFX_MULTIPLY : string ; + attribute CLKIN_DIVIDE_BY_2 : string ; + attribute CLKIN_PERIOD : string ; + attribute CLKOUT_PHASE_SHIFT : string ; + attribute DESKEW_ADJUST : string ; + attribute DFS_FREQUENCY_MODE : string ; + attribute DLL_FREQUENCY_MODE : string ; + attribute DUTY_CYCLE_CORRECTION : string ; + attribute FACTORY_JF : string ; + attribute PHASE_SHIFT : string ; + attribute STARTUP_WAIT : string ; + signal CLKFB_IN : std_logic; + signal CLKIN_IBUFG : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; + component IBUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + component BUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + component DCM_SP + -- synthesis translate_off + generic( CLK_FEEDBACK : string := "1X"; + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := FALSE; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DUTY_CYCLE_CORRECTION : boolean := TRUE; + FACTORY_JF : bit_vector := x"C080"; + PHASE_SHIFT : integer := 0; + STARTUP_WAIT : boolean := FALSE; + DSS_MODE : string := "NONE"); + -- synthesis translate_on + port ( CLKIN : in std_logic; + CLKFB : in std_logic; + RST : in std_logic; + PSEN : in std_logic; + PSINCDEC : in std_logic; + PSCLK : in std_logic; + DSSEN : in std_logic; + CLK0 : out std_logic; + CLK90 : out std_logic; + CLK180 : out std_logic; + CLK270 : out std_logic; + CLKDV : out std_logic; + CLK2X : out std_logic; + CLK2X180 : out std_logic; + CLKFX : out std_logic; + CLKFX180 : out std_logic; + STATUS : out std_logic_vector (7 downto 0); + LOCKED : out std_logic; + PSDONE : out std_logic); + end component; + + attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X"; + attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0"; + attribute CLKFX_DIVIDE of DCM_SP_INST : label is "1"; + attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "4"; + attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE"; + attribute CLKIN_PERIOD of DCM_SP_INST : label is "40.000"; + attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "FIXED"; + attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS"; + attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; + attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; + attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE"; + attribute FACTORY_JF of DCM_SP_INST : label is "C080"; + attribute PHASE_SHIFT of DCM_SP_INST : label is "243"; + attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE"; + +-- hds translate_on + +begin + +-- hds translate_off + + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLK0_OUT <= CLKFB_IN; + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + -- synthesis translate_off + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 4, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 40.000, + CLKOUT_PHASE_SHIFT => "FIXED", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 243, + STARTUP_WAIT => FALSE) + -- synthesis translate_on + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>open, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + + +-- hds translate_on + +end BEHAVIORAL; + + + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/DCM_25MHz_noPS_BEHAVIORAL.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/DCM_25MHz_noPS_BEHAVIORAL.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/DCM_25MHz_noPS_BEHAVIORAL.vhd (revision 9841) @@ -0,0 +1,189 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 10.1.03 +-- \ \ Application : xaw2vhdl +-- / / Filename : DCM_25MHz_noPS.vhd +-- /___/ /\ Timestamp : 03/29/2010 10:36:52 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st C:/DOKUME~1/FPGA_D~1/LOKALE~1/Temp/coregen_FPGA_Developer/coregen/project/DCM_25MHz_noPS.xaw C:/DOKUME~1/FPGA_D~1/LOKALE~1/Temp/coregen_FPGA_Developer/coregen/project/DCM_25MHz_noPS +--Design Name: DCM_25MHz_noPS +--Device: xc3s700a-4fg484 +-- +-- Module DCM_25MHz_noPS +-- Written for synthesis tool: Precision + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity DCM_25MHz_noPS is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKDV_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end DCM_25MHz_noPS; + +architecture BEHAVIORAL of DCM_25MHz_noPS is + +-- hds translate_off + + attribute CLK_FEEDBACK : string ; + attribute CLKDV_DIVIDE : string ; + attribute CLKFX_DIVIDE : string ; + attribute CLKFX_MULTIPLY : string ; + attribute CLKIN_DIVIDE_BY_2 : string ; + attribute CLKIN_PERIOD : string ; + attribute CLKOUT_PHASE_SHIFT : string ; + attribute DESKEW_ADJUST : string ; + attribute DFS_FREQUENCY_MODE : string ; + attribute DLL_FREQUENCY_MODE : string ; + attribute DUTY_CYCLE_CORRECTION : string ; + attribute FACTORY_JF : string ; + attribute PHASE_SHIFT : string ; + attribute STARTUP_WAIT : string ; + signal CLKDV_BUF : std_logic; + signal CLKFB_IN : std_logic; + signal CLKIN_IBUFG : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; + component BUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + component IBUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + component DCM_SP + -- synthesis translate_off + generic( CLK_FEEDBACK : string := "1X"; + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := FALSE; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DUTY_CYCLE_CORRECTION : boolean := TRUE; + FACTORY_JF : bit_vector := x"C080"; + PHASE_SHIFT : integer := 0; + STARTUP_WAIT : boolean := FALSE; + DSS_MODE : string := "NONE"); + -- synthesis translate_on + port ( CLKIN : in std_logic; + CLKFB : in std_logic; + RST : in std_logic; + PSEN : in std_logic; + PSINCDEC : in std_logic; + PSCLK : in std_logic; + DSSEN : in std_logic; + CLK0 : out std_logic; + CLK90 : out std_logic; + CLK180 : out std_logic; + CLK270 : out std_logic; + CLKDV : out std_logic; + CLK2X : out std_logic; + CLK2X180 : out std_logic; + CLKFX : out std_logic; + CLKFX180 : out std_logic; + STATUS : out std_logic_vector (7 downto 0); + LOCKED : out std_logic; + PSDONE : out std_logic); + end component; + + attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X"; + attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0"; + attribute CLKFX_DIVIDE of DCM_SP_INST : label is "1"; + attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "4"; + attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE"; + attribute CLKIN_PERIOD of DCM_SP_INST : label is "20.000"; + attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "NONE"; + attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS"; + attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; + attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; + attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE"; + attribute FACTORY_JF of DCM_SP_INST : label is "C080"; + attribute PHASE_SHIFT of DCM_SP_INST : label is "0"; + attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE"; + +-- hds translate_on + +begin + +-- hds translate_off + + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLK0_OUT <= CLKFB_IN; + CLKDV_BUFG_INST : BUFG + port map (I=>CLKDV_BUF, + O=>CLKDV_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + -- synthesis translate_off + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 4, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + -- synthesis translate_on + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>CLKDV_BUF, + CLKFX=>open, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + + +-- hds translate_on + +end BEHAVIORAL; + + + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/adc_buffer_beha.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/adc_buffer_beha.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/adc_buffer_beha.vhd (revision 9841) @@ -0,0 +1,47 @@ +-- +-- VHDL Architecture FACT_FAD_lib.adc_buffer.beha +-- +-- Created: +-- by - kai.UNKNOWN (E5PCXX) +-- at - 14:57:55 04.05.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use ieee.STD_LOGIC_UNSIGNED.all; + +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + +library UNISIM; +use UNISIM.VComponents.all; +USE IEEE.NUMERIC_STD.all; +USE IEEE.std_logic_signed.all; + +ENTITY adc_buffer IS + PORT( + clk_ps : IN std_logic; + adc_data_array : IN adc_data_array_type; + adc_otr_array : IN std_logic_vector (3 DOWNTO 0); + adc_data_array_int : OUT adc_data_array_type; + adc_otr : OUT std_logic_vector (3 DOWNTO 0) + ); + +-- Declarations + +END adc_buffer ; + +-- +ARCHITECTURE beha OF adc_buffer IS +BEGIN + adc_buf : process (clk_ps) + begin + if rising_edge (clk_ps) then + adc_data_array_int <= adc_data_array; + adc_otr <= adc_otr_array; + end if; + end process adc_buf; +END ARCHITECTURE beha; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/clock_generator_struct.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/clock_generator_struct.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/clock_generator_struct.vhd (revision 9841) @@ -0,0 +1,95 @@ +-- VHDL Entity FACT_FAD_lib.clock_generator.symbol +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 13:32:31 23.06.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +ENTITY clock_generator IS + PORT( + CLK : IN std_logic; + CLK_25 : OUT std_logic; + CLK_25_PS : OUT std_logic; + CLK_50 : OUT std_logic + ); + +-- Declarations + +END clock_generator ; + +-- +-- VHDL Architecture FACT_FAD_lib.clock_generator.struct +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 13:32:32 23.06.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.numeric_std.all; +LIBRARY UNISIM; +USE UNISIM.Vcomponents.all; + +LIBRARY FACT_FAD_lib; + +ARCHITECTURE struct OF clock_generator IS + + -- Architecture declarations + + -- Internal signal declarations + + -- Implicit buffer signal declarations + SIGNAL CLK_25_internal : std_logic; + + + -- Component Declarations + COMPONENT dcm_50_to_25 + PORT ( + CLKIN_IN : IN std_logic; + CLK0_OUT : OUT std_logic; + CLKFX_OUT : OUT std_logic; + CLKIN_IBUFG_OUT : OUT std_logic + ); + END COMPONENT; + COMPONENT dcm_ps_38ns + PORT ( + CLKIN_IN : IN std_logic; + CLK0_OUT : OUT std_logic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : dcm_50_to_25 USE ENTITY FACT_FAD_lib.dcm_50_to_25; + FOR ALL : dcm_ps_38ns USE ENTITY FACT_FAD_lib.dcm_ps_38ns; + -- pragma synthesis_on + + +BEGIN + + -- Instance port mappings. + U_0 : dcm_50_to_25 + PORT MAP ( + CLKIN_IN => CLK, + CLKFX_OUT => CLK_25_internal, + CLKIN_IBUFG_OUT => OPEN, + CLK0_OUT => CLK_50 + ); + U_1 : dcm_ps_38ns + PORT MAP ( + CLKIN_IN => CLK_25_internal, + CLK0_OUT => CLK_25_PS + ); + + -- Implicit buffered output assignments + CLK_25 <= CLK_25_internal; + +END struct; Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/controlRAM_16bit_x256_controlRAM_16bit_x256_a.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/controlRAM_16bit_x256_controlRAM_16bit_x256_a.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/controlRAM_16bit_x256_controlRAM_16bit_x256_a.vhd (revision 9841) @@ -0,0 +1,139 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file controlRAM_16bit_x256.vhd when simulating +-- the core, controlRAM_16bit_x256. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY controlRAM_16bit_x256 IS + port ( + clka: IN std_logic; + dina: IN std_logic_VECTOR(15 downto 0); + addra: IN std_logic_VECTOR(7 downto 0); + wea: IN std_logic_VECTOR(0 downto 0); + douta: OUT std_logic_VECTOR(15 downto 0)); +END controlRAM_16bit_x256; + +ARCHITECTURE controlRAM_16bit_x256_a OF controlRAM_16bit_x256 IS + +-- hds translate_off + +-- synthesis translate_off +component wrapped_controlRAM_16bit_x256 + port ( + clka: IN std_logic; + dina: IN std_logic_VECTOR(15 downto 0); + addra: IN std_logic_VECTOR(7 downto 0); + wea: IN std_logic_VECTOR(0 downto 0); + douta: OUT std_logic_VECTOR(15 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_controlRAM_16bit_x256 use entity XilinxCoreLib.blk_mem_gen_v2_8(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 0, + c_prim_type => 1, + c_sinita_val => "0", + c_read_width_b => 16, + c_family => "spartan3", + c_read_width_a => 16, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "WRITE_FIRST", + c_init_file_name => "no_coe_file_loaded", + c_write_mode_a => "WRITE_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 0, + c_xdevicefamily => "spartan3a", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 256, + c_write_depth_a => 256, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 8, + c_addrb_width => 8, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 16, + c_write_width_a => 16, + c_read_depth_b => 256, + c_read_depth_a => 256, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 0, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 0); +-- synthesis translate_on + +-- hds translate_on + +BEGIN + +-- hds translate_off + +-- synthesis translate_off +U0 : wrapped_controlRAM_16bit_x256 + port map ( + clka => clka, + dina => dina, + addra => addra, + wea => wea, + douta => douta); +-- synthesis translate_on + + +-- hds translate_on + +END controlRAM_16bit_x256_a; + + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd (revision 9841) @@ -0,0 +1,166 @@ +-- +-- VHDL Architecture FACT_FAD_lib.controlRAM_manager.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 14:35:46 14.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; +USE ieee.std_logic_unsigned.ALL; +LIBRARY FACT_FAD_LIB; +USE FACT_FAD_LIB.fad_definitions.ALL; + +ENTITY control_manager IS + GENERIC( + NO_OF_ROI : integer := 36; + NO_OF_DAC : integer := 8; + ADDR_WIDTH : integer := 8 + ); + PORT( + clk : IN std_logic; + ram_data_out : IN std_logic_vector (15 DOWNTO 0); + config_ready, config_started : OUT std_logic := '0'; + config_start : IN std_logic; + config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + config_addr : IN std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0); + config_wr_en : IN std_logic; + config_rd_en : IN std_logic; + config_data_valid : OUT std_logic := '0'; + config_busy : OUT std_logic := '0'; + ram_addr : OUT std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0); + ram_data_in : OUT std_logic_vector (15 DOWNTO 0); + ram_write_en : OUT std_logic_vector (0 DOWNTO 0); + dac_array : OUT dac_array_type; + roi_array : OUT roi_array_type; + drs_address : OUT std_logic_vector (3 DOWNTO 0); + drs_address_mode : OUT std_logic + ); + +-- Declarations + +END control_manager ; + +ARCHITECTURE beha OF control_manager IS + + type TYPE_CTRL_STATE is (CTRL_INIT, CTRL_IDLE, CTRL_WAIT_IDLE, CTRL_WRITE, + CTRL_LOAD_ADDR, CTRL_LOAD_WAIT, CTRL_LOAD_DATA, + CTRL_READ_ADDR, CTRL_READ_WAIT, CTRL_READ_DATA); + + signal ctrl_state : TYPE_CTRL_STATE := CTRL_INIT; + signal addr_cntr : integer range 0 to 2**ADDR_WIDTH - 1 := 0; + signal int_dac_array : dac_array_type := DEFAULT_DAC; + signal int_roi_array : roi_array_type := DEFAULT_ROI; + signal int_drs_address: std_logic_vector (3 DOWNTO 0) := DEFAULT_DRSADDR; + signal int_drs_address_mode: std_logic := DEFAULT_DRSADDR_MODE; + +BEGIN + + control_fsm_proc: process (clk) + begin + + if rising_edge(clk) then + + config_busy <= '1'; -- is always busy except in idle mode + + case ctrl_state is + + when CTRL_INIT => + -- WRITES DEFAULT VALUES IN config ram + addr_cntr <= addr_cntr + 1; + ram_addr <= conv_std_logic_vector(addr_cntr, ADDR_WIDTH); + config_data_valid <= '0'; + config_ready <= '0'; + ctrl_state <= CTRL_INIT; + ram_write_en <= "1"; + if (addr_cntr < NO_OF_ROI) then + ram_data_in <= conv_std_logic_vector(int_roi_array(addr_cntr ), 16); + elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then + ram_data_in <= conv_std_logic_vector(int_dac_array(addr_cntr - NO_OF_ROI), 16); + elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then + ram_data_in <= "0000" & "0000" + & "000" & conv_std_logic_vector(int_drs_address_mode, 1) + & int_drs_address; + else + ram_write_en <= "0"; + ctrl_state <= CTRL_IDLE; + end if; + + when CTRL_IDLE => + -- + addr_cntr <= 0; + ram_write_en <= "0"; + config_busy <= '0'; + if (config_start = '1') then + config_started <= '1'; + config_ready <= '0'; + config_data_valid <= '0'; + ctrl_state <= CTRL_LOAD_ADDR; + end if; + if (config_wr_en = '1') then + config_busy <= '1'; + config_data <= (others => 'Z'); + ctrl_state <= CTRL_WRITE; + end if; + if (config_rd_en = '1') then + ram_addr <= config_addr; + config_data_valid <= '0'; +-- ctrl_state <= CTRL_READ_ADDR; + ctrl_state <= CTRL_READ_WAIT; + end if; + + when CTRL_WAIT_IDLE => + ctrl_state <= CTRL_IDLE; + + when CTRL_LOAD_ADDR => + ram_addr <= conv_std_logic_vector(addr_cntr, ADDR_WIDTH); + ctrl_state <= CTRL_LOAD_WAIT; + when CTRL_LOAD_WAIT => + ctrl_state <= CTRL_LOAD_DATA; + when CTRL_LOAD_DATA => + addr_cntr <= addr_cntr + 1; + if (addr_cntr < NO_OF_ROI) then + roi_array(addr_cntr) <= conv_integer(ram_data_out); + ctrl_state <= CTRL_LOAD_ADDR; + elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then + dac_array(addr_cntr - NO_OF_ROI) <= conv_integer(ram_data_out); + ctrl_state <= CTRL_LOAD_ADDR; + elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then + drs_address <= ram_data_out(3 downto 0); + drs_address_mode <= ram_data_out(4); + ctrl_state <= CTRL_LOAD_ADDR; + else + addr_cntr <= 0; + config_started <= '0'; + config_ready <= '1'; + ctrl_state <= CTRL_WAIT_IDLE; + end if; + + when CTRL_WRITE => + ram_data_in <= config_data; + ram_addr <= config_addr; + ram_write_en <= "1"; + ctrl_state <= CTRL_IDLE; + + -- *** IMPORTANT *** + -- read address must remain two clock cycles + when CTRL_READ_ADDR => + ctrl_state <= CTRL_READ_WAIT; + when CTRL_READ_WAIT => + ctrl_state <= CTRL_READ_DATA; + when CTRL_READ_DATA => + config_data <= ram_data_out; + config_data_valid <= '1'; + ctrl_state <= CTRL_IDLE; + + end case; + + end if; + + end process control_fsm_proc; + +END ARCHITECTURE beha; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/control_unit_struct.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/control_unit_struct.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/control_unit_struct.vhd (revision 9841) @@ -0,0 +1,148 @@ +-- VHDL Entity FACT_FAD_lib.control_unit.symbol +-- +-- Created: +-- by - dneise.UNKNOWN (TU-CC4900F8C7D2) +-- at - 14:46:37 12.07.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; +LIBRARY FACT_FAD_LIB; +USE FACT_FAD_LIB.fad_definitions.ALL; + +ENTITY control_unit IS + PORT( + clk : IN STD_LOGIC; + config_addr : IN std_logic_vector (7 DOWNTO 0); + config_rd_en : IN std_logic; + config_start : IN std_logic; + config_wr_en : IN std_logic; + config_busy : OUT std_logic; + config_data_valid : OUT std_logic; + config_ready : OUT std_logic; + config_started : OUT std_logic := '0'; + dac_array : OUT dac_array_type; + drs_address : OUT std_logic_vector (3 DOWNTO 0); + drs_address_mode : OUT std_logic; + roi_array : OUT roi_array_type; + config_data : INOUT std_logic_vector (15 DOWNTO 0) + ); + +-- Declarations + +END control_unit ; + +-- +-- VHDL Architecture FACT_FAD_lib.control_unit.struct +-- +-- Created: +-- by - dneise.UNKNOWN (TU-CC4900F8C7D2) +-- at - 14:46:37 12.07.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; +LIBRARY FACT_FAD_LIB; +USE FACT_FAD_LIB.fad_definitions.ALL; + +LIBRARY FACT_FAD_lib; + +ARCHITECTURE struct OF control_unit IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL ram_addr : std_logic_VECTOR(7 DOWNTO 0); + SIGNAL ram_data_in : std_logic_VECTOR(15 DOWNTO 0); + SIGNAL ram_data_out : std_logic_VECTOR(15 DOWNTO 0); + SIGNAL ram_wren : std_logic_VECTOR(0 DOWNTO 0); + + + -- Component Declarations + COMPONENT controlRAM_16bit_x256 + PORT ( + clka : IN std_logic ; + dina : IN std_logic_VECTOR (15 DOWNTO 0); + addra : IN std_logic_VECTOR (7 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + douta : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + END COMPONENT; + COMPONENT control_manager + GENERIC ( + NO_OF_ROI : integer := 36; + NO_OF_DAC : integer := 8; + ADDR_WIDTH : integer := 8 + ); + PORT ( + clk : IN std_logic ; + ram_data_out : IN std_logic_vector (15 DOWNTO 0); + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0'; + config_start : IN std_logic ; + config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + config_addr : IN std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0); + config_wr_en : IN std_logic ; + config_rd_en : IN std_logic ; + config_data_valid : OUT std_logic := '0'; + config_busy : OUT std_logic := '0'; + ram_addr : OUT std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0); + ram_data_in : OUT std_logic_vector (15 DOWNTO 0); + ram_write_en : OUT std_logic_vector (0 DOWNTO 0); + dac_array : OUT dac_array_type ; + roi_array : OUT roi_array_type ; + drs_address : OUT std_logic_vector (3 DOWNTO 0); + drs_address_mode : OUT std_logic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : controlRAM_16bit_x256 USE ENTITY FACT_FAD_lib.controlRAM_16bit_x256; + FOR ALL : control_manager USE ENTITY FACT_FAD_lib.control_manager; + -- pragma synthesis_on + + +BEGIN + + -- Instance port mappings. + I_control_ram : controlRAM_16bit_x256 + PORT MAP ( + clka => clk, + dina => ram_data_in, + addra => ram_addr, + wea => ram_wren, + douta => ram_data_out + ); + I_control_manager : control_manager + GENERIC MAP ( + NO_OF_ROI => 36, + NO_OF_DAC => 8, + ADDR_WIDTH => 8 + ) + PORT MAP ( + clk => clk, + ram_data_out => ram_data_out, + config_ready => config_ready, + config_started => config_started, + config_start => config_start, + config_data => config_data, + config_addr => config_addr, + config_wr_en => config_wr_en, + config_rd_en => config_rd_en, + config_data_valid => config_data_valid, + config_busy => config_busy, + ram_addr => ram_addr, + ram_data_in => ram_data_in, + ram_write_en => ram_wren, + dac_array => dac_array, + roi_array => roi_array, + drs_address => drs_address, + drs_address_mode => drs_address_mode + ); + +END struct; Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/dataRAM_64b_16b_width14_5_dataRAM_64b_16b_width14_5_a.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/dataRAM_64b_16b_width14_5_dataRAM_64b_16b_width14_5_a.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/dataRAM_64b_16b_width14_5_dataRAM_64b_16b_width14_5_a.vhd (revision 9841) @@ -0,0 +1,153 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file dataRAM_64b_16b_width14_5.vhd when simulating +-- the core, dataRAM_64b_16b_width14_5. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +-- hds interface_start +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; + +-- synthesis translate_on +-- +ENTITY dataRAM_64b_16b_width14_5 IS + PORT( + clka : IN std_logic; + dina : IN std_logic_VECTOR (63 DOWNTO 0); + addra : IN std_logic_VECTOR (14 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + clkb : IN std_logic; + addrb : IN std_logic_VECTOR (16 DOWNTO 0); + doutb : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + +-- Declarations + +END dataRAM_64b_16b_width14_5 ; +-- hds interface_end + +ARCHITECTURE dataRAM_64b_16b_width14_5_a OF dataRAM_64b_16b_width14_5 IS + +-- hds translate_off + +-- synthesis translate_off +component wrapped_dataRAM_64b_16b_width14_5 + port ( + clka: IN std_logic; + dina: IN std_logic_VECTOR(63 downto 0); + addra: IN std_logic_VECTOR(14 downto 0); + wea: IN std_logic_VECTOR(0 downto 0); + clkb: IN std_logic; + addrb: IN std_logic_VECTOR(16 downto 0); + doutb: OUT std_logic_VECTOR(15 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_dataRAM_64b_16b_width14_5 use entity XilinxCoreLib.blk_mem_gen_v2_8(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 1, + c_prim_type => 1, + c_sinita_val => "0", + c_read_width_b => 16, + c_family => "spartan3", + c_read_width_a => 64, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "READ_FIRST", + c_init_file_name => "no_coe_file_loaded", + c_write_mode_a => "READ_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 0, + c_xdevicefamily => "spartan3adsp", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 98304, + c_write_depth_a => 24576, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 15, + c_addrb_width => 17, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 16, + c_write_width_a => 64, + c_read_depth_b => 98304, + c_read_depth_a => 24576, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 0, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 0); +-- synthesis translate_on + +-- hds translate_on + +BEGIN + +-- hds translate_off + +-- synthesis translate_off +U0 : wrapped_dataRAM_64b_16b_width14_5 + port map ( + clka => clka, + dina => dina, + addra => addra, + wea => wea, + clkb => clkb, + addrb => addrb, + doutb => doutb); +-- synthesis translate_on + + +-- hds translate_on + +END dataRAM_64b_16b_width14_5_a; + + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd (revision 9841) @@ -0,0 +1,153 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file dataRAM_64b_16b_width15.vhd when simulating +-- the core, dataRAM_64b_16b_width15. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +-- hds interface_start +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; + +-- synthesis translate_on +-- +ENTITY dataRAM_64b_16b_width15 IS + PORT( + clka : IN std_logic; + dina : IN std_logic_VECTOR (63 DOWNTO 0); + addra : IN std_logic_VECTOR (14 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + clkb : IN std_logic; + addrb : IN std_logic_VECTOR (16 DOWNTO 0); + doutb : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + +-- Declarations + +END dataRAM_64b_16b_width15 ; +-- hds interface_end + +ARCHITECTURE dataRAM_64b_16b_width15_a OF dataRAM_64b_16b_width15 IS + +-- hds translate_off + +-- synthesis translate_off +component wrapped_dataRAM_64b_16b_width15 + port ( + clka: IN std_logic; + dina: IN std_logic_VECTOR(63 downto 0); + addra: IN std_logic_VECTOR(14 downto 0); + wea: IN std_logic_VECTOR(0 downto 0); + clkb: IN std_logic; + addrb: IN std_logic_VECTOR(16 downto 0); + doutb: OUT std_logic_VECTOR(15 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_dataRAM_64b_16b_width15 use entity XilinxCoreLib.blk_mem_gen_v2_8(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 1, + c_prim_type => 1, + c_sinita_val => "0", + c_read_width_b => 16, + c_family => "spartan3", + c_read_width_a => 64, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "READ_FIRST", + c_init_file_name => "no_coe_file_loaded", + c_write_mode_a => "READ_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 0, + c_xdevicefamily => "spartan3adsp", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 131072, + c_write_depth_a => 32768, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 15, + c_addrb_width => 17, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 16, + c_write_width_a => 64, + c_read_depth_b => 131072, + c_read_depth_a => 32768, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 0, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 0); +-- synthesis translate_on + +-- hds translate_on + +BEGIN + +-- hds translate_off + +-- synthesis translate_off +U0 : wrapped_dataRAM_64b_16b_width15 + port map ( + clka => clka, + dina => dina, + addra => addra, + wea => wea, + clkb => clkb, + addrb => addrb, + doutb => doutb); +-- synthesis translate_on + + +-- hds translate_on + +END dataRAM_64b_16b_width15_a; + + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/dataRM_64b_16b_width14_dataRM_64b_16b_width14_a.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/dataRM_64b_16b_width14_dataRM_64b_16b_width14_a.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/dataRM_64b_16b_width14_dataRM_64b_16b_width14_a.vhd (revision 9841) @@ -0,0 +1,153 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file dataRM_64b_16b_width14.vhd when simulating +-- the core, dataRM_64b_16b_width14. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +-- hds interface_start +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; + +-- synthesis translate_on +-- +ENTITY dataRM_64b_16b_width14 IS + PORT( + clka : IN std_logic; + dina : IN std_logic_VECTOR (63 DOWNTO 0); + addra : IN std_logic_VECTOR (13 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + clkb : IN std_logic; + addrb : IN std_logic_VECTOR (15 DOWNTO 0); + doutb : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + +-- Declarations + +END dataRM_64b_16b_width14 ; +-- hds interface_end + +ARCHITECTURE dataRM_64b_16b_width14_a OF dataRM_64b_16b_width14 IS + +-- hds translate_off + +-- synthesis translate_off +component wrapped_dataRM_64b_16b_width14 + port ( + clka: IN std_logic; + dina: IN std_logic_VECTOR(63 downto 0); + addra: IN std_logic_VECTOR(13 downto 0); + wea: IN std_logic_VECTOR(0 downto 0); + clkb: IN std_logic; + addrb: IN std_logic_VECTOR(15 downto 0); + doutb: OUT std_logic_VECTOR(15 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_dataRM_64b_16b_width14 use entity XilinxCoreLib.blk_mem_gen_v2_8(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 1, + c_prim_type => 1, + c_sinita_val => "0", + c_read_width_b => 16, + c_family => "spartan3", + c_read_width_a => 64, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "READ_FIRST", + c_init_file_name => "no_coe_file_loaded", + c_write_mode_a => "READ_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 0, + c_xdevicefamily => "spartan3adsp", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 65536, + c_write_depth_a => 16384, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 14, + c_addrb_width => 16, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 16, + c_write_width_a => 64, + c_read_depth_b => 65536, + c_read_depth_a => 16384, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 0, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 0); +-- synthesis translate_on + +-- hds translate_on + +BEGIN + +-- hds translate_off + +-- synthesis translate_off +U0 : wrapped_dataRM_64b_16b_width14 + port map ( + clka => clka, + dina => dina, + addra => addra, + wea => wea, + clkb => clkb, + addrb => addrb, + doutb => doutb); +-- synthesis translate_on + + +-- hds translate_on + +END dataRM_64b_16b_width14_a; + + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/data_generator.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/data_generator.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/data_generator.vhd (revision 9841) @@ -0,0 +1,275 @@ +-- +-- VHDL Architecture FACT_FAD_lib.data_generator.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 14:36:14 10.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + +-- -- Uncomment the following library declaration if instantiating +-- -- any Xilinx primitives in this code. +-- library UNISIM; +-- use UNISIM.VComponents.all; + +entity data_generator is + generic( + RAM_ADDR_WIDTH : integer := 12 + ); + port( + clk : in std_logic; + data_out : out std_logic_vector (63 downto 0); + addr_out : out std_logic_vector (RAM_ADDR_WIDTH-1 downto 0); + write_ea : out std_logic_vector (0 downto 0) := "0"; + ram_start_addr : in std_logic_vector (RAM_ADDR_WIDTH-1 downto 0); + ram_write_ea : in std_logic; + ram_write_ready : out std_logic := '0'; + config_start_mm, config_start_cm, config_start_spi : out std_logic := '0'; + config_ready_mm, config_ready_cm, config_ready_spi : in std_logic; + config_started_mm, config_started_cm, config_started_spi : in std_logic; + roi_array : in roi_array_type; + roi_max : in roi_max_type; + sensor_array : in sensor_array_type; + sensor_ready : in std_logic; + dac_array : in dac_array_type; + package_length : in std_logic_vector (15 downto 0); + board_id : in std_logic_vector (3 downto 0); + crate_id : in std_logic_vector (1 downto 0); + trigger_id : in std_logic_vector (47 downto 0); + trigger : in std_logic; + s_trigger : in std_logic; + new_config : in std_logic; + config_started : out std_logic := '0'; + adc_data_array : in adc_data_array_type; + adc_oeb : out std_logic := '1'; + adc_otr : in std_logic_vector (3 downto 0); + drs_channel_id : out std_logic_vector (3 downto 0) := (others => '0'); + drs_dwrite : out std_logic := '1'; + drs_clk_en, drs_read_s_cell : out std_logic := '0'; + drs_read_s_cell_ready : in std_logic; + drs_s_cell_array : in drs_s_cell_array_type + ); +end data_generator ; + +architecture Behavioral of data_generator is + +type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES, + WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT, + WRITE_END_FLAG, WRITE_DATA_STOP, + WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING); + +signal state_generate : state_generate_type := INIT; +signal start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); + +signal data_cntr : integer range 0 to 1024 := 0; +signal evnt_cntr : std_logic_vector (31 downto 0) := (others => '0'); +signal addr_cntr : integer range 0 to RAM_SIZE_64B := 0; -- counts 64 bit words +signal channel_id : integer range 0 to 9 := 0; +signal adc_wait_cnt : integer range 0 to 7 := 0; + + +begin + + + generate_data : process (clk) + begin + if rising_edge (clk) then + + addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH); + + case state_generate is + when INIT => + state_generate <= CONFIG; + + when CONFIG => + config_started <= '1'; + -- config config manager + config_start_cm <= '1'; + if (config_started_cm = '1') then + state_generate <= CONFIG1; + end if; + when CONFIG1 => + if (config_ready_cm = '1') then + config_started <= '0'; + config_start_cm <= '0'; + config_start_mm <= '1'; + end if; + if (config_started_mm = '1') then + state_generate <= CONFIG2; + end if; + when CONFIG2 => + if (config_ready_mm = '1') then + config_start_mm <= '0'; + config_start_spi <= '1'; + end if; + if (config_started_spi = '1') then + state_generate <= CONFIG3; + end if; + when CONFIG3 => + if (config_ready_spi = '1') then + config_start_spi <= '0'; + state_generate <= WRITE_DATA_IDLE; + end if; + + when WRITE_DATA_IDLE => + if (new_config = '1') then + state_generate <= CONFIG; + end if; + if (ram_write_ea = '1' and (trigger = '1' or s_trigger = '1')) then + -- stop drs, dwrite low + drs_dwrite <= '0'; + -- start reading of drs stop cell + drs_read_s_cell <= '1'; + -- enable adc output + adc_oeb <= '0'; + start_addr <= ram_start_addr; + state_generate <= WRITE_HEADER; + evnt_cntr <= evnt_cntr + 1; + end if; + when WRITE_HEADER => + write_ea <= "1"; + data_out <= X"0000" & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01"; + addr_cntr <= addr_cntr + 3; + state_generate <= WRITE_BOARD_ID; + when WRITE_BOARD_ID => -- crate ID & board ID + data_out <= (63 downto 10 => '0') & crate_id & "1000" & board_id; + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_TEMPERATURES; + when WRITE_TEMPERATURES => -- temperatures + if (sensor_ready = '1') then + data_out <= conv_std_logic_vector (sensor_array (3), 16) + & conv_std_logic_vector (sensor_array (2), 16) + & conv_std_logic_vector (sensor_array (1), 16) + & conv_std_logic_vector (sensor_array (0), 16); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_DAC1; + end if; + + when WRITE_DAC1 => + data_out <= conv_std_logic_vector (dac_array (3), 16) + & conv_std_logic_vector (dac_array (2), 16) + & conv_std_logic_vector (dac_array (1), 16) + & conv_std_logic_vector (dac_array (0), 16); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_DAC2; + when WRITE_DAC2 => + data_out <= conv_std_logic_vector (dac_array (7), 16) + & conv_std_logic_vector (dac_array (6), 16) + & conv_std_logic_vector (dac_array (5), 16) + & conv_std_logic_vector (dac_array (4), 16); + addr_cntr <= addr_cntr + 1; + state_generate <= WAIT_FOR_STOP_CELL; + + when WAIT_FOR_STOP_CELL => + drs_read_s_cell <= '0'; + if (drs_read_s_cell_ready = '1') then + state_generate <= START_DRS_READING; + end if; + + when START_DRS_READING => + --drs channel number + drs_channel_id <= conv_std_logic_vector (channel_id, 4); + --starte drs-clocking + --adc_oeb <= '0'; -- nur für Emulator + drs_clk_en <= '1'; + adc_wait_cnt <= 0; + state_generate <= WRITE_CHANNEL_ID; + + when WRITE_CHANNEL_ID => -- write DRS and Channel IDs + data_out <= conv_std_logic_vector(0,10) & conv_std_logic_vector(3,2) & conv_std_logic_vector(channel_id,4) + & conv_std_logic_vector(0,10) & conv_std_logic_vector(2,2) & conv_std_logic_vector(channel_id,4) + & conv_std_logic_vector(0,10) & conv_std_logic_vector(1,2) & conv_std_logic_vector(channel_id,4) + & conv_std_logic_vector(0,10) & conv_std_logic_vector(0,2) & conv_std_logic_vector(channel_id,4); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_START_CELL; + when WRITE_START_CELL => -- write start cells + data_out <= "000000" & drs_s_cell_array (3) + & "000000" & drs_s_cell_array (2) + & "000000" & drs_s_cell_array (1) + & "000000" & drs_s_cell_array (0); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_ROI; + when WRITE_ROI => -- write ROI + data_out <= "00000" & conv_std_logic_vector (roi_array((3) * 9 + channel_id), 11) + & "00000" & conv_std_logic_vector (roi_array((2) * 9 + channel_id), 11) + & "00000" & conv_std_logic_vector (roi_array((1) * 9 + channel_id), 11) + & "00000" & conv_std_logic_vector (roi_array((0) * 9 + channel_id), 11); + addr_cntr <= addr_cntr + 1; + state_generate <= WAIT_FOR_ADC; + when WAIT_FOR_ADC => + -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + if (adc_wait_cnt < (4 + 3)) then -- anpassen!!!! -- 3 für Simulation, 4 für FPGA??? + adc_wait_cnt <= adc_wait_cnt + 1; + else + state_generate <= WRITE_ADC_DATA; + end if; + when WRITE_ADC_DATA => + if (data_cntr < roi_max (channel_id)) then + data_out <= "000" & adc_otr(3) & adc_data_array(3) + & "000" & adc_otr(2) & adc_data_array(2) + & "000" & adc_otr(1) & adc_data_array(1) + & "000" & adc_otr(0) & adc_data_array(0); +-- data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) +-- & "00010" & conv_std_logic_vector (data_cntr, 11) +-- & "00100" & conv_std_logic_vector (data_cntr, 11) +-- & "00110" & conv_std_logic_vector (data_cntr, 11) ; + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_ADC_DATA; + data_cntr <= data_cntr + 1; + else + drs_clk_en <= '0'; + --adc_oeb <= '1'; -- nur für Emulator + if (channel_id = 8) then + state_generate <= WRITE_EXTERNAL_TRIGGER; + adc_oeb <= '1'; + else + channel_id <= channel_id + 1; -- increment channel_id + state_generate <= START_DRS_READING; + data_cntr <= 0; + end if; + end if; + + + when WRITE_EXTERNAL_TRIGGER => -- external trigger ID + addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH); + data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16); + state_generate <= WRITE_INTERNAL_TRIGGER; + when WRITE_INTERNAL_TRIGGER => -- internal trigger ID + addr_out <= start_addr + conv_std_logic_vector(2, RAM_ADDR_WIDTH); + data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16); + state_generate <= WRITE_END_FLAG; + when WRITE_END_FLAG => + data_out <= (63 downto 32 => '0') & X"04FE" & X"4242"; + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_DATA_END; + when WRITE_DATA_END => + write_ea <= "0"; + ram_write_ready <= '1'; + state_generate <= WRITE_DATA_END_WAIT; + when WRITE_DATA_END_WAIT => + state_generate <= WRITE_DATA_STOP; + when WRITE_DATA_STOP => + drs_dwrite <= '1'; + data_cntr <= 0; + addr_cntr <= 0; + channel_id <= 0; + ram_write_ready <= '0'; + state_generate <= WRITE_DATA_IDLE; + + when others => + null; + + end case; -- state_generate + end if; -- rising_edge (clk) + end process generate_data; + +end Behavioral; + + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/data_generator.vhd.bak =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/data_generator.vhd.bak (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/data_generator.vhd.bak (revision 9841) @@ -0,0 +1,275 @@ +-- +-- VHDL Architecture FACT_FAD_lib.data_generator.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 14:36:14 10.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + +-- -- Uncomment the following library declaration if instantiating +-- -- any Xilinx primitives in this code. +-- library UNISIM; +-- use UNISIM.VComponents.all; + +entity data_generator is + generic( + RAM_ADDR_WIDTH : integer := 12 + ); + port( + clk : in std_logic; + data_out : out std_logic_vector (63 downto 0); + addr_out : out std_logic_vector (RAM_ADDR_WIDTH-1 downto 0); + write_ea : out std_logic_vector (0 downto 0) := "0"; + ram_start_addr : in std_logic_vector (RAM_ADDR_WIDTH-1 downto 0); + ram_write_ea : in std_logic; + ram_write_ready : out std_logic := '0'; + config_start_mm, config_start_cm, config_start_spi : out std_logic := '0'; + config_ready_mm, config_ready_cm, config_ready_spi : in std_logic; + config_started_mm, config_started_cm, config_started_spi : in std_logic; + roi_array : in roi_array_type; + roi_max : in roi_max_type; + sensor_array : in sensor_array_type; + sensor_ready : in std_logic; + dac_array : in dac_array_type; + package_length : in std_logic_vector (15 downto 0); + board_id : in std_logic_vector (3 downto 0); + crate_id : in std_logic_vector (1 downto 0); + trigger_id : in std_logic_vector (47 downto 0); + trigger : in std_logic; + s_trigger : in std_logic; + new_config : in std_logic; + config_started : out std_logic := '0'; + adc_data_array : in adc_data_array_type; + adc_oeb : out std_logic := '1'; + adc_otr : in std_logic_vector (3 downto 0); + drs_channel_id : out std_logic_vector (3 downto 0) := (others => '0'); + drs_dwrite : out std_logic := '1'; + drs_clk_en, drs_read_s_cell : out std_logic := '0'; + drs_read_s_cell_ready : in std_logic; + drs_s_cell_array : in drs_s_cell_array_type + ); +end data_generator ; + +architecture Behavioral of data_generator is + +type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES, + WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT, + WRITE_END_FLAG, WRITE_DATA_STOP, + WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING); + +signal state_generate : state_generate_type := INIT; +signal start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); + +signal data_cntr : integer range 0 to 1024 := 0; +signal evnt_cntr : std_logic_vector (31 downto 0) := (others => '0'); +signal addr_cntr : integer range 0 to RAM_SIZE_64B := 0; -- counts 64 bit words +signal channel_id : integer range 0 to 9 := 0; +signal adc_wait_cnt : integer range 0 to 7 := 0; + + +begin + + + generate_data : process (clk) + begin + if rising_edge (clk) then + + addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH); + + case state_generate is + when INIT => + state_generate <= CONFIG; + + when CONFIG => + config_started <= '1'; + -- config config manager + config_start_cm <= '1'; + if (config_started_cm = '1') then + state_generate <= CONFIG1; + end if; + when CONFIG1 => + if (config_ready_cm = '1') then + config_started <= '0'; + config_start_cm <= '0'; + config_start_mm <= '1'; + end if; + if (config_started_mm = '1') then + state_generate <= CONFIG2; + end if; + when CONFIG2 => + if (config_ready_mm = '1') then + config_start_mm <= '0'; + config_start_spi <= '1'; + end if; + if (config_started_spi = '1') then + state_generate <= CONFIG3; + end if; + when CONFIG3 => + if (config_ready_spi = '1') then + config_start_spi <= '0'; + state_generate <= WRITE_DATA_IDLE; + end if; + + when WRITE_DATA_IDLE => + if (new_config = '1') then + state_generate <= CONFIG; + end if; + if (ram_write_ea = '1' and (trigger = '1' or s_trigger = '1')) then + -- stop drs, dwrite low + drs_dwrite <= '0'; + -- start reading of drs stop cell + drs_read_s_cell <= '1'; + -- enable adc output + adc_oeb <= '0'; + start_addr <= ram_start_addr; + state_generate <= WRITE_HEADER; + evnt_cntr <= evnt_cntr + 1; + end if; + when WRITE_HEADER => + write_ea <= "1"; + data_out <= X"0000" & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01"; + addr_cntr <= addr_cntr + 3; + state_generate <= WRITE_BOARD_ID; + when WRITE_BOARD_ID => -- crate ID & board ID + data_out <= (63 downto 10 => '0') & crate_id & "1000" & board_id; + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_TEMPERATURES; + when WRITE_TEMPERATURES => -- temperatures + if (sensor_ready = '1') then + data_out <= conv_std_logic_vector (sensor_array (3), 16) + & conv_std_logic_vector (sensor_array (2), 16) + & conv_std_logic_vector (sensor_array (1), 16) + & conv_std_logic_vector (sensor_array (0), 16); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_DAC1; + end if; + + when WRITE_DAC1 => + data_out <= conv_std_logic_vector (dac_array (3), 16) + & conv_std_logic_vector (dac_array (2), 16) + & conv_std_logic_vector (dac_array (1), 16) + & conv_std_logic_vector (dac_array (0), 16); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_DAC2; + when WRITE_DAC2 => + data_out <= conv_std_logic_vector (dac_array (7), 16) + & conv_std_logic_vector (dac_array (6), 16) + & conv_std_logic_vector (dac_array (5), 16) + & conv_std_logic_vector (dac_array (4), 16); + addr_cntr <= addr_cntr + 1; + state_generate <= WAIT_FOR_STOP_CELL; + + when WAIT_FOR_STOP_CELL => + drs_read_s_cell <= '0'; + if (drs_read_s_cell_ready = '1') then + state_generate <= START_DRS_READING; + end if; + + when START_DRS_READING => + --drs channel number + drs_channel_id <= conv_std_logic_vector (channel_id, 4); + --starte drs-clocking + --adc_oeb <= '0'; -- nur für Emulator + drs_clk_en <= '1'; + adc_wait_cnt <= 0; + state_generate <= WRITE_CHANNEL_ID; + + when WRITE_CHANNEL_ID => -- write DRS and Channel IDs + data_out <= conv_std_logic_vector(0,10) & conv_std_logic_vector(3,2) & conv_std_logic_vector(channel_id,4) + & conv_std_logic_vector(0,10) & conv_std_logic_vector(2,2) & conv_std_logic_vector(channel_id,4) + & conv_std_logic_vector(0,10) & conv_std_logic_vector(1,2) & conv_std_logic_vector(channel_id,4) + & conv_std_logic_vector(0,10) & conv_std_logic_vector(0,2) & conv_std_logic_vector(channel_id,4); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_START_CELL; + when WRITE_START_CELL => -- write start cells + data_out <= "000000" & drs_s_cell_array (3) + & "000000" & drs_s_cell_array (2) + & "000000" & drs_s_cell_array (1) + & "000000" & drs_s_cell_array (0); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_ROI; + when WRITE_ROI => -- write ROI + data_out <= "00000" & conv_std_logic_vector (roi_array((3) * 9 + channel_id), 11) + & "00000" & conv_std_logic_vector (roi_array((2) * 9 + channel_id), 11) + & "00000" & conv_std_logic_vector (roi_array((1) * 9 + channel_id), 11) + & "00000" & conv_std_logic_vector (roi_array((0) * 9 + channel_id), 11); + addr_cntr <= addr_cntr + 1; + state_generate <= WAIT_FOR_ADC; + when WAIT_FOR_ADC => + -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + if (adc_wait_cnt < (4 + 3)) then -- anpassen!!!! -- 3 für Simulation, 4 für FPGA??? + adc_wait_cnt <= adc_wait_cnt + 1; + else + state_generate <= WRITE_ADC_DATA; + end if; + when WRITE_ADC_DATA => + if (data_cntr < roi_max (channel_id)) then +-- data_out <= "000" & adc_otr(3) & adc_data_array(3) +-- & "000" & adc_otr(2) & adc_data_array(2) +-- & "000" & adc_otr(1) & adc_data_array(1) +-- & "000" & adc_otr(0) & adc_data_array(0); + data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) + & "00010" & conv_std_logic_vector (data_cntr, 11) + & "00100" & conv_std_logic_vector (data_cntr, 11) + & "00110" & conv_std_logic_vector (data_cntr, 11) ; + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_ADC_DATA; + data_cntr <= data_cntr + 1; + else + drs_clk_en <= '0'; + --adc_oeb <= '1'; -- nur für Emulator + if (channel_id = 8) then + state_generate <= WRITE_EXTERNAL_TRIGGER; + adc_oeb <= '1'; + else + channel_id <= channel_id + 1; -- increment channel_id + state_generate <= START_DRS_READING; + data_cntr <= 0; + end if; + end if; + + + when WRITE_EXTERNAL_TRIGGER => -- external trigger ID + addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH); + data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16); + state_generate <= WRITE_INTERNAL_TRIGGER; + when WRITE_INTERNAL_TRIGGER => -- internal trigger ID + addr_out <= start_addr + conv_std_logic_vector(2, RAM_ADDR_WIDTH); + data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16); + state_generate <= WRITE_END_FLAG; + when WRITE_END_FLAG => + data_out <= (63 downto 32 => '0') & X"04FE" & X"4242"; + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_DATA_END; + when WRITE_DATA_END => + write_ea <= "0"; + ram_write_ready <= '1'; + state_generate <= WRITE_DATA_END_WAIT; + when WRITE_DATA_END_WAIT => + state_generate <= WRITE_DATA_STOP; + when WRITE_DATA_STOP => + drs_dwrite <= '1'; + data_cntr <= 0; + addr_cntr <= 0; + channel_id <= 0; + ram_write_ready <= '0'; + state_generate <= WRITE_DATA_IDLE; + + when others => + null; + + end case; -- state_generate + end if; -- rising_edge (clk) + end process generate_data; + +end Behavioral; + + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/dcm_50_to_25_BEHAVIORAL.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/dcm_50_to_25_BEHAVIORAL.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/dcm_50_to_25_BEHAVIORAL.vhd (revision 9841) @@ -0,0 +1,189 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 10.1.03 +-- \ \ Application : xaw2vhdl +-- / / Filename : dcm_50_to_25.vhd +-- /___/ /\ Timestamp : 04/19/2010 15:54:44 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st C:/DOKUME~1/kai/LOKALE~1/Temp/coregen_kai/coregen/project/dcm_50_to_25.xaw C:/DOKUME~1/kai/LOKALE~1/Temp/coregen_kai/coregen/project/dcm_50_to_25 +--Design Name: dcm_50_to_25 +--Device: xc3s50a-5tq144 +-- +-- Module dcm_50_to_25 +-- Written for synthesis tool: Precision + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity dcm_50_to_25 is + port ( CLKIN_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic); +end dcm_50_to_25; + +architecture BEHAVIORAL of dcm_50_to_25 is + +-- hds translate_off + + attribute CLK_FEEDBACK : string ; + attribute CLKDV_DIVIDE : string ; + attribute CLKFX_DIVIDE : string ; + attribute CLKFX_MULTIPLY : string ; + attribute CLKIN_DIVIDE_BY_2 : string ; + attribute CLKIN_PERIOD : string ; + attribute CLKOUT_PHASE_SHIFT : string ; + attribute DESKEW_ADJUST : string ; + attribute DFS_FREQUENCY_MODE : string ; + attribute DLL_FREQUENCY_MODE : string ; + attribute DUTY_CYCLE_CORRECTION : string ; + attribute FACTORY_JF : string ; + attribute PHASE_SHIFT : string ; + attribute STARTUP_WAIT : string ; + signal CLKFB_IN : std_logic; + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; + component BUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + component IBUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + -- Period Jitter (unit interval) for block DCM_SP_INST = 0.02 UI + -- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.18 ns + component DCM_SP + -- pragma synthesis_off + generic( CLK_FEEDBACK : string := "1X"; + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := FALSE; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DUTY_CYCLE_CORRECTION : boolean := TRUE; + FACTORY_JF : bit_vector := x"C080"; + PHASE_SHIFT : integer := 0; + STARTUP_WAIT : boolean := FALSE; + DSS_MODE : string := "NONE"); + -- pragma synthesis_on + port ( CLKIN : in std_logic; + CLKFB : in std_logic; + RST : in std_logic; + PSEN : in std_logic; + PSINCDEC : in std_logic; + PSCLK : in std_logic; + DSSEN : in std_logic; + CLK0 : out std_logic; + CLK90 : out std_logic; + CLK180 : out std_logic; + CLK270 : out std_logic; + CLKDV : out std_logic; + CLK2X : out std_logic; + CLK2X180 : out std_logic; + CLKFX : out std_logic; + CLKFX180 : out std_logic; + STATUS : out std_logic_vector (7 downto 0); + LOCKED : out std_logic; + PSDONE : out std_logic); + end component; + + attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X"; + attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0"; + attribute CLKFX_DIVIDE of DCM_SP_INST : label is "5"; + attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "2"; + attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE"; + attribute CLKIN_PERIOD of DCM_SP_INST : label is "20.000"; + attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "NONE"; + attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS"; + attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; + attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; + attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE"; + attribute FACTORY_JF of DCM_SP_INST : label is "C080"; + attribute PHASE_SHIFT of DCM_SP_INST : label is "0"; + attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE"; + +-- hds translate_on + +begin + +-- hds translate_off + + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLK0_OUT <= CLKFB_IN; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + -- pragma synthesis_off + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 5, + CLKFX_MULTIPLY => 2, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + -- pragma synthesis_on + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>GND_BIT, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>open, + PSDONE=>open, + STATUS=>open); + + +-- hds translate_on + +end BEHAVIORAL; + + + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/dcm_ps_38ns_BEHAVIORAL.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/dcm_ps_38ns_BEHAVIORAL.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/dcm_ps_38ns_BEHAVIORAL.vhd (revision 9841) @@ -0,0 +1,169 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 10.1.03 +-- \ \ Application : xaw2vhdl +-- / / Filename : dcm_ps_38ns.vhd +-- /___/ /\ Timestamp : 04/19/2010 15:55:48 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st C:/DOKUME~1/kai/LOKALE~1/Temp/coregen_kai/coregen/project/dcm_ps_38ns.xaw C:/DOKUME~1/kai/LOKALE~1/Temp/coregen_kai/coregen/project/dcm_ps_38ns +--Design Name: dcm_ps_38ns +--Device: xc3s50a-5tq144 +-- +-- Module dcm_ps_38ns +-- Written for synthesis tool: Precision + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity dcm_ps_38ns is + port ( CLKIN_IN : in std_logic; + CLK0_OUT : out std_logic); +end dcm_ps_38ns; + +architecture BEHAVIORAL of dcm_ps_38ns is + +-- hds translate_off + + attribute CLK_FEEDBACK : string ; + attribute CLKDV_DIVIDE : string ; + attribute CLKFX_DIVIDE : string ; + attribute CLKFX_MULTIPLY : string ; + attribute CLKIN_DIVIDE_BY_2 : string ; + attribute CLKIN_PERIOD : string ; + attribute CLKOUT_PHASE_SHIFT : string ; + attribute DESKEW_ADJUST : string ; + attribute DFS_FREQUENCY_MODE : string ; + attribute DLL_FREQUENCY_MODE : string ; + attribute DUTY_CYCLE_CORRECTION : string ; + attribute FACTORY_JF : string ; + attribute PHASE_SHIFT : string ; + attribute STARTUP_WAIT : string ; + signal CLKFB_IN : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; + component BUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + component DCM_SP + -- pragma synthesis_off + generic( CLK_FEEDBACK : string := "1X"; + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := FALSE; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DUTY_CYCLE_CORRECTION : boolean := TRUE; + FACTORY_JF : bit_vector := x"C080"; + PHASE_SHIFT : integer := 0; + STARTUP_WAIT : boolean := FALSE; + DSS_MODE : string := "NONE"); + -- pragma synthesis_on + port ( CLKIN : in std_logic; + CLKFB : in std_logic; + RST : in std_logic; + PSEN : in std_logic; + PSINCDEC : in std_logic; + PSCLK : in std_logic; + DSSEN : in std_logic; + CLK0 : out std_logic; + CLK90 : out std_logic; + CLK180 : out std_logic; + CLK270 : out std_logic; + CLKDV : out std_logic; + CLK2X : out std_logic; + CLK2X180 : out std_logic; + CLKFX : out std_logic; + CLKFX180 : out std_logic; + STATUS : out std_logic_vector (7 downto 0); + LOCKED : out std_logic; + PSDONE : out std_logic); + end component; + + attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X"; + attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0"; + attribute CLKFX_DIVIDE of DCM_SP_INST : label is "1"; + attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "4"; + attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE"; + attribute CLKIN_PERIOD of DCM_SP_INST : label is "50.000"; + attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "FIXED"; + attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS"; + attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; + attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; + attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE"; + attribute FACTORY_JF of DCM_SP_INST : label is "C080"; + attribute PHASE_SHIFT of DCM_SP_INST : label is "195"; + attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE"; + +-- hds translate_on + +begin + +-- hds translate_off + + GND_BIT <= '0'; + CLK0_OUT <= CLKFB_IN; + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + -- pragma synthesis_off + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 4, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 50.000, + CLKOUT_PHASE_SHIFT => "FIXED", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 195, + STARTUP_WAIT => FALSE) + -- pragma synthesis_on + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IN, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>GND_BIT, + CLKDV=>open, + CLKFX=>open, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>open, + PSDONE=>open, + STATUS=>open); + + +-- hds translate_on + +end BEHAVIORAL; + + + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/debouncer.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/debouncer.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/debouncer.vhd (revision 9841) @@ -0,0 +1,106 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:42:35 01/08/2010 +-- Design Name: +-- Module Name: debouncer - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +-- hds interface_start +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +-- -- Uncomment the following library declaration if instantiating +-- -- any Xilinx primitives in this code. +-- library UNISIM; +-- use UNISIM.VComponents.all; +-- +ENTITY debouncer IS + GENERIC( + WIDTH : INTEGER := 17 + ); + PORT( + clk : IN STD_LOGIC; + -- rst : in STD_LOGIC; + trigger_in : IN STD_LOGIC; + trigger_out : OUT STD_LOGIC := '0' + ); + +-- Declarations + +END debouncer ; +-- hds interface_end + +architecture Behavioral of debouncer is + + signal counter : STD_LOGIC_VECTOR(WIDTH-1 downto 0) := (others => '0'); + signal int_trigger : std_logic := '0'; + signal temp_trig : std_logic_vector(1 downto 0) := "00"; + signal trigger_flag : std_logic := '0'; + signal temp_signal : std_logic := '0'; + +begin + + debounce_proc: process (clk) + begin +-- if (rst = '1') then +-- counter <= (others => '0'); +-- trigger_out <= '0'; +-- elsif rising_edge(clk) then + if rising_edge(clk) then + if (trigger_in = '1') then + if (unsigned(counter) = 2**WIDTH-1) then + int_trigger <= '1'; + counter <= (others => '1'); + else + counter <= std_logic_vector(unsigned(counter) + to_unsigned(1,WIDTH)); + end if; + else + if (unsigned(counter) = 0) then + int_trigger <= '0'; + counter <= (others => '0'); + else + counter <= std_logic_vector(unsigned(counter) - to_unsigned(1,WIDTH)); + end if; + end if; + end if; + end process debounce_proc; + + shaping_proc : process (clk) + begin +-- if (rst = '1') then +-- trigger_out <= '0'; +-- trigger_flag <= '0'; +-- temp_signal <= '0'; +-- elsif rising_edge(clk) then + if rising_edge(clk) then +-- temp_trig <= temp_trig(2 downto 0) & trigger_in; +-- trigger_out <= not temp_trig(3) and temp_trig(2); + temp_trig <= temp_trig(0) & int_trigger; + temp_signal <= not temp_trig(1) and temp_trig(0); + trigger_out <= temp_signal and not trigger_flag; + if (int_trigger = '0') then + trigger_flag <= '0'; + end if; + if (temp_signal = '1') then + trigger_flag <= '1'; + end if; + end if; + end process shaping_proc; + + +end Behavioral; + + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/drs_pulser.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/drs_pulser.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/drs_pulser.vhd (revision 9841) @@ -0,0 +1,251 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.std_logic_signed.all; + +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + + +ENTITY drs_pulser is + port ( + -- input CLK; RSRLOAD and SRCLK are derived from this signal + CLK : in std_logic; + -- async reset; + reset : in std_logic; + + start_endless_mode : in std_logic; + start_read_stop_pos_mode : in std_logic; + + SROUT_in_0 : in std_logic; + SROUT_in_1 : in std_logic; + SROUT_in_2 : in std_logic; + SROUT_in_3 : in std_logic; + +-- stop_pos_0 : out std_logic_vector(9 downto 0); +-- stop_pos_1 : out std_logic_vector(9 downto 0); +-- stop_pos_2 : out std_logic_vector(9 downto 0); +-- stop_pos_3 : out std_logic_vector(9 downto 0); + stop_pos : out drs_s_cell_array_type; + stop_pos_valid : out std_logic; + + RSRLOAD : out std_logic; + SRCLK : out std_logic; + busy :out std_logic + ); +end drs_pulser; + + +ARCHITECTURE behavior of drs_pulser IS + +type states is (idle, started_endless, started_read_stop_pos , waiting_e, waiting_r, running_e, running_r); +signal current_state : states := idle; +signal next_state : states := idle; +signal CEN,LEN : std_logic; + + +signal local_roi : std_logic_vector (9 downto 0):= (others => '0'); + +signal flag_read_stop_pos : std_logic := '0'; + +signal cell_cntr : std_logic_vector (9 downto 0); +signal cc_en : std_logic; +signal cc_reset : std_logic; + +signal wait_cntr : std_logic_vector (2 downto 0); +signal wc_en : std_logic; +signal wc_reset : std_logic; + +signal int_stop_pos_0 : std_logic_vector(9 downto 0) := (others => '0'); +signal int_stop_pos_1 : std_logic_vector(9 downto 0) := (others => '0'); +signal int_stop_pos_2 : std_logic_vector(9 downto 0) := (others => '0'); +signal int_stop_pos_3 : std_logic_vector(9 downto 0) := (others => '0'); + +begin + RSRLOAD <= (LEN and CLK); + SRCLK <= (CEN and CLK); + stop_pos(0) <= int_stop_pos_0; + stop_pos(1) <= int_stop_pos_1; + stop_pos(2) <= int_stop_pos_2; + stop_pos(3) <= int_stop_pos_3; + + + + state_register: process(clk, reset) + begin + IF reset = '1' THEN + current_state <= idle ; + ELSIF clk = '0' and clk'event THEN -- ! falling edge ! + current_state <= next_state ; + END IF; + end process state_register; + + --Folgezustandsberechnung asynchron + transition: process(current_state, + start_endless_mode, + start_read_stop_pos_mode, + wait_cntr, + cell_cntr, + local_roi) + begin + CASE current_state IS + WHEN idle => + if start_endless_mode = '1' then + next_state <= started_endless ; + elsif start_read_stop_pos_mode = '1' then + next_state <= started_read_stop_pos ; + end if; + + WHEN started_endless => + if cell_cntr = conv_std_logic_vector(1,10) then + next_state <= waiting_e; + end if; + + + + WHEN started_read_stop_pos => + if cell_cntr = conv_std_logic_vector(1,10) then + next_state <= waiting_r; + end if; + + WHEN waiting_e => + if wait_cntr = conv_std_logic_vector(0,3) then + next_state <= running_e; + else + next_state <= waiting_e; + end if; + + WHEN waiting_r => + if wait_cntr = conv_std_logic_vector(0,3) then + next_state <= running_r; + end if; + + + WHEN running_e => + IF (start_endless_mode = '0') THEN + next_state <= idle; + END IF; + + WHEN running_r => + if cell_cntr >= local_roi THEN + next_state <= idle; + end if; + END CASE; + end process transition; + + output_proc: process(current_state) --Ausgangsberechnung synchron, da current_state sich nur synchron aendert + begin + case current_state is + + when idle => + local_roi <= (others => '0'); + flag_read_stop_pos <= '0'; + stop_pos_valid <= '1'; + LEN <= '0'; CEN <= '0'; + busy <= '0'; + cc_en <= '0'; cc_reset <= '1'; + wc_en <= '0'; wc_reset <= '0'; + + when started_endless => + local_roi <= "0111111111"; + flag_read_stop_pos <= '0'; + stop_pos_valid <= '0'; + LEN <= '1'; CEN <= '0'; + busy <= '1'; + cc_en <= '1'; cc_reset <= '0'; + wc_en <= '0'; wc_reset <= '1'; + + when started_read_stop_pos => + local_roi <= conv_std_logic_vector(11,10); + flag_read_stop_pos <= '1'; + stop_pos_valid <= '0'; + LEN <= '1'; CEN <= '0'; + busy <= '1'; + cc_en <= '1'; cc_reset <= '0'; + wc_en <= '0'; wc_reset <= '1'; + + when waiting_e | waiting_r => + local_roi <= local_roi; + stop_pos_valid <= '0'; + busy <= '1'; + LEN <= '0'; CEN <= '0'; + cc_en <= '0'; cc_reset <= '0'; + wc_en <= '1'; wc_reset <= '0'; + + when running_e => + flag_read_stop_pos <= '0'; + stop_pos_valid <= '0'; + LEN <= '0'; CEN <= '1'; + cc_en <= '1'; cc_reset <= '0'; + wc_en <= '0'; wc_reset <= '0'; + busy <= '1'; + + when running_r => + flag_read_stop_pos <= '1'; + stop_pos_valid <= '0'; + LEN <= '0'; CEN <= '1'; + cc_en <= '1'; cc_reset <= '0'; + wc_en <= '0'; wc_reset <= '0'; + busy <= '1'; + end case; + end process output_proc; + + + cellcounter: process (clk, cc_reset) begin + + if (cc_reset = '1') then + cell_cntr <= (others=>'0'); + elsif (rising_edge(clk)) then + if (cc_en = '1') then + cell_cntr <= cell_cntr + 1; + end if; + end if; + + end process cellcounter; + + + waitcounter: process (clk, wc_reset) begin + if (wc_reset = '1') then + wait_cntr <= "011"; -- RSRLOAD -> warte 3 -> SRCLK + elsif (rising_edge(clk)) then + if (wc_en = '1') then + wait_cntr <= wait_cntr - 1; + end if; + end if; + end process waitcounter; + + -- laut DRS4_rev09.pdf Seite 13 Figure 15 + -- funktioniert das auslesen der Stop bzw. Startadresse so: + -- Sende 1x RSRLOAD- und mind. 9 SRCLK- pulse und sample SROUT zur + -- steigenden Flanke von SRCLK. + -- MSB first LSB last, kommen dann die 10 bits, + -- die die Stopposition darstellen. + -- + -- diese Architecture liefert immer dann eine steigende Flanke + -- auf RSRCLK, wenn CLK eine steigende Flanke hat und CEN='1' ist. + -- Die an SROUT zur steigenden Flanke anliegenden Werte werden wie in einem Schieberegister + -- Schritt fuer Schritt in die stop_pos_x vectoren geschoben. + -- + -- wenn sie 10 schritte weit reingschoben wurden, ist der process fertig. + -- es gibt keinen eigenen counter fuer die 10 schritte, der cell counter kann hier + -- missbraucht werden. + -- + -- da der process eine steigende flanke auf SRCLK braucht um SROUT zu sampeln + -- wird im Prinzip ein Puls aud SRCLK *zuviel* erzeugt, das ist aber egal... + -- + stop_pos_reader: process (CEN, clk, flag_read_stop_pos) + begin + IF (flag_read_stop_pos = '1') THEN -- nur wenn ich im read_stop_mode bin, laeuft dieser process + IF (CEN = '1') THEN -- nur wenn CEN='1' ist kommen SRCLK pulse raus. + IF (rising_edge(CLK)) THEN -- wenn steigende Flanke, dann SROUT samplen. + int_stop_pos_0 <= int_stop_pos_0(8 downto 0) & SROUT_in_0; + int_stop_pos_1 <= int_stop_pos_1(8 downto 0) & SROUT_in_1; + int_stop_pos_2 <= int_stop_pos_2(8 downto 0) & SROUT_in_2; + int_stop_pos_3 <= int_stop_pos_3(8 downto 0) & SROUT_in_3; + + END IF; -- rising edge CLK + END IF; -- CEN ='1' + END IF; -- flag_read_stop_pos = '1' + end process stop_pos_reader; + +end behavior; Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd (revision 9841) @@ -0,0 +1,99 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.std_logic_signed.all; + +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + + +ENTITY drs_pulser is + port ( + CLK : in std_logic; + + start_endless_mode : in std_logic; + start_read_stop_pos_mode : in std_logic; + + SROUT_in_0 : in std_logic; + SROUT_in_1 : in std_logic; + SROUT_in_2 : in std_logic; + SROUT_in_3 : in std_logic; + + stop_pos : out drs_s_cell_array_type; + stop_pos_valid : out std_logic := '0'; + + RSRLOAD : out std_logic := '0'; + SRCLK : out std_logic := '0' + ); +end drs_pulser; + + +ARCHITECTURE behavior of drs_pulser IS + +type state_main_type is (MAIN, READ_STOP_POS, ENDLESS_MODE); +signal state_main : state_main_type := MAIN; +signal stop_pos_cntr, wait_cntr : integer range 0 to 31 := 0; + +signal stop_pos_int : drs_s_cell_array_type; +signal RSRLOAD_EN, SRCLK_EN : std_logic := '0'; + +begin + + + main_proc: process (clk) begin + + RSRLOAD <= (clk and RSRLOAD_EN); + SRCLK <= (clk and SRCLK_EN); + + if rising_edge(clk) then + case state_main is + when MAIN => + if (start_read_stop_pos_mode = '1') then + RSRLOAD_EN <= '1'; + stop_pos_valid <= '0'; + state_main <= READ_STOP_POS; + end if; + if (start_endless_mode = '1') then + RSRLOAD_EN <= '1'; + state_main <= ENDLESS_MODE; + end if; + + when ENDLESS_MODE => + RSRLOAD_EN <= '0'; + if (wait_cntr = 3) then + SRCLK_EN <= '1'; + else + wait_cntr <= wait_cntr + 1; + end if; + if (start_endless_mode = '0') then + SRCLK_EN <= '0'; + wait_cntr <= 0; + state_main <= MAIN; + end if; + + when READ_STOP_POS => + RSRLOAD_EN <= '0'; + if (stop_pos_cntr = 10) then + stop_pos (0) <= stop_pos_int (0); + stop_pos (1) <= stop_pos_int (1); + stop_pos (2) <= stop_pos_int (2); + stop_pos (3) <= stop_pos_int (3); + stop_pos_valid <= '1'; + stop_pos_cntr <= 0; + SRCLK_EN <= '0'; + state_main <= MAIN; + else + SRCLK_EN <= '1'; + stop_pos_int (0) <= stop_pos_int (0) (8 downto 0) & SROUT_in_0; + stop_pos_int (1) <= stop_pos_int (1) (8 downto 0) & SROUT_in_1; + stop_pos_int (2) <= stop_pos_int (2) (8 downto 0) & SROUT_in_2; + stop_pos_int (3) <= stop_pos_int (3) (8 downto 0) & SROUT_in_3; + stop_pos_cntr <= stop_pos_cntr + 1; + end if; + + end case; -- state_main + end if; + + end process main_proc; + +end behavior; Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/fad_board.ucf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/fad_board.ucf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/fad_board.ucf (revision 9841) @@ -0,0 +1,260 @@ +########################################################### +# Pin location constraints +########################################################### + +#CLOCK +NET X_50M LOC = AF13 | IOSTANDARD=LVCMOS33; #ok + +## single ended trigger input +NET TRG LOC = AC8 | IOSTANDARD=LVCMOS33; #ok + +#Test Trigger input on 'Testpoint near W5300' +#NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; #ok +NET TEST_IN LOC = R19 | IOSTANDARD=LVCMOS33 | PULLUP; + +#NET W_T<2> LOC = N21 | IOSTANDARD=LVCMOS33; #ok +NET TEST_OUT LOC = N21 | IOSTANDARD=LVCMOS33; #ok + +## trigger veto: xilinx output +NET TRG_V LOC = AC9 | IOSTANDARD=LVCMOS33; #ok +## NET INIT_B LOC = AA15 | IOSTANDARD=LVCMOS33; #ok + + + +# RS485 Driver + +NET RS485_C_DE LOC = C5 | IOSTANDARD=LVCMOS33; #ok +NET RS485_C_RE LOC = C6 | IOSTANDARD=LVCMOS33; #ok +#NET RS485_C_DO LOC = C7 | IOSTANDARD=LVCMOS33; #ok +#NET RS485_C_DI LOC = C8 | IOSTANDARD=LVCMOS33; #ok + +NET RS485_E_DE LOC = D20 | IOSTANDARD=LVCMOS33; #ok +NET RS485_E_RE LOC = D21 | IOSTANDARD=LVCMOS33; #ok +#NET RS485_E_DO LOC = D22 | IOSTANDARD=LVCMOS33; #ok +#NET RS485_E_DI LOC = D23 | IOSTANDARD=LVCMOS33; #ok + + +# BOARD ID - inputs +#NET LINE<0> LOC = Y1 | IOSTANDARD=LVCMOS33; #ok +#NET LINE<1> LOC = Y2 | IOSTANDARD=LVCMOS33; #ok +#NET LINE<2> LOC = AB1 | IOSTANDARD=LVCMOS33; #ok +#NET LINE<3> LOC = AC1 | IOSTANDARD=LVCMOS33; #ok +#NET LINE<4> LOC = AD1 | IOSTANDARD=LVCMOS33; #ok +#NET LINE<5> LOC = AD2 | IOSTANDARD=LVCMOS33; #ok + +# W5300 +####################################################### +NET W_D<15> LOC = D24 | IOSTANDARD=LVCMOS33; #ok +NET W_D<14> LOC = D25 | IOSTANDARD=LVCMOS33; #ok +NET W_D<13> LOC = D26 | IOSTANDARD=LVCMOS33; #ok +NET W_D<12> LOC = E24 | IOSTANDARD=LVCMOS33; #ok +NET W_D<11> LOC = E26 | IOSTANDARD=LVCMOS33; #ok +NET W_D<10> LOC = F25 | IOSTANDARD=LVCMOS33; #ok +NET W_D<9> LOC = F24 | IOSTANDARD=LVCMOS33; #ok +NET W_D<8> LOC = G23 | IOSTANDARD=LVCMOS33; #ok +NET W_D<7> LOC = G24 | IOSTANDARD=LVCMOS33; #ok +NET W_D<6> LOC = J23 | IOSTANDARD=LVCMOS33; #ok +NET W_D<5> LOC = K25 | IOSTANDARD=LVCMOS33; #ok +NET W_D<4> LOC = K26 | IOSTANDARD=LVCMOS33; #ok +NET W_D<3> LOC = J22 | IOSTANDARD=LVCMOS33; #ok +NET W_D<2> LOC = K23 | IOSTANDARD=LVCMOS33; #ok +NET W_D<1> LOC = L22 | IOSTANDARD=LVCMOS33; #ok +NET W_D<0> LOC = M22 | IOSTANDARD=LVCMOS33; #ok + +NET W_A<9> LOC = V24 | IOSTANDARD=LVCMOS33; #ok +NET W_A<8> LOC = V25 | IOSTANDARD=LVCMOS33; #ok +NET W_A<7> LOC = W23 | IOSTANDARD=LVCMOS33; #ok +NET W_A<6> LOC = Y23 | IOSTANDARD=LVCMOS33; #ok +NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; #ok +NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; #ok +NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; #ok +NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; #ok +NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; #ok +NET W_A<0> LOC = Y22 | IOSTANDARD=LVCMOS33; #ok DUMMY + +NET W_WR LOC = P22 | IOSTANDARD=LVCMOS33; #ok +NET W_RD LOC = R20 | IOSTANDARD=LVCMOS33; #ok +NET W_CS LOC = T20 | IOSTANDARD=LVCMOS33; #ok +NET W_INT LOC = U22 | IOSTANDARD=LVCMOS33; #ok +NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; #ok + +#NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; #ok +#NET W_BRDY<2> LOC = AC26 | IOSTANDARD=LVCMOS33; #ok +#NET W_BRDY<1> LOC = AC25 | IOSTANDARD=LVCMOS33; #ok +#NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; #ok +# Testpoint near W5300 +#NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; #ok +#NET W_T<2> LOC = N21 | IOSTANDARD=LVCMOS33; #ok +#NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; #ok +#NET W_T<0> LOC = K21 | IOSTANDARD=LVCMOS33; #ok + +# Platform Flash - serial connection +####################################################### +##NET FL_CLK LOC = AE24 | IOSTANDARD=LVCMOS33; #ok +##NET FL_D0 LOC = AF24 | IOSTANDARD=LVCMOS33; #ok + +# DRS Signals +####################################################### +NET DENABLE LOC = B1 | IOSTANDARD=LVCMOS25; #ok +NET DWRITE LOC = R2 | IOSTANDARD=LVCMOS25; #ok + +NET SRIN LOC = E1 | IOSTANDARD=LVCMOS25; #ok -- nur fuer vollauslese noetig; auf Z legen. +#NET REFCLK LOC = AC11 | IOSTANDARD=LVCMOS25; #ok -- listen to REFCLK possible + + +NET D_A<3> LOC = N1 | IOSTANDARD=LVCMOS25; #ok +NET D_A<2> LOC = M2 | IOSTANDARD=LVCMOS25; #ok +NET D_A<1> LOC = K2 | IOSTANDARD=LVCMOS25; #ok +NET D_A<0> LOC = H2 | IOSTANDARD=LVCMOS25; #ok + + +# PLL-Lock input: high active +NET D_PLLLCK<0> LOC = L3 | IOSTANDARD=LVCMOS25 | PULLDOWN ; #ok +NET D_PLLLCK<1> LOC = N2 | IOSTANDARD=LVCMOS25 | PULLDOWN ; #ok +NET D_PLLLCK<2> LOC = AA2 | IOSTANDARD=LVCMOS25 | PULLDOWN ; #ok +NET D_PLLLCK<3> LOC = AC2 | IOSTANDARD=LVCMOS25 | PULLDOWN ; #ok + +# SROUT input: read stop position here +# bus?? +NET D0_SROUT LOC = B2 | IOSTANDARD=LVCMOS25; #ok +NET D1_SROUT LOC = E3 | IOSTANDARD=LVCMOS25; #ok +NET D2_SROUT LOC = N4 | IOSTANDARD=LVCMOS25; #ok +NET D3_SROUT LOC = U1 | IOSTANDARD=LVCMOS25; #ok + +# RSRLOAD & SRCLK output: clock out analog samples here +# SRCLK bus?? +NET RSRLOAD LOC = H1 | IOSTANDARD=LVCMOS25; #ok +# +NET D0_SRCLK LOC = F2 | IOSTANDARD=LVCMOS25; #ok +NET D1_SRCLK LOC = F3 | IOSTANDARD=LVCMOS25; #ok +NET D2_SRCLK LOC = R3 | IOSTANDARD=LVCMOS25; #ok +NET D3_SRCLK LOC = V1 | IOSTANDARD=LVCMOS25; #ok + +# Testpoints near DRS Chips +# oganized in 3 times 4x2 pins +NET D_T<0> LOC = D3 | IOSTANDARD=LVCMOS25; #ok +NET D_T<1> LOC = G3 | IOSTANDARD=LVCMOS25; #ok +NET D_T<2> LOC = G4 | IOSTANDARD=LVCMOS25; #ok +NET D_T<3> LOC = J4 | IOSTANDARD=LVCMOS25; #ok +NET D_T<4> LOC = K5 | IOSTANDARD=LVCMOS25; #ok +NET D_T<5> LOC = L4 | IOSTANDARD=LVCMOS25; #ok +NET D_T<6> LOC = M3 | IOSTANDARD=LVCMOS25; #ok +NET D_T<7> LOC = T3 | IOSTANDARD=LVCMOS25; #ok +NET D_T2<0> LOC = U2 | IOSTANDARD=LVCMOS25; #ok was D_T<8> +NET D_T2<1> LOC = V2 | IOSTANDARD=LVCMOS25; #ok was D_T<9> +NET D_T2<2> LOC = W3 | IOSTANDARD=LVCMOS25; #ok aka D_TA was D_T<10> +NET D_T2<3> LOC = AA3 | IOSTANDARD=LVCMOS25; #ok aka D_TB was D_T<11> + + + +# ADC Signals +####################################################### +NET OE_ADC LOC = D6 | IOSTANDARD=LVCMOS33; #ok FIXME was A-OEB + +NET A_CLK<0> LOC = B23 | IOSTANDARD=LVCMOS33; #ok aka A0_CLK +NET A_CLK<1> LOC = A3 | IOSTANDARD=LVCMOS33; #ok aka A1_CLK +NET A_CLK<2> LOC = AE3 | IOSTANDARD=LVCMOS33; #ok aka A2_CLK +NET A_CLK<3> LOC = AE25 | IOSTANDARD=LVCMOS33; #ok aka A3_CLK + +NET A_OTR<0> LOC = A22 | IOSTANDARD=LVCMOS33; #ok aka A0_OTR +NET A_OTR<1> LOC = B12 | IOSTANDARD=LVCMOS33; #ok aka A1_OTR +NET A_OTR<2> LOC = AF3 | IOSTANDARD=LVCMOS33; #ok aka A2_OTR +NET A_OTR<3> LOC = AE17 | IOSTANDARD=LVCMOS33; #ok aka A3_OTR + +# ADC data +NET A0_D<0> LOC = D13 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<1> LOC = A15 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<2> LOC = B15 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<3> LOC = B17 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<4> LOC = D16 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<5> LOC = A18 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<6> LOC = B18 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<7> LOC = A19 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<8> LOC = B19 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<9> LOC = A20 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<10> LOC = B21 | IOSTANDARD=LVCMOS33; #ok +NET A0_D<11> LOC = C22 | IOSTANDARD=LVCMOS33; #ok + +NET A1_D<0> LOC = B3 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<1> LOC = A4 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<2> LOC = B4 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<3> LOC = B6 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<4> LOC = B7 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<5> LOC = A8 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<6> LOC = B8 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<7> LOC = A9 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<8> LOC = B9 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<9> LOC = A10 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<10> LOC = B10 | IOSTANDARD=LVCMOS33; #ok +NET A1_D<11> LOC = A12 | IOSTANDARD=LVCMOS33; #ok + +NET A2_D<0> LOC = AD14 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<1> LOC = AD11 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<2> LOC = AD7 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<3> LOC = AE8 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<4> LOC = AF8 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<5> LOC = AE7 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<6> LOC = AC6 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<7> LOC = AE6 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<8> LOC = AF5 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<9> LOC = AD6 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<10> LOC = AF4 | IOSTANDARD=LVCMOS33; #ok +NET A2_D<11> LOC = AE4 | IOSTANDARD=LVCMOS33; #ok + +NET A3_D<0> LOC = AF25 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<1> LOC = AE23 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<2> LOC = AF23 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<3> LOC = AD22 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<4> LOC = AE21 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<5> LOC = AD21 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<6> LOC = AF20 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<7> LOC = AE20 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<8> LOC = AF19 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<9> LOC = AC22 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<10> LOC = AE19 | IOSTANDARD=LVCMOS33; #ok +NET A3_D<11> LOC = AD19 | IOSTANDARD=LVCMOS33; #ok + +# testpoints near ADC + +#NET A0_T<0> LOC = D8 | IOSTANDARD=LVCMOS33; #ok +#NET A0_T<1> LOC = D9 | IOSTANDARD=LVCMOS33; #ok +#NET A0_T<2> LOC = D10 | IOSTANDARD=LVCMOS33; #ok +#NET A0_T<3> LOC = E10 | IOSTANDARD=LVCMOS33; #ok +#NET A0_T<4> LOC = E12 | IOSTANDARD=LVCMOS33; #ok +#NET A0_T<5> LOC = E14 | IOSTANDARD=LVCMOS33; #ok +#NET A0_T<6> LOC = D17 | IOSTANDARD=LVCMOS33; #ok +#NET A0_T<7> LOC = D18 | IOSTANDARD=LVCMOS33; #ok + +NET A1_T<0> LOC = AB9 | IOSTANDARD=LVCMOS33; #ok +NET A1_T<1> LOC = AB12 | IOSTANDARD=LVCMOS33; #ok +NET A1_T<2> LOC = AC12 | IOSTANDARD=LVCMOS33; #ok +NET A1_T<3> LOC = AC14 | IOSTANDARD=LVCMOS33; #ok +NET A1_T<4> LOC = AC15 | IOSTANDARD=LVCMOS33; #ok +#NET A1_T<5> LOC = AB16 | IOSTANDARD=LVCMOS33; #ok +#NET A1_T<6> LOC = AC16 | IOSTANDARD=LVCMOS33; #ok +#NET A1_T<7> LOC = AB18 | IOSTANDARD=LVCMOS33; #ok + + + +# SPI bus +####################################################### +NET S_CLK LOC = C10 | IOSTANDARD=LVCMOS33; #ok +NET MOSI LOC = C11 | IOSTANDARD=LVCMOS33; #ok +NET MISO LOC = C12 | IOSTANDARD=LVCMOS33; #ok + +NET T0_CS LOC = C15 | IOSTANDARD=LVCMOS33; #ok +NET T1_CS LOC = C16 | IOSTANDARD=LVCMOS33; #ok +NET T2_CS LOC = C17 | IOSTANDARD=LVCMOS33; #ok +NET T3_CS LOC = C18 | IOSTANDARD=LVCMOS33; #ok +NET DAC_CS LOC = C20 | IOSTANDARD=LVCMOS33; #ok +NET EE_CS LOC = C21 | IOSTANDARD=LVCMOS33; #ok + + + +# LEDs +####################################################### +NET LED<0> LOC = T4 | IOSTANDARD=LVCMOS25 | DRIVE = 2; +NET LED<1> LOC = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 2; +NET LED<2> LOC = AD20 | IOSTANDARD=LVCMOS33 | DRIVE = 2; + + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 9841) @@ -0,0 +1,269 @@ +-- VHDL Entity FACT_FAD_lib.FAD_Board.symbol +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 10:53:35 27.07.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +ENTITY FAD_Board IS + PORT( + A0_D : IN std_logic_vector (11 DOWNTO 0); + A1_D : IN std_logic_vector (11 DOWNTO 0); + A2_D : IN std_logic_vector (11 DOWNTO 0); + A3_D : IN std_logic_vector (11 DOWNTO 0); + A_OTR : IN std_logic_vector (3 DOWNTO 0); + D0_SROUT : IN std_logic; + D1_SROUT : IN std_logic; + D2_SROUT : IN std_logic; + D3_SROUT : IN std_logic; + D_PLLLCK : IN std_logic_vector (3 DOWNTO 0); + TEST_IN : IN std_logic; + TRG : IN STD_LOGIC; + W_INT : IN std_logic; + X_50M : IN STD_LOGIC; + A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + A_CLK : OUT std_logic_vector (3 DOWNTO 0); + D0_SRCLK : OUT STD_LOGIC; + D1_SRCLK : OUT STD_LOGIC; + D2_SRCLK : OUT STD_LOGIC; + D3_SRCLK : OUT STD_LOGIC; + DAC_CS : OUT std_logic; + DENABLE : OUT std_logic := '0'; + DWRITE : OUT std_logic := '0'; + D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + EE_CS : OUT std_logic; + LED : OUT std_logic_vector ( 2 DOWNTO 0 ) := (others => '1'); + MOSI : OUT std_logic := '0'; + OE_ADC : OUT STD_LOGIC; + RS485_C_DE : OUT std_logic; + RS485_C_RE : OUT std_logic; + RS485_E_DE : OUT std_logic; + RS485_E_RE : OUT std_logic; + RSRLOAD : OUT std_logic := '0'; + SRIN : OUT std_logic; + S_CLK : OUT std_logic; + T0_CS : OUT std_logic; + T1_CS : OUT std_logic; + T2_CS : OUT std_logic; + T3_CS : OUT std_logic; + TEST_OUT : OUT std_logic := '0'; + TRG_V : OUT std_logic; + W_A : OUT std_logic_vector (9 DOWNTO 0); + W_CS : OUT std_logic := '1'; + W_RD : OUT std_logic := '1'; + W_RES : OUT std_logic := '1'; + W_WR : OUT std_logic := '1'; + MISO : INOUT std_logic; + W_D : INOUT std_logic_vector (15 DOWNTO 0) + ); + +-- Declarations + +END FAD_Board ; + +-- +-- VHDL Architecture FACT_FAD_lib.FAD_Board.struct +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 10:53:35 27.07.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE IEEE.NUMERIC_STD.all; +USE ieee.std_logic_unsigned.all; + +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +LIBRARY FACT_FAD_lib; + +ARCHITECTURE struct OF FAD_Board IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL CLK_25_PS : std_logic; + SIGNAL CLK_50 : std_logic; + SIGNAL SRCLK : std_logic := '0'; + SIGNAL TRG_OR : std_logic; + SIGNAL adc_data_array : adc_data_array_type; + SIGNAL board_id : std_logic_vector(3 DOWNTO 0); + SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); + SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0'); + SIGNAL dummy : std_logic; + SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); + + + -- Component Declarations + COMPONENT FAD_main + GENERIC ( + RAMADDRWIDTH64b : integer := 12 + ); + PORT ( + CLK : IN std_logic ; + SROUT_in_0 : IN std_logic ; + SROUT_in_1 : IN std_logic ; + SROUT_in_2 : IN std_logic ; + SROUT_in_3 : IN std_logic ; + TEST_IN : IN std_logic ; + adc_data_array : IN adc_data_array_type ; + adc_otr_array : IN std_logic_vector (3 DOWNTO 0); + board_id : IN std_logic_vector (3 DOWNTO 0); + crate_id : IN std_logic_vector (1 DOWNTO 0); + trigger : IN std_logic ; + wiz_int : IN std_logic ; + CLK_25_PS : OUT std_logic ; + CLK_50 : OUT std_logic ; + RSRLOAD : OUT std_logic := '0'; + SRCLK : OUT std_logic := '0'; + adc_oeb : OUT std_logic := '1'; + config_start_out : OUT STD_LOGIC := "0"; + dac_cs : OUT std_logic ; + denable : OUT std_logic := '0'; -- default domino wave off + drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + drs_dwrite : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + mosi : OUT std_logic := '0'; + sclk : OUT std_logic ; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0); + wiz_addr : OUT std_logic_vector (9 DOWNTO 0); + wiz_cs : OUT std_logic := '1'; + wiz_rd : OUT std_logic := '1'; + wiz_reset : OUT std_logic := '1'; + wiz_wr : OUT std_logic := '1'; + sio : INOUT std_logic ; + wiz_data : INOUT std_logic_vector (15 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb_ID + -- hard-wired IDs + board_id <= "0101"; + crate_id <= "01"; + + -- HDL Embedded Text Block 2 ADC_CLK + -- ADC_CLK 2 + A_CLK (0) <= CLK_25_PS; + A_CLK (1) <= CLK_25_PS; + A_CLK (2) <= CLK_25_PS; + A_CLK (3) <= CLK_25_PS; + + -- HDL Embedded Text Block 3 ADC_DATA + -- ADC_DATA 3 + adc_data_array (0) <= A0_D; + adc_data_array (1) <= A1_D; + adc_data_array (2) <= A2_D; + adc_data_array (3) <= A3_D; + + -- HDL Embedded Text Block 4 SRCLK + -- SRCLK 4 + D0_SRCLK <= SRCLK; + D1_SRCLK <= SRCLK; + D2_SRCLK <= SRCLK; + D3_SRCLK <= SRCLK; + + -- HDL Embedded Text Block 5 T_CS + -- T_CS 5 + T0_CS <= sensor_cs (0); + T1_CS <= sensor_cs (1); + T2_CS <= sensor_cs (2); + T3_CS <= sensor_cs (3); + + -- HDL Embedded Text Block 6 MISC + -- MISC 6 + TRG_V <= '0'; + RS485_C_RE <= '1'; + RS485_C_DE <= '0'; + RS485_E_RE <= '1'; + RS485_E_DE <= '0'; + + -- DENABLE <= '0'; -- domino wave stopped + -- DENABLE <= '1'; -- domino wave running + + SRIN <= 'Z'; + EE_CS <= '1'; + -- LEDs are low active + LED(0) <= '1'; + LED(1) <= '0'; -- on + LED(2) <= '1'; + + + + + -- HDL Embedded Text Block 7 eb1 + D_T2 <= D_PLLLCK; + + -- HDL Embedded Text Block 8 eb2 + -- eb2 8 + A1_T(3 downto 0) <= drs_channel_id; + D_A <= drs_channel_id; + A1_T(4) <= TRG_OR; + + + -- ModuleWare code(v1.9) for instance 'I0' of 'assignment' + TRG_OR <= TRG; + + -- ModuleWare code(v1.9) for instance 'I3' of 'assignment' + DAC_CS <= dummy; + + -- Instance port mappings. + I_board_main : FAD_main + GENERIC MAP ( + RAMADDRWIDTH64b => LOG2_OF_RAM_SIZE_64B + ) + PORT MAP ( + CLK => X_50M, + SROUT_in_0 => D0_SROUT, + SROUT_in_1 => D1_SROUT, + SROUT_in_2 => D2_SROUT, + SROUT_in_3 => D3_SROUT, + TEST_IN => TEST_IN, + adc_data_array => adc_data_array, + adc_otr_array => A_OTR, + board_id => board_id, + crate_id => crate_id, + trigger => TRG_OR, + wiz_int => W_INT, + CLK_25_PS => CLK_25_PS, + CLK_50 => CLK_50, + RSRLOAD => RSRLOAD, + SRCLK => SRCLK, + adc_oeb => OE_ADC, + config_start_out => TEST_OUT, + dac_cs => dummy, + denable => DENABLE, + drs_channel_id => drs_channel_id, + drs_dwrite => DWRITE, + led => D_T, + mosi => MOSI, + sclk => S_CLK, + sensor_cs => sensor_cs, + wiz_addr => W_A, + wiz_cs => W_CS, + wiz_rd => W_RD, + wiz_reset => W_RES, + wiz_wr => W_WR, + sio => MISO, + wiz_data => W_D + ); + +END struct; Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 9841) @@ -0,0 +1,135 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- use IEEE.NUMERIC_STD.ALL; + +package fad_definitions is + + +-- Declare constants + + type mac_type is array (0 to 2) of std_logic_vector (15 downto 0); + type ip_type is array (0 to 3) of integer; +-- Network Settings + + constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"97B4"); + + -- @ ETH zurich + -- constant NETMASK : ip_type := (255, 255, 248, 0); + -- constant IP_ADDRESS : ip_type := (192, 33, 99, 225); + -- constant GATEWAY : ip_type := (192, 33, 96, 1); + + -- @ TU Dortmund + constant NETMASK : ip_type := (255, 255, 255, 0); + constant IP_ADDRESS : ip_type := (129, 217, 160, 119); + constant GATEWAY : ip_type := (129, 217, 160, 1); + + constant FIRST_PORT : integer := 5000; +-- Network Settings End + + constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"01"; + constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"02"; + constant PACKAGE_HEADER_LENGTH : integer := 22; + constant PACKAGE_END_LENGTH : integer := 2; -- CRC and END-Flag + + constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset + +-- W5300 Registers + constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0'); + constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0"; + constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2"; + constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4"; + constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8"; + constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10"; + constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14"; + constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18"; + constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C"; + constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E"; + constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20"; + constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22"; + constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24"; + constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26"; + constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28"; + constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A"; + constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C"; + constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E"; + constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30"; + + constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0"; + constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2"; + constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4"; + constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6"; + constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8"; + constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A"; + constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12"; + constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14"; + constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20"; + constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24"; + constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28"; + constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E"; + constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30"; +-- End W5300 registers + +-- + constant W5300_TX_FIFO_SIZE : integer := (15360 / 2); -- Socket TX FIFO-Size in 16 Bit Words + + constant LOG2_OF_RAM_SIZE_64B : integer := 15; + --constant RAM_SIZE_64B : integer := 2**LOG2_OF_RAM_SIZE_64B; + constant RAM_SIZE_64B : integer := 24576; + constant RAM_SIZE_16B : integer := RAM_SIZE_64B * 4; + +-- TYPE definitions + type roi_max_type is array (0 to 8) of std_logic_vector (10 downto 0); + type roi_array_type is array (0 to 35) of integer range 0 to 1024; + type drs_s_cell_array_type is array (0 to 3) of std_logic_vector (9 downto 0); + type adc_data_array_type is array (0 to 3) of std_logic_vector (11 downto 0); + + type dac_array_type is array (0 to 7) of integer range 0 to 2**16 - 1; + type sensor_array_type is array (0 to 3) of integer range 0 to 2**16 - 1; + +-- constant DEFAULT_ROI : roi_array_type := (115, 125, 100, 102, 155, 101, 0, 101, 106, +-- 181, 121, 189, 101, 101, 187, 56, 187, 101, +-- 2, 141, 101, 100, 10, 100, 178, 101, 174, +-- 12, 181, 100, 102, 101, 102, 0, 101, 108); +-- constant DEFAULT_ROI : roi_array_type := (others => 100); + constant DEFAULT_ROI : roi_array_type := (others => 210); + + constant DEFAULT_DAC : dac_array_type := (20972, 34079, 20526, 0, 28836, 28836, 28836, 28836); + --constant DEFAULT_DAC : dac_array_type := (others => 0); + + constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= "0000"; + constant DEFAULT_DRSADDR_MODE : std_logic := '0'; + + + +-- Commands + constant CMD_START : std_logic_vector := X"C0"; + constant CMD_STOP : std_logic_vector := X"30"; + constant CMD_TRIGGER : std_logic_vector := X"A0"; + + constant CMD_TRIGGER_C : std_logic_vector := X"B0"; + constant CMD_TRIGGER_S : std_logic_vector := X"20"; + constant CMD_READ : std_logic_vector := X"0A"; + constant CMD_WRITE : std_logic_vector := X"05"; + + constant CMD_DENABLE : std_logic_vector := X"06"; + constant CMD_DDISABLE : std_logic_vector := X"07"; + constant CMD_DWRITE_RUN : std_logic_vector := X"08"; + constant CMD_DWRITE_STOP : std_logic_vector := X"09"; + constant CMD_SCLK_ON : std_logic_vector := X"10"; + constant CMD_SCLK_OFF : std_logic_vector := X"11"; + + +-- Declare functions and procedure + + +end fad_definitions; + + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd.bak =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd.bak (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd.bak (revision 9841) @@ -0,0 +1,135 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- use IEEE.NUMERIC_STD.ALL; + +package fad_definitions is + + +-- Declare constants + + type mac_type is array (0 to 2) of std_logic_vector (15 downto 0); + type ip_type is array (0 to 3) of integer; +-- Network Settings + + constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"97B4"); + + -- @ ETH zurich + -- constant NETMASK : ip_type := (255, 255, 248, 0); + -- constant IP_ADDRESS : ip_type := (192, 33, 99, 225); + -- constant GATEWAY : ip_type := (192, 33, 96, 1); + + -- @ TU Dortmund + constant NETMASK : ip_type := (255, 255, 255, 0); + constant IP_ADDRESS : ip_type := (129, 217, 160, 119); + constant GATEWAY : ip_type := (129, 217, 160, 1); + + constant FIRST_PORT : integer := 5000; +-- Network Settings End + + constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"01"; + constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"02"; + constant PACKAGE_HEADER_LENGTH : integer := 22; + constant PACKAGE_END_LENGTH : integer := 2; -- CRC and END-Flag + + constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset + +-- W5300 Registers + constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0'); + constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0"; + constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2"; + constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4"; + constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8"; + constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10"; + constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14"; + constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18"; + constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C"; + constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E"; + constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20"; + constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22"; + constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24"; + constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26"; + constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28"; + constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A"; + constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C"; + constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E"; + constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30"; + + constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0"; + constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2"; + constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4"; + constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6"; + constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8"; + constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A"; + constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12"; + constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14"; + constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20"; + constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24"; + constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28"; + constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E"; + constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30"; +-- End W5300 registers + +-- + constant W5300_TX_FIFO_SIZE : integer := (15360 / 2); -- Socket TX FIFO-Size in 16 Bit Words + + constant LOG2_OF_RAM_SIZE_64B : integer := 15; + --constant RAM_SIZE_64B : integer := 2**LOG2_OF_RAM_SIZE_64B; + constant RAM_SIZE_64B : integer := 24576; + constant RAM_SIZE_16B : integer := RAM_SIZE_64B * 4; + +-- TYPE definitions + type roi_max_type is array (0 to 8) of std_logic_vector (10 downto 0); + type roi_array_type is array (0 to 35) of integer range 0 to 1024; + type drs_s_cell_array_type is array (0 to 3) of std_logic_vector (9 downto 0); + type adc_data_array_type is array (0 to 3) of std_logic_vector (11 downto 0); + + type dac_array_type is array (0 to 7) of integer range 0 to 2**16 - 1; + type sensor_array_type is array (0 to 3) of integer range 0 to 2**16 - 1; + +-- constant DEFAULT_ROI : roi_array_type := (115, 125, 100, 102, 155, 101, 0, 101, 106, +-- 181, 121, 189, 101, 101, 187, 56, 187, 101, +-- 2, 141, 101, 100, 10, 100, 178, 101, 174, +-- 12, 181, 100, 102, 101, 102, 0, 101, 108); +-- constant DEFAULT_ROI : roi_array_type := (others => 100); + constant DEFAULT_ROI : roi_array_type := (others => 210); + + constant DEFAULT_DAC : dac_array_type := (20972, 34079, 20526, 0, 28836, 28836, 28836, 28836); + --constant DEFAULT_DAC : dac_array_type := (others => 0); + + constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= "0000"; + constant DEFAULT_DRSADDR_MODE : std_logic := '0'; + + + +-- Commands + constant CMD_START : std_logic_vector := X"C0"; + constant CMD_STOP : std_logic_vector := X"30"; + constant CMD_TRIGGER : std_logic_vector := X"A0"; + + constant CMD_TRIGGER_C : std_logic_vector := X"B0"; + constant CMD_TRIGGER_S : std_logic_vector := X"20"; + constant CMD_READ : std_logic_vector := X"0A"; + constant CMD_WRITE : std_logic_vector := X"05"; + + constant CMD_DENABLE : std_logic_vector := X"06"; + constant CMD_DDISABLE : std_logic_vector := X"07"; + constant CMD_DWRITE_RUN : std_logic_vector := X"08"; + constant CMD_DWRITE_STOP : std_logic_vector := X"09"; + constant CMD_SCLK_ON : std_logic_vector := X"10"; + constant CMD_SCLK_ON : std_logic_vector := X"11"; + + +-- Declare functions and procedure + + +end fad_definitions; + + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 9841) @@ -0,0 +1,598 @@ +-- VHDL Entity FACT_FAD_lib.FAD_main.symbol +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 10:54:06 27.07.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +ENTITY FAD_main IS + GENERIC( + RAMADDRWIDTH64b : integer := 12 + ); + PORT( + CLK : IN std_logic; + SROUT_in_0 : IN std_logic; + SROUT_in_1 : IN std_logic; + SROUT_in_2 : IN std_logic; + SROUT_in_3 : IN std_logic; + TEST_IN : IN std_logic; + adc_data_array : IN adc_data_array_type; + adc_otr_array : IN std_logic_vector (3 DOWNTO 0); + board_id : IN std_logic_vector (3 DOWNTO 0); + crate_id : IN std_logic_vector (1 DOWNTO 0); + trigger : IN std_logic; + wiz_int : IN std_logic; + CLK_25_PS : OUT std_logic; + CLK_50 : OUT std_logic; + RSRLOAD : OUT std_logic := '0'; + SRCLK : OUT std_logic := '0'; + adc_oeb : OUT std_logic := '1'; + config_start_out : OUT STD_LOGIC := '0'; + dac_cs : OUT std_logic; + denable : OUT std_logic := '0'; -- default domino wave off + drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + drs_dwrite : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + mosi : OUT std_logic := '0'; + sclk : OUT std_logic; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0); + wiz_addr : OUT std_logic_vector (9 DOWNTO 0); + wiz_cs : OUT std_logic := '1'; + wiz_rd : OUT std_logic := '1'; + wiz_reset : OUT std_logic := '1'; + wiz_wr : OUT std_logic := '1'; + sio : INOUT std_logic; + wiz_data : INOUT std_logic_vector (15 DOWNTO 0) + ); + +-- Declarations + +END FAD_main ; + +-- +-- VHDL Architecture FACT_FAD_lib.FAD_main.struct +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 10:54:06 27.07.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use ieee.STD_LOGIC_UNSIGNED.all; + +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + +library UNISIM; +use UNISIM.VComponents.all; +USE IEEE.NUMERIC_STD.all; +USE IEEE.std_logic_signed.all; + +LIBRARY FACT_FAD_lib; + +ARCHITECTURE struct OF FAD_main IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL CLK_25 : std_logic; + SIGNAL adc_data_array_int : adc_data_array_type; + SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0); + SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); + SIGNAL config_addr : std_logic_vector(7 DOWNTO 0); + SIGNAL config_busy : std_logic; + SIGNAL config_data : std_logic_vector(15 DOWNTO 0); + SIGNAL config_data_valid : std_logic; + SIGNAL config_rd_en : std_logic; + SIGNAL config_ready : std_logic; + SIGNAL config_ready_cm : std_logic; + SIGNAL config_ready_spi : std_logic; + SIGNAL config_start : std_logic := '0'; + SIGNAL config_start1 : std_logic; + SIGNAL config_start_cm : std_logic; + SIGNAL config_start_spi : std_logic := '0'; + SIGNAL config_started : std_logic; + SIGNAL config_started_cu : std_logic := '0'; + SIGNAL config_started_mm : std_logic; + SIGNAL config_started_spi : std_logic := '0'; + SIGNAL config_wr_en : std_logic; + SIGNAL dac_array : dac_array_type; + SIGNAL data_out : std_logic_vector(63 DOWNTO 0); + SIGNAL dout : std_logic; + SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0'); + SIGNAL drs_address_mode : std_logic; + SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0'); + SIGNAL drs_clk_en : std_logic := '0'; + SIGNAL drs_read_s_cell : std_logic := '0'; + SIGNAL drs_read_s_cell_ready : std_logic; + SIGNAL drs_s_cell_array : drs_s_cell_array_type; + SIGNAL dwrite : std_logic := '1'; + SIGNAL dwrite_enable : std_logic := '1'; + SIGNAL new_config : std_logic := '0'; + SIGNAL package_length : std_logic_vector(15 DOWNTO 0); + SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0); + SIGNAL ram_data : std_logic_vector(15 DOWNTO 0); + SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); + SIGNAL ram_write_ea : std_logic; + SIGNAL ram_write_ready : std_logic := '0'; + SIGNAL roi_array : roi_array_type; + SIGNAL roi_max : roi_max_type; + SIGNAL s_trigger : std_logic := '0'; + SIGNAL sclk1 : std_logic; + SIGNAL sclk_enable : std_logic; + SIGNAL sensor_array : sensor_array_type; + SIGNAL sensor_ready : std_logic; + SIGNAL trigger_id : std_logic_vector(47 DOWNTO 0); + SIGNAL trigger_out : STD_LOGIC := '0'; + SIGNAL wiz_ack : std_logic; + SIGNAL wiz_busy : std_logic; + SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); + SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); + SIGNAL wiz_write_ea : std_logic := '0'; + SIGNAL wiz_write_end : std_logic := '0'; + SIGNAL wiz_write_header : std_logic := '0'; + SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0'); + SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0"; + + -- Implicit buffer signal declarations + SIGNAL CLK_25_PS_internal : std_logic; + SIGNAL CLK_50_internal : std_logic; + + + -- Component Declarations + COMPONENT adc_buffer + PORT ( + adc_data_array : IN adc_data_array_type; + adc_otr_array : IN std_logic_vector (3 DOWNTO 0); + clk_ps : IN std_logic; + adc_data_array_int : OUT adc_data_array_type; + adc_otr : OUT std_logic_vector (3 DOWNTO 0) + ); + END COMPONENT; + COMPONENT clock_generator + PORT ( + CLK : IN std_logic ; + CLK_25 : OUT std_logic ; + CLK_25_PS : OUT std_logic ; + CLK_50 : OUT std_logic + ); + END COMPONENT; + COMPONENT control_unit + PORT ( + clk : IN STD_LOGIC ; + config_addr : IN std_logic_vector (7 DOWNTO 0); + config_rd_en : IN std_logic ; + config_start : IN std_logic ; + config_wr_en : IN std_logic ; + config_busy : OUT std_logic ; + config_data_valid : OUT std_logic ; + config_ready : OUT std_logic ; + config_started : OUT std_logic := '0'; + dac_array : OUT dac_array_type ; + drs_address : OUT std_logic_vector (3 DOWNTO 0); + drs_address_mode : OUT std_logic ; + roi_array : OUT roi_array_type ; + config_data : INOUT std_logic_vector (15 DOWNTO 0) + ); + END COMPONENT; + COMPONENT dataRAM_64b_16b_width14_5 + PORT ( + clka : IN std_logic ; + dina : IN std_logic_VECTOR (63 DOWNTO 0); + addra : IN std_logic_VECTOR (14 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + clkb : IN std_logic ; + addrb : IN std_logic_VECTOR (16 DOWNTO 0); + doutb : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + END COMPONENT; + COMPONENT data_generator + GENERIC ( + RAM_ADDR_WIDTH : integer := 12 + ); + PORT ( + clk : IN std_logic ; + data_out : OUT std_logic_vector (63 DOWNTO 0); + addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + write_ea : OUT std_logic_vector (0 DOWNTO 0) := "0"; + ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + ram_write_ea : IN std_logic ; + ram_write_ready : OUT std_logic := '0'; + config_start_mm : OUT std_logic := '0'; + config_start_cm : OUT std_logic := '0'; + config_start_spi : OUT std_logic := '0'; + config_ready_mm : IN std_logic ; + config_ready_cm : IN std_logic ; + config_ready_spi : IN std_logic ; + config_started_mm : IN std_logic ; + config_started_cm : IN std_logic ; + config_started_spi : IN std_logic ; + roi_array : IN roi_array_type ; + roi_max : IN roi_max_type ; + sensor_array : IN sensor_array_type ; + sensor_ready : IN std_logic ; + dac_array : IN dac_array_type ; + package_length : IN std_logic_vector (15 DOWNTO 0); + board_id : IN std_logic_vector (3 DOWNTO 0); + crate_id : IN std_logic_vector (1 DOWNTO 0); + trigger_id : IN std_logic_vector (47 DOWNTO 0); + trigger : IN std_logic ; + s_trigger : IN std_logic ; + new_config : IN std_logic ; + config_started : OUT std_logic := '0'; + adc_data_array : IN adc_data_array_type ; + adc_oeb : OUT std_logic := '1'; + adc_otr : IN std_logic_vector (3 DOWNTO 0); + drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + drs_dwrite : OUT std_logic := '1'; + drs_clk_en : OUT std_logic := '0'; + drs_read_s_cell : OUT std_logic := '0'; + drs_read_s_cell_ready : IN std_logic ; + drs_s_cell_array : IN drs_s_cell_array_type + ); + END COMPONENT; + COMPONENT debouncer + GENERIC ( + WIDTH : INTEGER := 17 + ); + PORT ( + clk : IN STD_LOGIC ; + -- rst : in STD_LOGIC; + trigger_in : IN STD_LOGIC ; + trigger_out : OUT STD_LOGIC := '0' + ); + END COMPONENT; + COMPONENT drs_pulser + PORT ( + CLK : IN std_logic; + SROUT_in_0 : IN std_logic; + SROUT_in_1 : IN std_logic; + SROUT_in_2 : IN std_logic; + SROUT_in_3 : IN std_logic; + start_endless_mode : IN std_logic; + start_read_stop_pos_mode : IN std_logic; + RSRLOAD : OUT std_logic := '0'; + SRCLK : OUT std_logic := '0'; + stop_pos : OUT drs_s_cell_array_type; + stop_pos_valid : OUT std_logic := '0' + ); + END COMPONENT; + COMPONENT memory_manager + GENERIC ( + RAM_ADDR_WIDTH_64B : integer := 12; + RAM_ADDR_WIDTH_16B : integer := 14 + ); + PORT ( + clk : IN std_logic ; + config_start : IN std_logic ; + ram_write_ready : IN std_logic ; + roi_array : IN roi_array_type ; + ram_write_ea : OUT std_logic := '0'; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0'; + roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); + package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 DOWNTO 0) := (others => '0'); + wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0'); + wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + wiz_write_ea : OUT std_logic := '0'; + wiz_write_header : OUT std_logic := '0'; + wiz_write_end : OUT std_logic := '0'; + wiz_busy : IN std_logic ; + wiz_ack : IN std_logic ; + ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') + ); + END COMPONENT; + COMPONENT spi_interface + PORT ( + clk_50MHz : IN std_logic ; + config_start : IN std_logic ; + dac_array : IN dac_array_type ; + config_ready : OUT std_logic ; + config_started : OUT std_logic := '0'; + dac_cs : OUT std_logic ; + mosi : OUT std_logic := '0'; + sclk : OUT std_logic ; + sensor_array : OUT sensor_array_type ; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0); + sensor_ready : OUT std_logic ; + miso : INOUT std_logic + ); + END COMPONENT; + COMPONENT trigger_counter + PORT ( + trigger_id : OUT std_logic_vector (47 DOWNTO 0); + trigger : IN std_logic ; + clk : IN std_logic + ); + END COMPONENT; + COMPONENT w5300_modul + GENERIC ( + RAM_ADDR_WIDTH : integer := 14 + ); + PORT ( + clk : IN std_logic ; + wiz_reset : OUT std_logic := '1'; + addr : OUT std_logic_vector (9 DOWNTO 0); + data : INOUT std_logic_vector (15 DOWNTO 0); + cs : OUT std_logic := '1'; + wr : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + rd : OUT std_logic := '1'; + int : IN std_logic ; + write_length : IN std_logic_vector (16 DOWNTO 0); + ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + ram_data : IN std_logic_vector (15 DOWNTO 0); + ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + data_valid : IN std_logic ; + data_valid_ack : OUT std_logic := '0'; + busy : OUT std_logic := '1'; + write_header_flag : IN std_logic ; + write_end_flag : IN std_logic ; + fifo_channels : IN std_logic_vector (3 DOWNTO 0); + s_trigger : OUT std_logic := '0'; + new_config : OUT std_logic := '0'; + config_started : IN std_logic ; + config_addr : OUT std_logic_vector (7 DOWNTO 0); + config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + config_wr_en : OUT std_logic := '0'; + config_rd_en : OUT std_logic := '0'; + config_busy : IN std_logic ; + denable : OUT std_logic := '0'; -- default domino wave off + dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. + sclk_enable : OUT std_logic := '1' -- default DWRITE HIGH. + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer; + FOR ALL : clock_generator USE ENTITY FACT_FAD_lib.clock_generator; + FOR ALL : control_unit USE ENTITY FACT_FAD_lib.control_unit; + FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5; + FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator; + FOR ALL : debouncer USE ENTITY FACT_FAD_lib.debouncer; + FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser; + FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager; + FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface; + FOR ALL : trigger_counter USE ENTITY FACT_FAD_lib.trigger_counter; + FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul; + -- pragma synthesis_on + + +BEGIN + + -- ModuleWare code(v1.9) for instance 'I5' of 'and' + drs_dwrite <= dwrite AND dwrite_enable; + + -- ModuleWare code(v1.9) for instance 'U_1' of 'and' + sclk <= sclk_enable AND sclk1; + + -- ModuleWare code(v1.9) for instance 'U_6' of 'assignment' + config_start_out <= config_start1; + + -- ModuleWare code(v1.9) for instance 'U_3' of 'inv' + dout <= NOT(TEST_IN); + + -- ModuleWare code(v1.9) for instance 'U_0' of 'mux' + u_0combo_proc: PROCESS(drs_channel_internal, drs_address, + drs_address_mode) + BEGIN + CASE drs_address_mode IS + WHEN '0' => drs_channel_id <= drs_channel_internal; + WHEN '1' => drs_channel_id <= drs_address; + WHEN OTHERS => drs_channel_id <= (OTHERS => 'X'); + END CASE; + END PROCESS u_0combo_proc; + + -- ModuleWare code(v1.9) for instance 'U_2' of 'or' + config_start1 <= config_start_cm OR trigger_out; + + -- Instance port mappings. + I_main_adc_buffer : adc_buffer + PORT MAP ( + clk_ps => CLK_25_PS_internal, + adc_data_array => adc_data_array, + adc_otr_array => adc_otr_array, + adc_data_array_int => adc_data_array_int, + adc_otr => adc_otr + ); + I_main_clock_gen : clock_generator + PORT MAP ( + CLK => CLK, + CLK_25 => CLK_25, + CLK_25_PS => CLK_25_PS_internal, + CLK_50 => CLK_50_internal + ); + I_main_control_unit : control_unit + PORT MAP ( + clk => CLK_50_internal, + config_addr => config_addr, + config_rd_en => config_rd_en, + config_start => config_start1, + config_wr_en => config_wr_en, + config_busy => config_busy, + config_data_valid => config_data_valid, + config_ready => config_ready_cm, + config_started => config_started_cu, + dac_array => dac_array, + drs_address => drs_address, + drs_address_mode => drs_address_mode, + roi_array => roi_array, + config_data => config_data + ); + U_4 : dataRAM_64b_16b_width14_5 + PORT MAP ( + clka => CLK_25, + dina => data_out, + addra => addr_out, + wea => write_ea, + clkb => CLK_50_internal, + addrb => ram_addr, + doutb => ram_data + ); + I_main_data_generator : data_generator + GENERIC MAP ( + RAM_ADDR_WIDTH => RAMADDRWIDTH64b + ) + PORT MAP ( + clk => CLK_25, + data_out => data_out, + addr_out => addr_out, + write_ea => write_ea, + ram_start_addr => ram_start_addr, + ram_write_ea => ram_write_ea, + ram_write_ready => ram_write_ready, + config_start_mm => config_start, + config_start_cm => config_start_cm, + config_start_spi => config_start_spi, + config_ready_mm => config_ready, + config_ready_cm => config_ready_cm, + config_ready_spi => config_ready_spi, + config_started_mm => config_started_mm, + config_started_cm => config_started_cu, + config_started_spi => config_started_spi, + roi_array => roi_array, + roi_max => roi_max, + sensor_array => sensor_array, + sensor_ready => sensor_ready, + dac_array => dac_array, + package_length => package_length, + board_id => board_id, + crate_id => crate_id, + trigger_id => trigger_id, + trigger => trigger, + s_trigger => s_trigger, + new_config => new_config, + config_started => config_started, + adc_data_array => adc_data_array_int, + adc_oeb => adc_oeb, + adc_otr => adc_otr, + drs_channel_id => drs_channel_internal, + drs_dwrite => dwrite, + drs_clk_en => drs_clk_en, + drs_read_s_cell => drs_read_s_cell, + drs_read_s_cell_ready => drs_read_s_cell_ready, + drs_s_cell_array => drs_s_cell_array + ); + U_5 : debouncer + GENERIC MAP ( + WIDTH => 17 + ) + PORT MAP ( + clk => CLK_50_internal, + trigger_in => dout, + trigger_out => trigger_out + ); + I_main_drs_pulser : drs_pulser + PORT MAP ( + CLK => CLK_25, + start_endless_mode => drs_clk_en, + start_read_stop_pos_mode => drs_read_s_cell, + SROUT_in_0 => SROUT_in_0, + SROUT_in_1 => SROUT_in_1, + SROUT_in_2 => SROUT_in_2, + SROUT_in_3 => SROUT_in_3, + stop_pos => drs_s_cell_array, + stop_pos_valid => drs_read_s_cell_ready, + RSRLOAD => RSRLOAD, + SRCLK => SRCLK + ); + I_main_memory_manager : memory_manager + GENERIC MAP ( + RAM_ADDR_WIDTH_64B => RAMADDRWIDTH64b, + RAM_ADDR_WIDTH_16B => RAMADDRWIDTH64b+2 + ) + PORT MAP ( + clk => CLK_25, + config_start => config_start, + ram_write_ready => ram_write_ready, + roi_array => roi_array, + ram_write_ea => ram_write_ea, + config_ready => config_ready, + config_started => config_started_mm, + roi_max => roi_max, + package_length => package_length, + wiz_ram_start_addr => wiz_ram_start_addr, + wiz_write_length => wiz_write_length, + wiz_number_of_channels => wiz_number_of_channels, + wiz_write_ea => wiz_write_ea, + wiz_write_header => wiz_write_header, + wiz_write_end => wiz_write_end, + wiz_busy => wiz_busy, + wiz_ack => wiz_ack, + ram_start_addr => ram_start_addr + ); + I_main_SPI_interface : spi_interface + PORT MAP ( + clk_50MHz => CLK_50_internal, + config_start => config_start_spi, + dac_array => dac_array, + config_ready => config_ready_spi, + config_started => config_started_spi, + dac_cs => dac_cs, + mosi => mosi, + sclk => sclk1, + sensor_array => sensor_array, + sensor_cs => sensor_cs, + sensor_ready => sensor_ready, + miso => sio + ); + I_main_ext_trigger : trigger_counter + PORT MAP ( + trigger_id => trigger_id, + trigger => trigger, + clk => CLK_25_PS_internal + ); + I_main_ethernet : w5300_modul + GENERIC MAP ( + RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2 + ) + PORT MAP ( + clk => CLK_50_internal, + wiz_reset => wiz_reset, + addr => wiz_addr, + data => wiz_data, + cs => wiz_cs, + wr => wiz_wr, + led => led, + rd => wiz_rd, + int => wiz_int, + write_length => wiz_write_length, + ram_start_addr => wiz_ram_start_addr, + ram_data => ram_data, + ram_addr => ram_addr, + data_valid => wiz_write_ea, + data_valid_ack => wiz_ack, + busy => wiz_busy, + write_header_flag => wiz_write_header, + write_end_flag => wiz_write_end, + fifo_channels => wiz_number_of_channels, + s_trigger => s_trigger, + new_config => new_config, + config_started => config_started, + config_addr => config_addr, + config_data => config_data, + config_wr_en => config_wr_en, + config_rd_en => config_rd_en, + config_busy => config_busy, + denable => denable, + dwrite_enable => dwrite_enable, + sclk_enable => sclk_enable + ); + + -- Implicit buffered output assignments + CLK_25_PS <= CLK_25_PS_internal; + CLK_50 <= CLK_50_internal; + +END struct; Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/memory_manager_beha.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/memory_manager_beha.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/memory_manager_beha.vhd (revision 9841) @@ -0,0 +1,289 @@ +-- +-- VHDL Architecture FACT_FAD_lib.memory_manager.beha +-- +-- Created: +-- by - kai.UNKNOWN (E5PCXX) +-- at - 14:33:25 02.03.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use ieee.STD_LOGIC_UNSIGNED.all; + +library FACT_FAD_lib; +use FACT_FAD_lib.fad_definitions.all; + +-- library UNISIM; +-- use UNISIM.VComponents.all; +-- USE IEEE.NUMERIC_STD.all; + +-- RAM_ADDR_WIDTH_64B is used for +-- output ram_start_addr + +-- RAM_ADDR_WIDTH_16B is used for +-- output wiz_ram_start_addr + + +ENTITY memory_manager IS + generic( + RAM_ADDR_WIDTH_64B : integer := 12; + RAM_ADDR_WIDTH_16B : integer := 14 + ); + PORT( + clk : IN std_logic; + config_start : IN std_logic; + ram_write_ready : IN std_logic; + roi_array : IN roi_array_type; + ram_write_ea : OUT std_logic := '0'; + config_ready, config_started : OUT std_logic := '0'; + roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); + package_length : OUT std_logic_vector (15 downto 0) := (others => '0'); + wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0'); + wiz_write_length : OUT std_logic_vector (16 downto 0) := (others => '0'); + wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0'); + wiz_write_ea : OUT std_logic := '0'; + wiz_write_header : OUT std_logic := '0'; + wiz_write_end : OUT std_logic := '0'; + wiz_busy : IN std_logic; + wiz_ack : IN std_logic; + ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') + ); + +-- Declarations + +END memory_manager ; + +-- +ARCHITECTURE beha OF memory_manager IS + +type state_mm_type is (MM_CONFIG, MAX_ROI, MAX_ROI1, MAX_ROI2, FIFO_CALC, RAM_CALC, RAM_CALC1, RAM_CALC2, MM_MAIN, MM_MAIN1); +signal state_mm : state_mm_type := MM_CONFIG; + +--type roi_array_type is array (0 to 35) of integer range 0 to 1024; +type roi_max_array_type is array (0 to 8) of integer range 0 to 1024; +type channel_size_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE; +type fifo_write_length_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE; +type fifo_channels_array_type is array (0 to 8) of integer range 0 to 9; +type fifo_package_size_ram_type is array (0 to 8) of integer range 0 to RAM_SIZE_16B; + +signal roi_max_array : roi_max_array_type := (others => 0); + +-- size of channel groups (16 bit) +signal channel_size : channel_size_type := (others => 0); +-- write length of packages (16 bit) +signal fifo_write_length : fifo_write_length_type := (others => 0); +-- number of channels per package +signal fifo_channels_array : fifo_channels_array_type := (others => 0); +-- size of packages in ram (16 bit) +signal fifo_package_size_ram : fifo_package_size_ram_type := (others => 0); +-- +signal event_size_ram : integer range 0 to RAM_SIZE_16B := 0; +signal event_size_ram_64b : integer range 0 to RAM_SIZE_64B := 0; +signal event_size : integer range 0 to RAM_SIZE_16B := 0; + +signal drs_id : integer range 0 to 4 := 0; +signal channel_id : integer range 0 to 9 := 0; +signal channel_index : integer range 0 to 9 := 0; +signal package_index : integer range 0 to 9 := 0; +signal number_of_packages : integer range 0 to 9 := 0; +signal max_events_ram, events_in_ram : integer range 0 to 2048; +signal event_start_addr : integer range 0 to (RAM_SIZE_64B - 1); +signal write_start_addr : integer range 0 to (RAM_SIZE_16B - 1); +signal event_ready_flag : std_logic := '0'; +signal wiz_ack_flag : std_logic := '0'; + +signal roi_index : integer range 0 to 45 := 0; +signal temp_roi : integer range 0 to 1024 := 0; + +BEGIN + + mm : process (clk) + begin + if rising_edge (clk) then + case state_mm is + + when MM_CONFIG => + if (config_start = '1') then + config_started <= '1'; + roi_max_array <= (others => 0); + channel_size <= (others => 0); + fifo_write_length <= (others => 0); + fifo_channels_array <= (others => 0); + event_size <= 0; + ram_write_ea <= '0'; + state_mm <= MAX_ROI; + end if; + + -- calculate max ROIs and channel sizes + when MAX_ROI => + roi_index <= (drs_id * 9) + channel_id; + state_mm <= MAX_ROI1; + when MAX_ROI1 => + temp_roi <= roi_array (roi_index); + state_mm <= MAX_ROI2; + when MAX_ROI2 => + if (channel_id < 9) then + if ( temp_roi > roi_max_array (channel_id)) then + roi_max_array (channel_id) <= temp_roi; + end if; + channel_size (channel_id) <= channel_size (channel_id) + temp_roi + 3; + drs_id <= drs_id + 1; + state_mm <= MAX_ROI; + if (drs_id = 3) then + drs_id <= 0; + channel_id <= channel_id + 1; + end if; + else + drs_id <= 0; + channel_id <= 0; + channel_size (0) <= channel_size (0) + PACKAGE_HEADER_LENGTH; + channel_size (8) <= channel_size (8) + PACKAGE_END_LENGTH; + state_mm <= FIFO_CALC; + end if; + + -- calculate number of channels that fit in FIFO + when FIFO_CALC => + if (channel_id < 9) then + if ((fifo_write_length (package_index) + channel_size (channel_id)) <= W5300_TX_FIFO_SIZE) then + fifo_write_length (package_index) <= fifo_write_length (package_index) + channel_size (channel_id); + fifo_channels_array (package_index) <= fifo_channels_array (package_index) + 1; + channel_id <= channel_id + 1; + event_size <= event_size + channel_size (channel_id); + else + package_index <= package_index + 1; + end if; + else + number_of_packages <= package_index + 1; + package_index <= 0; + channel_index <= 0; + channel_id <= 0; + fifo_package_size_ram <= (others => 0); + fifo_package_size_ram (0) <= PACKAGE_HEADER_LENGTH + 6; + event_size_ram <= 0; + event_size_ram_64b <= 0; + max_events_ram <= 0; + state_mm <= RAM_CALC; + end if; + + when RAM_CALC => + if (package_index < number_of_packages) then + if (channel_index < fifo_channels_array (package_index)) then + fifo_package_size_ram (package_index) <= fifo_package_size_ram (package_index) + ((roi_max_array (channel_id) + 3) * 4); + channel_index <= channel_index + 1; + channel_id <= channel_id + 1; + else + package_index <= package_index + 1; + event_size_ram <= event_size_ram + fifo_package_size_ram (package_index); + channel_index <= 0; + end if; + else + fifo_package_size_ram (package_index - 1) <= fifo_package_size_ram (package_index - 1) + 4; + event_size_ram <= event_size_ram + 4; -- Size of Event in RAM (16 Bit), + CRC + Endflag + 2 Spare + state_mm <= RAM_CALC1; + end if; + when RAM_CALC1 => + max_events_ram <= max_events_ram + 1; + if ((max_events_ram * event_size_ram) <= RAM_SIZE_16B) then + state_mm <= RAM_CALC1; + else + max_events_ram <= max_events_ram - 1; + state_mm <= RAM_CALC2; + end if; + when RAM_CALC2 => + event_size_ram_64b <= (event_size_ram / 4); + events_in_ram <= 0; + event_start_addr <= 0; + write_start_addr <= 0; + package_index <= 0; + channel_id <= 0; + ram_start_addr <= (others => '0'); + ram_write_ea <= '1'; + config_started <= '0'; + config_ready <= '1'; + package_length <= conv_std_logic_vector (event_size, 16); + for i in 0 to 8 loop + roi_max(i) <= conv_std_logic_vector(roi_max_array(i), 11); + end loop; + state_mm <= MM_MAIN; + + when MM_MAIN => + state_mm <= MM_MAIN1; + if ((ram_write_ready = '1') and (event_ready_flag = '0')) then + ram_write_ea <= '0'; + events_in_ram <= events_in_ram + 1; + if ((event_start_addr + event_size_ram_64b) < (RAM_SIZE_64B - event_size_ram_64b)) then + event_start_addr <= event_start_addr + event_size_ram_64b; + else + event_start_addr <= 0; + end if; + event_ready_flag <= '1'; + end if; + + + when MM_MAIN1 => + state_mm <= MM_MAIN; + if (config_start = '1') then + config_ready <= '0'; + if (events_in_ram = 0) then + state_mm <= MM_CONFIG; + end if; + end if; + if (event_ready_flag = '1') then + if (events_in_ram < max_events_ram) then + ram_write_ea <= '1'; + ram_start_addr <= conv_std_logic_vector(event_start_addr, RAM_ADDR_WIDTH_64B); + event_ready_flag <= '0'; + end if; + end if; + + if ((events_in_ram > 0) and (wiz_busy = '0')) then + if (package_index < number_of_packages) then + wiz_ram_start_addr <= conv_std_logic_vector(write_start_addr, RAM_ADDR_WIDTH_16B); + wiz_write_length <= conv_std_logic_vector(fifo_write_length (package_index), 17); + wiz_number_of_channels <= conv_std_logic_vector(fifo_channels_array (package_index), 4); + wiz_write_ea <= '1'; + wiz_ack_flag <= '0'; + if (package_index = 0) then + -- first package -> write header + wiz_write_header <= '1'; + else + wiz_write_header <= '0'; + end if; + if (package_index = (number_of_packages - 1)) then + -- last package -> write end-flag + wiz_write_end <= '1'; + else + wiz_write_end <= '0'; + end if; + else + events_in_ram <= events_in_ram - 1; + package_index <= 0; + end if; + end if; + + if ((wiz_ack = '1') and (wiz_ack_flag = '0')) then + wiz_ack_flag <= '1'; + wiz_write_ea <= '0'; + package_index <= package_index + 1; + if (package_index = (number_of_packages - 1)) then + -- next address + if ((write_start_addr + fifo_package_size_ram (package_index)) < (RAM_SIZE_16B - event_size_ram)) then + write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); + else + write_start_addr <= 0; + end if; + else + write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); + end if; + end if; -- wiz_ack + + end case; -- state_mm + end if; + end process mm; + + + +END ARCHITECTURE beha; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/memory_manager_beha.vhd.bak =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/memory_manager_beha.vhd.bak (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/memory_manager_beha.vhd.bak (revision 9841) @@ -0,0 +1,281 @@ +-- +-- VHDL Architecture FACT_FAD_lib.memory_manager.beha +-- +-- Created: +-- by - kai.UNKNOWN (E5PCXX) +-- at - 14:33:25 02.03.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use ieee.STD_LOGIC_UNSIGNED.all; + +library FACT_FAD_lib; +use FACT_FAD_lib.fad_definitions.all; + +-- library UNISIM; +-- use UNISIM.VComponents.all; +-- USE IEEE.NUMERIC_STD.all; + +-- RAM_ADDR_WIDTH_64B is used for +-- output ram_start_addr + +-- RAM_ADDR_WIDTH_16B is used for +-- output wiz_ram_start_addr + + +ENTITY memory_manager IS + generic( + RAM_ADDR_WIDTH_64B : integer := 12; + RAM_ADDR_WIDTH_16B : integer := 14 + ); + PORT( + clk : IN std_logic; + config_start : IN std_logic; + ram_write_ready : IN std_logic; + roi_array : IN roi_array_type; + ram_write_ea : OUT std_logic := '0'; + config_ready, config_started : OUT std_logic := '0'; + roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); + package_length : OUT std_logic_vector (15 downto 0) := (others => '0'); + wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0'); + wiz_write_length : OUT std_logic_vector (16 downto 0) := (others => '0'); + wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0'); + wiz_write_ea : OUT std_logic := '0'; + wiz_write_header : OUT std_logic := '0'; + wiz_write_end : OUT std_logic := '0'; + wiz_busy : IN std_logic; + ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') + ); + +-- Declarations + +END memory_manager ; + +-- +ARCHITECTURE beha OF memory_manager IS + +type state_mm_type is (MM_CONFIG, MAX_ROI, MAX_ROI1, MAX_ROI2, FIFO_CALC, RAM_CALC, RAM_CALC1, RAM_CALC2, MM_MAIN, MM_MAIN1); +signal state_mm : state_mm_type := MM_CONFIG; + +--type roi_array_type is array (0 to 35) of integer range 0 to 1024; +type roi_max_array_type is array (0 to 8) of integer range 0 to 1024; +type channel_size_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE; +type fifo_write_length_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE; +type fifo_channels_array_type is array (0 to 8) of integer range 0 to 9; +type fifo_package_size_ram_type is array (0 to 8) of integer range 0 to RAM_SIZE_16B; + +signal roi_max_array : roi_max_array_type := (others => 0); + +-- size of channel groups (16 bit) +signal channel_size : channel_size_type := (others => 0); +-- write length of packages (16 bit) +signal fifo_write_length : fifo_write_length_type := (others => 0); +-- number of channels per package +signal fifo_channels_array : fifo_channels_array_type := (others => 0); +-- size of packages in ram (16 bit) +signal fifo_package_size_ram : fifo_package_size_ram_type := (others => 0); +-- +signal event_size_ram : integer range 0 to RAM_SIZE_16B := 0; +signal event_size_ram_64b : integer range 0 to RAM_SIZE_64B := 0; +signal event_size : integer range 0 to RAM_SIZE_16B := 0; + +signal drs_id : integer range 0 to 4 := 0; +signal channel_id : integer range 0 to 9 := 0; +signal channel_index : integer range 0 to 9 := 0; +signal package_index : integer range 0 to 9 := 0; +signal number_of_packages : integer range 0 to 9 := 0; +signal max_events_ram, events_in_ram : integer range 0 to 2048; +signal event_start_addr : integer range 0 to (RAM_SIZE_64B - 1); +signal write_start_addr : integer range 0 to (RAM_SIZE_16B - 1); +signal event_ready_flag : std_logic := '0'; + +signal roi_index : integer range 0 to 45 := 0; +signal temp_roi : integer range 0 to 1024 := 0; + +BEGIN + + mm : process (clk) + begin + if rising_edge (clk) then + case state_mm is + + when MM_CONFIG => + if (config_start = '1') then + config_started <= '1'; + roi_max_array <= (others => 0); + channel_size <= (others => 0); + fifo_write_length <= (others => 0); + fifo_channels_array <= (others => 0); + event_size <= 0; + ram_write_ea <= '0'; + state_mm <= MAX_ROI; + end if; + + -- calculate max ROIs and channel sizes + when MAX_ROI => + roi_index <= (drs_id * 9) + channel_id; + state_mm <= MAX_ROI1; + when MAX_ROI1 => + temp_roi <= roi_array (roi_index); + state_mm <= MAX_ROI2; + when MAX_ROI2 => + if (channel_id < 9) then + if ( temp_roi > roi_max_array (channel_id)) then + roi_max_array (channel_id) <= temp_roi; + end if; + channel_size (channel_id) <= channel_size (channel_id) + temp_roi + 3; + drs_id <= drs_id + 1; + state_mm <= MAX_ROI; + if (drs_id = 3) then + drs_id <= 0; + channel_id <= channel_id + 1; + end if; + else + drs_id <= 0; + channel_id <= 0; + channel_size (0) <= channel_size (0) + PACKAGE_HEADER_LENGTH; + channel_size (8) <= channel_size (8) + PACKAGE_END_LENGTH; + state_mm <= FIFO_CALC; + end if; + + -- calculate number of channels that fit in FIFO + when FIFO_CALC => + if (channel_id < 9) then + if ((fifo_write_length (package_index) + channel_size (channel_id)) <= W5300_TX_FIFO_SIZE) then + fifo_write_length (package_index) <= fifo_write_length (package_index) + channel_size (channel_id); + fifo_channels_array (package_index) <= fifo_channels_array (package_index) + 1; + channel_id <= channel_id + 1; + event_size <= event_size + channel_size (channel_id); + else + package_index <= package_index + 1; + end if; + else + number_of_packages <= package_index + 1; + package_index <= 0; + channel_index <= 0; + channel_id <= 0; + fifo_package_size_ram <= (others => 0); + fifo_package_size_ram (0) <= PACKAGE_HEADER_LENGTH + 6; + event_size_ram <= 0; + event_size_ram_64b <= 0; + max_events_ram <= 0; + state_mm <= RAM_CALC; + end if; + + when RAM_CALC => + if (package_index < number_of_packages) then + if (channel_index < fifo_channels_array (package_index)) then + fifo_package_size_ram (package_index) <= fifo_package_size_ram (package_index) + ((roi_max_array (channel_id) + 3) * 4); + channel_index <= channel_index + 1; + channel_id <= channel_id + 1; + else + package_index <= package_index + 1; + event_size_ram <= event_size_ram + fifo_package_size_ram (package_index); + channel_index <= 0; + end if; + else + fifo_package_size_ram (package_index - 1) <= fifo_package_size_ram (package_index - 1) + 4; + event_size_ram <= event_size_ram + 4; -- Size of Event in RAM (16 Bit), + CRC + Endflag + 2 Spare + state_mm <= RAM_CALC1; + end if; + when RAM_CALC1 => + max_events_ram <= max_events_ram + 1; + if ((max_events_ram * event_size_ram) <= RAM_SIZE_16B) then + state_mm <= RAM_CALC1; + else + max_events_ram <= max_events_ram - 1; + state_mm <= RAM_CALC2; + end if; + when RAM_CALC2 => + event_size_ram_64b <= (event_size_ram / 4); + events_in_ram <= 0; + event_start_addr <= 0; + write_start_addr <= 0; + package_index <= 0; + channel_id <= 0; + ram_start_addr <= (others => '0'); + ram_write_ea <= '1'; + config_started <= '0'; + config_ready <= '1'; + package_length <= conv_std_logic_vector (event_size, 16); + for i in 0 to 8 loop + roi_max(i) <= conv_std_logic_vector(roi_max_array(i), 11); + end loop; + state_mm <= MM_MAIN; + + when MM_MAIN => + state_mm <= MM_MAIN1; + if ((ram_write_ready = '1') and (event_ready_flag = '0')) then + ram_write_ea <= '0'; + events_in_ram <= events_in_ram + 1; + if ((event_start_addr + event_size_ram_64b) < (RAM_SIZE_64B - event_size_ram_64b)) then + event_start_addr <= event_start_addr + event_size_ram_64b; + else + event_start_addr <= 0; + end if; + event_ready_flag <= '1'; + end if; + wiz_write_ea <= '0'; -- ????? + + when MM_MAIN1 => + state_mm <= MM_MAIN; + if (config_start = '1') then + config_ready <= '0'; + if (events_in_ram = 0) then + state_mm <= MM_CONFIG; + end if; + end if; + if (event_ready_flag = '1') then + if (events_in_ram < max_events_ram) then + ram_write_ea <= '1'; + -- ram_start_addr <= conv_std_logic_vector(event_start_addr, 12); + ram_start_addr <= conv_std_logic_vector(event_start_addr, RAM_ADDR_WIDTH_64B); + event_ready_flag <= '0'; + end if; + end if; + if ((events_in_ram > 0) and (wiz_busy = '0')) then + if (package_index < number_of_packages) then + -- wiz_ram_start_addr <= conv_std_logic_vector(write_start_addr, 14); + wiz_ram_start_addr <= conv_std_logic_vector(write_start_addr, RAM_ADDR_WIDTH_16B); + wiz_write_length <= conv_std_logic_vector(fifo_write_length (package_index), 17); + wiz_number_of_channels <= conv_std_logic_vector(fifo_channels_array (package_index), 4); + wiz_write_ea <= '1'; + package_index <= package_index + 1; + if (package_index = 0) then + -- first package -> write header + wiz_write_header <= '1'; + else + wiz_write_header <= '0'; + end if; + if (package_index = (number_of_packages - 1)) then + -- last package -> write end-flag + wiz_write_end <= '1'; + -- next address + if ((write_start_addr + event_size_ram + fifo_package_size_ram (package_index) ) < (RAM_SIZE_16B - event_size_ram)) then + --write_start_addr <= write_start_addr + event_size_ram; + write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); + else + write_start_addr <= 0; + end if; + else + write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); + wiz_write_end <= '0'; + end if; + else + events_in_ram <= events_in_ram - 1; + package_index <= 0; + end if; + end if; + + + end case; -- state_mm + end if; + end process mm; + + + +END ARCHITECTURE beha; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/spi_clock_gen_beha.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/spi_clock_gen_beha.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/spi_clock_gen_beha.vhd (revision 9841) @@ -0,0 +1,47 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_clock_generator.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 14:49:19 01.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY spi_clock_generator IS + GENERIC( + CLK_DIVIDER : integer := 25 --2 MHz @ 50 MHz + ); + PORT( + clk : IN std_logic; + sclk : OUT std_logic := '0' + ); +END spi_clock_generator ; + +ARCHITECTURE beha OF spi_clock_generator IS + +BEGIN + + spi_clk_proc: process (clk) + variable Z: integer range 0 to clk_divider - 1; + begin + if rising_edge(clk) then + if (Z < clk_divider - 1) then + Z := Z + 1; + else + Z := 0; + end if; + if (Z = 0) then + sclk <= '1'; + end if; + if (Z = clk_divider / 2) then + sclk <= '0'; + end if; + end if; + end process spi_clk_proc; + +END ARCHITECTURE beha; Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/spi_controller_beha.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/spi_controller_beha.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/spi_controller_beha.vhd (revision 9841) @@ -0,0 +1,117 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_controller.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 10:37:20 12.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY spi_controller IS + PORT( + clk : IN std_logic; + miso : INOUT std_logic := 'Z'; + mosi : OUT std_logic := '0'; + dac_id : IN std_logic_vector (2 DOWNTO 0); + sensor_id : IN std_logic_vector (1 downto 0); + data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + dac_cs : OUT std_logic := '1'; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0) := (others => '1'); + dac_start : IN std_logic; + dac_ready : OUT std_logic := '0'; + sensor_start : IN std_logic; + sensor_valid : OUT std_logic := '0' + ); +END spi_controller ; + +ARCHITECTURE beha OF spi_controller IS + + type TYPE_SPI_STATE is (SPI_IDLE, SPI_LOAD_DAC, SPI_LOAD_COMMAND, SPI_GET_TEMP); + + signal spi_state : TYPE_SPI_STATE := SPI_IDLE; + signal spi_cycle_cnt : integer range 0 to 25 := 0; + signal shift_reg : std_logic_vector (23 downto 0) := (others => '0'); + signal data_reg : std_logic_vector (15 downto 0) := (others => '0'); + +BEGIN + + spi_write_proc: process (clk) + begin + if falling_edge(clk) then + dac_cs <= '1'; + sensor_cs <= (others => '1'); + miso <= 'Z'; + mosi <= '0'; + data <= (others => 'Z'); + case spi_state is + when SPI_IDLE => + if (dac_start = '1') then + dac_ready <= '0'; + spi_state <= SPI_LOAD_COMMAND; + elsif (sensor_start = '1') then + sensor_valid <= '0'; + spi_state <= SPI_LOAD_COMMAND; + end if; + + when SPI_LOAD_COMMAND => + spi_cycle_cnt <= 0; + if (sensor_start = '1') then + shift_reg <= X"C1" & X"0000"; -- command: Temperature register read + spi_state <= SPI_GET_TEMP; + elsif (dac_start = '1') then + shift_reg <= "0011" & '0' & dac_id & data; + spi_state <= SPI_LOAD_DAC; + end if; + + -- start temperature sensor read + when SPI_GET_TEMP => + if (spi_cycle_cnt < 24) then -- must be on more cause MAX6662 provides data on falling edge + sensor_cs(conv_integer(sensor_id)) <= '0'; + sensor_valid <= '0'; + spi_cycle_cnt <= spi_cycle_cnt + 1; + if (spi_cycle_cnt < 9) then -- send data + miso <= shift_reg(23); + shift_reg <= shift_reg(22 downto 0) & shift_reg(23); + end if; + else + data <= data_reg; + sensor_valid <= '1'; + spi_state <= SPI_IDLE; + end if; + + -- start loading DACs + when SPI_LOAD_DAC => + dac_cs <= '0'; + if (spi_cycle_cnt < 24) then + mosi <= shift_reg(23); + shift_reg <= shift_reg(22 downto 0) & shift_reg(23); + dac_ready <= '0'; + spi_cycle_cnt <= spi_cycle_cnt + 1; + spi_state <= SPI_LOAD_DAC; + else + dac_cs <= '1'; + dac_ready <= '1'; + spi_state <= SPI_IDLE; + end if; + end case; + end if; + end process spi_write_proc; + + -- MAX6662 input must be read with rising edge + spi_read_proc: process (clk) + begin + if rising_edge(clk) then + if (spi_state = SPI_GET_TEMP and spi_cycle_cnt >= 9) then + data_reg(0) <= miso; + data_reg(15 downto 1) <= data_reg(14 downto 0); + end if; + end if; + end process spi_read_proc; + +END ARCHITECTURE beha; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/spi_distributor_beha.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/spi_distributor_beha.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/spi_distributor_beha.vhd (revision 9841) @@ -0,0 +1,150 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_distributor.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 09:24:21 23.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +ENTITY spi_distributor IS + +-- TEMP_MEASUREMENT_BEAT * clk ist the measurement period of the +-- Temperature measurement +-- e.g. 5*10**6 means every second + + GENERIC( + TEMP_MEASUREMENT_BEAT : integer := 5*10**6 + ); + + PORT( + clk : IN std_logic; -- 50MHz + config_start : IN std_logic; + config_ready, config_started : OUT std_logic := '0'; + sensor_valid : OUT std_logic := '0'; + dac_array : IN dac_array_type; + sensor_array : OUT sensor_array_type; + dac_config_start : OUT std_logic := '0'; + dac_config_ready : IN std_logic; + sensor_read_start : OUT std_logic := '0'; + sensor_read_valid : IN std_logic; + dac_id : OUT std_logic_vector(2 downto 0) := (others => '0'); + sensor_id : OUT std_logic_vector(1 downto 0) := (others => '0'); + data : INOUT std_logic_vector(15 downto 0) := (others => 'Z') + ); +END ENTITY spi_distributor; + +ARCHITECTURE beha OF spi_distributor IS + + type TYPE_SPI_DISTRIBUTION_STATE is (INIT, IDLE, READ_SENSOR, CONFIG_DAC); + + signal spi_distr_state : TYPE_SPI_DISTRIBUTION_STATE := INIT; + signal int_sensor_read_start : std_logic := '0'; + signal int_sensor_valid : std_logic := '0'; + signal int_sensor_array : sensor_array_type; + signal sensor_id_cnt : integer range 0 to 4 := 0; + signal dac_id_cnt : integer range 0 to 7 := 0; + + +BEGIN + + spi_distribute_proc: process (clk) + begin + + if rising_edge(clk) then + data <= (others => 'Z'); + case spi_distr_state is + when INIT => + data <= (others => 'Z'); + int_sensor_valid <= '0'; + spi_distr_state <= READ_SENSOR; + when IDLE => + if (int_sensor_valid = '1') then + sensor_array <= int_sensor_array; + sensor_valid <= '1'; + end if; + data <= (others => 'Z'); + -- start DAC configuration + if (config_start = '1' AND int_sensor_valid = '1') then + config_started <= '1'; + config_ready <= '0'; + dac_config_start <= '1'; + dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); + data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); + spi_distr_state <= CONFIG_DAC; + -- start temperature sensor reading + elsif (dac_config_ready <= '1' AND int_sensor_read_start = '1') then + int_sensor_valid <= '0'; + sensor_read_start <= '1'; + sensor_id <= conv_std_logic_vector(sensor_id_cnt, sensor_id'length); + spi_distr_state <= READ_SENSOR; + end if; + + -- sensor reading + when READ_SENSOR => + sensor_read_start <= '1'; + sensor_id <= conv_std_logic_vector(sensor_id_cnt, sensor_id'length); + if (sensor_read_valid = '1') then + int_sensor_array(sensor_id_cnt) <= conv_integer(data); + sensor_read_start <= '0'; + if (sensor_id_cnt < 3) then + sensor_id_cnt <= sensor_id_cnt + 1; + sensor_read_start <= '1'; + spi_distr_state <= READ_SENSOR; + else + sensor_id_cnt <= 0; + sensor_valid <= '0'; + int_sensor_valid <= '1'; + spi_distr_state <= IDLE; + end if; + end if; + + -- DAC configuration + when CONFIG_DAC => + dac_config_start <= '1'; + dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); + data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); + if (dac_config_ready = '1') then + dac_config_start <= '0'; + if (dac_id_cnt < 7) then + dac_id_cnt <= dac_id_cnt + 1; + dac_config_start <= '1'; + spi_distr_state <= CONFIG_DAC; + else + dac_id_cnt <= 0; + config_started <= '0'; + config_ready <= '1'; + spi_distr_state <= IDLE; + end if; + end if; + end case; + end if; + + end process spi_distribute_proc; + + sensor_tmr_proc: process (clk) + variable Z: integer range 0 to (TEMP_MEASUREMENT_BEAT - 1); + begin + if rising_edge(clk) then + int_sensor_read_start <= '0'; + if (Z < TEMP_MEASUREMENT_BEAT - 1) then + Z := Z + 1; + else + Z := 0; + end if; + if (Z = 0) then + int_sensor_read_start <= '1'; + end if; + end if; + end process sensor_tmr_proc; + + +END ARCHITECTURE beha; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/spi_interface_struct.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/spi_interface_struct.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/spi_interface_struct.vhd (revision 9841) @@ -0,0 +1,177 @@ +-- VHDL Entity FACT_FAD_lib.spi_interface.symbol +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 12:04:03 23.06.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +ENTITY spi_interface IS + PORT( + clk_50MHz : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + config_ready : OUT std_logic; + config_started : OUT std_logic := '0'; + dac_cs : OUT std_logic; + mosi : OUT std_logic := '0'; + sclk : OUT std_logic; + sensor_array : OUT sensor_array_type; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0); + sensor_ready : OUT std_logic; + miso : INOUT std_logic + ); + +-- Declarations + +END spi_interface ; + +-- +-- VHDL Architecture FACT_FAD_lib.spi_interface.struct +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 12:04:03 23.06.2010 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; +USE IEEE.NUMERIC_STD.ALL; + +LIBRARY FACT_FAD_lib; + +ARCHITECTURE struct OF spi_interface IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL dac_config_ready : std_logic; + SIGNAL dac_config_start : std_logic; + SIGNAL dac_id : std_logic_vector(2 DOWNTO 0); + SIGNAL data : std_logic_vector(15 DOWNTO 0); + SIGNAL sensor_id : std_logic_vector(1 DOWNTO 0); + SIGNAL sensor_start : std_logic; + SIGNAL sensor_valid : std_logic; + + -- Implicit buffer signal declarations + SIGNAL sclk_internal : std_logic; + + + -- Component Declarations + COMPONENT spi_clock_generator + GENERIC ( + CLK_DIVIDER : integer := 25 --2 MHz @ 50 MHz + ); + PORT ( + clk : IN std_logic; + sclk : OUT std_logic := '0' + ); + END COMPONENT; + COMPONENT spi_controller + PORT ( + clk : IN std_logic; + dac_id : IN std_logic_vector (2 DOWNTO 0); + dac_start : IN std_logic; + sensor_id : IN std_logic_vector (1 DOWNTO 0); + sensor_start : IN std_logic; + dac_cs : OUT std_logic := '1'; + dac_ready : OUT std_logic := '0'; + mosi : OUT std_logic := '0'; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0) := (others => '1'); + sensor_valid : OUT std_logic := '0'; + data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + miso : INOUT std_logic := 'Z' + ); + END COMPONENT; + COMPONENT spi_distributor + GENERIC ( + TEMP_MEASUREMENT_BEAT : integer := 5*10**6 + ); + PORT ( + clk : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + dac_config_ready : IN std_logic; + sensor_read_valid : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0'; + dac_config_start : OUT std_logic := '0'; + dac_id : OUT std_logic_vector (2 DOWNTO 0) := (others => '0'); + sensor_array : OUT sensor_array_type; + sensor_id : OUT std_logic_vector (1 DOWNTO 0) := (others => '0'); + sensor_read_start : OUT std_logic := '0'; + sensor_valid : OUT std_logic := '0'; + data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z') + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : spi_clock_generator USE ENTITY FACT_FAD_lib.spi_clock_generator; + FOR ALL : spi_controller USE ENTITY FACT_FAD_lib.spi_controller; + FOR ALL : spi_distributor USE ENTITY FACT_FAD_lib.spi_distributor; + -- pragma synthesis_on + + +BEGIN + + -- Instance port mappings. + I_spi_clkgen : spi_clock_generator + GENERIC MAP ( + CLK_DIVIDER => 25 --2 MHz @ 50 MHz + ) + PORT MAP ( + clk => clk_50MHz, + sclk => sclk_internal + ); + I_spi_controller : spi_controller + PORT MAP ( + clk => sclk_internal, + miso => miso, + mosi => mosi, + dac_id => dac_id, + sensor_id => sensor_id, + data => data, + dac_cs => dac_cs, + sensor_cs => sensor_cs, + dac_start => dac_config_start, + dac_ready => dac_config_ready, + sensor_start => sensor_start, + sensor_valid => sensor_valid + ); + I_spi_distributor : spi_distributor + GENERIC MAP ( + TEMP_MEASUREMENT_BEAT => 5*10**6 + ) + PORT MAP ( + clk => sclk_internal, + config_start => config_start, + config_ready => config_ready, + config_started => config_started, + sensor_valid => sensor_ready, + dac_array => dac_array, + sensor_array => sensor_array, + dac_config_start => dac_config_start, + dac_config_ready => dac_config_ready, + sensor_read_start => sensor_start, + sensor_read_valid => sensor_valid, + dac_id => dac_id, + sensor_id => sensor_id, + data => data + ); + + -- Implicit buffered output assignments + sclk <= sclk_internal; + +END struct; Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/trigger_counter_beha.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/trigger_counter_beha.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/trigger_counter_beha.vhd (revision 9841) @@ -0,0 +1,43 @@ +-- +-- VHDL Architecture FACT_FAD_TB_lib.trigger_counter.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 14:36:14 10.02.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +entity trigger_counter is + port( + trigger_id : out std_logic_vector(47 downto 0); + trigger : in std_logic; + clk : in std_logic + ); + +end entity trigger_counter; + +architecture beha of trigger_counter is + + signal temp_id : integer := 0; + +begin + + trigger_id <= X"AA55" & conv_std_logic_vector(temp_id, 32); + + trigger_incr_proc: process(clk) + begin + if rising_edge(clk) then + if (trigger = '1') then + temp_id <= temp_id + 1; + end if; + end if; + end process trigger_incr_proc; + +end architecture beha; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/trigger_shaper_beha.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/trigger_shaper_beha.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/trigger_shaper_beha.vhd (revision 9841) @@ -0,0 +1,51 @@ +-- +-- VHDL Architecture FACT_FAD_test_devices_lib.trigger_shaper.beha +-- +-- Created: +-- by - FPGA_Developer.UNKNOWN (EEPC8) +-- at - 11:59:20 28.01.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.NUMERIC_STD.all; + +entity trigger_shaper is + port( + trigger_in : in std_logic; + trigger_out : out std_logic; + clk : in std_logic; + rst : in std_logic + ); +end entity trigger_shaper; + +architecture beha of trigger_shaper is + +-- signal temp_trig : std_logic_vector(3 downto 0); + signal temp_trig : std_logic_vector(1 downto 0); + signal trigger_flag : std_logic; + signal temp_signal : std_logic; + +begin + + test_proc : process (clk, rst) + begin + if (rst = '1') then + trigger_out <= '0'; + trigger_flag <= '0'; + temp_signal <= '0'; + elsif rising_edge(clk) then +-- temp_trig <= temp_trig(2 downto 0) & trigger_in; +-- trigger_out <= not temp_trig(3) and temp_trig(2); + temp_trig <= temp_trig(0) & trigger_in; + temp_signal <= not temp_trig(1) and temp_trig(0); + trigger_out <= temp_signal and not trigger_flag; + if (temp_signal = '1') then + trigger_flag <= '1'; + end if; + end if; + end process test_proc; + +end architecture beha; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 9841) @@ -0,0 +1,818 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11:48:48 11/10/2009 +-- Design Name: +-- Module Name: w5300_modul - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library FACT_FAD_lib; +use FACT_FAD_lib.fad_definitions.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +ENTITY w5300_modul IS + generic( + RAM_ADDR_WIDTH : integer := 14 + ); + PORT( + clk : IN std_logic; + wiz_reset : OUT std_logic := '1'; + addr : OUT std_logic_vector (9 DOWNTO 0); + data : INOUT std_logic_vector (15 DOWNTO 0); + cs : OUT std_logic := '1'; + wr : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + rd : OUT std_logic := '1'; + int : IN std_logic; + write_length : IN std_logic_vector (16 DOWNTO 0); + ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + ram_data : IN std_logic_vector (15 DOWNTO 0); + ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + data_valid : IN std_logic; + data_valid_ack : OUT std_logic := '0'; + busy : OUT std_logic := '1'; + write_header_flag, write_end_flag : IN std_logic; + fifo_channels : IN std_logic_vector (3 downto 0); + s_trigger : OUT std_logic := '0'; + new_config : OUT std_logic := '0'; + config_started : in std_logic; + config_addr : out std_logic_vector (7 downto 0); + config_data : inout std_logic_vector (15 downto 0) := (others => 'Z'); + config_wr_en : out std_logic := '0'; + config_rd_en : out std_logic := '0'; + config_busy : in std_logic; + + + + denable : out std_logic := '0'; -- default domino wave off + dwrite_enable : out std_logic := '0'; -- default DWRITE low. + sclk_enable : out std_logic := '1' -- default DWRITE HIGH. + ); + +-- Declarations + +END w5300_modul ; + +architecture Behavioral of w5300_modul is + +type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, + INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, + SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, CHK_RECEIVED, READ_DATA); +type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, + WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3); +type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); +type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); +type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END); + +signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; + +signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0'); +signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0'); +signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0'); +signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + +signal state_init, next_state , next_state_tmp : state_init_type := RESET; +signal count : std_logic_vector (2 downto 0) := "000"; +signal state_write : state_write_type := WR_START; +signal state_interrupt_1 : state_interrupt_1_type := IR1_01; +signal state_interrupt_2 : state_interrupt_2_type := IR2_01; +signal state_read_data : state_read_data_type := RD_1; + +signal interrupt_ignore : std_logic := '1'; +signal int_flag : std_logic := '0'; +signal ram_access : std_logic := '0'; + +signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0'); +signal data_cnt : integer := 0; +signal drs_cnt : integer :=0; +signal channel_cnt : integer range 0 to 9 :=0; +signal socket_cnt : std_logic_vector (2 downto 0) := "000"; +signal roi_max : std_logic_vector (10 downto 0); +signal data_end : integer := 0; + +signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0'); +signal write_length_bytes : std_logic_vector (16 downto 0); + +signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0'); +signal chk_recv_cntr : integer range 0 to 10000 := 0; +signal rx_packets_cnt : std_logic_vector (15 downto 0); +signal next_packet_data : std_logic := '0'; +signal new_config_flag : std_logic := '0'; + +signal trigger_stop : std_logic := '1'; + +signal local_write_length : std_logic_vector (16 DOWNTO 0); +signal local_ram_start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); +signal local_ram_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0); +signal local_socket_nr : std_logic_vector (2 DOWNTO 0); +signal local_write_header_flag, local_write_end_flag : std_logic; +signal local_fifo_channels : std_logic_vector (3 downto 0); + +begin + + --synthesis translate_off + RST_TIME <= X"00120"; + --synthesis translate_on + + w5300_init_proc : process (clk, int) + begin + + if rising_edge (clk) then + + -- Interrupt low + if (int = '0') and (interrupt_ignore = '0') then + case state_interrupt_1 is + when IR1_01 => + int_flag <= '1'; + busy <= '1'; + state_interrupt_1 <= IR1_02; + when IR1_02 => + state_interrupt_1 <= IR1_03; + when IR1_03 => + state_init <= INTERRUPT; + socket_cnt <= "000"; + ram_access <= '0'; + zaehler <= X"00000"; + count <= "000"; + int_flag <= '0'; + interrupt_ignore <= '1'; + state_interrupt_1 <= IR1_04; + when others => + null; + end case; + end if; -- int = '0' + + if int_flag = '0' then + case state_init is + -- Interrupt + when INTERRUPT => + case state_interrupt_2 is + when IR2_01 => + par_addr <= W5300_IR; + state_init <= READ_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_02; + when IR2_02 => + if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt + state_interrupt_2 <= IR2_03; + else + socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then + state_interrupt_2 <= IR2_06; + else + state_interrupt_2 <= IR2_02; + end if; + end if; + when IR2_03 => + par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register + state_init <= READ_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_04; + when IR2_04 => + par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; + par_data <= data_read; -- clear Interrupts + state_init <= WRITE_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_05; + when IR2_05 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0010"; -- CLOSE + state_init <= WRITE_REG; + next_state <= INTERRUPT; + socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then + state_interrupt_2 <= IR2_06; + else + state_interrupt_2 <= IR2_01; + end if; + + when IR2_06 => + state_interrupt_1 <= IR1_01; + state_interrupt_2 <= IR2_01; + socket_cnt <= "000"; + state_init <= RESET; + end case; + + -- reset W5300 + when RESET => + zaehler <= zaehler + 1; + wiz_reset <= '0'; + led <= X"FF"; + if (zaehler >= X"00064") then -- wait 2µs + wiz_reset <= '1'; + end if; + if (zaehler = RST_TIME) then -- wait 10ms + zaehler <= X"00000"; + socket_cnt <= "000"; + count <= "000"; + ram_access <= '0'; + interrupt_ignore <= '0'; + rd <= '1'; + wr <= '1'; + cs <= '1'; + state_write <= WR_START; + state_init <= INIT; + end if; + + -- Init + when INIT => + par_addr <= W5300_MR; + par_data <= X"0000"; + state_init <= WRITE_REG; + next_state <= IM; + + -- Interrupt Mask + when IM => + par_addr <= W5300_IMR; + par_data <= X"00FF"; -- S0-S7 Interrupts + state_init <= WRITE_REG; + next_state <= MT; + + -- Memory Type + when MT => + par_addr <= W5300_MTYPER; + par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer + state_init <= WRITE_REG; + next_state <= STX; + + -- Socket TX Memory Size + when STX => + par_data <= X"0F0F"; -- 15K TX + + par_addr <= W5300_TMS01R; + state_init <=WRITE_REG; + next_state <= STX1; + when STX1 => + par_addr <= W5300_TMS23R; + state_init <=WRITE_REG; + next_state <= STX2; + when STX2 => + par_addr <= W5300_TMS45R; + state_init <=WRITE_REG; + next_state <= STX3; + when STX3 => + par_addr <= W5300_TMS67R; + state_init <=WRITE_REG; + next_state <= SRX; + + -- Socket RX Memory Size + when SRX => + par_data <= X"0101"; -- 1K RX + + par_addr <= W5300_RMS01R; + state_init <=WRITE_REG; + next_state <= SRX1; + when SRX1 => + par_addr <= W5300_RMS23R; + state_init <=WRITE_REG; + next_state <= SRX2; + when SRX2 => + par_addr <= W5300_RMS45R; + state_init <=WRITE_REG; + next_state <= SRX3; + when SRX3 => + par_addr <= W5300_RMS67R; + state_init <=WRITE_REG; + next_state <= MAC; + + -- MAC + when MAC => + par_addr <= W5300_SHAR; + par_data <= MAC_ADDRESS (0); + state_init <= WRITE_REG; + next_state <= MAC1; + when MAC1 => + par_addr <= W5300_SHAR + 2; + par_data <= MAC_ADDRESS (1); + state_init <= WRITE_REG; + next_state <= MAC2; + when MAC2 => + par_addr <= W5300_SHAR + 4; + par_data <= MAC_ADDRESS (2); + state_init <= WRITE_REG; + next_state <= GW; + + -- Gateway + when GW => + par_addr <= W5300_GAR; + par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8); + par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8); + state_init <= WRITE_REG; + next_state <= GW1; + when GW1 => + par_addr <= W5300_GAR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8); + par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8); + state_init <= WRITE_REG; + next_state <= SNM; + + -- Subnet Mask + when SNM => + par_addr <= W5300_SUBR; + par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8); + par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8); + state_init <= WRITE_REG; + next_state <= SNM1; + when SNM1 => + par_addr <= W5300_SUBR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8); + par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8); + state_init <= WRITE_REG; + next_state <= IP; + -- Own IP-Address + when IP => + par_addr <= W5300_SIPR; + par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8); + par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8); + state_init <= WRITE_REG; + next_state <= IP1; + when IP1 => + par_addr <= W5300_SIPR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8); + par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8); + state_init <= WRITE_REG; + next_state <= TIMEOUT; + when TIMEOUT => + par_addr <= W5300_RTR; + par_data <= X"07D0"; -- 0x07D0 = 200ms + state_init <= WRITE_REG; + next_state <= RETRY; + when RETRY => + par_addr <= W5300_RCR; + par_data <= X"0008"; + state_init <= WRITE_REG; + next_state <= SI; + + -- Socket Init + when SI => + par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC; + par_data <= X"0101"; -- ALIGN, TCP + state_init <= WRITE_REG; + next_state <= SI1; + -- Sx Interrupt Mask + when SI1 => + par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC; + par_data <= X"000A"; -- TIMEOUT, DISCON + state_init <= WRITE_REG; + next_state <= SI2; + when SI2 => + par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC; + par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16); + state_init <= WRITE_REG; + next_state <= SI3; + when SI3 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0001"; -- OPEN + state_init <= WRITE_REG; + next_state <= SI4; + when SI4 => + par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; + state_init <= READ_REG; + next_state <= SI5; + when SI5 => + if (data_read (7 downto 0) = X"13") then -- is open? + state_init <= SI6; + else + state_init <= SI4; + end if; + when SI6 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0002"; -- LISTEN + state_init <= WRITE_REG; + socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then + socket_cnt <= "000"; + next_state <= ESTABLISH; -- All Sockets open + else + next_state <= SI; -- Next Socket + end if; + -- End Socket Init + + when ESTABLISH => + par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; + state_init <= READ_REG; + next_state <= EST1; + when EST1 => + led <= data_read (7 downto 0); + case data_read (7 downto 0) is + when X"17" => -- established + if (socket_cnt = 7) then + socket_cnt <= "000"; + busy <= '0'; + state_init <= MAIN; + else + socket_cnt <= socket_cnt + 1; + state_init <= ESTABLISH; + end if; + when others => + state_init <= ESTABLISH; + end case; + + when CONFIG => + led <= X"F0"; + new_config <= '1'; + if (config_started = '1') then + led <= X"0F"; + new_config <= '0'; + busy <= '0'; + state_init <= MAIN; + end if; + + -- main "loop" + when MAIN => + if (trigger_stop = '1') then + s_trigger <= '0'; + end if; + if (chk_recv_cntr = 1000) then + chk_recv_cntr <= 0; + state_read_data <= RD_1; + state_init <= READ_DATA; + busy <= '1'; + else + busy <= '0'; + data_valid_ack <= '0'; + chk_recv_cntr <= chk_recv_cntr + 1; + if (data_valid = '1') then + data_valid_ack <= '1'; + local_write_length <= write_length; + local_ram_start_addr <= ram_start_addr; + local_ram_addr <= (others => '0'); + local_write_header_flag <= write_header_flag; + local_write_end_flag <= write_end_flag; + local_fifo_channels <= fifo_channels; + next_state <= MAIN; + state_init <= WRITE_DATA; + busy <= '1'; + end if; + end if; + + -- read data from socket 0 + when READ_DATA => + case state_read_data is + when RD_1 => + par_addr <= W5300_S0_RX_RSR; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_2; + when RD_2 => + socket_rx_received (31 downto 16) <= data_read; + par_addr <= W5300_S0_RX_RSR + X"2"; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_3; + when RD_3 => + socket_rx_received (15 downto 0) <= data_read; + state_read_data <= RD_4; + when RD_4 => + if (socket_rx_received (16 downto 0) > ('0' & X"000")) then + rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2 + state_read_data <= RD_5; + else + busy <= '0'; + state_init <= MAIN; + end if; + when RD_5 => + if (rx_packets_cnt > 0) then + rx_packets_cnt <= rx_packets_cnt - '1'; + par_addr <= W5300_S0_RX_FIFOR; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_6; + else + state_read_data <= RD_END; +-- if (new_config_flag = '1') then +-- new_config_flag <= '0'; +-- state_init <= CONFIG; +-- else +-- busy <= '0'; +-- state_init <= MAIN; +-- end if; + end if; + when RD_6 => + led <= data_read (15 downto 8); + -- read command + if (next_packet_data = '0') then + case data_read (15 downto 8) is + when CMD_TRIGGER => + trigger_stop <= '1'; + s_trigger <= '1'; + state_read_data <= RD_WAIT; + when CMD_DWRITE_RUN => + dwrite_enable <= '1'; + state_read_data <= RD_WAIT; + when CMD_DWRITE_STOP => + dwrite_enable <= '0'; + state_read_data <= RD_WAIT; + when CMD_SCLK_ON => + sclk_enable <= '1'; + state_read_data <= RD_WAIT; + when CMD_SCLK_OFF => + sclk_enable <= '0'; + state_read_data <= RD_WAIT; + when CMD_DENABLE => + denable <= '1'; + state_read_data <= RD_WAIT; + when CMD_DDISABLE => + denable <= '0'; + state_read_data <= RD_WAIT; + when CMD_TRIGGER_C => + trigger_stop <= '0'; + s_trigger <= '1'; + state_read_data <= RD_WAIT; + when CMD_TRIGGER_S => + trigger_stop <= '1'; + state_read_data <= RD_WAIT; + when CMD_WRITE => + next_packet_data <= '1'; + config_addr <= data_read (7 downto 0); + state_read_data <= RD_5; + when others => + state_read_data <= RD_5; + end case; + -- read data + else + if (config_busy = '0') then + config_data <= data_read; + config_wr_en <= '1'; + new_config_flag <= '1'; + next_packet_data <= '0'; + state_read_data <= RD_WAIT; + end if; + end if; + when RD_WAIT => + state_read_data <= RD_WAIT1; + when RD_WAIT1 => + config_data <= (others => 'Z'); + config_wr_en <= '0'; + state_read_data <= RD_5; + when RD_END => + par_addr <= W5300_S0_CR; + par_data <= X"0040"; -- RECV + state_init <= WRITE_REG; + if (new_config_flag = '1') then + new_config_flag <= '0'; + next_state <= CONFIG; + else +-- busy <= '0'; + next_state <= MAIN; + end if; + + end case; -- state_data_read + + + + when WRITE_DATA => + case state_write is + when WR_START => + if (local_write_header_flag = '1') then + ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ???? + end if; + state_write <= WR_WAIT1; + when WR_WAIT1 => + state_write <= WR_LENGTH; + when WR_LENGTH => + if (local_write_header_flag = '1') then + local_socket_nr <= ram_data (2 downto 0); + end if; + next_state_tmp <= next_state; + write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2) + data_cnt <= 0; + state_write <= WR_01; + -- Check FIFO Size + when WR_01 => + par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC; + state_init <= READ_REG; + next_state <= WRITE_DATA; + state_write <= WR_02; + when WR_02 => + socket_tx_free (31 downto 16) <= data_read; + par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2"; + state_init <= READ_REG; + next_state <= WRITE_DATA; + state_write <= WR_03; + when WR_03 => + socket_tx_free (15 downto 0) <= data_read; + state_write <= WR_04; + when WR_04 => + if (socket_tx_free (16 downto 0) < write_length_bytes) then + state_write <= WR_01; + else + if (local_write_header_flag = '1') then + state_write <= WR_FIFO; + else + state_write <= WR_ADC; + end if; + end if; + + -- Fill FIFO + + -- Write Header + when WR_FIFO => + ram_addr <= local_ram_start_addr + local_ram_addr; + state_write <= WR_FIFO1; + when WR_FIFO1 => + data_cnt <= data_cnt + 1; + if (data_cnt < PACKAGE_HEADER_LENGTH) then --??? + local_ram_addr <= local_ram_addr + 1; + if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words + local_ram_addr <= local_ram_addr + 2; + end if; + if (data_cnt = 9) then -- skip empty words + local_ram_addr <= local_ram_addr + 4; + end if; + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + ram_access <= '1'; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_FIFO; + else + state_write <= WR_ADC; + end if; + -- End Write Header + + -- Write ADC-Data + ---- Start... + when WR_ADC => + adc_data_addr <= local_ram_start_addr + local_ram_addr; + drs_cnt <= 0; + channel_cnt <= 1; + data_cnt <= 0; + roi_max <= (others => '0'); + data_end <= 3; + state_write <= WR_ADC1; + + ---- Write Channel + when WR_ADC1 => + -- read ROI and set end of Channel-Data + if (data_cnt = 3) then + data_end <= conv_integer (ram_data) + 3; + if (ram_data > roi_max) then + roi_max <= ram_data (10 downto 0); + end if; + end if; + ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4); + state_write <= WR_ADC2; + when WR_ADC2 => + if (data_cnt < data_end) then + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + ram_access <= '1'; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + data_cnt <= data_cnt + 1; + state_write <= WR_ADC1; + else + -- Next DRS + if (drs_cnt < 3) then + drs_cnt <= drs_cnt + 1; + data_cnt <= 0; + data_end <= 3; + state_write <= WR_ADC1; + else + -- Next Channel + if (channel_cnt < local_fifo_channels) then + channel_cnt <= channel_cnt + 1; + roi_max <= (others => '0'); + drs_cnt <= 0; + data_cnt <= 0; + data_end <= 3; + adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4); + state_write <= WR_ADC1; + else + -- Ready + if (local_write_end_flag = '1') then + state_write <= WR_ENDFLAG; + else + state_write <= WR_05; + end if; + end if; + end if; + end if; + -- End Write ADC-Data + + -- Write End Package Flag + when WR_ENDFLAG => + ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4); + state_write <= WR_ENDFLAG1; + when WR_ENDFLAG1 => + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + ram_access <= '1'; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_ENDFLAG2; + when WR_ENDFLAG2 => + ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1; + state_write <= WR_ENDFLAG3; + when WR_ENDFLAG3 => + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_05; + + -- End Write End Package Flag + + --Send FIFO + when WR_05 => + ram_access <= '0'; + par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC; + par_data <= (0 => write_length_bytes (16), others => '0'); + state_init <= WRITE_REG; + state_write <= WR_06; + when WR_06 => + par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2"; + par_data <= write_length_bytes (15 downto 0); + state_init <= WRITE_REG; + state_write <= WR_07; + when WR_07 => + par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC; + par_data <= X"0020"; -- Send + state_init <= WRITE_REG; + state_write <= WR_08; + when others => +-- busy <= '0'; + state_init <= next_state_tmp; + state_write <= WR_START; + end case; + -- End WRITE_DATA + + when READ_REG => + case count is + when "000" => + cs <= '0'; + rd <= '0'; + wr <= '1'; + data <= (others => 'Z'); -- !!!!!!!!!! + count <= "001"; + addr <= par_addr; + when "001" => + count <= "010"; + when "010" => + count <= "100"; + when "100" => + data_read <= data; + count <= "110"; + when "110" => + count <= "111"; + when "111" => + cs <= '1'; + rd <= '1'; + count <= "000"; + state_init <= next_state; + when others => + null; + end case; + + when WRITE_REG => + case count is + when "000" => + cs <= '0'; + wr <= '0'; + rd <= '1'; + addr <= par_addr; + if (ram_access = '1') then + data <= ram_data; + else + data <= par_data; + end if; + count <= "100"; + when "100" => + count <= "101"; + when "101" => + count <= "110"; + when "110" => + cs <= '1'; + wr <= '1'; + state_init <= next_state; + count <= "000"; + when others => + null; + end case; + + when others => + null; + end case; + end if; -- int_flag = '0' + + end if; -- rising_edge (clk) + + end process w5300_init_proc; + +end Behavioral; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd.bak =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd.bak (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd.bak (revision 9841) @@ -0,0 +1,812 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11:48:48 11/10/2009 +-- Design Name: +-- Module Name: w5300_modul - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library FACT_FAD_lib; +use FACT_FAD_lib.fad_definitions.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +ENTITY w5300_modul IS + generic( + RAM_ADDR_WIDTH : integer := 14 + ); + PORT( + clk : IN std_logic; + wiz_reset : OUT std_logic := '1'; + addr : OUT std_logic_vector (9 DOWNTO 0); + data : INOUT std_logic_vector (15 DOWNTO 0); + cs : OUT std_logic := '1'; + wr : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + rd : OUT std_logic := '1'; + int : IN std_logic; + write_length : IN std_logic_vector (16 DOWNTO 0); + ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + ram_data : IN std_logic_vector (15 DOWNTO 0); + ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + data_valid : IN std_logic; + data_valid_ack : OUT std_logic := '0'; + busy : OUT std_logic := '1'; + write_header_flag, write_end_flag : IN std_logic; + fifo_channels : IN std_logic_vector (3 downto 0); + s_trigger : OUT std_logic := '0'; + new_config : OUT std_logic := '0'; + config_started : in std_logic; + config_addr : out std_logic_vector (7 downto 0); + config_data : inout std_logic_vector (15 downto 0) := (others => 'Z'); + config_wr_en : out std_logic := '0'; + config_rd_en : out std_logic := '0'; + config_busy : in std_logic; + + + + denable : out std_logic := '0'; -- default domino wave off + dwrite_enable : out std_logic := '0'; -- default DWRITE low. + sclk_enable : out std_logic := '1' -- default DWRITE HIGH. + ); + +-- Declarations + +END w5300_modul ; + +architecture Behavioral of w5300_modul is + +type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, + INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, + SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, CHK_RECEIVED, READ_DATA); +type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, + WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3); +type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); +type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); +type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END); + +signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; + +signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0'); +signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0'); +signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0'); +signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + +signal state_init, next_state , next_state_tmp : state_init_type := RESET; +signal count : std_logic_vector (2 downto 0) := "000"; +signal state_write : state_write_type := WR_START; +signal state_interrupt_1 : state_interrupt_1_type := IR1_01; +signal state_interrupt_2 : state_interrupt_2_type := IR2_01; +signal state_read_data : state_read_data_type := RD_1; + +signal interrupt_ignore : std_logic := '1'; +signal int_flag : std_logic := '0'; +signal ram_access : std_logic := '0'; + +signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0'); +signal data_cnt : integer := 0; +signal drs_cnt : integer :=0; +signal channel_cnt : integer range 0 to 9 :=0; +signal socket_cnt : std_logic_vector (2 downto 0) := "000"; +signal roi_max : std_logic_vector (10 downto 0); +signal data_end : integer := 0; + +signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0'); +signal write_length_bytes : std_logic_vector (16 downto 0); + +signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0'); +signal chk_recv_cntr : integer range 0 to 10000 := 0; +signal rx_packets_cnt : std_logic_vector (15 downto 0); +signal next_packet_data : std_logic := '0'; +signal new_config_flag : std_logic := '0'; + +signal trigger_stop : std_logic := '1'; + +signal local_write_length : std_logic_vector (16 DOWNTO 0); +signal local_ram_start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); +signal local_ram_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0); +signal local_socket_nr : std_logic_vector (2 DOWNTO 0); +signal local_write_header_flag, local_write_end_flag : std_logic; +signal local_fifo_channels : std_logic_vector (3 downto 0); + +begin + + --synthesis translate_off + RST_TIME <= X"00120"; + --synthesis translate_on + + w5300_init_proc : process (clk, int) + begin + + if rising_edge (clk) then + + -- Interrupt low + if (int = '0') and (interrupt_ignore = '0') then + case state_interrupt_1 is + when IR1_01 => + int_flag <= '1'; + busy <= '1'; + state_interrupt_1 <= IR1_02; + when IR1_02 => + state_interrupt_1 <= IR1_03; + when IR1_03 => + state_init <= INTERRUPT; + socket_cnt <= "000"; + ram_access <= '0'; + zaehler <= X"00000"; + count <= "000"; + int_flag <= '0'; + interrupt_ignore <= '1'; + state_interrupt_1 <= IR1_04; + when others => + null; + end case; + end if; -- int = '0' + + if int_flag = '0' then + case state_init is + -- Interrupt + when INTERRUPT => + case state_interrupt_2 is + when IR2_01 => + par_addr <= W5300_IR; + state_init <= READ_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_02; + when IR2_02 => + if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt + state_interrupt_2 <= IR2_03; + else + socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then + state_interrupt_2 <= IR2_06; + else + state_interrupt_2 <= IR2_02; + end if; + end if; + when IR2_03 => + par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register + state_init <= READ_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_04; + when IR2_04 => + par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; + par_data <= data_read; -- clear Interrupts + state_init <= WRITE_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_05; + when IR2_05 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0010"; -- CLOSE + state_init <= WRITE_REG; + next_state <= INTERRUPT; + socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then + state_interrupt_2 <= IR2_06; + else + state_interrupt_2 <= IR2_01; + end if; + + when IR2_06 => + state_interrupt_1 <= IR1_01; + state_interrupt_2 <= IR2_01; + socket_cnt <= "000"; + state_init <= RESET; + end case; + + -- reset W5300 + when RESET => + zaehler <= zaehler + 1; + wiz_reset <= '0'; + led <= X"FF"; + if (zaehler >= X"00064") then -- wait 2µs + wiz_reset <= '1'; + end if; + if (zaehler = RST_TIME) then -- wait 10ms + zaehler <= X"00000"; + socket_cnt <= "000"; + count <= "000"; + ram_access <= '0'; + interrupt_ignore <= '0'; + rd <= '1'; + wr <= '1'; + cs <= '1'; + state_write <= WR_START; + state_init <= INIT; + end if; + + -- Init + when INIT => + par_addr <= W5300_MR; + par_data <= X"0000"; + state_init <= WRITE_REG; + next_state <= IM; + + -- Interrupt Mask + when IM => + par_addr <= W5300_IMR; + par_data <= X"00FF"; -- S0-S7 Interrupts + state_init <= WRITE_REG; + next_state <= MT; + + -- Memory Type + when MT => + par_addr <= W5300_MTYPER; + par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer + state_init <= WRITE_REG; + next_state <= STX; + + -- Socket TX Memory Size + when STX => + par_data <= X"0F0F"; -- 15K TX + + par_addr <= W5300_TMS01R; + state_init <=WRITE_REG; + next_state <= STX1; + when STX1 => + par_addr <= W5300_TMS23R; + state_init <=WRITE_REG; + next_state <= STX2; + when STX2 => + par_addr <= W5300_TMS45R; + state_init <=WRITE_REG; + next_state <= STX3; + when STX3 => + par_addr <= W5300_TMS67R; + state_init <=WRITE_REG; + next_state <= SRX; + + -- Socket RX Memory Size + when SRX => + par_data <= X"0101"; -- 1K RX + + par_addr <= W5300_RMS01R; + state_init <=WRITE_REG; + next_state <= SRX1; + when SRX1 => + par_addr <= W5300_RMS23R; + state_init <=WRITE_REG; + next_state <= SRX2; + when SRX2 => + par_addr <= W5300_RMS45R; + state_init <=WRITE_REG; + next_state <= SRX3; + when SRX3 => + par_addr <= W5300_RMS67R; + state_init <=WRITE_REG; + next_state <= MAC; + + -- MAC + when MAC => + par_addr <= W5300_SHAR; + par_data <= MAC_ADDRESS (0); + state_init <= WRITE_REG; + next_state <= MAC1; + when MAC1 => + par_addr <= W5300_SHAR + 2; + par_data <= MAC_ADDRESS (1); + state_init <= WRITE_REG; + next_state <= MAC2; + when MAC2 => + par_addr <= W5300_SHAR + 4; + par_data <= MAC_ADDRESS (2); + state_init <= WRITE_REG; + next_state <= GW; + + -- Gateway + when GW => + par_addr <= W5300_GAR; + par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8); + par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8); + state_init <= WRITE_REG; + next_state <= GW1; + when GW1 => + par_addr <= W5300_GAR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8); + par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8); + state_init <= WRITE_REG; + next_state <= SNM; + + -- Subnet Mask + when SNM => + par_addr <= W5300_SUBR; + par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8); + par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8); + state_init <= WRITE_REG; + next_state <= SNM1; + when SNM1 => + par_addr <= W5300_SUBR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8); + par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8); + state_init <= WRITE_REG; + next_state <= IP; + -- Own IP-Address + when IP => + par_addr <= W5300_SIPR; + par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8); + par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8); + state_init <= WRITE_REG; + next_state <= IP1; + when IP1 => + par_addr <= W5300_SIPR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8); + par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8); + state_init <= WRITE_REG; + next_state <= TIMEOUT; + when TIMEOUT => + par_addr <= W5300_RTR; + par_data <= X"07D0"; -- 0x07D0 = 200ms + state_init <= WRITE_REG; + next_state <= RETRY; + when RETRY => + par_addr <= W5300_RCR; + par_data <= X"0008"; + state_init <= WRITE_REG; + next_state <= SI; + + -- Socket Init + when SI => + par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC; + par_data <= X"0101"; -- ALIGN, TCP + state_init <= WRITE_REG; + next_state <= SI1; + -- Sx Interrupt Mask + when SI1 => + par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC; + par_data <= X"000A"; -- TIMEOUT, DISCON + state_init <= WRITE_REG; + next_state <= SI2; + when SI2 => + par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC; + par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16); + state_init <= WRITE_REG; + next_state <= SI3; + when SI3 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0001"; -- OPEN + state_init <= WRITE_REG; + next_state <= SI4; + when SI4 => + par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; + state_init <= READ_REG; + next_state <= SI5; + when SI5 => + if (data_read (7 downto 0) = X"13") then -- is open? + state_init <= SI6; + else + state_init <= SI4; + end if; + when SI6 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0002"; -- LISTEN + state_init <= WRITE_REG; + socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then + socket_cnt <= "000"; + next_state <= ESTABLISH; -- All Sockets open + else + next_state <= SI; -- Next Socket + end if; + -- End Socket Init + + when ESTABLISH => + par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; + state_init <= READ_REG; + next_state <= EST1; + when EST1 => + led <= data_read (7 downto 0); + case data_read (7 downto 0) is + when X"17" => -- established + if (socket_cnt = 7) then + socket_cnt <= "000"; + busy <= '0'; + state_init <= MAIN; + else + socket_cnt <= socket_cnt + 1; + state_init <= ESTABLISH; + end if; + when others => + state_init <= ESTABLISH; + end case; + + when CONFIG => + led <= X"F0"; + new_config <= '1'; + if (config_started = '1') then + led <= X"0F"; + new_config <= '0'; + busy <= '0'; + state_init <= MAIN; + end if; + + -- main "loop" + when MAIN => + if (trigger_stop = '1') then + s_trigger <= '0'; + end if; + if (chk_recv_cntr = 1000) then + chk_recv_cntr <= 0; + state_read_data <= RD_1; + state_init <= READ_DATA; + busy <= '1'; + else + busy <= '0'; + data_valid_ack <= '0'; + chk_recv_cntr <= chk_recv_cntr + 1; + if (data_valid = '1') then + data_valid_ack <= '1'; + local_write_length <= write_length; + local_ram_start_addr <= ram_start_addr; + local_ram_addr <= (others => '0'); + local_write_header_flag <= write_header_flag; + local_write_end_flag <= write_end_flag; + local_fifo_channels <= fifo_channels; + next_state <= MAIN; + state_init <= WRITE_DATA; + busy <= '1'; + end if; + end if; + + -- read data from socket 0 + when READ_DATA => + case state_read_data is + when RD_1 => + par_addr <= W5300_S0_RX_RSR; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_2; + when RD_2 => + socket_rx_received (31 downto 16) <= data_read; + par_addr <= W5300_S0_RX_RSR + X"2"; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_3; + when RD_3 => + socket_rx_received (15 downto 0) <= data_read; + state_read_data <= RD_4; + when RD_4 => + if (socket_rx_received (16 downto 0) > ('0' & X"000")) then + rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2 + state_read_data <= RD_5; + else + busy <= '0'; + state_init <= MAIN; + end if; + when RD_5 => + if (rx_packets_cnt > 0) then + rx_packets_cnt <= rx_packets_cnt - '1'; + par_addr <= W5300_S0_RX_FIFOR; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_6; + else + state_read_data <= RD_END; +-- if (new_config_flag = '1') then +-- new_config_flag <= '0'; +-- state_init <= CONFIG; +-- else +-- busy <= '0'; +-- state_init <= MAIN; +-- end if; + end if; + when RD_6 => + led <= data_read (15 downto 8); + -- read command + if (next_packet_data = '0') then + case data_read (15 downto 8) is + when CMD_TRIGGER => + trigger_stop <= '1'; + s_trigger <= '1'; + state_read_data <= RD_WAIT; + when CMD_DWRITE_RUN => + dwrite_enable <= '1'; + state_read_data <= RD_WAIT; + when CMD_DWRITE_STOP => + dwrite_enable <= '0'; + state_read_data <= RD_WAIT; + when CMD_DENABLE => + denable <= '1'; + state_read_data <= RD_WAIT; + when CMD_DDISABLE => + denable <= '0'; + state_read_data <= RD_WAIT; + when CMD_TRIGGER_C => + trigger_stop <= '0'; + s_trigger <= '1'; + state_read_data <= RD_WAIT; + when CMD_TRIGGER_S => + trigger_stop <= '1'; + state_read_data <= RD_WAIT; + when CMD_WRITE => + next_packet_data <= '1'; + config_addr <= data_read (7 downto 0); + state_read_data <= RD_5; + when others => + state_read_data <= RD_5; + end case; + -- read data + else + if (config_busy = '0') then + config_data <= data_read; + config_wr_en <= '1'; + new_config_flag <= '1'; + next_packet_data <= '0'; + state_read_data <= RD_WAIT; + end if; + end if; + when RD_WAIT => + state_read_data <= RD_WAIT1; + when RD_WAIT1 => + config_data <= (others => 'Z'); + config_wr_en <= '0'; + state_read_data <= RD_5; + when RD_END => + par_addr <= W5300_S0_CR; + par_data <= X"0040"; -- RECV + state_init <= WRITE_REG; + if (new_config_flag = '1') then + new_config_flag <= '0'; + next_state <= CONFIG; + else +-- busy <= '0'; + next_state <= MAIN; + end if; + + end case; -- state_data_read + + + + when WRITE_DATA => + case state_write is + when WR_START => + if (local_write_header_flag = '1') then + ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ???? + end if; + state_write <= WR_WAIT1; + when WR_WAIT1 => + state_write <= WR_LENGTH; + when WR_LENGTH => + if (local_write_header_flag = '1') then + local_socket_nr <= ram_data (2 downto 0); + end if; + next_state_tmp <= next_state; + write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2) + data_cnt <= 0; + state_write <= WR_01; + -- Check FIFO Size + when WR_01 => + par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC; + state_init <= READ_REG; + next_state <= WRITE_DATA; + state_write <= WR_02; + when WR_02 => + socket_tx_free (31 downto 16) <= data_read; + par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2"; + state_init <= READ_REG; + next_state <= WRITE_DATA; + state_write <= WR_03; + when WR_03 => + socket_tx_free (15 downto 0) <= data_read; + state_write <= WR_04; + when WR_04 => + if (socket_tx_free (16 downto 0) < write_length_bytes) then + state_write <= WR_01; + else + if (local_write_header_flag = '1') then + state_write <= WR_FIFO; + else + state_write <= WR_ADC; + end if; + end if; + + -- Fill FIFO + + -- Write Header + when WR_FIFO => + ram_addr <= local_ram_start_addr + local_ram_addr; + state_write <= WR_FIFO1; + when WR_FIFO1 => + data_cnt <= data_cnt + 1; + if (data_cnt < PACKAGE_HEADER_LENGTH) then --??? + local_ram_addr <= local_ram_addr + 1; + if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words + local_ram_addr <= local_ram_addr + 2; + end if; + if (data_cnt = 9) then -- skip empty words + local_ram_addr <= local_ram_addr + 4; + end if; + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + ram_access <= '1'; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_FIFO; + else + state_write <= WR_ADC; + end if; + -- End Write Header + + -- Write ADC-Data + ---- Start... + when WR_ADC => + adc_data_addr <= local_ram_start_addr + local_ram_addr; + drs_cnt <= 0; + channel_cnt <= 1; + data_cnt <= 0; + roi_max <= (others => '0'); + data_end <= 3; + state_write <= WR_ADC1; + + ---- Write Channel + when WR_ADC1 => + -- read ROI and set end of Channel-Data + if (data_cnt = 3) then + data_end <= conv_integer (ram_data) + 3; + if (ram_data > roi_max) then + roi_max <= ram_data (10 downto 0); + end if; + end if; + ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4); + state_write <= WR_ADC2; + when WR_ADC2 => + if (data_cnt < data_end) then + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + ram_access <= '1'; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + data_cnt <= data_cnt + 1; + state_write <= WR_ADC1; + else + -- Next DRS + if (drs_cnt < 3) then + drs_cnt <= drs_cnt + 1; + data_cnt <= 0; + data_end <= 3; + state_write <= WR_ADC1; + else + -- Next Channel + if (channel_cnt < local_fifo_channels) then + channel_cnt <= channel_cnt + 1; + roi_max <= (others => '0'); + drs_cnt <= 0; + data_cnt <= 0; + data_end <= 3; + adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4); + state_write <= WR_ADC1; + else + -- Ready + if (local_write_end_flag = '1') then + state_write <= WR_ENDFLAG; + else + state_write <= WR_05; + end if; + end if; + end if; + end if; + -- End Write ADC-Data + + -- Write End Package Flag + when WR_ENDFLAG => + ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4); + state_write <= WR_ENDFLAG1; + when WR_ENDFLAG1 => + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + ram_access <= '1'; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_ENDFLAG2; + when WR_ENDFLAG2 => + ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1; + state_write <= WR_ENDFLAG3; + when WR_ENDFLAG3 => + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_05; + + -- End Write End Package Flag + + --Send FIFO + when WR_05 => + ram_access <= '0'; + par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC; + par_data <= (0 => write_length_bytes (16), others => '0'); + state_init <= WRITE_REG; + state_write <= WR_06; + when WR_06 => + par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2"; + par_data <= write_length_bytes (15 downto 0); + state_init <= WRITE_REG; + state_write <= WR_07; + when WR_07 => + par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC; + par_data <= X"0020"; -- Send + state_init <= WRITE_REG; + state_write <= WR_08; + when others => +-- busy <= '0'; + state_init <= next_state_tmp; + state_write <= WR_START; + end case; + -- End WRITE_DATA + + when READ_REG => + case count is + when "000" => + cs <= '0'; + rd <= '0'; + wr <= '1'; + data <= (others => 'Z'); -- !!!!!!!!!! + count <= "001"; + addr <= par_addr; + when "001" => + count <= "010"; + when "010" => + count <= "100"; + when "100" => + data_read <= data; + count <= "110"; + when "110" => + count <= "111"; + when "111" => + cs <= '1'; + rd <= '1'; + count <= "000"; + state_init <= next_state; + when others => + null; + end case; + + when WRITE_REG => + case count is + when "000" => + cs <= '0'; + wr <= '0'; + rd <= '1'; + addr <= par_addr; + if (ram_access = '1') then + data <= ram_data; + else + data <= par_data; + end if; + count <= "100"; + when "100" => + count <= "101"; + when "101" => + count <= "110"; + when "110" => + cs <= '1'; + wr <= '1'; + state_init <= next_state; + count <= "000"; + when others => + null; + end case; + + when others => + null; + end case; + end if; -- int_flag = '0' + + end if; -- rising_edge (clk) + + end process w5300_init_proc; + +end Behavioral; + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Coregen/DCM_25MHz_38nsPS.xaw =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Coregen/DCM_25MHz_38nsPS.xaw (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Coregen/DCM_25MHz_38nsPS.xaw (revision 9841) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$90x4>7<9>1:<#?!02:853!oK92;>6?W1:00?724:28>=6:9;52-45603HXHDZGU169BVR\XGGFRSNO\C@FJJBYDDB;37L\XZ^MMH\YDDBCESHV[ESLBH43GU_SUDBAWPV@NJ@ZBA[VGDHHo4ARQLGZQN\Al0MZTPCMIAQCR^XL;::6OXZ^AOOGSA\PZN=R@@EEKW56=F_SUH@FQ@UURVPZR^XLi0MZTPFMMTP\VB02K\VR^NRUf8ER\X[PD_DYA@L59AKQN33K_MK8k4C;^GKNSJMw;WJ]IN_E|2XIILIEOu=QZjmq^`kwc`mgUM\JOPDdtfhjvbzUid~hijn]rqkocd|UNHAR<:MIx\7=htXZ$smz:4CMI3<>EKC9UIYKk4CMI3[GSAOVCE_Y64CMI3[JSS>2IGG<6?6:AOO717=2IGG?V7;BNH6]7?8<1H@F7?5:AOOAPd3JF@H[QKIWKGA0=DDBLI46MCKG@\MK34CMIJJZOE]OMTEC][f:AOOLHXAK_MKRAZT99@HNOIW@Dh7NBDIO]SAWOHLl1H@FGA_RP@[Q_WM880OAE@UU]SLDUBWZBBJYm4CMI\B@CCJHI@56M@MLKWP@B03JXNMYKK6:F@IZUWj2NHAR]__HLPPa=CMZAN[ROKJTQW57=CNZUM^H_ZEOAZ[HICM:1O@A?=;ENO[CTBY\OEOTQBOEG6?AUTMG;>7I[[Y^AZGICXKFXYINZFOO58@ZPFD\O37HV[ESLBHd=AIJ^D^TQEF49EEIUB12LIS^AZRBG`?CCBLKKHGRLZF89EMKYRF@^X96HFXDF;?CIR\VY_^l5IOTV\QKOS[h1MCXZPV@NVA4=N=2CIYKI7;HLWAWHFD8;0FDZ[ES]JJUSSW]S[I;5COBIF@d=KGJANHRAZT29OKR5HB\^EYG95AOOG2?J>VNF^COXE64PSKNP\VB991[^B^PPHLJWDESA_O>7]]LLJ48TVBHFL>0\^KA8:RPMKECMJ90^^Z9;SQW[LHe3ZCLIUZJROCO2>UNFNFNo6][ASVVTZQFA]<0_YO[UR31?V_T\LGT_T@LHSMMKPU43]E[86Z]UD:8QVCXJ\LL56[\E^@VBBU23_CN[^ceVGjfb|Yesqjkk773QnfS@gaosTfvvohf<1P<7>R5:Y3>2[33hx|v>5kcl;8twcdazcdbo5yesqjkk&6&9>0zejcf:z`7v178h'?jj:74|BCt64=1;;5rS2f93f<0n3;8>o:j9;371c6i1<7?51zQ0a?1d2>l1=>=}T;l028>>><5m7183>5<421q/m79k;%3`>=6<,8n14<5+1d84a>"0=380n9>50;30>5<7s-<86>h4$c81f>"d2?i0(h4=2:&e>74<,8:1>;5+10816>"6:3?n7)?<:7a8 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/firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Synthesis/Constraints/DCM_25MHz_38nsPS_arwz.ucf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Synthesis/Constraints/DCM_25MHz_38nsPS_arwz.ucf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Synthesis/Constraints/DCM_25MHz_38nsPS_arwz.ucf (revision 9841) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = 1X; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 1; +INST DCM_SP_INST CLKFX_MULTIPLY = 4; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 40.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = FIXED; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 243; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Synthesis/Constraints/DCM_25MHz_noPS_arwz.ucf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Synthesis/Constraints/DCM_25MHz_noPS_arwz.ucf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_38nsPS_BEHAVIORAL.vhd.info/Synthesis/Constraints/DCM_25MHz_noPS_arwz.ucf (revision 9841) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = 1X; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 1; +INST DCM_SP_INST CLKFX_MULTIPLY = 4; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 20.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_noPS_BEHAVIORAL.vhd.info/Coregen/DCM_25MHz_noPS.xaw =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_noPS_BEHAVIORAL.vhd.info/Coregen/DCM_25MHz_noPS.xaw (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/DCM_25MHz_noPS_BEHAVIORAL.vhd.info/Coregen/DCM_25MHz_noPS.xaw (revision 9841) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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3?=?110e;j50;&5e?>63-<26:64;h6`>5<#>h03=6*99;5;?>i5>3:1(;o5809'2f<002.:h7<;;%3f>05<3f8n6=4+6`8;5>=h:h0;6)8n:938?j4e290/:l471:9l6c<72-i5l3:1(;o58098k65=83.=m76>;%4`>2><,8i1>954o2694?"1i32:76a85;29 3g=0;1/:5488:9l1c<72-5<#>h03=65rb2f94?4=83:p(;l5589j1=<72-207pl=8;296?6=8r.=n7<;;h7;>5<#>h03=6*9c;5;?>i1=3:1(;o5809'2f<0021vn>850;094?6|,?h1>95f5983>!0f21;0(;m57998k33=83.=m76>;%4`>2><3ty8o7>52z?73?5f349o6;;4$0`97`=z{:81<7b;0:?xu5?3:1>v3;7;05?84?2<20q~=::1818202:901>85599~w6`=83;p1>j5599'37<202wx?44?:0y>73<1=2.<>78:;|q0a?6=8r.<>78:;|q1=?6=8r.<>78:;|m6<<728qvb?o50;3xyk4e290:wp`=c;295~{i:m0;6{|l04?6=9rwvqpNOCz1:>d15:oknqMNM{1CDU}zHI Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25.ctr =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25.ctr (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25.ctr (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700a +# set_package fg484 +# set_speed -4 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25.sdc =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25.sdc (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25.sdc (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700a +# set_package fg484 +# set_speed -4 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25_arwz.ucf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25_arwz.ucf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_50_to_25_BEHAVIORAL.vhd.info/Synthesis/Constraints/dcm_50_to_25_arwz.ucf (revision 9841) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = 1X; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 5; +INST DCM_SP_INST CLKFX_MULTIPLY = 2; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 20.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_ps_38ns_BEHAVIORAL.vhd.info/Coregen/dcm_ps_38ns.xaw =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_ps_38ns_BEHAVIORAL.vhd.info/Coregen/dcm_ps_38ns.xaw (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dcm_ps_38ns_BEHAVIORAL.vhd.info/Coregen/dcm_ps_38ns.xaw (revision 9841) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 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+) +(Line +uid 499,0 +sl 0 +ro 90 +xt "111000,74000,111500,74000" +pts [ +"111500,74000" +"111000,74000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 500,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 501,0 +va (VaSet +) +xt "114000,73500,116800,74500" +st "W_INT" +blo "114000,74300" +tm "WireNameMgr" +) +) +) +*62 (PortIoOut +uid 502,0 +shape (CompositeShape +uid 503,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 504,0 +sl 0 +ro 270 +xt "111500,71625,113000,72375" +) +(Line +uid 505,0 +sl 0 +ro 270 +xt "111000,72000,111500,72000" +pts [ +"111000,72000" +"111500,72000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 506,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 507,0 +va (VaSet +) +xt "114000,71500,116700,72500" +st "W_RD" +blo "114000,72300" +tm "WireNameMgr" +) +) +) +*63 (PortIoOut +uid 508,0 +shape (CompositeShape +uid 509,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 510,0 +sl 0 +ro 270 +xt "111500,72625,113000,73375" +) +(Line +uid 511,0 +sl 0 +ro 270 +xt "111000,73000,111500,73000" +pts [ +"111000,73000" +"111500,73000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 512,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 513,0 +va (VaSet +) +xt "114000,72500,116800,73500" +st "W_WR" +blo "114000,73300" +tm "WireNameMgr" +) +) +) +*64 (Net +uid 1465,0 +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 55 +suid 29,0 +) +declText (MLText +uid 1466,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,48000,62500,48800" +st "SIGNAL adc_data_array : adc_data_array_type +" +) +) +*65 (Net +uid 2407,0 +decl (Decl +n "RSRLOAD" +t "std_logic" +o 35 +suid 57,0 +i "'0'" +) +declText (MLText +uid 2408,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,31000,68000,31800" +st "RSRLOAD : std_logic := '0' +" +) +) +*66 (PortIoOut +uid 2415,0 +shape (CompositeShape +uid 2416,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2417,0 +sl 0 +ro 90 +xt "19000,110625,20500,111375" +) +(Line +uid 2418,0 +sl 0 +ro 90 +xt "20500,111000,21000,111000" +pts [ +"21000,111000" +"20500,111000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2419,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2420,0 +va (VaSet +) +xt "13800,110500,18000,111500" +st "RSRLOAD" +ju 2 +blo "18000,111300" +tm "WireNameMgr" +) +) +) +*67 (Net +uid 2421,0 +decl (Decl +n "SRCLK" +t "std_logic" +o 52 +suid 58,0 +i "'0'" +) +declText (MLText +uid 2422,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,46400,71500,47200" +st "SIGNAL SRCLK : std_logic := '0' +" +) +) +*68 (Net +uid 3019,0 +decl (Decl +n "sensor_cs" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 60 +suid 65,0 +) +declText (MLText +uid 3020,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,52000,67000,52800" +st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0) +" +) +) +*69 (Net +uid 3025,0 +decl (Decl +n "DAC_CS" +t "std_logic" +o 21 +suid 66,0 +) +declText (MLText +uid 3026,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,19800,53500,20600" +st "DAC_CS : std_logic +" +) +) +*70 (PortIoOut +uid 3153,0 +shape (CompositeShape +uid 3154,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3155,0 +sl 0 +ro 90 +xt "19000,69625,20500,70375" +) +(Line +uid 3156,0 +sl 0 +ro 90 +xt "20500,70000,21000,70000" +pts [ +"21000,70000" +"20500,70000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3157,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3158,0 +va (VaSet +) +xt "15200,69500,18000,70500" +st "A_CLK" +ju 2 +blo "18000,70300" +tm "WireNameMgr" +) +) +) +*71 (Net +uid 3216,0 +decl (Decl +n "X_50M" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 14 +suid 67,0 +) +declText (MLText +uid 3217,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,14200,53500,15000" +st "X_50M : STD_LOGIC +" +) +) +*72 (Net +uid 3226,0 +decl (Decl +n "TRG" +t "STD_LOGIC" +o 12 +suid 68,0 +) +declText (MLText +uid 3227,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,12600,53500,13400" +st "TRG : STD_LOGIC +" +) +) +*73 (HdlText +uid 3248,0 +optionalChildren [ +*74 (EmbeddedText +uid 3254,0 +commentText (CommentText +uid 3255,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3256,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "32000,71000,44000,77000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3257,0 +va (VaSet +) +xt "32200,71200,44100,77200" +st " +-- ADC_CLK 2 +A_CLK (0) <= CLK_25_PS; +A_CLK (1) <= CLK_25_PS; +A_CLK (2) <= CLK_25_PS; +A_CLK (3) <= CLK_25_PS; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 3249,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "24000,69000,32000,77000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3250,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*75 (Text +uid 3251,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,70000,31350,71000" +st "ADC_CLK" +blo "27150,70800" +tm "HdlTextNameMgr" +) +*76 (Text +uid 3252,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,71000,27950,72000" +st "2" +blo "27150,71800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3253,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "24250,75250,25750,76750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*77 (Net +uid 3266,0 +decl (Decl +n "A_CLK" +t "std_logic_vector" +b "(3 downto 0)" +o 16 +suid 71,0 +) +declText (MLText +uid 3267,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,15800,63500,16600" +st "A_CLK : std_logic_vector(3 downto 0) +" +) +) +*78 (Net +uid 3268,0 +decl (Decl +n "CLK_25_PS" +t "std_logic" +o 50 +suid 72,0 +) +declText (MLText +uid 3269,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,44800,57000,45600" +st "SIGNAL CLK_25_PS : std_logic +" +) +) +*79 (PortIoOut +uid 3284,0 +shape (CompositeShape +uid 3285,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3286,0 +sl 0 +ro 90 +xt "19000,89625,20500,90375" +) +(Line +uid 3287,0 +sl 0 +ro 90 +xt "20500,90000,21000,90000" +pts [ +"21000,90000" +"20500,90000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3288,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3289,0 +va (VaSet +) +xt "14400,89500,18000,90500" +st "OE_ADC" +ju 2 +blo "18000,90300" +tm "WireNameMgr" +) +) +) +*80 (Net +uid 3290,0 +decl (Decl +n "OE_ADC" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 30 +suid 73,0 +) +declText (MLText +uid 3291,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,27000,53500,27800" +st "OE_ADC : STD_LOGIC +" +) +) +*81 (PortIoIn +uid 3292,0 +shape (CompositeShape +uid 3293,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3294,0 +sl 0 +ro 270 +xt "19000,88625,20500,89375" +) +(Line +uid 3295,0 +sl 0 +ro 270 +xt "20500,89000,21000,89000" +pts [ +"20500,89000" +"21000,89000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3296,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3297,0 +va (VaSet +) +xt "15000,88500,18000,89500" +st "A_OTR" +ju 2 +blo "18000,89300" +tm "WireNameMgr" +) +) +) +*82 (Net +uid 3298,0 +decl (Decl +n "A_OTR" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 5 +suid 74,0 +) +declText (MLText +uid 3299,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,7000,63500,7800" +st "A_OTR : std_logic_vector(3 DOWNTO 0) +" +) +) +*83 (HdlText +uid 3300,0 +optionalChildren [ +*84 (EmbeddedText +uid 3306,0 +commentText (CommentText +uid 3307,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3308,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "32000,96000,44000,102000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3309,0 +va (VaSet +) +xt "32200,96200,44200,102200" +st " +-- ADC_DATA 3 +adc_data_array (0) <= A0_D; +adc_data_array (1) <= A1_D; +adc_data_array (2) <= A2_D; +adc_data_array (3) <= A3_D; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 3301,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "24000,94000,32000,102000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3302,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*85 (Text +uid 3303,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,95000,31750,96000" +st "ADC_DATA" +blo "27150,95800" +tm "HdlTextNameMgr" +) +*86 (Text +uid 3304,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,96000,27950,97000" +st "3" +blo "27150,96800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3305,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "24250,100250,25750,101750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*87 (PortIoIn +uid 3310,0 +shape (CompositeShape +uid 3311,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3312,0 +sl 0 +ro 270 +xt "19000,94625,20500,95375" +) +(Line +uid 3313,0 +sl 0 +ro 270 +xt "20500,95000,21000,95000" +pts [ +"20500,95000" +"21000,95000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3314,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3315,0 +va (VaSet +) +xt "15700,94500,18000,95500" +st "A0_D" +ju 2 +blo "18000,95300" +tm "WireNameMgr" +) +) +) +*88 (PortIoIn +uid 3332,0 +shape (CompositeShape +uid 3333,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3334,0 +sl 0 +ro 270 +xt "19000,95625,20500,96375" +) +(Line +uid 3335,0 +sl 0 +ro 270 +xt "20500,96000,21000,96000" +pts [ +"20500,96000" +"21000,96000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3336,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3337,0 +va (VaSet +) +xt "15700,95500,18000,96500" +st "A1_D" +ju 2 +blo "18000,96300" +tm "WireNameMgr" +) +) +) +*89 (PortIoIn +uid 3338,0 +shape (CompositeShape +uid 3339,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3340,0 +sl 0 +ro 270 +xt "19000,96625,20500,97375" +) +(Line +uid 3341,0 +sl 0 +ro 270 +xt "20500,97000,21000,97000" +pts [ +"20500,97000" +"21000,97000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3342,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3343,0 +va (VaSet +) +xt "15700,96500,18000,97500" +st "A2_D" +ju 2 +blo "18000,97300" +tm "WireNameMgr" +) +) +) +*90 (PortIoIn +uid 3344,0 +shape (CompositeShape +uid 3345,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3346,0 +sl 0 +ro 270 +xt "19000,97625,20500,98375" +) +(Line +uid 3347,0 +sl 0 +ro 270 +xt "20500,98000,21000,98000" +pts [ +"20500,98000" +"21000,98000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3348,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3349,0 +va (VaSet +) +xt "15700,97500,18000,98500" +st "A3_D" +ju 2 +blo "18000,98300" +tm "WireNameMgr" +) +) +) +*91 (Net +uid 3374,0 +decl (Decl +n "A0_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 1 +suid 79,0 +) +declText (MLText +uid 3375,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,3800,64000,4600" +st "A0_D : std_logic_vector(11 DOWNTO 0) +" +) +) +*92 (Net +uid 3376,0 +decl (Decl +n "A1_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 2 +suid 80,0 +) +declText (MLText +uid 3377,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,4600,64000,5400" +st "A1_D : std_logic_vector(11 DOWNTO 0) +" +) +) +*93 (Net +uid 3378,0 +decl (Decl +n "A2_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 3 +suid 81,0 +) +declText (MLText +uid 3379,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,5400,64000,6200" +st "A2_D : std_logic_vector(11 DOWNTO 0) +" +) +) +*94 (Net +uid 3380,0 +decl (Decl +n "A3_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 4 +suid 82,0 +) +declText (MLText +uid 3381,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,6200,64000,7000" +st "A3_D : std_logic_vector(11 DOWNTO 0) +" +) +) +*95 (HdlText +uid 3394,0 +optionalChildren [ +*96 (EmbeddedText +uid 3400,0 +commentText (CommentText +uid 3401,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3402,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "32000,114000,44000,120000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3403,0 +va (VaSet +) +xt "32200,114200,44200,120200" +st " +-- SRCLK 4 +D0_SRCLK <= SRCLK; +D1_SRCLK <= SRCLK; +D2_SRCLK <= SRCLK; +D3_SRCLK <= SRCLK; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 3395,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "24000,112000,32000,120000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3396,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*97 (Text +uid 3397,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,113000,30350,114000" +st "SRCLK" +blo "27150,113800" +tm "HdlTextNameMgr" +) +*98 (Text +uid 3398,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,114000,27950,115000" +st "4" +blo "27150,114800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3399,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "24250,118250,25750,119750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*99 (Net +uid 3460,0 +decl (Decl +n "D0_SRCLK" +t "STD_LOGIC" +o 17 +suid 87,0 +) +declText (MLText +uid 3461,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,16600,53500,17400" +st "D0_SRCLK : STD_LOGIC +" +) +) +*100 (Net +uid 3462,0 +decl (Decl +n "D1_SRCLK" +t "STD_LOGIC" +o 18 +suid 88,0 +) +declText (MLText +uid 3463,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,17400,53500,18200" +st "D1_SRCLK : STD_LOGIC +" +) +) +*101 (Net +uid 3464,0 +decl (Decl +n "D2_SRCLK" +t "STD_LOGIC" +o 19 +suid 89,0 +) +declText (MLText +uid 3465,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,18200,53500,19000" +st "D2_SRCLK : STD_LOGIC +" +) +) +*102 (Net +uid 3466,0 +decl (Decl +n "D3_SRCLK" +t "STD_LOGIC" +o 20 +suid 90,0 +) +declText (MLText +uid 3467,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,19000,53500,19800" +st "D3_SRCLK : STD_LOGIC +" +) +) +*103 (PortIoIn +uid 3476,0 +shape (CompositeShape +uid 3477,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3478,0 +sl 0 +ro 270 +xt "19000,104625,20500,105375" +) +(Line +uid 3479,0 +sl 0 +ro 270 +xt "20500,105000,21000,105000" +pts [ +"20500,105000" +"21000,105000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3480,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3481,0 +va (VaSet +) +xt "13400,104500,18000,105500" +st "D0_SROUT" +ju 2 +blo "18000,105300" +tm "WireNameMgr" +) +) +) +*104 (PortIoIn +uid 3482,0 +shape (CompositeShape +uid 3483,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3484,0 +sl 0 +ro 270 +xt "19000,105625,20500,106375" +) +(Line +uid 3485,0 +sl 0 +ro 270 +xt "20500,106000,21000,106000" +pts [ +"20500,106000" +"21000,106000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3486,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3487,0 +va (VaSet +) +xt "13400,105500,18000,106500" +st "D1_SROUT" +ju 2 +blo "18000,106300" +tm "WireNameMgr" +) +) +) +*105 (PortIoIn +uid 3488,0 +shape (CompositeShape +uid 3489,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3490,0 +sl 0 +ro 270 +xt "19000,106625,20500,107375" +) +(Line +uid 3491,0 +sl 0 +ro 270 +xt "20500,107000,21000,107000" +pts [ +"20500,107000" +"21000,107000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3492,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3493,0 +va (VaSet +) +xt "13400,106500,18000,107500" +st "D2_SROUT" +ju 2 +blo "18000,107300" +tm "WireNameMgr" +) +) +) +*106 (PortIoIn +uid 3494,0 +shape (CompositeShape +uid 3495,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3496,0 +sl 0 +ro 270 +xt "19000,107625,20500,108375" +) +(Line +uid 3497,0 +sl 0 +ro 270 +xt "20500,108000,21000,108000" +pts [ +"20500,108000" +"21000,108000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3498,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3499,0 +va (VaSet +) +xt "13400,107500,18000,108500" +st "D3_SROUT" +ju 2 +blo "18000,108300" +tm "WireNameMgr" +) +) +) +*107 (Net +uid 3500,0 +decl (Decl +n "D0_SROUT" +t "std_logic" +o 6 +suid 91,0 +) +declText (MLText +uid 3501,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,7800,53500,8600" +st "D0_SROUT : std_logic +" +) +) +*108 (Net +uid 3502,0 +decl (Decl +n "D1_SROUT" +t "std_logic" +o 7 +suid 92,0 +) +declText (MLText +uid 3503,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,8600,53500,9400" +st "D1_SROUT : std_logic +" +) +) +*109 (Net +uid 3504,0 +decl (Decl +n "D2_SROUT" +t "std_logic" +o 8 +suid 93,0 +) +declText (MLText +uid 3505,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,9400,53500,10200" +st "D2_SROUT : std_logic +" +) +) +*110 (Net +uid 3506,0 +decl (Decl +n "D3_SROUT" +t "std_logic" +o 9 +suid 94,0 +) +declText (MLText +uid 3507,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,10200,53500,11000" +st "D3_SROUT : std_logic +" +) +) +*111 (PortIoOut +uid 3508,0 +shape (CompositeShape +uid 3509,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3510,0 +sl 0 +ro 90 +xt "4000,133625,5500,134375" +) +(Line +uid 3511,0 +sl 0 +ro 90 +xt "5500,134000,6000,134000" +pts [ +"6000,134000" +"5500,134000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3512,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3513,0 +va (VaSet +) +xt "1100,133500,3000,134500" +st "D_A" +ju 2 +blo "3000,134300" +tm "WireNameMgr" +) +) +) +*112 (Net +uid 3514,0 +decl (Decl +n "D_A" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 24 +suid 95,0 +i "(others => '0')" +) +declText (MLText +uid 3515,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,22200,74000,23000" +st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0') +" +) +) +*113 (PortIoOut +uid 3516,0 +shape (CompositeShape +uid 3517,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3518,0 +sl 0 +ro 90 +xt "19000,109625,20500,110375" +) +(Line +uid 3519,0 +sl 0 +ro 90 +xt "20500,110000,21000,110000" +pts [ +"21000,110000" +"20500,110000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3520,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3521,0 +va (VaSet +) +xt "14500,109500,18000,110500" +st "DWRITE" +ju 2 +blo "18000,110300" +tm "WireNameMgr" +) +) +) +*114 (Net +uid 3522,0 +decl (Decl +n "DWRITE" +t "std_logic" +o 23 +suid 96,0 +i "'0'" +) +declText (MLText +uid 3523,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,21400,68000,22200" +st "DWRITE : std_logic := '0' +" +) +) +*115 (PortIoOut +uid 3536,0 +shape (CompositeShape +uid 3537,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3538,0 +sl 0 +ro 270 +xt "111500,86625,113000,87375" +) +(Line +uid 3539,0 +sl 0 +ro 270 +xt "111000,87000,111500,87000" +pts [ +"111000,87000" +"111500,87000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3540,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3541,0 +va (VaSet +) +xt "114000,86500,117600,87500" +st "DAC_CS" +blo "114000,87300" +tm "WireNameMgr" +) +) +) +*116 (HdlText +uid 3542,0 +optionalChildren [ +*117 (EmbeddedText +uid 3612,0 +commentText (CommentText +uid 3613,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3614,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "88000,90000,100000,96000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3615,0 +va (VaSet +) +xt "88200,90200,100100,96200" +st " +-- T_CS 5 +T0_CS <= sensor_cs (0); +T1_CS <= sensor_cs (1); +T2_CS <= sensor_cs (2); +T3_CS <= sensor_cs (3); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 3543,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "100000,88000,108000,96000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3544,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*118 (Text +uid 3545,0 +va (VaSet +font "Arial,8,1" +) +xt "103150,89000,105550,90000" +st "T_CS" +blo "103150,89800" +tm "HdlTextNameMgr" +) +*119 (Text +uid 3546,0 +va (VaSet +font "Arial,8,1" +) +xt "103150,90000,103950,91000" +st "5" +blo "103150,90800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3547,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "100250,94250,101750,95750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*120 (PortIoOut +uid 3548,0 +shape (CompositeShape +uid 3549,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3550,0 +sl 0 +ro 270 +xt "111500,88625,113000,89375" +) +(Line +uid 3551,0 +sl 0 +ro 270 +xt "111000,89000,111500,89000" +pts [ +"111000,89000" +"111500,89000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3552,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3553,0 +va (VaSet +) +xt "114000,88500,116800,89500" +st "T0_CS" +blo "114000,89300" +tm "WireNameMgr" +) +) +) +*121 (PortIoOut +uid 3554,0 +shape (CompositeShape +uid 3555,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3556,0 +sl 0 +ro 270 +xt "111500,89625,113000,90375" +) +(Line +uid 3557,0 +sl 0 +ro 270 +xt "111000,90000,111500,90000" +pts [ +"111000,90000" +"111500,90000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3558,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3559,0 +va (VaSet +) +xt "114000,89500,116800,90500" +st "T1_CS" +blo "114000,90300" +tm "WireNameMgr" +) +) +) +*122 (PortIoOut +uid 3560,0 +shape (CompositeShape +uid 3561,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3562,0 +sl 0 +ro 270 +xt "111500,90625,113000,91375" +) +(Line +uid 3563,0 +sl 0 +ro 270 +xt "111000,91000,111500,91000" +pts [ +"111000,91000" +"111500,91000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3564,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3565,0 +va (VaSet +) +xt "114000,90500,116800,91500" +st "T2_CS" +blo "114000,91300" +tm "WireNameMgr" +) +) +) +*123 (PortIoOut +uid 3566,0 +shape (CompositeShape +uid 3567,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3568,0 +sl 0 +ro 270 +xt "111500,91625,113000,92375" +) +(Line +uid 3569,0 +sl 0 +ro 270 +xt "111000,92000,111500,92000" +pts [ +"111000,92000" +"111500,92000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3570,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3571,0 +va (VaSet +) +xt "114000,91500,116800,92500" +st "T3_CS" +blo "114000,92300" +tm "WireNameMgr" +) +) +) +*124 (Net +uid 3604,0 +decl (Decl +n "T0_CS" +t "std_logic" +o 38 +suid 101,0 +) +declText (MLText +uid 3605,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,33400,53500,34200" +st "T0_CS : std_logic +" +) +) +*125 (Net +uid 3606,0 +decl (Decl +n "T1_CS" +t "std_logic" +o 39 +suid 102,0 +) +declText (MLText +uid 3607,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,34200,53500,35000" +st "T1_CS : std_logic +" +) +) +*126 (Net +uid 3608,0 +decl (Decl +n "T2_CS" +t "std_logic" +o 40 +suid 103,0 +) +declText (MLText +uid 3609,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,35000,53500,35800" +st "T2_CS : std_logic +" +) +) +*127 (Net +uid 3610,0 +decl (Decl +n "T3_CS" +t "std_logic" +o 41 +suid 104,0 +) +declText (MLText +uid 3611,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,35800,53500,36600" +st "T3_CS : std_logic +" +) +) +*128 (PortIoOut +uid 3624,0 +shape (CompositeShape +uid 3625,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3626,0 +sl 0 +ro 270 +xt "111500,97625,113000,98375" +) +(Line +uid 3627,0 +sl 0 +ro 270 +xt "111000,98000,111500,98000" +pts [ +"111000,98000" +"111500,98000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3628,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3629,0 +va (VaSet +) +xt "113750,97500,116550,98500" +st "S_CLK" +blo "113750,98300" +tm "WireNameMgr" +) +) +) +*129 (Net +uid 3630,0 +decl (Decl +n "S_CLK" +t "std_logic" +o 37 +suid 105,0 +) +declText (MLText +uid 3631,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,32600,53500,33400" +st "S_CLK : std_logic +" +) +) +*130 (Net +uid 3632,0 +decl (Decl +n "W_A" +t "std_logic_vector" +b "(9 DOWNTO 0)" +o 43 +suid 106,0 +) +declText (MLText +uid 3633,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,38200,63500,39000" +st "W_A : std_logic_vector(9 DOWNTO 0) +" +) +) +*131 (Net +uid 3634,0 +decl (Decl +n "W_D" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 49 +suid 107,0 +) +declText (MLText +uid 3635,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,43000,64000,43800" +st "W_D : std_logic_vector(15 DOWNTO 0) +" +) +) +*132 (Net +uid 3636,0 +decl (Decl +n "W_RES" +t "std_logic" +o 46 +suid 108,0 +i "'1'" +) +declText (MLText +uid 3637,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,40600,68000,41400" +st "W_RES : std_logic := '1' +" +) +) +*133 (Net +uid 3638,0 +decl (Decl +n "W_RD" +t "std_logic" +o 45 +suid 109,0 +i "'1'" +) +declText (MLText +uid 3639,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,39800,68000,40600" +st "W_RD : std_logic := '1' +" +) +) +*134 (Net +uid 3640,0 +decl (Decl +n "W_WR" +t "std_logic" +o 47 +suid 110,0 +i "'1'" +) +declText (MLText +uid 3641,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,41400,68000,42200" +st "W_WR : std_logic := '1' +" +) +) +*135 (Net +uid 3642,0 +decl (Decl +n "W_INT" +t "std_logic" +o 13 +suid 111,0 +) +declText (MLText +uid 3643,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,13400,53500,14200" +st "W_INT : std_logic +" +) +) +*136 (Net +uid 3644,0 +decl (Decl +n "W_CS" +t "std_logic" +o 44 +suid 112,0 +i "'1'" +) +declText (MLText +uid 3645,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,39000,68000,39800" +st "W_CS : std_logic := '1' +" +) +) +*137 (PortIoInOut +uid 3674,0 +shape (CompositeShape +uid 3675,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Hexagon +uid 3676,0 +sl 0 +xt "111500,98625,113000,99375" +) +(Line +uid 3677,0 +sl 0 +xt "111000,99000,111500,99000" +pts [ +"111000,99000" +"111500,99000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3678,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3679,0 +va (VaSet +) +xt "114000,98500,116400,99500" +st "MISO" +blo "114000,99300" +tm "WireNameMgr" +) +) +) +*138 (Net +uid 3680,0 +decl (Decl +n "MOSI" +t "std_logic" +o 29 +suid 113,0 +i "'0'" +) +declText (MLText +uid 3681,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,26200,68000,27000" +st "MOSI : std_logic := '0' +" +) +) +*139 (PortIoOut +uid 3688,0 +shape (CompositeShape +uid 3689,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3690,0 +sl 0 +ro 270 +xt "111500,99625,113000,100375" +) +(Line +uid 3691,0 +sl 0 +ro 270 +xt "111000,100000,111500,100000" +pts [ +"111000,100000" +"111500,100000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3692,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3693,0 +va (VaSet +) +xt "114000,99500,116400,100500" +st "MOSI" +blo "114000,100300" +tm "WireNameMgr" +) +) +) +*140 (Net +uid 3694,0 +decl (Decl +n "MISO" +t "std_logic" +preAdd 0 +posAdd 0 +o 48 +suid 114,0 +) +declText (MLText +uid 3695,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,42200,53500,43000" +st "MISO : std_logic +" +) +) +*141 (HdlText +uid 3700,0 +optionalChildren [ +*142 (EmbeddedText +uid 3706,0 +commentText (CommentText +uid 3707,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3708,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "82000,102000,100000,118000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3709,0 +va (VaSet +) +xt "82200,102200,98600,118200" +st " +-- MISC 6 +TRG_V <= '0'; +RS485_C_RE <= '1'; +RS485_C_DE <= '0'; +RS485_E_RE <= '1'; +RS485_E_DE <= '0'; + +-- DENABLE <= '0'; -- domino wave stopped +-- DENABLE <= '1'; -- domino wave running + +SRIN <= 'Z'; +EE_CS <= '1'; +-- LEDs are low active +LED(0) <= '1'; +LED(1) <= '0'; -- on +LED(2) <= '1'; + + + + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 16000 +visibleWidth 18000 +) +) +) +] +shape (Rectangle +uid 3701,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "100000,102000,108000,115000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3702,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*143 (Text +uid 3703,0 +va (VaSet +font "Arial,8,1" +) +xt "103150,106000,105550,107000" +st "MISC" +blo "103150,106800" +tm "HdlTextNameMgr" +) +*144 (Text +uid 3704,0 +va (VaSet +font "Arial,8,1" +) +xt "103150,107000,103950,108000" +st "6" +blo "103150,107800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3705,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "100250,113250,101750,114750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*145 (PortIoOut +uid 3710,0 +shape (CompositeShape +uid 3711,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3712,0 +sl 0 +ro 270 +xt "111500,102625,113000,103375" +) +(Line +uid 3713,0 +sl 0 +ro 270 +xt "111000,103000,111500,103000" +pts [ +"111000,103000" +"111500,103000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3714,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3715,0 +va (VaSet +) +xt "114000,102500,117000,103500" +st "TRG_V" +blo "114000,103300" +tm "WireNameMgr" +) +) +) +*146 (PortIoOut +uid 3716,0 +shape (CompositeShape +uid 3717,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3718,0 +sl 0 +ro 270 +xt "111500,103625,113000,104375" +) +(Line +uid 3719,0 +sl 0 +ro 270 +xt "111000,104000,111500,104000" +pts [ +"111000,104000" +"111500,104000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3720,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3721,0 +va (VaSet +) +xt "114000,103500,119600,104500" +st "RS485_C_RE" +blo "114000,104300" +tm "WireNameMgr" +) +) +) +*147 (PortIoOut +uid 3722,0 +shape (CompositeShape +uid 3723,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3724,0 +sl 0 +ro 270 +xt "111500,104625,113000,105375" +) +(Line +uid 3725,0 +sl 0 +ro 270 +xt "111000,105000,111500,105000" +pts [ +"111000,105000" +"111500,105000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3726,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3727,0 +va (VaSet +) +xt "114000,104500,119600,105500" +st "RS485_C_DE" +blo "114000,105300" +tm "WireNameMgr" +) +) +) +*148 (PortIoOut +uid 3728,0 +shape (CompositeShape +uid 3729,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3730,0 +sl 0 +ro 270 +xt "111500,105625,113000,106375" +) +(Line +uid 3731,0 +sl 0 +ro 270 +xt "111000,106000,111500,106000" +pts [ +"111000,106000" +"111500,106000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3732,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3733,0 +va (VaSet +) +xt "114000,105500,119500,106500" +st "RS485_E_RE" +blo "114000,106300" +tm "WireNameMgr" +) +) +) +*149 (PortIoOut +uid 3734,0 +shape (CompositeShape +uid 3735,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3736,0 +sl 0 +ro 270 +xt "111500,106625,113000,107375" +) +(Line +uid 3737,0 +sl 0 +ro 270 +xt "111000,107000,111500,107000" +pts [ +"111000,107000" +"111500,107000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3738,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3739,0 +va (VaSet +) +xt "114000,106500,119500,107500" +st "RS485_E_DE" +blo "114000,107300" +tm "WireNameMgr" +) +) +) +*150 (PortIoOut +uid 3740,0 +shape (CompositeShape +uid 3741,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3742,0 +sl 0 +ro 270 +xt "111500,120625,113000,121375" +) +(Line +uid 3743,0 +sl 0 +ro 270 +xt "111000,121000,111500,121000" +pts [ +"111000,121000" +"111500,121000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3744,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3745,0 +va (VaSet +) +xt "114000,120500,118000,121500" +st "DENABLE" +blo "114000,121300" +tm "WireNameMgr" +) +) +) +*151 (PortIoOut +uid 3746,0 +shape (CompositeShape +uid 3747,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3748,0 +sl 0 +ro 270 +xt "111500,108625,113000,109375" +) +(Line +uid 3749,0 +sl 0 +ro 270 +xt "111000,109000,111500,109000" +pts [ +"111000,109000" +"111500,109000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3750,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3751,0 +va (VaSet +) +xt "114000,108500,116300,109500" +st "SRIN" +blo "114000,109300" +tm "WireNameMgr" +) +) +) +*152 (PortIoOut +uid 3752,0 +shape (CompositeShape +uid 3753,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3754,0 +sl 0 +ro 270 +xt "111500,109625,113000,110375" +) +(Line +uid 3755,0 +sl 0 +ro 270 +xt "111000,110000,111500,110000" +pts [ +"111000,110000" +"111500,110000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3756,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3757,0 +va (VaSet +) +xt "114000,109500,116900,110500" +st "EE_CS" +blo "114000,110300" +tm "WireNameMgr" +) +) +) +*153 (PortIoOut +uid 3758,0 +shape (CompositeShape +uid 3759,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3760,0 +sl 0 +ro 270 +xt "111500,110625,113000,111375" +) +(Line +uid 3761,0 +sl 0 +ro 270 +xt "111000,111000,111500,111000" +pts [ +"111000,111000" +"111500,111000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3762,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3763,0 +va (VaSet +) +xt "114000,110500,115900,111500" +st "LED" +blo "114000,111300" +tm "WireNameMgr" +) +) +) +*154 (Net +uid 3864,0 +decl (Decl +n "TRG_V" +t "std_logic" +o 42 +suid 126,0 +) +declText (MLText +uid 3865,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,37400,53500,38200" +st "TRG_V : std_logic +" +) +) +*155 (Net +uid 3866,0 +decl (Decl +n "RS485_C_RE" +t "std_logic" +o 32 +suid 127,0 +) +declText (MLText +uid 3867,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,28600,53500,29400" +st "RS485_C_RE : std_logic +" +) +) +*156 (Net +uid 3868,0 +decl (Decl +n "RS485_C_DE" +t "std_logic" +o 31 +suid 128,0 +) +declText (MLText +uid 3869,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,27800,53500,28600" +st "RS485_C_DE : std_logic +" +) +) +*157 (Net +uid 3870,0 +decl (Decl +n "RS485_E_RE" +t "std_logic" +o 34 +suid 129,0 +) +declText (MLText +uid 3871,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,30200,53500,31000" +st "RS485_E_RE : std_logic +" +) +) +*158 (Net +uid 3872,0 +decl (Decl +n "RS485_E_DE" +t "std_logic" +o 33 +suid 130,0 +) +declText (MLText +uid 3873,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,29400,53500,30200" +st "RS485_E_DE : std_logic +" +) +) +*159 (Net +uid 3874,0 +decl (Decl +n "DENABLE" +t "std_logic" +o 22 +suid 131,0 +i "'0'" +) +declText (MLText +uid 3875,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,20600,68000,21400" +st "DENABLE : std_logic := '0' +" +) +) +*160 (Net +uid 3876,0 +decl (Decl +n "SRIN" +t "std_logic" +o 36 +suid 132,0 +) +declText (MLText +uid 3877,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,31800,53500,32600" +st "SRIN : std_logic +" +) +) +*161 (Net +uid 3878,0 +decl (Decl +n "EE_CS" +t "std_logic" +o 27 +suid 133,0 +) +declText (MLText +uid 3879,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,24600,53500,25400" +st "EE_CS : std_logic +" +) +) +*162 (Net +uid 3880,0 +decl (Decl +n "LED" +t "std_logic_vector" +b "( 2 DOWNTO 0 )" +o 28 +suid 134,0 +i "(others => '1')" +) +declText (MLText +uid 3881,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,25400,74000,26200" +st "LED : std_logic_vector( 2 DOWNTO 0 ) := (others => '1') +" +) +) +*163 (PortIoOut +uid 3995,0 +shape (CompositeShape +uid 3996,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3997,0 +sl 0 +ro 90 +xt "19000,112625,20500,113375" +) +(Line +uid 3998,0 +sl 0 +ro 90 +xt "20500,113000,21000,113000" +pts [ +"21000,113000" +"20500,113000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3999,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4000,0 +va (VaSet +) +xt "13600,112500,18000,113500" +st "D0_SRCLK" +ju 2 +blo "18000,113300" +tm "WireNameMgr" +) +) +) +*164 (PortIoOut +uid 4001,0 +shape (CompositeShape +uid 4002,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4003,0 +sl 0 +ro 90 +xt "19000,113625,20500,114375" +) +(Line +uid 4004,0 +sl 0 +ro 90 +xt "20500,114000,21000,114000" +pts [ +"21000,114000" +"20500,114000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 4005,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4006,0 +va (VaSet +) +xt "13600,113500,18000,114500" +st "D1_SRCLK" +ju 2 +blo "18000,114300" +tm "WireNameMgr" +) +) +) +*165 (PortIoOut +uid 4007,0 +shape (CompositeShape +uid 4008,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4009,0 +sl 0 +ro 90 +xt "19000,114625,20500,115375" +) +(Line +uid 4010,0 +sl 0 +ro 90 +xt "20500,115000,21000,115000" +pts [ +"21000,115000" +"20500,115000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 4011,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4012,0 +va (VaSet +) +xt "13600,114500,18000,115500" +st "D2_SRCLK" +ju 2 +blo "18000,115300" +tm "WireNameMgr" +) +) +) +*166 (PortIoOut +uid 4013,0 +shape (CompositeShape +uid 4014,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4015,0 +sl 0 +ro 90 +xt "19000,115625,20500,116375" +) +(Line +uid 4016,0 +sl 0 +ro 90 +xt "20500,116000,21000,116000" +pts [ +"21000,116000" +"20500,116000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 4017,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4018,0 +va (VaSet +) +xt "13600,115500,18000,116500" +st "D3_SRCLK" +ju 2 +blo "18000,116300" +tm "WireNameMgr" +) +) +) +*167 (PortIoOut +uid 4916,0 +shape (CompositeShape +uid 4917,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4918,0 +sl 0 +ro 270 +xt "111500,119625,113000,120375" +) +(Line +uid 4919,0 +sl 0 +ro 270 +xt "111000,120000,111500,120000" +pts [ +"111000,120000" +"111500,120000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 4920,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4921,0 +va (VaSet +) +xt "114000,119500,115900,120500" +st "D_T" +blo "114000,120300" +tm "WireNameMgr" +) +) +) +*168 (Net +uid 5320,0 +decl (Decl +n "D_T" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 25 +suid 141,0 +i "(OTHERS => '0')" +) +declText (MLText +uid 5321,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,23000,74000,23800" +st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') +" +) +) +*169 (PortIoIn +uid 5650,0 +shape (CompositeShape +uid 5651,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5652,0 +sl 0 +ro 270 +xt "38000,123625,39500,124375" +) +(Line +uid 5653,0 +sl 0 +ro 270 +xt "39500,124000,40000,124000" +pts [ +"39500,124000" +"40000,124000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 5654,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5655,0 +va (VaSet +) +xt "33400,123500,37000,124500" +st "TEST_IN" +ju 2 +blo "37000,124300" +tm "WireNameMgr" +) +) +) +*170 (Net +uid 5662,0 +decl (Decl +n "TEST_IN" +t "std_logic" +o 11 +suid 142,0 +) +declText (MLText +uid 5663,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,11800,53500,12600" +st "TEST_IN : std_logic +" +) +) +*171 (Net +uid 6138,0 +decl (Decl +n "TRG_OR" +t "std_logic" +o 54 +suid 146,0 +) +declText (MLText +uid 6139,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,47200,57000,48000" +st "SIGNAL TRG_OR : std_logic +" +) +) +*172 (PortIoIn +uid 6781,0 +shape (CompositeShape +uid 6782,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 6783,0 +sl 0 +ro 270 +xt "91000,131625,92500,132375" +) +(Line +uid 6784,0 +sl 0 +ro 270 +xt "92500,132000,93000,132000" +pts [ +"92500,132000" +"93000,132000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 6785,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6786,0 +va (VaSet +) +xt "85800,131500,90000,132500" +st "D_PLLLCK" +ju 2 +blo "90000,132300" +tm "WireNameMgr" +) +) +) +*173 (Net +uid 6793,0 +decl (Decl +n "D_PLLLCK" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 10 +suid 152,0 +) +declText (MLText +uid 6794,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,11000,63500,11800" +st "D_PLLLCK : std_logic_vector(3 DOWNTO 0) +" +) +) +*174 (PortIoOut +uid 6874,0 +shape (CompositeShape +uid 6875,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 6876,0 +sl 0 +ro 270 +xt "109500,131625,111000,132375" +) +(Line +uid 6877,0 +sl 0 +ro 270 +xt "109000,132000,109500,132000" +pts [ +"109000,132000" +"109500,132000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 6878,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6879,0 +va (VaSet +) +xt "112000,131500,114300,132500" +st "D_T2" +blo "112000,132300" +tm "WireNameMgr" +) +) +) +*175 (Net +uid 6886,0 +decl (Decl +n "D_T2" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 26 +suid 154,0 +i "(others => '0')" +) +declText (MLText +uid 6887,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,23800,74000,24600" +st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0') +" +) +) +*176 (HdlText +uid 6888,0 +optionalChildren [ +*177 (EmbeddedText +uid 6894,0 +commentText (CommentText +uid 6895,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 6896,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "96000,128000,106000,131000" +) +oxt "0,0,18000,5000" +text (MLText +uid 6897,0 +va (VaSet +) +xt "96200,128200,104300,129200" +st " +D_T2 <= D_PLLLCK; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 3000 +visibleWidth 10000 +) +) +) +] +shape (Rectangle +uid 6889,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "99000,131000,102000,134000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 6890,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*178 (Text +uid 6891,0 +va (VaSet +font "Arial,8,1" +) +xt "100150,135000,101850,136000" +st "eb1" +blo "100150,135800" +tm "HdlTextNameMgr" +) +*179 (Text +uid 6892,0 +va (VaSet +font "Arial,8,1" +) +xt "100150,136000,100950,137000" +st "7" +blo "100150,136800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 6893,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "99250,132250,100750,133750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*180 (HdlText +uid 7092,0 +optionalChildren [ +*181 (EmbeddedText +uid 7098,0 +commentText (CommentText +uid 7099,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 7100,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "26000,137000,46000,143000" +) +oxt "0,0,18000,5000" +text (MLText +uid 7101,0 +va (VaSet +) +xt "26200,137200,40000,141200" +st " +-- eb2 8 +A1_T(3 downto 0) <= drs_channel_id; +D_A <= drs_channel_id; +A1_T(4) <= TRG_OR; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 20000 +) +) +) +] +shape (Rectangle +uid 7093,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "31000,131000,39000,137000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 7094,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*182 (Text +uid 7095,0 +va (VaSet +font "Arial,8,1" +) +xt "34150,135000,35850,136000" +st "eb2" +blo "34150,135800" +tm "HdlTextNameMgr" +) +*183 (Text +uid 7096,0 +va (VaSet +font "Arial,8,1" +) +xt "34150,136000,34950,137000" +st "8" +blo "34150,136800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 7097,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "31250,135250,32750,136750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*184 (PortIoOut +uid 7138,0 +shape (CompositeShape +uid 7139,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 7140,0 +sl 0 +ro 270 +xt "44500,131625,46000,132375" +) +(Line +uid 7141,0 +sl 0 +ro 270 +xt "44000,132000,44500,132000" +pts [ +"44000,132000" +"44500,132000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 7142,0 +ps "PortIoTextPlaceStrategy" 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"92000,88000,98500,89000" +st "sensor_cs : (3:0)" +blo "92000,88800" +tm "WireNameMgr" +) +) +on &68 +) +*241 (Wire +uid 3027,0 +shape (OrthoPolyLine +uid 3028,0 +va (VaSet +vasetType 3 +) +xt "94000,87000,111000,87000" +pts [ +"94000,87000" +"111000,87000" +] +) +start &190 +end &115 +ss 0 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3031,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3032,0 +va (VaSet +isHidden 1 +) +xt "95000,86000,98600,87000" +st "DAC_CS" +blo "95000,86800" +tm "WireNameMgr" +) +) +on &69 +) +*242 (Wire +uid 3218,0 +shape (OrthoPolyLine +uid 3219,0 +va (VaSet +vasetType 3 +) +xt "14000,78000,16000,78000" +pts [ +"14000,78000" +"16000,78000" +] +) +start &49 +end &203 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3220,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3221,0 +va (VaSet +isHidden 1 +) +xt "25000,77000,27100,78000" +st "TRG" +blo "25000,77800" +tm "WireNameMgr" +) +) +on &72 +) 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"21000,95000,24000,95000" +pts [ +"21000,95000" +"24000,95000" +] +) +start &87 +end &83 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3322,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3323,0 +va (VaSet +isHidden 1 +) +xt "23000,94000,25300,95000" +st "A0_D" +blo "23000,94800" +tm "WireNameMgr" +) +) +on &91 +) +*246 (Wire +uid 3352,0 +shape (OrthoPolyLine +uid 3353,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "21000,96000,24000,96000" +pts [ +"21000,96000" +"24000,96000" +] +) +start &88 +end &83 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3356,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3357,0 +va (VaSet +isHidden 1 +) +xt "23000,95000,25300,96000" +st "A1_D" +blo "23000,95800" +tm "WireNameMgr" +) +) +on &92 +) +*247 (Wire +uid 3360,0 +shape (OrthoPolyLine +uid 3361,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "21000,97000,24000,97000" +pts [ +"21000,97000" +"24000,97000" +] +) +start &89 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"ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3435,0 +va (VaSet +isHidden 1 +) +xt "23000,112000,27400,113000" +st "D0_SRCLK" +blo "23000,112800" +tm "WireNameMgr" +) +) +on &99 +) +*250 (Wire +uid 3438,0 +shape (OrthoPolyLine +uid 3439,0 +va (VaSet +vasetType 3 +) +xt "21000,114000,24000,114000" +pts [ +"21000,114000" +"24000,114000" +] +) +start &164 +end &95 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3442,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3443,0 +va (VaSet +isHidden 1 +) +xt "23000,113000,27400,114000" +st "D1_SRCLK" +blo "23000,113800" +tm "WireNameMgr" +) +) +on &100 +) +*251 (Wire +uid 3446,0 +shape (OrthoPolyLine +uid 3447,0 +va (VaSet +vasetType 3 +) +xt "21000,115000,24000,115000" +pts [ +"21000,115000" +"24000,115000" +] +) +start &165 +end &95 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3450,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3451,0 +va (VaSet +isHidden 1 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&124 +) +*254 (Wire +uid 3582,0 +shape (OrthoPolyLine +uid 3583,0 +va (VaSet +vasetType 3 +) +xt "108000,90000,111000,90000" +pts [ +"111000,90000" +"108000,90000" +] +) +start &121 +end &116 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3586,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3587,0 +va (VaSet +isHidden 1 +) +xt "108000,89000,110800,90000" +st "T1_CS" +blo "108000,89800" +tm "WireNameMgr" +) +) +on &125 +) +*255 (Wire +uid 3590,0 +shape (OrthoPolyLine +uid 3591,0 +va (VaSet +vasetType 3 +) +xt "108000,91000,111000,91000" +pts [ +"111000,91000" +"108000,91000" +] +) +start &122 +end &116 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3594,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3595,0 +va (VaSet +isHidden 1 +) +xt "108000,90000,110800,91000" +st "T2_CS" +blo "108000,90800" +tm "WireNameMgr" +) +) +on &126 +) +*256 (Wire +uid 3598,0 +shape (OrthoPolyLine +uid 3599,0 +va (VaSet +vasetType 3 +) +xt "108000,92000,111000,92000" +pts [ +"111000,92000" +"108000,92000" +] +) +start &123 +end &116 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3602,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3603,0 +va (VaSet +isHidden 1 +) +xt "108000,91000,110800,92000" +st "T3_CS" +blo "108000,91800" +tm "WireNameMgr" +) +) +on &127 +) +*257 (Wire +uid 3682,0 +shape (OrthoPolyLine +uid 3683,0 +va (VaSet +vasetType 3 +) +xt "80750,100000,111000,100000" +pts [ +"80750,100000" +"111000,100000" +] +) +start &42 +end &139 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3686,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3687,0 +va (VaSet +isHidden 1 +) +xt "82750,99000,85150,100000" +st "MOSI" +blo "82750,99800" +tm "WireNameMgr" +) +) +on &138 +) +*258 (Wire +uid 3778,0 +shape (OrthoPolyLine +uid 3779,0 +va (VaSet +vasetType 3 +) +xt "108000,103000,111000,103000" +pts [ +"111000,103000" +"108000,103000" +] +) +start &145 +end &141 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"ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3799,0 +va (VaSet +isHidden 1 +) +xt "108000,104000,113600,105000" +st "RS485_C_DE" +blo "108000,104800" +tm "WireNameMgr" +) +) +on &156 +) +*261 (Wire +uid 3802,0 +shape (OrthoPolyLine +uid 3803,0 +va (VaSet +vasetType 3 +) +xt "108000,106000,111000,106000" +pts [ +"111000,106000" +"108000,106000" +] +) +start &148 +end &141 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3806,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3807,0 +va (VaSet +isHidden 1 +) +xt "108000,105000,113500,106000" +st "RS485_E_RE" +blo "108000,105800" +tm "WireNameMgr" +) +) +on &157 +) +*262 (Wire +uid 3810,0 +shape (OrthoPolyLine +uid 3811,0 +va (VaSet +vasetType 3 +) +xt "108000,107000,111000,107000" +pts [ +"111000,107000" +"108000,107000" +] +) +start &149 +end &141 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3814,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3815,0 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"108000,109800" +tm "WireNameMgr" +) +) +on &161 +) +*265 (Wire +uid 3842,0 +shape (OrthoPolyLine +uid 3843,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "108000,111000,111000,111000" +pts [ +"111000,111000" +"108000,111000" +] +) +start &153 +end &141 +sat 32 +eat 2 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3846,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3847,0 +va (VaSet +isHidden 1 +) +xt "108000,110000,109900,111000" +st "LED" +blo "108000,110800" +tm "WireNameMgr" +) +) +on &162 +) +*266 (Wire +uid 4942,0 +shape (OrthoPolyLine +uid 4943,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "80750,120000,111000,120000" +pts [ +"80750,120000" +"111000,120000" +] +) +start &14 +end &167 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 4948,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4949,0 +va (VaSet +isHidden 1 +) +xt "82750,117000,84650,118000" +st "D_T" +blo "82750,117800" +tm "WireNameMgr" +) +) +on &168 +) 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"CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2980,0 +va (VaSet +) +xt "72500,88500,79000,89500" +st "sensor_cs : (3:0)" +ju 2 +blo "79000,89300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sensor_cs" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 25 +suid 65,0 +) +) +) +*41 (CptPort +uid 2981,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 2982,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "80000,98625,80750,99375" +) +tg (CPTG +uid 2983,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2984,0 +va (VaSet +) +xt "77600,98500,79000,99500" +st "sio" +ju 2 +blo "79000,99300" +) +) +thePort (LogicalPort +m 2 +decl (Decl +n "sio" +t "std_logic" +preAdd 0 +posAdd 0 +o 31 +suid 63,0 +) +) +) +*42 (CptPort +uid 3670,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3671,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "80000,99625,80750,100375" +) +tg (CPTG +uid 3672,0 +ps "CptPortTextPlaceStrategy" +stg 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(Text +uid 10063,0 +va (VaSet +) +xt "53000,120500,56600,121500" +st "TEST_IN" +blo "53000,121300" +) +) +thePort (LogicalPort +decl (Decl +n "TEST_IN" +t "std_logic" +o 6 +suid 69,0 +) +) +) +] +shape (Rectangle +uid 170,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "52000,66000,80000,123000" +) +oxt "15000,-1000,43000,27000" +ttg (MlTextGroup +uid 171,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*45 (Text +uid 172,0 +va (VaSet +font "Arial,8,1" +) +xt "52200,123000,58400,124000" +st "FACT_FAD_lib" +blo "52200,123800" +tm "BdLibraryNameMgr" +) +*46 (Text +uid 173,0 +va (VaSet +font "Arial,8,1" +) +xt "52200,124000,56400,125000" +st "FAD_main" +blo "52200,124800" +tm "CptNameMgr" +) +*47 (Text +uid 174,0 +va (VaSet +font "Arial,8,1" +) +xt "52200,125000,58000,126000" +st "I_board_main" +blo "52200,125800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 175,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 176,0 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"8900,77500,11000,78500" +st "TRG" +ju 2 +blo "11000,78300" +tm "WireNameMgr" +) +) +) +*49 (PortIoIn +uid 251,0 +shape (CompositeShape +uid 252,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 253,0 +sl 0 +ro 270 +xt "19000,67625,20500,68375" +) +(Line +uid 254,0 +sl 0 +ro 270 +xt "20500,68000,21000,68000" +pts [ +"20500,68000" +"21000,68000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 255,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 256,0 +va (VaSet +) +xt "15200,67500,18000,68500" +st "X_50M" +ju 2 +blo "18000,68300" +tm "WireNameMgr" +) +) +) +*50 (HdlText +uid 265,0 +optionalChildren [ +*51 (EmbeddedText +uid 271,0 +commentText (CommentText +uid 272,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 273,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "32000,83000,44000,87000" +) +oxt "12000,27000,20000,31000" +text (MLText +uid 274,0 +va (VaSet +) +xt "32200,83200,39700,86200" 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"W_CS" +blo "114000,75300" +tm "WireNameMgr" +) +) +) +*59 (PortIoInOut +uid 490,0 +shape (CompositeShape +uid 491,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Hexagon +uid 492,0 +sl 0 +xt "111500,68625,113000,69375" +) +(Line +uid 493,0 +sl 0 +xt "111000,69000,111500,69000" +pts [ +"111000,69000" +"111500,69000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 494,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 495,0 +va (VaSet +) +xt "114000,68500,116100,69500" +st "W_D" +blo "114000,69300" +tm "WireNameMgr" +) +) +) +*60 (PortIoIn +uid 496,0 +shape (CompositeShape +uid 497,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 498,0 +sl 0 +ro 90 +xt "111500,73625,113000,74375" +) +(Line +uid 499,0 +sl 0 +ro 90 +xt "111000,74000,111500,74000" +pts [ +"111500,74000" +"111000,74000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 500,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 501,0 +va (VaSet +) +xt "114000,73500,116800,74500" +st "W_INT" +blo "114000,74300" +tm "WireNameMgr" +) +) +) +*61 (PortIoOut +uid 502,0 +shape (CompositeShape +uid 503,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 504,0 +sl 0 +ro 270 +xt "111500,71625,113000,72375" +) +(Line +uid 505,0 +sl 0 +ro 270 +xt "111000,72000,111500,72000" +pts [ +"111000,72000" +"111500,72000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 506,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 507,0 +va (VaSet +) +xt "114000,71500,116700,72500" +st "W_RD" +blo "114000,72300" +tm "WireNameMgr" +) +) +) +*62 (PortIoOut +uid 508,0 +shape (CompositeShape +uid 509,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 510,0 +sl 0 +ro 270 +xt "111500,72625,113000,73375" +) +(Line +uid 511,0 +sl 0 +ro 270 +xt "111000,73000,111500,73000" +pts [ +"111000,73000" +"111500,73000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 512,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 513,0 +va (VaSet +) +xt "114000,72500,116800,73500" +st "W_WR" +blo "114000,73300" +tm "WireNameMgr" +) +) +) +*63 (Net +uid 1465,0 +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 55 +suid 29,0 +) +declText (MLText +uid 1466,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,48000,62500,48800" +st "SIGNAL adc_data_array : adc_data_array_type" +) +) +*64 (Net +uid 2407,0 +decl (Decl +n "RSRLOAD" +t "std_logic" +o 35 +suid 57,0 +i "'0'" +) +declText (MLText +uid 2408,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,31000,68000,31800" +st "RSRLOAD : std_logic := '0'" +) +) +*65 (PortIoOut +uid 2415,0 +shape (CompositeShape +uid 2416,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2417,0 +sl 0 +ro 90 +xt "19000,110625,20500,111375" +) +(Line +uid 2418,0 +sl 0 +ro 90 +xt "20500,111000,21000,111000" +pts [ +"21000,111000" +"20500,111000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2419,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2420,0 +va (VaSet +) +xt "13800,110500,18000,111500" +st "RSRLOAD" +ju 2 +blo "18000,111300" +tm "WireNameMgr" +) +) +) +*66 (Net +uid 2421,0 +decl (Decl +n "SRCLK" +t "std_logic" +o 52 +suid 58,0 +i "'0'" +) +declText (MLText +uid 2422,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,46400,71500,47200" +st "SIGNAL SRCLK : std_logic := '0'" +) +) +*67 (Net +uid 3019,0 +decl (Decl +n "sensor_cs" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 60 +suid 65,0 +) +declText (MLText +uid 3020,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,52000,67000,52800" +st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" +) +) +*68 (Net +uid 3025,0 +decl (Decl +n "DAC_CS" +t "std_logic" +o 21 +suid 66,0 +) +declText (MLText +uid 3026,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,19800,53500,20600" +st "DAC_CS : std_logic" +) +) +*69 (PortIoOut +uid 3153,0 +shape (CompositeShape +uid 3154,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3155,0 +sl 0 +ro 90 +xt "19000,69625,20500,70375" +) +(Line +uid 3156,0 +sl 0 +ro 90 +xt "20500,70000,21000,70000" +pts [ +"21000,70000" +"20500,70000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3157,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3158,0 +va (VaSet +) +xt "15200,69500,18000,70500" +st "A_CLK" +ju 2 +blo "18000,70300" +tm "WireNameMgr" +) +) +) +*70 (Net +uid 3216,0 +decl (Decl +n "X_50M" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 14 +suid 67,0 +) +declText (MLText +uid 3217,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,14200,53500,15000" +st "X_50M : STD_LOGIC" +) +) +*71 (Net +uid 3226,0 +decl (Decl +n "TRG" +t "STD_LOGIC" +o 12 +suid 68,0 +) +declText (MLText +uid 3227,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,12600,53500,13400" +st "TRG : STD_LOGIC" +) +) +*72 (HdlText +uid 3248,0 +optionalChildren [ +*73 (EmbeddedText +uid 3254,0 +commentText (CommentText +uid 3255,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3256,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "32000,71000,44000,77000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3257,0 +va (VaSet +) +xt "32200,71200,44100,77200" +st " +-- ADC_CLK 2 +A_CLK (0) <= CLK_25_PS; +A_CLK (1) <= CLK_25_PS; +A_CLK (2) <= CLK_25_PS; +A_CLK (3) <= CLK_25_PS; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 3249,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "24000,69000,32000,77000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3250,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*74 (Text +uid 3251,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,70000,31350,71000" +st "ADC_CLK" +blo "27150,70800" +tm "HdlTextNameMgr" +) +*75 (Text +uid 3252,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,71000,27950,72000" +st "2" +blo "27150,71800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3253,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "24250,75250,25750,76750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*76 (Net +uid 3266,0 +decl (Decl +n "A_CLK" +t "std_logic_vector" +b "(3 downto 0)" +o 16 +suid 71,0 +) +declText (MLText +uid 3267,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,15800,63500,16600" +st "A_CLK : std_logic_vector(3 downto 0)" +) +) +*77 (Net +uid 3268,0 +decl (Decl +n "CLK_25_PS" +t "std_logic" +o 50 +suid 72,0 +) +declText (MLText +uid 3269,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,44800,57000,45600" +st "SIGNAL CLK_25_PS : std_logic" +) +) +*78 (PortIoOut +uid 3284,0 +shape (CompositeShape +uid 3285,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3286,0 +sl 0 +ro 90 +xt "19000,89625,20500,90375" +) +(Line +uid 3287,0 +sl 0 +ro 90 +xt "20500,90000,21000,90000" +pts [ +"21000,90000" +"20500,90000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3288,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3289,0 +va (VaSet +) +xt "14400,89500,18000,90500" +st "OE_ADC" +ju 2 +blo "18000,90300" +tm "WireNameMgr" +) +) +) +*79 (Net +uid 3290,0 +decl (Decl +n "OE_ADC" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 30 +suid 73,0 +) +declText (MLText +uid 3291,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,27000,53500,27800" +st "OE_ADC : STD_LOGIC" +) +) +*80 (PortIoIn +uid 3292,0 +shape (CompositeShape +uid 3293,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3294,0 +sl 0 +ro 270 +xt "19000,88625,20500,89375" +) +(Line +uid 3295,0 +sl 0 +ro 270 +xt "20500,89000,21000,89000" +pts [ +"20500,89000" +"21000,89000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3296,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3297,0 +va (VaSet +) +xt "15000,88500,18000,89500" +st "A_OTR" +ju 2 +blo "18000,89300" +tm "WireNameMgr" +) +) +) +*81 (Net +uid 3298,0 +decl (Decl +n "A_OTR" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 5 +suid 74,0 +) +declText (MLText +uid 3299,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,7000,63500,7800" +st "A_OTR : std_logic_vector(3 DOWNTO 0)" +) +) +*82 (HdlText +uid 3300,0 +optionalChildren [ +*83 (EmbeddedText +uid 3306,0 +commentText (CommentText +uid 3307,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3308,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "32000,96000,44000,102000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3309,0 +va (VaSet +) +xt "32200,96200,44200,102200" +st " +-- ADC_DATA 3 +adc_data_array (0) <= A0_D; +adc_data_array (1) <= A1_D; +adc_data_array (2) <= A2_D; +adc_data_array (3) <= A3_D; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 3301,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "24000,94000,32000,102000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3302,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*84 (Text +uid 3303,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,95000,31750,96000" +st "ADC_DATA" +blo "27150,95800" +tm "HdlTextNameMgr" +) +*85 (Text +uid 3304,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,96000,27950,97000" +st "3" +blo "27150,96800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3305,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "24250,100250,25750,101750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*86 (PortIoIn +uid 3310,0 +shape (CompositeShape +uid 3311,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3312,0 +sl 0 +ro 270 +xt "19000,94625,20500,95375" +) +(Line +uid 3313,0 +sl 0 +ro 270 +xt "20500,95000,21000,95000" +pts [ +"20500,95000" +"21000,95000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3314,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3315,0 +va (VaSet +) +xt "15700,94500,18000,95500" +st "A0_D" +ju 2 +blo "18000,95300" +tm "WireNameMgr" +) +) +) +*87 (PortIoIn +uid 3332,0 +shape (CompositeShape +uid 3333,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3334,0 +sl 0 +ro 270 +xt "19000,95625,20500,96375" +) +(Line +uid 3335,0 +sl 0 +ro 270 +xt "20500,96000,21000,96000" +pts [ +"20500,96000" +"21000,96000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3336,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3337,0 +va (VaSet +) +xt "15700,95500,18000,96500" +st "A1_D" +ju 2 +blo "18000,96300" +tm "WireNameMgr" +) +) +) +*88 (PortIoIn +uid 3338,0 +shape (CompositeShape +uid 3339,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3340,0 +sl 0 +ro 270 +xt "19000,96625,20500,97375" +) +(Line +uid 3341,0 +sl 0 +ro 270 +xt "20500,97000,21000,97000" +pts [ +"20500,97000" +"21000,97000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3342,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3343,0 +va (VaSet +) +xt "15700,96500,18000,97500" +st "A2_D" +ju 2 +blo "18000,97300" +tm "WireNameMgr" +) +) +) +*89 (PortIoIn +uid 3344,0 +shape (CompositeShape +uid 3345,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3346,0 +sl 0 +ro 270 +xt "19000,97625,20500,98375" +) +(Line +uid 3347,0 +sl 0 +ro 270 +xt "20500,98000,21000,98000" +pts [ +"20500,98000" +"21000,98000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3348,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3349,0 +va (VaSet +) +xt "15700,97500,18000,98500" +st "A3_D" +ju 2 +blo "18000,98300" +tm "WireNameMgr" +) +) +) +*90 (Net +uid 3374,0 +decl (Decl +n "A0_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 1 +suid 79,0 +) +declText (MLText +uid 3375,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,3800,64000,4600" +st "A0_D : std_logic_vector(11 DOWNTO 0)" +) +) +*91 (Net +uid 3376,0 +decl (Decl +n "A1_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 2 +suid 80,0 +) +declText (MLText +uid 3377,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,4600,64000,5400" +st "A1_D : std_logic_vector(11 DOWNTO 0)" +) +) +*92 (Net +uid 3378,0 +decl (Decl +n "A2_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 3 +suid 81,0 +) +declText (MLText +uid 3379,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,5400,64000,6200" +st "A2_D : std_logic_vector(11 DOWNTO 0)" +) +) +*93 (Net +uid 3380,0 +decl (Decl +n "A3_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 4 +suid 82,0 +) +declText (MLText +uid 3381,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,6200,64000,7000" +st "A3_D : std_logic_vector(11 DOWNTO 0)" +) +) +*94 (HdlText +uid 3394,0 +optionalChildren [ +*95 (EmbeddedText +uid 3400,0 +commentText (CommentText +uid 3401,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3402,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "32000,114000,44000,120000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3403,0 +va (VaSet +) +xt "32200,114200,44200,120200" +st " +-- SRCLK 4 +D0_SRCLK <= SRCLK; +D1_SRCLK <= SRCLK; +D2_SRCLK <= SRCLK; +D3_SRCLK <= SRCLK; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 3395,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "24000,112000,32000,120000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3396,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*96 (Text +uid 3397,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,113000,30350,114000" +st "SRCLK" +blo "27150,113800" +tm "HdlTextNameMgr" +) +*97 (Text +uid 3398,0 +va (VaSet +font "Arial,8,1" +) +xt "27150,114000,27950,115000" +st "4" +blo "27150,114800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3399,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "24250,118250,25750,119750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*98 (Net +uid 3460,0 +decl (Decl +n "D0_SRCLK" +t "STD_LOGIC" +o 17 +suid 87,0 +) +declText (MLText +uid 3461,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,16600,53500,17400" +st "D0_SRCLK : STD_LOGIC" +) +) +*99 (Net +uid 3462,0 +decl (Decl +n "D1_SRCLK" +t "STD_LOGIC" +o 18 +suid 88,0 +) +declText (MLText +uid 3463,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,17400,53500,18200" +st "D1_SRCLK : STD_LOGIC" +) +) +*100 (Net +uid 3464,0 +decl (Decl +n "D2_SRCLK" +t "STD_LOGIC" +o 19 +suid 89,0 +) +declText (MLText +uid 3465,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,18200,53500,19000" +st "D2_SRCLK : STD_LOGIC" +) +) +*101 (Net +uid 3466,0 +decl (Decl +n "D3_SRCLK" +t "STD_LOGIC" +o 20 +suid 90,0 +) +declText (MLText +uid 3467,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,19000,53500,19800" +st "D3_SRCLK : STD_LOGIC" +) +) +*102 (PortIoIn +uid 3476,0 +shape (CompositeShape +uid 3477,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3478,0 +sl 0 +ro 270 +xt "19000,104625,20500,105375" +) +(Line +uid 3479,0 +sl 0 +ro 270 +xt "20500,105000,21000,105000" +pts [ +"20500,105000" +"21000,105000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3480,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3481,0 +va (VaSet +) +xt "13400,104500,18000,105500" +st "D0_SROUT" +ju 2 +blo "18000,105300" +tm "WireNameMgr" +) +) +) +*103 (PortIoIn +uid 3482,0 +shape (CompositeShape +uid 3483,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3484,0 +sl 0 +ro 270 +xt "19000,105625,20500,106375" +) +(Line +uid 3485,0 +sl 0 +ro 270 +xt "20500,106000,21000,106000" +pts [ +"20500,106000" +"21000,106000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3486,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3487,0 +va (VaSet +) +xt "13400,105500,18000,106500" +st "D1_SROUT" +ju 2 +blo "18000,106300" +tm "WireNameMgr" +) +) +) +*104 (PortIoIn +uid 3488,0 +shape (CompositeShape +uid 3489,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3490,0 +sl 0 +ro 270 +xt "19000,106625,20500,107375" +) +(Line +uid 3491,0 +sl 0 +ro 270 +xt "20500,107000,21000,107000" +pts [ +"20500,107000" +"21000,107000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3492,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3493,0 +va (VaSet +) +xt "13400,106500,18000,107500" +st "D2_SROUT" +ju 2 +blo "18000,107300" +tm "WireNameMgr" +) +) +) +*105 (PortIoIn +uid 3494,0 +shape (CompositeShape +uid 3495,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3496,0 +sl 0 +ro 270 +xt "19000,107625,20500,108375" +) +(Line +uid 3497,0 +sl 0 +ro 270 +xt "20500,108000,21000,108000" +pts [ +"20500,108000" +"21000,108000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3498,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3499,0 +va (VaSet +) +xt "13400,107500,18000,108500" +st "D3_SROUT" +ju 2 +blo "18000,108300" +tm "WireNameMgr" +) +) +) +*106 (Net +uid 3500,0 +decl (Decl +n "D0_SROUT" +t "std_logic" +o 6 +suid 91,0 +) +declText (MLText +uid 3501,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,7800,53500,8600" +st "D0_SROUT : std_logic" +) +) +*107 (Net +uid 3502,0 +decl (Decl +n "D1_SROUT" +t "std_logic" +o 7 +suid 92,0 +) +declText (MLText +uid 3503,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,8600,53500,9400" +st "D1_SROUT : std_logic" +) +) +*108 (Net +uid 3504,0 +decl (Decl +n "D2_SROUT" +t "std_logic" +o 8 +suid 93,0 +) +declText (MLText +uid 3505,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,9400,53500,10200" +st "D2_SROUT : std_logic" +) +) +*109 (Net +uid 3506,0 +decl (Decl +n "D3_SROUT" +t "std_logic" +o 9 +suid 94,0 +) +declText (MLText +uid 3507,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,10200,53500,11000" +st "D3_SROUT : std_logic" +) +) +*110 (PortIoOut +uid 3508,0 +shape (CompositeShape +uid 3509,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3510,0 +sl 0 +ro 90 +xt "4000,133625,5500,134375" +) +(Line +uid 3511,0 +sl 0 +ro 90 +xt "5500,134000,6000,134000" +pts [ +"6000,134000" +"5500,134000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3512,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3513,0 +va (VaSet +) +xt "1100,133500,3000,134500" +st "D_A" +ju 2 +blo "3000,134300" +tm "WireNameMgr" +) +) +) +*111 (Net +uid 3514,0 +decl (Decl +n "D_A" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 24 +suid 95,0 +i "(others => '0')" +) +declText (MLText +uid 3515,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,22200,74000,23000" +st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0')" +) +) +*112 (PortIoOut +uid 3516,0 +shape (CompositeShape +uid 3517,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3518,0 +sl 0 +ro 90 +xt "19000,109625,20500,110375" +) +(Line +uid 3519,0 +sl 0 +ro 90 +xt "20500,110000,21000,110000" +pts [ +"21000,110000" +"20500,110000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3520,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3521,0 +va (VaSet +) +xt "14500,109500,18000,110500" +st "DWRITE" +ju 2 +blo "18000,110300" +tm "WireNameMgr" +) +) +) +*113 (Net +uid 3522,0 +decl (Decl +n "DWRITE" +t "std_logic" +o 23 +suid 96,0 +i "'0'" +) +declText (MLText +uid 3523,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,21400,68000,22200" +st "DWRITE : std_logic := '0'" +) +) +*114 (PortIoOut +uid 3536,0 +shape (CompositeShape +uid 3537,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3538,0 +sl 0 +ro 270 +xt "111500,86625,113000,87375" +) +(Line +uid 3539,0 +sl 0 +ro 270 +xt "111000,87000,111500,87000" +pts [ +"111000,87000" +"111500,87000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3540,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3541,0 +va (VaSet +) +xt "114000,86500,117600,87500" +st "DAC_CS" +blo "114000,87300" +tm "WireNameMgr" +) +) +) +*115 (HdlText +uid 3542,0 +optionalChildren [ +*116 (EmbeddedText +uid 3612,0 +commentText (CommentText +uid 3613,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3614,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "88000,90000,100000,96000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3615,0 +va (VaSet +) +xt "88200,90200,100100,96200" +st " +-- T_CS 5 +T0_CS <= sensor_cs (0); +T1_CS <= sensor_cs (1); +T2_CS <= sensor_cs (2); +T3_CS <= sensor_cs (3); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 3543,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "100000,88000,108000,96000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3544,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*117 (Text +uid 3545,0 +va (VaSet +font "Arial,8,1" +) +xt "103150,89000,105550,90000" +st "T_CS" +blo "103150,89800" +tm "HdlTextNameMgr" +) +*118 (Text +uid 3546,0 +va (VaSet +font "Arial,8,1" +) +xt "103150,90000,103950,91000" +st "5" +blo "103150,90800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3547,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "100250,94250,101750,95750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*119 (PortIoOut +uid 3548,0 +shape (CompositeShape +uid 3549,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3550,0 +sl 0 +ro 270 +xt "111500,88625,113000,89375" +) +(Line +uid 3551,0 +sl 0 +ro 270 +xt "111000,89000,111500,89000" +pts [ +"111000,89000" +"111500,89000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3552,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3553,0 +va (VaSet +) +xt "114000,88500,116800,89500" +st "T0_CS" +blo "114000,89300" +tm "WireNameMgr" +) +) +) +*120 (PortIoOut +uid 3554,0 +shape (CompositeShape +uid 3555,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3556,0 +sl 0 +ro 270 +xt "111500,89625,113000,90375" +) +(Line +uid 3557,0 +sl 0 +ro 270 +xt "111000,90000,111500,90000" +pts [ +"111000,90000" +"111500,90000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3558,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3559,0 +va (VaSet +) +xt "114000,89500,116800,90500" +st "T1_CS" +blo "114000,90300" +tm "WireNameMgr" +) +) +) +*121 (PortIoOut +uid 3560,0 +shape (CompositeShape +uid 3561,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3562,0 +sl 0 +ro 270 +xt "111500,90625,113000,91375" +) +(Line +uid 3563,0 +sl 0 +ro 270 +xt "111000,91000,111500,91000" +pts [ +"111000,91000" +"111500,91000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3564,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3565,0 +va (VaSet +) +xt "114000,90500,116800,91500" +st "T2_CS" +blo "114000,91300" +tm "WireNameMgr" +) +) +) +*122 (PortIoOut +uid 3566,0 +shape (CompositeShape +uid 3567,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3568,0 +sl 0 +ro 270 +xt "111500,91625,113000,92375" +) +(Line +uid 3569,0 +sl 0 +ro 270 +xt "111000,92000,111500,92000" +pts [ +"111000,92000" +"111500,92000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3570,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3571,0 +va (VaSet +) +xt "114000,91500,116800,92500" +st "T3_CS" +blo "114000,92300" +tm "WireNameMgr" +) +) +) +*123 (Net +uid 3604,0 +decl (Decl +n "T0_CS" +t "std_logic" +o 38 +suid 101,0 +) +declText (MLText +uid 3605,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,33400,53500,34200" +st "T0_CS : std_logic" +) +) +*124 (Net +uid 3606,0 +decl (Decl +n "T1_CS" +t "std_logic" +o 39 +suid 102,0 +) +declText (MLText +uid 3607,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,34200,53500,35000" +st "T1_CS : std_logic" +) +) +*125 (Net +uid 3608,0 +decl (Decl +n "T2_CS" +t "std_logic" +o 40 +suid 103,0 +) +declText (MLText +uid 3609,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,35000,53500,35800" +st "T2_CS : std_logic" +) +) +*126 (Net +uid 3610,0 +decl (Decl +n "T3_CS" +t "std_logic" +o 41 +suid 104,0 +) +declText (MLText +uid 3611,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,35800,53500,36600" +st "T3_CS : std_logic" +) +) +*127 (PortIoOut +uid 3624,0 +shape (CompositeShape +uid 3625,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3626,0 +sl 0 +ro 270 +xt "111500,97625,113000,98375" +) +(Line +uid 3627,0 +sl 0 +ro 270 +xt "111000,98000,111500,98000" +pts [ +"111000,98000" +"111500,98000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3628,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3629,0 +va (VaSet +) +xt "113750,97500,116550,98500" +st "S_CLK" +blo "113750,98300" +tm "WireNameMgr" +) +) +) +*128 (Net +uid 3630,0 +decl (Decl +n "S_CLK" +t "std_logic" +o 37 +suid 105,0 +) +declText (MLText +uid 3631,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,32600,53500,33400" +st "S_CLK : std_logic" +) +) +*129 (Net +uid 3632,0 +decl (Decl +n "W_A" +t "std_logic_vector" +b "(9 DOWNTO 0)" +o 43 +suid 106,0 +) +declText (MLText +uid 3633,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,38200,63500,39000" +st "W_A : std_logic_vector(9 DOWNTO 0)" +) +) +*130 (Net +uid 3634,0 +decl (Decl +n "W_D" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 49 +suid 107,0 +) +declText (MLText +uid 3635,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,43000,64000,43800" +st "W_D : std_logic_vector(15 DOWNTO 0)" +) +) +*131 (Net +uid 3636,0 +decl (Decl +n "W_RES" +t "std_logic" +o 46 +suid 108,0 +i "'1'" +) +declText (MLText +uid 3637,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,40600,68000,41400" +st "W_RES : std_logic := '1'" +) +) +*132 (Net +uid 3638,0 +decl (Decl +n "W_RD" +t "std_logic" +o 45 +suid 109,0 +i "'1'" +) +declText (MLText +uid 3639,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,39800,68000,40600" +st "W_RD : std_logic := '1'" +) +) +*133 (Net +uid 3640,0 +decl (Decl +n "W_WR" +t "std_logic" +o 47 +suid 110,0 +i "'1'" +) +declText (MLText +uid 3641,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,41400,68000,42200" +st "W_WR : std_logic := '1'" +) +) +*134 (Net +uid 3642,0 +decl (Decl +n "W_INT" +t "std_logic" +o 13 +suid 111,0 +) +declText (MLText +uid 3643,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,13400,53500,14200" +st "W_INT : std_logic" +) +) +*135 (Net +uid 3644,0 +decl (Decl +n "W_CS" +t "std_logic" +o 44 +suid 112,0 +i "'1'" +) +declText (MLText +uid 3645,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,39000,68000,39800" +st "W_CS : std_logic := '1'" +) +) +*136 (PortIoInOut +uid 3674,0 +shape (CompositeShape +uid 3675,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Hexagon +uid 3676,0 +sl 0 +xt "111500,98625,113000,99375" +) +(Line +uid 3677,0 +sl 0 +xt "111000,99000,111500,99000" +pts [ +"111000,99000" +"111500,99000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3678,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3679,0 +va (VaSet +) +xt "114000,98500,116400,99500" +st "MISO" +blo "114000,99300" +tm "WireNameMgr" +) +) +) +*137 (Net +uid 3680,0 +decl (Decl +n "MOSI" +t "std_logic" +o 29 +suid 113,0 +i "'0'" +) +declText (MLText +uid 3681,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,26200,68000,27000" +st "MOSI : std_logic := '0'" +) +) +*138 (PortIoOut +uid 3688,0 +shape (CompositeShape +uid 3689,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3690,0 +sl 0 +ro 270 +xt "111500,99625,113000,100375" +) +(Line +uid 3691,0 +sl 0 +ro 270 +xt "111000,100000,111500,100000" +pts [ +"111000,100000" +"111500,100000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3692,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3693,0 +va (VaSet +) +xt "114000,99500,116400,100500" +st "MOSI" +blo "114000,100300" +tm "WireNameMgr" +) +) +) +*139 (Net +uid 3694,0 +decl (Decl +n "MISO" +t "std_logic" +preAdd 0 +posAdd 0 +o 48 +suid 114,0 +) +declText (MLText +uid 3695,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,42200,53500,43000" +st "MISO : std_logic" +) +) +*140 (HdlText +uid 3700,0 +optionalChildren [ +*141 (EmbeddedText +uid 3706,0 +commentText (CommentText +uid 3707,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3708,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "82000,102000,100000,118000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3709,0 +va (VaSet +) +xt "82200,102200,98600,118200" +st " +-- MISC 6 +TRG_V <= '0'; +RS485_C_RE <= '1'; +RS485_C_DE <= '0'; +RS485_E_RE <= '1'; +RS485_E_DE <= '0'; + +-- DENABLE <= '0'; -- domino wave stopped +-- DENABLE <= '1'; -- domino wave running + +SRIN <= 'Z'; +EE_CS <= '1'; +-- LEDs are low active +LED(0) <= '1'; +LED(1) <= '0'; -- on +LED(2) <= '1'; + + + + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 16000 +visibleWidth 18000 +) +) +) +] +shape (Rectangle +uid 3701,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "100000,102000,108000,115000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3702,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*142 (Text +uid 3703,0 +va (VaSet +font "Arial,8,1" +) +xt "103150,106000,105550,107000" +st "MISC" +blo "103150,106800" +tm "HdlTextNameMgr" +) +*143 (Text +uid 3704,0 +va (VaSet +font "Arial,8,1" +) +xt "103150,107000,103950,108000" +st "6" +blo "103150,107800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 3705,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "100250,113250,101750,114750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*144 (PortIoOut +uid 3710,0 +shape (CompositeShape +uid 3711,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3712,0 +sl 0 +ro 270 +xt "111500,102625,113000,103375" +) +(Line +uid 3713,0 +sl 0 +ro 270 +xt "111000,103000,111500,103000" +pts [ +"111000,103000" +"111500,103000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3714,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3715,0 +va (VaSet +) +xt "114000,102500,117000,103500" +st "TRG_V" +blo "114000,103300" +tm "WireNameMgr" +) +) +) +*145 (PortIoOut +uid 3716,0 +shape (CompositeShape +uid 3717,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3718,0 +sl 0 +ro 270 +xt "111500,103625,113000,104375" +) +(Line +uid 3719,0 +sl 0 +ro 270 +xt "111000,104000,111500,104000" +pts [ +"111000,104000" +"111500,104000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3720,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3721,0 +va (VaSet +) +xt "114000,103500,119600,104500" +st "RS485_C_RE" +blo "114000,104300" +tm "WireNameMgr" +) +) +) +*146 (PortIoOut +uid 3722,0 +shape (CompositeShape +uid 3723,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3724,0 +sl 0 +ro 270 +xt "111500,104625,113000,105375" +) +(Line +uid 3725,0 +sl 0 +ro 270 +xt "111000,105000,111500,105000" +pts [ +"111000,105000" +"111500,105000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3726,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3727,0 +va (VaSet +) +xt "114000,104500,119600,105500" +st "RS485_C_DE" +blo "114000,105300" +tm "WireNameMgr" +) +) +) +*147 (PortIoOut +uid 3728,0 +shape (CompositeShape +uid 3729,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3730,0 +sl 0 +ro 270 +xt "111500,105625,113000,106375" +) +(Line +uid 3731,0 +sl 0 +ro 270 +xt "111000,106000,111500,106000" +pts [ +"111000,106000" +"111500,106000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3732,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3733,0 +va (VaSet +) +xt "114000,105500,119500,106500" +st "RS485_E_RE" +blo "114000,106300" +tm "WireNameMgr" +) +) +) +*148 (PortIoOut +uid 3734,0 +shape (CompositeShape +uid 3735,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3736,0 +sl 0 +ro 270 +xt "111500,106625,113000,107375" +) +(Line +uid 3737,0 +sl 0 +ro 270 +xt "111000,107000,111500,107000" +pts [ +"111000,107000" +"111500,107000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3738,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3739,0 +va (VaSet +) +xt "114000,106500,119500,107500" +st "RS485_E_DE" +blo "114000,107300" +tm "WireNameMgr" +) +) +) +*149 (PortIoOut +uid 3740,0 +shape (CompositeShape +uid 3741,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3742,0 +sl 0 +ro 270 +xt "111500,120625,113000,121375" +) +(Line +uid 3743,0 +sl 0 +ro 270 +xt "111000,121000,111500,121000" +pts [ +"111000,121000" +"111500,121000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3744,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3745,0 +va (VaSet +) +xt "114000,120500,118000,121500" +st "DENABLE" +blo "114000,121300" +tm "WireNameMgr" +) +) +) +*150 (PortIoOut +uid 3746,0 +shape (CompositeShape +uid 3747,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3748,0 +sl 0 +ro 270 +xt "111500,108625,113000,109375" +) +(Line +uid 3749,0 +sl 0 +ro 270 +xt "111000,109000,111500,109000" +pts [ +"111000,109000" +"111500,109000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3750,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3751,0 +va (VaSet +) +xt "114000,108500,116300,109500" +st "SRIN" +blo "114000,109300" +tm "WireNameMgr" +) +) +) +*151 (PortIoOut +uid 3752,0 +shape (CompositeShape +uid 3753,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3754,0 +sl 0 +ro 270 +xt "111500,109625,113000,110375" +) +(Line +uid 3755,0 +sl 0 +ro 270 +xt "111000,110000,111500,110000" +pts [ +"111000,110000" +"111500,110000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3756,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3757,0 +va (VaSet +) +xt "114000,109500,116900,110500" +st "EE_CS" +blo "114000,110300" +tm "WireNameMgr" +) +) +) +*152 (PortIoOut +uid 3758,0 +shape (CompositeShape +uid 3759,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3760,0 +sl 0 +ro 270 +xt "111500,110625,113000,111375" +) +(Line +uid 3761,0 +sl 0 +ro 270 +xt "111000,111000,111500,111000" +pts [ +"111000,111000" +"111500,111000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3762,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3763,0 +va (VaSet +) +xt "114000,110500,115900,111500" +st "LED" +blo "114000,111300" +tm "WireNameMgr" +) +) +) +*153 (Net +uid 3864,0 +decl (Decl +n "TRG_V" +t "std_logic" +o 42 +suid 126,0 +) +declText (MLText +uid 3865,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,37400,53500,38200" +st "TRG_V : std_logic" +) +) +*154 (Net +uid 3866,0 +decl (Decl +n "RS485_C_RE" +t "std_logic" +o 32 +suid 127,0 +) +declText (MLText +uid 3867,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,28600,53500,29400" +st "RS485_C_RE : std_logic" +) +) +*155 (Net +uid 3868,0 +decl (Decl +n "RS485_C_DE" +t "std_logic" +o 31 +suid 128,0 +) +declText (MLText +uid 3869,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,27800,53500,28600" +st "RS485_C_DE : std_logic" +) +) +*156 (Net +uid 3870,0 +decl (Decl +n "RS485_E_RE" +t "std_logic" +o 34 +suid 129,0 +) +declText (MLText +uid 3871,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,30200,53500,31000" +st "RS485_E_RE : std_logic" +) +) +*157 (Net +uid 3872,0 +decl (Decl +n "RS485_E_DE" +t "std_logic" +o 33 +suid 130,0 +) +declText (MLText +uid 3873,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,29400,53500,30200" +st "RS485_E_DE : std_logic" +) +) +*158 (Net +uid 3874,0 +decl (Decl +n "DENABLE" +t "std_logic" +o 22 +suid 131,0 +i "'0'" +) +declText (MLText +uid 3875,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,20600,68000,21400" +st "DENABLE : std_logic := '0'" +) +) +*159 (Net +uid 3876,0 +decl (Decl +n "SRIN" +t "std_logic" +o 36 +suid 132,0 +) +declText (MLText +uid 3877,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,31800,53500,32600" +st "SRIN : std_logic" +) +) +*160 (Net +uid 3878,0 +decl (Decl +n "EE_CS" +t "std_logic" +o 27 +suid 133,0 +) +declText (MLText +uid 3879,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,24600,53500,25400" +st "EE_CS : std_logic" +) +) +*161 (Net +uid 3880,0 +decl (Decl +n "LED" +t "std_logic_vector" +b "( 2 DOWNTO 0 )" +o 28 +suid 134,0 +i "(others => '1')" +) +declText (MLText +uid 3881,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,25400,74000,26200" +st "LED : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')" +) +) +*162 (PortIoOut +uid 3995,0 +shape (CompositeShape +uid 3996,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3997,0 +sl 0 +ro 90 +xt "19000,112625,20500,113375" +) +(Line +uid 3998,0 +sl 0 +ro 90 +xt "20500,113000,21000,113000" +pts [ +"21000,113000" +"20500,113000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3999,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4000,0 +va (VaSet +) +xt "13600,112500,18000,113500" +st "D0_SRCLK" +ju 2 +blo "18000,113300" +tm "WireNameMgr" +) +) +) +*163 (PortIoOut +uid 4001,0 +shape (CompositeShape +uid 4002,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4003,0 +sl 0 +ro 90 +xt "19000,113625,20500,114375" +) +(Line +uid 4004,0 +sl 0 +ro 90 +xt "20500,114000,21000,114000" +pts [ +"21000,114000" +"20500,114000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 4005,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4006,0 +va (VaSet +) +xt "13600,113500,18000,114500" +st "D1_SRCLK" +ju 2 +blo "18000,114300" +tm "WireNameMgr" +) +) +) +*164 (PortIoOut +uid 4007,0 +shape (CompositeShape +uid 4008,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4009,0 +sl 0 +ro 90 +xt "19000,114625,20500,115375" +) +(Line +uid 4010,0 +sl 0 +ro 90 +xt "20500,115000,21000,115000" +pts [ +"21000,115000" +"20500,115000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 4011,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4012,0 +va (VaSet +) +xt "13600,114500,18000,115500" +st "D2_SRCLK" +ju 2 +blo "18000,115300" +tm "WireNameMgr" +) +) +) +*165 (PortIoOut +uid 4013,0 +shape (CompositeShape +uid 4014,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4015,0 +sl 0 +ro 90 +xt "19000,115625,20500,116375" +) +(Line +uid 4016,0 +sl 0 +ro 90 +xt "20500,116000,21000,116000" +pts [ +"21000,116000" +"20500,116000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 4017,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4018,0 +va (VaSet +) +xt "13600,115500,18000,116500" +st "D3_SRCLK" +ju 2 +blo "18000,116300" +tm "WireNameMgr" +) +) +) +*166 (PortIoOut +uid 4916,0 +shape (CompositeShape +uid 4917,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4918,0 +sl 0 +ro 270 +xt "111500,119625,113000,120375" +) +(Line +uid 4919,0 +sl 0 +ro 270 +xt "111000,120000,111500,120000" +pts [ +"111000,120000" +"111500,120000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 4920,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4921,0 +va (VaSet +) +xt "114000,119500,115900,120500" +st "D_T" +blo "114000,120300" +tm "WireNameMgr" +) +) +) +*167 (Net +uid 5320,0 +decl (Decl +n "D_T" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 25 +suid 141,0 +i "(OTHERS => '0')" +) +declText (MLText +uid 5321,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,23000,74000,23800" +st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" +) +) +*168 (PortIoIn +uid 5650,0 +shape (CompositeShape +uid 5651,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5652,0 +sl 0 +ro 270 +xt "38000,123625,39500,124375" +) +(Line +uid 5653,0 +sl 0 +ro 270 +xt "39500,124000,40000,124000" +pts [ +"39500,124000" +"40000,124000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 5654,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5655,0 +va (VaSet +) +xt "33400,123500,37000,124500" +st "TEST_IN" +ju 2 +blo "37000,124300" +tm "WireNameMgr" +) +) +) +*169 (Net +uid 5662,0 +decl (Decl +n "TEST_IN" +t "std_logic" +o 11 +suid 142,0 +) +declText (MLText +uid 5663,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,11800,53500,12600" +st "TEST_IN : std_logic" +) +) +*170 (Net +uid 6138,0 +decl (Decl +n "TRG_OR" +t "std_logic" +o 54 +suid 146,0 +) +declText (MLText +uid 6139,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,47200,57000,48000" +st "SIGNAL TRG_OR : std_logic" +) +) +*171 (PortIoIn +uid 6781,0 +shape (CompositeShape +uid 6782,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 6783,0 +sl 0 +ro 270 +xt "91000,131625,92500,132375" +) +(Line +uid 6784,0 +sl 0 +ro 270 +xt "92500,132000,93000,132000" +pts [ +"92500,132000" +"93000,132000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 6785,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6786,0 +va (VaSet +) +xt "85800,131500,90000,132500" +st "D_PLLLCK" +ju 2 +blo "90000,132300" +tm "WireNameMgr" +) +) +) +*172 (Net +uid 6793,0 +decl (Decl +n "D_PLLLCK" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 10 +suid 152,0 +) +declText (MLText +uid 6794,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,11000,63500,11800" +st "D_PLLLCK : std_logic_vector(3 DOWNTO 0)" +) +) +*173 (PortIoOut +uid 6874,0 +shape (CompositeShape +uid 6875,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 6876,0 +sl 0 +ro 270 +xt "109500,131625,111000,132375" +) +(Line +uid 6877,0 +sl 0 +ro 270 +xt "109000,132000,109500,132000" +pts [ +"109000,132000" +"109500,132000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 6878,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6879,0 +va (VaSet +) +xt "112000,131500,114300,132500" +st "D_T2" +blo "112000,132300" +tm "WireNameMgr" +) +) +) +*174 (Net +uid 6886,0 +decl (Decl +n "D_T2" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 26 +suid 154,0 +i "(others => '0')" +) +declText (MLText +uid 6887,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,23800,74000,24600" +st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0')" +) +) +*175 (HdlText +uid 6888,0 +optionalChildren [ +*176 (EmbeddedText +uid 6894,0 +commentText (CommentText +uid 6895,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 6896,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "96000,128000,106000,131000" +) +oxt "0,0,18000,5000" +text (MLText +uid 6897,0 +va (VaSet +) +xt "96200,128200,104300,129200" +st " +D_T2 <= D_PLLLCK; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 3000 +visibleWidth 10000 +) +) +) +] +shape (Rectangle +uid 6889,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "99000,131000,102000,134000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 6890,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*177 (Text +uid 6891,0 +va (VaSet +font "Arial,8,1" +) +xt "100150,135000,101850,136000" +st "eb1" +blo "100150,135800" +tm "HdlTextNameMgr" +) +*178 (Text +uid 6892,0 +va (VaSet +font "Arial,8,1" +) +xt "100150,136000,100950,137000" +st "7" +blo "100150,136800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 6893,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "99250,132250,100750,133750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*179 (HdlText +uid 7092,0 +optionalChildren [ +*180 (EmbeddedText +uid 7098,0 +commentText (CommentText +uid 7099,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 7100,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "26000,137000,46000,143000" +) +oxt "0,0,18000,5000" +text (MLText +uid 7101,0 +va (VaSet +) +xt "26200,137200,40000,141200" +st " +-- eb2 8 +A1_T(3 downto 0) <= drs_channel_id; +D_A <= drs_channel_id; +A1_T(4) <= TRG_OR; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 20000 +) +) +) +] +shape (Rectangle +uid 7093,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "31000,131000,39000,137000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 7094,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*181 (Text +uid 7095,0 +va (VaSet +font "Arial,8,1" +) +xt "34150,135000,35850,136000" +st "eb2" +blo "34150,135800" +tm "HdlTextNameMgr" +) +*182 (Text +uid 7096,0 +va (VaSet +font "Arial,8,1" +) +xt "34150,136000,34950,137000" +st "8" +blo "34150,136800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 7097,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "31250,135250,32750,136750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*183 (PortIoOut +uid 7138,0 +shape (CompositeShape +uid 7139,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 7140,0 +sl 0 +ro 270 +xt "44500,131625,46000,132375" +) +(Line +uid 7141,0 +sl 0 +ro 270 +xt "44000,132000,44500,132000" +pts [ +"44000,132000" +"44500,132000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 7142,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7143,0 +va (VaSet +) +xt "47000,131500,49200,132500" +st "A1_T" +blo "47000,132300" +tm "WireNameMgr" +) +) +) +*184 (Net +uid 7150,0 +decl (Decl +n "A1_T" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 15 +suid 155,0 +i "(OTHERS => '0')" +) +declText (MLText +uid 7151,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,15000,74000,15800" +st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" +) +) +*185 (Net +uid 7485,0 +decl (Decl +n "dummy" +t "std_logic" +o 59 +suid 157,0 +) +declText (MLText +uid 7486,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,51200,57000,52000" +st "SIGNAL dummy : std_logic" +) +) +*186 (MWC +uid 7652,0 +optionalChildren [ +*187 (CptPort +uid 7632,0 +optionalChildren [ +*188 (Line +uid 7636,0 +layer 5 +sl 0 +va (VaSet +vasetType 3 +) +xt "91000,87000,91000,87000" +pts [ +"91000,87000" +"91000,87000" +] +) +] +ps "OnEdgeStrategy" +shape (Triangle +uid 7633,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,65535" +) +xt "90250,86625,91000,87375" +) +tg (CPTG +uid 7634,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 7635,0 +sl 0 +va (VaSet +isHidden 1 +font "arial,8,0" +) +xt "698200,401500,699000,402500" +st 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"WireNameMgr" +) +) +on &64 +) +*236 (Wire +uid 2423,0 +shape (OrthoPolyLine +uid 2424,0 +va (VaSet +vasetType 3 +) +xt "32000,113000,51250,113000" +pts [ +"51250,113000" +"32000,113000" +] +) +start &37 +end &94 +sat 32 +eat 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2427,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2428,0 +va (VaSet +isHidden 1 +) +xt "66250,109000,69250,110000" +st "SRCLK" +blo "66250,109800" +tm "WireNameMgr" +) +) +on &66 +) +*237 (Wire +uid 3009,0 +shape (OrthoPolyLine +uid 3010,0 +va (VaSet +vasetType 3 +) +xt "80750,98000,111000,98000" +pts [ +"80750,98000" +"111000,98000" +] +) +start &39 +end &127 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3011,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3012,0 +va (VaSet +isHidden 1 +) +xt "82000,97000,84800,98000" +st "S_CLK" +blo "82000,97800" +tm "WireNameMgr" +) +) +on &128 +) +*238 (Wire +uid 3015,0 +shape (OrthoPolyLine +uid 3016,0 +va (VaSet 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&189 +end &114 +ss 0 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3031,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3032,0 +va (VaSet +isHidden 1 +) +xt "95000,86000,98600,87000" +st "DAC_CS" +blo "95000,86800" +tm "WireNameMgr" +) +) +on &68 +) +*241 (Wire +uid 3218,0 +shape (OrthoPolyLine +uid 3219,0 +va (VaSet +vasetType 3 +) +xt "14000,78000,16000,78000" +pts [ +"14000,78000" +"16000,78000" +] +) +start &48 +end &202 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3220,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3221,0 +va (VaSet +isHidden 1 +) +xt "25000,77000,27100,78000" +st "TRG" +blo "25000,77800" +tm "WireNameMgr" +) +) +on &71 +) +*242 (Wire +uid 3260,0 +shape (OrthoPolyLine +uid 3261,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "21000,70000,24000,70000" +pts [ +"21000,70000" +"24000,70000" +] +) +start &69 +end &72 +sat 32 +eat 2 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3264,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3265,0 +va (VaSet +isHidden 1 +) +xt "23000,69000,25800,70000" +st "A_CLK" +blo "23000,69800" +tm "WireNameMgr" +) +) +on &76 +) +*243 (Wire +uid 3270,0 +shape (OrthoPolyLine +uid 3271,0 +va (VaSet +vasetType 3 +) +xt "32000,70000,51250,70000" +pts [ +"51250,70000" +"32000,70000" +] +) +start &25 +end &72 +sat 32 +eat 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 3274,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3275,0 +va (VaSet +) +xt "46000,69000,50500,70000" +st "CLK_25_PS" +blo "46000,69800" +tm "WireNameMgr" +) +) +on &77 +) +*244 (Wire +uid 3318,0 +shape (OrthoPolyLine +uid 3319,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "21000,95000,24000,95000" +pts [ +"21000,95000" +"24000,95000" +] +) +start &86 +end &82 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3322,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3323,0 +va (VaSet +isHidden 1 +) +xt "23000,94000,25300,95000" +st "A0_D" +blo "23000,94800" +tm "WireNameMgr" +) +) +on &90 +) +*245 (Wire +uid 3352,0 +shape (OrthoPolyLine +uid 3353,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "21000,96000,24000,96000" +pts [ +"21000,96000" +"24000,96000" +] +) +start &87 +end &82 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3356,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3357,0 +va (VaSet +isHidden 1 +) +xt "23000,95000,25300,96000" +st "A1_D" +blo "23000,95800" +tm "WireNameMgr" +) +) +on &91 +) +*246 (Wire +uid 3360,0 +shape (OrthoPolyLine +uid 3361,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "21000,97000,24000,97000" +pts [ +"21000,97000" +"24000,97000" +] +) +start &88 +end &82 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3364,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3365,0 +va (VaSet +isHidden 1 +) +xt "23000,96000,25300,97000" +st "A2_D" +blo "23000,96800" +tm "WireNameMgr" +) +) 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3 +) +xt "21000,114000,24000,114000" +pts [ +"21000,114000" +"24000,114000" +] +) +start &163 +end &94 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3442,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3443,0 +va (VaSet +isHidden 1 +) +xt "23000,113000,27400,114000" +st "D1_SRCLK" +blo "23000,113800" +tm "WireNameMgr" +) +) +on &99 +) +*250 (Wire +uid 3446,0 +shape (OrthoPolyLine +uid 3447,0 +va (VaSet +vasetType 3 +) +xt "21000,115000,24000,115000" +pts [ +"21000,115000" +"24000,115000" +] +) +start &164 +end &94 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3450,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3451,0 +va (VaSet +isHidden 1 +) +xt "23000,114000,27400,115000" +st "D2_SRCLK" +blo "23000,114800" +tm "WireNameMgr" +) +) +on &100 +) +*251 (Wire +uid 3454,0 +shape (OrthoPolyLine +uid 3455,0 +va (VaSet +vasetType 3 +) +xt "21000,116000,24000,116000" +pts [ +"21000,116000" +"24000,116000" +] +) +start &165 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+stg "STSignalDisplayStrategy" +f (Text +uid 3587,0 +va (VaSet +isHidden 1 +) +xt "108000,89000,110800,90000" +st "T1_CS" +blo "108000,89800" +tm "WireNameMgr" +) +) +on &124 +) +*254 (Wire +uid 3590,0 +shape (OrthoPolyLine +uid 3591,0 +va (VaSet +vasetType 3 +) +xt "108000,91000,111000,91000" +pts [ +"111000,91000" +"108000,91000" +] +) +start &121 +end &115 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3594,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3595,0 +va (VaSet +isHidden 1 +) +xt "108000,90000,110800,91000" +st "T2_CS" +blo "108000,90800" +tm "WireNameMgr" +) +) +on &125 +) +*255 (Wire +uid 3598,0 +shape (OrthoPolyLine +uid 3599,0 +va (VaSet +vasetType 3 +) +xt "108000,92000,111000,92000" +pts [ +"111000,92000" +"108000,92000" +] +) +start &122 +end &115 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3602,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3603,0 +va (VaSet +isHidden 1 +) +xt "108000,91000,110800,92000" +st "T3_CS" +blo "108000,91800" +tm "WireNameMgr" +) +) +on &126 +) +*256 (Wire +uid 3682,0 +shape (OrthoPolyLine +uid 3683,0 +va (VaSet +vasetType 3 +) +xt "80750,100000,111000,100000" +pts [ +"80750,100000" +"111000,100000" +] +) +start &42 +end &138 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3686,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3687,0 +va (VaSet +isHidden 1 +) +xt "82750,99000,85150,100000" +st "MOSI" +blo "82750,99800" +tm "WireNameMgr" +) +) +on &137 +) +*257 (Wire +uid 3778,0 +shape (OrthoPolyLine +uid 3779,0 +va (VaSet +vasetType 3 +) +xt "108000,103000,111000,103000" +pts [ +"111000,103000" +"108000,103000" +] +) +start &144 +end &140 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3782,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3783,0 +va (VaSet +isHidden 1 +) +xt "108000,102000,111000,103000" +st "TRG_V" +blo "108000,102800" +tm "WireNameMgr" +) +) +on &153 +) +*258 (Wire +uid 3786,0 +shape (OrthoPolyLine +uid 3787,0 +va (VaSet +vasetType 3 +) +xt "108000,104000,111000,104000" +pts [ +"111000,104000" +"108000,104000" +] +) +start &145 +end &140 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3790,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3791,0 +va (VaSet +isHidden 1 +) +xt "108000,103000,113600,104000" +st "RS485_C_RE" +blo "108000,103800" +tm "WireNameMgr" +) +) +on &154 +) +*259 (Wire +uid 3794,0 +shape (OrthoPolyLine +uid 3795,0 +va (VaSet +vasetType 3 +) +xt "108000,105000,111000,105000" +pts [ +"111000,105000" +"108000,105000" +] +) +start &146 +end &140 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3798,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3799,0 +va (VaSet +isHidden 1 +) +xt "108000,104000,113600,105000" +st "RS485_C_DE" +blo "108000,104800" +tm "WireNameMgr" +) +) +on &155 +) +*260 (Wire +uid 3802,0 +shape (OrthoPolyLine +uid 3803,0 +va (VaSet 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(MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *467 (MRCItem +litem &454 +pos 0 +dimension 20 +) +uid 97,0 +optionalChildren [ +*468 (MRCItem +litem &455 +pos 0 +dimension 20 +uid 98,0 +) +*469 (MRCItem +litem &456 +pos 1 +dimension 23 +uid 99,0 +) +*470 (MRCItem +litem &457 +pos 2 +hidden 1 +dimension 20 +uid 100,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 101,0 +optionalChildren [ +*471 (MRCItem +litem &458 +pos 0 +dimension 20 +uid 102,0 +) +*472 (MRCItem +litem &460 +pos 1 +dimension 50 +uid 103,0 +) +*473 (MRCItem +litem &461 +pos 2 +dimension 100 +uid 104,0 +) +*474 (MRCItem +litem &462 +pos 3 +dimension 100 +uid 105,0 +) +*475 (MRCItem +litem &463 +pos 4 +dimension 50 +uid 106,0 +) +*476 (MRCItem +litem &464 +pos 5 +dimension 50 +uid 107,0 +) +*477 (MRCItem +litem &465 +pos 6 +dimension 80 +uid 108,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 96,0 +vaOverrides [ +] +) +] +) +uid 82,0 +type 1 +) +activeModelName "BlockDiag" +) Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.info/Synthesis/Constraints/FAD_Testboard.ctr =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.info/Synthesis/Constraints/FAD_Testboard.ctr (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.info/Synthesis/Constraints/FAD_Testboard.ctr (revision 9841) @@ -0,0 +1,7 @@ +# set_vendor xilinx +# set_family spartan3adsp +# set_device 3sd3400a +# set_package fg676 +# set_speed -4 + + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.info/Synthesis/Constraints/FAD_Testboard.sdc =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.info/Synthesis/Constraints/FAD_Testboard.sdc (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.info/Synthesis/Constraints/FAD_Testboard.sdc (revision 9841) @@ -0,0 +1,7 @@ +# set_vendor xilinx +# set_family spartan3adsp +# set_device 3sd3400a +# set_package fg676 +# set_speed -4 + + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb (revision 9841) @@ -0,0 +1,4547 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +] +libraryRefs [ +"ieee" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 69,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 53,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "RSRLOAD" +t "std_logic" +o 35 +suid 11,0 +i "'0'" +) +) +uid 690,0 +) +*15 (LogPort +port (LogicalPort +decl (Decl +n "X_50M" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 14 +suid 15,0 +) +) +uid 1111,0 +) +*16 (LogPort +port (LogicalPort +decl (Decl +n "TRG" +t "STD_LOGIC" +o 12 +suid 16,0 +) +) +uid 1113,0 +) +*17 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "A_CLK" +t "std_logic_vector" +b "(3 downto 0)" +o 16 +suid 17,0 +) +) +uid 1115,0 +) +*18 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "OE_ADC" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 30 +suid 18,0 +) +) +uid 1155,0 +) +*19 (LogPort +port (LogicalPort +decl (Decl +n "A_OTR" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 5 +suid 19,0 +) +) +uid 1157,0 +) +*20 (LogPort +port (LogicalPort +decl (Decl +n "A0_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 1 +suid 20,0 +) +) +uid 1159,0 +) +*21 (LogPort +port (LogicalPort +decl (Decl +n "A1_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 2 +suid 21,0 +) +) +uid 1161,0 +) +*22 (LogPort +port (LogicalPort +decl (Decl +n "A2_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 3 +suid 22,0 +) +) +uid 1163,0 +) +*23 (LogPort +port (LogicalPort +decl (Decl +n "A3_D" +t "std_logic_vector" +b "(11 DOWNTO 0)" +o 4 +suid 23,0 +) +) +uid 1165,0 +) +*24 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "D0_SRCLK" +t "STD_LOGIC" +o 17 +suid 24,0 +) +) +uid 1220,0 +) +*25 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "D1_SRCLK" +t "STD_LOGIC" +o 18 +suid 25,0 +) +) +uid 1222,0 +) +*26 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "D2_SRCLK" +t "STD_LOGIC" +o 19 +suid 26,0 +) +) +uid 1224,0 +) +*27 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "D3_SRCLK" +t "STD_LOGIC" +o 20 +suid 27,0 +) +) +uid 1226,0 +) +*28 (LogPort +port (LogicalPort +decl (Decl +n "D0_SROUT" +t "std_logic" +o 6 +suid 28,0 +) +) +uid 1271,0 +) +*29 (LogPort +port (LogicalPort +decl (Decl +n "D1_SROUT" +t "std_logic" +o 7 +suid 29,0 +) +) +uid 1273,0 +) +*30 (LogPort +port (LogicalPort +decl (Decl +n "D2_SROUT" +t "std_logic" +o 8 +suid 30,0 +) +) +uid 1275,0 +) +*31 (LogPort +port (LogicalPort +decl (Decl +n "D3_SROUT" +t "std_logic" +o 9 +suid 31,0 +) +) +uid 1277,0 +) +*32 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "D_A" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 24 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"RightVerticalLayoutStrategy" +f (Text +uid 1240,0 +va (VaSet +) +xt "27600,87500,32000,88500" +st "D2_SRCLK" +ju 2 +blo "32000,88300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1241,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,16400,61500,17200" +st "D2_SRCLK : OUT STD_LOGIC ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "D2_SRCLK" +t "STD_LOGIC" +o 19 +suid 26,0 +) +) +) +*165 (CptPort +uid 1242,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1780,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,89625,33750,90375" +) +tg (CPTG +uid 1244,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1245,0 +va (VaSet +) +xt "27600,89500,32000,90500" +st "D3_SRCLK" +ju 2 +blo "32000,90300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1246,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,17200,61500,18000" +st "D3_SRCLK : OUT STD_LOGIC ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "D3_SRCLK" +t "STD_LOGIC" +o 20 +suid 27,0 +) +) +) +*166 (CptPort +uid 1282,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1283,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,33625,15000,34375" +) +tg (CPTG +uid 1284,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1285,0 +va (VaSet +) +xt "16000,33500,20600,34500" +st "D0_SROUT" +blo "16000,34300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1286,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6000,61500,6800" +st "D0_SROUT : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "D0_SROUT" +t "std_logic" +o 6 +suid 28,0 +) +) +) +*167 (CptPort +uid 1287,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1288,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,35625,15000,36375" +) +tg (CPTG +uid 1289,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1290,0 +va (VaSet +) +xt "16000,35500,20600,36500" +st "D1_SROUT" +blo "16000,36300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1291,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6800,61500,7600" +st "D1_SROUT : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "D1_SROUT" +t "std_logic" +o 7 +suid 29,0 +) +) +) +*168 (CptPort +uid 1292,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1293,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,37625,15000,38375" +) +tg (CPTG +uid 1294,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1295,0 +va (VaSet +) +xt "16000,37500,20600,38500" +st "D2_SROUT" +blo "16000,38300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1296,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,7600,61500,8400" +st "D2_SROUT : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "D2_SROUT" +t "std_logic" +o 8 +suid 30,0 +) +) +) +*169 (CptPort +uid 1297,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1298,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,39625,15000,40375" +) +tg (CPTG +uid 1299,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1300,0 +va (VaSet +) +xt "16000,39500,20600,40500" +st "D3_SROUT" +blo "16000,40300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1301,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,8400,61500,9200" +st "D3_SROUT : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "D3_SROUT" +t "std_logic" +o 9 +suid 31,0 +) +) +) +*170 (CptPort +uid 1302,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1303,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,29625,33750,30375" +) +tg (CPTG +uid 1304,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1305,0 +va (VaSet +) +xt "27500,29500,32000,30500" +st "D_A : (3:0)" +ju 2 +blo "32000,30300" +tm "CptPortNameMgr" +) +t (Text +uid 1306,0 +va (VaSet +) +xt "26300,30500,32000,31500" +st "(others => '0')" +ju 2 +blo "32000,31300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 1307,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,20400,82000,21200" +st "D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "D_A" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 24 +suid 32,0 +i "(others => '0')" +) +) +) +*171 (CptPort +uid 1308,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1309,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,31625,33750,32375" +) +tg (CPTG +uid 1310,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1311,0 +va (VaSet +) +xt "28500,31500,32000,32500" +st "DWRITE" +ju 2 +blo "32000,32300" +tm "CptPortNameMgr" +) +t (Text +uid 1312,0 +va (VaSet +) +xt "30800,32500,32000,33500" +st "'0'" +ju 2 +blo "32000,33300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 1313,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,19600,76000,20400" +st "DWRITE : OUT std_logic := '0' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "DWRITE" +t "std_logic" +o 23 +suid 33,0 +i "'0'" +) +) +) +*172 (CptPort +uid 1363,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1364,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,33625,33750,34375" +) +tg (CPTG +uid 1365,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1366,0 +va (VaSet +) +xt "28400,33500,32000,34500" +st "DAC_CS" +ju 2 +blo "32000,34300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1367,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,18000,61500,18800" +st "DAC_CS : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "DAC_CS" +t "std_logic" +o 21 +suid 34,0 +) +) +) +*173 (CptPort +uid 1368,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1369,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,35625,33750,36375" +) +tg (CPTG +uid 1370,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1371,0 +va (VaSet +) +xt "29200,35500,32000,36500" +st "T0_CS" +ju 2 +blo "32000,36300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1372,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,31600,61500,32400" +st "T0_CS : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "T0_CS" +t "std_logic" +o 38 +suid 35,0 +) +) +) +*174 (CptPort +uid 1373,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1374,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,37625,33750,38375" +) +tg (CPTG +uid 1375,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1376,0 +va (VaSet +) +xt "29200,37500,32000,38500" +st "T1_CS" +ju 2 +blo "32000,38300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1377,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,32400,61500,33200" +st "T1_CS : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "T1_CS" +t "std_logic" +o 39 +suid 36,0 +) +) +) +*175 (CptPort +uid 1378,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1379,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,39625,33750,40375" +) +tg (CPTG +uid 1380,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1381,0 +va (VaSet +) +xt "29200,39500,32000,40500" +st "T2_CS" +ju 2 +blo "32000,40300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1382,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,33200,61500,34000" +st "T2_CS : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "T2_CS" +t "std_logic" +o 40 +suid 37,0 +) +) +) +*176 (CptPort +uid 1383,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1384,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,41625,33750,42375" +) +tg (CPTG +uid 1385,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1386,0 +va (VaSet +) +xt "29200,41500,32000,42500" +st "T3_CS" +ju 2 +blo "32000,42300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1387,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,34000,61500,34800" +st "T3_CS : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "T3_CS" +t "std_logic" +o 41 +suid 38,0 +) +) +) +*177 (CptPort +uid 1388,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1389,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,43625,33750,44375" +) +tg (CPTG +uid 1390,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1391,0 +va (VaSet +) +xt "29200,43500,32000,44500" +st "S_CLK" +ju 2 +blo "32000,44300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1392,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,30800,61500,31600" +st "S_CLK : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "S_CLK" +t "std_logic" +o 37 +suid 39,0 +) +) +) +*178 (CptPort +uid 1393,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1394,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,45625,33750,46375" +) +tg (CPTG +uid 1395,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1396,0 +va (VaSet +) +xt "27400,45500,32000,46500" +st "W_A : (9:0)" +ju 2 +blo "32000,46300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1397,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,36400,71500,37200" +st "W_A : OUT std_logic_vector (9 DOWNTO 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "W_A" +t "std_logic_vector" +b "(9 DOWNTO 0)" +o 44 +suid 40,0 +) +) +) +*179 (CptPort +uid 1398,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 1399,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,47625,33750,48375" +) +tg (CPTG +uid 1400,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1401,0 +va (VaSet +) +xt "26900,47500,32000,48500" +st "W_D : (15:0)" +ju 2 +blo "32000,48300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1402,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,41200,71000,42000" +st "W_D : INOUT std_logic_vector (15 DOWNTO 0)" +) +thePort (LogicalPort +m 2 +decl (Decl +n "W_D" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 50 +suid 41,0 +) +) +) +*180 (CptPort +uid 1403,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1404,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,49625,33750,50375" +) +tg (CPTG +uid 1405,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1406,0 +va (VaSet +) +xt "28900,49500,32000,50500" +st "W_RES" +ju 2 +blo "32000,50300" +tm "CptPortNameMgr" +) +t (Text +uid 1407,0 +va (VaSet +) +xt "30800,50500,32000,51500" +st "'1'" +ju 2 +blo "32000,51300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 1408,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,38800,76000,39600" +st "W_RES : OUT std_logic := '1' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "W_RES" +t "std_logic" +o 47 +suid 42,0 +i "'1'" +) +) +) +*181 (CptPort +uid 1409,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1410,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,51625,33750,52375" +) +tg (CPTG +uid 1411,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1412,0 +va (VaSet +) +xt "29300,51500,32000,52500" +st "W_RD" +ju 2 +blo "32000,52300" +tm "CptPortNameMgr" +) +t (Text +uid 1413,0 +va (VaSet +) +xt "30800,52500,32000,53500" +st "'1'" +ju 2 +blo "32000,53300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 1414,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,38000,76000,38800" +st "W_RD : OUT std_logic := '1' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "W_RD" +t "std_logic" +o 46 +suid 43,0 +i "'1'" +) +) +) +*182 (CptPort +uid 1415,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1416,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,53625,33750,54375" +) +tg (CPTG +uid 1417,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1418,0 +va (VaSet +) +xt "29200,53500,32000,54500" +st "W_WR" +ju 2 +blo "32000,54300" +tm "CptPortNameMgr" +) +t (Text +uid 1419,0 +va (VaSet +) +xt "30800,54500,32000,55500" +st "'1'" +ju 2 +blo "32000,55300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 1420,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,39600,76000,40400" +st "W_WR : OUT std_logic := '1' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "W_WR" +t "std_logic" +o 48 +suid 44,0 +i "'1'" +) +) +) +*183 (CptPort +uid 1421,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1422,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,41625,15000,42375" +) +tg (CPTG +uid 1423,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1424,0 +va (VaSet +) +xt "16000,41500,18800,42500" +st "W_INT" +blo "16000,42300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1425,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,11600,61500,12400" +st "W_INT : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "W_INT" +t "std_logic" +o 13 +suid 45,0 +) +) +) +*184 (CptPort +uid 1426,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1427,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,55625,33750,56375" +) +tg (CPTG +uid 1428,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1429,0 +va (VaSet +) +xt "29400,55500,32000,56500" +st "W_CS" +ju 2 +blo "32000,56300" +tm "CptPortNameMgr" +) +t (Text +uid 1430,0 +va (VaSet +) +xt "30800,56500,32000,57500" +st "'1'" +ju 2 +blo "32000,57300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 1431,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,37200,76000,38000" +st "W_CS : OUT std_logic := '1' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "W_CS" +t "std_logic" +o 45 +suid 46,0 +i "'1'" +) +) +) +*185 (CptPort +uid 1620,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1621,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,57625,33750,58375" +) +tg (CPTG +uid 1622,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1623,0 +va (VaSet +) +xt "29600,57500,32000,58500" +st "MOSI" +ju 2 +blo "32000,58300" +tm "CptPortNameMgr" +) +t (Text +uid 1624,0 +va (VaSet +) +xt "30800,58500,32000,59500" +st "'0'" +ju 2 +blo "32000,59300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 1625,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,24400,76000,25200" +st "MOSI : OUT std_logic := '0' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "MOSI" +t "std_logic" +o 29 +suid 47,0 +i "'0'" +) +) +) +*186 (CptPort +uid 1626,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 1627,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,59625,33750,60375" +) +tg (CPTG +uid 1628,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1629,0 +va (VaSet +) +xt "29600,59500,32000,60500" +st "MISO" +ju 2 +blo "32000,60300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1630,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,40400,61500,41200" +st "MISO : INOUT std_logic ;" +) +thePort (LogicalPort +m 2 +decl (Decl +n "MISO" +t "std_logic" +preAdd 0 +posAdd 0 +o 49 +suid 48,0 +) +) +) +*187 (CptPort +uid 1676,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1677,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,61625,33750,62375" +) +tg (CPTG +uid 1678,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1679,0 +va (VaSet +) +xt "29000,61500,32000,62500" +st "TRG_V" +ju 2 +blo "32000,62300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1680,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,35600,61500,36400" +st "TRG_V : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "TRG_V" +t "std_logic" +o 43 +suid 49,0 +) +) +) +*188 (CptPort +uid 1681,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1682,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,63625,33750,64375" +) +tg (CPTG +uid 1683,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1684,0 +va (VaSet +) +xt "26400,63500,32000,64500" +st "RS485_C_RE" +ju 2 +blo "32000,64300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1685,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,26800,61500,27600" +st "RS485_C_RE : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "RS485_C_RE" +t "std_logic" +o 32 +suid 50,0 +) +) +) +*189 (CptPort +uid 1686,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1687,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,65625,33750,66375" +) +tg (CPTG +uid 1688,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1689,0 +va (VaSet +) +xt "26400,65500,32000,66500" +st "RS485_C_DE" +ju 2 +blo "32000,66300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1690,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,26000,61500,26800" +st "RS485_C_DE : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "RS485_C_DE" +t "std_logic" +o 31 +suid 51,0 +) +) +) +*190 (CptPort +uid 1691,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1692,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,67625,33750,68375" +) +tg (CPTG +uid 1693,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1694,0 +va (VaSet +) +xt "26500,67500,32000,68500" +st "RS485_E_RE" +ju 2 +blo "32000,68300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1695,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,28400,61500,29200" +st "RS485_E_RE : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "RS485_E_RE" +t "std_logic" +o 34 +suid 52,0 +) +) +) +*191 (CptPort +uid 1696,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1697,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,69625,33750,70375" +) +tg (CPTG +uid 1698,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1699,0 +va (VaSet +) +xt "26500,69500,32000,70500" +st "RS485_E_DE" +ju 2 +blo "32000,70300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1700,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,27600,61500,28400" +st "RS485_E_DE : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "RS485_E_DE" +t "std_logic" +o 33 +suid 53,0 +) +) +) +*192 (CptPort +uid 1701,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1702,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,71625,33750,72375" +) +tg (CPTG +uid 1703,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1704,0 +va (VaSet +) +xt "28000,71500,32000,72500" +st "DENABLE" +ju 2 +blo "32000,72300" +tm "CptPortNameMgr" +) +t (Text +uid 1919,0 +va (VaSet +) +xt "30800,72500,32000,73500" +st "'0'" +ju 2 +blo "32000,73300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 1705,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,18800,76000,19600" +st "DENABLE : OUT std_logic := '0' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "DENABLE" +t "std_logic" +o 22 +suid 54,0 +i "'0'" +) +) +) +*193 (CptPort +uid 1706,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1707,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,73625,33750,74375" +) +tg (CPTG +uid 1708,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1709,0 +va (VaSet +) +xt "29700,73500,32000,74500" +st "SRIN" +ju 2 +blo "32000,74300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1710,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,30000,61500,30800" +st "SRIN : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "SRIN" +t "std_logic" +o 36 +suid 55,0 +) +) +) +*194 (CptPort +uid 1711,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1712,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,75625,33750,76375" +) +tg (CPTG +uid 1713,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1714,0 +va (VaSet +) +xt "29100,75500,32000,76500" +st "EE_CS" +ju 2 +blo "32000,76300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1715,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,22800,61500,23600" +st "EE_CS : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "EE_CS" +t "std_logic" +o 27 +suid 56,0 +) +) +) +*195 (CptPort +uid 2068,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2069,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,91625,33750,92375" +) +tg (CPTG +uid 2070,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2071,0 +va (VaSet +) +xt "27500,91500,32000,92500" +st "D_T : (7:0)" +ju 2 +blo "32000,92300" +tm "CptPortNameMgr" +) +t (Text +uid 2072,0 +va (VaSet +) +xt "25100,92500,32000,93500" +st "(OTHERS => '0')" +ju 2 +blo "32000,93300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 2073,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,21200,82000,22000" +st "D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "D_T" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 25 +suid 61,0 +i "(OTHERS => '0')" +) +) +) +*196 (CptPort +uid 2375,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2376,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,93625,33750,94375" +) +tg (CPTG +uid 2377,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2378,0 +va (VaSet +) +xt "27500,93500,32000,94500" +st "LED : (2:0)" +ju 2 +blo "32000,94300" +tm "CptPortNameMgr" +) +t (Text +uid 2379,0 +va (VaSet +) +xt "26300,94500,32000,95500" +st "(others => '1')" +ju 2 +blo "32000,95300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 2380,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,23600,82000,24400" +st "LED : OUT std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "LED" +t "std_logic_vector" +b "( 2 DOWNTO 0 )" +o 28 +suid 62,0 +i "(others => '1')" +) +) +) +*197 (CptPort +uid 2919,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2920,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,45625,15000,46375" +) +tg (CPTG +uid 2921,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2922,0 +va (VaSet +) +xt "16000,45500,22800,46500" +st "D_PLLLCK : (3:0)" +blo "16000,46300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2923,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,9200,71500,10000" +st "D_PLLLCK : IN std_logic_vector (3 DOWNTO 0) ;" +) +thePort (LogicalPort +decl (Decl +n "D_PLLLCK" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 10 +suid 64,0 +) +) +) +*198 (CptPort +uid 2949,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2950,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,95625,33750,96375" +) +tg (CPTG +uid 2951,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2952,0 +va (VaSet +) +xt "27100,95500,32000,96500" +st "D_T2 : (3:0)" +ju 2 +blo "32000,96300" +tm "CptPortNameMgr" +) +t (Text +uid 2953,0 +va (VaSet +) +xt "26300,96500,32000,97500" +st "(others => '0')" +ju 2 +blo "32000,97300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 2954,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,22000,82000,22800" +st "D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "D_T2" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 26 +suid 65,0 +i "(others => '0')" +) +) +) +*199 (CptPort +uid 3026,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3027,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,97625,33750,98375" +) +tg (CPTG +uid 3028,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3029,0 +va (VaSet +) +xt "27200,97500,32000,98500" +st "A1_T : (7:0)" +ju 2 +blo "32000,98300" +tm "CptPortNameMgr" +) +t (Text +uid 3123,0 +va (VaSet +) +xt "25100,98500,32000,99500" +st "(OTHERS => '0')" +ju 2 +blo "32000,99300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 3030,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,13200,82000,14000" +st "A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "A1_T" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 15 +suid 66,0 +i "(OTHERS => '0')" +) +) +) +*200 (CptPort +uid 3318,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3319,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,47625,15000,48375" +) +tg (CPTG +uid 3320,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3321,0 +va (VaSet +) +xt "16000,47500,19600,48500" +st "TEST_IN" +blo "16000,48300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 3322,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10000,61500,10800" +st "TEST_IN : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "TEST_IN" +t "std_logic" +o 11 +suid 68,0 +) +) +) +*201 (CptPort +uid 3348,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3349,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33000,99625,33750,100375" +) +tg (CPTG +uid 3350,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3351,0 +va (VaSet +) +xt "27500,99500,32000,100500" +st "TEST_OUT" +ju 2 +blo "32000,100300" +tm "CptPortNameMgr" +) +t (Text +uid 3399,0 +va (VaSet +) +xt "30800,100500,32000,101500" +st "'0'" +ju 2 +blo "32000,101300" +tm "InitValueDelayMgr" +) +) +dt (MLText +uid 3352,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,34800,76000,35600" +st "TEST_OUT : OUT std_logic := '0' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "TEST_OUT" +t "std_logic" +o 42 +suid 69,0 +i "'0'" +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,101000" +) +oxt "15000,6000,33000,26000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,28400,16000" +st "FACT_FAD_lib" +blo "22200,15800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,26900,17000" +st "FAD_Board" +blo "22200,16800" +) +) +gi *202 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +*203 (Grouping +uid 16,0 +optionalChildren [ +*204 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48000,45500,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*205 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,44000,56200,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*206 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,46000,46200,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*207 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,46000,34300,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*208 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,45200,62400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*209 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,44000,61700,45000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*210 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "39700,44000,45300,46000" +st " +TU Dortmund +Physik / EE +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*211 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,47000,34300,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*212 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,48000,34900,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*213 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,47000,49400,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *214 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*215 (Text +uid 49,0 +va (VaSet +font "Arial,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*216 (MLText +uid 50,0 +va (VaSet +) +xt "0,1000,10900,4000" +st "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all;" +tm "PackageList" +) +] +) +windowSize "0,0,1015,690" +viewArea "0,0,0,0" +cachedDiagramExtent "0,0,0,0" +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text 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/firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/_symbol.sb._fpf (revision 9841) @@ -0,0 +1,3 @@ +INCLUDE list { + DEFAULT atom 1 +} Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd (revision 9841) @@ -0,0 +1,19991 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "IEEE" +unitName "STD_LOGIC_ARITH" +) +(DmPackageRef +library "ieee" +unitName "STD_LOGIC_UNSIGNED" +) +(DmPackageRef +library "fact_fad_lib" +unitName "fad_definitions" +) +(DmPackageRef +library "UNISIM" +unitName "VComponents" +) +(DmPackageRef +library "IEEE" +unitName "NUMERIC_STD" +) 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"148000,54625,148750,55375" +) +tg (CPTG +uid 1572,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1573,0 +va (VaSet +) +xt "145900,54500,147000,55500" +st "rd" +ju 2 +blo "147000,55300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "rd" +t "std_logic" +preAdd 0 +posAdd 0 +o 8 +suid 8,0 +i "'1'" +) +) +) +*75 (CptPort +uid 1574,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1575,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,55625,148750,56375" +) +tg (CPTG +uid 1576,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1577,0 +va (VaSet +) +xt "145800,55500,147000,56500" +st "int" +ju 2 +blo "147000,56300" +) +) +thePort (LogicalPort +decl (Decl +n "int" +t "std_logic" +preAdd 0 +posAdd 0 +o 9 +suid 9,0 +) +) +) +*76 (CptPort +uid 1578,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1579,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,69625,127000,70375" +) +tg (CPTG +uid 1580,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1581,0 +va (VaSet +) +xt "128000,69500,135900,70500" +st "write_length : (16:0)" +blo "128000,70300" +) +) +thePort (LogicalPort +decl (Decl +n "write_length" +t "std_logic_vector" +b "(16 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 10 +suid 10,0 +) +) +) +*77 (CptPort +uid 1582,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1583,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,70625,127000,71375" +) +tg (CPTG +uid 1584,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1585,0 +va (VaSet +) +xt "128000,70500,144300,71500" +st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)" +blo "128000,71300" +) +) +thePort (LogicalPort +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 11 +suid 11,0 +) +) +) +*78 (CptPort +uid 1586,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1587,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,54625,127000,55375" +) +tg (CPTG +uid 1588,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1589,0 +va (VaSet +) +xt "128000,54500,134500,55500" +st "ram_data : (15:0)" +blo "128000,55300" +) +) +thePort (LogicalPort +decl (Decl +n "ram_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 12 +suid 12,0 +) +) +) +*79 (CptPort +uid 1590,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1591,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,53625,127000,54375" +) +tg (CPTG +uid 1592,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1593,0 +va (VaSet +) +xt "128000,53500,142400,54500" +st "ram_addr : (RAM_ADDR_WIDTH-1:0)" +blo "128000,54300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "ram_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 13 +suid 13,0 +) +) +) +*80 (CptPort +uid 1594,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1595,0 +ro 90 +va (VaSet +vasetType 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"VerticalLayoutStrategy" +f (Text +uid 2229,0 +va (VaSet +) +xt "128000,73500,134800,74500" +st "write_header_flag" +blo "128000,74300" +) +) +thePort (LogicalPort +decl (Decl +n "write_header_flag" +t "std_logic" +o 17 +suid 19,0 +) +) +) +*85 (CptPort +uid 5216,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5217,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,70625,148750,71375" +) +tg (CPTG +uid 5218,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5219,0 +va (VaSet +) +xt "143000,70500,147000,71500" +st "led : (7:0)" +ju 2 +blo "147000,71300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 DOWNTO 0)" +posAdd 0 +o 7 +suid 22,0 +i "(OTHERS => '0')" +) +) +) +*86 (CptPort +uid 5275,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5276,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,58625,127000,59375" +) +tg (CPTG +uid 5277,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5278,0 +va (VaSet +) +xt "128000,58500,131600,59500" +st "s_trigger" +blo "128000,59300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "s_trigger" +t "std_logic" +o 20 +suid 23,0 +i "'0'" +) +) +) +*87 (CptPort +uid 5924,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5925,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,78625,127000,79375" +) +tg (CPTG +uid 5926,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5927,0 +va (VaSet +) +xt "128000,78500,135000,79500" +st "config_addr : (7:0)" +blo "128000,79300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(7 downto 0)" +o 23 +suid 24,0 +) +) +) +*88 (CptPort +uid 5928,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5929,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,83625,127000,84375" +) +tg (CPTG +uid 5930,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5931,0 +va (VaSet +) +xt "128000,83500,132800,84500" +st "config_busy" +blo "128000,84300" +) +) +thePort (LogicalPort +decl (Decl +n "config_busy" +t "std_logic" +o 27 +suid 25,0 +) +) +) +*89 (CptPort +uid 5932,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 6051,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,79625,127000,80375" +) +tg (CPTG +uid 5934,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5935,0 +va (VaSet +) +xt "128000,79500,135700,80500" +st "config_data : (15:0)" +blo "128000,80300" +) +) +thePort (LogicalPort +m 2 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 downto 0)" +o 24 +suid 26,0 +i "(others => 'Z')" +) +) +) +*90 (CptPort +uid 5936,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5937,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,60625,127000,61375" +) +tg (CPTG +uid 5938,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5939,0 +va (VaSet +) +xt "128000,60500,133600,61500" +st "config_started" +blo "128000,61300" +) +) +thePort (LogicalPort +decl (Decl +n "config_started" +t "std_logic" +o 22 +suid 27,0 +) +) +) +*91 (CptPort +uid 5940,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5941,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,81625,127000,82375" +) +tg (CPTG +uid 5942,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5943,0 +va (VaSet +) +xt "128000,81500,133300,82500" +st "config_wr_en" +blo "128000,82300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_wr_en" +t "std_logic" +o 25 +suid 28,0 +i "'0'" +) +) +) +*92 (CptPort +uid 5944,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5945,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,59625,127000,60375" +) +tg (CPTG +uid 5946,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5947,0 +va (VaSet +) +xt "128000,59500,132600,60500" +st "new_config" +blo "128000,60300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "new_config" +t "std_logic" +o 21 +suid 29,0 +i "'0'" +) +) +) +*93 (CptPort +uid 5970,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5971,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,82625,127000,83375" +) +tg (CPTG +uid 5972,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5973,0 +va (VaSet +) +xt "128000,82500,133200,83500" +st "config_rd_en" +blo "128000,83300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_rd_en" +t "std_logic" +o 26 +suid 30,0 +i "'0'" +) +) +) +*94 (CptPort +uid 6356,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6357,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,74625,148750,75375" +) +tg (CPTG +uid 6358,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6359,0 +va (VaSet +) +xt "144000,74500,147000,75500" +st "denable" +ju 2 +blo "147000,75300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "denable" +t "std_logic" +eolc "-- default domino wave off" +posAdd 0 +o 28 +suid 31,0 +i "'0'" +) +) +) +*95 (CptPort +uid 6446,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6447,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,75625,148750,76375" +) +tg (CPTG +uid 6448,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6449,0 +va (VaSet +) +xt "141600,75500,147000,76500" +st "dwrite_enable" +ju 2 +blo "147000,76300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "dwrite_enable" +t "std_logic" +eolc "-- default DWRITE low." +preAdd 0 +posAdd 0 +o 29 +suid 32,0 +i "'0'" +) +) +) +*96 (CptPort +uid 8406,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8407,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,74625,127000,75375" +) +tg (CPTG +uid 8408,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8409,0 +va (VaSet +) +xt "128000,74500,133600,75500" +st "data_valid_ack" +blo "128000,75300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "data_valid_ack" +t "std_logic" +o 15 +suid 34,0 +i "'0'" +) +) +) +*97 (CptPort +uid 8748,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8749,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,76625,148750,77375" +) +tg (CPTG +uid 8750,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8751,0 +va (VaSet +) +xt "142300,76500,147000,77500" +st "sclk_enable" +ju 2 +blo "147000,77300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sclk_enable" +t "std_logic" +eolc "-- default DWRITE HIGH." +posAdd 0 +o 30 +suid 35,0 +i "'1'" +) +) +) +] +shape (Rectangle +uid 1607,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "127000,51000,148000,87000" +) +oxt "43000,2000,56000,22000" +ttg (MlTextGroup +uid 1608,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*98 (Text +uid 1609,0 +va (VaSet +font "Arial,8,1" +) +xt "126700,87000,132900,88000" +st "FACT_FAD_lib" +blo "126700,87800" +tm "BdLibraryNameMgr" +) +*99 (Text +uid 1610,0 +va (VaSet +font "Arial,8,1" +) +xt "126700,88000,132400,89000" +st "w5300_modul" +blo "126700,88800" +tm "CptNameMgr" +) +*100 (Text +uid 1611,0 +va (VaSet +font "Arial,8,1" +) +xt "126700,89000,133400,90000" +st "I_main_ethernet" +blo "126700,89800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1612,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1613,0 +text (MLText +uid 1614,0 +va (VaSet +font "Courier New,8,0" +) +xt "127000,50200,154500,51000" +st "RAM_ADDR_WIDTH = RAMADDRWIDTH64b+2 ( integer ) " +) +header "" +) +elements [ +(GiElement +name "RAM_ADDR_WIDTH" +type "integer" +value "RAMADDRWIDTH64b+2" +) +] +) +viewicon (ZoomableIcon +uid 1615,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "127250,85250,128750,86750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*101 (Net +uid 1680,0 +decl (Decl +n "crate_id" +t "std_logic_vector" +b "(1 downto 0)" +o 10 +suid 30,0 +) +declText (MLText +uid 1681,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,25400,-56500,26200" +st "crate_id : std_logic_vector(1 downto 0) +" +) +) +*102 (SaComponent +uid 1768,0 +optionalChildren [ +*103 (CptPort +uid 1760,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1761,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-7000,63625,-6250,64375" +) +tg (CPTG +uid 1762,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1763,0 +va (VaSet +) +xt "-14800,63500,-8000,64500" +st "trigger_id : (47:0)" +ju 2 +blo "-8000,64300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "trigger_id" +t "std_logic_vector" +b "(47 downto 0)" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*104 (CptPort +uid 1764,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1765,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-18750,63625,-18000,64375" +) +tg (CPTG +uid 1766,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1767,0 +va (VaSet +) +xt "-17000,63500,-14200,64500" +st "trigger" +blo "-17000,64300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "trigger" +t "std_logic" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +) +) +) +*105 (CptPort +uid 6207,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6208,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-18750,62625,-18000,63375" +) +tg (CPTG +uid 6209,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6210,0 +va (VaSet +) +xt "-17000,62500,-15700,63500" +st "clk" +blo "-17000,63300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "clk" +t "std_logic" +o 3 +suid 3,0 +) +) +) +] +shape (Rectangle +uid 1769,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "-18000,62000,-7000,67000" +) +oxt "32000,2000,43000,12000" +ttg (MlTextGroup +uid 1770,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*106 (Text +uid 1771,0 +va (VaSet +font "Arial,8,1" +) +xt "-6300,65000,300,66000" +st "FACT_FAD_LIB" +blo "-6300,65800" +tm "BdLibraryNameMgr" +) +*107 (Text +uid 1772,0 +va (VaSet +font "Arial,8,1" +) +xt "-6300,66000,300,67000" +st "trigger_counter" +blo "-6300,66800" +tm "CptNameMgr" +) +*108 (Text +uid 1773,0 +va (VaSet +font "Arial,8,1" +) +xt "-6300,67000,1300,68000" +st "I_main_ext_trigger" +blo "-6300,67800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1774,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1775,0 +text (MLText +uid 1776,0 +va (VaSet +font "Courier New,8,0" +) +xt "-18000,61000,-18000,61000" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 1777,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "-17750,65250,-16250,66750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sIVOD 1 +) +archFileType "UNKNOWN" +) +*109 (Net +uid 1981,0 +lang 2 +decl (Decl +n "trigger_id" +t "std_logic_vector" +b "(47 downto 0)" +preAdd 0 +posAdd 0 +o 81 +suid 34,0 +) +declText (MLText +uid 1982,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,84200,-52500,85000" +st "SIGNAL trigger_id : std_logic_vector(47 downto 0) +" +) +) +*110 (Net +uid 2297,0 +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAMADDRWIDTH64b-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 71 +suid 36,0 +) +declText (MLText +uid 2298,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,76200,-45000,77000" +st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) +" +) +) +*111 (SaComponent +uid 2311,0 +optionalChildren [ +*112 (CptPort +uid 2307,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2308,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,69625,72000,70375" +) +tg (CPTG +uid 2309,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2310,0 +va (VaSet +font "arial,8,0" +) +xt "73000,69500,91400,70500" +st "ram_start_addr : (RAM_ADDR_WIDTH_64B-1:0)" +blo "73000,70300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH_64B-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 18 +suid 1,0 +i "(others => '0')" +) +) +) +*113 (CptPort +uid 2351,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2352,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,67625,72000,68375" +) +tg (CPTG +uid 2353,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2354,0 +va (VaSet +font "arial,8,0" +) +xt "73000,67500,74300,68500" +st "clk" +blo "73000,68300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "clk" +t "std_logic" +o 1 +suid 2,0 +) +) +) +*114 (CptPort +uid 2361,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2362,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,76625,72000,77375" +) +tg (CPTG +uid 2363,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2364,0 +va (VaSet +font "arial,8,0" +) +xt "73000,76500,78100,77500" +st "config_ready" +blo "73000,77300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "config_ready" +t "std_logic" +o 6 +suid 5,0 +i "'0'" +) +) +) +*115 (CptPort +uid 2365,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2366,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,74625,72000,75375" +) +tg (CPTG +uid 2367,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2368,0 +va (VaSet +font "arial,8,0" +) +xt "73000,74500,77800,75500" +st "config_start" +blo "73000,75300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "config_start" +t "std_logic" +o 2 +suid 3,0 +) +) +) +*116 (CptPort +uid 2369,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2370,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,70625,72000,71375" +) +tg (CPTG +uid 2371,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2372,0 +va (VaSet +font "arial,8,0" +) +xt "73000,70500,78300,71500" +st "ram_write_ea" +blo "73000,71300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "ram_write_ea" +t "std_logic" +o 5 +suid 4,0 +i "'0'" +) +) +) +*117 (CptPort +uid 2373,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2374,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,71625,72000,72375" +) +tg (CPTG +uid 2375,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2376,0 +va (VaSet +font "arial,8,0" +) +xt "73000,71500,79300,72500" +st "ram_write_ready" +blo "73000,72300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "ram_write_ready" +t "std_logic" +o 3 +suid 12,0 +) +) +) +*118 (CptPort +uid 2377,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2378,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,77625,72000,78375" +) +tg (CPTG +uid 2379,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2380,0 +va (VaSet +font "arial,8,0" +) +xt "73000,77500,76000,78500" +st "roi_max" +blo "73000,78300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "roi_max" +t "roi_max_type" +posAdd 0 +o 8 +suid 14,0 +i "(others => conv_std_logic_vector (0, 11))" +) +) +) +*119 (CptPort +uid 2381,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2382,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,67625,103750,68375" +) +tg (CPTG +uid 2383,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2384,0 +va (VaSet +font "arial,8,0" +) +xt "98600,67500,102000,68500" +st "wiz_busy" +ju 2 +blo "102000,68300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "wiz_busy" +t "std_logic" +o 16 +suid 13,0 +) +) +) +*120 (CptPort +uid 2385,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2386,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,71625,103750,72375" +) +tg (CPTG +uid 2387,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2388,0 +va (VaSet +font "arial,8,0" +) +xt "90200,71500,102000,72500" +st "wiz_number_of_channels : (3:0)" +ju 2 +blo "102000,72300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_number_of_channels" +t "std_logic_vector" +b "(3 downto 0)" +o 12 +suid 6,0 +i "(others => '0')" +) +) +) +*121 (CptPort +uid 2389,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2390,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,70625,103750,71375" +) +tg (CPTG +uid 2391,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2392,0 +va (VaSet +font "arial,8,0" +) +xt "82100,70500,102000,71500" +st "wiz_ram_start_addr : (RAM_ADDR_WIDTH_16B-1:0)" +ju 2 +blo "102000,71300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH_16B-1 downto 0)" +preAdd 0 +o 10 +suid 7,0 +i "(others => '0')" +) +) +) +*122 (CptPort +uid 2393,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2394,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,68625,103750,69375" +) +tg (CPTG +uid 2395,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2396,0 +va (VaSet +font "arial,8,0" +) +xt "96900,68500,102000,69500" +st "wiz_write_ea" +ju 2 +blo "102000,69300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_ea" +t "std_logic" +o 13 +suid 8,0 +i "'0'" +) +) +) +*123 (CptPort +uid 2397,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2398,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,72625,103750,73375" +) +tg (CPTG +uid 2399,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2400,0 +va (VaSet +font "arial,8,0" +) +xt "96500,72500,102000,73500" +st "wiz_write_end" +ju 2 +blo "102000,73300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_end" +t "std_logic" +o 15 +suid 9,0 +i "'0'" +) +) +) +*124 (CptPort +uid 2401,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2402,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,73625,103750,74375" +) +tg (CPTG +uid 2403,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2404,0 +va (VaSet +font "arial,8,0" +) +xt "95400,73500,102000,74500" +st "wiz_write_header" +ju 2 +blo "102000,74300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_header" +t "std_logic" +o 14 +suid 10,0 +i "'0'" +) +) +) +*125 (CptPort +uid 2405,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2406,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,69625,103750,70375" +) +tg (CPTG +uid 2407,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2408,0 +va (VaSet +font "arial,8,0" +) +xt "92600,69500,102000,70500" +st "wiz_write_length : (16:0)" +ju 2 +blo "102000,70300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_length" +t "std_logic_vector" +b "(16 downto 0)" +o 11 +suid 11,0 +i "(others => '0')" +) +) +) +*126 (CptPort +uid 2454,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2455,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,84625,72000,85375" +) +tg (CPTG +uid 2456,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2457,0 +va (VaSet +font "arial,8,0" +) +xt "73000,84500,76400,85500" +st "roi_array" +blo "73000,85300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "roi_array" +t "roi_array_type" +o 4 +suid 15,0 +) +) +) +*127 (CptPort +uid 2628,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2629,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,78625,72000,79375" +) +tg (CPTG +uid 2630,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2631,0 +va (VaSet +font "arial,8,0" +) +xt "73000,78500,82100,79500" +st "package_length : (15:0)" +blo "73000,79300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "package_length" +t "std_logic_vector" +b "(15 downto 0)" +o 9 +suid 18,0 +i "(others => '0')" +) +) +) +*128 (CptPort +uid 5991,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5992,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,75625,72000,76375" +) +tg (CPTG +uid 5993,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5994,0 +va (VaSet +font "arial,8,0" +) +xt "73000,75500,78600,76500" +st "config_started" +blo "73000,76300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "config_started" +t "std_logic" +o 7 +suid 21,0 +i "'0'" +) +) +) +*129 (CptPort +uid 8410,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8411,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,74625,103750,75375" +) +tg (CPTG +uid 8412,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8413,0 +va (VaSet +font "arial,8,0" +) +xt "99000,74500,102000,75500" +st "wiz_ack" +ju 2 +blo "102000,75300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "wiz_ack" +t "std_logic" +o 17 +suid 22,0 +) +) +) +] +shape (Rectangle +uid 2312,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "72000,67000,103000,87000" +) +oxt "15000,6000,23000,16000" +ttg (MlTextGroup +uid 2313,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*130 (Text +uid 2314,0 +va (VaSet +font "arial,8,1" +) +xt "72350,87000,78550,88000" +st "FACT_FAD_lib" +blo "72350,87800" +tm "BdLibraryNameMgr" +) +*131 (Text +uid 2315,0 +va (VaSet +font "arial,8,1" +) +xt "72350,88000,79650,89000" +st "memory_manager" +blo "72350,88800" +tm "CptNameMgr" +) +*132 (Text +uid 2316,0 +va (VaSet +font "arial,8,1" +) +xt "72350,89000,82850,90000" +st "I_main_memory_manager" +blo "72350,89800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 2317,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 2318,0 +text (MLText +uid 2319,0 +va (VaSet +font "Courier New,8,0" +) +xt "72000,65400,101500,67000" +st "RAM_ADDR_WIDTH_64B = RAMADDRWIDTH64b ( integer ) +RAM_ADDR_WIDTH_16B = RAMADDRWIDTH64b+2 ( integer ) " +) +header "" +) +elements [ +(GiElement +name "RAM_ADDR_WIDTH_64B" +type "integer" +value "RAMADDRWIDTH64b" +) +(GiElement +name "RAM_ADDR_WIDTH_16B" +type "integer" +value "RAMADDRWIDTH64b+2" +) +] +) +viewicon (ZoomableIcon +uid 2320,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "72250,85250,73750,86750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*133 (Net +uid 2468,0 +lang 2 +decl (Decl +n "wiz_busy" +t "std_logic" +o 84 +suid 38,0 +) +declText (MLText +uid 2469,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,86600,-62500,87400" +st "SIGNAL wiz_busy : std_logic +" +) +) +*134 (Net +uid 2474,0 +lang 2 +decl (Decl +n "wiz_write_ea" +t "std_logic" +o 87 +suid 39,0 +i "'0'" +) +declText (MLText +uid 2475,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,89000,-41500,89800" +st "SIGNAL wiz_write_ea : std_logic := '0' +" +) +) +*135 (Net +uid 2480,0 +lang 2 +decl (Decl +n "wiz_write_length" +t "std_logic_vector" +b "(16 downto 0)" +o 90 +suid 40,0 +i "(others => '0')" +) +declText (MLText +uid 2481,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,91400,-35500,92200" +st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0') +" +) +) +*136 (Net +uid 2486,0 +lang 2 +decl (Decl +n "wiz_ram_start_addr" +t "std_logic_vector" +b "(RAMADDRWIDTH64b+1 DOWNTO 0)" +preAdd 0 +o 86 +suid 41,0 +i "(others => '0')" +) +declText (MLText +uid 2487,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,88200,-35500,89000" +st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0') +" +) +) +*137 (Net +uid 2492,0 +lang 2 +decl (Decl +n "wiz_number_of_channels" +t "std_logic_vector" +b "(3 downto 0)" +o 85 +suid 42,0 +i "(others => '0')" +) +declText (MLText +uid 2493,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,87400,-35500,88200" +st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0') +" +) +) +*138 (Net +uid 2498,0 +lang 2 +decl (Decl +n "wiz_write_end" +t "std_logic" +o 88 +suid 43,0 +i "'0'" +) +declText (MLText +uid 2499,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,89800,-41500,90600" +st "SIGNAL wiz_write_end : std_logic := '0' +" +) +) +*139 (Net +uid 2504,0 +lang 2 +decl (Decl +n "wiz_write_header" +t "std_logic" +o 89 +suid 44,0 +i "'0'" +) +declText (MLText +uid 2505,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,90600,-41500,91400" +st "SIGNAL wiz_write_header : std_logic := '0' +" +) +) +*140 (Net +uid 2574,0 +decl (Decl +n "ram_write_ea" +t "std_logic" +o 72 +suid 48,0 +) +declText (MLText +uid 2575,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,77000,-62500,77800" +st "SIGNAL ram_write_ea : std_logic +" +) +) +*141 (Net +uid 2580,0 +decl (Decl +n "ram_write_ready" +t "std_logic" +o 73 +suid 49,0 +i "'0'" +) +declText (MLText +uid 2581,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,77800,-41500,78600" +st "SIGNAL ram_write_ready : std_logic := '0' +" +) +) +*142 (Net +uid 2586,0 +decl (Decl +n "config_start" +t "std_logic" +o 45 +suid 50,0 +i "'0'" +) +declText (MLText +uid 2587,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,56200,-41500,57000" +st "SIGNAL config_start : std_logic := '0' +" +) +) +*143 (Net +uid 2592,0 +decl (Decl +n "config_ready" +t "std_logic" +o 42 +suid 51,0 +) +declText (MLText +uid 2593,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,53800,-62500,54600" +st "SIGNAL config_ready : std_logic +" +) +) +*144 (Net +uid 2598,0 +decl (Decl +n "roi_max" +t "roi_max_type" +o 75 +suid 52,0 +) +declText (MLText +uid 2599,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,79400,-61000,80200" +st "SIGNAL roi_max : roi_max_type +" +) +) +*145 (Net +uid 2640,0 +decl (Decl +n "package_length" +t "std_logic_vector" +b "(15 downto 0)" +o 68 +suid 54,0 +) +declText (MLText +uid 2641,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,73800,-52500,74600" +st "SIGNAL package_length : std_logic_vector(15 downto 0) +" +) +) +*146 (Net +uid 2776,0 +decl (Decl +n "adc_oeb" +t "std_logic" +o 17 +suid 57,0 +i "'1'" +) +declText (MLText +uid 2777,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,31000,-45000,31800" +st "adc_oeb : std_logic := '1' +" +) +) +*147 (PortIoOut +uid 2798,0 +shape (CompositeShape +uid 2799,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2800,0 +sl 0 +ro 90 +xt "-28000,81625,-26500,82375" +) +(Line +uid 2801,0 +sl 0 +ro 90 +xt "-26500,82000,-26000,82000" +pts [ +"-26000,82000" +"-26500,82000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2802,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2803,0 +va (VaSet +) +xt "-32200,81500,-29000,82500" +st "adc_oeb" +ju 2 +blo "-29000,82300" +tm "WireNameMgr" +) +) +) +*148 (PortIoIn +uid 2804,0 +shape (CompositeShape +uid 2805,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2806,0 +sl 0 +ro 270 +xt "-28000,76625,-26500,77375" +) +(Line +uid 2807,0 +sl 0 +ro 270 +xt "-26500,77000,-26000,77000" +pts [ +"-26500,77000" +"-26000,77000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2808,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2809,0 +va (VaSet +) +xt "-34400,76500,-29000,77500" +st "adc_otr_array" +ju 2 +blo "-29000,77300" +tm "WireNameMgr" +) +) +) +*149 (Net +uid 2924,0 +decl (Decl +n "roi_array" +t "roi_array_type" +o 74 +suid 65,0 +) +declText (MLText +uid 2925,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,78600,-60000,79400" +st "SIGNAL roi_array : roi_array_type +" +) +) +*150 (PortIoIn +uid 2950,0 +shape (CompositeShape +uid 2951,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2952,0 +sl 0 +ro 270 +xt "-28000,85625,-26500,86375" +) +(Line +uid 2953,0 +sl 0 +ro 270 +xt "-26500,86000,-26000,86000" +pts [ +"-26500,86000" +"-26000,86000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2954,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2955,0 +va (VaSet +) +xt "-32300,85500,-29000,86500" +st "board_id" +ju 2 +blo "-29000,86300" +tm "WireNameMgr" +) +) +) +*151 (PortIoIn +uid 2956,0 +shape (CompositeShape +uid 2957,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2958,0 +sl 0 +ro 270 +xt "-28000,86625,-26500,87375" +) +(Line +uid 2959,0 +sl 0 +ro 270 +xt "-26500,87000,-26000,87000" +pts [ +"-26500,87000" +"-26000,87000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2960,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2961,0 +va (VaSet +) +xt "-32100,86500,-29000,87500" +st "crate_id" +ju 2 +blo "-29000,87300" +tm "WireNameMgr" +) +) +) +*152 (Grouping +uid 3137,0 +optionalChildren [ +*153 (CommentText +uid 3139,0 +shape (Rectangle +uid 3140,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "125000,175000,142000,176000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 3141,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "125200,175000,134500,176000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*154 (CommentText +uid 3142,0 +shape (Rectangle +uid 3143,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "142000,171000,146000,172000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 3144,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "142200,171000,145200,172000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*155 (CommentText +uid 3145,0 +shape (Rectangle +uid 3146,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "125000,173000,142000,174000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 3147,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "125200,173000,135200,174000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*156 (CommentText +uid 3148,0 +shape (Rectangle +uid 3149,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "121000,173000,125000,174000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 3150,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "121200,173000,123300,174000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*157 (CommentText +uid 3151,0 +shape (Rectangle +uid 3152,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "142000,172000,162000,176000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 3153,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "142200,172200,151400,173200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*158 (CommentText +uid 3154,0 +shape (Rectangle +uid 3155,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "146000,171000,162000,172000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 3156,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "146200,171000,150700,172000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*159 (CommentText +uid 3157,0 +shape (Rectangle +uid 3158,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "121000,171000,142000,173000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 3159,0 +va (VaSet +fg "32768,0,0" +) +xt "128700,171000,134300,173000" +st " +TU Dortmund +Physik / EE +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*160 (CommentText +uid 3160,0 +shape (Rectangle +uid 3161,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "121000,174000,125000,175000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 3162,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "121200,174000,123300,175000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*161 (CommentText +uid 3163,0 +shape (Rectangle +uid 3164,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "121000,175000,125000,176000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 3165,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "121200,175000,123900,176000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*162 (CommentText +uid 3166,0 +shape (Rectangle +uid 3167,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "125000,174000,142000,175000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 3168,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "125200,174000,137600,175000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape 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"-33200,50500,-29000,51500" +st "RSRLOAD" +ju 2 +blo "-29000,51300" +tm "WireNameMgr" +) +) +) +*213 (Net +uid 4960,0 +decl (Decl +n "SRCLK" +t "std_logic" +o 16 +suid 118,0 +i "'0'" +) +declText (MLText +uid 4961,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,30200,-45000,31000" +st "SRCLK : std_logic := '0' +" +) +) +*214 (PortIoOut +uid 4968,0 +shape (CompositeShape +uid 4969,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4970,0 +sl 0 +ro 90 +xt "-28000,51625,-26500,52375" +) +(Line +uid 4971,0 +sl 0 +ro 90 +xt "-26500,52000,-26000,52000" +pts [ +"-26000,52000" +"-26500,52000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 4972,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4973,0 +va (VaSet +) +xt "-32000,51500,-29000,52500" +st "SRCLK" +ju 2 +blo "-29000,52300" +tm "WireNameMgr" +) +) +) +*215 (SaComponent +uid 5072,0 +optionalChildren [ +*216 (CptPort +uid 5028,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5029,0 +ro 90 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"RightVerticalLayoutStrategy" +f (Text +uid 5047,0 +va (VaSet +) +xt "83300,100500,91000,101500" +st "config_data : (15:0)" +ju 2 +blo "91000,101300" +) +) +thePort (LogicalPort +m 2 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 14 +suid 5,0 +) +) +) +*221 (CptPort +uid 5048,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5049,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "73250,101625,74000,102375" +) +tg (CPTG +uid 5050,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5051,0 +va (VaSet +) +xt "75000,101500,78400,102500" +st "roi_array" +blo "75000,102300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "roi_array" +t "roi_array_type" +o 13 +suid 6,0 +) +) +) +*222 (CptPort +uid 5052,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5053,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92000,103625,92750,104375" +) +tg (CPTG +uid 5054,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5055,0 +va (VaSet +) +xt "85700,103500,91000,104500" +st "config_wr_en" +ju 2 +blo "91000,104300" +) +) +thePort (LogicalPort +decl (Decl +n "config_wr_en" +t "std_logic" +o 5 +suid 7,0 +) +) +) +*223 (CptPort +uid 5056,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5057,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "73250,108625,74000,109375" +) +tg (CPTG +uid 5058,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5059,0 +va (VaSet +) +xt "75000,108500,78700,109500" +st "dac_array" +blo "75000,109300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "dac_array" +t "dac_array_type" +o 10 +suid 8,0 +) +) +) +*224 (CptPort +uid 5060,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5061,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92000,104625,92750,105375" +) +tg (CPTG +uid 5062,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5063,0 +va (VaSet +) +xt "85800,104500,91000,105500" +st "config_rd_en" +ju 2 +blo "91000,105300" +) +) +thePort (LogicalPort +decl (Decl +n "config_rd_en" +t "std_logic" +o 3 +suid 9,0 +) +) +) +*225 (CptPort +uid 5064,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5065,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "73250,102625,74000,103375" +) +tg (CPTG +uid 5066,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5067,0 +va (VaSet +) +xt "75000,102500,79800,103500" +st "config_start" +blo "75000,103300" +) +) +thePort (LogicalPort +decl (Decl +n "config_start" +t "std_logic" +o 4 +suid 10,0 +) +) +) +*226 (CptPort +uid 5068,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5069,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "73250,104625,74000,105375" +) +tg (CPTG +uid 5070,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5071,0 +va (VaSet +) +xt "75000,104500,80100,105500" +st "config_ready" +blo "75000,105300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_ready" +t "std_logic" +o 8 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"74200,113800" +tm "CptNameMgr" +) +*232 (Text +uid 5077,0 +va (VaSet +font "Arial,8,1" +) +xt "74200,114000,82400,115000" +st "I_main_control_unit" +blo "74200,114800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 5078,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 5079,0 +text (MLText +uid 5080,0 +va (VaSet +font "Courier New,8,0" +) +xt "59000,98800,59000,98800" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 5081,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "74250,110250,75750,111750" +iconName "BlockDiagram.png" +iconMaskName "BlockDiagram.msk" +ftype 1 +) +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*233 (Net +uid 5088,0 +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 37 +suid 119,0 +) +declText (MLText +uid 5089,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,49800,-53000,50600" +st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0) +" +) +) +*234 (Net +uid 5096,0 +decl (Decl +n "config_data_valid" +t "std_logic" +o 40 +suid 120,0 +) +declText (MLText +uid 5097,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,52200,-62500,53000" +st "SIGNAL config_data_valid : std_logic +" +) +) +*235 (Net +uid 5104,0 +decl (Decl +n "config_busy" +t "std_logic" +o 38 +suid 121,0 +) +declText (MLText +uid 5105,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,50600,-62500,51400" +st "SIGNAL config_busy : std_logic +" +) +) +*236 (Net +uid 5112,0 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 39 +suid 122,0 +) +declText (MLText +uid 5113,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,51400,-52500,52200" +st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0) +" +) +) +*237 (Net +uid 5120,0 +decl (Decl +n "config_wr_en" +t "std_logic" +o 54 +suid 123,0 +) +declText (MLText +uid 5121,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,62600,-62500,63400" +st "SIGNAL config_wr_en : std_logic +" +) +) +*238 (Net +uid 5128,0 +decl (Decl +n "config_rd_en" +t "std_logic" +o 41 +suid 124,0 +) +declText (MLText +uid 5129,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,53000,-62500,53800" +st "SIGNAL config_rd_en : std_logic +" +) +) +*239 (Net +uid 5144,0 +decl (Decl +n "dac_array" +t "dac_array_type" +o 55 +suid 126,0 +) +declText (MLText +uid 5145,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,63400,-60000,64200" +st "SIGNAL dac_array : dac_array_type +" +) +) +*240 (Net +uid 5194,0 +decl (Decl +n "config_start_cm" +t "std_logic" +o 47 +suid 131,0 +) +declText (MLText +uid 5195,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,57800,-62500,58600" +st "SIGNAL config_start_cm : std_logic +" +) +) +*241 (Net +uid 5196,0 +decl (Decl +n "config_ready_cm" +t "std_logic" +o 43 +suid 132,0 +) +declText (MLText +uid 5197,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,54600,-62500,55400" +st "SIGNAL config_ready_cm : std_logic +" +) +) +*242 (Net +uid 5220,0 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 DOWNTO 0)" +posAdd 0 +o 22 +suid 133,0 +i "(OTHERS => '0')" +) +declText (MLText +uid 5221,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,35800,-39000,36600" +st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') +" +) +) +*243 (Net +uid 5279,0 +decl (Decl +n "s_trigger" +t "std_logic" +o 76 +suid 134,0 +i "'0'" +) +declText (MLText +uid 5280,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,80200,-41500,81000" +st "SIGNAL s_trigger : std_logic := '0' +" +) +) +*244 (Net +uid 5472,0 +decl (Decl +n "sensor_ready" +t "std_logic" +o 80 +suid 140,0 +) +declText (MLText +uid 5473,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,83400,-62500,84200" +st "SIGNAL sensor_ready : std_logic +" +) +) +*245 (Net +uid 5478,0 +decl (Decl +n "sensor_array" +t "sensor_array_type" +o 79 +suid 141,0 +) +declText (MLText +uid 5479,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,82600,-58500,83400" +st "SIGNAL sensor_array : sensor_array_type +" +) +) +*246 (Net +uid 5588,0 +decl (Decl +n "config_ready_spi" +t "std_logic" +o 44 +suid 144,0 +) +declText (MLText +uid 5589,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,55400,-62500,56200" +st "SIGNAL config_ready_spi : std_logic +" +) +) +*247 (Net +uid 5632,0 +lang 10 +decl (Decl +n "adc_otr" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 35 +suid 146,0 +) +declText (MLText +uid 5633,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,48200,-53000,49000" +st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0) +" +) +) +*248 (Net +uid 5640,0 +decl (Decl +n "adc_data_array_int" +t "adc_data_array_type" +o 34 +suid 147,0 +) +declText (MLText +uid 5641,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,47400,-57500,48200" +st "SIGNAL adc_data_array_int : adc_data_array_type +" +) +) +*249 (SaComponent +uid 5678,0 +optionalChildren [ +*250 (CptPort +uid 5658,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5659,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-18750,75625,-18000,76375" +) +tg (CPTG +uid 5660,0 +ps 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1 +fg "0,65535,0" +) +xt "20250,107625,21000,108375" +) +tg (CPTG +uid 6319,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6320,0 +va (VaSet +) +xt "22000,107500,24000,108500" +st "miso" +blo "22000,108300" +) +) +thePort (LogicalPort +m 2 +decl (Decl +n "miso" +t "std_logic" +preAdd 0 +posAdd 0 +o 12 +suid 20,0 +) +) +) +] +shape (Rectangle +uid 5794,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "21000,100000,37000,112000" +) +oxt "15000,12000,30000,26000" +ttg (MlTextGroup +uid 5795,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*272 (Text +uid 5796,0 +va (VaSet +font "Arial,8,1" +) +xt "21200,112000,27400,113000" +st "FACT_FAD_lib" +blo "21200,112800" +tm "BdLibraryNameMgr" +) +*273 (Text +uid 5797,0 +va (VaSet +font "Arial,8,1" +) +xt "21200,113000,26700,114000" +st "spi_interface" +blo "21200,113800" +tm "CptNameMgr" +) +*274 (Text +uid 5798,0 +va (VaSet +font "Arial,8,1" +) +xt "21200,114000,30000,115000" +st "I_main_SPI_interface" +blo "21200,114800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 5799,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 5800,0 +text (MLText +uid 5801,0 +va (VaSet +font "Courier New,8,0" +) +xt "6000,100000,6000,100000" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 5802,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "21250,110250,22750,111750" +iconName "BlockDiagram.png" +iconMaskName "BlockDiagram.msk" +ftype 1 +) +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*275 (Net +uid 5811,0 +decl (Decl +n "sclk" +t "std_logic" +o 24 +suid 151,0 +) +declText (MLText +uid 5812,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,37400,-66500,38200" +st "sclk : std_logic +" +) +) +*276 (Net +uid 5819,0 +decl (Decl +n "sio" +t "std_logic" +preAdd 0 +posAdd 0 +o 31 +suid 152,0 +) +declText (MLText +uid 5820,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,43000,-66500,43800" +st "sio : std_logic +" +) +) +*277 (Net +uid 5827,0 +decl (Decl +n "dac_cs" +t "std_logic" +o 18 +suid 153,0 +) +declText (MLText +uid 5828,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,32600,-66500,33400" +st "dac_cs : std_logic +" +) +) +*278 (Net +uid 5835,0 +decl (Decl +n "sensor_cs" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 25 +suid 154,0 +) +declText (MLText +uid 5836,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,38200,-56500,39000" +st "sensor_cs : std_logic_vector(3 DOWNTO 0) +" +) +) +*279 (PortIoOut +uid 5843,0 +shape (CompositeShape +uid 5844,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5845,0 +sl 0 +ro 90 +xt "-20000,111625,-18500,112375" +) +(Line +uid 5846,0 +sl 0 +ro 90 +xt "-18500,112000,-18000,112000" +pts [ +"-18000,112000" +"-18500,112000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 5847,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5848,0 +va (VaSet +) +xt "-22700,111500,-21000,112500" +st "sclk" +ju 2 +blo "-21000,112300" +tm "WireNameMgr" +) +) +) +*280 (PortIoInOut +uid 5849,0 +shape (CompositeShape +uid 5850,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Hexagon +uid 5851,0 +sl 0 +ro 180 +xt "10000,107625,11500,108375" +) +(Line +uid 5852,0 +sl 0 +ro 180 +xt "11500,108000,12000,108000" +pts [ +"12000,108000" +"11500,108000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 5853,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5854,0 +va (VaSet +) +xt "7600,107500,9000,108500" +st "sio" +ju 2 +blo "9000,108300" +tm "WireNameMgr" +) +) +) +*281 (PortIoOut +uid 5855,0 +shape (CompositeShape +uid 5856,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5857,0 +sl 0 +ro 90 +xt "10000,104625,11500,105375" +) +(Line +uid 5858,0 +sl 0 +ro 90 +xt "11500,105000,12000,105000" +pts [ +"12000,105000" +"11500,105000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 5859,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5860,0 +va (VaSet +) +xt "6200,104500,9000,105500" +st "dac_cs" +ju 2 +blo "9000,105300" +tm "WireNameMgr" +) +) +) +*282 (PortIoOut +uid 5861,0 +shape (CompositeShape +uid 5862,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5863,0 +sl 0 +ro 90 +xt "10000,103625,11500,104375" +) +(Line +uid 5864,0 +sl 0 +ro 90 +xt "11500,104000,12000,104000" +pts [ +"12000,104000" +"11500,104000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 5865,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5866,0 +va (VaSet +) +xt "5100,103500,9000,104500" +st "sensor_cs" +ju 2 +blo "9000,104300" +tm "WireNameMgr" +) +) +) +*283 (Net +uid 5948,0 +decl (Decl +n "new_config" +t "std_logic" +o 67 +suid 155,0 +i "'0'" +) +declText (MLText +uid 5949,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,73000,-41500,73800" +st "SIGNAL new_config : std_logic := '0' +" +) +) +*284 (Net +uid 5960,0 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6158,0 +decl (Decl +n "mosi" +t "std_logic" +o 23 +suid 162,0 +i "'0'" +) +declText (MLText +uid 6159,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,36600,-45000,37400" +st "mosi : std_logic := '0' +" +) +) +*289 (PortIoOut +uid 6166,0 +shape (CompositeShape +uid 6167,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 6168,0 +sl 0 +ro 90 +xt "10000,108625,11500,109375" +) +(Line +uid 6169,0 +sl 0 +ro 90 +xt "11500,109000,12000,109000" +pts [ +"12000,109000" +"11500,109000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 6170,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6171,0 +va (VaSet +) +xt "7000,108500,9000,109500" +st "mosi" +ju 2 +blo "9000,109300" +tm "WireNameMgr" +) +) +) +*290 (Net +uid 6360,0 +decl (Decl +n "denable" +t "std_logic" +eolc "-- default domino wave off" +posAdd 0 +o 19 +suid 166,0 +i "'0'" +) +declText (MLText +uid 6361,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,33400,-31500,34200" +st "denable : std_logic := '0' -- default domino wave off +" +) +) +*291 (PortIoOut +uid 6368,0 +shape (CompositeShape +uid 6369,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 6370,0 +sl 0 +ro 270 +xt "153500,74625,155000,75375" +) +(Line +uid 6371,0 +sl 0 +ro 270 +xt "153000,75000,153500,75000" +pts [ +"153000,75000" +"153500,75000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 6372,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6373,0 +va (VaSet +) +xt "156000,74500,159000,75500" +st "denable" +blo "156000,75300" +tm "WireNameMgr" +) +) +) +*292 (Net +uid 6450,0 +decl (Decl +n "dwrite_enable" +t "std_logic" +o 66 +suid 167,0 +i "'1'" +) +declText (MLText +uid 6451,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,72200,-41500,73000" +st "SIGNAL dwrite_enable : std_logic := '1' +" +) +) +*293 (MWC +uid 6529,0 +optionalChildren [ +*294 (CptPort +uid 6501,0 +optionalChildren [ +*295 (Line +uid 6505,0 +layer 5 +sl 0 +va (VaSet +vasetType 3 +) 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+"120000,83000" +"120000,105000" +"92750,105000" +] +) +start &93 +end &224 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5134,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5135,0 +va (VaSet +) +xt "121000,82000,126200,83000" +st "config_rd_en" +blo "121000,82800" +tm "WireNameMgr" +) +) +on &238 +) +*491 (Wire +uid 5138,0 +optionalChildren [ +*492 (BdJunction +uid 5400,0 +ps "OnConnectorStrategy" +shape (Circle +uid 5401,0 +va (VaSet +vasetType 1 +) +xt "57600,84600,58400,85400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 5139,0 +va (VaSet +vasetType 3 +) +xt "40750,80000,73250,102000" +pts [ +"73250,102000" +"58000,102000" +"58000,80000" +"40750,80000" +] +) +start &221 +end &35 +ss 0 +es 0 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5142,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5143,0 +va (VaSet +) +xt "42000,79000,45400,80000" +st "roi_array" +blo "42000,79800" +tm "WireNameMgr" +) +) +on &149 +) +*493 (Wire +uid 5146,0 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+"52000,81000" +"40750,81000" +] +) +start &376 +end &47 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5186,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5187,0 +va (VaSet +) +xt "46000,114000,52200,115000" +st "config_start_cm" +blo "46000,114800" +tm "WireNameMgr" +) +) +on &240 +) +*496 (Wire +uid 5190,0 +shape (OrthoPolyLine +uid 5191,0 +va (VaSet +vasetType 3 +) +xt "40750,83000,73250,105000" +pts [ +"73250,105000" +"55000,105000" +"55000,83000" +"40750,83000" +] +) +start &226 +end &46 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5192,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5193,0 +va (VaSet +) +xt "66000,104000,72500,105000" +st "config_ready_cm" +blo "66000,104800" +tm "WireNameMgr" +) +) +on &241 +) +*497 (Wire +uid 5222,0 +shape (OrthoPolyLine +uid 5223,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "148750,71000,153000,71000" +pts [ +"148750,71000" +"153000,71000" +] +) +start &85 +end &19 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5224,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5225,0 +va (VaSet +isHidden 1 +) +xt "150750,70000,152150,71000" +st "led" +blo "150750,70800" +tm "WireNameMgr" +) +) +on &242 +) +*498 (Wire +uid 5281,0 +shape (OrthoPolyLine +uid 5282,0 +va (VaSet +vasetType 3 +) +xt "40750,53000,126250,59000" +pts [ +"126250,59000" +"73000,59000" +"73000,53000" +"40750,53000" +] +) +start &86 +end &48 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5283,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5284,0 +va (VaSet +) +xt "121250,58000,124850,59000" +st "s_trigger" +blo "121250,58800" +tm "WireNameMgr" +) +) +on &243 +) +*499 (Wire +uid 5404,0 +shape (OrthoPolyLine +uid 5405,0 +va (VaSet +vasetType 3 +) +xt "37750,85000,48000,107000" +pts [ +"37750,107000" +"48000,107000" +"48000,85000" +"40750,85000" +] +) +start &262 +end &50 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5406,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5407,0 +va (VaSet +) +xt "39000,106000,45500,107000" +st "config_ready_spi" +blo "39000,106800" +tm "WireNameMgr" +) +) +on &246 +) +*500 (Wire +uid 5474,0 +shape (OrthoPolyLine +uid 5475,0 +va (VaSet +vasetType 3 +) +xt "37750,90000,44000,101000" +pts [ +"37750,101000" +"44000,101000" +"44000,90000" +"40750,90000" +] +) +start &265 +end &52 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5476,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5477,0 +va (VaSet +) +xt "39750,100000,45050,101000" +st "sensor_ready" +blo "39750,100800" +tm "WireNameMgr" +) +) +on &244 +) +*501 (Wire +uid 5480,0 +shape (OrthoPolyLine +uid 5481,0 +va (VaSet +vasetType 3 +) +xt "37750,89000,45000,102000" +pts [ +"37750,102000" +"45000,102000" +"45000,89000" +"40750,89000" +] +) +start &264 +end &51 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5482,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5483,0 +va (VaSet +) +xt "39750,101000,44950,102000" +st "sensor_array" +blo "39750,101800" +tm "WireNameMgr" +) +) +on &245 +) +*502 (Wire +uid 5582,0 +shape (OrthoPolyLine +uid 5583,0 +va (VaSet +vasetType 3 +lineColor "0,0,65535" +) +xt "69000,100000,73250,100000" +pts [ +"69000,100000" +"73250,100000" +] +) +end &216 +sat 16 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5586,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5587,0 +va (VaSet +) +xt "70000,99000,73100,100000" +st "CLK_50" +blo "70000,99800" +tm "WireNameMgr" +) +) +on &165 +) +*503 (Wire +uid 5602,0 +optionalChildren [ +&482 +*504 (BdJunction +uid 6086,0 +ps "OnConnectorStrategy" +shape (Circle +uid 6087,0 +va (VaSet +vasetType 1 +) +xt "67600,43600,68400,44400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 5603,0 +va (VaSet +vasetType 3 +lineColor "0,32896,0" +) +xt "15000,38000,76250,48000" +pts [ +"18250,48000" +"15000,48000" +"15000,38000" +"68000,38000" +"68000,44000" +"76250,44000" +] +) +start &23 +end &313 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5604,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5605,0 +va (VaSet +) +xt "15000,47000,18100,48000" +st "CLK_25" +blo "15000,47800" +tm "WireNameMgr" +) +) +on &174 +) +*505 (Wire +uid 5626,0 +shape (OrthoPolyLine +uid 5627,0 +va (VaSet +vasetType 3 +) +xt "750,76000,18250,76000" +pts [ +"18250,76000" +"750,76000" +] +) +start &45 +end &251 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5630,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5631,0 +va (VaSet +) +xt "11250,75000,18350,76000" +st "adc_data_array_int" +blo "11250,75800" +tm "WireNameMgr" +) +) +on &248 +) +*506 (Wire +uid 5634,0 +shape (OrthoPolyLine +uid 5635,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "750,77000,18250,77000" +pts [ +"18250,77000" +"750,77000" +] +) +start &38 +end &252 +sat 32 +eat 32 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 5638,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5639,0 +va (VaSet +) +xt "11250,76000,16750,77000" +st "adc_otr : (3:0)" +blo "11250,76800" +tm "WireNameMgr" +) +) +on &247 +) +*507 (Wire +uid 5646,0 +shape (OrthoPolyLine +uid 5647,0 +va (VaSet +vasetType 3 +lineColor "49152,0,0" +) +xt "-26000,74000,-18750,74000" +pts [ +"-26000,74000" +"-18750,74000" +] +) +end &254 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5652,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5653,0 +va (VaSet +) +xt "-25000,73000,-20500,74000" +st "CLK_25_PS" +blo "-25000,73800" +tm "WireNameMgr" +) +) +on &163 +) +*508 (Wire +uid 5745,0 +shape (OrthoPolyLine +uid 5746,0 +va (VaSet +vasetType 3 +) +xt "37750,87000,46000,105000" +pts [ +"40750,87000" +"46000,87000" +"46000,105000" +"37750,105000" +] +) +start &54 +end &263 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5749,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5750,0 +va (VaSet +) +xt "39000,104000,45200,105000" +st "config_start_spi" +blo "39000,104800" +tm "WireNameMgr" +) +) +on &258 +) +*509 (Wire +uid 5805,0 +shape (OrthoPolyLine +uid 5806,0 +va (VaSet +vasetType 3 +) +xt "16000,101000,20250,101000" +pts [ +"16000,101000" +"20250,101000" +] +) +end &268 +sat 16 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5809,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5810,0 +va (VaSet +) +xt "17000,100000,20100,101000" +st "CLK_50" +blo "17000,100800" +tm "WireNameMgr" +) +) +on &165 +) +*510 (Wire +uid 5813,0 +shape (OrthoPolyLine +uid 5814,0 +va (VaSet +vasetType 3 +) +xt "-18000,112000,-13000,112000" +pts [ +"-13000,112000" +"-18000,112000" +] +) +start &349 +end &279 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5817,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5818,0 +va (VaSet +isHidden 1 +) +xt "-17000,111000,-15300,112000" +st "sclk" +blo "-17000,111800" +tm "WireNameMgr" +) +) +on &275 +) +*511 (Wire +uid 5821,0 +shape (OrthoPolyLine +uid 5822,0 +va (VaSet +vasetType 3 +) +xt "12000,108000,20250,108000" +pts [ +"20250,108000" +"12000,108000" +] +) +start &271 +end &280 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5825,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5826,0 +va (VaSet +isHidden 1 +) +xt "13000,107000,14400,108000" +st "sio" +blo "13000,107800" +tm "WireNameMgr" +) +) +on &276 +) +*512 (Wire +uid 5829,0 +shape (OrthoPolyLine +uid 5830,0 +va (VaSet +vasetType 3 +) +xt "12000,105000,20250,105000" +pts [ +"20250,105000" +"12000,105000" +] +) +start &266 +end &281 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5833,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5834,0 +va (VaSet +isHidden 1 +) +xt "13000,104000,15800,105000" +st "dac_cs" +blo "13000,104800" +tm "WireNameMgr" +) +) +on &277 +) +*513 (Wire +uid 5837,0 +shape (OrthoPolyLine +uid 5838,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "12000,104000,20250,104000" +pts [ +"20250,104000" +"12000,104000" +] +) +start &267 +end &282 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5841,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5842,0 +va (VaSet +isHidden 1 +) +xt "13000,103000,16900,104000" +st "sensor_cs" +blo "13000,103800" +tm "WireNameMgr" +) +) +on &278 +) +*514 (Wire +uid 5950,0 +shape (OrthoPolyLine +uid 5951,0 +va (VaSet +vasetType 3 +) +xt "40750,54000,126250,60000" +pts [ +"126250,60000" +"72000,60000" +"72000,54000" +"40750,54000" +] +) +start &92 +end &56 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5952,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5953,0 +va (VaSet +) +xt "120250,59000,124850,60000" +st "new_config" +blo "120250,59800" +tm "WireNameMgr" +) +) +on &283 +) +*515 (Wire +uid 5962,0 +shape (OrthoPolyLine +uid 5963,0 +va (VaSet +vasetType 3 +) +xt "40750,55000,126250,61000" +pts [ +"126250,61000" +"71000,61000" +"71000,55000" +"40750,55000" +] +) +start &90 +end &55 +sat 32 +eat 32 +st 0 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(Text +uid 8757,0 +va (VaSet +) +xt "150000,76000,154700,77000" +st "sclk_enable" +blo "150000,76800" +tm "WireNameMgr" +) +) +on &367 +) +*538 (Wire +uid 8825,0 +shape (OrthoPolyLine +uid 8826,0 +va (VaSet +vasetType 3 +) +xt "21000,124000,27000,124000" +pts [ +"21000,124000" +"27000,124000" +] +) +start &368 +end &395 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 8829,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8830,0 +va (VaSet +isHidden 1 +) +xt "23000,123000,26600,124000" +st "TEST_IN" +blo "23000,123800" +tm "WireNameMgr" +) +) +on &369 +) +*539 (Wire +uid 8880,0 +optionalChildren [ +*540 (BdJunction +uid 9126,0 +ps "OnConnectorStrategy" +shape (Circle +uid 9127,0 +va (VaSet +vasetType 1 +) +xt "61600,115600,62400,116400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 8881,0 +va (VaSet +vasetType 3 +) +xt "59000,103000,73250,116000" +pts [ +"73250,103000" +"62000,103000" +"62000,116000" +"59000,116000" +] +) +start &225 +end &373 +sat 32 +eat 32 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"STSignalDisplayStrategy" +f (Text +uid 8944,0 +va (VaSet +) +xt "46750,117000,51350,118000" +st "trigger_out" +blo "46750,117800" +tm "WireNameMgr" +) +) +on &412 +) +*543 (Wire +uid 8947,0 +shape (OrthoPolyLine +uid 8948,0 +va (VaSet +vasetType 3 +) +xt "34000,123000,38250,123000" +pts [ +"34000,123000" +"38250,123000" +] +) +end &405 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 8951,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8952,0 +va (VaSet +) +xt "35000,122000,38100,123000" +st "CLK_50" +blo "35000,122800" +tm "WireNameMgr" +) +) +on &165 +) +*544 (Wire +uid 9083,0 +shape (OrthoPolyLine +uid 9084,0 +va (VaSet +vasetType 3 +) +xt "72000,121000,82000,121000" +pts [ +"72000,121000" +"82000,121000" +] +) +start &418 +end &413 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 9087,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 9088,0 +va (VaSet +isHidden 1 +) +xt "74000,120000,80200,121000" +st "config_start_out" +blo "74000,120800" +tm "WireNameMgr" +) +) +on &414 +) +*545 (Wire +uid 9122,0 +shape (OrthoPolyLine +uid 9123,0 +va (VaSet +vasetType 3 +) +xt "62000,116000,69000,121000" +pts [ +"62000,116000" +"62000,121000" +"69000,121000" +] +) +start &540 +end &416 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 9124,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 9125,0 +va (VaSet +) +xt "63000,120000,68200,121000" +st "config_start1" +blo "63000,120800" +tm "WireNameMgr" +) +) +on &393 +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *546 (PackageList +uid 41,0 +stg "VerticalLayoutStrategy" +textVec [ +*547 (Text +uid 42,0 +va (VaSet +font "arial,8,1" +) +xt "-87000,1000,-81600,2000" +st "Package List" +blo "-87000,1800" +) +*548 (MLText +uid 43,0 +va (VaSet +) +xt "-87000,2000,-72600,14000" +st "library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use ieee.STD_LOGIC_UNSIGNED.all; + +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + +library UNISIM; +use UNISIM.VComponents.all; +USE IEEE.NUMERIC_STD.all; +USE IEEE.std_logic_signed.all;" +tm "PackageList" +) +] +) +compDirBlock (MlTextGroup +uid 44,0 +stg "VerticalLayoutStrategy" +textVec [ +*549 (Text +uid 45,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "20000,0,28100,1000" +st "Compiler Directives" +blo "20000,800" +) +*550 (Text +uid 46,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "20000,1000,29600,2000" +st "Pre-module directives:" +blo "20000,1800" +) +*551 (MLText +uid 47,0 +va (VaSet +isHidden 1 +) +xt "20000,2000,27500,4000" +st "`resetall +`timescale 1ns/10ps" +tm "BdCompilerDirectivesTextMgr" +) +*552 (Text +uid 48,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "20000,4000,30100,5000" +st "Post-module directives:" +blo "20000,4800" +) +*553 (MLText +uid 49,0 +va (VaSet +isHidden 1 +) +xt "20000,0,20000,0" +tm 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+duName "clock_generator" +elements [ +] +mwi 0 +uid 4194,0 +) +(Instance +name "I_main_drs_pulser" +duLibraryName "FACT_FAD_LIB" +duName "drs_pulser" +elements [ +] +mwi 0 +uid 4903,0 +) +(Instance +name "I_main_control_unit" +duLibraryName "FACT_FAD_lib" +duName "control_unit" +elements [ +] +mwi 0 +uid 5072,0 +) +(Instance +name "I_main_adc_buffer" +duLibraryName "FACT_FAD_lib" +duName "adc_buffer" +elements [ +] +mwi 0 +uid 5678,0 +) +(Instance +name "I_main_SPI_interface" +duLibraryName "FACT_FAD_lib" +duName "spi_interface" +elements [ +] +mwi 0 +uid 5793,0 +) +(Instance +name "I5" +duLibraryName "moduleware" +duName "and" +elements [ +] +mwi 1 +uid 6529,0 +) +(Instance +name "U_4" +duLibraryName "FACT_FAD_lib" +duName "dataRAM_64b_16b_width14_5" +elements [ +] +mwi 0 +uid 8277,0 +) +(Instance +name "U_0" +duLibraryName "moduleware" +duName "mux" +elements [ +] +mwi 1 +uid 8562,0 +) +(Instance +name "U_1" +duLibraryName "moduleware" +duName "and" +elements [ +] +mwi 1 +uid 8721,0 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"148000,54625,148750,55375" +) +tg (CPTG +uid 1572,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1573,0 +va (VaSet +) +xt "145900,54500,147000,55500" +st "rd" +ju 2 +blo "147000,55300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "rd" +t "std_logic" +preAdd 0 +posAdd 0 +o 8 +suid 8,0 +i "'1'" +) +) +) +*75 (CptPort +uid 1574,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1575,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,55625,148750,56375" +) +tg (CPTG +uid 1576,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1577,0 +va (VaSet +) +xt "145800,55500,147000,56500" +st "int" +ju 2 +blo "147000,56300" +) +) +thePort (LogicalPort +decl (Decl +n "int" +t "std_logic" +preAdd 0 +posAdd 0 +o 9 +suid 9,0 +) +) +) +*76 (CptPort +uid 1578,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1579,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,69625,127000,70375" +) +tg (CPTG +uid 1580,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1581,0 +va (VaSet +) +xt "128000,69500,135900,70500" +st "write_length : (16:0)" +blo "128000,70300" +) +) +thePort (LogicalPort +decl (Decl +n "write_length" +t "std_logic_vector" +b "(16 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 10 +suid 10,0 +) +) +) +*77 (CptPort +uid 1582,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1583,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,70625,127000,71375" +) +tg (CPTG +uid 1584,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1585,0 +va (VaSet +) +xt "128000,70500,144300,71500" +st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)" +blo "128000,71300" +) +) +thePort (LogicalPort +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 11 +suid 11,0 +) +) +) +*78 (CptPort +uid 1586,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1587,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,54625,127000,55375" +) +tg (CPTG +uid 1588,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1589,0 +va (VaSet +) +xt "128000,54500,134500,55500" +st "ram_data : (15:0)" +blo "128000,55300" +) +) +thePort (LogicalPort +decl (Decl +n "ram_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 12 +suid 12,0 +) +) +) +*79 (CptPort +uid 1590,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1591,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,53625,127000,54375" +) +tg (CPTG +uid 1592,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1593,0 +va (VaSet +) +xt "128000,53500,142400,54500" +st "ram_addr : (RAM_ADDR_WIDTH-1:0)" +blo "128000,54300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "ram_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 13 +suid 13,0 +) +) +) +*80 (CptPort +uid 1594,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1595,0 +ro 90 +va (VaSet +vasetType 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"VerticalLayoutStrategy" +f (Text +uid 2229,0 +va (VaSet +) +xt "128000,73500,134800,74500" +st "write_header_flag" +blo "128000,74300" +) +) +thePort (LogicalPort +decl (Decl +n "write_header_flag" +t "std_logic" +o 17 +suid 19,0 +) +) +) +*85 (CptPort +uid 5216,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5217,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,70625,148750,71375" +) +tg (CPTG +uid 5218,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5219,0 +va (VaSet +) +xt "143000,70500,147000,71500" +st "led : (7:0)" +ju 2 +blo "147000,71300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 DOWNTO 0)" +posAdd 0 +o 7 +suid 22,0 +i "(OTHERS => '0')" +) +) +) +*86 (CptPort +uid 5275,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5276,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,58625,127000,59375" +) +tg (CPTG +uid 5277,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5278,0 +va (VaSet +) +xt "128000,58500,131600,59500" +st "s_trigger" +blo "128000,59300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "s_trigger" +t "std_logic" +o 20 +suid 23,0 +i "'0'" +) +) +) +*87 (CptPort +uid 5924,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5925,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,78625,127000,79375" +) +tg (CPTG +uid 5926,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5927,0 +va (VaSet +) +xt "128000,78500,135000,79500" +st "config_addr : (7:0)" +blo "128000,79300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(7 downto 0)" +o 23 +suid 24,0 +) +) +) +*88 (CptPort +uid 5928,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5929,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,83625,127000,84375" +) +tg (CPTG +uid 5930,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5931,0 +va (VaSet +) +xt "128000,83500,132800,84500" +st "config_busy" +blo "128000,84300" +) +) +thePort (LogicalPort +decl (Decl +n "config_busy" +t "std_logic" +o 27 +suid 25,0 +) +) +) +*89 (CptPort +uid 5932,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 6051,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,79625,127000,80375" +) +tg (CPTG +uid 5934,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5935,0 +va (VaSet +) +xt "128000,79500,135700,80500" +st "config_data : (15:0)" +blo "128000,80300" +) +) +thePort (LogicalPort +m 2 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 downto 0)" +o 24 +suid 26,0 +i "(others => 'Z')" +) +) +) +*90 (CptPort +uid 5936,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5937,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,60625,127000,61375" +) +tg (CPTG +uid 5938,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5939,0 +va (VaSet +) +xt "128000,60500,133600,61500" +st "config_started" +blo "128000,61300" +) +) +thePort (LogicalPort +decl (Decl +n "config_started" +t "std_logic" +o 22 +suid 27,0 +) +) +) +*91 (CptPort +uid 5940,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5941,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,81625,127000,82375" +) +tg (CPTG +uid 5942,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5943,0 +va (VaSet +) +xt "128000,81500,133300,82500" +st "config_wr_en" +blo "128000,82300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_wr_en" +t "std_logic" +o 25 +suid 28,0 +i "'0'" +) +) +) +*92 (CptPort +uid 5944,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5945,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,59625,127000,60375" +) +tg (CPTG +uid 5946,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5947,0 +va (VaSet +) +xt "128000,59500,132600,60500" +st "new_config" +blo "128000,60300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "new_config" +t "std_logic" +o 21 +suid 29,0 +i "'0'" +) +) +) +*93 (CptPort +uid 5970,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5971,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,82625,127000,83375" +) +tg (CPTG +uid 5972,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5973,0 +va (VaSet +) +xt "128000,82500,133200,83500" +st "config_rd_en" +blo "128000,83300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_rd_en" +t "std_logic" +o 26 +suid 30,0 +i "'0'" +) +) +) +*94 (CptPort +uid 6356,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6357,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,74625,148750,75375" +) +tg (CPTG +uid 6358,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6359,0 +va (VaSet +) +xt "144000,74500,147000,75500" +st "denable" +ju 2 +blo "147000,75300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "denable" +t "std_logic" +eolc "-- default domino wave off" +posAdd 0 +o 28 +suid 31,0 +i "'0'" +) +) +) +*95 (CptPort +uid 6446,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6447,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,75625,148750,76375" +) +tg (CPTG +uid 6448,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6449,0 +va (VaSet +) +xt "141600,75500,147000,76500" +st "dwrite_enable" +ju 2 +blo "147000,76300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "dwrite_enable" +t "std_logic" +eolc "-- default DWRITE low." +preAdd 0 +posAdd 0 +o 29 +suid 32,0 +i "'0'" +) +) +) +*96 (CptPort +uid 8406,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8407,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "126250,74625,127000,75375" +) +tg (CPTG +uid 8408,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8409,0 +va (VaSet +) +xt "128000,74500,133600,75500" +st "data_valid_ack" +blo "128000,75300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "data_valid_ack" +t "std_logic" +o 15 +suid 34,0 +i "'0'" +) +) +) +*97 (CptPort +uid 8748,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8749,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148000,76625,148750,77375" +) +tg (CPTG +uid 8750,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8751,0 +va (VaSet +) +xt "142300,76500,147000,77500" +st "sclk_enable" +ju 2 +blo "147000,77300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sclk_enable" +t "std_logic" +eolc "-- default DWRITE HIGH." +posAdd 0 +o 30 +suid 35,0 +i "'1'" +) +) +) +] +shape (Rectangle +uid 1607,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "127000,51000,148000,87000" +) +oxt "43000,2000,56000,22000" +ttg (MlTextGroup +uid 1608,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*98 (Text +uid 1609,0 +va (VaSet +font "Arial,8,1" +) +xt "126700,87000,132900,88000" +st "FACT_FAD_lib" +blo "126700,87800" +tm "BdLibraryNameMgr" +) +*99 (Text +uid 1610,0 +va (VaSet +font "Arial,8,1" +) +xt "126700,88000,132400,89000" +st "w5300_modul" +blo "126700,88800" +tm "CptNameMgr" +) +*100 (Text +uid 1611,0 +va (VaSet +font "Arial,8,1" +) +xt "126700,89000,133400,90000" +st "I_main_ethernet" +blo "126700,89800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1612,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1613,0 +text (MLText +uid 1614,0 +va (VaSet +font "Courier New,8,0" +) +xt "127000,50200,154500,51000" +st "RAM_ADDR_WIDTH = RAMADDRWIDTH64b+2 ( integer ) " +) +header "" +) +elements [ +(GiElement +name "RAM_ADDR_WIDTH" +type "integer" +value "RAMADDRWIDTH64b+2" +) +] +) +viewicon (ZoomableIcon +uid 1615,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "127250,85250,128750,86750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*101 (Net +uid 1680,0 +decl (Decl +n "crate_id" +t "std_logic_vector" +b "(1 downto 0)" +o 10 +suid 30,0 +) +declText (MLText +uid 1681,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,25400,-56500,26200" +st "crate_id : std_logic_vector(1 downto 0)" +) +) +*102 (SaComponent +uid 1768,0 +optionalChildren [ +*103 (CptPort +uid 1760,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1761,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-7000,63625,-6250,64375" +) +tg (CPTG +uid 1762,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1763,0 +va (VaSet +) +xt "-14800,63500,-8000,64500" +st "trigger_id : (47:0)" +ju 2 +blo "-8000,64300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "trigger_id" +t "std_logic_vector" +b "(47 downto 0)" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*104 (CptPort +uid 1764,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1765,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-18750,63625,-18000,64375" +) +tg (CPTG +uid 1766,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1767,0 +va (VaSet +) +xt "-17000,63500,-14200,64500" +st "trigger" +blo "-17000,64300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "trigger" +t "std_logic" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +) +) +) +*105 (CptPort +uid 6207,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6208,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-18750,62625,-18000,63375" +) +tg (CPTG +uid 6209,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6210,0 +va (VaSet +) +xt "-17000,62500,-15700,63500" +st "clk" +blo "-17000,63300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "clk" +t "std_logic" +o 3 +suid 3,0 +) +) +) +] +shape (Rectangle +uid 1769,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "-18000,62000,-7000,67000" +) +oxt "32000,2000,43000,12000" +ttg (MlTextGroup +uid 1770,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*106 (Text +uid 1771,0 +va (VaSet +font "Arial,8,1" +) +xt "-6300,65000,300,66000" +st "FACT_FAD_LIB" +blo "-6300,65800" +tm "BdLibraryNameMgr" +) +*107 (Text +uid 1772,0 +va (VaSet +font "Arial,8,1" +) +xt "-6300,66000,300,67000" +st "trigger_counter" +blo "-6300,66800" +tm "CptNameMgr" +) +*108 (Text +uid 1773,0 +va (VaSet +font "Arial,8,1" +) +xt "-6300,67000,1300,68000" +st "I_main_ext_trigger" +blo "-6300,67800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1774,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1775,0 +text (MLText +uid 1776,0 +va (VaSet +font "Courier New,8,0" +) +xt "-18000,61000,-18000,61000" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 1777,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "-17750,65250,-16250,66750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sIVOD 1 +) +archFileType "UNKNOWN" +) +*109 (Net +uid 1981,0 +lang 2 +decl (Decl +n "trigger_id" +t "std_logic_vector" +b "(47 downto 0)" +preAdd 0 +posAdd 0 +o 81 +suid 34,0 +) +declText (MLText +uid 1982,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,84200,-52500,85000" +st "SIGNAL trigger_id : std_logic_vector(47 downto 0)" +) +) +*110 (Net +uid 2297,0 +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAMADDRWIDTH64b-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 71 +suid 36,0 +) +declText (MLText +uid 2298,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,76200,-45000,77000" +st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" +) +) +*111 (SaComponent +uid 2311,0 +optionalChildren [ +*112 (CptPort +uid 2307,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2308,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,69625,72000,70375" +) +tg (CPTG +uid 2309,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2310,0 +va (VaSet +font "arial,8,0" +) +xt "73000,69500,91400,70500" +st "ram_start_addr : (RAM_ADDR_WIDTH_64B-1:0)" +blo "73000,70300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH_64B-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 18 +suid 1,0 +i "(others => '0')" +) +) +) +*113 (CptPort +uid 2351,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2352,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,67625,72000,68375" +) +tg (CPTG +uid 2353,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2354,0 +va (VaSet +font "arial,8,0" +) +xt "73000,67500,74300,68500" +st "clk" +blo "73000,68300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "clk" +t "std_logic" +o 1 +suid 2,0 +) +) +) +*114 (CptPort +uid 2361,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2362,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,76625,72000,77375" +) +tg (CPTG +uid 2363,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2364,0 +va (VaSet +font "arial,8,0" +) +xt "73000,76500,78100,77500" +st "config_ready" +blo "73000,77300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "config_ready" +t "std_logic" +o 6 +suid 5,0 +i "'0'" +) +) +) +*115 (CptPort +uid 2365,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2366,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,74625,72000,75375" +) +tg (CPTG +uid 2367,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2368,0 +va (VaSet +font "arial,8,0" +) +xt "73000,74500,77800,75500" +st "config_start" +blo "73000,75300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "config_start" +t "std_logic" +o 2 +suid 3,0 +) +) +) +*116 (CptPort +uid 2369,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2370,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,70625,72000,71375" +) +tg (CPTG +uid 2371,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2372,0 +va (VaSet +font "arial,8,0" +) +xt "73000,70500,78300,71500" +st "ram_write_ea" +blo "73000,71300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "ram_write_ea" +t "std_logic" +o 5 +suid 4,0 +i "'0'" +) +) +) +*117 (CptPort +uid 2373,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2374,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,71625,72000,72375" +) +tg (CPTG +uid 2375,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2376,0 +va (VaSet +font "arial,8,0" +) +xt "73000,71500,79300,72500" +st "ram_write_ready" +blo "73000,72300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "ram_write_ready" +t "std_logic" +o 3 +suid 12,0 +) +) +) +*118 (CptPort +uid 2377,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2378,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,77625,72000,78375" +) +tg (CPTG +uid 2379,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2380,0 +va (VaSet +font "arial,8,0" +) +xt "73000,77500,76000,78500" +st "roi_max" +blo "73000,78300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "roi_max" +t "roi_max_type" +posAdd 0 +o 8 +suid 14,0 +i "(others => conv_std_logic_vector (0, 11))" +) +) +) +*119 (CptPort +uid 2381,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2382,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,67625,103750,68375" +) +tg (CPTG +uid 2383,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2384,0 +va (VaSet +font "arial,8,0" +) +xt "98600,67500,102000,68500" +st "wiz_busy" +ju 2 +blo "102000,68300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "wiz_busy" +t "std_logic" +o 16 +suid 13,0 +) +) +) +*120 (CptPort +uid 2385,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2386,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,71625,103750,72375" +) +tg (CPTG +uid 2387,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2388,0 +va (VaSet +font "arial,8,0" +) +xt "90200,71500,102000,72500" +st "wiz_number_of_channels : (3:0)" +ju 2 +blo "102000,72300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_number_of_channels" +t "std_logic_vector" +b "(3 downto 0)" +o 12 +suid 6,0 +i "(others => '0')" +) +) +) +*121 (CptPort +uid 2389,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2390,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,70625,103750,71375" +) +tg (CPTG +uid 2391,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2392,0 +va (VaSet +font "arial,8,0" +) +xt "82100,70500,102000,71500" +st "wiz_ram_start_addr : (RAM_ADDR_WIDTH_16B-1:0)" +ju 2 +blo "102000,71300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH_16B-1 downto 0)" +preAdd 0 +o 10 +suid 7,0 +i "(others => '0')" +) +) +) +*122 (CptPort +uid 2393,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2394,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,68625,103750,69375" +) +tg (CPTG +uid 2395,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2396,0 +va (VaSet +font "arial,8,0" +) +xt "96900,68500,102000,69500" +st "wiz_write_ea" +ju 2 +blo "102000,69300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_ea" +t "std_logic" +o 13 +suid 8,0 +i "'0'" +) +) +) +*123 (CptPort +uid 2397,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2398,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,72625,103750,73375" +) +tg (CPTG +uid 2399,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2400,0 +va (VaSet +font "arial,8,0" +) +xt "96500,72500,102000,73500" +st "wiz_write_end" +ju 2 +blo "102000,73300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_end" +t "std_logic" +o 15 +suid 9,0 +i "'0'" +) +) +) +*124 (CptPort +uid 2401,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2402,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,73625,103750,74375" +) +tg (CPTG +uid 2403,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2404,0 +va (VaSet +font "arial,8,0" +) +xt "95400,73500,102000,74500" +st "wiz_write_header" +ju 2 +blo "102000,74300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_header" +t "std_logic" +o 14 +suid 10,0 +i "'0'" +) +) +) +*125 (CptPort +uid 2405,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2406,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,69625,103750,70375" +) +tg (CPTG +uid 2407,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2408,0 +va (VaSet +font "arial,8,0" +) +xt "92600,69500,102000,70500" +st "wiz_write_length : (16:0)" +ju 2 +blo "102000,70300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_length" +t "std_logic_vector" +b "(16 downto 0)" +o 11 +suid 11,0 +i "(others => '0')" +) +) +) +*126 (CptPort +uid 2454,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2455,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,84625,72000,85375" +) +tg (CPTG +uid 2456,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2457,0 +va (VaSet +font "arial,8,0" +) +xt "73000,84500,76400,85500" +st "roi_array" +blo "73000,85300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "roi_array" +t "roi_array_type" +o 4 +suid 15,0 +) +) +) +*127 (CptPort +uid 2628,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2629,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,78625,72000,79375" +) +tg (CPTG +uid 2630,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2631,0 +va (VaSet +font "arial,8,0" +) +xt "73000,78500,82100,79500" +st "package_length : (15:0)" +blo "73000,79300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "package_length" +t "std_logic_vector" +b "(15 downto 0)" +o 9 +suid 18,0 +i "(others => '0')" +) +) +) +*128 (CptPort +uid 5991,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5992,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71250,75625,72000,76375" +) +tg (CPTG +uid 5993,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5994,0 +va (VaSet +font "arial,8,0" +) +xt "73000,75500,78600,76500" +st "config_started" +blo "73000,76300" +) +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "config_started" +t "std_logic" +o 7 +suid 21,0 +i "'0'" +) +) +) +*129 (CptPort +uid 8410,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8411,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103000,74625,103750,75375" +) +tg (CPTG +uid 8412,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8413,0 +va (VaSet +font "arial,8,0" +) +xt "99000,74500,102000,75500" +st "wiz_ack" +ju 2 +blo "102000,75300" +) +) +thePort (LogicalPort +lang 2 +decl (Decl +n "wiz_ack" +t "std_logic" +o 17 +suid 22,0 +) +) +) +] +shape (Rectangle +uid 2312,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "72000,67000,103000,87000" +) +oxt "15000,6000,23000,16000" +ttg (MlTextGroup +uid 2313,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*130 (Text +uid 2314,0 +va (VaSet +font "arial,8,1" +) +xt "72350,87000,78550,88000" +st "FACT_FAD_lib" +blo "72350,87800" +tm "BdLibraryNameMgr" +) +*131 (Text +uid 2315,0 +va (VaSet +font "arial,8,1" +) +xt "72350,88000,79650,89000" +st "memory_manager" +blo "72350,88800" +tm "CptNameMgr" +) +*132 (Text +uid 2316,0 +va (VaSet +font "arial,8,1" +) +xt "72350,89000,82850,90000" +st "I_main_memory_manager" +blo "72350,89800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 2317,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 2318,0 +text (MLText +uid 2319,0 +va (VaSet +font "Courier New,8,0" +) +xt "72000,65400,101500,67000" +st "RAM_ADDR_WIDTH_64B = RAMADDRWIDTH64b ( integer ) +RAM_ADDR_WIDTH_16B = RAMADDRWIDTH64b+2 ( integer ) " +) +header "" +) +elements [ +(GiElement +name "RAM_ADDR_WIDTH_64B" +type "integer" +value "RAMADDRWIDTH64b" +) +(GiElement +name "RAM_ADDR_WIDTH_16B" +type "integer" +value "RAMADDRWIDTH64b+2" +) +] +) +viewicon (ZoomableIcon +uid 2320,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "72250,85250,73750,86750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*133 (Net +uid 2468,0 +lang 2 +decl (Decl +n "wiz_busy" +t "std_logic" +o 84 +suid 38,0 +) +declText (MLText +uid 2469,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,86600,-62500,87400" +st "SIGNAL wiz_busy : std_logic" +) +) +*134 (Net +uid 2474,0 +lang 2 +decl (Decl +n "wiz_write_ea" +t "std_logic" +o 87 +suid 39,0 +i "'0'" +) +declText (MLText +uid 2475,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,89000,-41500,89800" +st "SIGNAL wiz_write_ea : std_logic := '0'" +) +) +*135 (Net +uid 2480,0 +lang 2 +decl (Decl +n "wiz_write_length" +t "std_logic_vector" +b "(16 downto 0)" +o 90 +suid 40,0 +i "(others => '0')" +) +declText (MLText +uid 2481,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,91400,-35500,92200" +st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0')" +) +) +*136 (Net +uid 2486,0 +lang 2 +decl (Decl +n "wiz_ram_start_addr" +t "std_logic_vector" +b "(RAMADDRWIDTH64b+1 DOWNTO 0)" +preAdd 0 +o 86 +suid 41,0 +i "(others => '0')" +) +declText (MLText +uid 2487,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,88200,-35500,89000" +st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')" +) +) +*137 (Net +uid 2492,0 +lang 2 +decl (Decl +n "wiz_number_of_channels" +t "std_logic_vector" +b "(3 downto 0)" +o 85 +suid 42,0 +i "(others => '0')" +) +declText (MLText +uid 2493,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,87400,-35500,88200" +st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0')" +) +) +*138 (Net +uid 2498,0 +lang 2 +decl (Decl +n "wiz_write_end" +t "std_logic" +o 88 +suid 43,0 +i "'0'" +) +declText (MLText +uid 2499,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,89800,-41500,90600" +st "SIGNAL wiz_write_end : std_logic := '0'" +) +) +*139 (Net +uid 2504,0 +lang 2 +decl (Decl +n "wiz_write_header" +t "std_logic" +o 89 +suid 44,0 +i "'0'" +) +declText (MLText +uid 2505,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,90600,-41500,91400" +st "SIGNAL wiz_write_header : std_logic := '0'" +) +) +*140 (Net +uid 2574,0 +decl (Decl +n "ram_write_ea" +t "std_logic" +o 72 +suid 48,0 +) +declText (MLText +uid 2575,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,77000,-62500,77800" +st "SIGNAL ram_write_ea : std_logic" +) +) +*141 (Net +uid 2580,0 +decl (Decl +n "ram_write_ready" +t "std_logic" +o 73 +suid 49,0 +i "'0'" +) +declText (MLText +uid 2581,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,77800,-41500,78600" +st "SIGNAL ram_write_ready : std_logic := '0'" +) +) +*142 (Net +uid 2586,0 +decl (Decl +n "config_start" +t "std_logic" +o 45 +suid 50,0 +i "'0'" +) +declText (MLText +uid 2587,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,56200,-41500,57000" +st "SIGNAL config_start : std_logic := '0'" +) +) +*143 (Net +uid 2592,0 +decl (Decl +n "config_ready" +t "std_logic" +o 42 +suid 51,0 +) +declText (MLText +uid 2593,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,53800,-62500,54600" +st "SIGNAL config_ready : std_logic" +) +) +*144 (Net +uid 2598,0 +decl (Decl +n "roi_max" +t "roi_max_type" +o 75 +suid 52,0 +) +declText (MLText +uid 2599,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,79400,-61000,80200" +st "SIGNAL roi_max : roi_max_type" +) +) +*145 (Net +uid 2640,0 +decl (Decl +n "package_length" +t "std_logic_vector" +b "(15 downto 0)" +o 68 +suid 54,0 +) +declText (MLText +uid 2641,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,73800,-52500,74600" +st "SIGNAL package_length : std_logic_vector(15 downto 0)" +) +) +*146 (Net +uid 2776,0 +decl (Decl +n "adc_oeb" +t "std_logic" +o 17 +suid 57,0 +i "'1'" +) +declText (MLText +uid 2777,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,31000,-45000,31800" +st "adc_oeb : std_logic := '1'" +) +) +*147 (PortIoOut +uid 2798,0 +shape (CompositeShape +uid 2799,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2800,0 +sl 0 +ro 90 +xt "-28000,81625,-26500,82375" +) +(Line +uid 2801,0 +sl 0 +ro 90 +xt "-26500,82000,-26000,82000" +pts [ +"-26000,82000" +"-26500,82000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2802,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2803,0 +va (VaSet +) +xt "-32200,81500,-29000,82500" +st "adc_oeb" +ju 2 +blo "-29000,82300" +tm "WireNameMgr" +) +) +) +*148 (PortIoIn +uid 2804,0 +shape (CompositeShape +uid 2805,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2806,0 +sl 0 +ro 270 +xt "-28000,76625,-26500,77375" +) +(Line +uid 2807,0 +sl 0 +ro 270 +xt "-26500,77000,-26000,77000" +pts [ +"-26500,77000" +"-26000,77000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2808,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2809,0 +va (VaSet +) +xt "-34400,76500,-29000,77500" +st "adc_otr_array" +ju 2 +blo "-29000,77300" +tm "WireNameMgr" +) +) +) +*149 (Net +uid 2924,0 +decl (Decl +n "roi_array" +t "roi_array_type" +o 74 +suid 65,0 +) +declText (MLText +uid 2925,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,78600,-60000,79400" +st "SIGNAL roi_array : roi_array_type" +) +) +*150 (PortIoIn +uid 2950,0 +shape (CompositeShape +uid 2951,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2952,0 +sl 0 +ro 270 +xt "-28000,85625,-26500,86375" +) +(Line +uid 2953,0 +sl 0 +ro 270 +xt "-26500,86000,-26000,86000" +pts [ +"-26500,86000" +"-26000,86000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2954,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2955,0 +va (VaSet +) +xt "-32300,85500,-29000,86500" +st "board_id" +ju 2 +blo "-29000,86300" +tm "WireNameMgr" +) +) +) +*151 (PortIoIn +uid 2956,0 +shape (CompositeShape +uid 2957,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2958,0 +sl 0 +ro 270 +xt "-28000,86625,-26500,87375" +) +(Line +uid 2959,0 +sl 0 +ro 270 +xt "-26500,87000,-26000,87000" +pts [ +"-26500,87000" +"-26000,87000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2960,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2961,0 +va (VaSet +) +xt "-32100,86500,-29000,87500" +st "crate_id" +ju 2 +blo "-29000,87300" +tm "WireNameMgr" +) +) +) +*152 (Grouping +uid 3137,0 +optionalChildren [ +*153 (CommentText +uid 3139,0 +shape (Rectangle +uid 3140,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "125000,175000,142000,176000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 3141,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "125200,175000,134500,176000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*154 (CommentText +uid 3142,0 +shape (Rectangle +uid 3143,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "142000,171000,146000,172000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 3144,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "142200,171000,145200,172000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*155 (CommentText +uid 3145,0 +shape (Rectangle +uid 3146,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "125000,173000,142000,174000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 3147,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "125200,173000,135200,174000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*156 (CommentText +uid 3148,0 +shape (Rectangle +uid 3149,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "121000,173000,125000,174000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 3150,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "121200,173000,123300,174000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*157 (CommentText +uid 3151,0 +shape (Rectangle +uid 3152,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "142000,172000,162000,176000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 3153,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "142200,172200,151400,173200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*158 (CommentText +uid 3154,0 +shape (Rectangle +uid 3155,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "146000,171000,162000,172000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 3156,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "146200,171000,150700,172000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*159 (CommentText +uid 3157,0 +shape (Rectangle +uid 3158,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "121000,171000,142000,173000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 3159,0 +va (VaSet +fg "32768,0,0" +) +xt "128700,171000,134300,173000" +st " +TU Dortmund +Physik / EE +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*160 (CommentText +uid 3160,0 +shape (Rectangle +uid 3161,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "121000,174000,125000,175000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 3162,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "121200,174000,123300,175000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*161 (CommentText +uid 3163,0 +shape (Rectangle +uid 3164,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "121000,175000,125000,176000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 3165,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "121200,175000,123900,176000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*162 (CommentText +uid 3166,0 +shape (Rectangle +uid 3167,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "125000,174000,142000,175000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 3168,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "125200,174000,137600,175000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 3138,0 +va (VaSet +vasetType 1 +fg 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"73250,99625,74000,100375" +) +tg (CPTG +uid 5030,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5031,0 +va (VaSet +) +xt "75000,99500,76300,100500" +st "clk" +blo "75000,100300" +) +) +thePort (LogicalPort +decl (Decl +n "clk" +t "STD_LOGIC" +o 1 +suid 1,0 +) +) +) +*217 (CptPort +uid 5032,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5033,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92000,99625,92750,100375" +) +tg (CPTG +uid 5034,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5035,0 +va (VaSet +) +xt "84000,99500,91000,100500" +st "config_addr : (7:0)" +ju 2 +blo "91000,100300" +) +) +thePort (LogicalPort +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 2 +suid 2,0 +) +) +) +*218 (CptPort +uid 5036,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5037,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92000,101625,92750,102375" +) +tg (CPTG +uid 5038,0 +ps "CptPortTextPlaceStrategy" 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(VaSet +) +xt "83300,100500,91000,101500" +st "config_data : (15:0)" +ju 2 +blo "91000,101300" +) +) +thePort (LogicalPort +m 2 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 14 +suid 5,0 +) +) +) +*221 (CptPort +uid 5048,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5049,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "73250,101625,74000,102375" +) +tg (CPTG +uid 5050,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5051,0 +va (VaSet +) +xt "75000,101500,78400,102500" +st "roi_array" +blo "75000,102300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "roi_array" +t "roi_array_type" +o 13 +suid 6,0 +) +) +) +*222 (CptPort +uid 5052,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5053,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92000,103625,92750,104375" +) +tg (CPTG +uid 5054,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5055,0 +va (VaSet +) +xt "85700,103500,91000,104500" +st "config_wr_en" +ju 2 +blo "91000,104300" +) +) +thePort (LogicalPort +decl (Decl +n "config_wr_en" +t "std_logic" +o 5 +suid 7,0 +) +) +) +*223 (CptPort +uid 5056,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5057,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "73250,108625,74000,109375" +) +tg (CPTG +uid 5058,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5059,0 +va (VaSet +) +xt "75000,108500,78700,109500" +st "dac_array" +blo "75000,109300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "dac_array" +t "dac_array_type" +o 10 +suid 8,0 +) +) +) +*224 (CptPort +uid 5060,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5061,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92000,104625,92750,105375" +) +tg (CPTG +uid 5062,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5063,0 +va (VaSet +) +xt "85800,104500,91000,105500" +st "config_rd_en" +ju 2 +blo "91000,105300" +) +) +thePort (LogicalPort +decl (Decl +n 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"OnEdgeStrategy" +shape (Triangle +uid 5996,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "73250,103625,74000,104375" +) +tg (CPTG +uid 5997,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5998,0 +va (VaSet +) +xt "75000,103500,80600,104500" +st "config_started" +blo "75000,104300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_started" +t "std_logic" +o 9 +suid 12,0 +i "'0'" +) +) +) +*228 (CptPort +uid 8500,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8501,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92000,109625,92750,110375" +) +tg (CPTG +uid 8502,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8503,0 +va (VaSet +) +xt "83800,109500,91000,110500" +st "drs_address : (3:0)" +ju 2 +blo "91000,110300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 11 +suid 13,0 +) +) +) +*229 (CptPort +uid 8504,0 +ps "OnEdgeStrategy" +shape (Triangle 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5077,0 +va (VaSet +font "Arial,8,1" +) +xt "74200,114000,82400,115000" +st "I_main_control_unit" +blo "74200,114800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 5078,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 5079,0 +text (MLText +uid 5080,0 +va (VaSet +font "Courier New,8,0" +) +xt "59000,98800,59000,98800" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 5081,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "74250,110250,75750,111750" +iconName "BlockDiagram.png" +iconMaskName "BlockDiagram.msk" +ftype 1 +) +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*233 (Net +uid 5088,0 +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 37 +suid 119,0 +) +declText (MLText +uid 5089,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,49800,-53000,50600" +st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0)" +) +) +*234 (Net +uid 5096,0 +decl (Decl +n "config_data_valid" +t "std_logic" +o 40 +suid 120,0 +) +declText (MLText +uid 5097,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,52200,-62500,53000" +st "SIGNAL config_data_valid : std_logic" +) +) +*235 (Net +uid 5104,0 +decl (Decl +n "config_busy" +t "std_logic" +o 38 +suid 121,0 +) +declText (MLText +uid 5105,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,50600,-62500,51400" +st "SIGNAL config_busy : std_logic" +) +) +*236 (Net +uid 5112,0 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 39 +suid 122,0 +) +declText (MLText +uid 5113,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,51400,-52500,52200" +st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0)" +) +) +*237 (Net +uid 5120,0 +decl (Decl +n "config_wr_en" +t "std_logic" +o 54 +suid 123,0 +) +declText (MLText +uid 5121,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,62600,-62500,63400" +st "SIGNAL config_wr_en : std_logic" +) +) +*238 (Net +uid 5128,0 +decl (Decl +n "config_rd_en" +t "std_logic" +o 41 +suid 124,0 +) +declText (MLText +uid 5129,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,53000,-62500,53800" +st "SIGNAL config_rd_en : std_logic" +) +) +*239 (Net +uid 5144,0 +decl (Decl +n "dac_array" +t "dac_array_type" +o 55 +suid 126,0 +) +declText (MLText +uid 5145,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,63400,-60000,64200" +st "SIGNAL dac_array : dac_array_type" +) +) +*240 (Net +uid 5194,0 +decl (Decl +n "config_start_cm" +t "std_logic" +o 47 +suid 131,0 +) +declText (MLText +uid 5195,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,57800,-62500,58600" +st "SIGNAL config_start_cm : std_logic" +) +) +*241 (Net +uid 5196,0 +decl (Decl +n "config_ready_cm" +t "std_logic" +o 43 +suid 132,0 +) +declText (MLText +uid 5197,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,54600,-62500,55400" +st "SIGNAL config_ready_cm : std_logic" +) +) +*242 (Net +uid 5220,0 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 DOWNTO 0)" +posAdd 0 +o 22 +suid 133,0 +i "(OTHERS => '0')" +) +declText (MLText +uid 5221,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,35800,-39000,36600" +st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" +) +) +*243 (Net +uid 5279,0 +decl (Decl +n "s_trigger" +t "std_logic" +o 76 +suid 134,0 +i "'0'" +) +declText (MLText +uid 5280,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,80200,-41500,81000" +st "SIGNAL s_trigger : std_logic := '0'" +) +) +*244 (Net +uid 5472,0 +decl (Decl +n "sensor_ready" +t "std_logic" +o 80 +suid 140,0 +) +declText (MLText +uid 5473,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,83400,-62500,84200" +st "SIGNAL sensor_ready : std_logic" +) +) +*245 (Net +uid 5478,0 +decl (Decl +n "sensor_array" +t "sensor_array_type" +o 79 +suid 141,0 +) +declText (MLText +uid 5479,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,82600,-58500,83400" +st "SIGNAL sensor_array : sensor_array_type" +) +) +*246 (Net +uid 5588,0 +decl (Decl +n "config_ready_spi" +t "std_logic" +o 44 +suid 144,0 +) +declText (MLText +uid 5589,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,55400,-62500,56200" +st "SIGNAL config_ready_spi : std_logic" +) +) +*247 (Net +uid 5632,0 +lang 10 +decl (Decl +n "adc_otr" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 35 +suid 146,0 +) +declText (MLText +uid 5633,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,48200,-53000,49000" +st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0)" +) +) +*248 (Net +uid 5640,0 +decl (Decl +n "adc_data_array_int" +t "adc_data_array_type" +o 34 +suid 147,0 +) +declText (MLText +uid 5641,0 +va (VaSet +font "Courier New,8,0" +) +xt "-85000,47400,-57500,48200" +st "SIGNAL adc_data_array_int : adc_data_array_type" +) +) +*249 (SaComponent +uid 5678,0 +optionalChildren [ +*250 (CptPort +uid 5658,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5659,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-18750,75625,-18000,76375" +) +tg (CPTG +uid 5660,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5661,0 +va (VaSet +font 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"ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5119,0 +va (VaSet +) +xt "94000,100000,101700,101000" +st "config_data : (15:0)" +blo "94000,100800" +tm "WireNameMgr" +) +) +on &236 +) +*489 (Wire +uid 5122,0 +shape (OrthoPolyLine +uid 5123,0 +va (VaSet +vasetType 3 +) +xt "92750,82000,126250,104000" +pts [ +"126250,82000" +"119000,82000" +"119000,104000" +"92750,104000" +] +) +start &91 +end &222 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5126,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5127,0 +va (VaSet +) +xt "121000,81000,126300,82000" +st "config_wr_en" +blo "121000,81800" +tm "WireNameMgr" +) +) +on &237 +) +*490 (Wire +uid 5130,0 +shape (OrthoPolyLine +uid 5131,0 +va (VaSet +vasetType 3 +) +xt "92750,83000,126250,105000" +pts [ +"126250,83000" +"120000,83000" +"120000,105000" +"92750,105000" +] +) +start &93 +end &224 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5134,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5135,0 +va (VaSet +) +xt "121000,82000,126200,83000" +st "config_rd_en" +blo "121000,82800" +tm "WireNameMgr" +) +) +on &238 +) +*491 (Wire +uid 5138,0 +optionalChildren [ +*492 (BdJunction +uid 5400,0 +ps "OnConnectorStrategy" +shape (Circle +uid 5401,0 +va (VaSet +vasetType 1 +) +xt "57600,84600,58400,85400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 5139,0 +va (VaSet +vasetType 3 +) +xt "40750,80000,73250,102000" +pts [ +"73250,102000" +"58000,102000" +"58000,80000" +"40750,80000" +] +) +start &221 +end &35 +ss 0 +es 0 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5142,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5143,0 +va (VaSet +) +xt "42000,79000,45400,80000" +st "roi_array" +blo "42000,79800" +tm "WireNameMgr" +) +) +on &149 +) +*493 (Wire +uid 5146,0 +shape (OrthoPolyLine +uid 5147,0 +va (VaSet +vasetType 3 +) +xt "37750,109000,73250,109000" +pts [ +"73250,109000" +"37750,109000" +] +) +start &223 +end &261 +es 0 +sat 32 +eat 32 +st 0 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(VaSet +) +xt "46000,114000,52200,115000" +st "config_start_cm" +blo "46000,114800" +tm "WireNameMgr" +) +) +on &240 +) +*496 (Wire +uid 5190,0 +shape (OrthoPolyLine +uid 5191,0 +va (VaSet +vasetType 3 +) +xt "40750,83000,73250,105000" +pts [ +"73250,105000" +"55000,105000" +"55000,83000" +"40750,83000" +] +) +start &226 +end &46 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5192,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5193,0 +va (VaSet +) +xt "66000,104000,72500,105000" +st "config_ready_cm" +blo "66000,104800" +tm "WireNameMgr" +) +) +on &241 +) +*497 (Wire +uid 5222,0 +shape (OrthoPolyLine +uid 5223,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "148750,71000,153000,71000" +pts [ +"148750,71000" +"153000,71000" +] +) +start &85 +end &19 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5224,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5225,0 +va (VaSet +isHidden 1 +) +xt "150750,70000,152150,71000" +st "led" +blo "150750,70800" +tm "WireNameMgr" +) +) +on &242 +) +*498 (Wire +uid 5281,0 +shape (OrthoPolyLine +uid 5282,0 +va (VaSet +vasetType 3 +) +xt "40750,53000,126250,59000" +pts [ +"126250,59000" +"73000,59000" +"73000,53000" +"40750,53000" +] +) +start &86 +end &48 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5283,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5284,0 +va (VaSet +) +xt "121250,58000,124850,59000" +st "s_trigger" +blo "121250,58800" +tm "WireNameMgr" +) +) +on &243 +) +*499 (Wire +uid 5404,0 +shape (OrthoPolyLine +uid 5405,0 +va (VaSet +vasetType 3 +) +xt "37750,85000,48000,107000" +pts [ +"37750,107000" +"48000,107000" +"48000,85000" +"40750,85000" +] +) +start &262 +end &50 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5406,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5407,0 +va (VaSet +) +xt "39000,106000,45500,107000" +st "config_ready_spi" +blo "39000,106800" +tm "WireNameMgr" +) +) +on &246 +) +*500 (Wire +uid 5474,0 +shape (OrthoPolyLine +uid 5475,0 +va (VaSet +vasetType 3 +) +xt "37750,90000,44000,101000" +pts [ +"37750,101000" +"44000,101000" +"44000,90000" +"40750,90000" +] +) +start &265 +end &52 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5476,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5477,0 +va (VaSet +) +xt "39750,100000,45050,101000" +st "sensor_ready" +blo "39750,100800" +tm "WireNameMgr" +) +) +on &244 +) +*501 (Wire +uid 5480,0 +shape (OrthoPolyLine +uid 5481,0 +va (VaSet +vasetType 3 +) +xt "37750,89000,45000,102000" +pts [ +"37750,102000" +"45000,102000" +"45000,89000" +"40750,89000" +] +) +start &264 +end &51 +sat 32 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5482,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5483,0 +va (VaSet +) +xt "39750,101000,44950,102000" +st "sensor_array" +blo "39750,101800" +tm "WireNameMgr" +) +) +on &245 +) +*502 (Wire +uid 5582,0 +shape (OrthoPolyLine +uid 5583,0 +va (VaSet +vasetType 3 +lineColor "0,0,65535" +) +xt "69000,100000,73250,100000" +pts [ +"69000,100000" +"73250,100000" +] +) +end &216 +sat 16 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5586,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5587,0 +va (VaSet +) +xt "70000,99000,73100,100000" +st "CLK_50" +blo "70000,99800" +tm "WireNameMgr" +) +) +on &165 +) +*503 (Wire +uid 5602,0 +optionalChildren [ +&482 +*504 (BdJunction +uid 6086,0 +ps "OnConnectorStrategy" +shape (Circle +uid 6087,0 +va (VaSet +vasetType 1 +) +xt "67600,43600,68400,44400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 5603,0 +va (VaSet +vasetType 3 +lineColor "0,32896,0" +) +xt "15000,38000,76250,48000" +pts [ +"18250,48000" +"15000,48000" +"15000,38000" +"68000,38000" +"68000,44000" +"76250,44000" +] +) +start &23 +end &313 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5604,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5605,0 +va (VaSet +) +xt "15000,47000,18100,48000" +st "CLK_25" +blo "15000,47800" +tm "WireNameMgr" +) +) +on &174 +) +*505 (Wire +uid 5626,0 +shape (OrthoPolyLine +uid 5627,0 +va (VaSet +vasetType 3 +) +xt "750,76000,18250,76000" +pts [ +"18250,76000" +"750,76000" +] +) +start &45 +end &251 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5630,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5631,0 +va (VaSet +) +xt "11250,75000,18350,76000" +st "adc_data_array_int" +blo "11250,75800" +tm "WireNameMgr" +) +) +on &248 +) +*506 (Wire +uid 5634,0 +shape (OrthoPolyLine +uid 5635,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "750,77000,18250,77000" +pts [ +"18250,77000" +"750,77000" +] +) +start &38 +end &252 +sat 32 +eat 32 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 5638,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5639,0 +va (VaSet +) +xt "11250,76000,16750,77000" +st "adc_otr : (3:0)" +blo "11250,76800" +tm "WireNameMgr" +) +) +on &247 +) +*507 (Wire +uid 5646,0 +shape (OrthoPolyLine +uid 5647,0 +va (VaSet +vasetType 3 +lineColor "49152,0,0" +) +xt "-26000,74000,-18750,74000" +pts [ +"-26000,74000" +"-18750,74000" +] +) +end &254 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5652,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5653,0 +va (VaSet +) +xt "-25000,73000,-20500,74000" +st "CLK_25_PS" +blo "-25000,73800" +tm "WireNameMgr" +) +) +on &163 +) +*508 (Wire +uid 5745,0 +shape (OrthoPolyLine +uid 5746,0 +va (VaSet +vasetType 3 +) +xt "37750,87000,46000,105000" +pts [ +"40750,87000" +"46000,87000" +"46000,105000" +"37750,105000" +] +) +start &54 +end &263 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5749,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5750,0 +va (VaSet +) +xt "39000,104000,45200,105000" +st "config_start_spi" +blo "39000,104800" +tm "WireNameMgr" +) +) +on &258 +) +*509 (Wire +uid 5805,0 +shape (OrthoPolyLine +uid 5806,0 +va (VaSet +vasetType 3 +) +xt "16000,101000,20250,101000" +pts [ +"16000,101000" +"20250,101000" +] +) +end &268 +sat 16 +eat 32 +st 0 +sf 1 +tg (WTG +uid 5809,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5810,0 +va (VaSet +) +xt "17000,100000,20100,101000" +st "CLK_50" +blo "17000,100800" +tm "WireNameMgr" +) +) +on &165 +) +*510 (Wire +uid 5813,0 +shape (OrthoPolyLine +uid 5814,0 +va (VaSet +vasetType 3 +) +xt "-18000,112000,-13000,112000" +pts [ +"-13000,112000" +"-18000,112000" +] +) +start &349 +end &279 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5817,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5818,0 +va (VaSet +isHidden 1 +) +xt "-17000,111000,-15300,112000" +st "sclk" +blo "-17000,111800" +tm "WireNameMgr" +) +) +on &275 +) +*511 (Wire +uid 5821,0 +shape (OrthoPolyLine +uid 5822,0 +va (VaSet +vasetType 3 +) +xt "12000,108000,20250,108000" +pts [ +"20250,108000" +"12000,108000" +] +) +start &271 +end &280 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5825,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5826,0 +va (VaSet +isHidden 1 +) +xt "13000,107000,14400,108000" +st "sio" +blo "13000,107800" +tm "WireNameMgr" +) +) +on &276 +) +*512 (Wire +uid 5829,0 +shape (OrthoPolyLine +uid 5830,0 +va (VaSet +vasetType 3 +) +xt "12000,105000,20250,105000" +pts [ +"20250,105000" +"12000,105000" +] +) +start &266 +end &281 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5833,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5834,0 +va (VaSet +isHidden 1 +) +xt "13000,104000,15800,105000" +st "dac_cs" +blo "13000,104800" +tm "WireNameMgr" +) +) +on &277 +) +*513 (Wire +uid 5837,0 +shape (OrthoPolyLine +uid 5838,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "12000,104000,20250,104000" +pts [ +"20250,104000" +"12000,104000" +] +) +start &267 +end &282 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5841,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5842,0 +va (VaSet +isHidden 1 +) +xt "13000,103000,16900,104000" +st "sensor_cs" +blo "13000,103800" +tm "WireNameMgr" +) +) +on &278 +) +*514 (Wire +uid 5950,0 +shape (OrthoPolyLine +uid 5951,0 +va (VaSet +vasetType 3 +) +xt "40750,54000,126250,60000" +pts [ +"126250,60000" +"72000,60000" +"72000,54000" +"40750,54000" +] +) +start &92 +end &56 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5952,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5953,0 +va (VaSet +) +xt "120250,59000,124850,60000" +st "new_config" +blo "120250,59800" +tm "WireNameMgr" +) +) +on &283 +) +*515 (Wire +uid 5962,0 +shape (OrthoPolyLine +uid 5963,0 +va (VaSet +vasetType 3 +) +xt "40750,55000,126250,61000" +pts [ +"126250,61000" +"71000,61000" +"71000,55000" +"40750,55000" +] +) +start &90 +end &55 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 5964,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5965,0 +va (VaSet +) +xt "119250,60000,124850,61000" +st "config_started" +blo "119250,60800" +tm "WireNameMgr" +) +) +on &284 +) +*516 (Wire +uid 6002,0 +shape (OrthoPolyLine +uid 6003,0 +va (VaSet +vasetType 3 +) +xt "40750,82000,73250,104000" +pts [ +"73250,104000" +"56000,104000" +"56000,82000" +"40750,82000" +] +) +start &227 +end &57 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 6004,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6005,0 +va (VaSet +) +xt "66250,103000,73050,104000" +st "config_started_cu" +blo "66250,103800" +tm "WireNameMgr" +) +) +on &286 +) +*517 (Wire +uid 6008,0 +shape (OrthoPolyLine +uid 6009,0 +va (VaSet +vasetType 3 +) +xt "37750,86000,47000,106000" +pts [ +"37750,106000" +"47000,106000" +"47000,86000" +"40750,86000" +] +) +start &269 +end &59 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 6010,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6011,0 +va (VaSet +) +xt "39000,105000,46000,106000" +st "config_started_spi" +blo "39000,105800" +tm "WireNameMgr" +) +) +on &285 +) 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"-1250,21000,15000,38000" +pts [ +"-1250,21000" +"15000,21000" +"15000,38000" +] +) +start &168 +end &481 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 6074,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6075,0 +va (VaSet +) +xt "750,20000,3850,21000" +st "CLK_25" +blo "750,20800" +tm "WireNameMgr" +) +) +on &174 +) +*521 (Wire +uid 6082,0 +shape (OrthoPolyLine +uid 6083,0 +va (VaSet +vasetType 3 +lineColor "0,32896,0" +) +xt "68000,44000,71250,68000" +pts [ +"71250,68000" +"68000,68000" +"68000,44000" +] +) +start &113 +end &504 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 6084,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6085,0 +va (VaSet +) +xt "68000,67000,71100,68000" +st "CLK_25" +blo "68000,67800" +tm "WireNameMgr" +) +) +on &174 +) +*522 (Wire +uid 6160,0 +shape (OrthoPolyLine +uid 6161,0 +va (VaSet +vasetType 3 +) +xt "12000,109000,20250,109000" +pts [ +"20250,109000" +"12000,109000" +] +) +start &270 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(Text +uid 6367,0 +va (VaSet +isHidden 1 +) +xt "150000,74000,153000,75000" +st "denable" +blo "150000,74800" +tm "WireNameMgr" +) +) +on &290 +) +*525 (Wire +uid 6452,0 +shape (OrthoPolyLine +uid 6453,0 +va (VaSet +vasetType 3 +) +xt "148750,76000,153000,76000" +pts [ +"148750,76000" +"153000,76000" +] +) +start &95 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 6456,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6457,0 +va (VaSet +isHidden 1 +) +xt "150000,75000,155400,76000" +st "dwrite_enable" +blo "150000,75800" +tm "WireNameMgr" +) +) +on &292 +) +*526 (Wire +uid 6540,0 +shape (OrthoPolyLine +uid 6541,0 +va (VaSet +vasetType 3 +) +xt "7000,59000,18250,59000" +pts [ +"7000,59000" +"18250,59000" +] +) +start &297 +end &41 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 6542,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6543,0 +va (VaSet +) +xt "7000,58000,9400,59000" +st "dwrite" +blo "7000,58800" +tm "WireNameMgr" +) +) +on &311 +) +*527 (Wire +uid 6548,0 +shape (OrthoPolyLine +uid 6549,0 +va (VaSet +vasetType 3 +) +xt "7000,61000,15000,61000" +pts [ +"7000,61000" +"15000,61000" +] +) +start &299 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 6552,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6553,0 +va (VaSet +) +xt "7000,60000,12400,61000" +st "dwrite_enable" +blo "7000,60800" +tm "WireNameMgr" +) +) +on &292 +) +*528 (Wire +uid 8416,0 +shape (OrthoPolyLine +uid 8417,0 +va (VaSet +vasetType 3 +) +xt "103750,75000,126250,75000" +pts [ +"103750,75000" +"126250,75000" +] +) +start &129 +end &96 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 8418,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8419,0 +va (VaSet +) +xt "104000,74000,107000,75000" +st "wiz_ack" +blo "104000,74800" +tm "WireNameMgr" +) +) +on &323 +) +*529 (Wire +uid 8510,0 +shape (OrthoPolyLine +uid 8511,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "92750,110000,102000,110000" +pts [ +"92750,110000" +"102000,110000" +] +) +start &228 +sat 32 +eat 16 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 8514,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8515,0 +va (VaSet +) +xt "94000,109000,101200,110000" +st "drs_address : (3:0)" +blo "94000,109800" +tm "WireNameMgr" +) +) +on &324 +) +*530 (Wire +uid 8518,0 +shape (OrthoPolyLine +uid 8519,0 +va (VaSet +vasetType 3 +) +xt "92750,111000,102000,111000" +pts [ +"92750,111000" +"102000,111000" +] +) +start &229 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 8522,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8523,0 +va (VaSet +) +xt "94000,110000,101200,111000" +st "drs_address_mode" +blo "94000,110800" +tm "WireNameMgr" +) +) +on &325 +) +*531 (Wire +uid 8577,0 +shape (OrthoPolyLine +uid 8578,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "7000,57000,18250,57000" +pts [ +"18250,57000" +"7000,57000" +] +) +start &39 +sat 32 +eat 16 +sty 1 +st 0 +sf 1 +si 0 +tg (WTG +uid 8581,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8582,0 +va (VaSet +) +xt "8000,56000,18400,57000" +st "drs_channel_internal : (3:0)" +blo "8000,56800" +tm "WireNameMgr" +) +) +on &347 +) +*532 (Wire +uid 8587,0 +shape (OrthoPolyLine +uid 8588,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "-29000,101000,-20000,101000" +pts [ +"-20000,101000" +"-29000,101000" +] +) +end &327 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 8591,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8592,0 +va (VaSet +) +xt "-29000,100000,-20800,101000" +st "drs_channel_internal" +blo "-29000,100800" +tm "WireNameMgr" +) +) +on &347 +) +*533 (Wire +uid 8595,0 +shape (OrthoPolyLine +uid 8596,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "-29000,99000,-20000,99000" +pts [ +"-20000,99000" +"-29000,99000" +] +) +end &332 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 8599,0 +ps "ConnStartEndStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8600,0 +va (VaSet +) +xt "-29000,98000,-24000,99000" +st "drs_address" +blo "-29000,98800" +tm "WireNameMgr" +) +) +on &324 +) +*534 (Wire +uid 8603,0 +shape (OrthoPolyLine +uid 8604,0 +va (VaSet +vasetType 3 +) +xt "-31000,103000,-20000,107000" +pts [ +"-20000,107000" +"-31000,107000" +"-31000,103000" +] +) +end &334 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 8607,0 +ps "ConnStartEndStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8608,0 +va (VaSet +) +xt "-29000,106000,-21800,107000" +st "drs_address_mode" +blo "-29000,106800" +tm "WireNameMgr" +) +) +on &325 +) +*535 (Wire +uid 8732,0 +shape (OrthoPolyLine +uid 8733,0 +va (VaSet +vasetType 3 +) +xt "-7000,107000,20250,111000" +pts [ +"20250,107000" +"-1000,107000" +"-1000,111000" +"-7000,111000" +] +) +start &260 +end &354 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 8734,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8735,0 +va (VaSet +) +xt "17250,106000,19350,107000" +st "sclk1" +blo "17250,106800" +tm "WireNameMgr" +) +) +on &366 +) +*536 (Wire +uid 8738,0 +shape (OrthoPolyLine +uid 8739,0 +va (VaSet +vasetType 3 +) +xt "-7000,113000,-1000,113000" +pts [ +"-1000,113000" +"-7000,113000" +] +) +end &352 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 8742,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8743,0 +va (VaSet +) +xt "-5000,112000,-300,113000" +st "sclk_enable" +blo "-5000,112800" +tm "WireNameMgr" +) +) +on &367 +) +*537 (Wire +uid 8752,0 +shape (OrthoPolyLine +uid 8753,0 +va (VaSet +vasetType 3 +) +xt "148750,77000,156000,77000" +pts [ +"148750,77000" +"156000,77000" +] +) +start &97 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 8756,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8757,0 +va (VaSet +) +xt "150000,76000,154700,77000" +st "sclk_enable" +blo "150000,76800" +tm "WireNameMgr" +) +) +on &367 +) +*538 (Wire +uid 8825,0 +shape (OrthoPolyLine +uid 8826,0 +va (VaSet +vasetType 3 +) +xt "21000,124000,27000,124000" +pts [ +"21000,124000" +"27000,124000" +] +) +start &368 +end &395 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 8829,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8830,0 +va (VaSet +isHidden 1 +) +xt "23000,123000,26600,124000" +st "TEST_IN" +blo "23000,123800" +tm "WireNameMgr" +) +) +on &369 +) +*539 (Wire +uid 8880,0 +optionalChildren [ +*540 (BdJunction +uid 9126,0 +ps "OnConnectorStrategy" +shape (Circle +uid 9127,0 +va (VaSet +vasetType 1 +) +xt "61600,115600,62400,116400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 8881,0 +va (VaSet +vasetType 3 +) +xt "59000,103000,73250,116000" +pts [ +"73250,103000" +"62000,103000" +"62000,116000" +"59000,116000" +] +) +start &225 +end &373 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 8882,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8883,0 +va (VaSet +) +xt "67250,102000,72450,103000" +st "config_start1" +blo "67250,102800" +tm "WireNameMgr" +) +) +on &393 +) +*541 (Wire +uid 8935,0 +shape (OrthoPolyLine +uid 8936,0 +va (VaSet +vasetType 3 +) +xt "32000,124000,38250,124000" +pts [ +"32000,124000" +"38250,124000" +] +) +start &397 +end &406 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 8937,0 +ps "ConnStartEndStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8938,0 +va (VaSet +isHidden 1 +) +xt "34000,123000,35800,124000" +st "dout" +blo "34000,123800" +tm "WireNameMgr" +) +) +on &411 +) +*542 (Wire +uid 8941,0 +shape (OrthoPolyLine +uid 8942,0 +va (VaSet +vasetType 3 +) +xt "51750,117000,53000,124000" +pts [ +"51750,124000" +"52000,124000" +"52000,117000" +"53000,117000" +] +) +start &407 +end &371 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 8943,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8944,0 +va (VaSet +) +xt "46750,117000,51350,118000" +st "trigger_out" +blo "46750,117800" +tm "WireNameMgr" +) +) +on &412 +) +*543 (Wire +uid 8947,0 +shape (OrthoPolyLine +uid 8948,0 +va (VaSet +vasetType 3 +) +xt "34000,123000,38250,123000" +pts [ +"34000,123000" +"38250,123000" +] +) +end &405 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 8951,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8952,0 +va (VaSet +) +xt "35000,122000,38100,123000" +st "CLK_50" +blo "35000,122800" +tm "WireNameMgr" +) +) +on &165 +) +*544 (Wire +uid 9083,0 +shape (OrthoPolyLine +uid 9084,0 +va (VaSet +vasetType 3 +) +xt "72000,121000,82000,121000" +pts [ +"72000,121000" +"82000,121000" +] +) +start &418 +end &413 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 9087,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 9088,0 +va (VaSet +isHidden 1 +) +xt "74000,120000,80200,121000" +st "config_start_out" +blo "74000,120800" +tm "WireNameMgr" +) +) +on &414 +) +*545 (Wire +uid 9122,0 +shape (OrthoPolyLine +uid 9123,0 +va (VaSet +vasetType 3 +) +xt "62000,116000,69000,121000" +pts [ +"62000,116000" +"62000,121000" +"69000,121000" +] +) +start &540 +end &416 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 9124,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 9125,0 +va (VaSet +) +xt "63000,120000,68200,121000" +st "config_start1" +blo "63000,120800" +tm "WireNameMgr" +) +) +on &393 +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *546 (PackageList +uid 41,0 +stg "VerticalLayoutStrategy" +textVec [ +*547 (Text +uid 42,0 +va (VaSet +font "arial,8,1" +) +xt "-87000,1000,-81600,2000" +st "Package List" +blo "-87000,1800" +) +*548 (MLText +uid 43,0 +va (VaSet +) +xt "-87000,2000,-72600,14000" +st "library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use ieee.STD_LOGIC_UNSIGNED.all; + +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + +library UNISIM; +use UNISIM.VComponents.all; +USE IEEE.NUMERIC_STD.all; +USE IEEE.std_logic_signed.all;" +tm "PackageList" +) +] +) +compDirBlock (MlTextGroup +uid 44,0 +stg "VerticalLayoutStrategy" +textVec [ +*549 (Text +uid 45,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "20000,0,28100,1000" +st "Compiler Directives" +blo "20000,800" +) +*550 (Text +uid 46,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "20000,1000,29600,2000" +st "Pre-module directives:" +blo "20000,1800" +) +*551 (MLText +uid 47,0 +va (VaSet +isHidden 1 +) +xt "20000,2000,27500,4000" +st "`resetall +`timescale 1ns/10ps" +tm "BdCompilerDirectivesTextMgr" +) +*552 (Text +uid 48,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "20000,4000,30100,5000" +st "Post-module directives:" +blo "20000,4800" +) +*553 (MLText +uid 49,0 +va (VaSet +isHidden 1 +) +xt "20000,0,20000,0" +tm "BdCompilerDirectivesTextMgr" +) +*554 (Text +uid 50,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "20000,5000,29900,6000" +st "End-module directives:" +blo "20000,5800" +) +*555 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/firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.info/Synthesis/Constraints/FAD_main.ctr =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.info/Synthesis/Constraints/FAD_main.ctr (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.info/Synthesis/Constraints/FAD_main.ctr (revision 9841) @@ -0,0 +1,6 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700an +# set_package fgg484 +# set_speed -4 + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.info/Synthesis/Constraints/FAD_main.sdc =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.info/Synthesis/Constraints/FAD_main.sdc (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.info/Synthesis/Constraints/FAD_main.sdc (revision 9841) @@ -0,0 +1,6 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700an +# set_package fgg484 +# set_speed -4 + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb (revision 9841) @@ -0,0 +1,3397 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "FACT_FAD_lib" +unitName "fad_definitions" +) +] +libraryRefs [ +"ieee" +"FACT_FAD_lib" +] +) +version "24.1" +appVersion "2009.2 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"C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main" +) +(vvPair +variable "d_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main" +) +(vvPair +variable "date" +value "27.07.2010" +) +(vvPair +variable "day" +value "Di" +) +(vvPair +variable "day_long" +value "Dienstag" +) +(vvPair +variable "dd" +value "27" +) +(vvPair +variable "entity_name" +value "FAD_main" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "E5B-LABOR6" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_PrecisionSynthesisDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "07" +) +(vvPair +variable "module_name" +value "FAD_main" +) +(vvPair +variable "month" +value "Jul" +) +(vvPair +variable "month_long" +value "Juli" +) +(vvPair +variable "p" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "10:53:52" +) +(vvPair +variable "unit" +value "FAD_main" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 51,0 +optionalChildren [ +*119 (SymbolBody +uid 8,0 +optionalChildren [ +*120 (CptPort +uid 135,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 136,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,-3375,43750,-2625" +) +tg (CPTG +uid 137,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 138,0 +va (VaSet +) +xt "38400,-3500,42000,-2500" +st "wiz_reset" +ju 2 +blo "42000,-2700" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 140,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,25200,78000,26000" +st "wiz_reset : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_reset" +t "std_logic" +o 30 +suid 2,0 +i "'1'" +) +) +) +*121 (CptPort +uid 163,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 164,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,42625,43750,43375" +) +tg (CPTG +uid 165,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 166,0 +va (VaSet +) +xt "38000,42500,42000,43500" +st "led : (7:0)" +ju 2 +blo "42000,43300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 168,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,19600,84000,20400" +st "led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 DOWNTO 0)" +posAdd 0 +o 23 +suid 7,0 +i "(OTHERS => '0')" +) +) +) +*122 (CptPort +uid 464,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 465,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,4625,15000,5375" +) +tg (CPTG +uid 466,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 467,0 +va (VaSet +) +xt "16000,4500,18800,5500" +st "trigger" +blo "16000,5300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 468,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10000,64500,10800" +st "trigger : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "trigger" +t "std_logic" +preAdd 0 +posAdd 0 +o 11 +suid 18,0 +) +) +) +*123 (CptPort +uid 833,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 834,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,15625,15000,16375" +) +tg (CPTG +uid 835,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 836,0 +va (VaSet +) +xt "16000,15500,19200,16500" +st "adc_oeb" +blo "16000,16300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 837,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,14800,78000,15600" +st "adc_oeb : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "adc_oeb" +t "std_logic" +o 17 +suid 21,0 +i "'1'" +) +) +) +*124 (CptPort +uid 923,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 924,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,6625,15000,7375" +) +tg (CPTG +uid 925,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 926,0 +va (VaSet +) +xt "16000,6500,21900,7500" +st "board_id : (3:0)" +blo "16000,7300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 927,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,8400,74500,9200" +st "board_id : IN std_logic_vector (3 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "board_id" +t "std_logic_vector" +b "(3 downto 0)" +preAdd 0 +posAdd 0 +o 9 +suid 24,0 +) +) +) +*125 (CptPort +uid 928,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 929,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,7625,15000,8375" +) +tg (CPTG +uid 930,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 931,0 +va (VaSet +) +xt "16000,7500,21700,8500" +st "crate_id : (1:0)" +blo "16000,8300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 932,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,9200,74500,10000" +st "crate_id : IN std_logic_vector (1 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "crate_id" +t "std_logic_vector" +b "(1 downto 0)" +o 10 +suid 25,0 +) +) +) +*126 (CptPort +uid 1037,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1038,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,-6375,43750,-5625" +) +tg (CPTG +uid 1039,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1040,0 +va (VaSet +) +xt "36000,-6500,42000,-5500" +st "wiz_addr : (9:0)" +ju 2 +blo "42000,-5700" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1041,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,22800,74500,23600" +st "wiz_addr : OUT std_logic_vector (9 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_addr" +t "std_logic_vector" +b "(9 DOWNTO 0)" +o 27 +suid 26,0 +) +) +) +*127 (CptPort +uid 1042,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 1043,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,-5375,43750,-4625" +) +tg (CPTG +uid 1044,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1045,0 +va (VaSet +) +xt "35700,-5500,42000,-4500" +st "wiz_data : (15:0)" +ju 2 +blo "42000,-4700" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1046,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,27600,74000,28400" +st "wiz_data : INOUT std_logic_vector (15 DOWNTO 0) +" +) +thePort (LogicalPort +m 2 +decl (Decl +n "wiz_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 33 +suid 27,0 +) +) +) +*128 (CptPort +uid 1047,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1048,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,625,43750,1375" +) +tg (CPTG +uid 1049,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1050,0 +va (VaSet +) +xt "39300,500,42000,1500" +st "wiz_cs" +ju 2 +blo "42000,1300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1051,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,23600,78000,24400" +st "wiz_cs : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_cs" +t "std_logic" +o 28 +suid 28,0 +i "'1'" +) +) +) +*129 (CptPort +uid 1052,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1053,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,-1375,43750,-625" +) +tg (CPTG +uid 1054,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1055,0 +va (VaSet +) +xt "39300,-1500,42000,-500" +st "wiz_wr" +ju 2 +blo "42000,-700" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1056,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,26000,78000,26800" +st "wiz_wr : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_wr" +t "std_logic" +o 31 +suid 29,0 +i "'1'" +) +) +) +*130 (CptPort +uid 1057,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1058,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,-2375,43750,-1625" +) +tg (CPTG +uid 1059,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1060,0 +va (VaSet +) +xt "39400,-2500,42000,-1500" +st "wiz_rd" +ju 2 +blo "42000,-1700" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1061,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,24400,78000,25200" +st "wiz_rd : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_rd" +t "std_logic" +o 29 +suid 30,0 +i "'1'" +) +) +) +*131 (CptPort +uid 1062,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1063,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,-375,43750,375" +) +tg (CPTG +uid 1064,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1065,0 +va (VaSet +) +xt "39300,-500,42000,500" +st "wiz_int" +ju 2 +blo "42000,300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1066,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10800,64500,11600" +st "wiz_int : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "wiz_int" +t "std_logic" +o 12 +suid 31,0 +) +) +) +*132 (CptPort +uid 1389,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1390,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,-4375,15000,-3625" +) +tg (CPTG +uid 1391,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1392,0 +va (VaSet +) +xt "16000,-4500,20500,-3500" +st "CLK_25_PS" +blo "16000,-3700" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1393,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,11600,64500,12400" +st "CLK_25_PS : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "CLK_25_PS" +t "std_logic" +o 13 +suid 35,0 +) +) +) +*133 (CptPort +uid 1725,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1726,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,-5375,15000,-4625" +) +tg (CPTG +uid 1727,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1728,0 +va (VaSet +) +xt "16000,-5500,19100,-4500" +st "CLK_50" +blo "16000,-4700" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1729,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,12400,64500,13200" +st "CLK_50 : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "CLK_50" +t "std_logic" +preAdd 0 +posAdd 0 +o 14 +suid 37,0 +) +) +) +*134 (CptPort +uid 1755,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1756,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,-6375,15000,-5625" +) +tg (CPTG +uid 1757,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1758,0 +va (VaSet +) +xt "16000,-6500,17900,-5500" +st "CLK" +blo "16000,-5700" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1759,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2000,64500,2800" +st "CLK : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "CLK" +t "std_logic" +o 1 +suid 38,0 +) +) +) +*135 (CptPort +uid 1976,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1977,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,14625,15000,15375" +) +tg (CPTG +uid 1978,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1979,0 +va (VaSet +) +xt "16000,14500,24000,15500" +st "adc_otr_array : (3:0)" +blo "16000,15300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1980,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,7600,74500,8400" +st "adc_otr_array : IN std_logic_vector (3 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "adc_otr_array" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 8 +suid 40,0 +) +) +) +*136 (CptPort +uid 2282,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2283,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,20625,15000,21375" +) +tg (CPTG +uid 2284,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2285,0 +va (VaSet +) +xt "16000,20500,21900,21500" +st "adc_data_array" +blo "16000,21300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2286,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6800,70000,7600" +st "adc_data_array : IN adc_data_array_type ; +" +) +thePort (LogicalPort +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 7 +suid 41,0 +) +) +) +*137 (CptPort +uid 2448,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2449,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,34625,15000,35375" +) +tg (CPTG +uid 2450,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2451,0 +va (VaSet +) +xt "16000,34500,24500,35500" +st "drs_channel_id : (3:0)" +blo "16000,35300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2452,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,18000,84000,18800" +st "drs_channel_id : OUT std_logic_vector (3 downto 0) := (others => '0') ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_channel_id" +t "std_logic_vector" +b "(3 downto 0)" +o 21 +suid 48,0 +i "(others => '0')" +) +) +) +*138 (CptPort +uid 2453,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2454,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,35625,15000,36375" +) +tg (CPTG +uid 2455,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2456,0 +va (VaSet +) +xt "16000,35500,20300,36500" +st "drs_dwrite" +blo "16000,36300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2457,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,18800,78000,19600" +st "drs_dwrite : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_dwrite" +t "std_logic" +o 22 +suid 49,0 +i "'1'" +) +) +) +*139 (CptPort +uid 2710,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2711,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,30625,15000,31375" +) +tg (CPTG +uid 2712,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2713,0 +va (VaSet +) +xt "16000,30500,21400,31500" +st "SROUT_in_0" +blo "16000,31300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2714,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2800,64500,3600" +st "SROUT_in_0 : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "SROUT_in_0" +t "std_logic" +o 2 +suid 52,0 +) +) +) +*140 (CptPort +uid 2715,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2716,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,31625,15000,32375" +) +tg (CPTG +uid 2717,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2718,0 +va (VaSet +) +xt "16000,31500,21400,32500" +st "SROUT_in_1" +blo "16000,32300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2719,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3600,64500,4400" +st "SROUT_in_1 : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "SROUT_in_1" +t "std_logic" +o 3 +suid 53,0 +) +) +) +*141 (CptPort +uid 2720,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2721,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,32625,15000,33375" +) +tg (CPTG +uid 2722,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2723,0 +va (VaSet +) +xt "16000,32500,21400,33500" +st "SROUT_in_2" +blo "16000,33300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2724,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,4400,64500,5200" +st "SROUT_in_2 : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "SROUT_in_2" +t "std_logic" +o 4 +suid 54,0 +) +) +) +*142 (CptPort +uid 2725,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2726,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,33625,15000,34375" +) +tg (CPTG +uid 2727,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2728,0 +va (VaSet +) +xt "16000,33500,21400,34500" +st "SROUT_in_3" +blo "16000,34300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2729,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,5200,64500,6000" +st "SROUT_in_3 : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "SROUT_in_3" +t "std_logic" +o 5 +suid 55,0 +) +) +) +*143 (CptPort +uid 2987,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2988,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,36625,15000,37375" +) +tg (CPTG +uid 2989,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2990,0 +va (VaSet +) +xt "16000,36500,20200,37500" +st "RSRLOAD" +blo "16000,37300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2991,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,13200,78000,14000" +st "RSRLOAD : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "RSRLOAD" +t "std_logic" +o 15 +suid 56,0 +i "'0'" +) +) +) +*144 (CptPort +uid 2992,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2993,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,38625,15000,39375" +) +tg (CPTG +uid 2994,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2995,0 +va (VaSet +) +xt "16000,38500,19000,39500" +st "SRCLK" +blo "16000,39300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2996,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,14000,78000,14800" +st "SRCLK : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "SRCLK" +t "std_logic" +o 16 +suid 57,0 +i "'0'" +) +) +) +*145 (CptPort +uid 3631,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3632,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,23625,43750,24375" +) +tg (CPTG +uid 3633,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3634,0 +va (VaSet +) +xt "40300,23500,42000,24500" +st "sclk" +ju 2 +blo "42000,24300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 3635,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,21200,64500,22000" +st "sclk : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sclk" +t "std_logic" +o 25 +suid 62,0 +) +) +) +*146 (CptPort +uid 3636,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 3637,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,24625,43750,25375" +) +tg (CPTG +uid 3638,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3639,0 +va (VaSet +) +xt "40600,24500,42000,25500" +st "sio" +ju 2 +blo "42000,25300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 3640,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,26800,64500,27600" +st "sio : INOUT std_logic ; +" +) +thePort (LogicalPort +m 2 +decl (Decl +n "sio" +t "std_logic" +preAdd 0 +posAdd 0 +o 32 +suid 63,0 +) +) +) +*147 (CptPort +uid 3641,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3642,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,12625,43750,13375" +) +tg (CPTG +uid 3643,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3644,0 +va (VaSet +) +xt "39200,12500,42000,13500" +st "dac_cs" +ju 2 +blo "42000,13300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 3645,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,16400,64500,17200" +st "dac_cs : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "dac_cs" +t "std_logic" +o 19 +suid 64,0 +) +) +) +*148 (CptPort +uid 3646,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3647,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,14625,43750,15375" +) +tg (CPTG +uid 3648,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3649,0 +va (VaSet +) +xt "35500,14500,42000,15500" +st "sensor_cs : (3:0)" +ju 2 +blo "42000,15300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 3650,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,22000,74500,22800" +st "sensor_cs : OUT std_logic_vector (3 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sensor_cs" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 26 +suid 65,0 +) +) +) +*149 (CptPort +uid 4067,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4068,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,25625,43750,26375" +) +tg (CPTG +uid 4069,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4070,0 +va (VaSet +) +xt "40000,25500,42000,26500" +st "mosi" +ju 2 +blo "42000,26300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 4071,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,20400,78000,21200" +st "mosi : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "mosi" +t "std_logic" +o 24 +suid 66,0 +i "'0'" +) +) +) +*150 (CptPort +uid 4144,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4145,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,43625,43750,44375" +) +tg (CPTG +uid 4146,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4147,0 +va (VaSet +) +xt "39000,43500,42000,44500" +st "denable" +ju 2 +blo "42000,44300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 4148,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,17200,91500,18000" +st "denable : OUT std_logic := '0' ; -- default domino wave off +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "denable" +t "std_logic" +eolc "-- default domino wave off" +posAdd 0 +o 20 +suid 67,0 +i "'0'" +) +) +) +*151 (CptPort +uid 4323,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4324,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,39625,15000,40375" +) +tg (CPTG +uid 4325,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4326,0 +va (VaSet +) +xt "16000,39500,19600,40500" +st "TEST_IN" +blo "16000,40300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 4327,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6000,64500,6800" +st "TEST_IN : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "TEST_IN" +t "std_logic" +o 6 +suid 69,0 +) +) +) +*152 (CptPort +uid 4422,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4423,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,44625,43750,45375" +) +tg (CPTG +uid 4424,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4425,0 +va (VaSet +) +xt "35800,44500,42000,45500" +st "config_start_out" +ju 2 +blo "42000,45300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 4426,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,15600,78000,16400" +st "config_start_out : OUT STD_LOGIC := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_start_out" +t "STD_LOGIC" +o 18 +suid 70,0 +i "'0'" +) +) +) +] +shape (Rectangle +uid 4141,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,-8000,43000,46000" +) +oxt "15000,-8000,43000,45000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "15200,45000,21400,46000" +st "FACT_FAD_lib" +blo "15200,45800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "15200,46000,19400,47000" +st "FAD_main" +blo "15200,46800" +) +) +gi *153 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,15500,14400" +st "Generic Declarations + +RAMADDRWIDTH64b integer 12 " +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "RAMADDRWIDTH64b" +type "integer" +value "12" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +) +portVis (PortSigDisplay +) +) +*154 (Grouping +uid 16,0 +optionalChildren [ +*155 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48000,45500,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*156 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,44000,56200,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*157 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,46000,46200,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*158 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,46000,34300,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*159 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,45200,62400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*160 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,44000,61700,45000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*161 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "39150,44500,45850,45500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*162 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,47000,34300,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*163 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,48000,34900,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*164 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,47000,49000,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *165 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*166 (Text +uid 49,0 +va (VaSet +font "arial,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*167 (MLText +uid 50,0 +va (VaSet +) +xt "0,1000,14500,6000" +st "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all;" +tm "PackageList" +) +] +) +windowSize "0,0,1553,1028" +viewArea "-12542,-31642,130863,66614" +cachedDiagramExtent "0,-1000,83000,49000" +hasePageBreakOrigin 1 +pageBreakOrigin "0,-2000" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *168 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) 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"Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,29400,44000,29400" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 4587,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb.bak =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb.bak (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb.bak (revision 9841) @@ -0,0 +1,2320 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" 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IN std_logic_vector (3 downto 0) ;" +) +thePort (LogicalPort +decl (Decl +n "board_id" +t "std_logic_vector" +b "(3 downto 0)" +preAdd 0 +posAdd 0 +o 4 +suid 24,0 +) +) +) +*91 (CptPort +uid 928,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 929,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,17625,15000,18375" +) +tg (CPTG +uid 930,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 931,0 +va (VaSet +) +xt "16000,17500,21700,18500" +st "crate_id : (1:0)" +blo "16000,18300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 932,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,5200,73500,6000" +st "crate_id : IN std_logic_vector (1 downto 0) ;" +) +thePort (LogicalPort +decl (Decl +n "crate_id" +t "std_logic_vector" +b "(1 downto 0)" +o 5 +suid 25,0 +) +) +) +*92 (CptPort +uid 1037,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1038,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,26625,43750,27375" +) +tg (CPTG +uid 1039,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1040,0 +va (VaSet +) +xt "36000,26500,42000,27500" +st "wiz_addr : (9:0)" +ju 2 +blo "42000,27300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1041,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10800,73500,11600" +st "wiz_addr : OUT std_logic_vector (9 DOWNTO 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_addr" +t "std_logic_vector" +b "(9 DOWNTO 0)" +o 12 +suid 26,0 +) +) +) +*93 (CptPort +uid 1042,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 1043,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,27625,43750,28375" +) +tg (CPTG +uid 1044,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1045,0 +va (VaSet +) +xt "35700,27500,42000,28500" +st "wiz_data : (15:0)" +ju 2 +blo "42000,28300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1046,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,14800,73000,15600" +st "wiz_data : INOUT std_logic_vector (15 DOWNTO 0)" +) +thePort (LogicalPort +m 2 +decl (Decl +n "wiz_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 17 +suid 27,0 +) +) +) +*94 (CptPort +uid 1047,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1048,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,28625,43750,29375" +) +tg (CPTG +uid 1049,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1050,0 +va (VaSet +) +xt "39300,28500,42000,29500" +st "wiz_cs" +ju 2 +blo "42000,29300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1051,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,11600,77000,12400" +st "wiz_cs : OUT std_logic := '1' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_cs" +t "std_logic" +o 13 +suid 28,0 +i "'1'" +) +) +) +*95 (CptPort +uid 1052,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1053,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,29625,43750,30375" +) +tg (CPTG +uid 1054,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1055,0 +va (VaSet +) +xt "39300,29500,42000,30500" +st "wiz_wr" +ju 2 +blo "42000,30300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1056,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,14000,77000,14800" +st "wiz_wr : OUT std_logic := '1' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_wr" +t "std_logic" +o 16 +suid 29,0 +i "'1'" +) +) +) +*96 (CptPort +uid 1057,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1058,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,30625,43750,31375" +) +tg (CPTG +uid 1059,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1060,0 +va (VaSet +) +xt "39400,30500,42000,31500" +st "wiz_rd" +ju 2 +blo "42000,31300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1061,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,12400,77000,13200" +st "wiz_rd : OUT std_logic := '1' ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_rd" +t "std_logic" +o 14 +suid 30,0 +i "'1'" +) +) +) +*97 (CptPort +uid 1062,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1063,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,18625,15000,19375" +) +tg (CPTG +uid 1064,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1065,0 +va (VaSet +) +xt "16000,18500,18700,19500" +st "wiz_int" +blo "16000,19300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1066,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6800,63500,7600" +st "wiz_int : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "wiz_int" +t "std_logic" +o 7 +suid 31,0 +) +) +) +*98 (CptPort +uid 1389,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1390,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,31625,43750,32375" +) +tg (CPTG +uid 1391,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1392,0 +va (VaSet +) +xt "37500,31500,42000,32500" +st "CLK_25_PS" +ju 2 +blo "42000,32300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1393,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,7600,63500,8400" +st "CLK_25_PS : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "CLK_25_PS" +t "std_logic" +o 8 +suid 35,0 +) +) +) +*99 (CptPort +uid 1725,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1726,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,32625,43750,33375" +) +tg (CPTG +uid 1727,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1728,0 +va (VaSet +) +xt "38900,32500,42000,33500" +st "CLK_50" +ju 2 +blo "42000,33300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1729,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,8400,63500,9200" +st "CLK_50 : OUT std_logic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "CLK_50" +t "std_logic" +preAdd 0 +posAdd 0 +o 9 +suid 37,0 +) +) +) +*100 (CptPort +uid 1755,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1756,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,19625,15000,20375" +) +tg (CPTG +uid 1757,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1758,0 +va (VaSet +) +xt "16000,19500,17900,20500" +st "CLK" +blo "16000,20300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1759,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2000,63500,2800" +st "CLK : IN std_logic ;" +) +thePort (LogicalPort +decl (Decl +n "CLK" +t "std_logic" +o 1 +suid 38,0 +) +) +) +*101 (CptPort +uid 1976,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1977,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,21625,15000,22375" +) +tg (CPTG +uid 1978,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1979,0 +va (VaSet +) +xt "16000,21500,24000,22500" +st "adc_otr_array : (3:0)" +blo "16000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1980,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3600,73500,4400" +st "adc_otr_array : IN std_logic_vector (3 DOWNTO 0) ;" +) +thePort (LogicalPort +decl (Decl +n "adc_otr_array" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 3 +suid 40,0 +) +) +) +*102 (CptPort +uid 2282,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2283,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,22625,15000,23375" +) +tg (CPTG +uid 2284,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2285,0 +va (VaSet +) +xt "16000,22500,21900,23500" +st "adc_data_array" +blo "16000,23300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2286,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2800,69000,3600" +st "adc_data_array : IN adc_data_array_type ;" +) +thePort (LogicalPort +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 2 +suid 41,0 +) +) +) +] +shape (Rectangle +uid 584,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,-1000,43000,34000" +) +oxt "15000,-1000,43000,26000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "22200,8000,28400,9000" +st "FACT_FAD_lib" +blo "22200,8800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "22200,9000,26400,10000" +st "FAD_main" +blo "22200,9800" +) +) +gi *103 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +) +portVis (PortSigDisplay +) +) +*104 (Grouping +uid 16,0 +optionalChildren [ +*105 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48000,44400,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*106 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,44000,56200,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*107 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,46000,46200,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*108 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,46000,34300,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*109 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,45200,62400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*110 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,44000,61700,45000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*111 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "39150,44500,45850,45500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*112 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,47000,34300,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*113 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,48000,34900,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*114 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,47000,49000,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *115 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*116 (Text +uid 49,0 +va (VaSet +font "arial,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*117 (MLText +uid 50,0 +va (VaSet +) +xt "0,1000,10900,4000" +st "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all;" +tm "PackageList" +) +] +) +windowSize "0,0,1015,690" +viewArea "0,0,0,0" +cachedDiagramExtent "0,0,0,0" +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *118 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *119 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,15600,44400,16600" +st "User:" +blo "42000,16400" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,16600,44000,16600" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 2355,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol:CDM" +) Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_adc_buffer._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_adc_buffer._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_adc_buffer._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom beha +DEFAULT_FILE atom adc_buffer_beha.vhd Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_clock_generator._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_clock_generator._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_clock_generator._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom clock_generator/struct.bd Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_control_manager._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_control_manager._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_control_manager._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom control_manager_beha.vhd +DEFAULT_ARCHITECTURE atom beha Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_control_unit._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_control_unit._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_control_unit._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom control_unit/struct.bd +DEFAULT_ARCHITECTURE atom struct Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_controlram_16bit_x256._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_controlram_16bit_x256._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_controlram_16bit_x256._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom controlRAM_16bit_x256_controlRAM_16bit_x256_a.vhd +DEFAULT_ARCHITECTURE atom controlRAM_16bit_x256_a Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_data_generator._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_data_generator._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_data_generator._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom Behavioral +DEFAULT_FILE atom data_generator.vhd Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_dcm_50_to_25._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_dcm_50_to_25._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_dcm_50_to_25._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom BEHAVIORAL +DEFAULT_FILE atom dcm_50_to_25_BEHAVIORAL.vhd Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_debouncer._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_debouncer._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_debouncer._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom debouncer.vhd +DEFAULT_ARCHITECTURE atom Behavioral Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_drs_pulser._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_drs_pulser._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_drs_pulser._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom drs_pulser_dummy.vhd +DEFAULT_ARCHITECTURE atom behavior Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_fad_board._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_fad_board._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_fad_board._epf (revision 9841) @@ -0,0 +1,3 @@ +DEFAULT_FILE atom @f@a@d_@board/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_fad_main._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_fad_main._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_fad_main._epf (revision 9841) @@ -0,0 +1,3 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom @f@a@d_main/struct.bd +TOP_MARKER atom 0 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_memory_manager._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_memory_manager._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_memory_manager._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom beha +DEFAULT_FILE atom memory_manager_beha.vhd Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_spi_clock_generator._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_spi_clock_generator._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_spi_clock_generator._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom spi_clock_gen_beha.vhd +DEFAULT_ARCHITECTURE atom beha Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_spi_controller._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_spi_controller._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_spi_controller._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom spi_controller_beha.vhd +DEFAULT_ARCHITECTURE atom beha Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_spi_distributor._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_spi_distributor._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_spi_distributor._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom spi_distributor_beha.vhd +DEFAULT_ARCHITECTURE atom beha Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_spi_interface._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_spi_interface._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_spi_interface._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom spi_interface/struct.bd +DEFAULT_ARCHITECTURE atom struct Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_trigger_counter._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_trigger_counter._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_trigger_counter._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom trigger_counter_beha.vhd +DEFAULT_ARCHITECTURE atom beha Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_w5300_modul._epf =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_w5300_modul._epf (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/_w5300_modul._epf (revision 9841) @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom Behavioral +DEFAULT_FILE atom w5300_modul.vhd Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd (revision 9841) @@ -0,0 +1,2979 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "UNISIM" +unitName "Vcomponents" +) +] +instances [ +(Instance +name "U_1" +duLibraryName "FACT_FAD_lib" +duName "dcm_ps_38ns" +elements [ +] +mwi 0 +uid 354,0 +) +(Instance +name "U_0" +duLibraryName "FACT_FAD_lib" +duName "dcm_50_to_25" +elements [ +] +mwi 0 +uid 403,0 +) +] +libraryRefs [ +"ieee" +"UNISIM" +] +) +version "29.1" +appVersion "2009.1 (Build 12)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator" +) +(vvPair +variable "d_logical" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator" +) +(vvPair +variable "date" +value "26.05.2010" +) +(vvPair +variable "day" +value "Mi" +) +(vvPair +variable "day_long" +value "Mittwoch" +) +(vvPair +variable "dd" +value "26" +) +(vvPair +variable "entity_name" +value "clock_generator" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "IHP110" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "05" +) +(vvPair +variable "module_name" +value "clock_generator" +) +(vvPair +variable "month" +value "Mai" +) +(vvPair +variable "month_long" +value "Mai" +) +(vvPair +variable "p" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator\\struct.bd" +) +(vvPair +variable "p_logical" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "D:\\modeltech_6.5e\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "11:23:07" +) +(vvPair +variable "unit" +value "clock_generator" +) +(vvPair +variable "user" +value "daqct3" +) +(vvPair +variable "version" +value "2009.1 (Build 12)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 52,0 +optionalChildren [ +*1 (Grouping +uid 9,0 +optionalChildren [ +*2 (CommentText +uid 11,0 +shape (Rectangle +uid 12,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "31000,50000,48000,51000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 13,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "31200,50000,39400,51000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*3 (CommentText +uid 14,0 +shape (Rectangle +uid 15,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "48000,46000,52000,47000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 16,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "48200,46000,51200,47000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*4 (CommentText +uid 17,0 +shape (Rectangle +uid 18,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "31000,48000,48000,49000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 19,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "31200,48000,41200,49000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*5 (CommentText +uid 20,0 +shape (Rectangle +uid 21,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "27000,48000,31000,49000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 22,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "27200,48000,29300,49000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*6 (CommentText +uid 23,0 +shape (Rectangle +uid 24,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "48000,47000,68000,51000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 25,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "48200,47200,57400,48200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*7 (CommentText +uid 26,0 +shape (Rectangle +uid 27,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "52000,46000,68000,47000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 28,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "52200,46000,56700,47000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*8 (CommentText +uid 29,0 +shape (Rectangle +uid 30,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "27000,46000,48000,48000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 31,0 +va (VaSet +fg "32768,0,0" +) +xt "34150,46500,40850,47500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*9 (CommentText +uid 32,0 +shape (Rectangle +uid 33,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "27000,49000,31000,50000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 34,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "27200,49000,29300,50000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*10 (CommentText +uid 35,0 +shape (Rectangle +uid 36,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "27000,50000,31000,51000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 37,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "27200,50000,29900,51000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*11 (CommentText +uid 38,0 +shape (Rectangle +uid 39,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "31000,49000,48000,50000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 40,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "31200,49000,45400,50000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 10,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "27000,46000,68000,51000" +) +oxt "14000,66000,55000,71000" +) +*12 (PortIoIn +uid 169,0 +shape (CompositeShape +uid 170,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 171,0 +sl 0 +ro 270 +xt "8000,13625,9500,14375" +) +(Line +uid 172,0 +sl 0 +ro 270 +xt "9500,14000,10000,14000" +pts [ +"9500,14000" +"10000,14000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 173,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 174,0 +va (VaSet +font "arial,8,0" +) +xt "5100,13500,7000,14500" +st "CLK" +ju 2 +blo "7000,14300" +tm "WireNameMgr" +) +) +) +*13 (PortIoOut +uid 183,0 +shape (CompositeShape +uid 184,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 185,0 +sl 0 +ro 270 +xt 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(MRCItem +litem &113 +pos 3 +dimension 100 +uid 105,0 +) +*126 (MRCItem +litem &114 +pos 4 +dimension 50 +uid 106,0 +) +*127 (MRCItem +litem &115 +pos 5 +dimension 50 +uid 107,0 +) +*128 (MRCItem +litem &116 +pos 6 +dimension 80 +uid 108,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 96,0 +vaOverrides [ +] +) +] +) +uid 82,0 +type 1 +) +activeModelName "BlockDiag" +) Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd.info/Synthesis/Constraints/clock_generator.ctr =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd.info/Synthesis/Constraints/clock_generator.ctr (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd.info/Synthesis/Constraints/clock_generator.ctr (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700a +# set_package fg484 +# set_speed -4 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd.info/Synthesis/Constraints/clock_generator.sdc =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd.info/Synthesis/Constraints/clock_generator.sdc (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/clock_generator/struct.bd.info/Synthesis/Constraints/clock_generator.sdc (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700a +# set_package fg484 +# set_speed -4 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/clock_generator/symbol.sb =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/clock_generator/symbol.sb (revision 9841) +++ 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+value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator\\symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator" +) +(vvPair +variable "d_logical" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator" +) +(vvPair +variable "date" +value "08.04.2010" +) +(vvPair +variable "day" +value "Do" +) +(vvPair +variable "day_long" +value "Donnerstag" +) +(vvPair +variable "dd" +value "08" +) +(vvPair +variable "entity_name" +value "clock_generator" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "E5PCXX" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "clock_generator" +) +(vvPair +variable "month" +value "Apr" +) +(vvPair +variable "month_long" +value "April" +) +(vvPair +variable "p" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator\\symbol.sb" +) +(vvPair +variable "p_logical" +value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\clock_generator\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "$HDS_HOME/../Exemplar/bin/win32" +) +(vvPair +variable "task_ModelSimPath" +value "D:\\Programme\\FPGAdv82LSPS\\Modeltech\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "$HDS_HOME/../Precision/Mgc_home/bin" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "12:13:40" +) +(vvPair +variable "unit" +value "clock_generator" +) +(vvPair +variable "user" +value "kai" +) +(vvPair +variable "version" +value "2009.1 (Build 12)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 51,0 +optionalChildren [ +*59 (SymbolBody +uid 8,0 +optionalChildren [ +*60 (CptPort +uid 121,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 122,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "46000,13625,46750,14375" +) +tg (CPTG +uid 123,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 124,0 +va (VaSet +font "arial,8,0" +) +xt "41900,13500,45000,14500" +st "CLK_50" +ju 2 +blo "45000,14300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 125,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,4400,60000,5200" +st "CLK_50 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"%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager" +) +(vvPair +variable "d_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager" +) +(vvPair +variable "date" +value "12.07.2010" +) +(vvPair +variable "day" +value "Mo" +) +(vvPair +variable "day_long" +value "Montag" +) +(vvPair +variable "dd" +value "12" +) +(vvPair +variable "entity_name" +value "control_manager" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "TU-CC4900F8C7D2" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "07" +) +(vvPair +variable "module_name" +value "control_manager" +) +(vvPair +variable "month" +value "Jul" +) +(vvPair +variable "month_long" +value "Juli" +) +(vvPair +variable "p" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "14:11:44" +) +(vvPair +variable "unit" +value "control_manager" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 172,0 +optionalChildren [ +*93 (SymbolBody +uid 8,0 +optionalChildren [ +*94 (CptPort +uid 48,0 +ps "OnEdgeStrategy" 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"config_ready : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_ready" +t "std_logic" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +i "'0'" +) +) +) +*96 (CptPort +uid 63,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 64,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,20625,67750,21375" +) +tg (CPTG +uid 65,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 66,0 +va (VaSet +) +xt "61200,20500,66000,21500" +st "config_start" +ju 2 +blo "66000,21300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 67,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,14200,23000,15000" +st "config_start : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_start" +t "std_logic" +preAdd 0 +posAdd 0 +o 5 +suid 4,0 +) +) +) +*97 (CptPort +uid 68,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 69,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,15625,67750,16375" +) +tg (CPTG +uid 70,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 71,0 +va (VaSet +) +xt "58300,15500,66000,16500" +st "config_data : (15:0)" +ju 2 +blo "66000,16300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 72,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,15000,43000,15800" +st "config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z') ; +" +) +thePort (LogicalPort +m 2 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 6 +suid 5,0 +i "(others => 'Z')" +) +) +) +*98 (CptPort +uid 73,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 74,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,14625,67750,15375" +) +tg (CPTG +uid 75,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 76,0 +va (VaSet +) +xt "52600,14500,66000,15500" +st "config_addr : (ADDR_WIDTH - 1:0)" +ju 2 +blo "66000,15300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 77,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,15800,39500,16600" +st "config_addr : IN std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(ADDR_WIDTH - 1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 7 +suid 6,0 +) +) +) +*99 (CptPort +uid 78,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 79,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,17625,67750,18375" +) +tg (CPTG +uid 80,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 81,0 +va (VaSet +) +xt "60700,17500,66000,18500" +st "config_wr_en" +ju 2 +blo "66000,18300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 82,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,16600,23000,17400" +st "config_wr_en : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_wr_en" +t "std_logic" +preAdd 0 +posAdd 0 +o 8 +suid 7,0 +) +) +) +*100 (CptPort +uid 83,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 84,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67000,18625,67750,19375" +) +tg (CPTG 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/firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd (revision 9841) @@ -0,0 +1,5141 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +itemName "ALL" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +itemName "ALL" +) +(DmPackageRef +library "FACT_FAD_LIB" +unitName "fad_definitions" +itemName "ALL" +) +] +instances [ +(Instance +name "I_control_manager" +duLibraryName "FACT_FAD_lib" +duName "control_manager" +elements [ +(GiElement +name "NO_OF_ROI" +type "integer" +value "36" +) +(GiElement +name "NO_OF_DAC" +type "integer" +value "8" +) +(GiElement +name "ADDR_WIDTH" +type "integer" +value "8" +) +] +mwi 0 +uid 960,0 +) +(Instance +name "I_control_ram" +duLibraryName "FACT_FAD_lib" +duName "controlRAM_16bit_x256" +elements [ +] +mwi 0 +uid 993,0 +) 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"%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" +) +(vvPair +variable "d_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" +) +(vvPair +variable "date" +value "12.07.2010" +) +(vvPair +variable "day" +value "Mo" +) +(vvPair +variable "day_long" +value "Montag" +) +(vvPair +variable "dd" +value "12" +) +(vvPair +variable "entity_name" +value "control_unit" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "TU-CC4900F8C7D2" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value 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"BlockDiag" +) Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.bak =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.bak (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.bak (revision 9841) @@ -0,0 +1,4812 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +itemName "ALL" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +itemName "ALL" +) +(DmPackageRef +library "FACT_FAD_LIB" +unitName "fad_definitions" +itemName "ALL" +) +] +instances [ +(Instance +name "I_control_manager" +duLibraryName "FACT_FAD_lib" +duName "control_manager" +elements [ +(GiElement +name "NO_OF_ROI" +type "integer" +value "36" +) +(GiElement +name "NO_OF_DAC" +type "integer" +value "8" +) +(GiElement +name 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"C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" +) +(vvPair +variable "d_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" +) +(vvPair +variable "date" +value "12.07.2010" +) +(vvPair +variable "day" +value "Mo" +) +(vvPair +variable "day_long" +value "Montag" +) +(vvPair +variable "dd" +value "12" +) +(vvPair +variable "entity_name" +value "control_unit" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "TU-CC4900F8C7D2" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "07" +) +(vvPair +variable "module_name" +value "control_unit" +) +(vvPair +variable "month" +value "Jul" +) +(vvPair +variable "month_long" +value "Juli" +) +(vvPair +variable "p" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd" 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+uid 95,0 +optionalChildren [ +*187 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *188 (MRCItem +litem &175 +pos 0 +dimension 20 +) +uid 97,0 +optionalChildren [ +*189 (MRCItem +litem &176 +pos 0 +dimension 20 +uid 98,0 +) +*190 (MRCItem +litem &177 +pos 1 +dimension 23 +uid 99,0 +) +*191 (MRCItem +litem &178 +pos 2 +hidden 1 +dimension 20 +uid 100,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 101,0 +optionalChildren [ +*192 (MRCItem +litem &179 +pos 0 +dimension 20 +uid 102,0 +) +*193 (MRCItem +litem &181 +pos 1 +dimension 50 +uid 103,0 +) +*194 (MRCItem +litem &182 +pos 2 +dimension 100 +uid 104,0 +) +*195 (MRCItem +litem &183 +pos 3 +dimension 100 +uid 105,0 +) +*196 (MRCItem +litem &184 +pos 4 +dimension 50 +uid 106,0 +) +*197 (MRCItem +litem &185 +pos 5 +dimension 50 +uid 107,0 +) +*198 (MRCItem +litem &186 +pos 6 +dimension 80 +uid 108,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 96,0 +vaOverrides [ +] +) +] +) +uid 82,0 +type 1 +) +activeModelName "BlockDiag" +) Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.info/Synthesis/Constraints/control_unit.ctr =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.info/Synthesis/Constraints/control_unit.ctr (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.info/Synthesis/Constraints/control_unit.ctr (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700a +# set_package fg484 +# set_speed -4 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.info/Synthesis/Constraints/control_unit.sdc =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.info/Synthesis/Constraints/control_unit.sdc (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.info/Synthesis/Constraints/control_unit.sdc (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700a +# set_package fg484 +# set_speed -4 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/symbol.sb =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/symbol.sb (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/symbol.sb (revision 9841) @@ -0,0 +1,2143 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"CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 529,0 +va (VaSet +) +xt "24800,30500,32000,31500" +st "drs_address_mode" +ju 2 +blo "32000,31300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 530,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10800,65000,11600" +st "drs_address_mode : OUT std_logic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_address_mode" +t "std_logic" +o 12 +suid 14,0 +) +) +) +] +shape (Rectangle +uid 301,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,13000,33000,32000" +) +oxt "15000,13000,33000,26000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "15200,26000,21400,27000" +st "FACT_FAD_lib" +blo "15200,26800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "15200,27000,20600,28000" +st "control_unit" +blo "15200,27800" +) +) +gi *94 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +*95 (Grouping +uid 16,0 +optionalChildren [ +*96 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48000,45500,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*97 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,44000,56200,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*98 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,46000,46200,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*99 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,46000,34300,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*100 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,45200,62400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*101 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,44000,61700,45000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*102 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "39700,44000,45300,46000" +st " +TU Dortmund +Physik / EE +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*103 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,47000,34300,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*104 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,48000,34900,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*105 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,47000,49300,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *106 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*107 (Text +uid 49,0 +va (VaSet +font "Arial,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*108 (MLText +uid 50,0 +va (VaSet +) +xt "0,1000,15300,6000" +st "LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; +LIBRARY FACT_FAD_LIB; +USE FACT_FAD_LIB.fad_definitions.ALL;" +tm "PackageList" +) +] +) +windowSize "256,204,1273,894" +viewArea "-30300,-21800,35934,26008" +cachedDiagramExtent "0,0,75000,49000" +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *109 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *110 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,13200,44400,14200" +st "User:" +blo "42000,14000" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,14200,44000,14200" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 530,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/symbol.sb.bak =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/symbol.sb.bak (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/control_unit/symbol.sb.bak (revision 9841) @@ -0,0 +1,1925 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +itemName "ALL" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +itemName "ALL" +) +(DmPackageRef +library "IMPORT_LIB" +unitName "fad_definitions" +itemName "ALL" +) +] +libraryRefs [ +"ieee" +"IMPORT_LIB" +] +) +version "24.1" +appVersion "2009.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 11,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 53,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +decl (Decl +n "clk" +t "STD_LOGIC" +o 1 +suid 1,0 +) +) +uid 109,0 +) +*15 (LogPort +port (LogicalPort +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(7 DOWNTO 0)" +o 2 +suid 2,0 +) +) +uid 111,0 +) +*16 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "config_data_valid" +t "std_logic" +o 7 +suid 3,0 +) +) +uid 113,0 +) +*17 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "config_busy" +t "std_logic" +o 6 +suid 4,0 +) +) +uid 115,0 +) +*18 (LogPort +port (LogicalPort +m 2 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 11 +suid 5,0 +) +) +uid 117,0 +) +*19 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "roi_array" +t "roi_array_type" +o 10 +suid 6,0 +) +) +uid 119,0 +) +*20 (LogPort +port (LogicalPort +decl (Decl +n "config_wr_en" +t "std_logic" +o 5 +suid 7,0 +) +) +uid 121,0 +) +*21 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "dac_array" +t "dac_array_type" +o 9 +suid 8,0 +) +) +uid 123,0 +) +*22 (LogPort +port (LogicalPort +decl (Decl +n "config_rd_en" +t "std_logic" +o 3 +suid 9,0 +) +) +uid 125,0 +) +*23 (LogPort +port (LogicalPort +decl (Decl +n "config_start" +t "std_logic" +o 4 +suid 10,0 +) +) +uid 127,0 +) +*24 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "config_ready" +t "std_logic" +o 8 +suid 11,0 +) +) +uid 129,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 66,0 +optionalChildren [ +*25 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *26 (MRCItem +litem &1 +pos 11 +dimension 20 +) +uid 68,0 +optionalChildren [ +*27 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 69,0 +) +*28 (MRCItem +litem &3 +pos 1 +dimension 23 +uid 70,0 +) +*29 (MRCItem +litem &4 +pos 2 +hidden 1 +dimension 20 +uid 71,0 +) +*30 (MRCItem +litem &14 +pos 0 +dimension 20 +uid 108,0 +) +*31 (MRCItem +litem &15 +pos 1 +dimension 20 +uid 110,0 +) +*32 (MRCItem +litem &16 +pos 2 +dimension 20 +uid 112,0 +) +*33 (MRCItem +litem &17 +pos 3 +dimension 20 +uid 114,0 +) +*34 (MRCItem +litem &18 +pos 4 +dimension 20 +uid 116,0 +) +*35 (MRCItem +litem &19 +pos 5 +dimension 20 +uid 118,0 +) +*36 (MRCItem +litem &20 +pos 6 +dimension 20 +uid 120,0 +) +*37 (MRCItem +litem &21 +pos 7 +dimension 20 +uid 122,0 +) +*38 (MRCItem +litem &22 +pos 8 +dimension 20 +uid 124,0 +) +*39 (MRCItem +litem &23 +pos 9 +dimension 20 +uid 126,0 +) +*40 (MRCItem +litem &24 +pos 10 +dimension 20 +uid 128,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 72,0 +optionalChildren [ +*41 (MRCItem +litem &5 +pos 0 +dimension 20 +uid 73,0 +) +*42 (MRCItem +litem &7 +pos 1 +dimension 50 +uid 74,0 +) +*43 (MRCItem +litem &8 +pos 2 +dimension 100 +uid 75,0 +) +*44 (MRCItem +litem &9 +pos 3 +dimension 50 +uid 76,0 +) +*45 (MRCItem +litem &10 +pos 4 +dimension 100 +uid 77,0 +) +*46 (MRCItem +litem &11 +pos 5 +dimension 100 +uid 78,0 +) +*47 (MRCItem +litem &12 +pos 6 +dimension 50 +uid 79,0 +) +*48 (MRCItem +litem &13 +pos 7 +dimension 80 +uid 80,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 67,0 +vaOverrides [ +] +) +] +) +uid 52,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *49 (LEmptyRow +) +uid 82,0 +optionalChildren [ +*50 (RefLabelRowHdr +) +*51 (TitleRowHdr +) +*52 (FilterRowHdr +) +*53 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*54 (RowExpandColHdr +tm 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"0,7000,0,7000" +tm "SyDeclarativeTextMgr" +) +) +lastUid 162,0 +activeModelName "Symbol:CDM" +) Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/data@r@a@m_64b_16b_width15/symbol.sb =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/data@r@a@m_64b_16b_width15/symbol.sb (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/data@r@a@m_64b_16b_width15/symbol.sb (revision 9841) @@ -0,0 +1,1760 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +itemName "ALL" +) +] +libraryRefs [ +"ieee" +"XilinxCoreLib" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 7,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 108,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 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"C:\\FPGA_projects\\FACT_FAD_21062010\\FACT_FAD_lib\\hds\\data_generator" +) +(vvPair +variable "date" +value "21.06.2010" +) +(vvPair +variable "day" +value "Mo" +) +(vvPair +variable "day_long" +value "Montag" +) +(vvPair +variable "dd" +value "21" +) +(vvPair +variable "entity_name" +value "data_generator" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "TU-CC4900F8C7D2" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_PrecisionSynthesisDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "06" +) +(vvPair +variable "module_name" +value "data_generator" +) +(vvPair +variable "month" +value "Jun" +) +(vvPair +variable "month_long" +value "Juni" +) +(vvPair +variable "p" +value "C:\\FPGA_projects\\FACT_FAD_21062010\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\FPGA_projects\\FACT_FAD_21062010\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "14:50:41" +) +(vvPair +variable "unit" +value "data_generator" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 134,0 +optionalChildren [ +*129 (SymbolBody +uid 8,0 +optionalChildren [ +*130 (CptPort +uid 48,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 49,0 +ro 90 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"Courier New,8,0" +) +xt "2000,15200,42500,16000" +st "ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH-1 downto 0)" +preAdd 0 +posAdd 0 +o 5 +suid 7,0 +) +) +) +*135 (CptPort +uid 88,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 89,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,10625,37000,11375" +) +tg (CPTG +uid 90,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 91,0 +va (VaSet +) +xt "38000,10500,43900,11500" +st "board_id : (3:0)" +blo "38000,11300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 92,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,29600,35000,30400" +st "board_id : IN std_logic_vector (3 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "board_id" +t "std_logic_vector" +b "(3 downto 0)" +preAdd 0 +posAdd 0 +o 23 +suid 9,0 +) +) +) +*136 (CptPort +uid 93,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 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16,0 +) +) +) +*141 (CptPort +uid 407,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 408,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,20625,58750,21375" +) +tg (CPTG +uid 409,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 410,0 +va (VaSet +) +xt "50700,20500,57000,21500" +st "ram_write_ready" +ju 2 +blo "57000,21300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 411,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,16800,38500,17600" +st "ram_write_ready : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "ram_write_ready" +t "std_logic" +o 7 +suid 17,0 +i "'0'" +) +) +) +*142 (CptPort +uid 412,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 413,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,15625,37000,16375" +) +tg (CPTG +uid 414,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 415,0 +va (VaSet +) +xt "38000,15500,41000,16500" +st "roi_max" +blo "38000,16300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 416,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,25600,27000,26400" +st "roi_max : IN roi_max_type ; +" +) +thePort (LogicalPort +decl (Decl +n "roi_max" +t "roi_max_type" +o 18 +suid 18,0 +) +) +) +*143 (CptPort +uid 473,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 474,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,16625,37000,17375" +) +tg (CPTG +uid 475,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 476,0 +va (VaSet +) +xt "38000,16500,41400,17500" +st "roi_array" +blo "38000,17300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 477,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,24800,28000,25600" +st "roi_array : IN roi_array_type ; +" +) +thePort (LogicalPort +decl (Decl +n "roi_array" +t "roi_array_type" +o 17 +suid 19,0 +) +) +) +*144 (CptPort +uid 526,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 527,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,17625,37000,18375" +) +tg (CPTG +uid 528,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 529,0 +va (VaSet +) +xt "38000,17500,47100,18500" +st "package_length : (15:0)" +blo "38000,18300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 530,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,28800,35500,29600" +st "package_length : IN std_logic_vector (15 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "package_length" +t "std_logic_vector" +b "(15 downto 0)" +o 22 +suid 20,0 +) +) +) +*145 (CptPort +uid 637,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 638,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,21625,58750,22375" +) +tg (CPTG +uid 639,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 640,0 +va (VaSet +) +xt "53800,21500,57000,22500" +st "adc_oeb" +ju 2 +blo "57000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 641,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,36000,38500,36800" +st "adc_oeb : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "adc_oeb" +t "std_logic" +o 31 +suid 23,0 +i "'1'" +) +) +) +*146 (CptPort +uid 642,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 643,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,19625,37000,20375" +) +tg (CPTG +uid 644,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 645,0 +va (VaSet +) +xt "38000,19500,43500,20500" +st "adc_otr : (3:0)" +blo "38000,20300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 646,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,36800,35000,37600" +st "adc_otr : IN std_logic_vector (3 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "adc_otr" +t "std_logic_vector" +b "(3 downto 0)" +o 32 +suid 24,0 +) +) +) +*147 (CptPort +uid 676,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 677,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,22625,58750,23375" +) +tg (CPTG +uid 678,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 679,0 +va (VaSet +) +xt "48500,22500,57000,23500" +st "drs_channel_id : (3:0)" +ju 2 +blo "57000,23300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 680,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,37600,44500,38400" +st "drs_channel_id : OUT std_logic_vector (3 downto 0) := (others => '0') ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_channel_id" +t "std_logic_vector" +b "(3 downto 0)" +o 33 +suid 25,0 +i "(others => '0')" +) +) +) +*148 (CptPort +uid 681,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 682,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,23625,58750,24375" +) +tg (CPTG +uid 683,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 684,0 +va (VaSet +) +xt "52600,23500,57000,24500" +st "drs_clk_en" +ju 2 +blo "57000,24300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 685,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,39200,38500,40000" +st "drs_clk_en : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_clk_en" +t "std_logic" +o 35 +suid 26,0 +i "'0'" +) +) +) +*149 (CptPort +uid 801,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 802,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,24625,58750,25375" +) +tg (CPTG +uid 803,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 804,0 +va (VaSet +) +xt "50800,24500,57000,25500" +st "drs_read_s_cell" +ju 2 +blo "57000,25300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 805,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,40000,38500,40800" +st "drs_read_s_cell : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_read_s_cell" +t "std_logic" +o 36 +suid 33,0 +i "'0'" +) +) +) +*150 (CptPort +uid 806,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 807,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,20625,37000,21375" +) +tg (CPTG +uid 808,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 809,0 +va (VaSet +) +xt "38000,20500,46800,21500" +st "drs_read_s_cell_ready" +blo "38000,21300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 810,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,40800,25500,41600" +st "drs_read_s_cell_ready : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "drs_read_s_cell_ready" +t "std_logic" +o 37 +suid 34,0 +) +) +) +*151 (CptPort +uid 811,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 812,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,21625,37000,22375" +) +tg (CPTG +uid 813,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 814,0 +va (VaSet +) +xt "38000,21500,44400,22500" +st "drs_s_cell_array" +blo "38000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 815,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,41600,30500,42400" +st "drs_s_cell_array : IN drs_s_cell_array_type +" +) +thePort (LogicalPort +decl (Decl +n "drs_s_cell_array" +t "drs_s_cell_array_type" +o 38 +suid 35,0 +) +) +) +*152 (CptPort +uid 845,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 846,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,25625,58750,26375" +) +tg (CPTG +uid 847,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 848,0 +va (VaSet +) +xt "52700,25500,57000,26500" +st "drs_dwrite" +ju 2 +blo "57000,26300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 849,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,38400,38500,39200" +st "drs_dwrite : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "drs_dwrite" +t "std_logic" +o 34 +suid 36,0 +i "'1'" +) +) +) +*153 (CptPort +uid 898,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 899,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,22625,37000,23375" +) +tg (CPTG +uid 900,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 901,0 +va (VaSet +) +xt "38000,22500,43900,23500" +st "adc_data_array" +blo "38000,23300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 902,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,35200,30500,36000" +st "adc_data_array : IN adc_data_array_type ; +" +) +thePort (LogicalPort +decl (Decl +n "adc_data_array" +t "adc_data_array_type" +o 30 +suid 37,0 +) +) +) +*154 (CptPort +uid 958,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 959,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,23625,37000,24375" +) +tg (CPTG +uid 960,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 961,0 +va (VaSet +) +xt "38000,23500,44500,24500" +st "config_ready_cm" +blo "38000,24300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 962,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,20800,25500,21600" +st "config_ready_cm : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_ready_cm" +t "std_logic" +o 12 +suid 39,0 +) +) +) +*155 (CptPort +uid 963,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 964,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,27625,58750,28375" +) +tg (CPTG +uid 965,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 966,0 +va (VaSet +) +xt "50800,27500,57000,28500" +st "config_start_cm" +ju 2 +blo "57000,28300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 967,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,18400,38500,19200" +st "config_start_cm : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_start_cm" +t "std_logic" +o 9 +suid 40,0 +i "'0'" +) +) +) +*156 (CptPort +uid 1018,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1019,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,24625,37000,25375" +) +tg (CPTG +uid 1020,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1021,0 +va (VaSet +) +xt "38000,24500,41600,25500" +st "s_trigger" +blo "38000,25300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1022,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,32800,25500,33600" +st "s_trigger : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "s_trigger" +t "std_logic" +o 27 +suid 41,0 +) +) +) +*157 (CptPort +uid 1048,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1049,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,25625,37000,26375" +) +tg (CPTG +uid 1050,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1051,0 +va (VaSet +) +xt "38000,25500,44700,26500" +st "config_ready_mm" +blo "38000,26300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1052,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,20000,25500,20800" +st "config_ready_mm : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_ready_mm" +t "std_logic" +o 11 +suid 42,0 +) +) +) +*158 (CptPort +uid 1053,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1054,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,26625,37000,27375" +) +tg (CPTG +uid 1055,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1056,0 +va (VaSet +) +xt "38000,26500,44500,27500" +st "config_ready_spi" +blo "38000,27300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1057,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,21600,25500,22400" +st "config_ready_spi : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_ready_spi" +t "std_logic" +o 13 +suid 43,0 +) +) +) +*159 (CptPort +uid 1085,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1086,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,27625,37000,28375" +) +tg (CPTG +uid 1087,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1088,0 +va (VaSet +) +xt "38000,27500,43200,28500" +st "sensor_array" +blo "38000,28300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1089,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,26400,29500,27200" +st "sensor_array : IN sensor_array_type ; +" +) +thePort (LogicalPort +decl (Decl +n "sensor_array" +t "sensor_array_type" +o 19 +suid 44,0 +) +) +) +*160 (CptPort +uid 1090,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1091,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,28625,37000,29375" +) +tg (CPTG +uid 1092,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1093,0 +va (VaSet +) +xt "38000,28500,43300,29500" +st "sensor_ready" +blo "38000,29300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1094,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,27200,25500,28000" +st "sensor_ready : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "sensor_ready" +t "std_logic" +o 20 +suid 45,0 +) +) +) +*161 (CptPort +uid 1122,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1123,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,28625,58750,29375" +) +tg (CPTG +uid 1124,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1125,0 +va (VaSet +) +xt "50600,28500,57000,29500" +st "config_start_mm" +ju 2 +blo "57000,29300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1126,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,17600,38500,18400" +st "config_start_mm : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_start_mm" +t "std_logic" +o 8 +suid 46,0 +i "'0'" +) +) +) +*162 (CptPort +uid 1127,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1128,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,29625,58750,30375" +) +tg (CPTG +uid 1129,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1130,0 +va (VaSet +) +xt "50800,29500,57000,30500" +st "config_start_spi" +ju 2 +blo "57000,30300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1131,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,19200,38500,20000" +st "config_start_spi : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_start_spi" +t "std_logic" +o 10 +suid 47,0 +i "'0'" +) +) +) +*163 (CptPort +uid 1159,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1160,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,30625,58750,31375" +) +tg (CPTG +uid 1161,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1162,0 +va (VaSet +) +xt "51400,30500,57000,31500" +st "config_started" +ju 2 +blo "57000,31300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1163,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,34400,38500,35200" +st "config_started : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_started" +t "std_logic" +o 29 +suid 48,0 +i "'0'" +) +) +) +*164 (CptPort +uid 1164,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1165,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,29625,37000,30375" +) +tg (CPTG +uid 1166,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1167,0 +va (VaSet +) +xt "38000,29500,42600,30500" +st "new_config" +blo "38000,30300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1168,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,33600,25500,34400" +st "new_config : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "new_config" +t "std_logic" +o 28 +suid 49,0 +) +) +) +*165 (CptPort +uid 1196,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1197,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,30625,37000,31375" +) +tg (CPTG +uid 1198,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1199,0 +va (VaSet +) +xt "38000,30500,45000,31500" +st "config_started_cm" +blo "38000,31300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1200,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,23200,25500,24000" +st "config_started_cm : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_started_cm" +t "std_logic" +o 15 +suid 50,0 +) +) +) +*166 (CptPort +uid 1201,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1202,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,31625,37000,32375" +) +tg (CPTG +uid 1203,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1204,0 +va (VaSet +) +xt "38000,31500,45200,32500" +st "config_started_mm" +blo "38000,32300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1205,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22400,25500,23200" +st "config_started_mm : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_started_mm" +t "std_logic" +o 14 +suid 51,0 +) +) +) +*167 (CptPort +uid 1206,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1207,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,32625,37000,33375" +) +tg (CPTG +uid 1208,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1209,0 +va (VaSet +) +xt "38000,32500,45000,33500" +st "config_started_spi" +blo "38000,33300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1210,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,24000,25500,24800" +st "config_started_spi : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_started_spi" +t "std_logic" +o 16 +suid 52,0 +) +) +) +*168 (CptPort +uid 1240,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1241,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,33625,37000,34375" +) +tg (CPTG +uid 1242,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1243,0 +va (VaSet +) +xt "38000,33500,41700,34500" +st "dac_array" +blo "38000,34300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1244,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,28000,28000,28800" +st "dac_array : IN dac_array_type ; +" +) +thePort (LogicalPort +decl (Decl +n "dac_array" +t "dac_array_type" +o 21 +suid 53,0 +) +) +) +] +shape (Rectangle +uid 238,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "37000,1000,58000,35000" +) +oxt "37000,1000,51000,21000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "38300,21000,44500,22000" +st "FACT_FAD_lib" +blo "38300,21800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "38300,22000,44700,23000" +st "data_generator" +blo "38300,22800" +) +) +gi *169 (GenericInterface +uid 13,0 +ps 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"C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\debouncer\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\debouncer\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "10:22:23" +) +(vvPair +variable "unit" +value "debouncer" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 80,0 +optionalChildren [ +*59 (SymbolBody +uid 8,0 +optionalChildren [ +*60 (CptPort +uid 48,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 49,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,13625,25000,14375" +) +tg (CPTG +uid 50,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 51,0 +va (VaSet +) +xt "26000,13500,27300,14500" +st "clk" +blo "26000,14300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 52,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,8000,20000,8800" +st "clk : IN STD_LOGIC ; +" +) +thePort (LogicalPort +decl (Decl +n "clk" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*61 (CptPort +uid 53,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 54,0 +ro 90 +va (VaSet +vasetType 1 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9841) @@ -0,0 +1,2564 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "IEEE" +unitName "STD_LOGIC_ARITH" +) +(DmPackageRef +library "ieee" +unitName "STD_LOGIC_UNSIGNED" +) +(DmPackageRef +library "FACT_FAD_lib" +unitName "fad_definitions" +) +] +libraryRefs [ +"ieee" +"FACT_FAD_lib" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 22,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 60,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) 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"SourceDir" +value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager" +) +(vvPair +variable "d_logical" +value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager" +) +(vvPair +variable "date" +value "02.07.2010" +) +(vvPair +variable "day" +value "Fr" +) +(vvPair +variable "day_long" +value "Freitag" +) +(vvPair +variable "dd" +value "02" +) +(vvPair +variable "entity_name" +value "memory_manager" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "TU-CC4900F8C7D2" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_PrecisionSynthesisDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "07" +) +(vvPair +variable "module_name" +value "memory_manager" +) +(vvPair +variable "month" +value "Jul" +) +(vvPair +variable "month_long" +value "Juli" +) +(vvPair +variable "p" +value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "10:38:11" +) +(vvPair +variable "unit" +value "memory_manager" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 58,0 +optionalChildren [ +*91 (SymbolBody +uid 8,0 +optionalChildren [ +*92 (CptPort +uid 51,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 52,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,7625,15000,8375" +) +tg (CPTG +uid 53,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 54,0 +va (VaSet +font "arial,8,0" +) +xt "16000,7500,21900,8500" +st "ram_start_addr" +blo "16000,8300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 55,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,15600,95500,16400" +st "ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH_64B-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 18 +suid 1,0 +i "(others => '0')" +) +) +) +*93 (CptPort +uid 138,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 139,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,8625,15000,9375" +) +tg (CPTG +uid 140,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 141,0 +va (VaSet +font "arial,8,0" +) +xt "16000,8500,17300,9500" +st "clk" +blo "16000,9300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 142,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2000,68000,2800" +st "clk : IN std_logic ; +" +) +thePort (LogicalPort +lang 2 +decl (Decl +n "clk" +t "std_logic" +o 1 +suid 2,0 +) +) +) +*94 (CommentText +uid 168,0 +ps "EdgeToEdgeStrategy" +shape (Rectangle +uid 169,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "42000,5600,57000,10600" +) +oxt "0,0,15000,5000" +text (MLText +uid 170,0 +va (VaSet +fg "0,0,32768" +font "arial,8,0" +) +xt "42200,5800,54900,9800" +st " +-- library UNISIM; +-- use UNISIM.VComponents.all; +-- USE IEEE.NUMERIC_STD.all; + +-- RAM_ADDR_WIDTH_64B is used for +-- output ram_start_addr + +-- RAM_ADDR_WIDTH_16B is used for +-- output wiz_ram_start_addr +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +included 1 +excludeCommentLeader 1 +) +*95 (CptPort +uid 194,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 195,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,9625,15000,10375" +) +tg (CPTG +uid 196,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 197,0 +va (VaSet +font "arial,8,0" +) +xt "16000,9500,20800,10500" +st "config_start" +blo "16000,10300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 198,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2800,68000,3600" +st "config_start : IN std_logic ; +" +) +thePort (LogicalPort +lang 2 +decl (Decl +n "config_start" +t "std_logic" +o 2 +suid 3,0 +) +) +) +*96 (CptPort +uid 224,0 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"CptPortNameMgr" +) +) +dt (MLText +uid 258,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6000,90500,6800" +st "config_ready : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "config_ready" +t "std_logic" +o 6 +suid 5,0 +i "'0'" +) +) +) +*98 (CptPort +uid 284,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 409,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,10625,15000,11375" +) +tg (CPTG +uid 286,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 287,0 +va (VaSet +font "arial,8,0" +) +xt "16000,10500,25600,11500" +st "wiz_number_of_channels" +blo "16000,11300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 288,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10800,96500,11600" +st "wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0') ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_number_of_channels" +t "std_logic_vector" +b "(3 downto 0)" +o 12 +suid 6,0 +i "(others => '0')" +) +) +) +*99 (CptPort +uid 289,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 290,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,8625,43750,9375" +) +tg (CPTG +uid 291,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 292,0 +va (VaSet +font "arial,8,0" +) +xt "34600,8500,42000,9500" +st "wiz_ram_start_addr" +ju 2 +blo "42000,9300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 293,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,9200,96500,10000" +st "wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0') ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH_16B-1 downto 0)" +preAdd 0 +o 10 +suid 7,0 +i "(others => '0')" +) +) +) +*100 (CptPort +uid 294,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 295,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,9625,43750,10375" +) +tg (CPTG +uid 296,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 297,0 +va (VaSet +font "arial,8,0" +) +xt "36900,9500,42000,10500" +st "wiz_write_ea" +ju 2 +blo "42000,10300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 298,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,11600,90500,12400" +st "wiz_write_ea : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_ea" +t "std_logic" +o 13 +suid 8,0 +i "'0'" +) +) +) +*101 (CptPort +uid 299,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 300,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,10625,43750,11375" +) +tg (CPTG +uid 301,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 302,0 +va (VaSet +font "arial,8,0" +) +xt "36500,10500,42000,11500" +st "wiz_write_end" +ju 2 +blo "42000,11300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 303,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,13200,90500,14000" +st "wiz_write_end : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_end" +t "std_logic" +o 15 +suid 9,0 +i "'0'" +) +) +) +*102 (CptPort +uid 304,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 305,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,11625,43750,12375" +) +tg (CPTG +uid 306,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 307,0 +va (VaSet +font "arial,8,0" +) +xt "35400,11500,42000,12500" +st "wiz_write_header" +ju 2 +blo "42000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 308,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,12400,90500,13200" +st "wiz_write_header : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "wiz_write_header" +t "std_logic" +o 14 +suid 10,0 +i "'0'" +) +) +) +*103 (CptPort +uid 309,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 310,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,12625,43750,13375" +) +tg (CPTG +uid 311,0 +ps "CptPortTextPlaceStrategy" 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"44000,3600,68000,4400" +st "ram_write_ready : IN std_logic ; +" +) +thePort (LogicalPort +lang 2 +decl (Decl +n "ram_write_ready" +t "std_logic" +o 3 +suid 12,0 +) +) +) +*105 (CptPort +uid 379,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 380,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,12625,15000,13375" +) +tg (CPTG +uid 381,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 382,0 +va (VaSet +font "arial,8,0" +) +xt "16000,12500,19400,13500" +st "wiz_busy" +blo "16000,13300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 383,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,14000,68000,14800" +st "wiz_busy : IN std_logic ; +" +) +thePort (LogicalPort +lang 2 +decl (Decl +n "wiz_busy" +t "std_logic" +o 16 +suid 13,0 +) +) +) +*106 (CptPort +uid 433,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 434,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,13625,43750,14375" +) +tg (CPTG +uid 435,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 436,0 +va (VaSet +font "arial,8,0" +) +xt "39000,13500,42000,14500" +st "roi_max" +ju 2 +blo "42000,14300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 437,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,7600,109500,8400" +st "roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)) ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "roi_max" +t "roi_max_type" +posAdd 0 +o 8 +suid 14,0 +i "(others => conv_std_logic_vector (0, 11))" +) +) +) +*107 (CptPort +uid 569,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 570,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,13625,15000,14375" +) +tg (CPTG +uid 571,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 572,0 +va (VaSet +font "arial,8,0" +) +xt "16000,13500,19400,14500" +st "roi_array" +blo "16000,14300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 573,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,4400,70500,5200" +st "roi_array : IN roi_array_type ; +" +) +thePort (LogicalPort +lang 2 +decl (Decl +n "roi_array" +t "roi_array_type" +o 4 +suid 17,0 +) +) +) +*108 (CptPort +uid 622,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 623,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,14625,43750,15375" +) +tg (CPTG +uid 624,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 625,0 +va (VaSet +font "arial,8,0" +) +xt "35900,14500,42000,15500" +st "package_length" +ju 2 +blo "42000,15300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 626,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,8400,96500,9200" +st "package_length : OUT std_logic_vector (15 downto 0) := (others => '0') ; +" +) +thePort (LogicalPort +lang 2 +m 1 +decl (Decl +n "package_length" +t "std_logic_vector" +b "(15 downto 0)" +o 9 +suid 18,0 +i "(others => '0')" +) +) +) +*109 (CptPort +uid 804,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 805,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt 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+st "wiz_ack : IN std_logic ; +" +) +thePort (LogicalPort +lang 2 +decl (Decl +n "wiz_ack" +t "std_logic" +o 17 +suid 22,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,43000,17000" +) +oxt "15000,6000,23000,16000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "arial,8,1" +) +xt "15350,10000,21550,11000" +st "FACT_FAD_lib" +blo "15350,10800" +) +second (Text +uid 12,0 +va (VaSet +font "arial,8,1" +) +xt "15350,11000,22650,12000" +st "memory_manager" +blo "15350,11800" +) +) +gi *111 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "-5000,7000,12000,10200" +st "Generic Declarations + +RAM_ADDR_WIDTH_64B integer 12 +RAM_ADDR_WIDTH_16B integer 14 +" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) 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"Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "FACT_FAD_lib" +entityName "FAD_main" +viewName "struct.bd" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *126 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "arial,8,0" +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "arial,8,0" +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *127 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "arial,8,1" +) +xt "42000,16400,44400,17400" +st "User:" +blo "42000,17200" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,17400,44000,17400" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 925,0 +activeModelName "Symbol:CDM" +) Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd (revision 9841) @@ -0,0 +1,5360 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "ieee" +unitName "std_logic_unsigned" +) +(DmPackageRef +library "FACT_FAD_lib" +unitName "fad_definitions" +) +(DmPackageRef +library "IEEE" +unitName "NUMERIC_STD" +itemName "ALL" +) +] +instances [ +(Instance +name "I_spi_distributor" +duLibraryName "FACT_FAD_lib" +duName "spi_distributor" +elements [ +(GiElement +name "TEMP_MEASUREMENT_BEAT" +type "integer" +value "5*10**6" +) +] +mwi 0 +uid 2195,0 +) +(Instance +name "I_spi_controller" +duLibraryName "FACT_FAD_lib" +duName "spi_controller" +elements [ +] +mwi 0 +uid 2249,0 +) +(Instance +name "I_spi_clkgen" +duLibraryName "FACT_FAD_lib" +duName "spi_clock_generator" +elements [ +(GiElement +name "CLK_DIVIDER" +type "integer" +value "25" +e "--2 MHz @ 50 MHz" +) +] +mwi 0 +uid 2267,0 +) +] +libraryRefs [ +"ieee" +"FACT_FAD_lib" +] +) +version "29.1" +appVersion "2009.2 (Build 10)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\spi_interface\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\spi_interface\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\spi_interface" +) +(vvPair +variable "d_logical" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\spi_interface" +) +(vvPair +variable "date" +value "16.06.2010" +) +(vvPair +variable "day" +value "Mi" +) +(vvPair +variable "day_long" +value "Mittwoch" +) +(vvPair +variable "dd" +value "16" +) +(vvPair +variable "entity_name" +value "spi_interface" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "TU-CC4900F8C7D2" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "06" +) +(vvPair +variable "module_name" +value "spi_interface" +) +(vvPair +variable "month" +value "Jun" +) +(vvPair +variable "month_long" +value "Juni" +) +(vvPair +variable "p" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\spi_interface\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\spi_interface\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "14:19:06" +) +(vvPair +variable "unit" +value "spi_interface" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 52,0 +optionalChildren [ +*1 (Grouping +uid 9,0 +optionalChildren [ +*2 (CommentText +uid 11,0 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/firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd.bak (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd.bak (revision 9841) @@ -0,0 +1,5853 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "ieee" +unitName "std_logic_unsigned" +) +(DmPackageRef +library "FACT_FAD_lib" +unitName "fad_definitions" +) +(DmPackageRef +library "IEEE" +unitName "NUMERIC_STD" +itemName "ALL" +) +] +instances [ +(Instance +name "I_spi_distributor" +duLibraryName "FACT_FAD_lib" +duName "spi_distributor" +elements [ +(GiElement +name "CLK_DIVIDER" +type "integer" +value "4*10**3" +) +] +mwi 0 +uid 2195,0 +) +(Instance +name "I_spi_controller" +duLibraryName "FACT_FAD_lib" +duName "spi_controller" +elements [ +] +mwi 0 +uid 2249,0 +) +(Instance +name "I_spi_clkgen" +duLibraryName "FACT_FAD_lib" +duName "spi_clock_generator" +elements [ +(GiElement +name "CLK_DIVIDER" +type "integer" +value "25" +e "--2 MHz @ 50 MHz" +) +] +mwi 0 +uid 2267,0 +) +(Instance +name "I0" +duLibraryName "FACT_FAD_test_devices_lib" +duName "debouncer" +elements [ +(GiElement +name "WIDTH" +type "INTEGER" +value "17" +) +] +mwi 0 +uid 2421,0 +) +] +libraryRefs [ +"ieee" +"FACT_FAD_lib" +] +) +version "29.1" +appVersion "2009.1 (Build 12)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\spi_interface\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\spi_interface\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\spi_interface" +) +(vvPair +variable "d_logical" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\spi_interface" +) +(vvPair +variable "date" +value "26.05.2010" +) +(vvPair +variable "day" +value "Mi" +) +(vvPair +variable "day_long" +value "Mittwoch" +) +(vvPair +variable "dd" +value "26" +) +(vvPair +variable "entity_name" +value "spi_interface" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "IHP110" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "05" +) +(vvPair +variable "module_name" +value "spi_interface" +) +(vvPair +variable "month" +value "Mai" +) +(vvPair +variable "month_long" +value "Mai" +) +(vvPair +variable "p" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\spi_interface\\struct.bd" +) +(vvPair +variable "p_logical" +value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\spi_interface\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "D:\\modeltech_6.5e\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "15:45:10" +) +(vvPair +variable "unit" +value "spi_interface" +) +(vvPair +variable "user" +value "daqct3" +) +(vvPair +variable "version" +value "2009.1 (Build 12)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 52,0 +optionalChildren [ +*1 (Grouping +uid 9,0 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2353,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2354,0 +va (VaSet +) +xt "50000,22500,52000,23500" +st "mosi" +ju 2 +blo "52000,23300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "mosi" +t "std_logic" +o 3 +i "'0'" +) +) +) +*68 (CptPort +uid 2398,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 2399,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "53000,21625,53750,22375" +) +tg (CPTG +uid 2400,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2401,0 +va (VaSet +) +xt "50000,21500,52000,22500" +st "miso" +ju 2 +blo "52000,22300" +) +) +thePort (LogicalPort +m 2 +decl (Decl +n "miso" +t "std_logic" +o 2 +i "'Z'" +) +) +) +] +shape (Rectangle +uid 2250,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "37000,21000,53000,33000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 2251,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*69 (Text +uid 2252,0 +va (VaSet +font "Arial,8,1" +) +xt "36900,34000,43100,35000" +st "FACT_FAD_lib" +blo "36900,34800" +tm "BdLibraryNameMgr" +) +*70 (Text +uid 2253,0 +va (VaSet +font "Arial,8,1" +) +xt "36900,35000,42800,36000" +st "spi_controller" +blo "36900,35800" +tm "CptNameMgr" +) +*71 (Text +uid 2254,0 +va (VaSet +font "Arial,8,1" +) +xt "36900,36000,43400,37000" +st "I_spi_controller" +blo "36900,36800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 2255,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 2256,0 +text (MLText +uid 2257,0 +va (VaSet +font "Courier New,8,0" +) +xt "45000,21000,45000,21000" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 2258,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "37250,31250,38750,32750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*72 (SaComponent +uid 2267,0 +optionalChildren [ +*73 (CptPort +uid 2259,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2260,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "12250,39625,13000,40375" +) +tg (CPTG +uid 2261,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2262,0 +va (VaSet +) +xt "14000,39500,15300,40500" +st "clk" +blo "14000,40300" +) +) +thePort (LogicalPort +decl (Decl +n "clk" +t "std_logic" +o 1 +) +) +) +*74 (CptPort +uid 2263,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2264,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "21000,39625,21750,40375" +) +tg (CPTG +uid 2265,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2266,0 +va (VaSet +) +xt "18300,39500,20000,40500" +st "sclk" +ju 2 +blo "20000,40300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sclk" +t "std_logic" +o 2 +i "'0'" +) +) +) +] +shape (Rectangle +uid 2268,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "13000,39000,21000,42000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 2269,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*75 (Text +uid 2270,0 +va (VaSet +font "Arial,8,1" +) +xt "12900,42000,19100,43000" +st "FACT_FAD_lib" +blo "12900,42800" +tm "BdLibraryNameMgr" +) +*76 (Text +uid 2271,0 +va (VaSet +font "Arial,8,1" +) +xt "12900,43000,21100,44000" +st "spi_clock_generator" +blo "12900,43800" +tm "CptNameMgr" +) +*77 (Text +uid 2272,0 +va (VaSet +font "Arial,8,1" +) +xt "12900,44000,18200,45000" +st "I_spi_clkgen" +blo "12900,44800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 2273,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 2274,0 +text (MLText +uid 2275,0 +va (VaSet +font "Courier New,8,0" +) +xt "13000,38200,39500,39000" +st "CLK_DIVIDER = 25 ( integer ) --2 MHz @ 50 MHz " +) +header "" +) +elements [ +(GiElement +name "CLK_DIVIDER" +type "integer" +value "25" +e "--2 MHz @ 50 MHz" +) +] +) +viewicon (ZoomableIcon +uid 2276,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "13250,40250,14750,41750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*78 (Net +uid 2308,0 +decl (Decl +n "config_started" +t "std_logic" +o 18 +suid 45,0 +i "'0'" +) +declText (MLText +uid 2309,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,5200,41000,6000" +st "config_started : std_logic := '0' +" +) +) +*79 (PortIoOut +uid 2316,0 +shape (CompositeShape +uid 2317,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2318,0 +sl 0 +ro 90 +xt "2000,24625,3500,25375" +) +(Line +uid 2319,0 +sl 0 +ro 90 +xt "3500,25000,4000,25000" +pts [ +"4000,25000" +"3500,25000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2320,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2321,0 +va (VaSet +) +xt "-4600,24500,1000,25500" +st "config_started" +ju 2 +blo "1000,25300" +tm "WireNameMgr" +) +) +) +*80 (Net +uid 2355,0 +decl (Decl +n "mosi" +t "std_logic" +o 19 +suid 46,0 +i "'0'" +) +declText (MLText +uid 2356,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,6800,41000,7600" +st "mosi : std_logic := '0' +" +) +) +*81 (PortIoOut +uid 2363,0 +shape (CompositeShape +uid 2364,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 2365,0 +sl 0 +ro 270 +xt "55500,22625,57000,23375" +) +(Line +uid 2366,0 +sl 0 +ro 270 +xt "55000,23000,55500,23000" +pts [ +"55000,23000" +"55500,23000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 2367,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2368,0 +va (VaSet +) +xt "58000,22500,60000,23500" +st "mosi" +blo "58000,23300" +tm "WireNameMgr" +) +) +) +*82 (Net +uid 2402,0 +decl (Decl +n "miso" +t "std_logic" +preAdd 0 +posAdd 0 +o 10 +suid 47,0 +) +declText (MLText +uid 2403,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,10800,37500,11600" +st "miso : std_logic +" +) +) +*83 (SaComponent +uid 2421,0 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(Triangle +uid 2415,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "13000,14625,13750,15375" +) +tg (CPTG +uid 2416,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2417,0 +va (VaSet +) +xt "7400,14500,12000,15500" +st "trigger_out" +ju 2 +blo "12000,15300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "trigger_out" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +i "'0'" +) +) +) +*87 (CommentText +uid 2418,0 +ps "EdgeToEdgeStrategy" +shape (Rectangle +uid 2419,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "500,3000,15500,7000" +) +oxt "24500,3000,39500,7000" +text (MLText +uid 2420,0 +va (VaSet +fg "0,0,32768" +) +xt "700,3200,13600,7200" +st " +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 15000 +) +included 1 +) +] +shape (Rectangle +uid 2422,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "1000,13000,13000,18000" +) +oxt "25000,13000,37000,18000" +ttg (MlTextGroup +uid 2423,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*88 (Text +uid 2424,0 +va (VaSet +font "Arial,8,1" +) +xt "1200,18000,12800,19000" +st "FACT_FAD_test_devices_lib" +blo "1200,18800" +tm "BdLibraryNameMgr" +) +*89 (Text +uid 2425,0 +va (VaSet +font "Arial,8,1" +) +xt "1200,19000,5600,20000" +st "debouncer" +blo "1200,19800" +tm "CptNameMgr" +) +*90 (Text +uid 2426,0 +va (VaSet +font "Arial,8,1" +) +xt "1200,20000,2200,21000" +st "I0" +blo "1200,20800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 2427,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 2428,0 +text (MLText +uid 2429,0 +va (VaSet +font "Courier New,8,0" +) +xt "500,6200,15500,7000" +st "WIDTH = 17 ( INTEGER ) +" +) +header "" +) +elements [ +(GiElement +name "WIDTH" +type "INTEGER" +value "17" +) +] +) +viewicon (ZoomableIcon +uid 2430,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "1250,16250,2750,17750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*91 (Net +uid 2431,0 +decl (Decl +n "trigger_out" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 20 +suid 48,0 +i "'0'" +) +declText (MLText +uid 2432,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,20600,45000,21400" +st "SIGNAL trigger_out : STD_LOGIC := '0' +" +) +) +*92 (Net +uid 2439,0 +decl (Decl +n "clk" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 21 +suid 49,0 +) +declText (MLText +uid 2440,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,12600,41000,13400" +st "SIGNAL clk : STD_LOGIC +" +) +) +*93 (Net +uid 2447,0 +decl (Decl +n "trigger_in" +t "STD_LOGIC" +prec "-- rst : in STD_LOGIC;" +preAdd 0 +posAdd 0 +o 22 +suid 50,0 +) +declText (MLText +uid 2448,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,19000,41000,20600" +st "-- rst : in STD_LOGIC; +SIGNAL trigger_in : STD_LOGIC +" +) +) +*94 (Wire +uid 214,0 +shape (OrthoPolyLine +uid 215,0 +va (VaSet +vasetType 3 +) +xt "21750,40000,56000,40000" +pts [ +"21750,40000" +"56000,40000" +] +) +start &74 +end &21 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 218,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 219,0 +va (VaSet +) +xt "38000,39000,39700,40000" +st "sclk" +blo "38000,39800" +tm "WireNameMgr" +) +) +on &12 +) +*95 (Wire +uid 222,0 +shape (OrthoPolyLine +uid 223,0 +va (VaSet +vasetType 3 +) +xt "10000,40000,12250,40000" +pts [ +"12250,40000" +"10000,40000" +] +) +start &73 +end &14 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 226,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 227,0 +va (VaSet +isHidden 1 +) +xt "12000,39000,16200,40000" +st "clk_50MHz" +blo "12000,39800" +tm "WireNameMgr" +) +) +on &13 +) +*96 (Wire +uid 244,0 +shape (OrthoPolyLine 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+lineWidth 2 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (MLText +va (VaSet +) +xt "0,-1100,12600,-100" +st "g0: FOR i IN 0 TO n GENERATE" +tm "FrameTitleTextMgr" +) +) +seqNum (FrameSequenceNumber +ps "TopLeftStrategy" +shape (Rectangle +va (VaSet +vasetType 1 +fg "65535,65535,65535" +) +xt "50,50,1250,1450" +) +num (Text +va (VaSet +) +xt "250,250,1050,1250" +st "1" +blo "250,1050" +tm "FrameSeqNumMgr" +) +) +decls (MlTextGroup +ps "BottomRightOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*145 (Text +va (VaSet +font "Arial,8,1" +) +xt "14100,20000,22000,21000" +st "Frame Declarations" +blo "14100,20800" +) +*146 (MLText +va (VaSet +) +xt "14100,21000,14100,21000" +tm "BdFrameDeclTextMgr" +) +] +) +) +defaultBlockFrame (Frame +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "26368,26368,26368" +lineStyle 1 +lineWidth 2 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (MLText +va (VaSet +) +xt "0,-1100,7400,-100" +st "b0: BLOCK (guard)" +tm "FrameTitleTextMgr" +) +) +seqNum (FrameSequenceNumber +ps "TopLeftStrategy" +shape (Rectangle +va (VaSet +vasetType 1 +fg "65535,65535,65535" +) +xt "50,50,1250,1450" +) +num (Text +va (VaSet +) +xt "250,250,1050,1250" +st "1" +blo "250,1050" +tm "FrameSeqNumMgr" +) +) +decls (MlTextGroup +ps "BottomRightOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*147 (Text +va (VaSet +font "Arial,8,1" +) +xt "14100,20000,22000,21000" +st "Frame Declarations" +blo "14100,20800" +) +*148 (MLText +va (VaSet +) +xt "14100,21000,14100,21000" +tm "BdFrameDeclTextMgr" +) +] +) +style 3 +) +defaultSaCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1800,1750" +st "Port" +blo "0,1550" +) +) +thePort (LogicalPort +decl (Decl +n "Port" +t "" +o 0 +) +) +) +defaultSaCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1800,1750" +st "Port" +blo "0,1550" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Port" +t "" +o 0 +) +) +) +defaultDeclText (MLText +va (VaSet +font "Courier New,8,0" +) +) +archDeclarativeBlock (BdArchDeclBlock +uid 1,0 +stg "BdArchDeclBlockLS" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "20000,0,25400,1000" +st "Declarations" +blo "20000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "20000,1000,22700,2000" +st "Ports:" +blo "20000,1800" +) +preUserLabel (Text +uid 4,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "20000,0,23800,1000" +st "Pre User:" +blo "20000,800" +) +preUserText (MLText +uid 5,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "20000,0,20000,0" +tm "BdDeclarativeTextMgr" +) +diagSignalLabel (Text +uid 6,0 +va (VaSet +font "Arial,8,1" +) +xt "20000,11600,27100,12600" +st "Diagram Signals:" +blo "20000,12400" +) +postUserLabel (Text +uid 7,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "20000,0,24700,1000" +st "Post User:" +blo "20000,800" +) +postUserText (MLText +uid 8,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "20000,0,20000,0" +tm "BdDeclarativeTextMgr" +) +showAttributes 1 +) +commonDM (CommonDM +ldm (LogicalDM +suid 50,0 +usingSuid 1 +emptyRow *149 (LEmptyRow +) +uid 54,0 +optionalChildren [ +*150 (RefLabelRowHdr +) +*151 (TitleRowHdr +) +*152 (FilterRowHdr +) +*153 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*154 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*155 (GroupColHdr +tm "GroupColHdrMgr" +) +*156 (NameColHdr +tm "BlockDiagramNameColHdrMgr" +) +*157 (ModeColHdr +tm "BlockDiagramModeColHdrMgr" +) +*158 (TypeColHdr +tm "BlockDiagramTypeColHdrMgr" +) +*159 (BoundsColHdr +tm "BlockDiagramBoundsColHdrMgr" +) +*160 (InitColHdr +tm "BlockDiagramInitColHdrMgr" +) +*161 (EolColHdr +tm "BlockDiagramEolColHdrMgr" +) +*162 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "sclk" +t "std_logic" +o 6 +suid 1,0 +) +) +uid 390,0 +) +*163 (LeafLogPort +port (LogicalPort +decl (Decl +n "clk_50MHz" +t "std_logic" +preAdd 0 +posAdd 0 +o 1 +suid 2,0 +) +) +uid 392,0 +) +*164 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "dac_cs" +t "std_logic" +o 5 +suid 5,0 +) +) +uid 398,0 +) +*165 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "sensor_cs" +t "std_logic_vector" +b "(3 DOWNTO 0)" +o 8 +suid 6,0 +) +) +uid 400,0 +) +*166 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "data" +t "std_logic_vector" +b "(15 downto 0)" +o 14 +suid 14,0 +) +) +uid 497,0 +) +*167 (LeafLogPort +port (LogicalPort +decl (Decl +n "dac_array" +t "dac_array_type" +o 3 +suid 17,0 +) +) +uid 499,0 +) +*168 (LeafLogPort +port (LogicalPort +decl (Decl +n "config_start" +t "std_logic" +o 2 +suid 27,0 +) +) +uid 1255,0 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(MRCItem +litem &166 +pos 9 +dimension 20 +uid 498,0 +) +*194 (MRCItem +litem &167 +pos 4 +dimension 20 +uid 500,0 +) +*195 (MRCItem +litem &168 +pos 5 +dimension 20 +uid 1256,0 +) +*196 (MRCItem +litem &169 +pos 6 +dimension 20 +uid 1258,0 +) +*197 (MRCItem +litem &170 +pos 10 +dimension 20 +uid 1260,0 +) +*198 (MRCItem +litem &171 +pos 11 +dimension 20 +uid 1262,0 +) +*199 (MRCItem +litem &172 +pos 12 +dimension 20 +uid 1359,0 +) +*200 (MRCItem +litem &173 +pos 13 +dimension 20 +uid 1361,0 +) +*201 (MRCItem +litem &174 +pos 14 +dimension 20 +uid 1363,0 +) +*202 (MRCItem +litem &175 +pos 15 +dimension 20 +uid 1365,0 +) +*203 (MRCItem +litem &176 +pos 7 +dimension 20 +uid 1609,0 +) +*204 (MRCItem +litem &177 +pos 8 +dimension 20 +uid 1611,0 +) +*205 (MRCItem +litem &178 +pos 16 +dimension 20 +uid 2323,0 +) +*206 (MRCItem +litem &179 +pos 17 +dimension 20 +uid 2370,0 +) +*207 (MRCItem +litem &180 +pos 18 +dimension 20 +uid 2405,0 +) +*208 (MRCItem +litem &181 +pos 19 +dimension 20 +uid 2456,0 +) +*209 (MRCItem +litem &182 +pos 20 +dimension 20 +uid 2458,0 +) +*210 (MRCItem +litem &183 +pos 21 +dimension 20 +uid 2460,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 73,0 +optionalChildren [ +*211 (MRCItem +litem &153 +pos 0 +dimension 20 +uid 74,0 +) +*212 (MRCItem +litem &155 +pos 1 +dimension 50 +uid 75,0 +) +*213 (MRCItem +litem &156 +pos 2 +dimension 100 +uid 76,0 +) +*214 (MRCItem +litem &157 +pos 3 +dimension 50 +uid 77,0 +) +*215 (MRCItem +litem &158 +pos 4 +dimension 100 +uid 78,0 +) +*216 (MRCItem +litem &159 +pos 5 +dimension 100 +uid 79,0 +) +*217 (MRCItem +litem &160 +pos 6 +dimension 50 +uid 80,0 +) +*218 (MRCItem +litem &161 +pos 7 +dimension 80 +uid 81,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 68,0 +vaOverrides [ +] +) +] +) +uid 53,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *219 (LEmptyRow +) +uid 83,0 +optionalChildren [ +*220 (RefLabelRowHdr +) +*221 (TitleRowHdr +) +*222 (FilterRowHdr +) +*223 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*224 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*225 (GroupColHdr +tm "GroupColHdrMgr" +) +*226 (NameColHdr +tm "GenericNameColHdrMgr" +) +*227 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*228 (InitColHdr +tm "GenericValueColHdrMgr" +) +*229 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*230 (EolColHdr +tm "GenericEolColHdrMgr" +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 95,0 +optionalChildren [ +*231 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *232 (MRCItem +litem &219 +pos 0 +dimension 20 +) +uid 97,0 +optionalChildren [ +*233 (MRCItem +litem &220 +pos 0 +dimension 20 +uid 98,0 +) +*234 (MRCItem +litem &221 +pos 1 +dimension 23 +uid 99,0 +) +*235 (MRCItem +litem &222 +pos 2 +hidden 1 +dimension 20 +uid 100,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 101,0 +optionalChildren [ +*236 (MRCItem +litem &223 +pos 0 +dimension 20 +uid 102,0 +) +*237 (MRCItem +litem &225 +pos 1 +dimension 50 +uid 103,0 +) +*238 (MRCItem +litem &226 +pos 2 +dimension 100 +uid 104,0 +) +*239 (MRCItem +litem &227 +pos 3 +dimension 100 +uid 105,0 +) +*240 (MRCItem +litem &228 +pos 4 +dimension 50 +uid 106,0 +) +*241 (MRCItem +litem &229 +pos 5 +dimension 50 +uid 107,0 +) +*242 (MRCItem +litem &230 +pos 6 +dimension 80 +uid 108,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 96,0 +vaOverrides [ +] +) +] +) +uid 82,0 +type 1 +) +activeModelName "BlockDiag" +) Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd.info/Synthesis/Constraints/spi_unit.ctr =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd.info/Synthesis/Constraints/spi_unit.ctr (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd.info/Synthesis/Constraints/spi_unit.ctr (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700a +# set_package fg484 +# set_speed -4 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd.info/Synthesis/Constraints/spi_unit.sdc =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd.info/Synthesis/Constraints/spi_unit.sdc (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/spi_interface/struct.bd.info/Synthesis/Constraints/spi_unit.sdc (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3a +# set_device 3s700a +# set_package fg484 +# set_speed -4 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/spi_interface/symbol.sb =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/spi_interface/symbol.sb (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/spi_interface/symbol.sb (revision 9841) @@ -0,0 +1,2014 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "FACT_FAD_lib" +unitName "fad_definitions" +) +] +libraryRefs [ +"ieee" +"FACT_FAD_lib" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 20,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 53,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "sclk" +t "std_logic" +o 8 +suid 1,0 +) +) +uid 109,0 +) +*15 (LogPort +port (LogicalPort +decl (Decl +n "dac_array" +t "dac_array_type" +o 3 +suid 10,0 +) +) +uid 196,0 +) +*16 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "config_ready" +t "std_logic" +o 4 +suid 11,0 +) +) +uid 318,0 +) +*17 (LogPort +port (LogicalPort +decl (Decl +n "config_start" +t "std_logic" +o 2 +suid 12,0 +) +) +uid 320,0 +) +*18 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "sensor_array" +t "sensor_array_type" +o 9 +suid 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1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol:CDM" +) Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/trigger_counter/symbol.sb =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/trigger_counter/symbol.sb (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/trigger_counter/symbol.sb (revision 9841) @@ -0,0 +1,1464 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "std_logic_arith" +) +(DmPackageRef +library "ieee" +unitName "std_logic_unsigned" +) +] +libraryRefs [ +"ieee" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 3,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 70,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 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"library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_PrecisionSynthesisDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "07" +) +(vvPair +variable "module_name" +value "w5300_modul" +) +(vvPair +variable "month" +value "Jul" +) +(vvPair +variable "month_long" +value "Juli" +) +(vvPair +variable "p" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "11:26:29" +) +(vvPair +variable "unit" +value "w5300_modul" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 173,0 +optionalChildren [ +*113 (SymbolBody +uid 8,0 +optionalChildren [ +*114 (CptPort +uid 48,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 49,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,3625,43000,4375" +) +tg (CPTG +uid 50,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 51,0 +va (VaSet +) +xt "44000,3500,45300,4500" +st "clk" +blo "44000,4300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 52,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,16000,23000,16800" +st "clk : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "clk" +t "std_logic" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*115 (CptPort +uid 53,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 54,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,3625,77750,4375" +) +tg (CPTG +uid 55,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 56,0 +va (VaSet +) +xt "72400,3500,76000,4500" +st "wiz_reset" +ju 2 +blo "76000,4300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 57,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,16800,37000,17600" +st "wiz_reset : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wiz_reset" +t "std_logic" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +i "'1'" +) +) +) +*116 (CptPort +uid 58,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 59,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,5625,77750,6375" +) +tg (CPTG +uid 60,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 61,0 +va (VaSet +) +xt "74100,5500,76000,6500" +st "addr" +ju 2 +blo "76000,6300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 62,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,17600,33000,18400" +st "addr : OUT std_logic_vector (9 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "addr" +t "std_logic_vector" +b "(9 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +) +) +) +*117 (CptPort +uid 63,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 64,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,7625,77750,8375" +) +tg (CPTG +uid 65,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 66,0 +va (VaSet +) +xt "74200,7500,76000,8500" +st "data" +ju 2 +blo "76000,8300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 67,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,18400,33500,19200" +st "data : INOUT std_logic_vector (15 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 2 +decl (Decl +n "data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 4 +suid 4,0 +) +) +) +*118 (CptPort +uid 68,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 69,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,9625,77750,10375" +) +tg (CPTG +uid 70,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 71,0 +va (VaSet +) +xt "74800,9500,76000,10500" +st "cs" +ju 2 +blo "76000,10300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 72,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,19200,37000,20000" +st "cs : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "cs" +t "std_logic" +preAdd 0 +posAdd 0 +o 5 +suid 5,0 +i "'1'" +) +) +) +*119 (CptPort +uid 73,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 74,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,11625,77750,12375" +) +tg (CPTG +uid 75,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 76,0 +va (VaSet +) +xt "74800,11500,76000,12500" +st "wr" +ju 2 +blo "76000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 77,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,20000,37000,20800" +st "wr : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "wr" +t "std_logic" +preAdd 0 +posAdd 0 +o 6 +suid 6,0 +i "'1'" +) +) +) +*120 (CptPort +uid 83,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 84,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,15625,77750,16375" +) +tg (CPTG +uid 85,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 86,0 +va (VaSet +) +xt "74900,15500,76000,16500" +st "rd" +ju 2 +blo "76000,16300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 87,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,21600,37000,22400" +st "rd : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "rd" +t "std_logic" +preAdd 0 +posAdd 0 +o 8 +suid 8,0 +i "'1'" +) +) +) +*121 (CptPort +uid 88,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 89,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,5625,43000,6375" +) +tg (CPTG +uid 90,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 91,0 +va (VaSet +) +xt "44000,5500,45200,6500" +st "int" +blo "44000,6300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 92,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22400,23000,23200" +st "int : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "int" +t "std_logic" +preAdd 0 +posAdd 0 +o 9 +suid 9,0 +) +) +) +*122 (CptPort +uid 93,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 94,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,7625,43000,8375" +) +tg (CPTG +uid 95,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 96,0 +va (VaSet +) +xt "44000,7500,48900,8500" +st "write_length" +blo "44000,8300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 97,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,23200,33500,24000" +st "write_length : IN std_logic_vector (16 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "write_length" +t "std_logic_vector" +b "(16 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 10 +suid 10,0 +) +) +) +*123 (CptPort +uid 98,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 99,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,9625,43000,10375" +) +tg (CPTG +uid 100,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 101,0 +va (VaSet +) +xt "44000,9500,49900,10500" +st "ram_start_addr" +blo "44000,10300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 102,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,24000,40500,24800" +st "ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "ram_start_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 11 +suid 11,0 +) +) +) +*124 (CptPort +uid 103,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 104,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,11625,43000,12375" +) +tg (CPTG +uid 105,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 106,0 +va (VaSet +) +xt "44000,11500,47500,12500" +st "ram_data" +blo "44000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 107,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,24800,33500,25600" +st "ram_data : IN std_logic_vector (15 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "ram_data" +t "std_logic_vector" +b "(15 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 12 +suid 12,0 +) +) +) +*125 (CptPort +uid 108,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 109,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,17625,77750,18375" +) +tg (CPTG +uid 110,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 111,0 +va (VaSet +) +xt "72400,17500,76000,18500" +st "ram_addr" +ju 2 +blo "76000,18300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 112,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,25600,40500,26400" +st "ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "ram_addr" +t "std_logic_vector" +b "(RAM_ADDR_WIDTH-1 DOWNTO 0)" +preAdd 0 +posAdd 0 +o 13 +suid 13,0 +) +) +) +*126 (CptPort +uid 113,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 114,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,13625,43000,14375" +) +tg (CPTG +uid 115,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 116,0 +va (VaSet +) +xt "44000,13500,48100,14500" +st "data_valid" +blo "44000,14300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 117,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,26400,23000,27200" +st "data_valid : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "data_valid" +t "std_logic" +preAdd 0 +posAdd 0 +o 14 +suid 14,0 +) +) +) +*127 (CptPort +uid 118,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 119,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,19625,77750,20375" +) +tg (CPTG +uid 120,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 121,0 +va (VaSet +) +xt "74100,19500,76000,20500" +st "busy" +ju 2 +blo "76000,20300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 122,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,28000,37000,28800" +st "busy : OUT std_logic := '1' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "busy" +t "std_logic" +preAdd 0 +posAdd 0 +o 16 +suid 15,0 +i "'1'" +) +) +) +*128 (CommentText +uid 299,0 +ps "EdgeToEdgeStrategy" +shape (Rectangle +uid 300,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,30800,15000,35800" +) +oxt "0,0,15000,5000" +text (MLText +uid 301,0 +va (VaSet +fg "0,0,32768" +) +xt "200,31000,13900,35000" +st " +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +included 1 +excludeCommentLeader 1 +) +*129 (CptPort +uid 348,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 349,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,14625,43000,15375" +) +tg (CPTG +uid 350,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 351,0 +va (VaSet +) +xt "44000,14500,49700,15500" +st "write_end_flag" +blo "44000,15300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 352,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,29600,23000,30400" +st "write_end_flag : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "write_end_flag" +t "std_logic" +o 18 +suid 18,0 +) +) +) +*130 (CptPort +uid 353,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 354,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,15625,43000,16375" +) +tg (CPTG +uid 355,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 356,0 +va (VaSet +) +xt "44000,15500,50800,16500" +st "write_header_flag" +blo "44000,16300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 357,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,28800,23000,29600" +st "write_header_flag : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "write_header_flag" +t "std_logic" +o 17 +suid 19,0 +) +) +) +*131 (CptPort +uid 385,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 386,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,16625,43000,17375" +) +tg (CPTG +uid 387,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 388,0 +va (VaSet +) +xt "44000,16500,49200,17500" +st "fifo_channels" +blo "44000,17300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 389,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,30400,33000,31200" +st "fifo_channels : IN std_logic_vector (3 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "fifo_channels" +t "std_logic_vector" +b "(3 downto 0)" +o 19 +suid 20,0 +) +) +) +*132 (CptPort +uid 491,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 492,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,20625,77750,21375" +) +tg (CPTG +uid 493,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 494,0 +va (VaSet +) +xt "74600,20500,76000,21500" +st "led" +ju 2 +blo "76000,21300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 495,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,20800,43000,21600" +st "led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "led" +t "std_logic_vector" +b "(7 DOWNTO 0)" +posAdd 0 +o 7 +suid 22,0 +i "(OTHERS => '0')" +) +) +) +*133 (CptPort +uid 521,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 522,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,21625,77750,22375" +) +tg (CPTG +uid 523,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 524,0 +va (VaSet +) +xt "72400,21500,76000,22500" +st "s_trigger" +ju 2 +blo "76000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 525,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,31200,37000,32000" +st "s_trigger : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "s_trigger" +t "std_logic" +o 20 +suid 23,0 +i "'0'" +) +) +) +*134 (CptPort +uid 551,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 552,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,22625,77750,23375" +) +tg (CPTG +uid 553,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 554,0 +va (VaSet +) +xt "71200,22500,76000,23500" +st "config_addr" +ju 2 +blo "76000,23300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 555,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,33600,33000,34400" +st "config_addr : OUT std_logic_vector (7 downto 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_addr" +t "std_logic_vector" +b "(7 downto 0)" +o 23 +suid 24,0 +) +) +) +*135 (CptPort +uid 556,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 557,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,17625,43000,18375" +) +tg (CPTG +uid 558,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 559,0 +va (VaSet +) +xt "44000,17500,48800,18500" +st "config_busy" +blo "44000,18300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 560,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,36800,23000,37600" +st "config_busy : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_busy" +t "std_logic" +o 27 +suid 25,0 +) +) +) +*136 (CptPort +uid 561,0 +ps "OnEdgeStrategy" +shape (Diamond +uid 639,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,23625,77750,24375" +) +tg (CPTG +uid 563,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 564,0 +va (VaSet +) +xt "71300,23500,76000,24500" +st "config_data" +ju 2 +blo "76000,24300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 565,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,34400,43000,35200" +st "config_data : INOUT std_logic_vector (15 downto 0) := (others => 'Z') ; +" +) +thePort (LogicalPort +m 2 +decl (Decl +n "config_data" +t "std_logic_vector" +b "(15 downto 0)" +o 24 +suid 26,0 +i "(others => 'Z')" +) +) +) +*137 (CptPort +uid 566,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 567,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42250,18625,43000,19375" +) +tg (CPTG +uid 568,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 569,0 +va (VaSet +) +xt "44000,18500,49600,19500" +st "config_started" +blo "44000,19300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 570,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,32800,23000,33600" +st "config_started : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "config_started" +t "std_logic" +o 22 +suid 27,0 +) +) +) +*138 (CptPort +uid 571,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 572,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,24625,77750,25375" +) +tg (CPTG +uid 573,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 574,0 +va (VaSet +) +xt "70700,24500,76000,25500" +st "config_wr_en" +ju 2 +blo "76000,25300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 575,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,35200,37000,36000" +st "config_wr_en : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_wr_en" +t "std_logic" +o 25 +suid 28,0 +i "'0'" +) +) +) +*139 (CptPort +uid 576,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 577,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,25625,77750,26375" +) +tg (CPTG +uid 578,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 579,0 +va (VaSet +) +xt "71400,25500,76000,26500" +st "new_config" +ju 2 +blo "76000,26300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 580,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,32000,37000,32800" +st "new_config : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "new_config" +t "std_logic" +o 21 +suid 29,0 +i "'0'" +) +) +) +*140 (CptPort +uid 640,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 641,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,26625,77750,27375" +) +tg (CPTG +uid 642,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 643,0 +va (VaSet +) +xt "70800,26500,76000,27500" +st "config_rd_en" +ju 2 +blo "76000,27300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 644,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,36000,37000,36800" +st "config_rd_en : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "config_rd_en" +t "std_logic" +o 26 +suid 30,0 +i "'0'" +) +) +) +*141 (CptPort +uid 670,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 671,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,27625,77750,28375" +) +tg (CPTG +uid 672,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 673,0 +va (VaSet +) +xt "73000,27500,76000,28500" +st "denable" +ju 2 +blo "76000,28300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 674,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,37600,50500,38400" +st "denable : OUT std_logic := '0' ; -- default domino wave off +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "denable" +t "std_logic" +eolc "-- default domino wave off" +posAdd 0 +o 28 +suid 31,0 +i "'0'" +) +) +) +*142 (CptPort +uid 723,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 724,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,28625,77750,29375" +) +tg (CPTG +uid 725,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 726,0 +va (VaSet +) +xt "70600,28500,76000,29500" +st "dwrite_enable" +ju 2 +blo "76000,29300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 727,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,38400,48500,39200" +st "dwrite_enable : OUT std_logic := '0' ; -- default DWRITE low. +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "dwrite_enable" +t "std_logic" +eolc "-- default DWRITE low." +preAdd 0 +posAdd 0 +o 29 +suid 32,0 +i "'0'" +) +) +) +*143 (CptPort +uid 885,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 886,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,29625,77750,30375" +) +tg (CPTG +uid 887,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 888,0 +va (VaSet +) +xt "70400,29500,76000,30500" +st "data_valid_ack" +ju 2 +blo "76000,30300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 889,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,27200,37000,28000" +st "data_valid_ack : OUT std_logic := '0' ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "data_valid_ack" +t "std_logic" +o 15 +suid 34,0 +i "'0'" +) +) +) +*144 (CptPort +uid 917,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 918,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,30625,77750,31375" +) +tg (CPTG +uid 919,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 920,0 +va (VaSet +) +xt "71300,30500,76000,31500" +st "sclk_enable" +ju 2 +blo "76000,31300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 921,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,39200,48000,40000" +st "sclk_enable : OUT std_logic := '1' -- default DWRITE HIGH. +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sclk_enable" +t "std_logic" +eolc "-- default DWRITE HIGH." +posAdd 0 +o 30 +suid 35,0 +i "'1'" +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "43000,2000,77000,32000" +) +oxt "43000,2000,56000,22000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "47700,11000,53900,12000" +st "FACT_FAD_lib" +blo "47700,11800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "47700,12000,53400,13000" +st "w5300_modul" +blo "47700,12800" +) +) +gi *145 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "43000,200,58000,2600" +st "Generic Declarations + +RAM_ADDR_WIDTH integer 14 +" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "RAM_ADDR_WIDTH" +type "integer" +value "14" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*146 (Grouping +uid 16,0 +optionalChildren [ +*147 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "47000,30000,64000,31000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "47200,30000,56500,31000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*148 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "64000,26000,68000,27000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "64200,26000,67200,27000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*149 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "47000,28000,64000,29000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "47200,28000,57200,29000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*150 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "43000,28000,47000,29000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "43200,28000,45300,29000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*151 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "64000,27000,84000,31000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "64200,27200,73400,28200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*152 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "68000,26000,84000,27000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "68200,26000,72700,27000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*153 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "43000,26000,64000,28000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "50150,26500,56850,27500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*154 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "43000,29000,47000,30000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "43200,29000,45300,30000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*155 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "43000,30000,47000,31000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "43200,30000,45900,31000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*156 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "47000,29000,64000,30000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "47200,29000,60900,30000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "43000,26000,84000,31000" +) +oxt "14000,66000,55000,71000" +) +*157 (CommentText +uid 133,0 +shape (Rectangle +uid 134,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,-6000,33000,0" +) +text (MLText +uid 135,0 +va (VaSet +fg "0,0,32768" +font "Arial,10,0" +) +xt "200,-5800,32200,-600" +st " +Created using Mentor Graphics HDL2Graphics(TM) Technology +on - 10:21:37 04.02.2010 +from - D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hdl\\w5300_modul.vhd + +" +tm "CommentText" +wrapOption 3 +visibleHeight 5600 +visibleWidth 32600 +) +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *158 (PackageList +uid 170,0 +stg "VerticalLayoutStrategy" +textVec [ +*159 (Text +uid 171,0 +va (VaSet +font "arial,8,1" +) +xt "0,1000,5400,2000" +st "Package List" +blo "0,1800" +) +*160 (MLText +uid 172,0 +va (VaSet +) +xt "0,2000,15200,8000" +st "library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library FACT_FAD_lib; +use FACT_FAD_lib.fad_definitions.ALL;" +tm "PackageList" +) +] +) +windowSize "0,0,1015,690" +viewArea "0,0,0,0" +cachedDiagramExtent "0,0,0,0" +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *161 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *162 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "0,14000,5400,15000" +st "Declarations" +blo "0,14800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "0,15000,2700,16000" +st "Ports:" +blo "0,15800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "0,40000,2400,41000" +st "User:" +blo "0,40800" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "0,14000,5800,15000" +st "Internal User:" +blo "0,14800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,41000,2000,41000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,14000,0,14000" +tm "SyDeclarativeTextMgr" +) +) +lastUid 925,0 +activeModelName "Symbol:CDM" +) Index: /firmware/FTU/FTU_control.vhd =================================================================== --- /firmware/FTU/FTU_control.vhd (revision 9841) +++ /firmware/FTU/FTU_control.vhd (revision 9841) @@ -0,0 +1,110 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 08/06/2010 +-- Design Name: +-- Module Name: FTU_control - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Control FSM of FACT FTU board +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library ftu_definitions; +USE ftu_definitions.ftu_array_types.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTU_control is + port( + clk_50MHz : IN std_logic; + clk_ready : IN std_logic; + config_ready : IN std_logic; + reset : OUT std_logic; + config_start : OUT std_logic + ); +end FTU_control; + +architecture Behavioral of FTU_control is + + signal reset_sig : STD_LOGIC := '0'; + + signal config_start_sig : STD_LOGIC := '0'; + signal config_ready_sig : STD_LOGIC := '0'; + + type FTU_control_StateType is (IDLE, INIT, RUNNING, RESET_ALL); + signal FTU_control_State, FTU_control_NextState: FTU_control_StateType; + +begin + + --FTU control state machine (two-process implementation) + + FTU_control_Registers: process (clk_50MHz) + begin + if Rising_edge(clk_50MHz) then + FTU_control_State <= FTU_control_NextState; + end if; + end process FTU_control_Registers; + + FTU_control_C_logic: process (FTU_control_State, clk_ready, config_ready_sig) + begin + FTU_control_NextState <= FTU_control_State; + case FTU_control_State is + when IDLE => -- wait for DMCs to lock + reset_sig <= '0'; + config_start_sig <= '0'; + --ram_web_sig <= "0"; + if (clk_ready = '1') then + FTU_control_NextState <= RUNNING; + end if; + when INIT => -- load default config data to RAM + reset_sig <= '0'; + config_start_sig <= '0'; + --ram_web_sig <= "1"; + --ram_adb_cntr <= ram_adb_cntr + 1; + --ram_adb_sig <= conv_std_logic_vector(ram_adb_cntr, 4); + --if (ram_adb_cntr < 4) then + -- ram_dib_sig <= DEFAULT_ENABLE(ram_adb_cntr); + -- FTU_top_NextState <= INIT; + --elsif (ram_adb_cntr < 4 + 5) then + -- ram_dib_sig <= conv_std_logic_vector(DEFAULT_DAC(ram_adb_cntr - 4), 16); + -- FTU_top_NextState <= INIT; + --elsif (ram_adb_cntr < 32) then + -- ram_dib_sig <= (others => '0'); + -- FTU_top_NextState <= INIT; + --else + -- ram_adb_cntr <= 0; + -- ram_web_sig <= "0"; + -- FTU_top_NextState <= RUNNING; + --end if; + when RUNNING => -- count triggers and react to commands + reset_sig <= '0'; + config_start_sig <= '0'; + --ram_web_sig <= "0"; + when RESET_ALL => -- reset/clear and start from scratch + reset_sig <= '1'; + config_start_sig <= '0'; + --ram_web_sig <= "0"; + FTU_control_NextState <= IDLE; + end case; + end process FTU_control_C_logic; + + reset <= reset_sig; + +end Behavioral; Index: /firmware/FTU/FTU_top.vhd =================================================================== --- /firmware/FTU/FTU_top.vhd (revision 9841) +++ /firmware/FTU/FTU_top.vhd (revision 9841) @@ -0,0 +1,202 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 11:59:40 01/19/2010 +-- Design Name: +-- Module Name: FTU_top - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Top level entity of FACT FTU board +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Revision 0.02 - New design of FTU firmware, 12.07.2010, Q. Weitzel +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library ftu_definitions; +USE ftu_definitions.ftu_array_types.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTU_top is + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); +end FTU_top; + +architecture Behavioral of FTU_top is + + signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up + signal dac_clr_sig : STD_LOGIC := '1'; -- initialize dac_clr to 1 at power up + + signal config_start_sig : STD_LOGIC := '0'; + signal config_ready_sig : STD_LOGIC := '0'; + + signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM + signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTU_clk_gen when DCMs have locked + + --signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port A + --signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port B + --signal ram_ada_cntr : INTEGER range 0 to 2**5 - 1 := 0; + --signal ram_adb_cntr : INTEGER range 0 to 2**4 - 1 := 0; + --signal ram_ada_sig : STD_LOGIC_VECTOR(4 downto 0); + --signal ram_adb_sig : STD_LOGIC_VECTOR(3 downto 0); + --signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0); + --signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0); + --signal ram_doa_sig : STD_LOGIC_VECTOR(7 downto 0); + --signal ram_dob_sig : STD_LOGIC_VECTOR(15 downto 0); + + component FTU_clk_gen + port( + clk : IN STD_LOGIC; + rst : IN STD_LOGIC; + clk_50 : OUT STD_LOGIC; + ready : OUT STD_LOGIC + ); + end component; + + component FTU_control + port( + clk_50MHz : IN std_logic; + clk_ready : IN std_logic; + config_ready : IN std_logic; + reset : OUT std_logic; + config_start : OUT std_logic + ); + end component; + + component FTU_spi_interface + port( + clk_50MHz : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + config_ready : OUT std_logic; + config_started : OUT std_logic; + dac_cs : OUT std_logic; + mosi : OUT std_logic; + sclk : OUT std_logic + ); + end component; + + --component FTU_dual_port_ram + -- port( + -- clka : IN std_logic; + -- ena : IN std_logic; + -- wea : IN std_logic_VECTOR(0 downto 0); + -- addra : IN std_logic_VECTOR(4 downto 0); + -- dina : IN std_logic_VECTOR(7 downto 0); + -- douta : OUT std_logic_VECTOR(7 downto 0); + -- clkb : IN std_logic; + -- enb : IN std_logic; + -- web : IN std_logic_VECTOR(0 downto 0); + -- addrb : IN std_logic_VECTOR(3 downto 0); + -- dinb : IN std_logic_VECTOR(15 downto 0); + -- doutb : OUT std_logic_VECTOR(15 downto 0) + -- ); + --end component; + + -- Synplicity black box declaration + --attribute syn_black_box : boolean; + --attribute syn_black_box of FTU_dual_port_ram: component is true; + +begin + + clr <= dac_clr_sig; + + Inst_FTU_clk_gen : FTU_clk_gen + port map( + clk => ext_clk, + rst => reset_sig, + clk_50 => clk_50M_sig, + ready => clk_ready_sig + ); + + Inst_FTU_control : FTU_control + port map( + clk_50MHz => clk_50M_sig, + clk_ready => clk_ready_sig, + config_ready => config_ready_sig, + reset => reset_sig, + config_start => config_start_sig + ); + + Inst_FTU_spi_interface : FTU_spi_interface + port map( + clk_50MHz => clk_50M_sig, + config_start => config_start_sig, + dac_array => DEFAULT_DAC, -- has to come from RAM + config_ready => config_ready_sig, + config_started => open, + dac_cs => cs_ld, + mosi => mosi, + sclk => sck + ); + + --Inst_FTU_dual_port_ram : FTU_dual_port_ram + -- port map( + -- clka => clk_50M_sig, + -- ena => '1', + -- wea => ram_wea_sig, + -- addra => ram_ada_sig, + -- dina => ram_dia_sig, + -- douta => ram_doa_sig, + -- clkb => clk_50M_sig, + -- enb => '1', + -- web => ram_web_sig, + -- addrb => ram_adb_sig, + -- dinb => ram_dib_sig, + -- doutb => ram_dob_sig + -- ); + +end Behavioral; Index: /firmware/FTU/FTU_top_tb.vhd =================================================================== --- /firmware/FTU/FTU_top_tb.vhd (revision 9841) +++ /firmware/FTU/FTU_top_tb.vhd (revision 9841) @@ -0,0 +1,171 @@ +-------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 12.07.2010 +-- Design Name: +-- Module Name: FTU_top_tb.vhd +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: Testbench for top level entity of FACT FTU board +-- +-- VHDL Test Bench Created by ISE for module: FTU_top +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity FTU_top_tb is +end FTU_top_tb; + +architecture behavior of FTU_top_tb is + + -- Component Declaration for the Unit Under Test (UUT) + + component FTU_top + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); + end component; + + --Inputs + signal ext_clk : STD_LOGIC := '0'; + signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); + signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); + signal patch_A_p : STD_LOGIC := '0'; + signal patch_A_n : STD_LOGIC := '0'; + signal patch_B_p : STD_LOGIC := '0'; + signal patch_B_n : STD_LOGIC := '0'; + signal patch_C_p : STD_LOGIC := '0'; + signal patch_C_n : STD_LOGIC := '0'; + signal patch_D_p : STD_LOGIC := '0'; + signal patch_D_n : STD_LOGIC := '0'; + signal trig_prim_p : STD_LOGIC := '0'; + signal trig_prim_n : STD_LOGIC := '0'; + signal rx : STD_LOGIC := '0'; + + --Outputs + signal enables_A : STD_LOGIC_VECTOR(8 downto 0); + signal enables_B : STD_LOGIC_VECTOR(8 downto 0); + signal enables_C : STD_LOGIC_VECTOR(8 downto 0); + signal enables_D : STD_LOGIC_VECTOR(8 downto 0); + signal clr : STD_LOGIC; + signal cs_ld : STD_LOGIC; + signal sck : STD_LOGIC; + signal mosi : STD_LOGIC; + signal tx : STD_LOGIC; + signal rx_en : STD_LOGIC; + signal tx_en : STD_LOGIC; + signal TP_A : STD_LOGIC_VECTOR(11 downto 0); + + -- Clock period definitions + constant ext_clk_period : TIME := 20 ns; + +begin + + -- Instantiate the Unit Under Test (UUT) + uut: FTU_top + port map( + ext_clk => ext_clk, + brd_add => brd_add, + brd_id => brd_id, + patch_A_p => patch_A_p, + patch_A_n => patch_A_n, + patch_B_p => patch_B_p, + patch_B_n => patch_B_n, + patch_C_p => patch_C_p, + patch_C_n => patch_C_n, + patch_D_p => patch_D_p, + patch_D_n => patch_D_n, + trig_prim_p => trig_prim_p, + trig_prim_n => trig_prim_n, + rx => rx, + rx_en => rx_en, + enables_A => enables_A, + enables_B => enables_B, + enables_C => enables_C, + enables_D => enables_D, + clr => clr, + cs_ld => cs_ld, + sck => sck, + mosi => mosi, + tx => tx, + tx_en => tx_en, + TP_A => TP_A + ); + + -- Clock process definitions + ext_clk_proc: process + begin + ext_clk <= '0'; + wait for ext_clk_period/2; + ext_clk <= '1'; + wait for ext_clk_period/2; + end process ext_clk_proc; + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + wait for 100ms; + + wait for ext_clk_period*10; + + -- insert stimulus here + + wait; + end process stim_proc; + +end; Index: /firmware/FTU/clock/FTU_clk_gen.vhd =================================================================== --- /firmware/FTU/clock/FTU_clk_gen.vhd (revision 9841) +++ /firmware/FTU/clock/FTU_clk_gen.vhd (revision 9841) @@ -0,0 +1,63 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Q. Weitzel +-- +-- Create Date: 14:09:39 07/12/2010 +-- Design Name: +-- Module Name: FTU_clk_gen - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: interface to different DCMs and clk dividers for FTU board +-- add here more DCMs if needed +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTU_clk_gen is + Port ( + clk : IN STD_LOGIC; + rst : IN STD_LOGIC; + clk_50 : OUT STD_LOGIC; + ready : OUT STD_LOGIC + ); +end FTU_clk_gen; + +architecture Behavioral of FTU_clk_gen is + + component FTU_dcm_50M_to_50M + port ( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + LOCKED_OUT : out std_logic); + end component; + +begin + + Inst_FTU_dcm_50M_to_50M : FTU_dcm_50M_to_50M + port map( + CLKIN_IN => clk, + RST_IN => rst, + CLKFX_OUT => clk_50, + CLKIN_IBUFG_OUT => open, + LOCKED_OUT => ready + ); + +end Behavioral; + Index: /firmware/FTU/clock/FTU_dcm_50M_to_50M.vhd =================================================================== --- /firmware/FTU/clock/FTU_dcm_50M_to_50M.vhd (revision 9841) +++ /firmware/FTU/clock/FTU_dcm_50M_to_50M.vhd (revision 9841) @@ -0,0 +1,90 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.5 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTU_dcm_50M_to_50M.vhd +-- /___/ /\ Timestamp : 07/12/2010 13:46:25 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /ihp/home01/qweitzel/CT3-FACT/fact_repos.svn/FPGA/FTU/clock/FTU_dcm_50M_to_50M.xaw /ihp/home01/qweitzel/CT3-FACT/fact_repos.svn/FPGA/FTU/clock/FTU_dcm_50M_to_50M +--Design Name: FTU_dcm_50M_to_50M +--Device: xc3s400an-4fgg400 +-- +-- Module FTU_dcm_50M_to_50M +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.79 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTU_dcm_50M_to_50M is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end FTU_dcm_50M_to_50M; + +architecture BEHAVIORAL of FTU_dcm_50M_to_50M is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 2, + CLKFX_MULTIPLY => 2, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: /firmware/FTU/clock/FTU_dcm_50M_to_50M.xaw =================================================================== --- /firmware/FTU/clock/FTU_dcm_50M_to_50M.xaw (revision 9841) +++ /firmware/FTU/clock/FTU_dcm_50M_to_50M.xaw (revision 9841) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.5e +$6dx17=(aaz$dbcj00-rs`osrlf$OY="F@AW+cgd|Vxn|b}!swl,BUAF'O^^#nb`cj-EPPYckdU><@Q{o^73I+~f81;86>!05684+1>92;?7<:5NRBJTM_703HX\VRAALX]@EVEFL@DLSNBD199BVR\XGGFRSNBDIO]F\QCUFHF:96O]W[]LJI_XKEABBRXNLTG2f>GU_SUDBAWPDBO\WROSKACEKRMCK028EWQ]WFDGURJKR^A355=FZ^PTCCBV_EFQ[F7692KY[WQ@NM[\@ATXKEA::6O]W[]LJI_XLMXTJAG_FMMS50=FZ^PTCCBV_G@\A]RBZGKG=?5NRVX\KKJ^W@DXXR@ZMd9BVR\XGGFRS]CLD078EWQ]WFDGUR\JSDV\HJANK820M_YU_NLO]ZPFD@NTHK]PMNFFe>GT[FIT[DZGf:CT^ZEKCK_MXT^J1018ER\XKEATCXZ_UU]W]UCd3H]QSKB@WU[SA==F_SU[M_Zk;@UY[V_I\A^DCA:4BNVK0>DRNN>0OAE?6:AOO4>7>2IGG?9?5:AOO7^?3JF@>U?7049@HN?7=2IGGIXl;BNH@SYCA_COI85LLJDA1>EKCOR37NBDFY3;4<=DDBLSSO[If:AOOC^XJ\LLSD@\Tb9@HN@_WMC]EIKj;BNHB]YJ]E^B\AW6;BNHB]YH]]?0OAEFN038GIMNFVNBZDJJ_C[\6g=DDBCESDLZFF33?FJLAGUBNXHH_HLPPc=DDBCESDLZFF]LQQ>7I[[Y^AZGICXKFXYINZFOO58@ZPFD\O37HV[ESLBHd=AIJ^D^TQEF49EEIUB12LIS^AZRBG:?COIW\DBX^64FNWW[VRUi2LDYYQZNHVPe>@H]]U]MA[J2:D[5>O23@H^JJ?>;KKWP@TXAGZ^XRZVPDa8NLRSM[U[G?^Dc:HJPQCUW_KGYH84LNAHAAgI?3FLOH_M_Ec9SLDUBWZBBJY74PHLKEVDR[h1[ECG\GOFF@==WAG]BHYF7;QPJIQ_WM8:0\_A__QKMMVGD\@\N96^\CMI5?UUCGGO?7]]JN99SWLHDLLI87_][6:PPPZOIj2YBKHV[ESLBH3=TAGMGIn5\T@PWQUYPI@^=7^ZNTTQ26>U^[]OFS^WACIPLJJST;2^D\95[RTG;?PUBWK_MK45ZSD]AQCAT=2\BIZ?m;YCT[SCU[@EE=i5WIMKM\(^CJ):%=-][UC"3*4&F[JCB:6Vkb^Kg55=_ldUFmga}Vdppmjh682RoaRCfnnpUawungg?0W=4?]49X4?1Z<2ky{w=4dboa?scu{`ee,< ?4:tk`i763qi89>?ao/7bba38990t~zr@Ar04>FGp90M6?4>{R1`>2?=?k0:??l96982fa3dsg=>6<5a7786?!132>90q^=m:6;93g<6;;h=:54>bga2?a1>290:6;1<7?51;5xW6e=?00c;5`?!7c2>n0(3;294~"1839o7)m5269'`?0>3-l1><5+11815>"693897)?=:338 45==k1/=9499:&21?2<,8<1945+16873>"603;m7)=n:4;8 7>=?2.9i794$3d93>"4:3><7)=8:99'7=<3=2.857;6;%1e>3e<,=>186*;0;76?!26236874$5;913=#:6*;c;c8 06=

4=#>h0?;6*9f;53?!c=i2.:n7:k;%71>7=#=8087d=>:18'1c<0?2.==78j;:k1=?6=,"1931/:<49e:9j21<72-?m6:94$4g92`=i78j;:k76?6=,=h:80;6);i:658?j41290/9k487:9l67<72-?m6:94;n00>5<#=o0<;65`2683>!3a2>=07b<;:18'1c<0?21d>84?:%7e>21<3f8j6=4+5g843>"193:50;094?6|,?:18k5f4d83>!3a2>=0(;?56d98k0g=83.>j798;%42>3c<3th9h7>52;294~"1838;7d:j:18'1c<0?2.==78j;:m6e?6=,=z{:91<7m6*>9;16?xu1?3:1=v3k5529'2=<2i2wx?;4?:0y>71<3m2.=47:j;|q04?6=9r79h7;n;%4;>0g6=4?{%4;>0g7>51zm66<728qvb?:50;3xyk42290:wp`=6;295~{i:>0;6 '0'); + dac_cs : OUT std_logic := '1'; + dac_start : IN std_logic; + dac_ready : OUT std_logic := '0' + ); +END FTU_spi_controller ; + +ARCHITECTURE beha OF FTU_spi_controller IS + + type TYPE_SPI_STATE is (SPI_IDLE, SPI_LOAD_DAC, SPI_LOAD_COMMAND); + + signal spi_state : TYPE_SPI_STATE := SPI_IDLE; + signal spi_cycle_cnt : integer range 0 to 25 := 0; + signal shift_reg : std_logic_vector (23 downto 0) := (others => '0'); + signal data_reg : std_logic_vector (15 downto 0) := (others => '0'); + +BEGIN + + spi_write_proc: process (clk) + begin + if falling_edge(clk) then + dac_cs <= '1'; + mosi <= '0'; + case spi_state is + when SPI_IDLE => + if (dac_start = '1') then + dac_ready <= '0'; + spi_state <= SPI_LOAD_COMMAND; + end if; + + when SPI_LOAD_COMMAND => + spi_cycle_cnt <= 0; + if (dac_start = '1') then + shift_reg <= "0011" & '0' & dac_id & data(11 downto 0) & "0000"; + spi_state <= SPI_LOAD_DAC; + end if; + + -- start loading DACs + when SPI_LOAD_DAC => + dac_cs <= '0'; + if (spi_cycle_cnt < 24) then + mosi <= shift_reg(23); + shift_reg <= shift_reg(22 downto 0) & shift_reg(23); + dac_ready <= '0'; + spi_cycle_cnt <= spi_cycle_cnt + 1; + spi_state <= SPI_LOAD_DAC; + else + dac_cs <= '1'; + dac_ready <= '1'; + spi_state <= SPI_IDLE; + end if; + end case; + end if; + end process spi_write_proc; + +END ARCHITECTURE beha; Index: /firmware/FTU/dac_spi/FTU_spi_distributor.vhd =================================================================== --- /firmware/FTU/dac_spi/FTU_spi_distributor.vhd (revision 9841) +++ /firmware/FTU/dac_spi/FTU_spi_distributor.vhd (revision 9841) @@ -0,0 +1,88 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_distributor.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 09:24:21 23.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- modified by Q. Weitzel +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +library ftu_definitions; +USE ftu_definitions.ftu_array_types.all; + +ENTITY FTU_spi_distributor IS + PORT( + clk : IN std_logic; -- 50MHz + config_start : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0'; + dac_array : IN dac_array_type; + dac_config_start : OUT std_logic := '0'; + dac_config_ready : IN std_logic; + dac_id : OUT std_logic_vector(2 downto 0) := (others => '0'); + data : OUT std_logic_vector(15 downto 0) := (others => '0') + ); +END ENTITY FTU_spi_distributor; + +ARCHITECTURE beha OF FTU_spi_distributor IS + + type TYPE_SPI_DISTRIBUTION_STATE is (INIT, IDLE, CONFIG_DAC); + + signal spi_distr_state : TYPE_SPI_DISTRIBUTION_STATE := INIT; + signal dac_id_cnt : integer range 0 to 7 := 0; + +BEGIN + + spi_distribute_proc: process (clk) + begin + + if rising_edge(clk) then + data <= (others => '0'); + case spi_distr_state is + when INIT => + data <= (others => '0'); + spi_distr_state <= IDLE; + when IDLE => + data <= (others => '0'); + -- start DAC configuration + if (config_start = '1') then + config_started <= '1'; + config_ready <= '0'; + dac_config_start <= '1'; + dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); + data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); + spi_distr_state <= CONFIG_DAC; + end if; + + -- DAC configuration + when CONFIG_DAC => + dac_config_start <= '1'; + dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); + data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); + if (dac_config_ready = '1') then + dac_config_start <= '0'; + if (dac_id_cnt < 7) then + dac_id_cnt <= dac_id_cnt + 1; + dac_config_start <= '1'; + spi_distr_state <= CONFIG_DAC; + else + dac_id_cnt <= 0; + config_started <= '0'; + config_ready <= '1'; + spi_distr_state <= IDLE; + end if; + end if; + end case; + end if; + + end process spi_distribute_proc; + +END ARCHITECTURE beha; + Index: /firmware/FTU/dac_spi/FTU_spi_interface.vhd =================================================================== --- /firmware/FTU/dac_spi/FTU_spi_interface.vhd (revision 9841) +++ /firmware/FTU/dac_spi/FTU_spi_interface.vhd (revision 9841) @@ -0,0 +1,126 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 07/01/2010 +-- Design Name: +-- Module Name: FTU_spi_interface - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Based on VHDL Entity FACT_FAD_lib.spi_interface.symbol +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ftu_definitions; +USE ftu_definitions.ftu_array_types.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +ENTITY FTU_spi_interface IS + PORT( + clk_50MHz : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + config_ready : OUT std_logic; + config_started : OUT std_logic := '0'; + dac_cs : OUT std_logic; + mosi : OUT std_logic := '0'; + sclk : OUT std_logic + ); +END FTU_spi_interface; + +ARCHITECTURE struct OF FTU_spi_interface IS + + SIGNAL dac_config_ready : std_logic; + SIGNAL dac_config_start : std_logic; + SIGNAL dac_id : std_logic_vector(2 DOWNTO 0); + SIGNAL data : std_logic_vector(15 DOWNTO 0); + SIGNAL sclk_internal : std_logic; + + COMPONENT FTU_spi_clock_generator + GENERIC ( + CLK_DIVIDER : integer := 25 --2 MHz @ 50 MHz + ); + PORT ( + clk : IN std_logic; + sclk : OUT std_logic := '0' + ); + END COMPONENT; + + COMPONENT FTU_spi_controller + PORT ( + clk : IN std_logic; + dac_id : IN std_logic_vector (2 DOWNTO 0); + dac_start : IN std_logic; + dac_cs : OUT std_logic := '1'; + dac_ready : OUT std_logic := '0'; + mosi : OUT std_logic := '0'; + data : IN std_logic_vector (15 DOWNTO 0) := (others => '0') + ); + END COMPONENT; + + COMPONENT FTU_spi_distributor + PORT ( + clk : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + dac_config_ready : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0'; + dac_config_start : OUT std_logic := '0'; + dac_id : OUT std_logic_vector (2 DOWNTO 0) := (others => '0'); + data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') + ); + END COMPONENT; + +BEGIN + + Inst_FTU_spi_clock_generator : FTU_spi_clock_generator + GENERIC MAP( + CLK_DIVIDER => 25 --2 MHz @ 50 MHz + ) + PORT MAP( + clk => clk_50MHz, + sclk => sclk_internal + ); + + Inst_FTU_spi_controller : FTU_spi_controller + PORT MAP ( + clk => sclk_internal, + mosi => mosi, + dac_id => dac_id, + data => data, + dac_cs => dac_cs, + dac_start => dac_config_start, + dac_ready => dac_config_ready + ); + + Inst_FTU_spi_distributor : FTU_spi_distributor + PORT MAP ( + clk => sclk_internal, + config_start => config_start, + config_ready => config_ready, + config_started => config_started, + dac_array => dac_array, + dac_config_start => dac_config_start, + dac_config_ready => dac_config_ready, + dac_id => dac_id, + data => data + ); + + sclk <= sclk_internal; + +END struct; Index: /firmware/FTU/ftu_board.ucf =================================================================== --- /firmware/FTU/ftu_board.ucf (revision 9841) +++ /firmware/FTU/ftu_board.ucf (revision 9841) @@ -0,0 +1,145 @@ +######################################################## +# FTU Board +# FACT Trigger Unit +# +# Pin location constraints +# +# by Patrick Vogler, Quirin Weitzel +# 01 July 2010 +######################################################## + + +#Clock +####################################################### +NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk + + +# RS-485 Interface +####################################################### +NET rx_en LOC = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver +NET tx_en LOC = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter +NET tx LOC = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM +NET rx LOC = R20 | IOSTANDARD=LVCMOS33; # 485_DI: serial data from FTM + + +# Board ID - inputs +# local board-ID "solder programmable" +####################################################### +NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0 +NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1 +NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2 +NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3 +NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4 +NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5 +NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6 +NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7 + + +# Board Addresses +# geographical slot address +####################################################### +NET brd_add<0> LOC = A15 | IOSTANDARD=LVCMOS33; # ADDR0 +NET brd_add<1> LOC = B15 | IOSTANDARD=LVCMOS33; # ADDR1 +NET brd_add<2> LOC = A16 | IOSTANDARD=LVCMOS33; # ADDR2 +NET brd_add<3> LOC = A17 | IOSTANDARD=LVCMOS33; # ADDR3 +NET brd_add<4> LOC = A18 | IOSTANDARD=LVCMOS33; # ADDR4 +NET brd_add<5> LOC = B18 | IOSTANDARD=LVCMOS33; # ADDR5 + + +# DAC SPI Interface +####################################################### +NET mosi LOC = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in +NET sck LOC = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC +NET cs_ld LOC = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC +NET clr LOC = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC + + +# Testpoints +###################################################### +# on Connector J5 +NET TP_A<0> LOC = B3 | IOSTANDARD=LVCMOS33; # TP0_0 +NET TP_A<1> LOC = A3 | IOSTANDARD=LVCMOS33; # TP1_0 +NET TP_A<2> LOC = A4 | IOSTANDARD=LVCMOS33; # TP2_0 +NET TP_A<3> LOC = B5 | IOSTANDARD=LVCMOS33; # TP2_0 + +# on Connector J6 +NET TP_A<4> LOC = A5 | IOSTANDARD=LVCMOS33; # TP4_0 +NET TP_A<5> LOC = A6 | IOSTANDARD=LVCMOS33; # TP5_0 +NET TP_A<6> LOC = B7 | IOSTANDARD=LVCMOS33; # TP6_0 +NET TP_A<7> LOC = A7 | IOSTANDARD=LVCMOS33; # TP7_0 + +# on Connector J7 +NET TP_A<8> LOC = B11 | IOSTANDARD=LVCMOS33; # TP8_0 +NET TP_A<9> LOC = A12 | IOSTANDARD=LVCMOS33; # TP9_0 +NET TP_A<10> LOC = B12 | IOSTANDARD=LVCMOS33; # TP10_0 +NET TP_A<11> LOC = A14 | IOSTANDARD=LVCMOS33; # TP11_0 + + +# Rate counter LVDS Inputs +###################################################### +# logic signal from first trigger patch +NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P +NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N + +# logic signal from second trigger patch +NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P +NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N + +# logic signal from third trigger patch +NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P +NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N + +# logic signal from fourth trigger patch +NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P +NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N + +#The Trigger Primitive: logic signal from n-out-of-4 circuit +NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+ +NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P- + + +# Enables +###################################################### +# Patch 0 +NET enables_A<0> LOC = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 +NET enables_A<1> LOC = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1 +NET enables_A<2> LOC = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2 +NET enables_A<3> LOC = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3 +NET enables_A<4> LOC = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4 +NET enables_A<5> LOC = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5 +NET enables_A<6> LOC = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6 +NET enables_A<7> LOC = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7 +NET enables_A<8> LOC = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8 + +## Patch 1 +NET enables_B<0> LOC = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0 +NET enables_B<1> LOC = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1 +NET enables_B<2> LOC = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2 +NET enables_B<3> LOC = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3 +NET enables_B<4> LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4 +NET enables_B<5> LOC = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5 +NET enables_B<6> LOC = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6 +NET enables_B<7> LOC = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7 +NET enables_B<8> LOC = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8 + +# Patch 2 +NET enables_C<0> LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0 +NET enables_C<1> LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1 +NET enables_C<2> LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2 +NET enables_C<3> LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3 +NET enables_C<4> LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4 +NET enables_C<5> LOC = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5 +NET enables_C<6> LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6 +NET enables_C<7> LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7 +NET enables_C<8> LOC = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8 + +# Patch 3 +NET enables_D<0> LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<1> LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<2> LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<3> LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<4> LOC = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<5> LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<6> LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<7> LOC = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<8> LOC = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 Index: /firmware/FTU/ftu_definitions.vhd =================================================================== --- /firmware/FTU/ftu_definitions.vhd (revision 9841) +++ /firmware/FTU/ftu_definitions.vhd (revision 9841) @@ -0,0 +1,18 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- use IEEE.NUMERIC_STD.ALL; + +package ftu_array_types is + + type enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0); + constant DEFAULT_ENABLE : enable_array_type := ("0000000111111111", --patch A + "0000000111111111", --patch B + "0000000111111111", --patch C + "0000000111111111");--patch D + + type dac_array_type is array (0 to 7) of integer range 0 to 2**12 - 1; + constant DEFAULT_DAC : dac_array_type := (500, 500, 500, 500, 0, 0, 0, 100); + +end ftu_array_types; Index: /firmware/FTU/old_design/FTU_dac_control.vhd =================================================================== --- /firmware/FTU/old_design/FTU_dac_control.vhd (revision 9841) +++ /firmware/FTU/old_design/FTU_dac_control.vhd (revision 9841) @@ -0,0 +1,180 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 16:24:08 01/19/2010 +-- Design Name: +-- Module Name: FTU_dac_control - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: control DAC on FTU board to set trigger thresholds +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTU_dac_control is + port( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + miso : IN STD_LOGIC; + clr : OUT STD_LOGIC; + mosi : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + cs_ld : OUT STD_LOGIC + ); +end FTU_dac_control; + +architecture Behavioral of FTU_dac_control is + + constant RESET_ACTIVE : std_logic := '0'; + + component spi_interface_16 + port( + clk : IN STD_LOGIC; + clkdiv : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + cpha : IN STD_LOGIC; + cpol : IN STD_LOGIC; + miso : IN STD_LOGIC; + rcv_cpol : IN STD_LOGIC; + rcv_full_reset : IN STD_LOGIC; + reset : IN STD_LOGIC; + ss_in_n : IN STD_LOGIC; + ss_mask_reg : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + start : IN STD_LOGIC; + xmit_data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + xmit_empty_reset : IN STD_LOGIC; + rcv_load : INOUT STD_LOGIC; + sck : INOUT STD_LOGIC; + ss_in_int : INOUT STD_LOGIC; + ss_n_int : INOUT STD_LOGIC; + xmit_empty : INOUT STD_LOGIC; + done : OUT STD_LOGIC; + mosi : OUT STD_LOGIC; + rcv_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + rcv_full : OUT STD_LOGIC; + ss_n : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + end component; + + component upcnt16 + port( + full : out STD_LOGIC; + clr : in STD_LOGIC; + reset : in STD_Logic; + clk : in STD_LOGIC + ); + end component; + + signal clk_sig : std_logic; + signal done_sig : std_logic; + signal start_sig : std_logic; + signal slave_select_sig : std_logic; + signal full_sig : std_logic; + signal clr_wcnt_sig : std_logic; + signal s_clock_sig : std_logic; + signal D_sig : STD_LOGIC_VECTOR (15 DOWNTO 0); + signal ss_n_sig : STD_LOGIC_VECTOR (7 DOWNTO 0); + signal reset_sig : STD_LOGIC; + signal reset_sig_inv : STD_LOGIC; + + -- Build an enumerated type for the state machine + type state_type is (Idle); + + -- Register to hold the current state + signal state, next_state: state_type; + +begin + + reset_sig <= reset; + reset_sig_inv <= not(reset); + clk_sig <= clk; + sck <= s_clock_sig; + clr <= reset_sig_inv; + cs_ld <= ss_n_sig(0); + + -- FSM for dac control: first process + FSM_Registers: process(clk_sig, reset_sig) + begin + if reset_sig = '1' then + state <= Idle; + elsif Rising_edge(clk_sig) then + state <= next_state; + end if; + end process; + + -- FSM for dac control: second process + FSM_logic: process(state) + begin + next_state <= state; + case state is + when Idle => + D_sig <= "0001000100000000"; + start_sig <= '0'; + slave_select_sig <= '0'; + clr_wcnt_sig <= '0'; + end case; + end process; + + Inst_spi_interface_16 : spi_interface_16 + port map( + clk=>clk_sig, clkdiv(1)=>'0', clkdiv(0)=>'0', + cpha=>'1', cpol=>'1', miso=>'1', rcv_cpol=>'1', + rcv_full_reset=>not(RESET_ACTIVE), reset=>reset_sig_inv, ss_in_n=>'1', + ss_mask_reg(7)=>'0', ss_mask_reg(6)=>'0', + ss_mask_reg(5)=>'0', ss_mask_reg(4)=>'0', + ss_mask_reg(3)=>'0', ss_mask_reg(2)=>'0', + ss_mask_reg(1)=>'0', ss_mask_reg(0)=>slave_select_sig, + start=>start_sig, + xmit_data(15)=>D_sig(15), xmit_data(14)=>D_sig(14), + xmit_data(13)=>D_sig(13), xmit_data(12)=>D_sig(12), + xmit_data(11)=>D_sig(11), xmit_data(10)=>D_sig(10), + xmit_data(9)=>D_sig(9), xmit_data(8)=>D_sig(8), + xmit_data(7)=>D_sig(7), xmit_data(6)=>D_sig(6), + xmit_data(5)=>D_sig(5), xmit_data(4)=>D_sig(4), + xmit_data(3)=>D_sig(3), xmit_data(2)=>D_sig(2), + xmit_data(1)=>D_sig(1), xmit_data(0)=>D_sig(0), + xmit_empty_reset=>RESET_ACTIVE, + rcv_load=>open, + sck=>s_clock_sig, + ss_in_int=>open, + ss_n_int=>open, + xmit_empty=>open, + done=>done_sig, mosi=>mosi,rcv_data=>open, + --rcv_data(15)=>open, rcv_data(14)=>open, + --rcv_data(13)=>open, rcv_data(12)=>open, + --rcv_data(11)=>open, rcv_data(10)=>open, + --rcv_data(9)=>open, rcv_data(8)=>open, + --rcv_data(7)=>open, rcv_data(6)=>open, + --rcv_data(5)=>open, rcv_data(4)=>open, + --rcv_data(3)=>open, rcv_data(2)=>open, + --rcv_data(1)=>open, rcv_data(0)=>open, + rcv_full=>open,ss_n=>ss_n_sig + --ss_n(7)=>open, ss_n(6)=>open, ss_n(5)=>open, ss_n(4)=>open, + --ss_n(3)=>open, ss_n(2)=>open, ss_n(1)=>open, ss_n(0)=>cs_ld + ); + + wait_cnt: upcnt16 + port map( + full => full_sig, + clr => clr_wcnt_sig, + reset => reset_sig, + clk => clk_sig + ); + +end Behavioral; + Index: /firmware/FTU/old_design/FTU_top.vhd =================================================================== --- /firmware/FTU/old_design/FTU_top.vhd (revision 9841) +++ /firmware/FTU/old_design/FTU_top.vhd (revision 9841) @@ -0,0 +1,157 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 11:59:40 01/19/2010 +-- Design Name: +-- Module Name: FTU_top - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Top level entity of FACT FTU board +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +entity FTU_top is + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : in STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); +end FTU_top; + + +architecture Behavioral of FTU_top is + + component FTU_dac_dcm + port( + CLKIN_IN : IN STD_LOGIC; + RST_IN : IN STD_LOGIC; + CLKFX_OUT : OUT STD_LOGIC; + CLKIN_IBUFG_OUT : OUT STD_LOGIC; + LOCKED_OUT : OUT STD_LOGIC + ); + end component; + + component FTU_dac_control + port( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + miso : IN STD_LOGIC; + clr : OUT STD_LOGIC; + mosi : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + cs_ld : OUT STD_LOGIC + ); + end component; + + signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up + signal clk_5M_sig : STD_LOGIC; + + type FTU_top_StateType is (Init, Running, Reset); + signal FTU_top_State, FTU_top_NextState: FTU_top_StateType; + +begin + + Inst_FTU_dac_dcm : FTU_dac_dcm + port map( + CLKIN_IN => ext_clk, + RST_IN => reset_sig, + CLKFX_OUT => clk_5M_sig, + CLKIN_IBUFG_OUT => open, + LOCKED_OUT => open + ); + + Inst_FTU_dac_control : FTU_dac_control + port map( + clk => clk_5M_sig, + reset => reset_sig, + miso => '0', + clr => clr, + mosi => mosi, + sck => sck, + cs_ld => cs_ld + ); + + --FTU main state machine (two-process implementation) + + FTU_top_Registers: process (ext_clk) + begin + if Rising_edge(ext_clk) then + FTU_top_State <= FTU_top_NextState; + end if; + end process FTU_top_Registers; + + FTU_top_C_logic: process (FTU_top_State) + begin + FTU_top_NextState <= FTU_top_State; + case FTU_top_State is + when Init => + reset_sig <= '0'; + FTU_top_NextState <= Running; + when Running => + when Reset => + reset_sig <= '1'; + FTU_top_NextState <= Init; + end case; + end process FTU_top_C_logic; + +end Behavioral; + +--What is missing? +--UART +--registers (enables, DAC values etc.) +--rate counters +--main state machine for FTU: talks to DAC, reads counters, listens to UART + Index: /firmware/FTU/old_design/FTU_top_tb.vhd =================================================================== --- /firmware/FTU/old_design/FTU_top_tb.vhd (revision 9841) +++ /firmware/FTU/old_design/FTU_top_tb.vhd (revision 9841) @@ -0,0 +1,171 @@ +-------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 14:57:43 01/19/2010 +-- Design Name: +-- Module Name: /home/qweitzel/FPGA/FACT/FTU/source/FTU_top_tb.vhd +-- Project Name: FTUsim01 +-- Target Device: +-- Tool versions: +-- Description: Testbench for top level entity of FACT FTU board +-- +-- VHDL Test Bench Created by ISE for module: FTU_top +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity FTU_top_tb is +end FTU_top_tb; + +architecture behavior of FTU_top_tb is + + -- Component Declaration for the Unit Under Test (UUT) + + component FTU_top + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : in STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); + end component; + + --Inputs + signal ext_clk : STD_LOGIC := '0'; + signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); + signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); + signal patch_A_p : STD_LOGIC := '0'; + signal patch_A_n : STD_LOGIC := '0'; + signal patch_B_p : STD_LOGIC := '0'; + signal patch_B_n : STD_LOGIC := '0'; + signal patch_C_p : STD_LOGIC := '0'; + signal patch_C_n : STD_LOGIC := '0'; + signal patch_D_p : STD_LOGIC := '0'; + signal patch_D_n : STD_LOGIC := '0'; + signal trig_prim_p : STD_LOGIC := '0'; + signal trig_prim_n : STD_LOGIC := '0'; + signal rx : STD_LOGIC := '0'; + + --Outputs + signal enables_A : STD_LOGIC_VECTOR(8 downto 0); + signal enables_B : STD_LOGIC_VECTOR(8 downto 0); + signal enables_C : STD_LOGIC_VECTOR(8 downto 0); + signal enables_D : STD_LOGIC_VECTOR(8 downto 0); + signal clr : STD_LOGIC; + signal cs_ld : STD_LOGIC; + signal sck : STD_LOGIC; + signal mosi : STD_LOGIC; + signal tx : STD_LOGIC; + signal rx_en : STD_LOGIC; + signal tx_en : STD_LOGIC; + signal TP_A : STD_LOGIC_VECTOR(11 downto 0); + + -- Clock period definitions + constant ext_clk_period : TIME := 20 ns; + +begin + + -- Instantiate the Unit Under Test (UUT) + uut: FTU_top + port map( + ext_clk => ext_clk, + brd_add => brd_add, + brd_id => brd_id, + patch_A_p => patch_A_p, + patch_A_n => patch_A_n, + patch_B_p => patch_B_p, + patch_B_n => patch_B_n, + patch_C_p => patch_C_p, + patch_C_n => patch_C_n, + patch_D_p => patch_D_p, + patch_D_n => patch_D_n, + trig_prim_p => trig_prim_p, + trig_prim_n => trig_prim_n, + rx => rx, + rx_en => rx_en, + enables_A => enables_A, + enables_B => enables_B, + enables_C => enables_C, + enables_D => enables_D, + clr => clr, + cs_ld => cs_ld, + sck => sck, + mosi => mosi, + tx => tx, + tx_en => tx_en, + TP_A => TP_A + ); + + -- Clock process definitions + ext_clk_proc: process + begin + ext_clk <= '0'; + wait for ext_clk_period/2; + ext_clk <= '1'; + wait for ext_clk_period/2; + end process ext_clk_proc; + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + wait for 100ms; + + wait for ext_clk_period*10; + + -- insert stimulus here + + wait; + end process stim_proc; + +end; Index: /firmware/FTU/old_design/counter/upcnt16.vhd =================================================================== --- /firmware/FTU/old_design/counter/upcnt16.vhd (revision 9841) +++ /firmware/FTU/old_design/counter/upcnt16.vhd (revision 9841) @@ -0,0 +1,53 @@ +-- File: upcnt16.vhd +-- +-- Purpose: Up 16-bit counter +-- +-- Created: 7-25-00 ALS +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +entity upcnt16 is + port( + full : out STD_LOGIC; + clr : in STD_LOGIC; + reset : in STD_Logic; + clk : in STD_LOGIC + ); + +end upcnt16; + +architecture DEFINITION of upcnt16 is + + constant RESET_ACTIVE : std_logic := '0'; + constant Cnt_full : Unsigned (15 DOWNTO 0) :="1111111111111111"; + + signal q : Unsigned (15 DOWNTO 0); + +begin + + process(clk, reset, clr) + begin + + if ((reset OR clr)='1') then + q <= (others => '0');-- Clear output register + elsif (clk'event) and clk = '1' and (not(q = Cnt_full)) then-- On rising edge of clock count + q <= q + 1; + end if; + + end process; + + process(q) + begin + + if (q = Cnt_full) then + full <= '1'; + else + full <= '0'; + end if; + + end process; + +end DEFINITION; Index: /firmware/FTU/old_design/counter/upcnt5.vhd =================================================================== --- /firmware/FTU/old_design/counter/upcnt5.vhd (revision 9841) +++ /firmware/FTU/old_design/counter/upcnt5.vhd (revision 9841) @@ -0,0 +1,59 @@ +-- File: upcnt5.vhd +-- +-- Author: Jennifer Jenkins +-- Purpose: Up 5-bit counter +-- +-- Created: 5-3-99 JLJ +-- Revised: 6-15-99 ALS + +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +-- Modified by Patrick Vogler +-- 18th November 2009 +-- +-- Counter width extended from 4 to 5 bit in order to extend the SPI interface from +-- 8 to 16 bit word size +-- +-- Modifications are marked by: *Mod: +-- +-- Cleaned up by Quirin Weitzel +-- 21th January 2010 +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +entity upcnt5 is --*Mod: 4 to 5 bit + port( + cnt_en : in STD_LOGIC; -- Count enable -- Load line enable + clr : in STD_LOGIC; -- Active low clear + clk : in STD_LOGIC; -- Clock + qout : inout STD_LOGIC_VECTOR (4 downto 0) --*Mod: 4 to 5 bit + ); +end upcnt5; + +architecture DEFINITION of upcnt5 is + +constant RESET_ACTIVE : std_logic := '0'; + +signal q_int : UNSIGNED (4 downto 0); --*Mod: 4 to 5 bit + +begin + + process(clk, clr) + begin + -- Clear output register + if (clr = RESET_ACTIVE) then + q_int <= (others => '0'); + -- On falling edge of clock count + elsif (clk'event) and clk = '1' then + if cnt_en = '1' then + q_int <= q_int + 1; + end if; + end if; + end process; + + qout <= STD_LOGIC_VECTOR(q_int); + +end DEFINITION; Index: /firmware/FTU/old_design/ftu_board.ucf =================================================================== --- /firmware/FTU/old_design/ftu_board.ucf (revision 9841) +++ /firmware/FTU/old_design/ftu_board.ucf (revision 9841) @@ -0,0 +1,145 @@ +######################################################## +# FTU Board +# FACT Trigger Unit +# +# Pin location constraints +# +# by Patrick Vogler, Quirin Weitzel +# 01 July 2010 +######################################################## + + +#Clock +####################################################### +NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk + + +# RS-485 Interface +####################################################### +NET rx_en LOC = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver +NET tx_en LOC = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter +NET tx LOC = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM +NET rx LOC = R20 | IOSTANDARD=LVCMOS33; # 485_DI: serial data from FTM + + +# Board ID - inputs +# local board-ID "solder programmable" +####################################################### +NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0 +NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1 +NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2 +NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3 +NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4 +NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5 +NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6 +NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7 + + +# Board Addresses +# geographical slot address +####################################################### +NET brd_add<0> LOC = A15 | IOSTANDARD=LVCMOS33; # ADDR0 +NET brd_add<1> LOC = B15 | IOSTANDARD=LVCMOS33; # ADDR1 +NET brd_add<2> LOC = A16 | IOSTANDARD=LVCMOS33; # ADDR2 +NET brd_add<3> LOC = A17 | IOSTANDARD=LVCMOS33; # ADDR3 +NET brd_add<4> LOC = A18 | IOSTANDARD=LVCMOS33; # ADDR4 +NET brd_add<5> LOC = B18 | IOSTANDARD=LVCMOS33; # ADDR5 + + +# DAC SPI Interface +####################################################### +NET mosi LOC = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in +NET sck LOC = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC +NET cs_ld LOC = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC +NET clr LOC = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC + + +# Testpoints +###################################################### +# on Connector J5 +NET TP_A<0> LOC = B3 | IOSTANDARD=LVCMOS33; # TP0_0 +NET TP_A<1> LOC = A3 | IOSTANDARD=LVCMOS33; # TP1_0 +NET TP_A<2> LOC = A4 | IOSTANDARD=LVCMOS33; # TP2_0 +NET TP_A<3> LOC = B5 | IOSTANDARD=LVCMOS33; # TP2_0 + +# on Connector J6 +NET TP_A<4> LOC = A5 | IOSTANDARD=LVCMOS33; # TP4_0 +NET TP_A<5> LOC = A6 | IOSTANDARD=LVCMOS33; # TP5_0 +NET TP_A<6> LOC = B7 | IOSTANDARD=LVCMOS33; # TP6_0 +NET TP_A<7> LOC = A7 | IOSTANDARD=LVCMOS33; # TP7_0 + +# on Connector J7 +NET TP_A<8> LOC = B11 | IOSTANDARD=LVCMOS33; # TP8_0 +NET TP_A<9> LOC = A12 | IOSTANDARD=LVCMOS33; # TP9_0 +NET TP_A<10> LOC = B12 | IOSTANDARD=LVCMOS33; # TP10_0 +NET TP_A<11> LOC = A14 | IOSTANDARD=LVCMOS33; # TP11_0 + + +# Rate counter LVDS Inputs +###################################################### +# logic signal from first trigger patch +NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P +NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N + +# logic signal from second trigger patch +NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P +NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N + +# logic signal from third trigger patch +NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P +NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N + +# logic signal from fourth trigger patch +NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P +NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N + +#The Trigger Primitive: logic signal from n-out-of-4 circuit +NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+ +NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P- + + +# Enables +###################################################### +# Patch 0 +NET enables_A<0> LOC = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 +NET enables_A<1> LOC = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1 +NET enables_A<2> LOC = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2 +NET enables_A<3> LOC = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3 +NET enables_A<4> LOC = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4 +NET enables_A<5> LOC = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5 +NET enables_A<6> LOC = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6 +NET enables_A<7> LOC = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7 +NET enables_A<8> LOC = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8 + +## Patch 1 +NET enables_B<0> LOC = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0 +NET enables_B<1> LOC = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1 +NET enables_B<2> LOC = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2 +NET enables_B<3> LOC = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3 +NET enables_B<4> LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4 +NET enables_B<5> LOC = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5 +NET enables_B<6> LOC = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6 +NET enables_B<7> LOC = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7 +NET enables_B<8> LOC = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8 + +# Patch 2 +NET enables_C<0> LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0 +NET enables_C<1> LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1 +NET enables_C<2> LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2 +NET enables_C<3> LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3 +NET enables_C<4> LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4 +NET enables_C<5> LOC = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5 +NET enables_C<6> LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6 +NET enables_C<7> LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7 +NET enables_C<8> LOC = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8 + +# Patch 3 +NET enables_D<0> LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<1> LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<2> LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<3> LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<4> LOC = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<5> LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<6> LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<7> LOC = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<8> LOC = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 Index: /firmware/FTU/old_design/ip_cores/FTU_dac_dcm.vhd =================================================================== --- /firmware/FTU/old_design/ip_cores/FTU_dac_dcm.vhd (revision 9841) +++ /firmware/FTU/old_design/ip_cores/FTU_dac_dcm.vhd (revision 9841) @@ -0,0 +1,90 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.1 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTU_dac_dcm.vhd +-- /___/ /\ Timestamp : 01/20/2010 16:36:17 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /home/qweitzel/FPGA/FACT/FTU/source/ip_cores/FTU_dac_dcm.xaw /home/qweitzel/FPGA/FACT/FTU/source/ip_cores/FTU_dac_dcm +--Design Name: FTU_dac_dcm +--Device: xc3s400an-4fgg400 +-- +-- Module FTU_dac_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 6.54 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTU_dac_dcm is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end FTU_dac_dcm; + +architecture BEHAVIORAL of FTU_dac_dcm is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 20, + CLKFX_MULTIPLY => 2, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: /firmware/FTU/old_design/ip_cores/FTU_dac_dcm_arwz.ucf =================================================================== --- /firmware/FTU/old_design/ip_cores/FTU_dac_dcm_arwz.ucf (revision 9841) +++ /firmware/FTU/old_design/ip_cores/FTU_dac_dcm_arwz.ucf (revision 9841) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = NONE; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 20; +INST DCM_SP_INST CLKFX_MULTIPLY = 2; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 20.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: /firmware/FTU/old_design/spi_interface/sck_logic_16.vhd =================================================================== --- /firmware/FTU/old_design/spi_interface/sck_logic_16.vhd (revision 9841) +++ /firmware/FTU/old_design/spi_interface/sck_logic_16.vhd (revision 9841) @@ -0,0 +1,233 @@ +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +-- File: sck_logic_16.vhd +-- +-- +-- Original file: sck_logic.vhd +-- + +-- Created: 8-23-00 ALS +-- This file generates an internal SCK by dividing the system clock as determined by CLKDIV. +-- This internal SCK has a CPHA=1 relationship to data and is used to clock the internal SPI +-- shift register. This internal SCK is used to generate the desired output SCK as determined +-- by CPHA and CPOL in the control register. The SCK output to the SPI bus is output only when +-- the slave select signals are asserted, but the internal SCK runs continuously. +-- +-- Revised: 8-28-00 ALS +-- Revised: 9-11-00 ALS +-- Revised: 10-17-00 ALS + +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +-- Modified from 8 to 16 bit word size by Patrick Vogler +-- 18th November 2009 +-- +-- Modifications are marked by: *Mod: +-- +-- Cleaned up by Quirin Weitzel +-- 21th January 2010 +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +entity sck_logic is + port( + -- internal uC interface signals + clkdiv : in std_logic_vector(1 downto 0); -- sets the clock divisor for sck clock + cpha : in std_logic; -- sets clock phase for output sck clock + cpol : in std_logic; -- sets clock polarity for output sck clock + + -- internal spi interface signals + clk0_mask : in std_logic; -- clock mask for sck when cpha=0 + clk1_mask : in std_logic; -- clock mask for sck when cpha=1 + sck_1 : inout std_logic; -- internal sck created from dividing system clock + sck_int_re : out std_logic; -- rising edge of internal sck + sck_int_fe : out std_logic; -- falling edge of internal sck + sck_re : out std_logic; -- rising edge of external sck + sck_fe : out std_logic; -- falling edge of external sck + ss_in_int : in std_logic; -- another master is on the bus + + -- external spi interface signals + sck : inout std_logic; -- sck as determined by cpha, cpol, and clkdiv + + -- clock and reset + reset : in std_logic; -- active high reset + clk : in std_logic -- clock + + ); + +end sck_logic; + +architecture DEFINITION of sck_logic is + +--**************************** Constants *************************************** + +constant RESET_ACTIVE : std_logic := '0'; + +--**************************** Signals *************************************** + +signal clk_cnt : STD_LOGIC_VECTOR(4 downto 0); -- clock divider output +signal clk_cnt_en : STD_LOGIC; -- count enable for clock divider +signal clk_cnt_rst : STD_LOGIC; -- clock count reset + + +signal sck_int_d1 : STD_LOGIC; -- sck_int delayed one clock for edge detection +signal sck_int : STD_LOGIC; -- version of sck when CPHA=1 +signal sck_0 : STD_LOGIC; -- version of sck when CPHA=0 +signal sck_out : STD_LOGIC; -- sck to be output if SS_IN_INT is not asserted +signal sck_d1 : std_logic; -- output sck delayed one clock for edge detection + + +--**************************** Component Definitions ******************************** +-- 5-bit counter for clock divider +component upcnt5 + port( + cnt_en : in STD_LOGIC; -- Count enable + clr : in STD_LOGIC; -- Active high clear + clk : in STD_LOGIC; -- Clock + qout : inout STD_LOGIC_VECTOR (4 downto 0) + ); + +end component; + +begin + + --************************** Clock Divider Instantiation ******************************** + CLK_DIVDR : upcnt5 + port map( + cnt_en => clk_cnt_en, + clr => clk_cnt_rst, + clk => clk, + qout => clk_cnt + ); + -- This counter is always enabled, can't instantiate the counter with a literal + clk_cnt_en <= '1'; + + -- Clock counter is reset whenever reset is active and ss_in_int is asserted + clk_cnt_rst <= RESET_ACTIVE when reset = RESET_ACTIVE or ss_in_int = '0' + else not(RESET_ACTIVE); + + --************************** Internal SCK Generation *************************************** + -- SCK when CPHA=1 is simply the output of the clock divider determined by the CLK_DIV bits + -- SCK_INT is based off the CPHA=1 waveforms and is used as the internal SCK + -- SCK_INT is used to clock the SPI shift register, therefore, it runs before and after SS_N + -- is asserted + -- SCK_1 is SCK_INT when clk1_mask = 1. The clock mask blocks SCK_INT edges that are before + -- and after SS_N + sck_int_process: process (clk,reset) + begin + if reset = RESET_ACTIVE then + sck_int <= '0'; + elsif clk'event and clk = '1' then + -- determine clock divider output based on control register + case clkdiv is + when "00" => + sck_int <= clk_cnt(1); + when "01" => + sck_int <= clk_cnt(2); + when "10" => + sck_int <= clk_cnt(3); + when "11" => + sck_int <= clk_cnt(4); + when others => -- error in register + sck_int <= '0'; + end case; + end if; + end process; + + sck_1 <= sck_int and clk1_mask; + + -- Detect rising and falling edges of SCK_1 to use as state transition + sck_intedge_process: process(clk, reset) + begin + if reset = RESET_ACTIVE then + sck_int_d1 <= '0'; + elsif clk'event and clk = '1' then + sck_int_d1 <= sck_int; + end if; + end process; + + sck_int_re <= '1' when sck_int = '1' and sck_int_d1 = '0' + else '0'; + sck_int_fe <= '1' when sck_int = '0' and sck_int_d1 = '1' + else '0'; + + -- SCK when CPHA=0 is out of phase with internal SCK - therefore its toggle needs to be delayed + -- by the signal clk_mask and then its simply an inversion of the counter bit + + sck_0_process: process (clk, reset) + begin + if reset = RESET_ACTIVE then + sck_0 <= '0'; + elsif clk'event and clk = '1' then + if clk0_mask = '0' then + sck_0 <= '0'; + else + case clkdiv is + when "00" => + sck_0 <= not(clk_cnt(1)); + when "01" => + sck_0 <= not(clk_cnt(2)); + when "10" => + sck_0 <= not(clk_cnt(3)); + when "11" => + sck_0 <= not(clk_cnt(4)); + when others => -- error in register + sck_0 <= '0'; + end case; + end if; + end if; + end process; + + --************************** External SCK Generation ********************************** + -- This process outputs SCK based on the CPHA and CPOL parameters set in the control register + sck_out_process: process(clk, reset, cpol) + variable temp: std_logic_vector(1 downto 0); + begin + if reset = RESET_ACTIVE then + sck_out <= '0'; + elsif clk'event and clk = '1' then + temp := cpol & cpha; + case temp is + when "00" => -- polarity = 0, phase = 0 + -- sck = sck_0 + sck_out <= sck_0; + when "01" => -- polarity= 0, phase = 1 + -- sck = sck_1 + sck_out <= sck_1; + when "10" => -- polarity = 1, phase = 0 + -- sck = not(sck_0) + sck_out <= not(sck_0); + when "11" => -- polarity = 1, phase = 1 + -- sck = not(sck_1) + sck_out <= not(sck_1); + when others => -- default to sck_0 + sck_out <= sck_0; + end case; + end if; + end process; + + -- Detect rising and falling edges of SCK_OUT to use to end cycle correctly + -- and to keep RCV_LOAD signal 1 system clock in width + SCK_DELAY_PROCESS: process(clk, reset) + begin + if reset = RESET_ACTIVE then + sck_d1 <= '0'; + elsif clk'event and clk = '1' then + sck_d1 <= sck_out; + end if; + end process; + + sck_re <= '1' when sck_out = '1' and sck_d1 = '0' + else '0'; + sck_fe <= '1' when sck_out = '0' and sck_d1 = '1' + else '0'; + + -- The SCK output is 3-stated if the SS_IN_INT signal is asserted indicating that another + -- master is on the bus + sck <= sck_out when ss_in_int = '1' + else 'Z'; + +end DEFINITION; Index: /firmware/FTU/old_design/spi_interface/spi_control_sm_16.vhd =================================================================== --- /firmware/FTU/old_design/spi_interface/spi_control_sm_16.vhd (revision 9841) +++ /firmware/FTU/old_design/spi_interface/spi_control_sm_16.vhd (revision 9841) @@ -0,0 +1,414 @@ +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +-- File: spi_control_sm_16.vhd +-- +-- +-- Original file: spi_control_sm.vhd +-- +-- Created: 8-23-00 ALS +-- This file contains the overall control of the SPI interface. It generates the slave +-- select signals and the masks so that the SCK signals output to the SPI bus align properly +-- with the data. It generates the control signals to the shift register and the receive +-- data register. +-- +-- This SPI interface operates on bytes of data. When the START signal from the uC is +-- asserted the byte-wide data in the SPI transmit register is transmitted on the SPI bus. +-- When this transfer is complete, the BUSY signal is negated and the START signal is +-- sampled. If the START signal is still asserted indicating that the uC has put new +-- data in the SPI transmit register, the data in the transmit register will be transmitted. +-- Each byte of data received from the SPI bus is captured in the receive register.The uC can +-- read this data once the BUSY signal has negated. +-- +-- Revised: 9-6-00 ALS +-- Revised: 9-12-00 ALS +-- Revised: 10-17-00 ALS +-- Revised: 10-19-00 ALS +-- Revised: 10-27-00 ALS +-- Revised: 12-12-02 JRH + +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +-- Modified from 8 to 16 bit word size by Patrick Vogler +-- 18th November 2009 +-- +-- Modifications are marked by: *Mod: +-- +-- Cleaned up by Quirin Weitzel +-- 21th January 2010 +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +entity spi_control_sm is + port( + -- internal uC interface signals + start : in std_logic; -- start transfer + done : out std_logic; -- byte transfer is complete + rcv_load : in std_logic; -- load control signal to spi receive register + ss_mask_reg : in std_logic_vector(7 downto 0); -- uc slave select register, Caution! No modification, not word size + ss_in_int : inout std_logic; -- internal sampled version of ss_in_n needed by uc to generate an interrupt + xmit_empty : inout std_logic; -- flag indicating that spitr is empty + xmit_empty_reset : in std_logic; -- xmit empty flag reset when spitr is written + rcv_full : out std_logic; -- flag indicating that spirr has new data + rcv_full_reset : in std_logic; -- rcv full flag reset when spirr is read + cpha : in std_logic; -- clock phase from uc + cpol : in std_logic; -- clock polarity from uc + + -- spi interface signals + ss_n : out std_logic_vector(7 downto 0); -- slave select signals Caution! NO modification slave select, not word size + ss_in_n : in std_logic; -- input slave select indicating master bus contention + ss_n_int : inout std_logic; -- internal ss_n that is masked with slave select register + + -- internal interface signals + sck_int : in std_logic; -- internal version of sck with cpha=1 + sck_int_re : in std_logic; -- indicates rising edge on internal sck + sck_int_fe : in std_logic; -- indicates falling edge on internal sck + sck_re : in std_logic; -- indicates rising edge on external sck + sck_fe : in std_logic; -- indicates falling edge on external sck + xmit_shift : out std_logic; -- shift control signal to spi xmit shift register + xmit_load : inout std_logic; -- load control signal to the spi xmit shift register + clk1_mask : out std_logic; -- masks cpha=1 version of sck + clk0_mask : out std_logic; -- masks cpha=0 version of sck + + -- clock and reset + reset : in std_logic; -- active low reset + clk : in std_logic -- clock + ); +end spi_control_sm; + +architecture DEFINITION of spi_control_sm is + +--**************************** Constants *************************************** + +constant RESET_ACTIVE : std_logic := '0'; + +constant SIXTEEN : std_logic_vector(4 downto 0) := "10000"; -- *Mod: width changed from 4 to 5 bits, Caution! bit counter + +--**************************** Signals *************************************** + +type SPI_STATE_TYPE is (IDLE, ASSERT_SSN1, ASSERT_SSN2, UNMASK_SCK, XFER_BIT, + ASSERT_DONE, CHK_START, MASK_SCK, HOLD_SSN1, HOLD_SSN2, + NEGATE_SSN); + +signal spi_state, next_spi_state : SPI_STATE_TYPE; + +signal bit_cnt : STD_LOGIC_VECTOR(4 downto 0); -- Caution! bit counter output *Mod: width changed from 4 to 5 bits +signal bit_cnt_en : STD_LOGIC; -- count enable for bit counter +signal bit_cnt_rst : STD_LOGIC; -- reset for bit counter from SPI control state machine +signal bit_cnt_reset : STD_LOGIC; -- reset to bit counter that includes SS_IN_INT +signal ss_in_neg : STD_LOGIC; -- SS_IN_N sampled with rising edge of clk +signal ss_in_pos : STD_LOGIC; -- SS_IN_N sampled with negative edge of clk +signal ss_n_out : STD_LOGIC_VECTOR(7 downto 0); -- output SS_N that are 3-stated if SS_IN_INT is asserted indicating another master slave select, + -- do not change width + +--**************************** Component Definitions ******************************** +-- 5-bit counter for bit counter +component upcnt5 --*Mod: 5 instead of 4 bit counter + port( + cnt_en : in STD_LOGIC; -- Count enable + clr : in STD_LOGIC; -- Active high clear + clk : in STD_LOGIC; -- Clock + qout : inout STD_LOGIC_VECTOR (4 downto 0) -- *Mod: 5 instead of 4 bit counter + ); +end component; + +begin + + --************************** Bit Counter Instantiation ******************************** + BIT_CNTR : upcnt5 --*Mod: 5 instead of 4 bit counter + port map( + cnt_en => bit_cnt_en, + clr => bit_cnt_reset, + clk => sck_int, + qout => bit_cnt + ); + + --************************** SS_IN_N Input synchronization ******************************* + -- When the SS_IN_N input is asserted, it indicates that there is another master on the bus + -- that has selected this master as a slave. When this signal asserts, the SPI master needs + -- to reset and tristate outputs. Therefore, the SS_IN_N input should be synchronized with the + -- system clock to prevent glitches on this signal from reseting the SPI master. The proces + -- below first samples SS_IN_N with the rising edge of the system clock and the falling edge + -- of the system clock. If both of these samples show that the signal is asserted, then the + -- internal SS_IN_INT signal will assert. SS_IN_INT is passed to the uC logic to generate an + -- interrupt if interrupts have been enabled. It is also passed to the SCK logic and the + -- SPI Xmit shift register to tri-state the SCK and MOSI outputs. + + ss_in_rising: process(clk, reset) + begin + if reset = RESET_ACTIVE then + ss_in_pos <= '1'; + elsif clk'event and clk = '1' then + ss_in_pos <= ss_in_n; + end if; + end process; + + ss_in_falling: process (clk, reset) + begin + if reset = RESET_ACTIVE then + ss_in_neg <= '1'; + elsif clk'event and clk = '0' then + ss_in_neg <= ss_in_n; + end if; + end process; + + ss_in_sample: process(clk,reset) + begin + if reset = RESET_ACTIVE then + ss_in_int <= '1'; + elsif clk'event and clk = '1' then + if ss_in_pos = '0' and ss_in_neg = '0' then + ss_in_int <= '0'; + else + ss_in_int <= '1'; + end if; + end if; + end process; + + --************************** Bit Counter reset *************************************** + -- The bit counter needs to be reset when the reset signal is asserted from the SPI control + -- state machine is asserted and when SS_IN_INT is asserted + -- is asserted + bit_cnt_reset <= RESET_ACTIVE when bit_cnt_rst = RESET_ACTIVE or ss_in_int = '0' + else not(RESET_ACTIVE); + + --************************** SPI Control State Machine ******************************* + -- Register process registers next state signals + -- Return to IDLE state whenever SS_IN_INT is asserted + + spi_sm_reg:process(clk, reset, ss_in_int) + begin + -- Set state to IDLE upon reset + if (reset = RESET_ACTIVE or ss_in_int = '0') then + spi_state <= IDLE; + elsif clk'event and clk = '1' then + spi_state <= next_spi_state; + end if; + end process; + + -- Combinatorial process determines next state logic + + spi_sm_comb: process(spi_state, start,bit_cnt, sck_re, sck_fe, sck_int_re, sck_int_fe, + xmit_empty, cpha, cpol) + + begin + + -- set defaults + clk0_mask <= '0'; + clk1_mask <= '0'; + bit_cnt_en <= '0'; + bit_cnt_rst <= RESET_ACTIVE; + next_spi_state <= spi_state; + done <= '0'; + xmit_shift <= '0'; + xmit_load <= '0'; + + case spi_state is + + --********************* IDLE State ***************** + when IDLE => + if start = '1' and xmit_empty = '0' then + next_spi_state <= ASSERT_SSN1; + end if; + + --********************* ASSERT_SSN1 State ***************** + when ASSERT_SSN1 => + -- this state asserts SS_N and waits for first edge of SCK_INT + -- SS_N must be asserted ~1 SCK before SCK is output from chip + if sck_int_re = '1' then + next_spi_state <= ASSERT_SSN2; + end if; + + --********************* ASSERT_SSN2 State ***************** + when ASSERT_SSN2 => + -- this state asserts SS_N and waits for next edge of SCK_INT + -- SS_N must be asserted ~1 SCK before SCK is output from chip + if sck_int_fe = '1' then + next_spi_state <= UNMASK_SCK; + end if; + + --********************* UNMASK_SCK State ***************** + when UNMASK_SCK => + bit_cnt_rst <= not(RESET_ACTIVE); -- release bit counter from reset + bit_cnt_en <= '1'; -- enable bit counter + clk1_mask <= '1'; -- unmask sck_1 + xmit_load <= '1'; -- load SPI shift register + + if sck_int_re = '1' then + -- first rising edge of CPHA=1 clock with SS_N asserted + -- transition to XFER_BIT state and unmask CPHA=0 clk + next_spi_state <= XFER_BIT; + end if; + + --********************* XFER_BIT State ***************** + when XFER_BIT => + clk0_mask <= '1'; -- unmask CPHA=0 clock + clk1_mask <= '1'; -- unmask CPHA=1 clock + bit_cnt_en <= '1'; -- enable bit counter + bit_cnt_rst <= not(RESET_ACTIVE); -- release bit counter from reset + + xmit_shift <= '1'; -- enable shifting of SPI shift registers + + if bit_cnt = SIXTEEN then -- *Mod: SIXTEEN instead of EIGHT bit + -- all 16 bits have transferred + next_spi_state <= ASSERT_DONE; + end if; + + --********************* ASSERT_DONE State ***************** + when ASSERT_DONE => + -- this state asserts done to the uC so that new data + -- can be written into the transmit register or data + -- can be read from the receive register + done <= '1'; + clk0_mask <= '1'; + clk1_mask <= '1'; + xmit_shift <= '1'; + if sck_int_fe = '1' then + next_spi_state <= CHK_START; + end if; + + --********************* CHK_START State ***************** + when CHK_START => + clk0_mask <= '1'; + clk1_mask <= '1'; + done <= '1'; + bit_cnt_en <= '1'; + bit_cnt_rst <= not(RESET_ACTIVE); -- release bit counter from reset + if cpha = '0' then + -- when CPHA = 0, have to negate slave select and then + -- re-assert it. Need to wait for last SCK pulse to complete + -- and mask SCK before negating SS_N. + if (sck_re = '1' and cpol = '1') or (sck_fe = '1' and cpol = '0') then + clk0_mask <= '0'; + clk1_mask <= '0'; + next_spi_state <= MASK_SCK; + end if; + elsif start = '1' and xmit_empty = '0' then + -- CPHA=1 and have more data to transfer, go back to + -- UNMASK_CK state + clk1_mask <= '1'; + xmit_load <= '1'; -- load SPI shift register + next_spi_state <= UNMASK_SCK; + else + -- CPHA=1 and no more data to transfer + -- wait for last SCKs and then mask SCK + if (sck_re = '1' and cpol = '1') or (sck_fe = '1' and cpol = '0') then + clk0_mask <= '0'; + clk1_mask <= '0'; + next_spi_state <= MASK_SCK; + end if; + clk0_mask <= '0'; + clk1_mask <= '1'; + end if; + + --********************* MASK_SCK State ***************** + when MASK_SCK => + done <= '1'; + -- wait for next internal SCK edge + -- to help provide SS_N hold time + if sck_int_fe <= '1' then + next_spi_state <= HOLD_SSN1; + end if; + + --********************* HOLD_SSN1 State ***************** + when HOLD_SSN1 => + -- This state waits for another SCK edge + -- to provide SS_N hold time + if sck_int_fe = '1' then + next_spi_state <= HOLD_SSN2; + end if; + + --********************* HOLD_SSN2 State ***************** + when HOLD_SSN2 => + -- This state waits for another SCK edge + -- to provide SS_N hold time + if sck_int_fe = '1' then + next_spi_state <= NEGATE_SSN; + end if; + + --********************* NEGATE_SSN State ***************** + when NEGATE_SSN => + -- SS_N should negate for an entire SCK + -- This state waits for an SCK edge + if sck_int_fe = '1' then + next_spi_state <= IDLE; + end if; + + --********************* Default State ***************** + when others => + next_spi_state <= IDLE; + end case; + end process; + + -- assert slave select when spi_state machine is in any state but IDLE or NEGATE_SSN + ss_n_int <= '1' when (spi_state = IDLE or spi_state = NEGATE_SSN) else '0'; + + --xmit_load <= '1' when (spi_state = UNMASK_SCK) else '0'; + + + --************************** Register Full/Empty flags ******************************* + -- When data is loaded into the SPI transmit shift register from SPITR, the XMIT_EMPTY + -- flag is set, indicating to the uC that new data can be written into SPITR. Note that + -- the SPI transmit shift register is clocked from SCK, therefore, this flag is clocked + -- from SCK. + mt_flag_process: process (sck_int, xmit_empty_reset, reset) + begin + if xmit_empty_reset = RESET_ACTIVE or reset = RESET_ACTIVE then + xmit_empty <= '0'; + elsif sck_int'event and sck_int = '1' then + if xmit_empty_reset = RESET_ACTIVE then + -- reset empty flag because uC has written data to SPITR + xmit_empty <= '0'; + elsif xmit_load = '1' then + -- set empty flag because SPITR data has been loaded into + -- SPI transmit shift register + xmit_empty <= '1'; + end if; + end if; + end process; + + -- When data is loaded into SPIRR, the RCV_FULL flag is set, indicating to the uC that + -- new data from the SPI bus has been received. + full_flag_process: process (reset, clk) + begin + if reset = RESET_ACTIVE then + rcv_full <= '0'; + elsif clk'event and clk = '1' then + if rcv_full_reset = RESET_ACTIVE then + -- reset the full flag because the spirr has been read + rcv_full <= '0'; + elsif rcv_load = '1' then + -- set the full flag because data has been loaded in spirr + rcv_full <= '1'; + end if; + end if; + end process; + + --************************** Slave Selects ******************************* + -- The internal slave select signal generated by the SPI Control state machine + -- is masked by the uC slave select register. The SS_N outputs are clocked on the + -- falling edge of the system clock. + ss_n_process: process ( reset, clk) + variable i : integer; + + begin + if reset = RESET_ACTIVE then + ss_n_out <= (others => '1'); + elsif clk'event and clk = '0' then + for i in 0 to 7 loop + if ss_n_int = '0' and ss_mask_reg (i) = '1' then + ss_n_out(i) <= '0'; -- assert corresponding slave select + else + ss_n_out(i) <= '1'; + end if; + end loop; + end if; + end process; + + -- Slave selects are 3-stated if SS_IN_INT is asserted + ss_n <= ss_n_out when ss_in_int = '1' + else (others => 'Z'); + +end DEFINITION; Index: /firmware/FTU/old_design/spi_interface/spi_interface_16.vhd =================================================================== --- /firmware/FTU/old_design/spi_interface/spi_interface_16.vhd (revision 9841) +++ /firmware/FTU/old_design/spi_interface/spi_interface_16.vhd (revision 9841) @@ -0,0 +1,226 @@ +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +-- File: spi_interface_16.vhd +-- +-- +-- Original file: spi_interface.vhd +-- +-- Created: 12-12-02 JRH +-- This file contains the interconnect structure of the SPI interface portion of +-- the SPI Master design. It was originally created in schematic form, but was +-- converted to VHDL from the VHF file generated by the ECS tool. +-- +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +-- Modified from 8 to 16 bit word size by Patrick Vogler +-- 18th November 2009 +-- +-- Modifications are marked by: *Mod: +-- +-- Cleaned up by Quirin Weitzel +-- 20th January 2010 +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +library IEEE; +library UNISIM; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use UNISIM.Vcomponents.ALL; + +entity spi_interface_16 is + port( + clk : IN STD_LOGIC; + clkdiv : IN STD_LOGIC_VECTOR (1 downto 0); + cpha : IN STD_LOGIC; + cpol : IN STD_LOGIC; + miso : IN STD_LOGIC; + rcv_cpol : IN STD_LOGIC; + rcv_full_reset : IN STD_LOGIC; + reset : IN STD_LOGIC; + ss_in_n : IN STD_LOGIC; + ss_mask_reg : IN STD_LOGIC_VECTOR (7 downto 0);-- slave select signals, caution! NO modification, slave select, not word size + start : IN STD_LOGIC; + xmit_data : IN STD_LOGIC_VECTOR (15 downto 0);-- *Mod: 15 instead of 7, transmit data word extended from 8 to 16 bit + xmit_empty_reset : IN STD_LOGIC; + done : OUT STD_LOGIC; + mosi : OUT STD_LOGIC; + rcv_data : OUT STD_LOGIC_VECTOR (15 downto 0);-- *Mod: 15 instead of 7, recieve data word extended from 8 to 16 bit + rcv_full : OUT STD_LOGIC; + ss_n : OUT STD_LOGIC_VECTOR (7 downto 0);-- slave select signals, caution! NO modification, slave select, not word size + rcv_load : INOUT STD_LOGIC; + sck : INOUT STD_LOGIC; + ss_in_int : INOUT STD_LOGIC; + ss_n_int : INOUT STD_LOGIC; + xmit_empty : INOUT STD_LOGIC + ); +end spi_interface_16; + +ARCHITECTURE SCHEMATIC OF spi_interface_16 IS + + SIGNAL clk0_mask : STD_LOGIC; + SIGNAL clk1_mask : STD_LOGIC; + SIGNAL sck_1 : STD_LOGIC; + SIGNAL sck_fe : STD_LOGIC; + SIGNAL sck_int_fe : STD_LOGIC; + SIGNAL sck_int_re : STD_LOGIC; + SIGNAL sck_re : STD_LOGIC; + SIGNAL vcc : STD_LOGIC; + SIGNAL xmit_load : STD_LOGIC; + SIGNAL xmit_shift : STD_LOGIC; + + ATTRIBUTE fpga_dont_touch : STRING; + ATTRIBUTE fpga_dont_touch OF XLXI_9 : LABEL IS "true"; + + COMPONENT sck_logic + PORT( + clk : IN STD_LOGIC; + clk0_mask : IN STD_LOGIC; + clk1_mask : IN STD_LOGIC; + clkdiv : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + cpha : IN STD_LOGIC; + cpol : IN STD_LOGIC; + reset : IN STD_LOGIC; + ss_in_int : IN STD_LOGIC; + sck : INOUT STD_LOGIC; + sck_1 : INOUT STD_LOGIC; + sck_fe : OUT STD_LOGIC; + sck_int_fe : OUT STD_LOGIC; + sck_int_re : OUT STD_LOGIC; + sck_re : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT spi_control_sm + PORT( + clk : IN STD_LOGIC; + cpha : IN STD_LOGIC; + cpol : IN STD_LOGIC; + rcv_full_reset : IN STD_LOGIC; + rcv_load : IN STD_LOGIC; + reset : IN STD_LOGIC; + sck_fe : IN STD_LOGIC; + sck_int : IN STD_LOGIC; + sck_int_fe : IN STD_LOGIC; + sck_int_re : IN STD_LOGIC; + sck_re : IN STD_LOGIC; + ss_in_n : IN STD_LOGIC; + ss_mask_reg : IN STD_LOGIC_VECTOR (7 DOWNTO 0);-- slave select signals, caution, NO modification, slave select, not word size + start : IN STD_LOGIC; + xmit_empty_reset : IN STD_LOGIC; + ss_in_int : INOUT STD_LOGIC; + ss_n_int : INOUT STD_LOGIC; + xmit_empty : INOUT STD_LOGIC; + xmit_load : INOUT STD_LOGIC; + clk0_mask : OUT STD_LOGIC; + clk1_mask : OUT STD_LOGIC; + done : OUT STD_LOGIC; + rcv_full : OUT STD_LOGIC; + ss_n : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- slave select signals, caution! NO modification slave select, not word size + xmit_shift : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT spi_rcv_shift_reg + PORT( + cpol : IN STD_LOGIC; + miso : IN STD_LOGIC; + rcv_cpol : IN STD_LOGIC; + reset : IN STD_LOGIC; + sck_fe : IN STD_LOGIC; + sck_re : IN STD_LOGIC; + sclk : IN STD_LOGIC; + shift_en : IN STD_LOGIC; + ss_in_int : IN STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);-- *Mod: 15 instead of 7, recieve data word extended from 8 to 16 bit + rcv_load : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT spi_xmit_shift_reg + PORT( + data_in : IN STD_LOGIC_VECTOR (15 DOWNTO 0);-- *Mod: 15 instead of 7, transmit data word extended from 8 to 16 bit + data_ld : IN STD_LOGIC; + reset : IN STD_LOGIC; + sclk : IN STD_LOGIC; + shift_en : IN STD_LOGIC; + shift_in : IN STD_LOGIC; + ss_in_int : IN STD_LOGIC; + sys_clk : IN STD_LOGIC; + mosi : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + + XLXI_9 : NAND2B1 + PORT MAP( + I0=>xmit_shift, I1=>xmit_shift, O=>vcc + ); + + SCK_GEN : sck_logic + PORT MAP( + clk=>clk, clk0_mask=>clk0_mask, clk1_mask=>clk1_mask, + clkdiv(1)=>clkdiv(1), clkdiv(0)=>clkdiv(0), cpha=>cpha, cpol=>cpol, + reset=>reset, ss_in_int=>ss_in_int, sck=>sck, sck_1=>sck_1, + sck_fe=>sck_fe, sck_int_fe=>sck_int_fe, sck_int_re=>sck_int_re, + sck_re=>sck_re + ); + + spi_ctrl_sm : spi_control_sm + PORT MAP( + clk=>clk, cpha=>cpha, cpol=>cpol, + rcv_full_reset=>rcv_full_reset, rcv_load=>rcv_load, reset=>reset, + sck_fe=>sck_fe, sck_int=>sck_1, sck_int_fe=>sck_int_fe, + sck_int_re=>sck_int_re, sck_re=>sck_re, ss_in_n=>ss_in_n, + ss_mask_reg(7)=>ss_mask_reg(7), ss_mask_reg(6)=>ss_mask_reg(6), + ss_mask_reg(5)=>ss_mask_reg(5), ss_mask_reg(4)=>ss_mask_reg(4), + ss_mask_reg(3)=>ss_mask_reg(3), ss_mask_reg(2)=>ss_mask_reg(2), + ss_mask_reg(1)=>ss_mask_reg(1), ss_mask_reg(0)=>ss_mask_reg(0), + start=>start, xmit_empty_reset=>xmit_empty_reset, ss_in_int=>ss_in_int, + ss_n_int=>ss_n_int, xmit_empty=>xmit_empty, xmit_load=>xmit_load, + clk0_mask=>clk0_mask, clk1_mask=>clk1_mask, done=>done, + rcv_full=>rcv_full, ss_n(7)=>ss_n(7), ss_n(6)=>ss_n(6), ss_n(5)=>ss_n(5), + ss_n(4)=>ss_n(4), ss_n(3)=>ss_n(3), ss_n(2)=>ss_n(2), ss_n(1)=>ss_n(1), + ss_n(0)=>ss_n(0), xmit_shift=>xmit_shift + ); + +-------------------------------------------------------------------------- +-- *Mod: recieve data word extended from 8 to 16 bit in this block ------ + rcv_shift_reg : spi_rcv_shift_reg + PORT MAP( + cpol=>cpol, miso=>miso, rcv_cpol=>rcv_cpol, reset=>reset, + sck_fe=>sck_fe, sck_re=>sck_re, sclk=>sck, shift_en=>ss_n_int, + ss_in_int=>ss_in_int, + data_out(15)=>rcv_data(15), data_out(14)=>rcv_data(14), + data_out(13)=>rcv_data(13), data_out(12)=>rcv_data(12), + data_out(11)=>rcv_data(11), data_out(10)=>rcv_data(10), + data_out(9)=>rcv_data(9), data_out(8)=>rcv_data(8), + data_out(7)=>rcv_data(7), data_out(6)=>rcv_data(6), + data_out(5)=>rcv_data(5), data_out(4)=>rcv_data(4), + data_out(3)=>rcv_data(3), data_out(2)=>rcv_data(2), + data_out(1)=>rcv_data(1), data_out(0)=>rcv_data(0), + rcv_load=>rcv_load + ); +-- *Mod: recieve data word extended from 8 to 16 bit in this block ----- +------------------------------------------------------------------------- + +-------------------------------------------------------------------------- +-- *Mod: transmit data word extended from 8 to 16 bit in this block ----- + xmit_shift_reg : spi_xmit_shift_reg + PORT MAP( + data_in(15)=>xmit_data(15), data_in(14)=>xmit_data(14), + data_in(13)=>xmit_data(13), data_in(12)=>xmit_data(12), + data_in(11)=>xmit_data(11), data_in(10)=>xmit_data(10), + data_in(9)=>xmit_data(9), data_in(8)=>xmit_data(8), + data_in(7)=>xmit_data(7), data_in(6)=>xmit_data(6), + data_in(5)=>xmit_data(5), data_in(4)=>xmit_data(4), + data_in(3)=>xmit_data(3), data_in(2)=>xmit_data(2), + data_in(1)=>xmit_data(1), data_in(0)=>xmit_data(0), + data_ld=>xmit_load, + reset=>reset, sclk=>sck_1, shift_en=>xmit_shift, shift_in=>vcc, + ss_in_int=>ss_in_int, sys_clk=>clk, mosi=>mosi + ); +-- *Mod: transmit data word extended from 8 to 16 bit in this block ----- +-------------------------------------------------------------------------- + +END SCHEMATIC; Index: /firmware/FTU/old_design/spi_interface/spi_rcv_shift_reg_16.vhd =================================================================== --- /firmware/FTU/old_design/spi_interface/spi_rcv_shift_reg_16.vhd (revision 9841) +++ /firmware/FTU/old_design/spi_interface/spi_rcv_shift_reg_16.vhd (revision 9841) @@ -0,0 +1,168 @@ +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +-- File: spi_rcv_shift_reg_16.vhd +-- +-- +-- Original file: spi_rcv_shift_reg.vhd +-- +-- Created: 9-6-00 ALS +-- SPI shift register that shifts data in on MISO. No data is shifted out. +-- This is an 8-bit register clocked on the outgoing SCK. The data input +-- on the MISO pin is first clocked by two registers - one on the rising edge +-- of SCK and one on the falling edge of SCK. The data selected to be input into the +-- shift register is determined by a control bit in the control register (RCV_CPOL). +-- When all bits have been shifted in, the data is loaded into the uC SPI Receive Data +-- register. +-- +-- Revised: 9-11-00 ALS +-- Revised: 10-17-00 ALS +-- Revised: 12-12-02 JRH + +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +-- Modified from 8 to 16 bit word size by Patrick Vogler +-- 18th November 2009 +-- +-- Modifications are marked by: *Mod: +-- +-- Cleaned up by Quirin Weitzel +-- 21th January 2010 +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +entity spi_rcv_shift_reg is + port( + -- shift control and data + miso : in STD_LOGIC; -- Serial data in + shift_en : in STD_LOGIC; -- Active low shift enable + + -- parallel data out + data_out : out STD_LOGIC_VECTOR (15 downto 0); -- Shifted data, *Mod: 15 instead of 7, parallel output extended from 8 to 16 bit + + rcv_load : out std_logic; -- load signal to uC register + + -- rising edge and falling SCK edges + sck_re : in std_logic; -- rising edge of SCK + sck_fe : in std_logic; -- falling edge of SCK + + -- uC configuration for receive clock polarity + rcv_cpol : in STD_LOGIC; -- receive clock polarity + cpol : in std_logic; -- spi clock polarity + + ss_in_int : in STD_LOGIC; -- signal indicating another master is on the bus + + reset : in STD_LOGIC; -- reset + sclk : in STD_LOGIC -- clock + ); +end spi_rcv_shift_reg; + +architecture DEFINITION of spi_rcv_shift_reg is + + --******************************** Constants *********************** + constant RESET_ACTIVE : std_logic := '0'; + + --******************************** Signals ************************* + signal data_int : STD_LOGIC_VECTOR (15 downto 0);-- *Mod: 15 instead of 7, extension form 8 to 16 bit + signal shift_in : STD_LOGIC; -- data to be shifted in + signal miso_neg : STD_LOGIC; -- data clocked on neg SCK + signal miso_pos : STD_LOGIC; -- data clocked on pos SCK + + signal rcv_bitcnt_int : unsigned(2 downto 0); -- internal bit count + signal rcv_bitcnt : std_logic_vector(2 downto 0); -- bit count + +begin + + --******************************** SPI Receive Shift Register *********************** + -- This shift register is clocked on the SCK output from the CPLD + + rcv_shift_reg: process(sclk, reset, ss_in_int) + begin + -- Clear output register + if (reset = RESET_ACTIVE or ss_in_int = '0') then + data_int <= (others => '0'); + + -- On rising edge of spi clock, shift in data + elsif sclk'event and sclk = '1' then + + -- If shift enable is high + if shift_en = '0' then + + -- Shift the data + data_int <= data_int(14 downto 0) & shift_in; -- *Mod: 14 instead of 6 + + end if; + + end if; + + end process; + + --******************************** MISO Input Registers *********************** + -- The MISO signal is clocked on both the rising and falling edges of SCK. The output + -- of both these registers is then multiplexed with the RCV_CPOL control bit choosing + -- which data is the valid data for the system. This data is then the input to the + -- shift register. + + -- SCK rising edge register + inreg_pos: process (sclk, reset, ss_in_int) + begin + if reset = RESET_ACTIVE or ss_in_int = '0' then + miso_pos <= '0'; + elsif sclk'event and sclk = '1' then + miso_pos <= miso; + end if; + end process; + + -- SCK falling edge register + inreg_neg: process (sclk, reset, ss_in_int) + begin + if reset = RESET_ACTIVE or ss_in_int = '0' then + miso_neg <= '0'; + elsif sclk'event and sclk = '0' then + miso_neg <= miso; + end if; + end process; + + -- RCV_CPOL multiplexor to determine shift in data + miso_mux: process (miso_neg, miso_pos, rcv_cpol) + begin + if rcv_cpol = '1' then + shift_in <= miso_pos; + else + shift_in <= miso_neg; + end if; + end process; + + --******************************** Parallel Data Out *********************** + + data_out <= data_int(14 downto 0) & shift_in; --*Mod: 14 instead of 6 + + --******************************** Receive Bit Counter *********************** + -- Count bits loading into the SPI receive shift register based on SCK + -- assert RCV_LOAD when bit count is 0 + RCV_BITCNT_PROC: process(sclk, reset, shift_en) + begin + if reset = RESET_ACTIVE or shift_en = '1' then + rcv_bitcnt_int <= (others => '0'); + elsif sclk'event and sclk = '1' then + rcv_bitcnt_int <= rcv_bitcnt_int + 1; + end if; + end process; + + rcv_bitcnt <= STD_LOGIC_VECTOR(rcv_bitcnt_int); + + --******************************** Receive Load *********************** + -- If RCV_CPOL = '0', want to assert RCV_LOAD with falling edge of SCK + -- If RCV_CPOL = '1', want to assert RCV_LOAD with rising edge of SCK + -- only want RCV_LOAD to be 1 system clock pulse in width + rcv_load <= '1' when ( shift_en = '0' and + ( (rcv_bitcnt="000" and cpol='0' and rcv_cpol='1' and sck_re='1') + or (rcv_bitcnt="000" and cpol='1' and rcv_cpol='1' and sck_re='1') + or (rcv_bitcnt="000" and cpol='0' and rcv_cpol='0' and sck_fe='1') + or (rcv_bitcnt="111" and cpol='1' and rcv_cpol='0' and sck_fe='1') ) + ) + else '0'; + +end DEFINITION; Index: /firmware/FTU/old_design/spi_interface/spi_xmit_shift_reg_16.vhd =================================================================== --- /firmware/FTU/old_design/spi_interface/spi_xmit_shift_reg_16.vhd (revision 9841) +++ /firmware/FTU/old_design/spi_interface/spi_xmit_shift_reg_16.vhd (revision 9841) @@ -0,0 +1,102 @@ +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +-- File: spi_xmit_shift_reg_16.vhd +-- +-- +-- Original file: spi_xmit_shift_reg.vhd +-- +-- Created: 9-6-00 ALS +-- SPI shift register that shifts data out on MOSI. No data is shifted in. +-- This is an 8-bit, loadable register. The data output from the shift register is +-- clocked one additional system clock to align the data with the outgoing clock on +-- SCK. +-- +-- Revised: 9-11-00 ALS +-- Revised: 9-20-00 ALS + +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +-- Modified from 8 to 16 bit word size by Patrick Vogler +-- 18th November 2009 +-- +-- Modifications are marked by: *Mod: +-- +-- Cleaned up by Quirin Weitzel +-- 21th January 2010 +--------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +entity spi_xmit_shift_reg is + port( + data_ld : in STD_LOGIC; -- Data load enable + data_in : in STD_LOGIC_VECTOR (15 downto 0); -- Data to load in, *Mod: 15 instead of 7, parallel input extended from 8 to 16 bit + shift_in : in STD_LOGIC; -- Serial data in + shift_en : in STD_LOGIC; -- Shift enable + mosi : out STD_LOGIC; -- Shift serial data out + ss_in_int : in STD_LOGIC; -- another master is on bus + reset : in STD_LOGIC; -- reset + sclk : in STD_LOGIC; -- clock + sys_clk : in STD_LOGIC -- system clock + ); + +end spi_xmit_shift_reg; + +architecture DEFINITION of spi_xmit_shift_reg is + +--******************************** Constants *********************** +constant RESET_ACTIVE : std_logic := '0'; + +--******************************** Signals ************************* +signal data_int : STD_LOGIC_VECTOR (15 downto 0);-- *Mod: 15 instead of 7, parallel output extended from 8 to 16 bit +signal mosi_int : STD_LOGIC; + +begin + + --******************************** SPI Xmit Shift Register *********************** + -- This shift register is clocked on SCK_1 + xmit_shift_reg: process(sclk, reset, ss_in_int) + begin + -- Clear output register + if (reset = RESET_ACTIVE or ss_in_int = '0') then + data_int <= (others => '0'); + + -- On rising edge of spi clock, shift data + elsif sclk'event and sclk = '1' then + + -- Load data + if (data_ld = '1') then + data_int <= data_in; + + -- If shift enable is high + elsif shift_en = '1' then + + -- Shift the data + data_int <= data_int(14 downto 0) & shift_in; --*Mod: 14 instead of 6, shift register extended from 8 to 16 bit + end if; + + end if; + + end process; + + --******************************** MOSI Output Register *********************** + -- This output register is clocked on the system clock and aligns the data from the + -- shift register with the outgoing SCK + outreg: process (sys_clk, reset) + begin + if reset = RESET_ACTIVE then + mosi_int <= '0'; + elsif sys_clk'event and sys_clk = '1' then + + mosi_int <= data_int(15); -- *Mod: 15 instead of 7, shift register extended form 8 to 16 bit + end if; + end process; + + -- The MOSI output is 3-stated if the SS_IN_INT signal is asserted indicating that another + -- master is on the bus + mosi <= mosi_int when ss_in_int = '1' + else 'Z'; + +end DEFINITION; Index: /firmware/FTU/ram/FTU_dual_port_ram.asy =================================================================== --- /firmware/FTU/ram/FTU_dual_port_ram.asy (revision 9841) +++ /firmware/FTU/ram/FTU_dual_port_ram.asy (revision 9841) @@ -0,0 +1,53 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 FTU_dual_port_ram +RECTANGLE Normal 32 32 544 672 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName addra[4:0] +PINATTR Polarity IN +LINE Wide 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName dina[7:0] +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName ena +PINATTR Polarity IN +LINE Wide 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName wea[0:0] +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName clka +PINATTR Polarity IN +LINE Wide 0 432 32 432 +PIN 0 432 LEFT 36 +PINATTR PinName addrb[3:0] +PINATTR Polarity IN +LINE Wide 0 464 32 464 +PIN 0 464 LEFT 36 +PINATTR PinName dinb[15:0] +PINATTR Polarity IN +LINE Normal 0 496 32 496 +PIN 0 496 LEFT 36 +PINATTR PinName enb +PINATTR Polarity IN +LINE Wide 0 560 32 560 +PIN 0 560 LEFT 36 +PINATTR PinName web[0:0] +PINATTR Polarity IN +LINE Normal 0 624 32 624 +PIN 0 624 LEFT 36 +PINATTR PinName clkb +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName douta[7:0] +PINATTR Polarity OUT +LINE Wide 576 368 544 368 +PIN 576 368 RIGHT 36 +PINATTR PinName doutb[15:0] +PINATTR Polarity OUT + Index: /firmware/FTU/ram/FTU_dual_port_ram.gise =================================================================== --- /firmware/FTU/ram/FTU_dual_port_ram.gise (revision 9841) +++ /firmware/FTU/ram/FTU_dual_port_ram.gise (revision 9841) @@ -0,0 +1,33 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + Index: /firmware/FTU/ram/FTU_dual_port_ram.ngc =================================================================== --- /firmware/FTU/ram/FTU_dual_port_ram.ngc (revision 9841) +++ /firmware/FTU/ram/FTU_dual_port_ram.ngc (revision 9841) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.5e 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Index: /firmware/FTU/ram/FTU_dual_port_ram.sym =================================================================== --- /firmware/FTU/ram/FTU_dual_port_ram.sym (revision 9841) +++ /firmware/FTU/ram/FTU_dual_port_ram.sym (revision 9841) @@ -0,0 +1,45 @@ + + + BLOCK + 2010-7-13T8:57:24 + + + + + + + + + + + + + + FTU_dual_port_ram + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: /firmware/FTU/ram/FTU_dual_port_ram.v =================================================================== --- /firmware/FTU/ram/FTU_dual_port_ram.v (revision 9841) +++ /firmware/FTU/ram/FTU_dual_port_ram.v (revision 9841) @@ -0,0 +1,152 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file FTU_dual_port_ram.v when simulating +// the core, FTU_dual_port_ram. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module FTU_dual_port_ram( + clka, + ena, + wea, + addra, + dina, + douta, + clkb, + enb, + web, + addrb, + dinb, + doutb); + + +input clka; +input ena; +input [0 : 0] wea; +input [4 : 0] addra; +input [7 : 0] dina; +output [7 : 0] douta; +input clkb; +input enb; +input [0 : 0] web; +input [3 : 0] addrb; +input [15 : 0] dinb; +output [15 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V3_3 #( + .C_ADDRA_WIDTH(5), + .C_ADDRB_WIDTH(4), + .C_ALGORITHM(2), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(0), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_ENA(1), + .C_HAS_ENB(1), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(2), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(32), + .C_READ_DEPTH_B(16), + .C_READ_WIDTH_A(8), + .C_READ_WIDTH_B(16), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(32), + .C_WRITE_DEPTH_B(16), + .C_WRITE_MODE_A("NO_CHANGE"), + .C_WRITE_MODE_B("NO_CHANGE"), + .C_WRITE_WIDTH_A(8), + .C_WRITE_WIDTH_B(16), + .C_XDEVICEFAMILY("spartan3a")) + inst ( + .CLKA(clka), + .ENA(ena), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .DOUTA(douta), + .CLKB(clkb), + .ENB(enb), + .WEB(web), + .ADDRB(addrb), + .DINB(dinb), + .DOUTB(doutb), + .RSTA(), + .REGCEA(), + .RSTB(), + .REGCEB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of FTU_dual_port_ram is "black_box" + +endmodule + Index: /firmware/FTU/ram/FTU_dual_port_ram.veo =================================================================== --- /firmware/FTU/ram/FTU_dual_port_ram.veo (revision 9841) +++ /firmware/FTU/ram/FTU_dual_port_ram.veo (revision 9841) @@ -0,0 +1,54 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +FTU_dual_port_ram YourInstanceName ( + .clka(clka), + .ena(ena), + .wea(wea), // Bus [0 : 0] + .addra(addra), // Bus [4 : 0] + .dina(dina), // Bus [7 : 0] + .douta(douta), // Bus [7 : 0] + .clkb(clkb), + .enb(enb), + .web(web), // Bus [0 : 0] + .addrb(addrb), // Bus [3 : 0] + .dinb(dinb), // Bus [15 : 0] + .doutb(doutb)); // Bus [15 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file FTU_dual_port_ram.v when simulating +// the core, FTU_dual_port_ram. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + Index: /firmware/FTU/ram/FTU_dual_port_ram.vhd =================================================================== --- /firmware/FTU/ram/FTU_dual_port_ram.vhd (revision 9841) +++ /firmware/FTU/ram/FTU_dual_port_ram.vhd (revision 9841) @@ -0,0 +1,150 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2009 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file FTU_dual_port_ram.vhd when simulating +-- the core, FTU_dual_port_ram. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY FTU_dual_port_ram IS + port ( + clka: IN std_logic; + ena: IN std_logic; + wea: IN std_logic_VECTOR(0 downto 0); + addra: IN std_logic_VECTOR(4 downto 0); + dina: IN std_logic_VECTOR(7 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0); + clkb: IN std_logic; + enb: IN std_logic; + web: IN std_logic_VECTOR(0 downto 0); + addrb: IN std_logic_VECTOR(3 downto 0); + dinb: IN std_logic_VECTOR(15 downto 0); + doutb: OUT std_logic_VECTOR(15 downto 0)); +END FTU_dual_port_ram; + +ARCHITECTURE FTU_dual_port_ram_a OF FTU_dual_port_ram IS +-- synthesis translate_off +component wrapped_FTU_dual_port_ram + port ( + clka: IN std_logic; + ena: IN std_logic; + wea: IN std_logic_VECTOR(0 downto 0); + addra: IN std_logic_VECTOR(4 downto 0); + dina: IN std_logic_VECTOR(7 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0); + clkb: IN std_logic; + enb: IN std_logic; + web: IN std_logic_VECTOR(0 downto 0); + addrb: IN std_logic_VECTOR(3 downto 0); + dinb: IN std_logic_VECTOR(15 downto 0); + doutb: OUT std_logic_VECTOR(15 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_FTU_dual_port_ram use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 2, + c_rstram_b => 0, + c_rstram_a => 0, + c_has_injecterr => 0, + c_rst_type => "SYNC", + c_prim_type => 1, + c_read_width_b => 16, + c_initb_val => "0", + c_family => "spartan3", + c_read_width_a => 8, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "NO_CHANGE", + c_init_file_name => "no_coe_file_loaded", + c_write_mode_a => "NO_CHANGE", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_has_mem_output_regs_a => 0, + c_load_init_file => 0, + c_xdevicefamily => "spartan3a", + c_write_depth_b => 16, + c_write_depth_a => 32, + c_has_rstb => 0, + c_has_rsta => 0, + c_has_mux_output_regs_b => 0, + c_inita_val => "0", + c_has_mux_output_regs_a => 0, + c_addra_width => 5, + c_addrb_width => 4, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 2, + c_disable_warn_bhv_range => 0, + c_write_width_b => 16, + c_write_width_a => 8, + c_read_depth_b => 16, + c_read_depth_a => 32, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 1, + c_web_width => 1, + c_has_ena => 1, + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_rst_priority_b => "CE", + c_rst_priority_a => "CE", + c_use_default_data => 0); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_FTU_dual_port_ram + port map ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta, + clkb => clkb, + enb => enb, + web => web, + addrb => addrb, + dinb => dinb, + doutb => doutb); +-- synthesis translate_on + +END FTU_dual_port_ram_a; + Index: /firmware/FTU/ram/FTU_dual_port_ram.vho =================================================================== --- /firmware/FTU/ram/FTU_dual_port_ram.vho (revision 9841) +++ /firmware/FTU/ram/FTU_dual_port_ram.vho (revision 9841) @@ -0,0 +1,78 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2009 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component FTU_dual_port_ram + port ( + clka: IN std_logic; + ena: IN std_logic; + wea: IN std_logic_VECTOR(0 downto 0); + addra: IN std_logic_VECTOR(4 downto 0); + dina: IN std_logic_VECTOR(7 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0); + clkb: IN std_logic; + enb: IN std_logic; + web: IN std_logic_VECTOR(0 downto 0); + addrb: IN std_logic_VECTOR(3 downto 0); + dinb: IN std_logic_VECTOR(15 downto 0); + doutb: OUT std_logic_VECTOR(15 downto 0)); +end component; + +-- Synplicity black box declaration +attribute syn_black_box : boolean; +attribute syn_black_box of FTU_dual_port_ram: component is true; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : FTU_dual_port_ram + port map ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + douta => douta, + clkb => clkb, + enb => enb, + web => web, + addrb => addrb, + dinb => dinb, + doutb => doutb); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file FTU_dual_port_ram.vhd when simulating +-- the core, FTU_dual_port_ram. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + Index: /firmware/FTU/ram/FTU_dual_port_ram.xco =================================================================== --- /firmware/FTU/ram/FTU_dual_port_ram.xco (revision 9841) +++ /firmware/FTU/ram/FTU_dual_port_ram.xco (revision 9841) @@ -0,0 +1,89 @@ +############################################################## +# +# Xilinx Core Generator version 11.5 +# Date: Tue Jul 13 08:58:12 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s400an +SET devicefamily = spartan3a +SET flowvendor = Foundation_ISE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fgg400 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = True +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator family Xilinx,_Inc. 3.3 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Low_Power +CSET assume_synchronous_clk=false +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=FTU_dual_port_ram +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET enable_a=Use_ENA_Pin +CSET enable_b=Use_ENB_Pin +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET load_init_file=false +CSET memory_type=True_Dual_Port_RAM +CSET operating_mode_a=NO_CHANGE +CSET operating_mode_b=NO_CHANGE +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=50 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=16 +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=32 +CSET write_width_a=8 +CSET write_width_b=16 +# END Parameters +GENERATE +# CRC: 54a45d78 Index: /firmware/FTU/ram/FTU_dual_port_ram.xise =================================================================== --- /firmware/FTU/ram/FTU_dual_port_ram.xise (revision 9841) +++ /firmware/FTU/ram/FTU_dual_port_ram.xise (revision 9841) @@ -0,0 +1,358 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: /firmware/FTU/ram/FTU_dual_port_ram_flist.txt =================================================================== --- /firmware/FTU/ram/FTU_dual_port_ram_flist.txt (revision 9841) +++ /firmware/FTU/ram/FTU_dual_port_ram_flist.txt (revision 9841) @@ -0,0 +1,18 @@ +# Output products list for +FTU_dual_port_ram.asy +FTU_dual_port_ram.gise +FTU_dual_port_ram.ise +FTU_dual_port_ram.ngc +FTU_dual_port_ram.sym +FTU_dual_port_ram.v +FTU_dual_port_ram.veo +FTU_dual_port_ram.vhd +FTU_dual_port_ram.vho +FTU_dual_port_ram.xco +FTU_dual_port_ram.xise +FTU_dual_port_ram_flist.txt +FTU_dual_port_ram_readme.txt +FTU_dual_port_ram_xdb/tmp/ +FTU_dual_port_ram_xmdf.tcl +_xmsgs/ +blk_mem_gen_ds512.pdf Index: /firmware/FTU/ram/FTU_dual_port_ram_readme.txt =================================================================== --- /firmware/FTU/ram/FTU_dual_port_ram_readme.txt (revision 9841) +++ /firmware/FTU/ram/FTU_dual_port_ram_readme.txt (revision 9841) @@ -0,0 +1,67 @@ +The following files were generated for 'FTU_dual_port_ram' in directory +/ihp/home01/qweitzel/CT3-FACT/fact_repos.svn/FPGA/FTU/ram/ + +FTU_dual_port_ram.asy: + Graphical symbol information file. Used by the ISE tools and some + third party tools to create a symbol representing the core. + +FTU_dual_port_ram.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +FTU_dual_port_ram.ise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +FTU_dual_port_ram.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +FTU_dual_port_ram.sym: + Please see the core data sheet. + +FTU_dual_port_ram.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +FTU_dual_port_ram.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +FTU_dual_port_ram.vhd: + VHDL wrapper file provided to support functional simulation. This + file contains simulation model customization data that is passed to + a parameterized simulation model for the core. + +FTU_dual_port_ram.vho: + VHO template file containing code that can be used as a model for + instantiating a CORE Generator module in a VHDL design. + +FTU_dual_port_ram.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +FTU_dual_port_ram.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +FTU_dual_port_ram_readme.txt: + Text file indicating the files generated and how they are used. + +FTU_dual_port_ram_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +FTU_dual_port_ram_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + +blk_mem_gen_ds512.pdf: + Please see the core data sheet. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + Index: /firmware/FTU/ram/FTU_dual_port_ram_xmdf.tcl =================================================================== --- /firmware/FTU/ram/FTU_dual_port_ram_xmdf.tcl (revision 9841) +++ /firmware/FTU/ram/FTU_dual_port_ram_xmdf.tcl (revision 9841) @@ -0,0 +1,84 @@ +# The package naming convention is _xmdf +package provide FTU_dual_port_ram_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::FTU_dual_port_ram_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::FTU_dual_port_ram_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name FTU_dual_port_ram +} +# ::FTU_dual_port_ram_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::FTU_dual_port_ram_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FTU_dual_port_ram.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FTU_dual_port_ram.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FTU_dual_port_ram.sym +utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FTU_dual_port_ram.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FTU_dual_port_ram.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FTU_dual_port_ram.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FTU_dual_port_ram.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FTU_dual_port_ram.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path FTU_dual_port_ram_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module FTU_dual_port_ram +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams Index: /firmware/FTU/ram/blk_mem_gen_ds512.pdf =================================================================== --- /firmware/FTU/ram/blk_mem_gen_ds512.pdf (revision 9841) +++ /firmware/FTU/ram/blk_mem_gen_ds512.pdf (revision 9841) @@ -0,0 +1,77874 @@ +%PDF-1.4 +%âãÏÓ +3532 0 obj +<> +endobj + +xref +3532 146 +0000000016 00000 n +0000005366 00000 n +0000005534 00000 n +0000005571 00000 n +0000005817 00000 n +0000005948 00000 n +0000006058 00000 n +0000006167 00000 n +0000006270 00000 n +0000006504 00000 n +0000006641 00000 n +0000007385 00000 n +0000007931 00000 n +0000008555 00000 n +0000008594 00000 n +0000008645 00000 n +0000008946 00000 n +0000009550 00000 n +0000010025 00000 n +0000010638 00000 n +0000010717 00000 n +0000012634 00000 n +0000012703 00000 n +0000014315 00000 n +0000014385 00000 n +0000016267 00000 n +0000018079 00000 n +0000019813 00000 n +0000021614 00000 n +0000023503 00000 n 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2002-11-22T16:13:34Z + 2009-08-07T14:29:23-04:00 + + + uuid:44ef2051-a8bb-4125-a537-833070c0061b + uuid:dd5f198d-a2e7-4db4-906f-aa0bbe641079 + + + + + + + + + + + + + + + + + + + + + + + + + +endstream +endobj +xref +3531 1 +0003253907 00000 n +3533 1 +0003254403 00000 n +3574 1 +0003254571 00000 n +3678 1 +0003254717 00000 n +trailer +<]/Prev 116 >> +startxref +3258901 +%%EOF Index: /firmware/FTU/test_firmware/FTU_test1/FTU_test1.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test1/FTU_test1.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test1/FTU_test1.vhd (revision 9841) @@ -0,0 +1,198 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 04/05/2010 +-- Design Name: +-- Module Name: FTU_test1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTU board, switch on/off enable signals +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTU_test1 is + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + --reset : in STD_LOGIC; -- reset + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + -- miso : IN STD_LOGIC; -- master-in-slave-out + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); +end FTU_test1; + +architecture Behavioral of FTU_test1 is + + component FTU_test1_dcm + port( + CLKIN_IN : IN STD_LOGIC; + CLKFX_OUT : OUT STD_LOGIC; + CLKIN_IBUFG_OUT : OUT STD_LOGIC + ); + end component; + + component Clock_Divider + port( + clock : IN STD_LOGIC; + enable_out : OUT STD_LOGIC + ); + end component; + + signal clk_5M_sig : STD_LOGIC; + signal enable_sig : STD_LOGIC; + +begin + + Inst_FTU_test1_dcm : FTU_test1_dcm + port map( + CLKIN_IN => ext_clk, + CLKFX_OUT => clk_5M_sig, + CLKIN_IBUFG_OUT => open + ); + + Inst_Clock_Divider : Clock_Divider + port map ( + clock => clk_5M_sig, + enable_out => enable_sig + ); + + enables_A(0) <= enable_sig; + enables_A(1) <= enable_sig; + enables_A(2) <= enable_sig; + enables_A(3) <= enable_sig; + enables_A(4) <= enable_sig; + enables_A(5) <= enable_sig; + enables_A(6) <= enable_sig; + enables_A(7) <= enable_sig; + enables_A(8) <= enable_sig; + + enables_B(0) <= enable_sig; + enables_B(1) <= enable_sig; + enables_B(2) <= enable_sig; + enables_B(3) <= enable_sig; + enables_B(4) <= enable_sig; + enables_B(5) <= enable_sig; + enables_B(6) <= enable_sig; + enables_B(7) <= enable_sig; + enables_B(8) <= enable_sig; + + enables_C(0) <= enable_sig; + enables_C(1) <= enable_sig; + enables_C(2) <= enable_sig; + enables_C(3) <= enable_sig; + enables_C(4) <= enable_sig; + enables_C(5) <= enable_sig; + enables_C(6) <= enable_sig; + enables_C(7) <= enable_sig; + enables_C(8) <= enable_sig; + + enables_D(0) <= enable_sig; + enables_D(1) <= enable_sig; + enables_D(2) <= enable_sig; + enables_D(3) <= enable_sig; + enables_D(4) <= enable_sig; + enables_D(5) <= enable_sig; + enables_D(6) <= enable_sig; + enables_D(7) <= enable_sig; + enables_D(8) <= enable_sig; + +end Behavioral; + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity Clock_Divider is + port( + clock : in std_logic; + enable_out: out std_logic + ); +end entity Clock_Divider; + +architecture RTL of Clock_Divider is + + --constant max_count : integer := 5000000/1000000; -- for simulation + constant max_count : integer := 5000000/1; -- for implementation + constant final_count : integer := 10; + +begin + + process(clock) + variable count : integer range 0 to max_count; + variable count2 : integer range 0 to final_count; + begin + if rising_edge(clock) then + --enable_out <= '0'; + if count2 = final_count then + enable_out <= '0'; + else + if count < max_count/2 then + enable_out <= '0'; + count := count + 1; + elsif count < max_count then + enable_out <= '1'; + count := count + 1; + else + count := 0; + enable_out <= '0'; + count2 := count2 + 1; + end if; + end if; + end if; + end process; + +end architecture RTL; Index: /firmware/FTU/test_firmware/FTU_test1/FTU_test1_dcm.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test1/FTU_test1_dcm.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test1/FTU_test1_dcm.vhd (revision 9841) @@ -0,0 +1,88 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.1 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTU_test1_dcm.vhd +-- /___/ /\ Timestamp : 05/04/2010 17:27:08 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /home/qweitzel/CT3-FACT/fact_repos.svn/FPGA/FTU/test_firmware/FTU_test1_dcm.xaw /home/qweitzel/CT3-FACT/fact_repos.svn/FPGA/FTU/test_firmware/FTU_test1_dcm +--Design Name: FTU_test1_dcm +--Device: xc3s400an-4fgg400 +-- +-- Module FTU_test1_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 6.54 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTU_test1_dcm is + port ( CLKIN_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic); +end FTU_test1_dcm; + +architecture BEHAVIORAL of FTU_test1_dcm is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 20, + CLKFX_MULTIPLY => 2, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>GND_BIT, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>open, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: /firmware/FTU/test_firmware/FTU_test1/FTU_test1_dcm_arwz.ucf =================================================================== --- /firmware/FTU/test_firmware/FTU_test1/FTU_test1_dcm_arwz.ucf (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test1/FTU_test1_dcm_arwz.ucf (revision 9841) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = NONE; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 20; +INST DCM_SP_INST CLKFX_MULTIPLY = 2; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 20.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: /firmware/FTU/test_firmware/FTU_test1/FTU_test1_tb.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test1/FTU_test1_tb.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test1/FTU_test1_tb.vhd (revision 9841) @@ -0,0 +1,177 @@ +-------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 05/04/2010 +-- Design Name: +-- Module Name: /home/qweitzel/FPGA/FACT/FTU/test_firmware/FTU_test1_tb.vhd +-- Project Name: FTU_test1_sim01 +-- Target Device: +-- Tool versions: +-- Description: Testbench for test1 entity of FACT FTU board +-- +-- VHDL Test Bench Created by ISE for module: FTU_test1 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity FTU_test1_tb is +end FTU_test1_tb; + +architecture behavior of FTU_test1_tb is + + -- Component Declaration for the Unit Under Test (UUT) + + component FTU_test1 + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + --reset : in STD_LOGIC; -- reset + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable address + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + -- miso : IN STD_LOGIC; -- master-in-slave-out + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); + end component; + + --Inputs + signal ext_clk : STD_LOGIC := '0'; + --signal reset : STD_LOGIC := '0'; + signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); + signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); + signal patch_A_p : STD_LOGIC := '0'; + signal patch_A_n : STD_LOGIC := '0'; + signal patch_B_p : STD_LOGIC := '0'; + signal patch_B_n : STD_LOGIC := '0'; + signal patch_C_p : STD_LOGIC := '0'; + signal patch_C_n : STD_LOGIC := '0'; + signal patch_D_p : STD_LOGIC := '0'; + signal patch_D_n : STD_LOGIC := '0'; + signal trig_prim_p : STD_LOGIC := '0'; + signal trig_prim_n : STD_LOGIC := '0'; + -- signal miso : STD_LOGIC := '0'; + signal rx : STD_LOGIC := '0'; + + --Outputs + signal enables_A : STD_LOGIC_VECTOR(8 downto 0); + signal enables_B : STD_LOGIC_VECTOR(8 downto 0); + signal enables_C : STD_LOGIC_VECTOR(8 downto 0); + signal enables_D : STD_LOGIC_VECTOR(8 downto 0); + signal clr : STD_LOGIC; + signal cs_ld : STD_LOGIC; + signal sck : STD_LOGIC; + signal mosi : STD_LOGIC; + signal tx : STD_LOGIC; + signal rx_en : STD_LOGIC; + signal tx_en : STD_LOGIC; + signal TP_A : STD_LOGIC_VECTOR(11 downto 0); + + -- Clock period definitions + constant ext_clk_period : TIME := 20 ns; + +begin + + -- Instantiate the Unit Under Test (UUT) + uut: FTU_test1 + port map( + ext_clk => ext_clk, + --reset => reset, + brd_add => brd_add, + brd_id => brd_id, + patch_A_p => patch_A_p, + patch_A_n => patch_A_n, + patch_B_p => patch_B_p, + patch_B_n => patch_B_n, + patch_C_p => patch_C_p, + patch_C_n => patch_C_n, + patch_D_p => patch_D_p, + patch_D_n => patch_D_n, + trig_prim_p => trig_prim_p, + trig_prim_n => trig_prim_n, + -- miso => miso, + rx => rx, + rx_en => rx_en, + enables_A => enables_A, + enables_B => enables_B, + enables_C => enables_C, + enables_D => enables_D, + clr => clr, + cs_ld => cs_ld, + sck => sck, + mosi => mosi, + tx => tx, + tx_en => tx_en, + TP_A => TP_A + ); + + -- Clock process definitions + ext_clk_proc: process + begin + ext_clk <= '0'; + wait for ext_clk_period/2; + ext_clk <= '1'; + wait for ext_clk_period/2; + end process ext_clk_proc; + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + wait for 100ms; + + wait for ext_clk_period*10; + + -- insert stimulus here + + wait; + end process stim_proc; + +end; Index: /firmware/FTU/test_firmware/FTU_test1/ftu_board_test1.ucf =================================================================== --- /firmware/FTU/test_firmware/FTU_test1/ftu_board_test1.ucf (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test1/ftu_board_test1.ucf (revision 9841) @@ -0,0 +1,145 @@ +######################################################## +# FTU Board +# FACT Trigger Unit +# +# Pin location constraints +# +# by Patrick Vogler, Quirin Weitzel +# 01 July 2010 +######################################################## + + +#Clock +####################################################### +NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk + + +# RS-485 Interface +####################################################### +#NET rx_en LOC = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver +#NET tx_en LOC = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter +#NET tx LOC = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM +#NET rx LOC = R20 | IOSTANDARD=LVCMOS33; # 485_DI: serial data from FTM + + +# Board ID - inputs +# local board-ID "solder programmable" +####################################################### +#NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0 +#NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1 +#NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2 +#NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3 +#NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4 +#NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5 +#NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6 +#NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7 + + +# Board Addresses +# geographical slot address +####################################################### +#NET brd_add<0> LOC = A15 | IOSTANDARD=LVCMOS33; # ADDR0 +#NET brd_add<1> LOC = B15 | IOSTANDARD=LVCMOS33; # ADDR1 +#NET brd_add<2> LOC = A16 | IOSTANDARD=LVCMOS33; # ADDR2 +#NET brd_add<3> LOC = A17 | IOSTANDARD=LVCMOS33; # ADDR3 +#NET brd_add<4> LOC = A18 | IOSTANDARD=LVCMOS33; # ADDR4 +#NET brd_add<5> LOC = B18 | IOSTANDARD=LVCMOS33; # ADDR5 + + +# DAC SPI Interface +####################################################### +#NET mosi LOC = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in +#NET sck LOC = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC +#NET cs_ld LOC = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC +#NET clr LOC = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC + + +# Testpoints +###################################################### +# on Connector J5 +#NET TP_A<0> LOC = B3 | IOSTANDARD=LVCMOS33; # TP0_0 +#NET TP_A<1> LOC = A3 | IOSTANDARD=LVCMOS33; # TP1_0 +#NET TP_A<2> LOC = A4 | IOSTANDARD=LVCMOS33; # TP2_0 +#NET TP_A<3> LOC = B5 | IOSTANDARD=LVCMOS33; # TP2_0 + +# on Connector J6 +#NET TP_A<4> LOC = A5 | IOSTANDARD=LVCMOS33; # TP4_0 +#NET TP_A<5> LOC = A6 | IOSTANDARD=LVCMOS33; # TP5_0 +#NET TP_A<6> LOC = B7 | IOSTANDARD=LVCMOS33; # TP6_0 +#NET TP_A<7> LOC = A7 | IOSTANDARD=LVCMOS33; # TP7_0 + +# on Connector J7 +#NET TP_A<8> LOC = B11 | IOSTANDARD=LVCMOS33; # TP8_0 +#NET TP_A<9> LOC = A12 | IOSTANDARD=LVCMOS33; # TP9_0 +#NET TP_A<10> LOC = B12 | IOSTANDARD=LVCMOS33; # TP10_0 +#NET TP_A<11> LOC = A14 | IOSTANDARD=LVCMOS33; # TP11_0 + + +# Rate counter LVDS Inputs +###################################################### +# logic signal from first trigger patch +#NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P +#NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N + +# logic signal from second trigger patch +#NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P +#NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N + +# logic signal from third trigger patch +#NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P +#NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N + +# logic signal from fourth trigger patch +#NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P +#NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N + +#The Trigger Primitive: logic signal from n-out-of-4 circuit +#NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+ +#NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P- + + +# Enables +###################################################### +# Patch 0 +NET enables_A<0> LOC = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 +NET enables_A<1> LOC = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1 +NET enables_A<2> LOC = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2 +NET enables_A<3> LOC = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3 +NET enables_A<4> LOC = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4 +NET enables_A<5> LOC = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5 +NET enables_A<6> LOC = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6 +NET enables_A<7> LOC = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7 +NET enables_A<8> LOC = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8 + +## Patch 1 +NET enables_B<0> LOC = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0 +NET enables_B<1> LOC = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1 +NET enables_B<2> LOC = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2 +NET enables_B<3> LOC = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3 +NET enables_B<4> LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4 +NET enables_B<5> LOC = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5 +NET enables_B<6> LOC = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6 +NET enables_B<7> LOC = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7 +NET enables_B<8> LOC = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8 + +# Patch 2 +NET enables_C<0> LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0 +NET enables_C<1> LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1 +NET enables_C<2> LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2 +NET enables_C<3> LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3 +NET enables_C<4> LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4 +NET enables_C<5> LOC = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5 +NET enables_C<6> LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6 +NET enables_C<7> LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7 +NET enables_C<8> LOC = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8 + +# Patch 3 +NET enables_D<0> LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<1> LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<2> LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<3> LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<4> LOC = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<5> LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<6> LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<7> LOC = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<8> LOC = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 Index: /firmware/FTU/test_firmware/FTU_test2/FTU_test2.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test2/FTU_test2.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test2/FTU_test2.vhd (revision 9841) @@ -0,0 +1,150 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 05/07/2010 +-- Design Name: +-- Module Name: FTU_test2 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTU board, set thresholds to some value +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +entity FTU_test2 is + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : in STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); +end FTU_test2; + + +architecture Behavioral of FTU_test2 is + + component FTU_test2_dac_dcm + port( + CLKIN_IN : IN STD_LOGIC; + RST_IN : IN STD_LOGIC; + CLKFX_OUT : OUT STD_LOGIC; + CLKIN_IBUFG_OUT : OUT STD_LOGIC; + LOCKED_OUT : OUT STD_LOGIC + ); + end component; + + component FTU_test2_dac_control + port( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr : OUT STD_LOGIC; + mosi : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + cs_ld : OUT STD_LOGIC; + enable1 : out STD_LOGIC; + enable2 : out STD_LOGIC; + enable3 : out STD_LOGIC + ); + end component; + + signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up + signal clk_50M_sig : STD_LOGIC; + + type FTU_test2_StateType is (Running); + signal FTU_test2_State, FTU_test2_NextState: FTU_test2_StateType; + +begin + + Inst_FTU_test2_dac_dcm : FTU_test2_dac_dcm + port map( + CLKIN_IN => ext_clk, + RST_IN => reset_sig, + CLKFX_OUT => clk_50M_sig, + CLKIN_IBUFG_OUT => open, + LOCKED_OUT => open + ); + + Inst_FTU_test2_dac_control : FTU_test2_dac_control + port map( + clk => clk_50M_sig, + reset => reset_sig, + clr => clr, + mosi => mosi, + sck => sck, + cs_ld => cs_ld, + enable1 => enables_A(1), + enable2 => enables_A(2), + enable3 => enables_A(3) + ); + + --FTU main state machine (two-process implementation) + + FTU_test2_Registers: process (ext_clk) + begin + if Rising_edge(ext_clk) then + FTU_test2_State <= FTU_test2_NextState; + end if; + end process FTU_test2_Registers; + + FTU_test2_C_logic: process (FTU_test2_State) + begin + FTU_test2_NextState <= FTU_test2_State; + case FTU_test2_State is + when Running => + reset_sig <= '0'; + enables_A(0) <= '1'; + end case; + end process FTU_test2_C_logic; + +end Behavioral; Index: /firmware/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd (revision 9841) @@ -0,0 +1,142 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 05/07/2010 +-- Design Name: +-- Module Name: FTU_test2_dac_control - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: test2 for control DAC on FTU board to set trigger thresholds +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ftu_definitions; +USE ftu_definitions.ftu_array_types.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTU_test2_dac_control is + port( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr : OUT STD_LOGIC; + mosi : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + cs_ld : out STD_LOGIC; + enable1 : out STD_LOGIC; + enable2 : out STD_LOGIC; + enable3 : out STD_LOGIC + ); +end FTU_test2_dac_control; + +architecture Behavioral of FTU_test2_dac_control is + + component FTU_test2_spi_interface + port( + clk_50MHz : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + config_ready : OUT std_logic; + config_started : OUT std_logic; + dac_cs : OUT std_logic; + mosi : OUT std_logic; + sclk : OUT std_logic; + miso : INOUT std_logic + ); + end component; + + signal clk_sig : std_logic; + signal reset_sig : std_logic; + + signal clr_sig : std_logic; + signal mosi_sig : std_logic := '0'; + signal serial_clock_sig : std_logic; + signal dac_cs_sig : std_logic; + + signal config_start_sig : std_logic := '0'; + signal config_ready_sig : std_logic; + signal config_started_sig : std_logic := '0'; + signal dac_array_sig : dac_array_type := (100,200,300,400,500); + + -- Build an enumerated type for the state machine + type state_type is (START, WAITING, STOP); + + -- Register to hold the current state + signal state, next_state : state_type; + +begin + + reset_sig <= reset; + clk_sig <= clk; + mosi <= mosi_sig; + sck <= serial_clock_sig; + cs_ld <= dac_cs_sig; + + -- FSM for dac control: first process + FSM_Registers: process(clk_sig, reset_sig) + begin + if reset_sig = '1' then + state <= START; + elsif Rising_edge(clk_sig) then + state <= next_state; + end if; + end process; + + -- FSM for dac control: second process + FSM_logic: process(state, config_ready_sig) + begin + next_state <= state; + case state is + when START => + config_start_sig <= '1'; + enable1 <= '1'; + enable2 <= '0'; + enable3 <= '0'; + next_state <= WAITING; + when WAITING => + config_start_sig <= '1'; + enable1 <= '0'; + enable2 <= '1'; + enable3 <= '0'; + if (config_ready_sig = '1') then + next_state <= STOP; + else + next_state <= WAITING; + end if; + when STOP => + enable1 <= '0'; + enable2 <= '0'; + enable3 <= '1'; + config_start_sig <= '0'; + end case; + end process; + + Inst_FTU_test2_spi_interface : FTU_test2_spi_interface + port map( + clk_50MHz => clk_sig, + config_start => config_start_sig, + dac_array => dac_array_sig, + config_ready => config_ready_sig, + config_started => config_started_sig, + dac_cs => dac_cs_sig, + mosi => mosi_sig, + sclk => serial_clock_sig, + miso => open + ); + +end Behavioral; + Index: /firmware/FTU/test_firmware/FTU_test2/FTU_test2_dac_dcm.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test2/FTU_test2_dac_dcm.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test2/FTU_test2_dac_dcm.vhd (revision 9841) @@ -0,0 +1,90 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.1 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTU_dac_dcm.vhd +-- /___/ /\ Timestamp : 01/20/2010 16:36:17 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /home/qweitzel/FPGA/FACT/FTU/source/ip_cores/FTU_dac_dcm.xaw /home/qweitzel/FPGA/FACT/FTU/source/ip_cores/FTU_dac_dcm +--Design Name: FTU_dac_dcm +--Device: xc3s400an-4fgg400 +-- +-- Module FTU_dac_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 6.54 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTU_test2_dac_dcm is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end FTU_test2_dac_dcm; + +architecture BEHAVIORAL of FTU_test2_dac_dcm is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 2, + CLKFX_MULTIPLY => 2, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: /firmware/FTU/test_firmware/FTU_test2/FTU_test2_dac_dcm_arwz.ucf =================================================================== --- /firmware/FTU/test_firmware/FTU_test2/FTU_test2_dac_dcm_arwz.ucf (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test2/FTU_test2_dac_dcm_arwz.ucf (revision 9841) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = NONE; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 20; +INST DCM_SP_INST CLKFX_MULTIPLY = 2; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 20.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: /firmware/FTU/test_firmware/FTU_test2/FTU_test2_spi_clock_gen.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test2/FTU_test2_spi_clock_gen.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test2/FTU_test2_spi_clock_gen.vhd (revision 9841) @@ -0,0 +1,47 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_clock_generator.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 14:49:19 01.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY FTU_test2_spi_clock_generator IS + GENERIC( + CLK_DIVIDER : integer := 25 --2 MHz @ 50 MHz + ); + PORT( + clk : IN std_logic; + sclk : OUT std_logic := '0' + ); +END FTU_test2_spi_clock_generator; + +ARCHITECTURE beha OF FTU_test2_spi_clock_generator IS + +BEGIN + + spi_clk_proc: process (clk) + variable Z: integer range 0 to clk_divider - 1; + begin + if rising_edge(clk) then + if (Z < clk_divider - 1) then + Z := Z + 1; + else + Z := 0; + end if; + if (Z = 0) then + sclk <= '1'; + end if; + if (Z = clk_divider / 2) then + sclk <= '0'; + end if; + end if; + end process spi_clk_proc; + +END ARCHITECTURE beha; Index: /firmware/FTU/test_firmware/FTU_test2/FTU_test2_spi_controller.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test2/FTU_test2_spi_controller.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test2/FTU_test2_spi_controller.vhd (revision 9841) @@ -0,0 +1,81 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_controller.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 10:37:20 12.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- modified by Q. Weitzel +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY FTU_test2_spi_controller IS + PORT( + clk : IN std_logic; + miso : INOUT std_logic := 'Z'; + mosi : OUT std_logic := '0'; + dac_id : IN std_logic_vector (2 DOWNTO 0); + --data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + data : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); + dac_cs : OUT std_logic := '1'; + dac_start : IN std_logic; + dac_ready : OUT std_logic := '0' + ); +END FTU_test2_spi_controller ; + +ARCHITECTURE beha OF FTU_test2_spi_controller IS + + type TYPE_SPI_STATE is (SPI_IDLE, SPI_LOAD_DAC, SPI_LOAD_COMMAND); + + signal spi_state : TYPE_SPI_STATE := SPI_IDLE; + signal spi_cycle_cnt : integer range 0 to 25 := 0; + signal shift_reg : std_logic_vector (23 downto 0) := (others => '0'); + signal data_reg : std_logic_vector (15 downto 0) := (others => '0'); + +BEGIN + + spi_write_proc: process (clk) + begin + if falling_edge(clk) then + dac_cs <= '1'; + miso <= 'Z'; + mosi <= '0'; + --data <= (others => 'Z'); + case spi_state is + when SPI_IDLE => + if (dac_start = '1') then + dac_ready <= '0'; + spi_state <= SPI_LOAD_COMMAND; + end if; + + when SPI_LOAD_COMMAND => + spi_cycle_cnt <= 0; + if (dac_start = '1') then + shift_reg <= "0011" & '0' & dac_id & data(11 downto 0) & "0000"; + spi_state <= SPI_LOAD_DAC; + end if; + + -- start loading DACs + when SPI_LOAD_DAC => + dac_cs <= '0'; + if (spi_cycle_cnt < 24) then + mosi <= shift_reg(23); + shift_reg <= shift_reg(22 downto 0) & shift_reg(23); + dac_ready <= '0'; + spi_cycle_cnt <= spi_cycle_cnt + 1; + spi_state <= SPI_LOAD_DAC; + else + dac_cs <= '1'; + dac_ready <= '1'; + spi_state <= SPI_IDLE; + end if; + end case; + end if; + end process spi_write_proc; + +END ARCHITECTURE beha; Index: /firmware/FTU/test_firmware/FTU_test2/FTU_test2_spi_distributor.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test2/FTU_test2_spi_distributor.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test2/FTU_test2_spi_distributor.vhd (revision 9841) @@ -0,0 +1,91 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_distributor.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 09:24:21 23.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- modified by Q. Weitzel +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +library ftu_definitions; +USE ftu_definitions.ftu_array_types.all; + +ENTITY FTU_test2_spi_distributor IS + PORT( + clk : IN std_logic; -- 50MHz + config_start : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0'; + dac_array : IN dac_array_type; + dac_config_start : OUT std_logic := '0'; + dac_config_ready : IN std_logic; + dac_id : OUT std_logic_vector(2 downto 0) := (others => '0'); + --data : INOUT std_logic_vector(15 downto 0) := (others => 'Z') + data : OUT std_logic_vector(15 downto 0) := (others => '0') + ); +END ENTITY FTU_test2_spi_distributor; + +ARCHITECTURE beha OF FTU_test2_spi_distributor IS + + type TYPE_SPI_DISTRIBUTION_STATE is (INIT, IDLE, CONFIG_DAC); + + signal spi_distr_state : TYPE_SPI_DISTRIBUTION_STATE := INIT; + signal dac_id_cnt : integer range 0 to 4 := 0; + +BEGIN + + spi_distribute_proc: process (clk) + begin + + if rising_edge(clk) then + --data <= (others => 'Z'); + data <= (others => '0'); + case spi_distr_state is + when INIT => + --data <= (others => 'Z'); + data <= (others => '0'); + spi_distr_state <= IDLE; + when IDLE => + --data <= (others => 'Z'); + data <= (others => '0'); + -- start DAC configuration + if (config_start = '1') then + config_started <= '1'; + config_ready <= '0'; + dac_config_start <= '1'; + dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); + data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); + spi_distr_state <= CONFIG_DAC; + end if; + + -- DAC configuration + when CONFIG_DAC => + dac_config_start <= '1'; + dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); + data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); + if (dac_config_ready = '1') then + dac_config_start <= '0'; + if (dac_id_cnt < 4) then + dac_id_cnt <= dac_id_cnt + 1; + dac_config_start <= '1'; + spi_distr_state <= CONFIG_DAC; + else + dac_id_cnt <= 0; + config_started <= '0'; + config_ready <= '1'; + spi_distr_state <= IDLE; + end if; + end if; + end case; + end if; + + end process spi_distribute_proc; + +END ARCHITECTURE beha; + Index: /firmware/FTU/test_firmware/FTU_test2/FTU_test2_spi_interface.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test2/FTU_test2_spi_interface.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test2/FTU_test2_spi_interface.vhd (revision 9841) @@ -0,0 +1,138 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 01/07/2010 +-- Design Name: +-- Module Name: FTU_test2_spi_interface - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Based on VHDL Entity FACT_FAD_lib.spi_interface.symbol +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ftu_definitions; +USE ftu_definitions.ftu_array_types.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +ENTITY FTU_test2_spi_interface IS + PORT( + clk_50MHz : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + config_ready : OUT std_logic; + config_started : OUT std_logic := '0'; + dac_cs : OUT std_logic; + mosi : OUT std_logic := '0'; + sclk : OUT std_logic; + miso : INOUT std_logic + ); +END FTU_test2_spi_interface; + +ARCHITECTURE struct OF FTU_test2_spi_interface IS + + -- Internal signal declarations + SIGNAL dac_config_ready : std_logic; + SIGNAL dac_config_start : std_logic; + SIGNAL dac_id : std_logic_vector(2 DOWNTO 0); + SIGNAL data : std_logic_vector(15 DOWNTO 0); + + -- Implicit buffer signal declarations + SIGNAL sclk_internal : std_logic; + + + -- Component Declarations + COMPONENT FTU_test2_spi_clock_generator + GENERIC ( + CLK_DIVIDER : integer := 25 --2 MHz @ 50 MHz + ); + PORT ( + clk : IN std_logic; + sclk : OUT std_logic := '0' + ); + END COMPONENT; + + COMPONENT FTU_test2_spi_controller + PORT ( + clk : IN std_logic; + dac_id : IN std_logic_vector (2 DOWNTO 0); + dac_start : IN std_logic; + dac_cs : OUT std_logic := '1'; + dac_ready : OUT std_logic := '0'; + mosi : OUT std_logic := '0'; + --data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + data : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); + miso : INOUT std_logic := 'Z' + ); + END COMPONENT; + + COMPONENT FTU_test2_spi_distributor + PORT ( + clk : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + dac_config_ready : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0'; + dac_config_start : OUT std_logic := '0'; + dac_id : OUT std_logic_vector (2 DOWNTO 0) := (others => '0'); + --data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z') + data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') + ); + END COMPONENT; + +BEGIN + + -- Instance port mappings. + Inst_FTU_test2_spi_clock_generator : FTU_test2_spi_clock_generator + GENERIC MAP ( + CLK_DIVIDER => 25 --2 MHz @ 50 MHz + ) + PORT MAP ( + clk => clk_50MHz, + sclk => sclk_internal + ); + + Inst_FTU_test2_spi_controller : FTU_test2_spi_controller + PORT MAP ( + clk => sclk_internal, + miso => miso, + mosi => mosi, + dac_id => dac_id, + data => data, + dac_cs => dac_cs, + dac_start => dac_config_start, + dac_ready => dac_config_ready + ); + + Inst_FTU_test2_spi_distributor : FTU_test2_spi_distributor + PORT MAP ( + clk => sclk_internal, + config_start => config_start, + config_ready => config_ready, + config_started => config_started, + dac_array => dac_array, + dac_config_start => dac_config_start, + dac_config_ready => dac_config_ready, + dac_id => dac_id, + data => data + ); + + -- Implicit buffered output assignments + sclk <= sclk_internal; + +END struct; Index: /firmware/FTU/test_firmware/FTU_test2/FTU_test2_tb.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test2/FTU_test2_tb.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test2/FTU_test2_tb.vhd (revision 9841) @@ -0,0 +1,180 @@ +-------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 02/07/2010 +-- Design Name: +-- Module Name: FTU_test2_tb.vhd +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: Testbench for test2 entity of FACT FTU board +-- +-- VHDL Test Bench Created by ISE for module: FTU_test2 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-- +-- based on testbench for FTU_test1 +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity FTU_test2_tb is +end FTU_test2_tb; + +architecture behavior of FTU_test2_tb is + + -- Component Declaration for the Unit Under Test (UUT) + + component FTU_test2 + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + --reset : in STD_LOGIC; -- reset + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable address + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + -- miso : IN STD_LOGIC; -- master-in-slave-out + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); + end component; + + --Inputs + signal ext_clk : STD_LOGIC := '0'; + --signal reset : STD_LOGIC := '0'; + signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); + signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); + signal patch_A_p : STD_LOGIC := '0'; + signal patch_A_n : STD_LOGIC := '0'; + signal patch_B_p : STD_LOGIC := '0'; + signal patch_B_n : STD_LOGIC := '0'; + signal patch_C_p : STD_LOGIC := '0'; + signal patch_C_n : STD_LOGIC := '0'; + signal patch_D_p : STD_LOGIC := '0'; + signal patch_D_n : STD_LOGIC := '0'; + signal trig_prim_p : STD_LOGIC := '0'; + signal trig_prim_n : STD_LOGIC := '0'; + -- signal miso : STD_LOGIC := '0'; + signal rx : STD_LOGIC := '0'; + + --Outputs + signal enables_A : STD_LOGIC_VECTOR(8 downto 0); + signal enables_B : STD_LOGIC_VECTOR(8 downto 0); + signal enables_C : STD_LOGIC_VECTOR(8 downto 0); + signal enables_D : STD_LOGIC_VECTOR(8 downto 0); + signal clr : STD_LOGIC; + signal cs_ld : STD_LOGIC; + signal sck : STD_LOGIC; + signal mosi : STD_LOGIC; + signal tx : STD_LOGIC; + signal rx_en : STD_LOGIC; + signal tx_en : STD_LOGIC; + signal TP_A : STD_LOGIC_VECTOR(11 downto 0); + + -- Clock period definitions + constant ext_clk_period : TIME := 20 ns; + +begin + + -- Instantiate the Unit Under Test (UUT) + uut: FTU_test2 + port map( + ext_clk => ext_clk, + --reset => reset, + brd_add => brd_add, + brd_id => brd_id, + patch_A_p => patch_A_p, + patch_A_n => patch_A_n, + patch_B_p => patch_B_p, + patch_B_n => patch_B_n, + patch_C_p => patch_C_p, + patch_C_n => patch_C_n, + patch_D_p => patch_D_p, + patch_D_n => patch_D_n, + trig_prim_p => trig_prim_p, + trig_prim_n => trig_prim_n, + -- miso => miso, + rx => rx, + rx_en => rx_en, + enables_A => enables_A, + enables_B => enables_B, + enables_C => enables_C, + enables_D => enables_D, + clr => clr, + cs_ld => cs_ld, + sck => sck, + mosi => mosi, + tx => tx, + tx_en => tx_en, + TP_A => TP_A + ); + + -- Clock process definitions + ext_clk_proc: process + begin + ext_clk <= '0'; + wait for ext_clk_period/2; + ext_clk <= '1'; + wait for ext_clk_period/2; + end process ext_clk_proc; + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + wait for 100ms; + + wait for ext_clk_period*10; + + -- insert stimulus here + + wait; + end process stim_proc; + +end; Index: /firmware/FTU/test_firmware/FTU_test2/FTU_test2_upcnt16.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test2/FTU_test2_upcnt16.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test2/FTU_test2_upcnt16.vhd (revision 9841) @@ -0,0 +1,44 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +entity FTU_test2_upcnt16 is + port( + full : out STD_LOGIC; + clr : in STD_LOGIC; + reset : in STD_Logic; + clk : in STD_LOGIC + ); + +end FTU_test2_upcnt16; + +architecture DEFINITION of upcnt16 is + + constant RESET_ACTIVE : std_logic := '0'; + constant Cnt_full : Unsigned (15 DOWNTO 0) :="1111111111111111"; + + signal q : Unsigned (15 DOWNTO 0); + +begin + + process(clk, reset, clr) + begin + -- Clear output register + if ((reset OR clr)='1') then + q <= (others => '0'); + -- On rising edge of clock count + elsif (clk'event) and clk = '1' and (not(q = Cnt_full)) then + q <= q + 1; + end if; + end process; + + process(q) + begin + if (q = Cnt_full) then + full <= '1'; + else + full <= '0'; + end if; + end process; + +end DEFINITION; Index: /firmware/FTU/test_firmware/FTU_test2/ftu_board_test2.ucf =================================================================== --- /firmware/FTU/test_firmware/FTU_test2/ftu_board_test2.ucf (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test2/ftu_board_test2.ucf (revision 9841) @@ -0,0 +1,145 @@ +######################################################## +# FTU Board +# FACT Trigger Unit +# +# Pin location constraints +# +# by Patrick Vogler, Quirin Weitzel +# 02 July 2010 +######################################################## + + +#Clock +####################################################### +NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk + + +# RS-485 Interface +####################################################### +#NET rx_en LOC = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver +#NET tx_en LOC = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter +#NET tx LOC = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM +#NET rx LOC = R20 | IOSTANDARD=LVCMOS33; # 485_DI: serial data from FTM + + +# Board ID - inputs +# local board-ID "solder programmable" +####################################################### +#NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0 +#NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1 +#NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2 +#NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3 +#NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4 +#NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5 +#NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6 +#NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7 + + +# Board Addresses +# geographical slot address +####################################################### +#NET brd_add<0> LOC = A15 | IOSTANDARD=LVCMOS33; # ADDR0 +#NET brd_add<1> LOC = B15 | IOSTANDARD=LVCMOS33; # ADDR1 +#NET brd_add<2> LOC = A16 | IOSTANDARD=LVCMOS33; # ADDR2 +#NET brd_add<3> LOC = A17 | IOSTANDARD=LVCMOS33; # ADDR3 +#NET brd_add<4> LOC = A18 | IOSTANDARD=LVCMOS33; # ADDR4 +#NET brd_add<5> LOC = B18 | IOSTANDARD=LVCMOS33; # ADDR5 + + +# DAC SPI Interface +####################################################### +NET mosi LOC = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in +NET sck LOC = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC +NET cs_ld LOC = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC +NET clr LOC = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC + + +# Testpoints +###################################################### +# on Connector J5 +#NET TP_A<0> LOC = B3 | IOSTANDARD=LVCMOS33; # TP0_0 +#NET TP_A<1> LOC = A3 | IOSTANDARD=LVCMOS33; # TP1_0 +#NET TP_A<2> LOC = A4 | IOSTANDARD=LVCMOS33; # TP2_0 +#NET TP_A<3> LOC = B5 | IOSTANDARD=LVCMOS33; # TP2_0 + +# on Connector J6 +#NET TP_A<4> LOC = A5 | IOSTANDARD=LVCMOS33; # TP4_0 +#NET TP_A<5> LOC = A6 | IOSTANDARD=LVCMOS33; # TP5_0 +#NET TP_A<6> LOC = B7 | IOSTANDARD=LVCMOS33; # TP6_0 +#NET TP_A<7> LOC = A7 | IOSTANDARD=LVCMOS33; # TP7_0 + +# on Connector J7 +#NET TP_A<8> LOC = B11 | IOSTANDARD=LVCMOS33; # TP8_0 +#NET TP_A<9> LOC = A12 | IOSTANDARD=LVCMOS33; # TP9_0 +#NET TP_A<10> LOC = B12 | IOSTANDARD=LVCMOS33; # TP10_0 +#NET TP_A<11> LOC = A14 | IOSTANDARD=LVCMOS33; # TP11_0 + + +# Rate counter LVDS Inputs +###################################################### +# logic signal from first trigger patch +#NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P +#NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N + +# logic signal from second trigger patch +#NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P +#NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N + +# logic signal from third trigger patch +#NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P +#NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N + +# logic signal from fourth trigger patch +#NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P +#NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N + +#The Trigger Primitive: logic signal from n-out-of-4 circuit +#NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+ +#NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P- + + +# Enables +###################################################### +# Patch 0 +NET enables_A<0> LOC = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 +NET enables_A<1> LOC = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1 +NET enables_A<2> LOC = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2 +NET enables_A<3> LOC = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3 +#NET enables_A<4> LOC = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4 +#NET enables_A<5> LOC = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5 +#NET enables_A<6> LOC = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6 +#NET enables_A<7> LOC = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7 +#NET enables_A<8> LOC = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8 + +## Patch 1 +#NET enables_B<0> LOC = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0 +#NET enables_B<1> LOC = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1 +#NET enables_B<2> LOC = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2 +#NET enables_B<3> LOC = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3 +#NET enables_B<4> LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4 +#NET enables_B<5> LOC = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5 +#NET enables_B<6> LOC = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6 +#NET enables_B<7> LOC = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7 +#NET enables_B<8> LOC = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8 + +# Patch 2 +#NET enables_C<0> LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0 +#NET enables_C<1> LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1 +#NET enables_C<2> LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2 +#NET enables_C<3> LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3 +#NET enables_C<4> LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4 +#NET enables_C<5> LOC = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5 +#NET enables_C<6> LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6 +#NET enables_C<7> LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7 +#NET enables_C<8> LOC = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8 + +# Patch 3 +#NET enables_D<0> LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<1> LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<2> LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<3> LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<4> LOC = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<5> LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<6> LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<7> LOC = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<8> LOC = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 Index: /firmware/FTU/test_firmware/FTU_test2/ftu_definitions.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test2/ftu_definitions.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test2/ftu_definitions.vhd (revision 9841) @@ -0,0 +1,9 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- use IEEE.NUMERIC_STD.ALL; + +package ftu_array_types is + type dac_array_type is array (0 to 4) of integer range 0 to 2**12 - 1; +end ftu_array_types; Index: /firmware/FTU/test_firmware/FTU_test3/FTU_test3.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test3/FTU_test3.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test3/FTU_test3.vhd (revision 9841) @@ -0,0 +1,104 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 06/07/2010 +-- Design Name: +-- Module Name: FTU_test3 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTU board, test the spi lines +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTU_test3 is + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + --reset : in STD_LOGIC; -- reset + --brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + --brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + --patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + --patch_A_n : IN STD_LOGIC; + --patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + --patch_B_n : IN STD_LOGIC; + --patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + --patch_C_n : IN STD_LOGIC; + --patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + --patch_D_n : IN STD_LOGIC; + --trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + --trig_prim_n : IN STD_LOGIC; + + -- DAC interface + -- miso : IN STD_LOGIC; -- master-in-slave-out + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + --clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC -- chip select or load to DAC + + -- RS-485 interface to FTM + --rx : IN STD_LOGIC; -- serial data from FTM + --tx : OUT STD_LOGIC; -- serial data to FTM + --rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + --tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + --enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + --enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + --enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + --enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + --TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); +end FTU_test3; + +architecture Behavioral of FTU_test3 is + + component FTU_test3_dcm + port( + CLKIN_IN : IN STD_LOGIC; + CLKFX_OUT : OUT STD_LOGIC; + CLKIN_IBUFG_OUT : OUT STD_LOGIC + ); + end component; + + signal ext_clk_sig: STD_LOGIC; + signal clk_5M_sig : STD_LOGIC; + +begin + + Inst_FTU_test3_dcm : FTU_test3_dcm + port map( + CLKIN_IN => ext_clk_sig, + CLKFX_OUT => clk_5M_sig, + CLKIN_IBUFG_OUT => open + ); + + ext_clk_sig <= ext_clk; + + sck <= clk_5M_sig; + mosi <= clk_5M_sig; + cs_ld <= clk_5M_sig; + +end Behavioral; Index: /firmware/FTU/test_firmware/FTU_test3/FTU_test3_dcm.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test3/FTU_test3_dcm.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test3/FTU_test3_dcm.vhd (revision 9841) @@ -0,0 +1,88 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.1 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTU_test1_dcm.vhd +-- /___/ /\ Timestamp : 05/04/2010 17:27:08 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /home/qweitzel/CT3-FACT/fact_repos.svn/FPGA/FTU/test_firmware/FTU_test1_dcm.xaw /home/qweitzel/CT3-FACT/fact_repos.svn/FPGA/FTU/test_firmware/FTU_test1_dcm +--Design Name: FTU_test1_dcm +--Device: xc3s400an-4fgg400 +-- +-- Module FTU_test1_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 6.54 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTU_test3_dcm is + port ( CLKIN_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic); +end FTU_test3_dcm; + +architecture BEHAVIORAL of FTU_test3_dcm is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 20, + CLKFX_MULTIPLY => 2, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>GND_BIT, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>open, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: /firmware/FTU/test_firmware/FTU_test3/FTU_test3_tb.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test3/FTU_test3_tb.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test3/FTU_test3_tb.vhd (revision 9841) @@ -0,0 +1,177 @@ +-------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 06/07/2010 +-- Design Name: +-- Module Name: /home/qweitzel/FPGA/FACT/FTU/test_firmware/FTU_test3/FTU_test3_tb.vhd +-- Project Name: FTU_test3_sim +-- Target Device: +-- Tool versions: +-- Description: Testbench for test3 entity of FACT FTU board +-- +-- VHDL Test Bench Created by ISE for module: FTU_test3 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity FTU_test3_tb is +end FTU_test3_tb; + +architecture behavior of FTU_test3_tb is + + -- Component Declaration for the Unit Under Test (UUT) + + component FTU_test3 + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + --reset : in STD_LOGIC; -- reset + --brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + --brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable address + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + --patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + --patch_A_n : IN STD_LOGIC; + --patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + --patch_B_n : IN STD_LOGIC; + --patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + --patch_C_n : IN STD_LOGIC; + --patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + --patch_D_n : IN STD_LOGIC; + --trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + --trig_prim_n : IN STD_LOGIC; + + -- DAC interface + -- miso : IN STD_LOGIC; -- master-in-slave-out + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + --clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC -- chip select or load to DAC + + -- RS-485 interface to FTM + --rx : IN STD_LOGIC; -- serial data from FTM + --tx : OUT STD_LOGIC; -- serial data to FTM + --rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + --tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + --enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + --enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + --enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + --enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + --TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); + end component; + + --Inputs + signal ext_clk : STD_LOGIC := '0'; + --signal reset : STD_LOGIC := '0'; + --signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); + --signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); + --signal patch_A_p : STD_LOGIC := '0'; + --signal patch_A_n : STD_LOGIC := '0'; + --signal patch_B_p : STD_LOGIC := '0'; + --signal patch_B_n : STD_LOGIC := '0'; + --signal patch_C_p : STD_LOGIC := '0'; + --signal patch_C_n : STD_LOGIC := '0'; + --signal patch_D_p : STD_LOGIC := '0'; + --signal patch_D_n : STD_LOGIC := '0'; + --signal trig_prim_p : STD_LOGIC := '0'; + --signal trig_prim_n : STD_LOGIC := '0'; + -- signal miso : STD_LOGIC := '0'; + --signal rx : STD_LOGIC := '0'; + + --Outputs + --signal enables_A : STD_LOGIC_VECTOR(8 downto 0); + --signal enables_B : STD_LOGIC_VECTOR(8 downto 0); + --signal enables_C : STD_LOGIC_VECTOR(8 downto 0); + --signal enables_D : STD_LOGIC_VECTOR(8 downto 0); + --signal clr : STD_LOGIC; + signal cs_ld : STD_LOGIC; + signal sck : STD_LOGIC; + signal mosi : STD_LOGIC; + --signal tx : STD_LOGIC; + --signal rx_en : STD_LOGIC; + --signal tx_en : STD_LOGIC; + --signal TP_A : STD_LOGIC_VECTOR(11 downto 0); + + -- Clock period definitions + constant ext_clk_period : TIME := 20 ns; + +begin + + -- Instantiate the Unit Under Test (UUT) + uut: FTU_test3 + port map( + ext_clk => ext_clk, + --reset => reset, + --brd_add => brd_add, + --brd_id => brd_id, + --patch_A_p => patch_A_p, + --patch_A_n => patch_A_n, + --patch_B_p => patch_B_p, + --patch_B_n => patch_B_n, + --patch_C_p => patch_C_p, + --patch_C_n => patch_C_n, + --patch_D_p => patch_D_p, + --patch_D_n => patch_D_n, + --trig_prim_p => trig_prim_p, + --trig_prim_n => trig_prim_n, + -- miso => miso, + --rx => rx, + --rx_en => rx_en, + --enables_A => enables_A, + --enables_B => enables_B, + --enables_C => enables_C, + --enables_D => enables_D, + --clr => clr, + cs_ld => cs_ld, + sck => sck, + mosi => mosi + --tx => tx, + --tx_en => tx_en, + --TP_A => TP_A + ); + + -- Clock process definitions + ext_clk_proc: process + begin + ext_clk <= '0'; + wait for ext_clk_period/2; + ext_clk <= '1'; + wait for ext_clk_period/2; + end process ext_clk_proc; + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + wait for 100ms; + + wait for ext_clk_period*10; + + -- insert stimulus here + + wait; + end process stim_proc; + +end; Index: /firmware/FTU/test_firmware/FTU_test3/ftu_board_test3.ucf =================================================================== --- /firmware/FTU/test_firmware/FTU_test3/ftu_board_test3.ucf (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test3/ftu_board_test3.ucf (revision 9841) @@ -0,0 +1,145 @@ +######################################################## +# FTU Board +# FACT Trigger Unit +# +# Pin location constraints +# +# by Patrick Vogler, Quirin Weitzel +# 01 July 2010 +######################################################## + + +#Clock +####################################################### +NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk + + +# RS-485 Interface +####################################################### +#NET rx_en LOC = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver +#NET tx_en LOC = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter +#NET tx LOC = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM +#NET rx LOC = R20 | IOSTANDARD=LVCMOS33; # 485_DI: serial data from FTM + + +# Board ID - inputs +# local board-ID "solder programmable" +####################################################### +#NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0 +#NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1 +#NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2 +#NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3 +#NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4 +#NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5 +#NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6 +#NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7 + + +# Board Addresses +# geographical slot address +####################################################### +#NET brd_add<0> LOC = A15 | IOSTANDARD=LVCMOS33; # ADDR0 +#NET brd_add<1> LOC = B15 | IOSTANDARD=LVCMOS33; # ADDR1 +#NET brd_add<2> LOC = A16 | IOSTANDARD=LVCMOS33; # ADDR2 +#NET brd_add<3> LOC = A17 | IOSTANDARD=LVCMOS33; # ADDR3 +#NET brd_add<4> LOC = A18 | IOSTANDARD=LVCMOS33; # ADDR4 +#NET brd_add<5> LOC = B18 | IOSTANDARD=LVCMOS33; # ADDR5 + + +# DAC SPI Interface +####################################################### +NET mosi LOC = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in +NET sck LOC = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC +NET cs_ld LOC = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC +#NET clr LOC = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC + + +# Testpoints +###################################################### +# on Connector J5 +#NET TP_A<0> LOC = B3 | IOSTANDARD=LVCMOS33; # TP0_0 +#NET TP_A<1> LOC = A3 | IOSTANDARD=LVCMOS33; # TP1_0 +#NET TP_A<2> LOC = A4 | IOSTANDARD=LVCMOS33; # TP2_0 +#NET TP_A<3> LOC = B5 | IOSTANDARD=LVCMOS33; # TP2_0 + +# on Connector J6 +#NET TP_A<4> LOC = A5 | IOSTANDARD=LVCMOS33; # TP4_0 +#NET TP_A<5> LOC = A6 | IOSTANDARD=LVCMOS33; # TP5_0 +#NET TP_A<6> LOC = B7 | IOSTANDARD=LVCMOS33; # TP6_0 +#NET TP_A<7> LOC = A7 | IOSTANDARD=LVCMOS33; # TP7_0 + +# on Connector J7 +#NET TP_A<8> LOC = B11 | IOSTANDARD=LVCMOS33; # TP8_0 +#NET TP_A<9> LOC = A12 | IOSTANDARD=LVCMOS33; # TP9_0 +#NET TP_A<10> LOC = B12 | IOSTANDARD=LVCMOS33; # TP10_0 +#NET TP_A<11> LOC = A14 | IOSTANDARD=LVCMOS33; # TP11_0 + + +# Rate counter LVDS Inputs +###################################################### +# logic signal from first trigger patch +#NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P +#NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N + +# logic signal from second trigger patch +#NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P +#NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N + +# logic signal from third trigger patch +#NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P +#NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N + +# logic signal from fourth trigger patch +#NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P +#NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N + +#The Trigger Primitive: logic signal from n-out-of-4 circuit +#NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+ +#NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P- + + +# Enables +###################################################### +# Patch 0 +#NET enables_A<0> LOC = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 +#NET enables_A<1> LOC = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1 +#NET enables_A<2> LOC = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2 +#NET enables_A<3> LOC = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3 +#NET enables_A<4> LOC = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4 +#NET enables_A<5> LOC = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5 +#NET enables_A<6> LOC = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6 +#NET enables_A<7> LOC = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7 +#NET enables_A<8> LOC = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8 + +## Patch 1 +#NET enables_B<0> LOC = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0 +#NET enables_B<1> LOC = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1 +#NET enables_B<2> LOC = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2 +#NET enables_B<3> LOC = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3 +#NET enables_B<4> LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4 +#NET enables_B<5> LOC = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5 +#NET enables_B<6> LOC = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6 +#NET enables_B<7> LOC = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7 +#NET enables_B<8> LOC = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8 + +# Patch 2 +#NET enables_C<0> LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0 +#NET enables_C<1> LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1 +#NET enables_C<2> LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2 +#NET enables_C<3> LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3 +#NET enables_C<4> LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4 +#NET enables_C<5> LOC = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5 +#NET enables_C<6> LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6 +#NET enables_C<7> LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7 +#NET enables_C<8> LOC = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8 + +# Patch 3 +#NET enables_D<0> LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<1> LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<2> LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<3> LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<4> LOC = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<5> LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<6> LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<7> LOC = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<8> LOC = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 Index: /firmware/FTU/test_firmware/FTU_test4/FTU_test4.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test4/FTU_test4.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test4/FTU_test4.vhd (revision 9841) @@ -0,0 +1,152 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 08/07/2010 +-- Design Name: +-- Module Name: FTU_test4 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTU board, enable tx and put 50kHz clock signal +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTU_test4 is + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + --reset : in STD_LOGIC; -- reset + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + -- miso : IN STD_LOGIC; -- master-in-slave-out + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); +end FTU_test4; + +architecture Behavioral of FTU_test4 is + + component FTU_test4_dcm + port( + CLKIN_IN : IN STD_LOGIC; + CLKFX_OUT : OUT STD_LOGIC; + CLKIN_IBUFG_OUT : OUT STD_LOGIC + ); + end component; + + component Clock_Divider + port( + clock_in : IN STD_LOGIC; + clock_out : OUT STD_LOGIC + ); + end component; + + signal clk_5M_sig : STD_LOGIC; + signal clk_50k_sig : STD_LOGIC; + +begin + + Inst_FTU_test4_dcm : FTU_test4_dcm + port map( + CLKIN_IN => ext_clk, + CLKFX_OUT => clk_5M_sig, + CLKIN_IBUFG_OUT => open + ); + + Inst_Clock_Divider : Clock_Divider + port map ( + clock_in => clk_5M_sig, + clock_out => clk_50k_sig + ); + + tx_en <= '1'; + tx <= clk_50k_sig; + +end Behavioral; + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity Clock_Divider is + port( + clock_in : in std_logic; + clock_out : out std_logic + ); +end entity Clock_Divider; + +architecture RTL of Clock_Divider is + + constant max_count : integer := 5000000/50000; -- for implementation + +begin + + process(clock_in) + variable count : integer range 0 to max_count; + begin + if rising_edge(clock_in) then + if count < max_count/2 then + clock_out <= '0'; + count := count + 1; + elsif count < max_count then + clock_out <= '1'; + count := count + 1; + else + count := 0; + clock_out <= '0'; + end if; + end if; + end process; + +end architecture RTL; Index: /firmware/FTU/test_firmware/FTU_test4/FTU_test4_dcm.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test4/FTU_test4_dcm.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test4/FTU_test4_dcm.vhd (revision 9841) @@ -0,0 +1,88 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.1 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTU_test4_dcm.vhd +-- /___/ /\ Timestamp : 05/04/2010 17:27:08 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /home/qweitzel/CT3-FACT/fact_repos.svn/FPGA/FTU/test_firmware/FTU_test1_dcm.xaw /home/qweitzel/CT3-FACT/fact_repos.svn/FPGA/FTU/test_firmware/FTU_test1_dcm +--Design Name: FTU_test1_dcm +--Device: xc3s400an-4fgg400 +-- +-- Module FTU_test1_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 6.54 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTU_test4_dcm is + port ( CLKIN_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic); +end FTU_test4_dcm; + +architecture BEHAVIORAL of FTU_test4_dcm is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 20, + CLKFX_MULTIPLY => 2, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>GND_BIT, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>open, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: /firmware/FTU/test_firmware/FTU_test4/FTU_test4_tb.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test4/FTU_test4_tb.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test4/FTU_test4_tb.vhd (revision 9841) @@ -0,0 +1,177 @@ +-------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 08/07/2010 +-- Design Name: +-- Module Name: /home/qweitzel/FPGA/FACT/FTU/test_firmware/FTU_test4_tb.vhd +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: Testbench for test4 entity of FACT FTU board +-- +-- VHDL Test Bench Created by ISE for module: FTU_test4 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity FTU_test4_tb is +end FTU_test4_tb; + +architecture behavior of FTU_test4_tb is + + -- Component Declaration for the Unit Under Test (UUT) + + component FTU_test4 + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + --reset : in STD_LOGIC; -- reset + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable address + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + -- miso : IN STD_LOGIC; -- master-in-slave-out + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); + end component; + + --Inputs + signal ext_clk : STD_LOGIC := '0'; + --signal reset : STD_LOGIC := '0'; + signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); + signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); + signal patch_A_p : STD_LOGIC := '0'; + signal patch_A_n : STD_LOGIC := '0'; + signal patch_B_p : STD_LOGIC := '0'; + signal patch_B_n : STD_LOGIC := '0'; + signal patch_C_p : STD_LOGIC := '0'; + signal patch_C_n : STD_LOGIC := '0'; + signal patch_D_p : STD_LOGIC := '0'; + signal patch_D_n : STD_LOGIC := '0'; + signal trig_prim_p : STD_LOGIC := '0'; + signal trig_prim_n : STD_LOGIC := '0'; + -- signal miso : STD_LOGIC := '0'; + signal rx : STD_LOGIC := '0'; + + --Outputs + signal enables_A : STD_LOGIC_VECTOR(8 downto 0); + signal enables_B : STD_LOGIC_VECTOR(8 downto 0); + signal enables_C : STD_LOGIC_VECTOR(8 downto 0); + signal enables_D : STD_LOGIC_VECTOR(8 downto 0); + signal clr : STD_LOGIC; + signal cs_ld : STD_LOGIC; + signal sck : STD_LOGIC; + signal mosi : STD_LOGIC; + signal tx : STD_LOGIC; + signal rx_en : STD_LOGIC; + signal tx_en : STD_LOGIC; + signal TP_A : STD_LOGIC_VECTOR(11 downto 0); + + -- Clock period definitions + constant ext_clk_period : TIME := 20 ns; + +begin + + -- Instantiate the Unit Under Test (UUT) + uut: FTU_test4 + port map( + ext_clk => ext_clk, + --reset => reset, + brd_add => brd_add, + brd_id => brd_id, + patch_A_p => patch_A_p, + patch_A_n => patch_A_n, + patch_B_p => patch_B_p, + patch_B_n => patch_B_n, + patch_C_p => patch_C_p, + patch_C_n => patch_C_n, + patch_D_p => patch_D_p, + patch_D_n => patch_D_n, + trig_prim_p => trig_prim_p, + trig_prim_n => trig_prim_n, + -- miso => miso, + rx => rx, + rx_en => rx_en, + enables_A => enables_A, + enables_B => enables_B, + enables_C => enables_C, + enables_D => enables_D, + clr => clr, + cs_ld => cs_ld, + sck => sck, + mosi => mosi, + tx => tx, + tx_en => tx_en, + TP_A => TP_A + ); + + -- Clock process definitions + ext_clk_proc: process + begin + ext_clk <= '0'; + wait for ext_clk_period/2; + ext_clk <= '1'; + wait for ext_clk_period/2; + end process ext_clk_proc; + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + wait for 100ms; + + wait for ext_clk_period*10; + + -- insert stimulus here + + wait; + end process stim_proc; + +end; Index: /firmware/FTU/test_firmware/FTU_test4/ftu_board_test4.ucf =================================================================== --- /firmware/FTU/test_firmware/FTU_test4/ftu_board_test4.ucf (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test4/ftu_board_test4.ucf (revision 9841) @@ -0,0 +1,145 @@ +######################################################## +# FTU Board +# FACT Trigger Unit +# +# Pin location constraints +# +# by Patrick Vogler, Quirin Weitzel +# 08 July 2010 +######################################################## + + +#Clock +####################################################### +NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk + + +# RS-485 Interface +####################################################### +#NET rx_en LOC = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver +NET tx_en LOC = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter +NET tx LOC = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM +#NET rx LOC = R20 | IOSTANDARD=LVCMOS33; # 485_DI: serial data from FTM + + +# Board ID - inputs +# local board-ID "solder programmable" +####################################################### +#NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0 +#NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1 +#NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2 +#NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3 +#NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4 +#NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5 +#NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6 +#NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7 + + +# Board Addresses +# geographical slot address +####################################################### +#NET brd_add<0> LOC = A15 | IOSTANDARD=LVCMOS33; # ADDR0 +#NET brd_add<1> LOC = B15 | IOSTANDARD=LVCMOS33; # ADDR1 +#NET brd_add<2> LOC = A16 | IOSTANDARD=LVCMOS33; # ADDR2 +#NET brd_add<3> LOC = A17 | IOSTANDARD=LVCMOS33; # ADDR3 +#NET brd_add<4> LOC = A18 | IOSTANDARD=LVCMOS33; # ADDR4 +#NET brd_add<5> LOC = B18 | IOSTANDARD=LVCMOS33; # ADDR5 + + +# DAC SPI Interface +####################################################### +#NET mosi LOC = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in +#NET sck LOC = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC +#NET cs_ld LOC = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC +#NET clr LOC = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC + + +# Testpoints +###################################################### +# on Connector J5 +#NET TP_A<0> LOC = B3 | IOSTANDARD=LVCMOS33; # TP0_0 +#NET TP_A<1> LOC = A3 | IOSTANDARD=LVCMOS33; # TP1_0 +#NET TP_A<2> LOC = A4 | IOSTANDARD=LVCMOS33; # TP2_0 +#NET TP_A<3> LOC = B5 | IOSTANDARD=LVCMOS33; # TP2_0 + +# on Connector J6 +#NET TP_A<4> LOC = A5 | IOSTANDARD=LVCMOS33; # TP4_0 +#NET TP_A<5> LOC = A6 | IOSTANDARD=LVCMOS33; # TP5_0 +#NET TP_A<6> LOC = B7 | IOSTANDARD=LVCMOS33; # TP6_0 +#NET TP_A<7> LOC = A7 | IOSTANDARD=LVCMOS33; # TP7_0 + +# on Connector J7 +#NET TP_A<8> LOC = B11 | IOSTANDARD=LVCMOS33; # TP8_0 +#NET TP_A<9> LOC = A12 | IOSTANDARD=LVCMOS33; # TP9_0 +#NET TP_A<10> LOC = B12 | IOSTANDARD=LVCMOS33; # TP10_0 +#NET TP_A<11> LOC = A14 | IOSTANDARD=LVCMOS33; # TP11_0 + + +# Rate counter LVDS Inputs +###################################################### +# logic signal from first trigger patch +#NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P +#NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N + +# logic signal from second trigger patch +#NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P +#NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N + +# logic signal from third trigger patch +#NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P +#NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N + +# logic signal from fourth trigger patch +#NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P +#NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N + +#The Trigger Primitive: logic signal from n-out-of-4 circuit +#NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+ +#NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P- + + +# Enables +###################################################### +# Patch 0 +#NET enables_A<0> LOC = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 +#NET enables_A<1> LOC = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1 +#NET enables_A<2> LOC = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2 +#NET enables_A<3> LOC = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3 +#NET enables_A<4> LOC = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4 +#NET enables_A<5> LOC = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5 +#NET enables_A<6> LOC = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6 +#NET enables_A<7> LOC = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7 +#NET enables_A<8> LOC = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8 + +## Patch 1 +#NET enables_B<0> LOC = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0 +#NET enables_B<1> LOC = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1 +#NET enables_B<2> LOC = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2 +#NET enables_B<3> LOC = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3 +#NET enables_B<4> LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4 +#NET enables_B<5> LOC = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5 +#NET enables_B<6> LOC = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6 +#NET enables_B<7> LOC = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7 +#NET enables_B<8> LOC = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8 + +# Patch 2 +#NET enables_C<0> LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0 +#NET enables_C<1> LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1 +#NET enables_C<2> LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2 +#NET enables_C<3> LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3 +#NET enables_C<4> LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4 +#NET enables_C<5> LOC = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5 +#NET enables_C<6> LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6 +#NET enables_C<7> LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7 +#NET enables_C<8> LOC = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8 + +# Patch 3 +#NET enables_D<0> LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<1> LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<2> LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<3> LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<4> LOC = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<5> LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<6> LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<7> LOC = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +#NET enables_D<8> LOC = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 Index: /firmware/FTU/test_firmware/FTU_test5/FTU_test5.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test5/FTU_test5.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test5/FTU_test5.vhd (revision 9841) @@ -0,0 +1,173 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 07/14/2010 +-- Design Name: +-- Module Name: FTU_test5 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTU board, set thresholds and enables +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ftu_definitions_test5; +USE ftu_definitions_test5.ftu_array_types.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +entity FTU_test5 is + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : in STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); +end FTU_test5; + + +architecture Behavioral of FTU_test5 is + + component FTU_test5_dac_dcm + port( + CLKIN_IN : IN STD_LOGIC; + RST_IN : IN STD_LOGIC; + CLKFX_OUT : OUT STD_LOGIC; + CLKIN_IBUFG_OUT : OUT STD_LOGIC; + LOCKED_OUT : OUT STD_LOGIC + ); + end component; + + component FTU_test5_dac_control + port( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + dacs : IN dac_array_type; + clr : OUT STD_LOGIC; + mosi : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + cs_ld : OUT STD_LOGIC + ); + end component; + + signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up + signal clk_50M_sig : STD_LOGIC; + + --signal enable_sig : enable_array_type := DEFAULT_ENABLE; + signal enable_sig : enable_array_type; + signal dac_array_sig : dac_array_type; + + type FTU_test5_StateType is (Running); + signal FTU_test5_State, FTU_test5_NextState: FTU_test5_StateType; + +begin + + Inst_FTU_test5_dac_dcm : FTU_test5_dac_dcm + port map( + CLKIN_IN => ext_clk, + RST_IN => reset_sig, + CLKFX_OUT => clk_50M_sig, + CLKIN_IBUFG_OUT => open, + LOCKED_OUT => open + ); + + Inst_FTU_test5_dac_control : FTU_test5_dac_control + port map( + clk => clk_50M_sig, + reset => reset_sig, + dacs => dac_array_sig, + clr => clr, + mosi => mosi, + sck => sck, + cs_ld => cs_ld + ); + + enable_sig <= ("0000000000000000","0000000000000000","0000000000000000","0000000000000000") when (brd_add(3 downto 0) = "0000") else + ("0000000101010101","0000000101010101","0000000101010101","0000000101010101") when (brd_add(3 downto 0) = "0001") else + ("0000000010101010","0000000010101010","0000000010101010","0000000010101010") when (brd_add(3 downto 0) = "0010") else + ("0000000000000001","0000000000000001","0000000000000001","0000000000000001") when (brd_add(3 downto 0) = "0011") else + ("0000000000000011","0000000000000011","0000000000000011","0000000000000011") when (brd_add(3 downto 0) = "0100") else + ("0000000000001111","0000000000001111","0000000000001111","0000000000001111") when (brd_add(3 downto 0) = "0101") else + ("0000000000111111","0000000000111111","0000000000111111","0000000000111111") when (brd_add(3 downto 0) = "0110") else + ("0000000111111111","0000000111111111","0000000111111111","0000000111111111") when (brd_add(3 downto 0) = "0111") else + ("0000000111110000","0000000111110000","0000000111110000","0000000111110000") when (brd_add(3 downto 0) = "1000") else + ("0000000000011111","0000000000011111","0000000000011111","0000000000011111") when (brd_add(3 downto 0) = "1001") else + DEFAULT_ENABLE; + + dac_array_sig <= (100,100,100,100,0,0,0,100) when (brd_add(5 downto 4) = "00") else + (200,200,200,200,0,0,0,100) when (brd_add(5 downto 4) = "01") else + (300,300,300,300,0,0,0,100) when (brd_add(5 downto 4) = "10") else + DEFAULT_DAC; + + enables_A <= enable_sig(0)(8 downto 0); + enables_B <= enable_sig(1)(8 downto 0); + enables_C <= enable_sig(2)(8 downto 0); + enables_D <= enable_sig(3)(8 downto 0); + + --FTU main state machine (two-process implementation) + + FTU_test5_Registers: process (ext_clk) + begin + if Rising_edge(ext_clk) then + FTU_test5_State <= FTU_test5_NextState; + end if; + end process FTU_test5_Registers; + + FTU_test5_C_logic: process (FTU_test5_State) + begin + FTU_test5_NextState <= FTU_test5_State; + case FTU_test5_State is + when Running => + reset_sig <= '0'; + end case; + end process FTU_test5_C_logic; + +end Behavioral; Index: /firmware/FTU/test_firmware/FTU_test5/FTU_test5_dac_control.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test5/FTU_test5_dac_control.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test5/FTU_test5_dac_control.vhd (revision 9841) @@ -0,0 +1,132 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 07/14/2010 +-- Design Name: +-- Module Name: FTU_test5_dac_control - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ftu_definitions_test5; +USE ftu_definitions_test5.ftu_array_types.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTU_test5_dac_control is + port( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + dacs : IN dac_array_type; + clr : OUT STD_LOGIC; + mosi : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + cs_ld : out STD_LOGIC + ); +end FTU_test5_dac_control; + +architecture Behavioral of FTU_test5_dac_control is + + component FTU_test5_spi_interface + port( + clk_50MHz : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + config_ready : OUT std_logic; + config_started : OUT std_logic; + dac_cs : OUT std_logic; + mosi : OUT std_logic; + sclk : OUT std_logic; + miso : INOUT std_logic + ); + end component; + + signal clk_sig : std_logic; + signal reset_sig : std_logic; + + signal clr_sig : std_logic; + signal mosi_sig : std_logic := '0'; + signal serial_clock_sig : std_logic; + signal dac_cs_sig : std_logic; + + signal config_start_sig : std_logic := '0'; + signal config_ready_sig : std_logic; + signal config_started_sig : std_logic := '0'; + --signal dac_array_sig : dac_array_type := DEFAULT_DAC; + signal dac_array_sig : dac_array_type; + + -- Build an enumerated type for the state machine + type state_type is (START, WAITING, STOP); + + -- Register to hold the current state + signal dac_ctrl_state, next_state : state_type; + +begin + + reset_sig <= reset; + clk_sig <= clk; + mosi <= mosi_sig; + sck <= serial_clock_sig; + cs_ld <= dac_cs_sig; + dac_array_sig <= dacs; + + -- FSM for dac control: first process + FSM_Registers: process(clk_sig, reset_sig) + begin + if reset_sig = '1' then + dac_ctrl_state <= START; + elsif Rising_edge(clk_sig) then + dac_ctrl_state <= next_state; + end if; + end process; + + -- FSM for dac control: second process + FSM_logic: process(dac_ctrl_state, config_ready_sig) + begin + next_state <= dac_ctrl_state; + case dac_ctrl_state is + when START => + config_start_sig <= '1'; + next_state <= WAITING; + when WAITING => + config_start_sig <= '1'; + if (config_ready_sig = '1') then + next_state <= STOP; + else + next_state <= WAITING; + end if; + when STOP => + config_start_sig <= '0'; + end case; + end process; + + Inst_FTU_test5_spi_interface : FTU_test5_spi_interface + port map( + clk_50MHz => clk_sig, + config_start => config_start_sig, + dac_array => dac_array_sig, + config_ready => config_ready_sig, + config_started => config_started_sig, + dac_cs => dac_cs_sig, + mosi => mosi_sig, + sclk => serial_clock_sig, + miso => open + ); + +end Behavioral; Index: /firmware/FTU/test_firmware/FTU_test5/FTU_test5_dac_dcm.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test5/FTU_test5_dac_dcm.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test5/FTU_test5_dac_dcm.vhd (revision 9841) @@ -0,0 +1,90 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.1 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTU_dac_dcm.vhd +-- /___/ /\ Timestamp : 01/20/2010 16:36:17 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /home/qweitzel/FPGA/FACT/FTU/source/ip_cores/FTU_dac_dcm.xaw /home/qweitzel/FPGA/FACT/FTU/source/ip_cores/FTU_dac_dcm +--Design Name: FTU_dac_dcm +--Device: xc3s400an-4fgg400 +-- +-- Module FTU_dac_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 6.54 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTU_test5_dac_dcm is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end FTU_test5_dac_dcm; + +architecture BEHAVIORAL of FTU_test5_dac_dcm is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 2, + CLKFX_MULTIPLY => 2, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: /firmware/FTU/test_firmware/FTU_test5/FTU_test5_spi_clock_gen.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test5/FTU_test5_spi_clock_gen.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test5/FTU_test5_spi_clock_gen.vhd (revision 9841) @@ -0,0 +1,47 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_clock_generator.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 14:49:19 01.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY FTU_test5_spi_clock_generator IS + GENERIC( + CLK_DIVIDER : integer := 25 --2 MHz @ 50 MHz + ); + PORT( + clk : IN std_logic; + sclk : OUT std_logic := '0' + ); +END FTU_test5_spi_clock_generator; + +ARCHITECTURE beha OF FTU_test5_spi_clock_generator IS + +BEGIN + + spi_clk_proc: process (clk) + variable Z: integer range 0 to clk_divider - 1; + begin + if rising_edge(clk) then + if (Z < clk_divider - 1) then + Z := Z + 1; + else + Z := 0; + end if; + if (Z = 0) then + sclk <= '1'; + end if; + if (Z = clk_divider / 2) then + sclk <= '0'; + end if; + end if; + end process spi_clk_proc; + +END ARCHITECTURE beha; Index: /firmware/FTU/test_firmware/FTU_test5/FTU_test5_spi_controller.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test5/FTU_test5_spi_controller.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test5/FTU_test5_spi_controller.vhd (revision 9841) @@ -0,0 +1,81 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_controller.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 10:37:20 12.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- modified by Q. Weitzel +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY FTU_test5_spi_controller IS + PORT( + clk : IN std_logic; + miso : INOUT std_logic := 'Z'; + mosi : OUT std_logic := '0'; + dac_id : IN std_logic_vector (2 DOWNTO 0); + --data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + data : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); + dac_cs : OUT std_logic := '1'; + dac_start : IN std_logic; + dac_ready : OUT std_logic := '0' + ); +END FTU_test5_spi_controller ; + +ARCHITECTURE beha OF FTU_test5_spi_controller IS + + type TYPE_SPI_STATE is (SPI_IDLE, SPI_LOAD_DAC, SPI_LOAD_COMMAND); + + signal spi_state : TYPE_SPI_STATE := SPI_IDLE; + signal spi_cycle_cnt : integer range 0 to 25 := 0; + signal shift_reg : std_logic_vector (23 downto 0) := (others => '0'); + signal data_reg : std_logic_vector (15 downto 0) := (others => '0'); + +BEGIN + + spi_write_proc: process (clk) + begin + if falling_edge(clk) then + dac_cs <= '1'; + miso <= 'Z'; + mosi <= '0'; + --data <= (others => 'Z'); + case spi_state is + when SPI_IDLE => + if (dac_start = '1') then + dac_ready <= '0'; + spi_state <= SPI_LOAD_COMMAND; + end if; + + when SPI_LOAD_COMMAND => + spi_cycle_cnt <= 0; + if (dac_start = '1') then + shift_reg <= "0011" & '0' & dac_id & data(11 downto 0) & "0000"; + spi_state <= SPI_LOAD_DAC; + end if; + + -- start loading DACs + when SPI_LOAD_DAC => + dac_cs <= '0'; + if (spi_cycle_cnt < 24) then + mosi <= shift_reg(23); + shift_reg <= shift_reg(22 downto 0) & shift_reg(23); + dac_ready <= '0'; + spi_cycle_cnt <= spi_cycle_cnt + 1; + spi_state <= SPI_LOAD_DAC; + else + dac_cs <= '1'; + dac_ready <= '1'; + spi_state <= SPI_IDLE; + end if; + end case; + end if; + end process spi_write_proc; + +END ARCHITECTURE beha; Index: /firmware/FTU/test_firmware/FTU_test5/FTU_test5_spi_distributor.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test5/FTU_test5_spi_distributor.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test5/FTU_test5_spi_distributor.vhd (revision 9841) @@ -0,0 +1,91 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_distributor.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 09:24:21 23.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- modified by Q. Weitzel +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +library ftu_definitions_test5; +USE ftu_definitions_test5.ftu_array_types.all; + +ENTITY FTU_test5_spi_distributor IS + PORT( + clk : IN std_logic; -- 50MHz + config_start : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0'; + dac_array : IN dac_array_type; + dac_config_start : OUT std_logic := '0'; + dac_config_ready : IN std_logic; + dac_id : OUT std_logic_vector(2 downto 0) := (others => '0'); + --data : INOUT std_logic_vector(15 downto 0) := (others => 'Z') + data : OUT std_logic_vector(15 downto 0) := (others => '0') + ); +END ENTITY FTU_test5_spi_distributor; + +ARCHITECTURE beha OF FTU_test5_spi_distributor IS + + type TYPE_SPI_DISTRIBUTION_STATE is (INIT, IDLE, CONFIG_DAC); + + signal spi_distr_state : TYPE_SPI_DISTRIBUTION_STATE := INIT; + signal dac_id_cnt : integer range 0 to 7 := 0; + +BEGIN + + spi_distribute_proc: process (clk) + begin + + if rising_edge(clk) then + --data <= (others => 'Z'); + data <= (others => '0'); + case spi_distr_state is + when INIT => + --data <= (others => 'Z'); + data <= (others => '0'); + spi_distr_state <= IDLE; + when IDLE => + --data <= (others => 'Z'); + data <= (others => '0'); + -- start DAC configuration + if (config_start = '1') then + config_started <= '1'; + config_ready <= '0'; + dac_config_start <= '1'; + dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); + data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); + spi_distr_state <= CONFIG_DAC; + end if; + + -- DAC configuration + when CONFIG_DAC => + dac_config_start <= '1'; + dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); + data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); + if (dac_config_ready = '1') then + dac_config_start <= '0'; + if (dac_id_cnt < 7) then + dac_id_cnt <= dac_id_cnt + 1; + dac_config_start <= '1'; + spi_distr_state <= CONFIG_DAC; + else + dac_id_cnt <= 0; + config_started <= '0'; + config_ready <= '1'; + spi_distr_state <= IDLE; + end if; + end if; + end case; + end if; + + end process spi_distribute_proc; + +END ARCHITECTURE beha; + Index: /firmware/FTU/test_firmware/FTU_test5/FTU_test5_spi_interface.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test5/FTU_test5_spi_interface.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test5/FTU_test5_spi_interface.vhd (revision 9841) @@ -0,0 +1,138 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 07/14/2010 +-- Design Name: +-- Module Name: FTU_test5_spi_interface - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Based on VHDL Entity FACT_FAD_lib.spi_interface.symbol +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ftu_definitions_test5; +USE ftu_definitions_test5.ftu_array_types.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +ENTITY FTU_test5_spi_interface IS + PORT( + clk_50MHz : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + config_ready : OUT std_logic; + config_started : OUT std_logic := '0'; + dac_cs : OUT std_logic; + mosi : OUT std_logic := '0'; + sclk : OUT std_logic; + miso : INOUT std_logic + ); +END FTU_test5_spi_interface; + +ARCHITECTURE struct OF FTU_test5_spi_interface IS + + -- Internal signal declarations + SIGNAL dac_config_ready : std_logic; + SIGNAL dac_config_start : std_logic; + SIGNAL dac_id : std_logic_vector(2 DOWNTO 0); + SIGNAL data : std_logic_vector(15 DOWNTO 0); + + -- Implicit buffer signal declarations + SIGNAL sclk_internal : std_logic; + + + -- Component Declarations + COMPONENT FTU_test5_spi_clock_generator + GENERIC ( + CLK_DIVIDER : integer := 25 --2 MHz @ 50 MHz + ); + PORT ( + clk : IN std_logic; + sclk : OUT std_logic := '0' + ); + END COMPONENT; + + COMPONENT FTU_test5_spi_controller + PORT ( + clk : IN std_logic; + dac_id : IN std_logic_vector (2 DOWNTO 0); + dac_start : IN std_logic; + dac_cs : OUT std_logic := '1'; + dac_ready : OUT std_logic := '0'; + mosi : OUT std_logic := '0'; + --data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + data : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); + miso : INOUT std_logic := 'Z' + ); + END COMPONENT; + + COMPONENT FTU_test5_spi_distributor + PORT ( + clk : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + dac_config_ready : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0'; + dac_config_start : OUT std_logic := '0'; + dac_id : OUT std_logic_vector (2 DOWNTO 0) := (others => '0'); + --data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z') + data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') + ); + END COMPONENT; + +BEGIN + + -- Instance port mappings. + Inst_FTU_test5_spi_clock_generator : FTU_test5_spi_clock_generator + GENERIC MAP ( + CLK_DIVIDER => 25 --2 MHz @ 50 MHz + ) + PORT MAP ( + clk => clk_50MHz, + sclk => sclk_internal + ); + + Inst_FTU_test5_spi_controller : FTU_test5_spi_controller + PORT MAP ( + clk => sclk_internal, + miso => miso, + mosi => mosi, + dac_id => dac_id, + data => data, + dac_cs => dac_cs, + dac_start => dac_config_start, + dac_ready => dac_config_ready + ); + + Inst_FTU_test5_spi_distributor : FTU_test5_spi_distributor + PORT MAP ( + clk => sclk_internal, + config_start => config_start, + config_ready => config_ready, + config_started => config_started, + dac_array => dac_array, + dac_config_start => dac_config_start, + dac_config_ready => dac_config_ready, + dac_id => dac_id, + data => data + ); + + -- Implicit buffered output assignments + sclk <= sclk_internal; + +END struct; Index: /firmware/FTU/test_firmware/FTU_test5/FTU_test5_tb.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test5/FTU_test5_tb.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test5/FTU_test5_tb.vhd (revision 9841) @@ -0,0 +1,180 @@ +-------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 07/14/2010 +-- Design Name: +-- Module Name: FTU_test5_tb.vhd +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: Testbench for test5 entity of FACT FTU board +-- +-- VHDL Test Bench Created by ISE for module: FTU_test5 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-- +-- based on testbench for FTU_test1 +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity FTU_test5_tb is +end FTU_test5_tb; + +architecture behavior of FTU_test5_tb is + + -- Component Declaration for the Unit Under Test (UUT) + + component FTU_test5 + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + --reset : in STD_LOGIC; -- reset + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable address + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + -- miso : IN STD_LOGIC; -- master-in-slave-out + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); + end component; + + --Inputs + signal ext_clk : STD_LOGIC := '0'; + --signal reset : STD_LOGIC := '0'; + signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := "000001"; + signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); + signal patch_A_p : STD_LOGIC := '0'; + signal patch_A_n : STD_LOGIC := '0'; + signal patch_B_p : STD_LOGIC := '0'; + signal patch_B_n : STD_LOGIC := '0'; + signal patch_C_p : STD_LOGIC := '0'; + signal patch_C_n : STD_LOGIC := '0'; + signal patch_D_p : STD_LOGIC := '0'; + signal patch_D_n : STD_LOGIC := '0'; + signal trig_prim_p : STD_LOGIC := '0'; + signal trig_prim_n : STD_LOGIC := '0'; + -- signal miso : STD_LOGIC := '0'; + signal rx : STD_LOGIC := '0'; + + --Outputs + signal enables_A : STD_LOGIC_VECTOR(8 downto 0); + signal enables_B : STD_LOGIC_VECTOR(8 downto 0); + signal enables_C : STD_LOGIC_VECTOR(8 downto 0); + signal enables_D : STD_LOGIC_VECTOR(8 downto 0); + signal clr : STD_LOGIC; + signal cs_ld : STD_LOGIC; + signal sck : STD_LOGIC; + signal mosi : STD_LOGIC; + signal tx : STD_LOGIC; + signal rx_en : STD_LOGIC; + signal tx_en : STD_LOGIC; + signal TP_A : STD_LOGIC_VECTOR(11 downto 0); + + -- Clock period definitions + constant ext_clk_period : TIME := 20 ns; + +begin + + -- Instantiate the Unit Under Test (UUT) + uut: FTU_test5 + port map( + ext_clk => ext_clk, + --reset => reset, + brd_add => brd_add, + brd_id => brd_id, + patch_A_p => patch_A_p, + patch_A_n => patch_A_n, + patch_B_p => patch_B_p, + patch_B_n => patch_B_n, + patch_C_p => patch_C_p, + patch_C_n => patch_C_n, + patch_D_p => patch_D_p, + patch_D_n => patch_D_n, + trig_prim_p => trig_prim_p, + trig_prim_n => trig_prim_n, + -- miso => miso, + rx => rx, + rx_en => rx_en, + enables_A => enables_A, + enables_B => enables_B, + enables_C => enables_C, + enables_D => enables_D, + clr => clr, + cs_ld => cs_ld, + sck => sck, + mosi => mosi, + tx => tx, + tx_en => tx_en, + TP_A => TP_A + ); + + -- Clock process definitions + ext_clk_proc: process + begin + ext_clk <= '0'; + wait for ext_clk_period/2; + ext_clk <= '1'; + wait for ext_clk_period/2; + end process ext_clk_proc; + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + wait for 100ms; + + wait for ext_clk_period*10; + + -- insert stimulus here + + wait; + end process stim_proc; + +end; Index: /firmware/FTU/test_firmware/FTU_test5/ftu_board_test5.ucf =================================================================== --- /firmware/FTU/test_firmware/FTU_test5/ftu_board_test5.ucf (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test5/ftu_board_test5.ucf (revision 9841) @@ -0,0 +1,145 @@ +######################################################## +# FTU Board +# FACT Trigger Unit +# +# Pin location constraints +# +# by Patrick Vogler, Quirin Weitzel +# 14 July 2010 +######################################################## + + +#Clock +####################################################### +NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk + + +# RS-485 Interface +####################################################### +#NET rx_en LOC = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver +#NET tx_en LOC = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter +#NET tx LOC = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM +#NET rx LOC = R20 | IOSTANDARD=LVCMOS33; # 485_DI: serial data from FTM + + +# Board ID - inputs +# local board-ID "solder programmable" +####################################################### +#NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0 +#NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1 +#NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2 +#NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3 +#NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4 +#NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5 +#NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6 +#NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7 + + +# Board Addresses +# geographical slot address +####################################################### +NET brd_add<0> LOC = A15 | IOSTANDARD=LVCMOS33; # ADDR0 +NET brd_add<1> LOC = B15 | IOSTANDARD=LVCMOS33; # ADDR1 +NET brd_add<2> LOC = A16 | IOSTANDARD=LVCMOS33; # ADDR2 +NET brd_add<3> LOC = A17 | IOSTANDARD=LVCMOS33; # ADDR3 +NET brd_add<4> LOC = A18 | IOSTANDARD=LVCMOS33; # ADDR4 +NET brd_add<5> LOC = B18 | IOSTANDARD=LVCMOS33; # ADDR5 + + +# DAC SPI Interface +####################################################### +NET mosi LOC = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in +NET sck LOC = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC +NET cs_ld LOC = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC +NET clr LOC = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC + + +# Testpoints +###################################################### +# on Connector J5 +#NET TP_A<0> LOC = B3 | IOSTANDARD=LVCMOS33; # TP0_0 +#NET TP_A<1> LOC = A3 | IOSTANDARD=LVCMOS33; # TP1_0 +#NET TP_A<2> LOC = A4 | IOSTANDARD=LVCMOS33; # TP2_0 +#NET TP_A<3> LOC = B5 | IOSTANDARD=LVCMOS33; # TP2_0 + +# on Connector J6 +#NET TP_A<4> LOC = A5 | IOSTANDARD=LVCMOS33; # TP4_0 +#NET TP_A<5> LOC = A6 | IOSTANDARD=LVCMOS33; # TP5_0 +#NET TP_A<6> LOC = B7 | IOSTANDARD=LVCMOS33; # TP6_0 +#NET TP_A<7> LOC = A7 | IOSTANDARD=LVCMOS33; # TP7_0 + +# on Connector J7 +#NET TP_A<8> LOC = B11 | IOSTANDARD=LVCMOS33; # TP8_0 +#NET TP_A<9> LOC = A12 | IOSTANDARD=LVCMOS33; # TP9_0 +#NET TP_A<10> LOC = B12 | IOSTANDARD=LVCMOS33; # TP10_0 +#NET TP_A<11> LOC = A14 | IOSTANDARD=LVCMOS33; # TP11_0 + + +# Rate counter LVDS Inputs +###################################################### +# logic signal from first trigger patch +#NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P +#NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N + +# logic signal from second trigger patch +#NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P +#NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N + +# logic signal from third trigger patch +#NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P +#NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N + +# logic signal from fourth trigger patch +#NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P +#NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N + +#The Trigger Primitive: logic signal from n-out-of-4 circuit +#NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+ +#NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P- + + +# Enables +###################################################### +# Patch 0 +NET enables_A<0> LOC = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 +NET enables_A<1> LOC = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1 +NET enables_A<2> LOC = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2 +NET enables_A<3> LOC = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3 +NET enables_A<4> LOC = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4 +NET enables_A<5> LOC = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5 +NET enables_A<6> LOC = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6 +NET enables_A<7> LOC = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7 +NET enables_A<8> LOC = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8 + +## Patch 1 +NET enables_B<0> LOC = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0 +NET enables_B<1> LOC = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1 +NET enables_B<2> LOC = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2 +NET enables_B<3> LOC = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3 +NET enables_B<4> LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4 +NET enables_B<5> LOC = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5 +NET enables_B<6> LOC = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6 +NET enables_B<7> LOC = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7 +NET enables_B<8> LOC = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8 + +# Patch 2 +NET enables_C<0> LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0 +NET enables_C<1> LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1 +NET enables_C<2> LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2 +NET enables_C<3> LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3 +NET enables_C<4> LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4 +NET enables_C<5> LOC = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5 +NET enables_C<6> LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6 +NET enables_C<7> LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7 +NET enables_C<8> LOC = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8 + +# Patch 3 +NET enables_D<0> LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<1> LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<2> LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<3> LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<4> LOC = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<5> LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<6> LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<7> LOC = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<8> LOC = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 Index: /firmware/FTU/test_firmware/FTU_test5/ftu_definitions_test5.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test5/ftu_definitions_test5.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test5/ftu_definitions_test5.vhd (revision 9841) @@ -0,0 +1,18 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- use IEEE.NUMERIC_STD.ALL; + +package ftu_array_types is + + type enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0); + constant DEFAULT_ENABLE : enable_array_type := ("0000000111111111", --patch A + "0000000111111111", --patch B + "0000000111111111", --patch C + "0000000111111111");--patch D + + type dac_array_type is array (0 to 7) of integer range 0 to 2**12 - 1; + constant DEFAULT_DAC : dac_array_type := (500, 500, 500, 500, 0, 0, 0, 100); + +end ftu_array_types; Index: /firmware/FTU/test_firmware/FTU_test6/FTU_test6.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test6/FTU_test6.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test6/FTU_test6.vhd (revision 9841) @@ -0,0 +1,256 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 07/30/2010 +-- Design Name: +-- Module Name: FTU_test6 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTU board, set enables via RS485 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ftu_definitions_test6; +USE ftu_definitions_test6.ftu_array_types.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +entity FTU_test6 is + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : in STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); +end FTU_test6; + + +architecture Behavioral of FTU_test6 is + + component FTU_test6_dcm + port( + CLKIN_IN : IN STD_LOGIC; + RST_IN : IN STD_LOGIC; + CLKFX_OUT : OUT STD_LOGIC; + CLKIN_IBUFG_OUT : OUT STD_LOGIC; + LOCKED_OUT : OUT STD_LOGIC + ); + end component; + + component FTU_test6_rs485_interface + GENERIC( + CLOCK_FREQUENCY : integer := 50000000; -- Hertz + BAUD_RATE : integer := 250000 -- bits / sec + ); + PORT( + clk : IN std_logic; + -- RS485 + rx_d : IN std_logic; + rx_en : OUT std_logic; + tx_d : OUT std_logic; + tx_en : OUT std_logic; + -- FPGA + rx_data : OUT std_logic_vector(7 DOWNTO 0); + rx_busy : OUT std_logic := '0'; + rx_valid : OUT std_logic := '0'; + tx_data : IN std_logic_vector(7 DOWNTO 0); + tx_busy : OUT std_logic := '0'; + tx_start : IN std_logic + ); + end component; + + signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up + signal clk_50M_sig : STD_LOGIC; + + signal enable_sig : enable_array_type := DEFAULT_ENABLE; + + signal rx_en_sig : STD_LOGIC := '0'; + signal tx_en_sig : STD_LOGIC := '0'; + signal rx_sig : STD_LOGIC; + signal tx_sig : STD_LOGIC := 'X'; + signal rx_data_sig : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); + signal rx_busy_sig : STD_LOGIC; + signal rx_valid_sig : STD_LOGIC; + + type FTU_test6_StateType is (INIT, RUN1, RUN2, RUN3, RUN4); + signal FTU_test6_State, FTU_test6_NextState: FTU_test6_StateType; + +begin + + Inst_FTU_test6_dcm : FTU_test6_dcm + port map( + CLKIN_IN => ext_clk, + RST_IN => reset_sig, + CLKFX_OUT => clk_50M_sig, + CLKIN_IBUFG_OUT => open, + LOCKED_OUT => open + ); + + Inst_FTU_test6_rs485_interface : FTU_test6_rs485_interface + generic map( + CLOCK_FREQUENCY => 50000000, + BAUD_RATE => 10000000 --simulation + --BAUD_RATE => 19600 --implement + ) + port map( + clk => clk_50M_sig, + -- RS485 + rx_d => rx_sig, + rx_en => rx_en_sig, + tx_d => tx_sig, + tx_en => tx_en_sig, + -- FPGA + rx_data => rx_data_sig, + rx_busy => rx_busy_sig, + rx_valid => rx_valid_sig, + tx_data => (others => '0'), + tx_busy => open, + tx_start => '0' + ); + + enables_A <= enable_sig(0)(8 downto 0); + enables_B <= enable_sig(1)(8 downto 0); + enables_C <= enable_sig(2)(8 downto 0); + enables_D <= enable_sig(3)(8 downto 0); + + rx_en <= rx_en_sig; + tx_en <= tx_en_sig; + tx <= tx_sig; + rx_sig <= rx; + + --FTU main state machine (two-process implementation) + + FTU_test6_Registers: process (clk_50M_sig) + begin + if Rising_edge(clk_50M_sig) then + FTU_test6_State <= FTU_test6_NextState; + end if; + end process FTU_test6_Registers; + + FTU_test6_C_logic: process (FTU_test6_State, rx_data_sig, rx_valid_sig) + begin + FTU_test6_NextState <= FTU_test6_State; + case FTU_test6_State is + when INIT => + reset_sig <= '0'; + enable_sig <= DEFAULT_ENABLE; + if (rx_data_sig = "00110001" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN1; + elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN2; + elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN3; + elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN4; + else + FTU_test6_NextState <= INIT; + end if; + when RUN1 => + reset_sig <= '0'; + enable_sig <= ("0000000000000000","0000000111111111","0000000111111111","0000000111111111"); + if (rx_data_sig = "00110000" and rx_valid_sig = '1') then + FTU_test6_NextState <= INIT; + elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN2; + elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN3; + elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN4; + else + FTU_test6_NextState <= RUN1; + end if; + when RUN2 => + reset_sig <= '0'; + enable_sig <= ("0000000111111111","0000000000000000","0000000111111111","0000000111111111"); + if (rx_data_sig = "00110000" and rx_valid_sig = '1') then + FTU_test6_NextState <= INIT; + elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN1; + elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN3; + elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN4; + else + FTU_test6_NextState <= RUN2; + end if; + when RUN3 => + reset_sig <= '0'; + enable_sig <= ("0000000111111111","0000000111111111","0000000000000000","0000000111111111"); + if (rx_data_sig = "00110000" and rx_valid_sig = '1') then + FTU_test6_NextState <= INIT; + elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN1; + elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN2; + elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN4; + else + FTU_test6_NextState <= RUN3; + end if; + when RUN4 => + reset_sig <= '0'; + enable_sig <= ("0000000111111111","0000000111111111","0000000111111111","0000000000000000"); + if (rx_data_sig = "00110000" and rx_valid_sig = '1') then + FTU_test6_NextState <= INIT; + elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN1; + elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN2; + elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then + FTU_test6_NextState <= RUN3; + else + FTU_test6_NextState <= RUN4; + end if; + end case; + end process FTU_test6_C_logic; + +end Behavioral; Index: /firmware/FTU/test_firmware/FTU_test6/FTU_test6_dcm.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test6/FTU_test6_dcm.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test6/FTU_test6_dcm.vhd (revision 9841) @@ -0,0 +1,90 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.1 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTU_dac_dcm.vhd +-- /___/ /\ Timestamp : 01/20/2010 16:36:17 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /home/qweitzel/FPGA/FACT/FTU/source/ip_cores/FTU_dac_dcm.xaw /home/qweitzel/FPGA/FACT/FTU/source/ip_cores/FTU_dac_dcm +--Design Name: FTU_dac_dcm +--Device: xc3s400an-4fgg400 +-- +-- Module FTU_dac_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 6.54 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTU_test6_dcm is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end FTU_test6_dcm; + +architecture BEHAVIORAL of FTU_test6_dcm is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 2, + CLKFX_MULTIPLY => 2, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: /firmware/FTU/test_firmware/FTU_test6/FTU_test6_rs485_interface.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test6/FTU_test6_rs485_interface.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test6/FTU_test6_rs485_interface.vhd (revision 9841) @@ -0,0 +1,124 @@ +-- +-- VHDL Architecture FACT_FAD_lib.rs485_interface.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 13:24:23 08.06.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- +-- modified by Q. Weitzel, 30 July 2010 +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +ENTITY FTU_test6_rs485_interface IS + GENERIC( + CLOCK_FREQUENCY : integer := 50000000; -- Hertz + BAUD_RATE : integer := 250000 -- bits / sec + ); + PORT( + clk : IN std_logic; + -- RS485 + rx_d : IN std_logic; + rx_en : OUT std_logic; + tx_d : OUT std_logic; + tx_en : OUT std_logic; + -- FPGA + rx_data : OUT std_logic_vector (7 DOWNTO 0); + rx_busy : OUT std_logic := '0'; + rx_valid : OUT std_logic := '0'; + tx_data : IN std_logic_vector (7 DOWNTO 0); + tx_busy : OUT std_logic := '0'; + tx_start : IN std_logic + ); + +-- Declarations + +END FTU_test6_rs485_interface; + +ARCHITECTURE beha OF FTU_test6_rs485_interface IS + + signal tx_start_f : std_logic := '0'; + signal tx_sr : std_logic_vector(10 downto 0) := (others => '1'); -- start bit, 8 data bits, 2 stop bit + signal tx_bitcnt : integer range 0 to 11 := 11; + signal tx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1); + + signal flow_ctrl : std_logic := '0'; -- '0' -> RX enable, '1' -> TX enable + + signal rx_dsr : std_logic_vector(3 downto 0) := (others => '1'); + signal rx_sr : std_logic_vector(7 downto 0) := (others => '0'); + signal rx_bitcnt : integer range 0 to 11 := 11; + signal rx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1); + +BEGIN + + + -- Senden + tx_data_proc: process(clk) + begin + if rising_edge(clk) then + tx_start_f <= tx_start; + if (tx_start = '1' or tx_bitcnt < 11) then + flow_ctrl <= '1'; + else + flow_ctrl <= '0'; + end if; + if (tx_start = '1' and tx_start_f = '0') then -- steigende Flanke, los gehts + tx_cnt <= 0; -- Zaehler initialisieren + tx_bitcnt <= 0; + tx_sr <= "11" & tx_data & '0'; -- 2 x Stopbit, 8 Datenbits, Startbit, rechts gehts los + else + if (tx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then + tx_cnt <= tx_cnt + 1; + else -- naechstes Bit ausgeben + if (tx_bitcnt < 11) then + tx_cnt <= 0; + tx_bitcnt <= tx_bitcnt + 1; + tx_sr <= '1' & tx_sr(tx_sr'left downto 1); + end if; + end if; + end if; + end if; + end process; + + tx_en <= flow_ctrl; + tx_d <= tx_sr(0); -- LSB first + tx_busy <= '1' when (tx_start = '1' or tx_bitcnt < 11) else '0'; + + -- Empfangen + rx_data_proc: process(clk) + begin + if rising_edge(clk) then + rx_dsr <= rx_dsr(rx_dsr'left - 1 downto 0) & rx_d; + if (rx_bitcnt < 11) then -- Empfang laeuft + if (rx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then + rx_cnt <= rx_cnt + 1; + else + rx_cnt <= 0; + rx_bitcnt <= rx_bitcnt + 1; + if (rx_bitcnt < 9) then + rx_sr <= rx_dsr(rx_dsr'left - 1) & rx_sr(rx_sr'left downto 1); -- rechts schieben, weil LSB first + else + rx_valid <= '1'; + end if; + end if; + else + if (rx_dsr(3 downto 2) = "10") then -- warten auf Start bit + rx_valid <= '0'; + rx_cnt <= ((CLOCK_FREQUENCY / BAUD_RATE) - 1) / 2; + rx_bitcnt <= 0; + end if; + end if; + end if; + end process; + + rx_en <= flow_ctrl; + rx_data <= rx_sr; + rx_busy <= '1' when (rx_bitcnt < 11) else '0'; + +END ARCHITECTURE beha; + Index: /firmware/FTU/test_firmware/FTU_test6/FTU_test6_tb.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test6/FTU_test6_tb.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test6/FTU_test6_tb.vhd (revision 9841) @@ -0,0 +1,194 @@ +-------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 07/30/2010 +-- Design Name: +-- Module Name: FTU_test6_tb.vhd +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: Testbench for test6 entity of FACT FTU board +-- +-- VHDL Test Bench Created by ISE for module: FTU_test6 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-- +-- based on testbench for FTU_test1 +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity FTU_test6_tb is +end FTU_test6_tb; + +architecture behavior of FTU_test6_tb is + + -- Component Declaration for the Unit Under Test (UUT) + + component FTU_test6 + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable address + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); + end component; + + --Inputs + signal ext_clk : STD_LOGIC := '0'; + signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); + signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); + signal patch_A_p : STD_LOGIC := '0'; + signal patch_A_n : STD_LOGIC := '0'; + signal patch_B_p : STD_LOGIC := '0'; + signal patch_B_n : STD_LOGIC := '0'; + signal patch_C_p : STD_LOGIC := '0'; + signal patch_C_n : STD_LOGIC := '0'; + signal patch_D_p : STD_LOGIC := '0'; + signal patch_D_n : STD_LOGIC := '0'; + signal trig_prim_p : STD_LOGIC := '0'; + signal trig_prim_n : STD_LOGIC := '0'; + signal rx : STD_LOGIC := '0'; + + --Outputs + signal enables_A : STD_LOGIC_VECTOR(8 downto 0); + signal enables_B : STD_LOGIC_VECTOR(8 downto 0); + signal enables_C : STD_LOGIC_VECTOR(8 downto 0); + signal enables_D : STD_LOGIC_VECTOR(8 downto 0); + signal clr : STD_LOGIC; + signal cs_ld : STD_LOGIC; + signal sck : STD_LOGIC; + signal mosi : STD_LOGIC; + signal tx : STD_LOGIC; + signal rx_en : STD_LOGIC; + signal tx_en : STD_LOGIC; + signal TP_A : STD_LOGIC_VECTOR(11 downto 0); + + -- Clock period definitions + constant ext_clk_period : TIME := 20 ns; + +begin + + -- Instantiate the Unit Under Test (UUT) + uut: FTU_test6 + port map( + ext_clk => ext_clk, + brd_add => brd_add, + brd_id => brd_id, + patch_A_p => patch_A_p, + patch_A_n => patch_A_n, + patch_B_p => patch_B_p, + patch_B_n => patch_B_n, + patch_C_p => patch_C_p, + patch_C_n => patch_C_n, + patch_D_p => patch_D_p, + patch_D_n => patch_D_n, + trig_prim_p => trig_prim_p, + trig_prim_n => trig_prim_n, + rx => rx, + rx_en => rx_en, + enables_A => enables_A, + enables_B => enables_B, + enables_C => enables_C, + enables_D => enables_D, + clr => clr, + cs_ld => cs_ld, + sck => sck, + mosi => mosi, + tx => tx, + tx_en => tx_en, + TP_A => TP_A + ); + + -- Clock process definitions + ext_clk_proc: process + begin + ext_clk <= '0'; + wait for ext_clk_period/2; + ext_clk <= '1'; + wait for ext_clk_period/2; + end process ext_clk_proc; + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + --wait for 100ms; + + wait for ext_clk_period*10; + + rx <= '1'; --start bit + wait for ext_clk_period*5; + rx <= '1'; + wait for ext_clk_period*5; + rx <= '0'; + wait for ext_clk_period*5; + rx <= '0'; + wait for ext_clk_period*5; + rx <= '0'; + wait for ext_clk_period*5; + rx <= '1'; + wait for ext_clk_period*5; + rx <= '1'; + wait for ext_clk_period*5; + rx <= '0'; + wait for ext_clk_period*5; + rx <= '0'; + wait for ext_clk_period*5; + rx <= '0'; --parity bit + wait for ext_clk_period*5; + rx <= '1'; --stop bit + + wait; + end process stim_proc; + +end; Index: /firmware/FTU/test_firmware/FTU_test6/ftu_board_test6.ucf =================================================================== --- /firmware/FTU/test_firmware/FTU_test6/ftu_board_test6.ucf (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test6/ftu_board_test6.ucf (revision 9841) @@ -0,0 +1,145 @@ +######################################################## +# FTU Board +# FACT Trigger Unit +# +# Pin location constraints +# +# by Patrick Vogler, Quirin Weitzel +# 30 July 2010 (for FTU_test6) +######################################################## + + +#Clock +####################################################### +NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk + + +# RS-485 Interface +####################################################### +NET rx_en LOC = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver +NET tx_en LOC = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter +NET tx LOC = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM +NET rx LOC = R20 | IOSTANDARD=LVCMOS33; # 485_DI: serial data from FTM + + +# Board ID - inputs +# local board-ID "solder programmable" +####################################################### +#NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0 +#NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1 +#NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2 +#NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3 +#NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4 +#NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5 +#NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6 +#NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7 + + +# Board Addresses +# geographical slot address +####################################################### +#NET brd_add<0> LOC = A15 | IOSTANDARD=LVCMOS33; # ADDR0 +#NET brd_add<1> LOC = B15 | IOSTANDARD=LVCMOS33; # ADDR1 +#NET brd_add<2> LOC = A16 | IOSTANDARD=LVCMOS33; # ADDR2 +#NET brd_add<3> LOC = A17 | IOSTANDARD=LVCMOS33; # ADDR3 +#NET brd_add<4> LOC = A18 | IOSTANDARD=LVCMOS33; # ADDR4 +#NET brd_add<5> LOC = B18 | IOSTANDARD=LVCMOS33; # ADDR5 + + +# DAC SPI Interface +####################################################### +#NET mosi LOC = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in +#NET sck LOC = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC +#NET cs_ld LOC = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC +#NET clr LOC = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC + + +# Testpoints +###################################################### +# on Connector J5 +#NET TP_A<0> LOC = B3 | IOSTANDARD=LVCMOS33; # TP0_0 +#NET TP_A<1> LOC = A3 | IOSTANDARD=LVCMOS33; # TP1_0 +#NET TP_A<2> LOC = A4 | IOSTANDARD=LVCMOS33; # TP2_0 +#NET TP_A<3> LOC = B5 | IOSTANDARD=LVCMOS33; # TP2_0 + +# on Connector J6 +#NET TP_A<4> LOC = A5 | IOSTANDARD=LVCMOS33; # TP4_0 +#NET TP_A<5> LOC = A6 | IOSTANDARD=LVCMOS33; # TP5_0 +#NET TP_A<6> LOC = B7 | IOSTANDARD=LVCMOS33; # TP6_0 +#NET TP_A<7> LOC = A7 | IOSTANDARD=LVCMOS33; # TP7_0 + +# on Connector J7 +#NET TP_A<8> LOC = B11 | IOSTANDARD=LVCMOS33; # TP8_0 +#NET TP_A<9> LOC = A12 | IOSTANDARD=LVCMOS33; # TP9_0 +#NET TP_A<10> LOC = B12 | IOSTANDARD=LVCMOS33; # TP10_0 +#NET TP_A<11> LOC = A14 | IOSTANDARD=LVCMOS33; # TP11_0 + + +# Rate counter LVDS Inputs +###################################################### +# logic signal from first trigger patch +#NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P +#NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N + +# logic signal from second trigger patch +#NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P +#NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N + +# logic signal from third trigger patch +#NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P +#NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N + +# logic signal from fourth trigger patch +#NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P +#NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N + +#The Trigger Primitive: logic signal from n-out-of-4 circuit +#NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+ +#NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P- + + +# Enables +###################################################### +# Patch 0 +NET enables_A<0> LOC = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 +NET enables_A<1> LOC = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1 +NET enables_A<2> LOC = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2 +NET enables_A<3> LOC = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3 +NET enables_A<4> LOC = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4 +NET enables_A<5> LOC = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5 +NET enables_A<6> LOC = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6 +NET enables_A<7> LOC = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7 +NET enables_A<8> LOC = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8 + +## Patch 1 +NET enables_B<0> LOC = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0 +NET enables_B<1> LOC = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1 +NET enables_B<2> LOC = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2 +NET enables_B<3> LOC = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3 +NET enables_B<4> LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4 +NET enables_B<5> LOC = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5 +NET enables_B<6> LOC = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6 +NET enables_B<7> LOC = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7 +NET enables_B<8> LOC = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8 + +# Patch 2 +NET enables_C<0> LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0 +NET enables_C<1> LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1 +NET enables_C<2> LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2 +NET enables_C<3> LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3 +NET enables_C<4> LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4 +NET enables_C<5> LOC = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5 +NET enables_C<6> LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6 +NET enables_C<7> LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7 +NET enables_C<8> LOC = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8 + +# Patch 3 +NET enables_D<0> LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<1> LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<2> LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<3> LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<4> LOC = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<5> LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<6> LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<7> LOC = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<8> LOC = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 Index: /firmware/FTU/test_firmware/FTU_test6/ftu_definitions_test6.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test6/ftu_definitions_test6.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test6/ftu_definitions_test6.vhd (revision 9841) @@ -0,0 +1,18 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- use IEEE.NUMERIC_STD.ALL; + +package ftu_array_types is + + type enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0); + constant DEFAULT_ENABLE : enable_array_type := ("0000000111111111", --patch A + "0000000111111111", --patch B + "0000000111111111", --patch C + "0000000111111111");--patch D + + type dac_array_type is array (0 to 7) of integer range 0 to 2**12 - 1; + constant DEFAULT_DAC : dac_array_type := (500, 500, 500, 500, 0, 0, 0, 100); + +end ftu_array_types; Index: /firmware/FTU/test_firmware/FTU_test8/FTU_test8.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test8/FTU_test8.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test8/FTU_test8.vhd (revision 9841) @@ -0,0 +1,155 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 08/04/2010 +-- Design Name: +-- Module Name: FTU_test8 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTU board, ramp thresholds up (and down) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +entity FTU_test8 is + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); +end FTU_test8; + + +architecture Behavioral of FTU_test8 is + + component FTU_test8_dac_dcm + port( + CLKIN_IN : IN STD_LOGIC; + RST_IN : IN STD_LOGIC; + CLKFX_OUT : OUT STD_LOGIC; + CLKIN_IBUFG_OUT : OUT STD_LOGIC; + LOCKED_OUT : OUT STD_LOGIC + ); + end component; + + component FTU_test8_dac_control + port( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr : OUT STD_LOGIC; + mosi : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + cs_ld : OUT STD_LOGIC; + enable1 : OUT STD_LOGIC; + enable2 : OUT STD_LOGIC; + enable3 : OUT STD_LOGIC + ); + end component; + + signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up + signal clk_50M_sig : STD_LOGIC; + + type FTU_test8_StateType is (Running); + signal FTU_test8_State, FTU_test8_NextState: FTU_test8_StateType; + +begin + + enables_B <= "111111111"; + enables_C <= "111111111"; + enables_D <= "111111111"; + + Inst_FTU_test8_dac_dcm : FTU_test8_dac_dcm + port map( + CLKIN_IN => ext_clk, + RST_IN => reset_sig, + CLKFX_OUT => clk_50M_sig, + CLKIN_IBUFG_OUT => open, + LOCKED_OUT => open + ); + + Inst_FTU_test8_dac_control : FTU_test8_dac_control + port map( + clk => clk_50M_sig, + reset => reset_sig, + clr => clr, + mosi => mosi, + sck => sck, + cs_ld => cs_ld, + enable1 => enables_A(1), + enable2 => enables_A(2), + enable3 => enables_A(3) + ); + + --FTU main state machine (two-process implementation) + + FTU_test8_Registers: process (ext_clk) + begin + if Rising_edge(ext_clk) then + FTU_test8_State <= FTU_test8_NextState; + end if; + end process FTU_test8_Registers; + + FTU_test8_C_logic: process (FTU_test8_State) + begin + FTU_test8_NextState <= FTU_test8_State; + case FTU_test8_State is + when Running => + reset_sig <= '0'; + enables_A(8 downto 4) <= "11111"; + enables_A(0) <= '0'; + end case; + end process FTU_test8_C_logic; + +end Behavioral; Index: /firmware/FTU/test_firmware/FTU_test8/FTU_test8_dac_control.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test8/FTU_test8_dac_control.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test8/FTU_test8_dac_control.vhd (revision 9841) @@ -0,0 +1,172 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 08/04/2010 +-- Design Name: +-- Module Name: FTU_test8_dac_control - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: test8 for controling DAC on FTU board +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ftu_definitions_test8; +USE ftu_definitions_test8.ftu_array_types.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTU_test8_dac_control is + port( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr : OUT STD_LOGIC; + mosi : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + cs_ld : out STD_LOGIC; + enable1 : out STD_LOGIC; + enable2 : out STD_LOGIC; + enable3 : out STD_LOGIC + ); +end FTU_test8_dac_control; + +architecture Behavioral of FTU_test8_dac_control is + + component FTU_test8_spi_interface + port( + clk_50MHz : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + config_ready : OUT std_logic; + config_started : OUT std_logic; + dac_cs : OUT std_logic; + mosi : OUT std_logic; + sclk : OUT std_logic; + miso : INOUT std_logic + ); + end component; + + signal clk_sig : std_logic; + signal reset_sig : std_logic; + + signal clr_sig : std_logic; + signal mosi_sig : std_logic := '0'; + signal serial_clock_sig : std_logic; + signal dac_cs_sig : std_logic; + + signal config_start_sig : std_logic := '0'; + signal config_ready_sig : std_logic; + signal config_started_sig : std_logic := '0'; + signal dac_array_sig : dac_array_type := (0,0,0,0,0,0,0,100); + + -- Build an enumerated type for the state machine + type state_type is (START, SET, WAITING, WAITING_MORE, STOP); + + -- Register to hold the current state + signal state : state_type; + + signal ramp_cnt : integer range 0 to 45 := 0; + constant RAMP_STEP : integer := 91; + + --signal wait_cnt : integer range 0 to 150000000 := 0; --implement + signal wait_cnt : integer range 0 to 10 := 0; --simulation + --change this also below!!! + +begin + + reset_sig <= reset; + clk_sig <= clk; + mosi <= mosi_sig; + sck <= serial_clock_sig; + cs_ld <= dac_cs_sig; + + -- FSM for dac control: second process + FSM_logic: process(clk_sig) + begin + if rising_edge(clk_sig) then + case state is + when START => + dac_array_sig <= (0,0,0,0,0,0,0,100); + config_start_sig <= '0'; + enable1 <= '0'; + enable2 <= '1'; + enable3 <= '1'; + state <= SET; + when SET => + dac_array_sig <= (ramp_cnt*91,ramp_cnt*91,ramp_cnt*91,ramp_cnt*91,0,0,0,100); + config_start_sig <= '1'; + enable1 <= '0'; + enable2 <= '1'; + enable3 <= '1'; + if config_started_sig = '1' then + state <= WAITING; + else + state <= SET; + end if; + when WAITING => + dac_array_sig <= (ramp_cnt*91,ramp_cnt*91,ramp_cnt*91,ramp_cnt*91,0,0,0,100); + config_start_sig <= '1'; + enable1 <= '0'; + enable2 <= '1'; + enable3 <= '1'; + if (config_ready_sig = '1') then + state <= WAITING_MORE; + else + state <= WAITING; + end if; + when WAITING_MORE => + dac_array_sig <= (ramp_cnt*91,ramp_cnt*91,ramp_cnt*91,ramp_cnt*91,0,0,0,100); + config_start_sig <= '0'; + enable1 <= '1'; + enable2 <= '0'; + enable3 <= '1'; + if wait_cnt < 10 then + wait_cnt <= wait_cnt + 1; + state <= WAITING_MORE; + else + wait_cnt <= 0; + if (ramp_cnt < 45) then + ramp_cnt <= ramp_cnt + 1; + state <= SET; + else + state <= STOP; + end if; + end if; + when STOP => + dac_array_sig <= (0,0,0,0,0,0,0,100); + enable1 <= '1'; + enable2 <= '1'; + enable3 <= '0'; + config_start_sig <= '0'; + end case; + end if; + end process; + + Inst_FTU_test8_spi_interface : FTU_test8_spi_interface + port map( + clk_50MHz => clk_sig, + config_start => config_start_sig, + dac_array => dac_array_sig, + config_ready => config_ready_sig, + config_started => config_started_sig, + dac_cs => dac_cs_sig, + mosi => mosi_sig, + sclk => serial_clock_sig, + miso => open + ); + +end Behavioral; + Index: /firmware/FTU/test_firmware/FTU_test8/FTU_test8_dac_dcm.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test8/FTU_test8_dac_dcm.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test8/FTU_test8_dac_dcm.vhd (revision 9841) @@ -0,0 +1,90 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.1 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTU_dac_dcm.vhd +-- /___/ /\ Timestamp : 01/20/2010 16:36:17 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /home/qweitzel/FPGA/FACT/FTU/source/ip_cores/FTU_dac_dcm.xaw /home/qweitzel/FPGA/FACT/FTU/source/ip_cores/FTU_dac_dcm +--Design Name: FTU_dac_dcm +--Device: xc3s400an-4fgg400 +-- +-- Module FTU_dac_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 6.54 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTU_test8_dac_dcm is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end FTU_test8_dac_dcm; + +architecture BEHAVIORAL of FTU_test8_dac_dcm is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 2, + CLKFX_MULTIPLY => 2, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: /firmware/FTU/test_firmware/FTU_test8/FTU_test8_spi_clock_gen.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test8/FTU_test8_spi_clock_gen.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test8/FTU_test8_spi_clock_gen.vhd (revision 9841) @@ -0,0 +1,47 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_clock_generator.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 14:49:19 01.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY FTU_test8_spi_clock_generator IS + GENERIC( + CLK_DIVIDER : integer := 25 --2 MHz @ 50 MHz + ); + PORT( + clk : IN std_logic; + sclk : OUT std_logic := '0' + ); +END FTU_test8_spi_clock_generator; + +ARCHITECTURE beha OF FTU_test8_spi_clock_generator IS + +BEGIN + + spi_clk_proc: process (clk) + variable Z: integer range 0 to clk_divider - 1; + begin + if rising_edge(clk) then + if (Z < clk_divider - 1) then + Z := Z + 1; + else + Z := 0; + end if; + if (Z = 0) then + sclk <= '1'; + end if; + if (Z = clk_divider / 2) then + sclk <= '0'; + end if; + end if; + end process spi_clk_proc; + +END ARCHITECTURE beha; Index: /firmware/FTU/test_firmware/FTU_test8/FTU_test8_spi_controller.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test8/FTU_test8_spi_controller.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test8/FTU_test8_spi_controller.vhd (revision 9841) @@ -0,0 +1,81 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_controller.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 10:37:20 12.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- modified by Q. Weitzel +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY FTU_test8_spi_controller IS + PORT( + clk : IN std_logic; + miso : INOUT std_logic := 'Z'; + mosi : OUT std_logic := '0'; + dac_id : IN std_logic_vector (2 DOWNTO 0); + --data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + data : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); + dac_cs : OUT std_logic := '1'; + dac_start : IN std_logic; + dac_ready : OUT std_logic := '0' + ); +END FTU_test8_spi_controller ; + +ARCHITECTURE beha OF FTU_test8_spi_controller IS + + type TYPE_SPI_STATE is (SPI_IDLE, SPI_LOAD_DAC, SPI_LOAD_COMMAND); + + signal spi_state : TYPE_SPI_STATE := SPI_IDLE; + signal spi_cycle_cnt : integer range 0 to 25 := 0; + signal shift_reg : std_logic_vector (23 downto 0) := (others => '0'); + signal data_reg : std_logic_vector (15 downto 0) := (others => '0'); + +BEGIN + + spi_write_proc: process (clk) + begin + if falling_edge(clk) then + dac_cs <= '1'; + miso <= 'Z'; + mosi <= '0'; + --data <= (others => 'Z'); + case spi_state is + when SPI_IDLE => + if (dac_start = '1') then + dac_ready <= '0'; + spi_state <= SPI_LOAD_COMMAND; + end if; + + when SPI_LOAD_COMMAND => + spi_cycle_cnt <= 0; + if (dac_start = '1') then + shift_reg <= "0011" & '0' & dac_id & data(11 downto 0) & "0000"; + spi_state <= SPI_LOAD_DAC; + end if; + + -- start loading DACs + when SPI_LOAD_DAC => + dac_cs <= '0'; + if (spi_cycle_cnt < 24) then + mosi <= shift_reg(23); + shift_reg <= shift_reg(22 downto 0) & shift_reg(23); + dac_ready <= '0'; + spi_cycle_cnt <= spi_cycle_cnt + 1; + spi_state <= SPI_LOAD_DAC; + else + dac_cs <= '1'; + dac_ready <= '1'; + spi_state <= SPI_IDLE; + end if; + end case; + end if; + end process spi_write_proc; + +END ARCHITECTURE beha; Index: /firmware/FTU/test_firmware/FTU_test8/FTU_test8_spi_distributor.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test8/FTU_test8_spi_distributor.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test8/FTU_test8_spi_distributor.vhd (revision 9841) @@ -0,0 +1,91 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_distributor.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 09:24:21 23.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- modified by Q. Weitzel +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +library ftu_definitions_test8; +USE ftu_definitions_test8.ftu_array_types.all; + +ENTITY FTU_test8_spi_distributor IS + PORT( + clk : IN std_logic; -- 50MHz + config_start : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0'; + dac_array : IN dac_array_type; + dac_config_start : OUT std_logic := '0'; + dac_config_ready : IN std_logic; + dac_id : OUT std_logic_vector(2 downto 0) := (others => '0'); + --data : INOUT std_logic_vector(15 downto 0) := (others => 'Z') + data : OUT std_logic_vector(15 downto 0) := (others => '0') + ); +END ENTITY FTU_test8_spi_distributor; + +ARCHITECTURE beha OF FTU_test8_spi_distributor IS + + type TYPE_SPI_DISTRIBUTION_STATE is (INIT, IDLE, CONFIG_DAC); + + signal spi_distr_state : TYPE_SPI_DISTRIBUTION_STATE := INIT; + signal dac_id_cnt : integer range 0 to 7 := 0; + +BEGIN + + spi_distribute_proc: process (clk) + begin + + if rising_edge(clk) then + --data <= (others => 'Z'); + data <= (others => '0'); + case spi_distr_state is + when INIT => + --data <= (others => 'Z'); + data <= (others => '0'); + spi_distr_state <= IDLE; + when IDLE => + --data <= (others => 'Z'); + data <= (others => '0'); + -- start DAC configuration + if (config_start = '1') then + config_started <= '1'; + config_ready <= '0'; + dac_config_start <= '1'; + dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); + data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); + spi_distr_state <= CONFIG_DAC; + end if; + + -- DAC configuration + when CONFIG_DAC => + dac_config_start <= '1'; + dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); + data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); + if (dac_config_ready = '1') then + dac_config_start <= '0'; + if (dac_id_cnt < 7) then + dac_id_cnt <= dac_id_cnt + 1; + dac_config_start <= '1'; + spi_distr_state <= CONFIG_DAC; + else + dac_id_cnt <= 0; + config_started <= '0'; + config_ready <= '1'; + spi_distr_state <= IDLE; + end if; + end if; + end case; + end if; + + end process spi_distribute_proc; + +END ARCHITECTURE beha; + Index: /firmware/FTU/test_firmware/FTU_test8/FTU_test8_spi_interface.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test8/FTU_test8_spi_interface.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test8/FTU_test8_spi_interface.vhd (revision 9841) @@ -0,0 +1,138 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 08/04/2010 +-- Design Name: +-- Module Name: FTU_test5_spi_interface - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Based on VHDL Entity FACT_FAD_lib.spi_interface.symbol +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ftu_definitions_test8; +USE ftu_definitions_test8.ftu_array_types.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +ENTITY FTU_test8_spi_interface IS + PORT( + clk_50MHz : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + config_ready : OUT std_logic; + config_started : OUT std_logic := '0'; + dac_cs : OUT std_logic; + mosi : OUT std_logic := '0'; + sclk : OUT std_logic; + miso : INOUT std_logic + ); +END FTU_test8_spi_interface; + +ARCHITECTURE struct OF FTU_test8_spi_interface IS + + -- Internal signal declarations + SIGNAL dac_config_ready : std_logic; + SIGNAL dac_config_start : std_logic; + SIGNAL dac_id : std_logic_vector(2 DOWNTO 0); + SIGNAL data : std_logic_vector(15 DOWNTO 0); + + -- Implicit buffer signal declarations + SIGNAL sclk_internal : std_logic; + + + -- Component Declarations + COMPONENT FTU_test8_spi_clock_generator + GENERIC ( + CLK_DIVIDER : integer := 25 --2 MHz @ 50 MHz + ); + PORT ( + clk : IN std_logic; + sclk : OUT std_logic := '0' + ); + END COMPONENT; + + COMPONENT FTU_test8_spi_controller + PORT ( + clk : IN std_logic; + dac_id : IN std_logic_vector (2 DOWNTO 0); + dac_start : IN std_logic; + dac_cs : OUT std_logic := '1'; + dac_ready : OUT std_logic := '0'; + mosi : OUT std_logic := '0'; + --data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + data : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); + miso : INOUT std_logic := 'Z' + ); + END COMPONENT; + + COMPONENT FTU_test8_spi_distributor + PORT ( + clk : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + dac_config_ready : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0'; + dac_config_start : OUT std_logic := '0'; + dac_id : OUT std_logic_vector (2 DOWNTO 0) := (others => '0'); + --data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z') + data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') + ); + END COMPONENT; + +BEGIN + + -- Instance port mappings. + Inst_FTU_test8_spi_clock_generator : FTU_test8_spi_clock_generator + GENERIC MAP ( + CLK_DIVIDER => 25 --2 MHz @ 50 MHz + ) + PORT MAP ( + clk => clk_50MHz, + sclk => sclk_internal + ); + + Inst_FTU_test8_spi_controller : FTU_test8_spi_controller + PORT MAP ( + clk => sclk_internal, + miso => miso, + mosi => mosi, + dac_id => dac_id, + data => data, + dac_cs => dac_cs, + dac_start => dac_config_start, + dac_ready => dac_config_ready + ); + + Inst_FTU_test8_spi_distributor : FTU_test8_spi_distributor + PORT MAP ( + clk => sclk_internal, + config_start => config_start, + config_ready => config_ready, + config_started => config_started, + dac_array => dac_array, + dac_config_start => dac_config_start, + dac_config_ready => dac_config_ready, + dac_id => dac_id, + data => data + ); + + -- Implicit buffered output assignments + sclk <= sclk_internal; + +END struct; Index: /firmware/FTU/test_firmware/FTU_test8/FTU_test8_tb.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test8/FTU_test8_tb.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test8/FTU_test8_tb.vhd (revision 9841) @@ -0,0 +1,174 @@ +-------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 08/04/2010 +-- Design Name: +-- Module Name: FTU_test8_tb.vhd +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: Testbench for test8 entity of FACT FTU board +-- +-- VHDL Test Bench Created by ISE for module: FTU_test8 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-- +-- based on testbench for FTU_test2 +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity FTU_test8_tb is +end FTU_test8_tb; + +architecture behavior of FTU_test8_tb is + + -- Component Declaration for the Unit Under Test (UUT) + + component FTU_test8 + port( + -- global control + ext_clk : IN STD_LOGIC; -- external clock from FTU board + brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address + brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable address + + -- rate counters LVDS inputs + -- use IBUFDS differential input buffer + patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch + patch_A_n : IN STD_LOGIC; + patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch + patch_B_n : IN STD_LOGIC; + patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch + patch_C_n : IN STD_LOGIC; + patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch + patch_D_n : IN STD_LOGIC; + trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit + trig_prim_n : IN STD_LOGIC; + + -- DAC interface + sck : OUT STD_LOGIC; -- serial clock to DAC + mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in + clr : OUT STD_LOGIC; -- clear signal to DAC + cs_ld : OUT STD_LOGIC; -- chip select or load to DAC + + -- RS-485 interface to FTM + rx : IN STD_LOGIC; -- serial data from FTM + tx : OUT STD_LOGIC; -- serial data to FTM + rx_en : OUT STD_LOGIC; -- enable RS-485 receiver + tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter + + -- analog buffer enable + enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs + + -- testpoints + TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints + ); + end component; + + --Inputs + signal ext_clk : STD_LOGIC := '0'; + signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); + signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); + signal patch_A_p : STD_LOGIC := '0'; + signal patch_A_n : STD_LOGIC := '0'; + signal patch_B_p : STD_LOGIC := '0'; + signal patch_B_n : STD_LOGIC := '0'; + signal patch_C_p : STD_LOGIC := '0'; + signal patch_C_n : STD_LOGIC := '0'; + signal patch_D_p : STD_LOGIC := '0'; + signal patch_D_n : STD_LOGIC := '0'; + signal trig_prim_p : STD_LOGIC := '0'; + signal trig_prim_n : STD_LOGIC := '0'; + signal rx : STD_LOGIC := '0'; + + --Outputs + signal enables_A : STD_LOGIC_VECTOR(8 downto 0); + signal enables_B : STD_LOGIC_VECTOR(8 downto 0); + signal enables_C : STD_LOGIC_VECTOR(8 downto 0); + signal enables_D : STD_LOGIC_VECTOR(8 downto 0); + signal clr : STD_LOGIC; + signal cs_ld : STD_LOGIC; + signal sck : STD_LOGIC; + signal mosi : STD_LOGIC; + signal tx : STD_LOGIC; + signal rx_en : STD_LOGIC; + signal tx_en : STD_LOGIC; + signal TP_A : STD_LOGIC_VECTOR(11 downto 0); + + -- Clock period definitions + constant ext_clk_period : TIME := 20 ns; + +begin + + -- Instantiate the Unit Under Test (UUT) + uut: FTU_test8 + port map( + ext_clk => ext_clk, + brd_add => brd_add, + brd_id => brd_id, + patch_A_p => patch_A_p, + patch_A_n => patch_A_n, + patch_B_p => patch_B_p, + patch_B_n => patch_B_n, + patch_C_p => patch_C_p, + patch_C_n => patch_C_n, + patch_D_p => patch_D_p, + patch_D_n => patch_D_n, + trig_prim_p => trig_prim_p, + trig_prim_n => trig_prim_n, + rx => rx, + rx_en => rx_en, + enables_A => enables_A, + enables_B => enables_B, + enables_C => enables_C, + enables_D => enables_D, + clr => clr, + cs_ld => cs_ld, + sck => sck, + mosi => mosi, + tx => tx, + tx_en => tx_en, + TP_A => TP_A + ); + + -- Clock process definitions + ext_clk_proc: process + begin + ext_clk <= '0'; + wait for ext_clk_period/2; + ext_clk <= '1'; + wait for ext_clk_period/2; + end process ext_clk_proc; + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100ms. + wait for 100ms; + + wait for ext_clk_period*10; + + -- insert stimulus here + + wait; + end process stim_proc; + +end; Index: /firmware/FTU/test_firmware/FTU_test8/ftu_board_test8.ucf =================================================================== --- /firmware/FTU/test_firmware/FTU_test8/ftu_board_test8.ucf (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test8/ftu_board_test8.ucf (revision 9841) @@ -0,0 +1,145 @@ +######################################################## +# FTU Board +# FACT Trigger Unit +# +# Pin location constraints +# +# by Patrick Vogler, Quirin Weitzel +# 02 July 2010 +######################################################## + + +#Clock +####################################################### +NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk + + +# RS-485 Interface +####################################################### +#NET rx_en LOC = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver +#NET tx_en LOC = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter +#NET tx LOC = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM +#NET rx LOC = R20 | IOSTANDARD=LVCMOS33; # 485_DI: serial data from FTM + + +# Board ID - inputs +# local board-ID "solder programmable" +####################################################### +#NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0 +#NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1 +#NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2 +#NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3 +#NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4 +#NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5 +#NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6 +#NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7 + + +# Board Addresses +# geographical slot address +####################################################### +#NET brd_add<0> LOC = A15 | IOSTANDARD=LVCMOS33; # ADDR0 +#NET brd_add<1> LOC = B15 | IOSTANDARD=LVCMOS33; # ADDR1 +#NET brd_add<2> LOC = A16 | IOSTANDARD=LVCMOS33; # ADDR2 +#NET brd_add<3> LOC = A17 | IOSTANDARD=LVCMOS33; # ADDR3 +#NET brd_add<4> LOC = A18 | IOSTANDARD=LVCMOS33; # ADDR4 +#NET brd_add<5> LOC = B18 | IOSTANDARD=LVCMOS33; # ADDR5 + + +# DAC SPI Interface +####################################################### +NET mosi LOC = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in +NET sck LOC = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC +NET cs_ld LOC = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC +NET clr LOC = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC + + +# Testpoints +###################################################### +# on Connector J5 +#NET TP_A<0> LOC = B3 | IOSTANDARD=LVCMOS33; # TP0_0 +#NET TP_A<1> LOC = A3 | IOSTANDARD=LVCMOS33; # TP1_0 +#NET TP_A<2> LOC = A4 | IOSTANDARD=LVCMOS33; # TP2_0 +#NET TP_A<3> LOC = B5 | IOSTANDARD=LVCMOS33; # TP2_0 + +# on Connector J6 +#NET TP_A<4> LOC = A5 | IOSTANDARD=LVCMOS33; # TP4_0 +#NET TP_A<5> LOC = A6 | IOSTANDARD=LVCMOS33; # TP5_0 +#NET TP_A<6> LOC = B7 | IOSTANDARD=LVCMOS33; # TP6_0 +#NET TP_A<7> LOC = A7 | IOSTANDARD=LVCMOS33; # TP7_0 + +# on Connector J7 +#NET TP_A<8> LOC = B11 | IOSTANDARD=LVCMOS33; # TP8_0 +#NET TP_A<9> LOC = A12 | IOSTANDARD=LVCMOS33; # TP9_0 +#NET TP_A<10> LOC = B12 | IOSTANDARD=LVCMOS33; # TP10_0 +#NET TP_A<11> LOC = A14 | IOSTANDARD=LVCMOS33; # TP11_0 + + +# Rate counter LVDS Inputs +###################################################### +# logic signal from first trigger patch +#NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P +#NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N + +# logic signal from second trigger patch +#NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P +#NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N + +# logic signal from third trigger patch +#NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P +#NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N + +# logic signal from fourth trigger patch +#NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P +#NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N + +#The Trigger Primitive: logic signal from n-out-of-4 circuit +#NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+ +#NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P- + + +# Enables +###################################################### +# Patch 0 +NET enables_A<0> LOC = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 +NET enables_A<1> LOC = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1 +NET enables_A<2> LOC = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2 +NET enables_A<3> LOC = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3 +NET enables_A<4> LOC = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4 +NET enables_A<5> LOC = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5 +NET enables_A<6> LOC = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6 +NET enables_A<7> LOC = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7 +NET enables_A<8> LOC = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8 + +## Patch 1 +NET enables_B<0> LOC = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0 +NET enables_B<1> LOC = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1 +NET enables_B<2> LOC = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2 +NET enables_B<3> LOC = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3 +NET enables_B<4> LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4 +NET enables_B<5> LOC = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5 +NET enables_B<6> LOC = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6 +NET enables_B<7> LOC = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7 +NET enables_B<8> LOC = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8 + +# Patch 2 +NET enables_C<0> LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0 +NET enables_C<1> LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1 +NET enables_C<2> LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2 +NET enables_C<3> LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3 +NET enables_C<4> LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4 +NET enables_C<5> LOC = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5 +NET enables_C<6> LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6 +NET enables_C<7> LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7 +NET enables_C<8> LOC = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8 + +# Patch 3 +NET enables_D<0> LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<1> LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<2> LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<3> LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<4> LOC = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<5> LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<6> LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<7> LOC = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 +NET enables_D<8> LOC = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0 Index: /firmware/FTU/test_firmware/FTU_test8/ftu_definitions_test8.vhd =================================================================== --- /firmware/FTU/test_firmware/FTU_test8/ftu_definitions_test8.vhd (revision 9841) +++ /firmware/FTU/test_firmware/FTU_test8/ftu_definitions_test8.vhd (revision 9841) @@ -0,0 +1,9 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- use IEEE.NUMERIC_STD.ALL; + +package ftu_array_types is + type dac_array_type is array (0 to 7) of integer range 0 to 2**12 - 1; +end ftu_array_types;

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~j02603:1=vF88e9~j02613:1=vF88e9~j026i3:1=vF88e9~j026j3:1=vF88e9~yx{GHJq>5auIJIw=sO@Qy~DE Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Coregen/dataRAM_64b_16b_width15.xco =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Coregen/dataRAM_64b_16b_width15.xco (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Coregen/dataRAM_64b_16b_width15.xco (revision 9841) @@ -0,0 +1,78 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Mon Jun 21 14:26:28 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatParenNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3sd3400a +SET devicefamily = spartan3adsp +SET flowvendor = MentorHDL +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg676 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator family Xilinx,_Inc. 2.8 +# END Select +# BEGIN Parameters +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=dataRAM_64b_16b_width15 +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET fill_remaining_memory_locations=false +CSET load_init_file=false +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=READ_FIRST +CSET operating_mode_b=READ_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET primitive=8kx2 +CSET read_width_a=64 +CSET read_width_b=16 +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET remaining_memory_locations=0 +CSET single_bit_ecc=false +CSET use_byte_write_enable=false +CSET use_ramb16bwer_reset_behavior=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_ssra_pin=false +CSET use_ssrb_pin=false +CSET write_depth_a=32768 +CSET write_width_a=64 +CSET write_width_b=16 +# END Parameters +GENERATE +# CRC: 66fba8fa + Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/Constraints/dataRAM_64b_16b_width15.ctr =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/Constraints/dataRAM_64b_16b_width15.ctr (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/Constraints/dataRAM_64b_16b_width15.ctr (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3adsp +# set_device 3sd3400a +# set_package fg676 +# set_speed -4 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/Constraints/dataRAM_64b_16b_width15.sdc =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/Constraints/dataRAM_64b_16b_width15.sdc (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/Constraints/dataRAM_64b_16b_width15.sdc (revision 9841) @@ -0,0 +1,5 @@ +# set_vendor xilinx +# set_family spartan3adsp +# set_device 3sd3400a +# set_package fg676 +# set_speed -4 Index: /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/dataRAM_64b_16b_width15.ngc =================================================================== --- /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/dataRAM_64b_16b_width15.ngc (revision 9841) +++ /firmware/FAD/update_DAC_per_button/FACT_FAD/FACT_FAD_lib/hds/.hdlsidedata/dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd.info/Synthesis/dataRAM_64b_16b_width15.ngc (revision 9841) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$`764g<,[o}e~g`n;"2*413&;$>"9 > %384<=789:;<=>?4193456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0127?567<=1;<=6=;130?4(7:2;;=95>4;KMTPR=IMNYM%?<:1+20>732@D[YY4NDEPA,45=8 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