Index: /firmware/FTM/ftm_board.ucf =================================================================== --- /firmware/FTM/ftm_board.ucf (revision 9844) +++ /firmware/FTM/ftm_board.ucf (revision 9844) @@ -0,0 +1,402 @@ +######################################################## +# FTM Board +# FACT Trigger Master +# +# Pin location constraints +# +# by Patrick Vogler +# 02 July 2010 +######################################################## + + +#Clock +####################################################### +NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK + + +# Ethernet Interface +# connection to the WIZnet W5300 ethernet controller +# on IO-Bank 1 +####################################################### +# data bus +NET W_D<0> LOC = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300 +NET W_D<1> LOC = L22 | IOSTANDARD=LVCMOS33; # +NET W_D<2> LOC = K23 | IOSTANDARD=LVCMOS33; # +NET W_D<3> LOC = K25 | IOSTANDARD=LVCMOS33; # +NET W_D<4> LOC = K26 | IOSTANDARD=LVCMOS33; # +NET W_D<5> LOC = J22 | IOSTANDARD=LVCMOS33; # +NET W_D<6> LOC = J23 | IOSTANDARD=LVCMOS33; # +NET W_D<7> LOC = G23 | IOSTANDARD=LVCMOS33; # +NET W_D<8> LOC = G24 | IOSTANDARD=LVCMOS33; # +NET W_D<9> LOC = F24 | IOSTANDARD=LVCMOS33; # +NET W_D<10> LOC = F25 | IOSTANDARD=LVCMOS33; # +NET W_D<11> LOC = E24 | IOSTANDARD=LVCMOS33; # +NET W_D<12> LOC = E26 | IOSTANDARD=LVCMOS33; # +NET W_D<13> LOC = D24 | IOSTANDARD=LVCMOS33; # +NET W_D<14> LOC = D26 | IOSTANDARD=LVCMOS33; # +NET W_D<15> LOC = D25 | IOSTANDARD=LVCMOS33; # + +# W5300 address bus +NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # there is NO net W_A0 because +NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode +NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # see W5300 datasheet +NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; # +NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; # +NET W_A<6> LOC = Y23 | IOSTANDARD=LVCMOS33; # +NET W_A<7> LOC = W23 | IOSTANDARD=LVCMOS33; # +NET W_A<8> LOC = V25 | IOSTANDARD=LVCMOS33; # +NET W_A<9> LOC = V24 | IOSTANDARD=LVCMOS33; # + +# W5300 controll signals +# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 +# W_CS is also routed to testpoint JP7 +NET W_CS LOC = T20 | IOSTANDARD=LVCMOS33; # W5300 chip select +NET W_INT LOC = U22 | IOSTANDARD=LVCMOS33; # interrupt +NET W_RD LOC = R20 | IOSTANDARD=LVCMOS33; # read +NET W_WR LOC = P22 | IOSTANDARD=LVCMOS33; # write +NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; # reset W5300 chip + +# W5300 +NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; # +NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; # +NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; # +NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; # + +# W5300 +NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; # +NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; # +NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; # + + +# SPI Interface +# connection to the EEPROM U36 (AL25L016M) and the temperature +# sensors U45, U46, U48 and U49 (all MAX6662) +# on IO-Bank 1 +####################################################### +NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock + +# EEPROM +NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in +NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out +NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in + +# temperature sensors +NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO +NET TS_CS_<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0 +NET TS_CS_<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1 +NET TS_CS_<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2 +NET TS_CS_<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3 + + +# Trigger primitives inputs +# on IO-Bank 2 +####################################################### +# crate 0 +NET Trig-Prim_0_<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_0_<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_0_<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_0_<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_0_<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_0_<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_0_<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_0_<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_0_<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_0_<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # + +# crate 1 +NET Trig-Prim_1_<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_1_<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_1_<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_1_<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_1_<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_1_<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_1_<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_1_<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_1_<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_1_<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # + +# crate 2 +NET Trig-Prim_2_<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_2_<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_2_<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_2_<3> LOC = AD21 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_2_<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_2_<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_2_<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_2_<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_2_<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_2_<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # + +# crate 3 +NET Trig-Prim_3_<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_3_<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_3_<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_3_<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_3_<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_3_<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_3_<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_3_<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_3_<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # +NET Trig-Prim_3_<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # + + +# NIM inputs +####################################################### +# on IO-Bank 3 +NET ext_Trig_<1> LOC = B1 | IOSTANDARD=LVCMOS33; # +NET ext_Trig_<2> LOC = B2 | IOSTANDARD=LVCMOS33; # +NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; # +NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; # +NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; # +NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; # + +# on IO-Bank 0 +NET NIM_In3/GCLK LOC = K14 | IOSTANDARD=LVCMOS33; # input with global clock buffer + # available + + +# LEDs +# on IO-Banks 0 and 3 +####################################################### +### ### +# OPEN COLLECTOR OUTPUTS FOR THE LEDs # +### ### +# red +NET LED_red_<0> LOC = D6 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +NET LED_red_<1> LOC = A4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +NET LED_red_<2> LOC = E1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET LED_red_<3> LOC = J5 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + +# yellow +NET LED_ye_<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +NET LED_ye_<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + +# green +NET LED_gn_<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +NET LED_gn_<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + + +# Clock conditioner LMK03000 +# on IO-Bank 3 +####################################################### +NET CLK_Clk-Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET LE_Clk-Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET LD_Clk-Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET DATA_Clk-Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET SYNC_Clk-Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + + +# various RS-485 Interfaces +# on IO-Bank 3 +####################################################### +# Bus 1: FTU slow control +NET Bus1_Tx-En LOC = H1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus1_Rx-En LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +NET Bus1_RxD_0 LOC = K3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus1_TxD_0 LOC = L3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +NET Bus1_RxD_1 LOC = M2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus1_TxD_1 LOC = N4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +NET Bus1_RxD_2 LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus1_TxD_2 LOC = P4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +NET Bus1_RxD_3 LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus1_TxD_3 LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Bus 2: Trigger-ID to FAD boards +NET Bus2_Tx-En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_Rx-En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# auxiliary access +NET Aux_Rx-D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Aux_Tx-D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Aux_Rx-En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable +NET Aux_Tx-En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary + # Trigger-ID + +# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +NET TrID_Rx-D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET TrID_Tx-D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Crate-Resets +# on IO-Bank 3 +####################################################### +NET Crate-Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Crate-Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Crate-Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Crate-Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Busy signals from the FAD boards +# on IO-Bank 3 +####################################################### +NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# NIM outputs +# on IO-Bank 0 +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# calibration +NET Cal_NIM1+ LOC = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # +NET Cal_NIM1- LOC = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # +NET Cal_NIM2+ LOC = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # +NET Cal_NIM2- LOC = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # + +# auxiliarry / spare NIM outputs +NET NIM_Out0+ LOC = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # +NET NIM_Out0- LOC = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # +NET NIM_Out1+ LOC = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # +NET NIM_Out1- LOC = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # + + +# fast control signal outputs +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +NET RES+ LOC = D16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # Reset +NET RES- LOC = C15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # IO-Bank 0 + +NET TRG+ LOC = B15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Trigger +NET TRG- LOC = A15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # IO-Bank 0 + +NET TIM_Run+ LOC = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # Time Marker +NET TIM_Run- LOC = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # IO-Bank 2 +NET TIM-Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector + # IO-Bank 2 +NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA + + +# LVDS calibration outputs +# on IO-Bank 0 +####################################################### +# to connector J13 +NET Cal_0+ LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # +NET Cal_0- LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # +NET Cal_1+ LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # +NET Cal_1- LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # +NET Cal_2+ LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # +NET Cal_2- LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # +NET Cal_3+ LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # +NET Cal_3- LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # + +# to connector J12 +NET Cal_4+ LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # +NET Cal_4- LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # +NET Cal_5+ LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # +NET Cal_5- LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # +NET Cal_6+ LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # +NET Cal_6- LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # +NET Cal_7+ LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # +NET Cal_7- LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # + + +# Testpoints +###################################################### +# Connector T7 +# IO-Bank 0 +NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; # +NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; # +NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; # +NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; # + +# Connector T10 +# IO-Bank 0 +NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; # +NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; # +NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; # +NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; # + +# on Connector T12 +# IO-Bank 0 +NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; # +NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; # + +# on Connector T14 +# IO-Bank 0 +NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; # +NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; # +NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; # +NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; # + +# on Connector T16 +# IO-Bank 0 +NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; # +NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; # +NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; # +NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; # + +# on Connector T8 +# IO-Bank 0 +NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; # +NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; # +NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; # +NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; # + +# on Connector T9 +# IO-Bank 0 +NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; # +NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; # + +# on Connector T11 +# IO-Bank 3 +NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; # +NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; # +NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; # +NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; # + +# on Connector T13 +# IO-Bank 3 +NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; # +NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; # +NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; # +NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; # + +# on Connector T15 +NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET TP<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only +NET TP<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only + + +# Board ID - inputs +# local board-ID "solder programmable" +# all on 'input only' pins +####################################################### +NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; # +NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; # +NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; # +NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; # +NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; # +NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; # +NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; # +NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; # +