Index: firmware/FTM/ftm_board.ucf =================================================================== --- firmware/FTM/ftm_board.ucf (revision 9844) +++ firmware/FTM/ftm_board.ucf (revision 9879) @@ -6,5 +6,5 @@ # # by Patrick Vogler -# 02 July 2010 +# 18 August 2010 ######################################################## @@ -12,9 +12,9 @@ #Clock ####################################################### -NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK +NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47 # Ethernet Interface -# connection to the WIZnet W5300 ethernet controller +# connection to the WIZnet W5300 ethernet controller (U37) # on IO-Bank 1 ####################################################### @@ -57,5 +57,5 @@ NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; # reset W5300 chip -# W5300 +# W5300 buffer ready indicator NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; # NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; # @@ -63,8 +63,9 @@ NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; # -# W5300 +# W5300 associated testpoints NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; # NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; # NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; # +NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; # @@ -83,8 +84,8 @@ # temperature sensors NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO -NET TS_CS_<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0 -NET TS_CS_<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1 -NET TS_CS_<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2 -NET TS_CS_<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3 +NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0 +NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1 +NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2 +NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3 @@ -92,51 +93,55 @@ # on IO-Bank 2 ####################################################### -# crate 0 -NET Trig-Prim_0_<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_0_<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_0_<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_0_<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_0_<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_0_<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_0_<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_0_<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_0_<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_0_<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # +# crate 0 +# crate A +NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0> +NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1> +NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2> +NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3> +NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4> +NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5> +NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6> +NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7> +NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8> +NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9> # crate 1 -NET Trig-Prim_1_<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_1_<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_1_<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_1_<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_1_<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_1_<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_1_<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_1_<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_1_<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_1_<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # +# crate B +NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0> +NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1> +NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2> +NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3> +NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4> +NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5> +NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6> +NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7> +NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8> +NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9> # crate 2 -NET Trig-Prim_2_<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_2_<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_2_<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_2_<3> LOC = AD21 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_2_<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_2_<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_2_<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_2_<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_2_<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_2_<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # +# crate C +NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0> +NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1> +NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2> +NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3> +NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4> +NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5> +NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6> +NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7> +NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8> +NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9> # crate 3 -NET Trig-Prim_3_<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_3_<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_3_<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_3_<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_3_<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_3_<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_3_<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_3_<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_3_<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # -NET Trig-Prim_3_<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # +# crate D +NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0> +NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1> +NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2> +NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3> +NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4> +NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5> +NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6> +NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7> +NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8> +NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9> @@ -144,6 +149,6 @@ ####################################################### # on IO-Bank 3 -NET ext_Trig_<1> LOC = B1 | IOSTANDARD=LVCMOS33; # -NET ext_Trig_<2> LOC = B2 | IOSTANDARD=LVCMOS33; # +NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; # +NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; # NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; # NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; # @@ -152,5 +157,5 @@ # on IO-Bank 0 -NET NIM_In3/GCLK LOC = K14 | IOSTANDARD=LVCMOS33; # input with global clock buffer +NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33; # input with global clock buffer # available @@ -159,20 +164,17 @@ # on IO-Banks 0 and 3 ####################################################### -### ### -# OPEN COLLECTOR OUTPUTS FOR THE LEDs # -### ### # red -NET LED_red_<0> LOC = D6 | IOSTANDARD=LVCMOS33; # IO-Bank 0 -NET LED_red_<1> LOC = A4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 -NET LED_red_<2> LOC = E1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 -NET LED_red_<3> LOC = J5 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET LED_red<0> LOC = D6 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +NET LED_red<1> LOC = A4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +NET LED_red<2> LOC = E1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET LED_red<3> LOC = J5 | IOSTANDARD=LVCMOS33; # IO-Bank 3 # yellow -NET LED_ye_<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0 -NET LED_ye_<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 # green -NET LED_gn_<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 -NET LED_gn_<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 @@ -180,9 +182,9 @@ # on IO-Bank 3 ####################################################### -NET CLK_Clk-Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 -NET LE_Clk-Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 -NET LD_Clk-Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 -NET DATA_Clk-Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 -NET SYNC_Clk-Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 @@ -191,6 +193,6 @@ ####################################################### # Bus 1: FTU slow control -NET Bus1_Tx-En LOC = H1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Bus1_Rx-En LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus1_Tx_En LOC = H1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus1_Rx_En LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # # crate 0 @@ -212,6 +214,6 @@ # Bus 2: Trigger-ID to FAD boards -NET Bus2_Tx-En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Bus2_Rx-En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # # crate 0 @@ -233,13 +235,13 @@ # auxiliary access -NET Aux_Rx-D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Aux_Tx-D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Aux_Rx-En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable -NET Aux_Tx-En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary +NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable +NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary # Trigger-ID # auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) -NET TrID_Rx-D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET TrID_Tx-D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # @@ -247,8 +249,8 @@ # on IO-Bank 3 ####################################################### -NET Crate-Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Crate-Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Crate-Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Crate-Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # @@ -268,14 +270,14 @@ ####################################################### # calibration -NET Cal_NIM1+ LOC = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # -NET Cal_NIM1- LOC = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # -NET Cal_NIM2+ LOC = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # -NET Cal_NIM2- LOC = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # +NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1+ +NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1- +NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2+ +NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2- # auxiliarry / spare NIM outputs -NET NIM_Out0+ LOC = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # -NET NIM_Out0- LOC = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # -NET NIM_Out1+ LOC = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # -NET NIM_Out1- LOC = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # +NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0+ +NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0- +NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # NIM_Out1+ +NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out1- @@ -284,13 +286,14 @@ # conversion stage ####################################################### -NET RES+ LOC = D16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # Reset -NET RES- LOC = C15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # IO-Bank 0 - -NET TRG+ LOC = B15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Trigger -NET TRG- LOC = A15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # IO-Bank 0 - -NET TIM_Run+ LOC = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # Time Marker -NET TIM_Run- LOC = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # IO-Bank 2 -NET TIM-Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector +NET RES_p LOC = D16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset +NET RES_n LOC = C15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0 + +NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger +NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0 + +NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker +NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- + # on IO-Bank2 +NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector # IO-Bank 2 NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA @@ -301,22 +304,22 @@ ####################################################### # to connector J13 -NET Cal_0+ LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # -NET Cal_0- LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # -NET Cal_1+ LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # -NET Cal_1- LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # -NET Cal_2+ LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # -NET Cal_2- LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # -NET Cal_3+ LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # -NET Cal_3- LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # +NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+ +NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0- +NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+ +NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1- +NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+ +NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2- +NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+ +NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3- # to connector J12 -NET Cal_4+ LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # -NET Cal_4- LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # -NET Cal_5+ LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # -NET Cal_5- LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # -NET Cal_6+ LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # -NET Cal_6- LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # -NET Cal_7+ LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # -NET Cal_7- LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # +NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+ +NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4- +NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+ +NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5- +NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+ +NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6- +NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+ +NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7- @@ -384,6 +387,6 @@ # on Connector T15 NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 -NET TP<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only -NET TP<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only +NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only +NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only