Changeset 9880 for firmware/FTU/FTU_top_tb.vhd
- Timestamp:
- 08/18/10 18:02:48 (15 years ago)
- File:
-
- 1 edited
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firmware/FTU/FTU_top_tb.vhd
r273 r9880 1 1 -------------------------------------------------------------------------------- 2 2 -- Company: ETH Zurich, Institute for Particle Physics 3 -- Engineer: P. Vogler, Q. Weitzel3 -- Engineer: Q. Weitzel, P. Vogler 4 4 -- 5 5 -- Create Date: 12.07.2010 … … 30 30 use IEEE.STD_LOGIC_UNSIGNED.ALL; 31 31 use IEEE.NUMERIC_STD.ALL; 32 32 33 library UNISIM; 34 use UNISIM.VComponents.all; 35 33 36 entity FTU_top_tb is 34 37 end FTU_top_tb; … … 110 113 signal tx_en : STD_LOGIC; 111 114 signal TP_A : STD_LOGIC_VECTOR(11 downto 0); 115 116 --single-ended trigger signals 117 signal patch_A_sig : STD_LOGIC := '0'; 118 signal patch_B_sig : STD_LOGIC := '0'; 119 signal patch_C_sig : STD_LOGIC := '0'; 120 signal patch_D_sig : STD_LOGIC := '0'; 121 signal trigger_sig : STD_LOGIC := '0'; 112 122 113 123 -- Clock period definitions … … 147 157 ); 148 158 159 --differential output buffer for patch A 160 OBUFDS_LVDS_33_A : OBUFDS_LVDS_33 161 port map( 162 O => patch_A_p, 163 OB => patch_A_n, 164 I => patch_A_sig 165 ); 166 167 OBUFDS_LVDS_33_B : OBUFDS_LVDS_33 168 port map( 169 O => patch_B_p, 170 OB => patch_B_n, 171 I => patch_B_sig 172 ); 173 174 OBUFDS_LVDS_33_C : OBUFDS_LVDS_33 175 port map( 176 O => patch_C_p, 177 OB => patch_C_n, 178 I => patch_C_sig 179 ); 180 181 OBUFDS_LVDS_33_D : OBUFDS_LVDS_33 182 port map( 183 O => patch_D_p, 184 OB => patch_D_n, 185 I => patch_D_sig 186 ); 187 188 OBUFDS_LVDS_33_t : OBUFDS_LVDS_33 189 port map( 190 O => trig_prim_p, 191 OB => trig_prim_n, 192 I => trigger_sig 193 ); 194 149 195 -- Clock process definitions 150 196 ext_clk_proc: process … … 158 204 -- Stimulus process 159 205 stim_proc: process 160 begin 161 -- hold reset state for 100ms. 162 wait for 100ms; 206 begin 207 -- FTU not yet initialized 208 wait for 10us; 209 trigger_sig <= '1'; 210 wait for 5ns; 211 trigger_sig <= '0'; 212 wait for 100us; 213 trigger_sig <= '1'; 214 wait for 5ns; 215 trigger_sig <= '0'; 216 -- now FTU is initialized 217 wait for 4us; 218 trigger_sig <= '1'; 219 wait for 5ns; 220 trigger_sig <= '0'; 221 wait for 4us; 222 trigger_sig <= '1'; 223 wait for 5ns; 224 trigger_sig <= '0'; 225 wait for 22us; 226 trigger_sig <= '1'; 227 wait for 5ns; 228 trigger_sig <= '0'; 229 wait; 163 230 164 wait for ext_clk_period*10;165 166 -- insert stimulus here167 168 wait;169 231 end process stim_proc; 170 232
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