Changeset 9890 for firmware/FTU/counter

Timestamp:

08/24/10 13:39:00 (14 years ago)

Author:

weitzel

Message:

overflow register implemented for FTU rate counter

File:

• firmware/FTU/counter/FTU_rate_counter.vhd (modified) (4 diffs)

firmware/FTU/counter/FTU_rate_counter.vhd

@@ -39 +39 @@
     trigger    : in  std_logic;
     prescaling : in  std_logic_vector(7 downto 0);
-    counts     : out integer range 0 to 2**16 - 1;
-    overflow   : out std_logic
+    counts     : out integer range 0 to 2**16 - 1 := 0;
+    overflow   : out std_logic := '0';
+    new_rate   : out std_logic
   );
 end FTU_rate_counter;
@@ -51 +52 @@
   signal clk_1M_sig      : std_logic;
   signal overflow_sig    : std_logic := '0';
+  signal new_rate_sig    : std_logic := '0';
   
   component Clock_Divider
@@ -67 +69 @@
     );
   
-  process(cntr_reset, clk_1M_sig)    
+  process(cntr_reset, clk_1M_sig)
+
     variable clk_cntr : integer range 0 to 128*COUNTER_FREQUENCY := 0;
+
   begin
-    if (cntr_reset = '1') then
-      counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2)*COUNTER_FREQUENCY;
-      clk_cntr := 0;
+
+    if rising_edge(cntr_reset) then
+      
+      --formula to calculate counting period from prescaling value
+      if (prescaling = "00000000") then
+        counting_period <= COUNTER_FREQUENCY / (2 * CNTR_FREQ_DIVIDER);
+      else
+        counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER);
+      end if;
+      
+      clk_cntr := 0;      
       period_finished <= '1';
+      new_rate_sig <= '0';
+      counts <= 0;
+      overflow <= '0';
+      
     elsif rising_edge(clk_1M_sig) then
       if (clk_cntr < counting_period - 1) then
         clk_cntr := clk_cntr + 1;
         period_finished <= '0';
+        new_rate_sig <= '0';
       else
         clk_cntr := 0;
         period_finished <= '1';
+        new_rate_sig <= '1';
         counts <= trigger_counts;
+        overflow <= overflow_sig;
       end if;
     end if;
@@ -90 +109 @@
     if rising_edge(period_finished) then
       trigger_counts <= 0;
+      overflow_sig <= '0';
     else
       if rising_edge(trigger) then
-        trigger_counts <= trigger_counts + 1;
+        if (trigger_counts < 2**16 - 1) then 
+          trigger_counts <= trigger_counts + 1;
+        else
+          trigger_counts <= 0;
+          overflow_sig <= '1';
+        end if;
       end if;
     end if;
   end process;
-
-  overflow <= overflow_sig;
+  
+  new_rate <= new_rate_sig;
   
 end Behavioral;