Changeset 9890 for firmware/FTU/counter
- Timestamp:
- 08/24/10 13:39:00 (15 years ago)
- File:
-
- 1 edited
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firmware/FTU/counter/FTU_rate_counter.vhd
r9880 r9890 39 39 trigger : in std_logic; 40 40 prescaling : in std_logic_vector(7 downto 0); 41 counts : out integer range 0 to 2**16 - 1; 42 overflow : out std_logic 41 counts : out integer range 0 to 2**16 - 1 := 0; 42 overflow : out std_logic := '0'; 43 new_rate : out std_logic 43 44 ); 44 45 end FTU_rate_counter; … … 51 52 signal clk_1M_sig : std_logic; 52 53 signal overflow_sig : std_logic := '0'; 54 signal new_rate_sig : std_logic := '0'; 53 55 54 56 component Clock_Divider … … 67 69 ); 68 70 69 process(cntr_reset, clk_1M_sig) 71 process(cntr_reset, clk_1M_sig) 72 70 73 variable clk_cntr : integer range 0 to 128*COUNTER_FREQUENCY := 0; 74 71 75 begin 72 if (cntr_reset = '1') then 73 counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2)*COUNTER_FREQUENCY; 74 clk_cntr := 0; 76 77 if rising_edge(cntr_reset) then 78 79 --formula to calculate counting period from prescaling value 80 if (prescaling = "00000000") then 81 counting_period <= COUNTER_FREQUENCY / (2 * CNTR_FREQ_DIVIDER); 82 else 83 counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER); 84 end if; 85 86 clk_cntr := 0; 75 87 period_finished <= '1'; 88 new_rate_sig <= '0'; 89 counts <= 0; 90 overflow <= '0'; 91 76 92 elsif rising_edge(clk_1M_sig) then 77 93 if (clk_cntr < counting_period - 1) then 78 94 clk_cntr := clk_cntr + 1; 79 95 period_finished <= '0'; 96 new_rate_sig <= '0'; 80 97 else 81 98 clk_cntr := 0; 82 99 period_finished <= '1'; 100 new_rate_sig <= '1'; 83 101 counts <= trigger_counts; 102 overflow <= overflow_sig; 84 103 end if; 85 104 end if; … … 90 109 if rising_edge(period_finished) then 91 110 trigger_counts <= 0; 111 overflow_sig <= '0'; 92 112 else 93 113 if rising_edge(trigger) then 94 trigger_counts <= trigger_counts + 1; 114 if (trigger_counts < 2**16 - 1) then 115 trigger_counts <= trigger_counts + 1; 116 else 117 trigger_counts <= 0; 118 overflow_sig <= '1'; 119 end if; 95 120 end if; 96 121 end if; 97 122 end process; 98 99 overflow <= overflow_sig;123 124 new_rate <= new_rate_sig; 100 125 101 126 end Behavioral;
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