Index: firmware/FTU/FTU_control.vhd
===================================================================
--- firmware/FTU/FTU_control.vhd	(revision 9880)
+++ firmware/FTU/FTU_control.vhd	(revision 9890)
@@ -42,4 +42,6 @@
     ram_dob        : IN  STD_LOGIC_VECTOR(15 downto 0);
     rate_array     : IN  rate_array_type;
+    overflow_array : in  STD_LOGIC_VECTOR(7 downto 0);
+    new_rates      : IN  std_logic;
     reset          : OUT std_logic;
     config_start   : OUT std_logic;
@@ -73,7 +75,7 @@
                                                   "0000000000000000");--patch D
 
-  signal rate_array_sig : rate_array_type;  -- initialized in FTU_top  
+  signal rate_array_sig : rate_array_type;  -- initialized in FTU_top
   signal cntr_reset_sig : STD_LOGIC := '0';
-  signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
+  signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0) := "00011101";  -- 29
   
   signal ram_ena_sig  : STD_LOGIC := '0';  -- RAM enable for port A
@@ -87,10 +89,14 @@
 
   --counter to loop through RAM
-  signal ram_ada_cntr    : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
-  signal ram_adb_cntr    : INTEGER range 0 to 2**RAM_ADDR_WIDTH_B := 0;
-  signal ram_dac_cntr    : INTEGER range 0 to (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2) := 0;
-  signal ram_enable_cntr : INTEGER range 0 to (NO_OF_ENABLE + 1) := 0;
-
+  signal ram_ada_cntr     : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
+  signal ram_adb_cntr     : INTEGER range 0 to 2**RAM_ADDR_WIDTH_B := 0;
+  signal ram_dac_cntr     : INTEGER range 0 to (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2) := 0;
+  signal ram_enable_cntr  : INTEGER range 0 to (NO_OF_ENABLE + 1) := 0;
+  signal ram_counter_cntr : INTEGER range 0 to (NO_OF_COUNTER + 2) := 0;  --includes overflow register
+  
   signal wait_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
+
+  signal new_rates_sig  : STD_LOGIC := '0';
+  signal new_rates_busy : STD_LOGIC := '0';
   
   signal new_DACs_in_RAM       : STD_LOGIC := '0';
@@ -98,5 +104,5 @@
   signal new_prescaling_in_RAM : STD_LOGIC := '0';
 
-  type FTU_control_StateType is (IDLE, INIT, RUNNING, CONFIG_ENABLE, CONFIG_DAC, CONFIG_COUNTER, RESET_ALL);
+  type FTU_control_StateType is (IDLE, INIT, RUNNING, CONFIG_ENABLE, CONFIG_DAC, CONFIG_COUNTER, WRITE_RATES, RESET_ALL);
   signal FTU_control_State : FTU_control_StateType;
   
@@ -117,5 +123,5 @@
           config_start_sig <= '0';
           ram_ena_sig <= '0';
-          ram_wea_sig <= "0";                    
+          ram_wea_sig <= "0";
           if (clk_ready = '1') then
             FTU_control_State <= INIT;
@@ -124,4 +130,5 @@
         when INIT =>  -- load default config data to RAM, see also ftu_definitions.vhd for more info
           reset_sig <= '0';
+          new_rates_busy <= '1';
           config_start_sig <= '0';
           ram_ena_sig <= '1';
@@ -175,40 +182,48 @@
             new_enables_in_RAM <= '1';
             new_prescaling_in_RAM <= '1';
+            cntr_reset_sig <= '1';
+            new_rates_busy <= '0';
             FTU_control_State <= RUNNING;
           end if;
                     
         when RUNNING =>  -- count triggers and react to commands from FTM
+          cntr_reset_sig <= '0';
           reset_sig <= '0';
           config_start_sig <= '0';
-          if (new_DACs_in_RAM = '1') then
-            ram_enb_sig <= '1';
-            ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER), RAM_ADDR_WIDTH_B);
-            FTU_control_State <= CONFIG_DAC;
-          elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '1') then
-            ram_enb_sig <= '1';
-            ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B);
-            FTU_control_State <= CONFIG_ENABLE;
-          elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '0' and new_prescaling_in_RAM = '1') then
-            ram_ena_sig <= '1';
-            ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
-            FTU_control_State <= CONFIG_COUNTER;
-          else
-            FTU_control_State <= RUNNING;
+          if (new_rates_sig = '1') then
+            FTU_control_State <= WRITE_RATES;
+          else
+            if (new_DACs_in_RAM = '1') then
+              ram_enb_sig <= '1';
+              ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER), RAM_ADDR_WIDTH_B);
+              FTU_control_State <= CONFIG_DAC;
+            elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '1') then
+              ram_enb_sig <= '1';
+              ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B);
+              FTU_control_State <= CONFIG_ENABLE;
+            elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '0' and new_prescaling_in_RAM = '1') then
+              ram_ena_sig <= '1';
+              ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
+              FTU_control_State <= CONFIG_COUNTER;
+            else
+              FTU_control_State <= RUNNING;
+            end if;
           end if;
 
         when CONFIG_COUNTER =>
           wait_cntr <= wait_cntr + 1;
+          new_rates_busy <= '1';
           if (wait_cntr = 0) then
             FTU_control_State <= CONFIG_COUNTER;
           elsif (wait_cntr = 1) then
             prescaling_sig <= ram_doa;
+            FTU_control_State <= CONFIG_COUNTER;
+          else
             cntr_reset_sig <= '1';
-            FTU_control_State <= CONFIG_COUNTER;
-          else
-            cntr_reset_sig <= '0';
             ram_ada_sig <= (others => '0');
             wait_cntr <= 0;
             new_prescaling_in_RAM <= '0';
             ram_ena_sig <= '0';
+            new_rates_busy <= '0';
             FTU_control_State <= RUNNING;
           end if;
@@ -216,4 +231,5 @@
         when CONFIG_ENABLE =>
           ram_enable_cntr <= ram_enable_cntr + 1;
+          new_rates_busy <= '1';
           if (ram_enable_cntr = 0) then
             ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
@@ -222,5 +238,5 @@
             ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
             enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
-            FTU_control_State <= CONFIG_ENABLE;            
+            FTU_control_State <= CONFIG_ENABLE;
           else
             ram_adb_sig <= (others => '0');
@@ -228,8 +244,11 @@
             new_enables_in_RAM <= '0';
             ram_enb_sig <= '0';
+            cntr_reset_sig <= '1';
+            new_rates_busy <= '0';
             FTU_control_State <= RUNNING;
           end if;
           
         when CONFIG_DAC =>
+          new_rates_busy <= '1';
           if (ram_dac_cntr <= (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2)) then            
             ram_dac_cntr <= ram_dac_cntr + 1;
@@ -254,4 +273,6 @@
               ram_dac_cntr <= 0;
               new_DACs_in_RAM <= '0';
+              cntr_reset_sig <= '1';
+              new_rates_busy <= '0';
               FTU_control_State <= RUNNING;
             elsif (config_ready = '0' and config_started = '1') then
@@ -263,5 +284,32 @@
             end if;
           end if;
-          
+
+        when WRITE_RATES =>  -- write trigger/patch rates to RAM B and overflow register to RAM A
+          new_rates_busy <= '1';          
+          ram_counter_cntr <= ram_counter_cntr + 1;
+          if (ram_counter_cntr < NO_OF_COUNTER) then
+            ram_enb_sig <= '1';
+            ram_web_sig <= "1";         
+            ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr), RAM_ADDR_WIDTH_B);
+            ram_dib_sig <= conv_std_logic_vector(rate_array_sig(ram_counter_cntr), 16);
+            FTU_control_State <= WRITE_RATES;
+          elsif (ram_counter_cntr = NO_Of_COUNTER) then
+            ram_dib_sig <= (others => '0');
+            ram_adb_sig <= (others => '0');
+            ram_enb_sig <= '0';
+            ram_web_sig <= "0";
+            ram_ena_sig <= '1';
+            ram_wea_sig <= "1"; 
+            ram_ada_sig <= conv_std_logic_vector(NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1, RAM_ADDR_WIDTH_A);
+            ram_dia_sig <= overflow_array;
+            FTU_control_State <= WRITE_RATES;
+          else              
+            ram_ena_sig <= '0';
+            ram_wea_sig <= "0"; 
+            ram_counter_cntr <= 0;            
+            new_rates_busy <= '0';
+            FTU_control_State <= RUNNING;
+          end if;
+            
         when RESET_ALL =>  -- reset/clear and start from scratch
           reset_sig <= '1';
@@ -272,4 +320,13 @@
   end process FTU_control_FSM;
 
+  detect_new_rates: process(new_rates, new_rates_busy)
+  begin
+    if (new_rates_busy = '0' and rising_edge(new_rates)) then
+      new_rates_sig <= '1';
+    else
+      new_rates_sig <= '0';
+    end if;
+  end process detect_new_rates;
+  
   reset <= reset_sig;
   
@@ -280,4 +337,5 @@
 
   rate_array_sig <= rate_array;
+  
   cntr_reset <= cntr_reset_sig;
   prescaling <= prescaling_sig;
Index: firmware/FTU/FTU_top.vhd
===================================================================
--- firmware/FTU/FTU_top.vhd	(revision 9880)
+++ firmware/FTU/FTU_top.vhd	(revision 9890)
@@ -97,8 +97,14 @@
 
   --rate counter signals
-  signal cntr_reset_sig : STD_LOGIC;  -- initialized in FTU_control  
-  signal rate_array_sig : rate_array_type := (0,0,0,0,0);
-  signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0);
+  signal cntr_reset_sig : STD_LOGIC;  -- initialized in FTU_control
+  signal rate_array_sig : rate_array_type;  -- initialized by counters
+  signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0);  -- initialized in FTU_control  
   signal overflow_array : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
+  signal new_rate_A_sig : STD_LOGIC;  -- initialized by patch A counter
+  signal new_rate_B_sig : STD_LOGIC;  -- initialized by patch B counter
+  signal new_rate_C_sig : STD_LOGIC;  -- initialized by patch C counter
+  signal new_rate_D_sig : STD_LOGIC;  -- initialized by patch D counter
+  signal new_rate_t_sig : STD_LOGIC;  -- initialized by trigger counter
+  signal new_rates_sig  : STD_LOGIC := '0';
   
   signal clk_50M_sig   : STD_LOGIC;         -- generated by internal DCM
@@ -133,5 +139,6 @@
       prescaling : in  std_logic_vector(7 downto 0);
       counts     : out integer range 0 to 2**16 - 1;
-      overflow   : out std_logic
+      overflow   : out std_logic;
+      new_rate   : out std_logic
       );
   end component;
@@ -146,4 +153,6 @@
       ram_dob        : IN  STD_LOGIC_VECTOR(15 downto 0);
       rate_array     : IN  rate_array_type;
+      overflow_array : in  STD_LOGIC_VECTOR(7 downto 0);
+      new_rates      : IN  std_logic;
       reset          : OUT std_logic;
       config_start   : OUT std_logic;
@@ -206,4 +215,6 @@
   enables_D <= enable_array_sig(3)(8 downto 0);
 
+  new_rates_sig <= new_rate_A_sig and new_rate_B_sig and new_rate_C_sig and new_rate_D_sig and new_rate_t_sig; 
+  
   --differential input buffer for patch A
   IBUFDS_LVDS_33_A : IBUFDS_LVDS_33
@@ -261,5 +272,6 @@
       prescaling => prescaling_sig,
       counts     => rate_array_sig(0),
-      overflow   => overflow_array(0)
+      overflow   => overflow_array(0),
+      new_rate   => new_rate_A_sig 
     );
 
@@ -271,5 +283,6 @@
       prescaling => prescaling_sig,
       counts     => rate_array_sig(1),
-      overflow   => overflow_array(1)
+      overflow   => overflow_array(1),
+      new_rate   => new_rate_B_sig 
     );
 
@@ -281,5 +294,6 @@
       prescaling => prescaling_sig,
       counts     => rate_array_sig(2),
-      overflow   => overflow_array(2)
+      overflow   => overflow_array(2),
+      new_rate   => new_rate_C_sig 
     );
 
@@ -291,5 +305,6 @@
       prescaling => prescaling_sig,
       counts     => rate_array_sig(3),
-      overflow   => overflow_array(3)
+      overflow   => overflow_array(3),
+      new_rate   => new_rate_D_sig 
     );
 
@@ -301,5 +316,6 @@
       prescaling => prescaling_sig,
       counts     => rate_array_sig(4),
-      overflow   => overflow_array(4)
+      overflow   => overflow_array(4),
+      new_rate   => new_rate_t_sig 
     );
   
@@ -313,4 +329,6 @@
       ram_dob        => ram_dob_sig,
       rate_array     => rate_array_sig,
+      overflow_array => overflow_array,
+      new_rates      => new_rates_sig,
       reset          => reset_sig,
       config_start   => config_start_sig,
Index: firmware/FTU/FTU_top_tb.vhd
===================================================================
--- firmware/FTU/FTU_top_tb.vhd	(revision 9880)
+++ firmware/FTU/FTU_top_tb.vhd	(revision 9890)
@@ -210,5 +210,9 @@
     wait for 5ns;
     trigger_sig <= '0';
-    wait for 100us;
+    wait for 99us;
+    trigger_sig <= '1';
+    wait for 5ns;
+    trigger_sig <= '0';
+    wait for 1us;
     trigger_sig <= '1';
     wait for 5ns;
Index: firmware/FTU/counter/FTU_rate_counter.vhd
===================================================================
--- firmware/FTU/counter/FTU_rate_counter.vhd	(revision 9880)
+++ firmware/FTU/counter/FTU_rate_counter.vhd	(revision 9890)
@@ -39,6 +39,7 @@
     trigger    : in  std_logic;
     prescaling : in  std_logic_vector(7 downto 0);
-    counts     : out integer range 0 to 2**16 - 1;
-    overflow   : out std_logic
+    counts     : out integer range 0 to 2**16 - 1 := 0;
+    overflow   : out std_logic := '0';
+    new_rate   : out std_logic
   );
 end FTU_rate_counter;
@@ -51,4 +52,5 @@
   signal clk_1M_sig      : std_logic;
   signal overflow_sig    : std_logic := '0';
+  signal new_rate_sig    : std_logic := '0';
   
   component Clock_Divider
@@ -67,19 +69,36 @@
     );
   
-  process(cntr_reset, clk_1M_sig)    
+  process(cntr_reset, clk_1M_sig)
+
     variable clk_cntr : integer range 0 to 128*COUNTER_FREQUENCY := 0;
+
   begin
-    if (cntr_reset = '1') then
-      counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2)*COUNTER_FREQUENCY;
-      clk_cntr := 0;
+
+    if rising_edge(cntr_reset) then
+      
+      --formula to calculate counting period from prescaling value
+      if (prescaling = "00000000") then
+        counting_period <= COUNTER_FREQUENCY / (2 * CNTR_FREQ_DIVIDER);
+      else
+        counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER);
+      end if;
+      
+      clk_cntr := 0;      
       period_finished <= '1';
+      new_rate_sig <= '0';
+      counts <= 0;
+      overflow <= '0';
+      
     elsif rising_edge(clk_1M_sig) then
       if (clk_cntr < counting_period - 1) then
         clk_cntr := clk_cntr + 1;
         period_finished <= '0';
+        new_rate_sig <= '0';
       else
         clk_cntr := 0;
         period_finished <= '1';
+        new_rate_sig <= '1';
         counts <= trigger_counts;
+        overflow <= overflow_sig;
       end if;
     end if;
@@ -90,12 +109,18 @@
     if rising_edge(period_finished) then
       trigger_counts <= 0;
+      overflow_sig <= '0';
     else
       if rising_edge(trigger) then
-        trigger_counts <= trigger_counts + 1;
+        if (trigger_counts < 2**16 - 1) then 
+          trigger_counts <= trigger_counts + 1;
+        else
+          trigger_counts <= 0;
+          overflow_sig <= '1';
+        end if;
       end if;
     end if;
   end process;
-
-  overflow <= overflow_sig;
+  
+  new_rate <= new_rate_sig;
   
 end Behavioral;
Index: firmware/FTU/ftu_definitions.vhd
===================================================================
--- firmware/FTU/ftu_definitions.vhd	(revision 9880)
+++ firmware/FTU/ftu_definitions.vhd	(revision 9890)
@@ -57,5 +57,6 @@
   --internal FPGA clock frequency and rate counter frequency 
   constant INT_CLK_FREQUENCY : integer := 50000000;  -- 50MHz
-  constant COUNTER_FREQUENCY : integer :=  1000000;  --  1MHZ, has to be smaller than INT_CLK_FREQUENCY
+  constant COUNTER_FREQUENCY : integer :=  1000000;  -- has to be smaller than INT_CLK_FREQUENCY
+  constant CNTR_FREQ_DIVIDER : integer :=   500000;
     
   --32byte dual-port RAM, port A: 8byte, port B: 16byte
