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uid 402,0
va (VaSet
)
xt "39000,27500,44200,28500"
st "config_rd_en"
blo "39000,28300"
tm "WireNameMgr"
)
)
)
*34 (PortIoOut
uid 403,0
shape (CompositeShape
uid 404,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 405,0
sl 0
ro 270
xt "36500,33625,38000,34375"
)
(Line
uid 406,0
sl 0
ro 270
xt "36000,34000,36500,34000"
pts [
"36000,34000"
"36500,34000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 407,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 408,0
va (VaSet
)
xt "39000,33500,42700,34500"
st "dac_array"
blo "39000,34300"
tm "WireNameMgr"
)
)
)
*35 (PortIoOut
uid 409,0
shape (CompositeShape
uid 410,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 411,0
sl 0
ro 270
xt "36500,34625,38000,35375"
)
(Line
uid 412,0
sl 0
ro 270
xt "36000,35000,36500,35000"
pts [
"36000,35000"
"36500,35000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 413,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 414,0
va (VaSet
)
xt "39000,34500,42400,35500"
st "roi_array"
blo "39000,35300"
tm "WireNameMgr"
)
)
)
*36 (PortIoOut
uid 415,0
shape (CompositeShape
uid 416,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 417,0
sl 0
ro 270
xt "36500,31625,38000,32375"
)
(Line
uid 418,0
sl 0
ro 270
xt "36000,32000,36500,32000"
pts [
"36000,32000"
"36500,32000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 419,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 420,0
va (VaSet
)
xt "39000,31500,45600,32500"
st "config_data_valid"
blo "39000,32300"
tm "WireNameMgr"
)
)
)
*37 (PortIoOut
uid 421,0
shape (CompositeShape
uid 422,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 423,0
sl 0
ro 270
xt "36500,32625,38000,33375"
)
(Line
uid 424,0
sl 0
ro 270
xt "36000,33000,36500,33000"
pts [
"36000,33000"
"36500,33000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 425,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 426,0
va (VaSet
)
xt "39000,32500,43800,33500"
st "config_busy"
blo "39000,33300"
tm "WireNameMgr"
)
)
)
*38 (SaComponent
uid 960,0
optionalChildren [
*39 (CptPort
uid 900,0
ps "OnEdgeStrategy"
shape (Triangle
uid 901,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "6250,23625,7000,24375"
)
tg (CPTG
uid 902,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 903,0
va (VaSet
)
xt "8000,23500,9300,24500"
st "clk"
blo "8000,24300"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*40 (CptPort
uid 904,0
ps "OnEdgeStrategy"
shape (Triangle
uid 905,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,28625,32750,29375"
)
tg (CPTG
uid 906,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 907,0
va (VaSet
)
xt "25900,28500,31000,29500"
st "config_ready"
ju 2
blo "31000,29300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_ready"
t "std_logic"
preAdd 0
posAdd 0
o 3
suid 3,0
i "'0'"
)
)
)
*41 (CptPort
uid 908,0
ps "OnEdgeStrategy"
shape (Triangle
uid 909,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,29625,32750,30375"
)
tg (CPTG
uid 910,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 911,0
va (VaSet
)
xt "26200,29500,31000,30500"
st "config_start"
ju 2
blo "31000,30300"
)
)
thePort (LogicalPort
decl (Decl
n "config_start"
t "std_logic"
preAdd 0
posAdd 0
o 5
suid 4,0
)
)
)
*42 (CptPort
uid 912,0
ps "OnEdgeStrategy"
shape (Diamond
uid 913,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,24625,32750,25375"
)
tg (CPTG
uid 914,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 915,0
va (VaSet
)
xt "23300,24500,31000,25500"
st "config_data : (15:0)"
ju 2
blo "31000,25300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "config_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
preAdd 0
posAdd 0
o 6
suid 5,0
i "(others => 'Z')"
)
)
)
*43 (CptPort
uid 916,0
ps "OnEdgeStrategy"
shape (Triangle
uid 917,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,23625,32750,24375"
)
tg (CPTG
uid 918,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 919,0
va (VaSet
)
xt "17600,23500,31000,24500"
st "config_addr : (ADDR_WIDTH - 1:0)"
ju 2
blo "31000,24300"
)
)
thePort (LogicalPort
decl (Decl
n "config_addr"
t "std_logic_vector"
b "(ADDR_WIDTH - 1 DOWNTO 0)"
preAdd 0
posAdd 0
o 7
suid 6,0
)
)
)
*44 (CptPort
uid 920,0
ps "OnEdgeStrategy"
shape (Triangle
uid 921,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,26625,32750,27375"
)
tg (CPTG
uid 922,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 923,0
va (VaSet
)
xt "25700,26500,31000,27500"
st "config_wr_en"
ju 2
blo "31000,27300"
)
)
thePort (LogicalPort
decl (Decl
n "config_wr_en"
t "std_logic"
preAdd 0
posAdd 0
o 8
suid 7,0
)
)
)
*45 (CptPort
uid 924,0
ps "OnEdgeStrategy"
shape (Triangle
uid 925,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,27625,32750,28375"
)
tg (CPTG
uid 926,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 927,0
va (VaSet
)
xt "25800,27500,31000,28500"
st "config_rd_en"
ju 2
blo "31000,28300"
)
)
thePort (LogicalPort
decl (Decl
n "config_rd_en"
t "std_logic"
preAdd 0
posAdd 0
o 9
suid 8,0
)
)
)
*46 (CptPort
uid 928,0
ps "OnEdgeStrategy"
shape (Triangle
uid 929,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,31625,32750,32375"
)
tg (CPTG
uid 930,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 931,0
va (VaSet
)
xt "24400,31500,31000,32500"
st "config_data_valid"
ju 2
blo "31000,32300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_data_valid"
t "std_logic"
preAdd 0
posAdd 0
o 10
suid 9,0
i "'0'"
)
)
)
*47 (CptPort
uid 932,0
ps "OnEdgeStrategy"
shape (Triangle
uid 933,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,32625,32750,33375"
)
tg (CPTG
uid 934,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 935,0
va (VaSet
)
xt "26200,32500,31000,33500"
st "config_busy"
ju 2
blo "31000,33300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_busy"
t "std_logic"
preAdd 0
posAdd 0
o 11
suid 10,0
i "'0'"
)
)
)
*48 (CptPort
uid 936,0
ps "OnEdgeStrategy"
shape (Triangle
uid 937,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,33625,32750,34375"
)
tg (CPTG
uid 938,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 939,0
va (VaSet
)
xt "27300,33500,31000,34500"
st "dac_array"
ju 2
blo "31000,34300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dac_array"
t "dac_array_type"
preAdd 0
posAdd 0
o 15
suid 15,0
)
)
)
*49 (CptPort
uid 940,0
ps "OnEdgeStrategy"
shape (Triangle
uid 941,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,34625,32750,35375"
)
tg (CPTG
uid 942,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 943,0
va (VaSet
)
xt "27600,34500,31000,35500"
st "roi_array"
ju 2
blo "31000,35300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "roi_array"
t "roi_array_type"
preAdd 0
posAdd 0
o 16
suid 16,0
)
)
)
*50 (CptPort
uid 944,0
ps "OnEdgeStrategy"
shape (Triangle
uid 945,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,37625,32750,38375"
)
tg (CPTG
uid 946,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 947,0
va (VaSet
)
xt "23100,37500,31000,38500"
st "ram_data_in : (15:0)"
ju 2
blo "31000,38300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_data_in"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 13
suid 19,0
)
)
)
*51 (CptPort
uid 948,0
ps "OnEdgeStrategy"
shape (Triangle
uid 949,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,38625,32750,39375"
)
tg (CPTG
uid 950,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 951,0
va (VaSet
)
xt "23100,38500,31000,39500"
st "ram_write_en : (0:0)"
ju 2
blo "31000,39300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_write_en"
t "std_logic_vector"
b "(0 DOWNTO 0)"
o 14
suid 20,0
)
)
)
*52 (CptPort
uid 952,0
ps "OnEdgeStrategy"
shape (Triangle
uid 953,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "6250,38625,7000,39375"
)
tg (CPTG
uid 954,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 955,0
va (VaSet
)
xt "8000,38500,16300,39500"
st "ram_data_out : (15:0)"
blo "8000,39300"
)
)
thePort (LogicalPort
decl (Decl
n "ram_data_out"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 2
suid 21,0
)
)
)
*53 (CptPort
uid 956,0
ps "OnEdgeStrategy"
shape (Triangle
uid 957,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,39625,32750,40375"
)
tg (CPTG
uid 958,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 959,0
va (VaSet
)
xt "18400,39500,31000,40500"
st "ram_addr : (ADDR_WIDTH - 1:0)"
ju 2
blo "31000,40300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_addr"
t "std_logic_vector"
b "(ADDR_WIDTH - 1 DOWNTO 0)"
o 12
suid 22,0
)
)
)
*54 (CptPort
uid 1078,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1079,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,30625,32750,31375"
)
tg (CPTG
uid 1080,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1081,0
va (VaSet
)
xt "25400,30500,31000,31500"
st "config_started"
ju 2
blo "31000,31300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_started"
t "std_logic"
o 4
suid 23,0
i "'0'"
)
)
)
*55 (CptPort
uid 1198,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1199,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,21625,32750,22375"
)
tg (CPTG
uid 1200,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1201,0
va (VaSet
)
xt "23800,21500,31000,22500"
st "drs_address : (3:0)"
ju 2
blo "31000,22300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_address"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 17
suid 24,0
)
)
)
*56 (CptPort
uid 1202,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1203,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32000,20625,32750,21375"
)
tg (CPTG
uid 1204,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1205,0
va (VaSet
)
xt "23800,20500,31000,21500"
st "drs_address_mode"
ju 2
blo "31000,21300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_address_mode"
t "std_logic"
o 18
suid 25,0
)
)
)
]
shape (Rectangle
uid 961,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "7000,20000,32000,41000"
)
oxt "42000,14000,67000,32000"
ttg (MlTextGroup
uid 962,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*57 (Text
uid 963,0
va (VaSet
font "Arial,8,1"
)
xt "6950,42000,13150,43000"
st "FACT_FAD_lib"
blo "6950,42800"
tm "BdLibraryNameMgr"
)
*58 (Text
uid 964,0
va (VaSet
font "Arial,8,1"
)
xt "6950,43000,14050,44000"
st "control_manager"
blo "6950,43800"
tm "CptNameMgr"
)
*59 (Text
uid 965,0
va (VaSet
font "Arial,8,1"
)
xt "6950,44000,14650,45000"
st "I_control_manager"
blo "6950,44800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 966,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 967,0
text (MLText
uid 968,0
va (VaSet
font "Courier New,8,0"
)
xt "10000,17600,27500,20000"
st "NO_OF_ROI  = 36    ( integer )  
NO_OF_DAC  = 8     ( integer )  
ADDR_WIDTH = 8     ( integer )  "
)
header ""
)
elements [
(GiElement
name "NO_OF_ROI"
type "integer"
value "36"
)
(GiElement
name "NO_OF_DAC"
type "integer"
value "8"
)
(GiElement
name "ADDR_WIDTH"
type "integer"
value "8"
)
]
)
viewicon (ZoomableIcon
uid 969,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "7250,39250,8750,40750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*60 (SaComponent
uid 993,0
optionalChildren [
*61 (CptPort
uid 970,0
ps "OnEdgeStrategy"
shape (Triangle
uid 971,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42625,41250,43375,42000"
)
tg (CPTG
uid 972,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 973,0
ro 270
va (VaSet
)
xt "42500,43000,43500,44700"
st "clka"
ju 2
blo "43300,43000"
)
)
thePort (LogicalPort
decl (Decl
n "clka"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*62 (CptPort
uid 974,0
ps "OnEdgeStrategy"
shape (Triangle
uid 975,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "39250,45625,40000,46375"
)
tg (CPTG
uid 976,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 977,0
va (VaSet
)
xt "41000,45500,45800,46500"
st "dina : (15:0)"
blo "41000,46300"
)
)
thePort (LogicalPort
decl (Decl
n "dina"
t "std_logic_VECTOR"
b "(15 downto 0)"
preAdd 0
posAdd 0
o 2
suid 2,0
)
)
)
*63 (CptPort
uid 978,0
ps "OnEdgeStrategy"
shape (Triangle
uid 979,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "39250,47625,40000,48375"
)
tg (CPTG
uid 980,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 981,0
va (VaSet
)
xt "41000,47500,45900,48500"
st "addra : (7:0)"
blo "41000,48300"
)
)
thePort (LogicalPort
decl (Decl
n "addra"
t "std_logic_VECTOR"
b "(7 downto 0)"
preAdd 0
posAdd 0
o 3
suid 3,0
)
)
)
*64 (CptPort
uid 982,0
ps "OnEdgeStrategy"
shape (Triangle
uid 983,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "39250,46625,40000,47375"
)
tg (CPTG
uid 984,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 985,0
va (VaSet
)
xt "41000,46500,45300,47500"
st "wea : (0:0)"
blo "41000,47300"
)
)
thePort (LogicalPort
decl (Decl
n "wea"
t "std_logic_VECTOR"
b "(0 downto 0)"
preAdd 0
posAdd 0
o 4
suid 4,0
)
)
)
*65 (CptPort
uid 986,0
ps "OnEdgeStrategy"
shape (Triangle
uid 987,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "50000,43625,50750,44375"
)
tg (CPTG
uid 988,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 989,0
va (VaSet
)
xt "43800,43500,49000,44500"
st "douta : (15:0)"
ju 2
blo "49000,44300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "douta"
t "std_logic_VECTOR"
b "(15 downto 0)"
preAdd 0
posAdd 0
o 5
suid 5,0
)
)
)
]
shape (Rectangle
uid 994,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "40000,42000,50000,52000"
)
oxt "30000,7000,40000,17000"
ttg (MlTextGroup
uid 995,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*66 (Text
uid 996,0
va (VaSet
font "Arial,8,1"
)
xt "40200,52000,46400,53000"
st "FACT_FAD_lib"
blo "40200,52800"
tm "BdLibraryNameMgr"
)
*67 (Text
uid 997,0
va (VaSet
font "Arial,8,1"
)
xt "40200,53000,50100,54000"
st "controlRAM_16bit_x256"
blo "40200,53800"
tm "CptNameMgr"
)
*68 (Text
uid 998,0
va (VaSet
font "Arial,8,1"
)
xt "40200,54000,46100,55000"
st "I_control_ram"
blo "40200,54800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 999,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1000,0
text (MLText
uid 1001,0
va (VaSet
font "Courier New,8,0"
)
xt "39500,41000,39500,41000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 1002,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "40250,50250,41750,51750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*69 (Net
uid 1082,0
decl (Decl
n "config_started"
t "std_logic"
o 16
suid 18,0
i "'0'"
)
declText (MLText
uid 1083,0
va (VaSet
font "Courier New,8,0"
)
xt "29000,8600,48500,9400"
st "config_started    : std_logic := '0'
"
)
)
*70 (PortIoOut
uid 1090,0
shape (CompositeShape
uid 1091,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1092,0
sl 0
ro 270
xt "36500,30625,38000,31375"
)
(Line
uid 1093,0
sl 0
ro 270
xt "36000,31000,36500,31000"
pts [
"36000,31000"
"36500,31000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 1094,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1095,0
va (VaSet
)
xt "39000,30500,44600,31500"
st "config_started"
blo "39000,31300"
tm "WireNameMgr"
)
)
)
*71 (Net
uid 1206,0
decl (Decl
n "drs_address"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 17
suid 19,0
)
declText (MLText
uid 1207,0
va (VaSet
font "Courier New,8,0"
)
xt "29000,10200,55000,11000"
st "drs_address       : std_logic_vector(3 DOWNTO 0)
"
)
)
*72 (PortIoOut
uid 1214,0
shape (CompositeShape
uid 1215,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1216,0
sl 0
ro 270
xt "36500,21625,38000,22375"
)
(Line
uid 1217,0
sl 0
ro 270
xt "36000,22000,36500,22000"
pts [
"36000,22000"
"36500,22000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 1218,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1219,0
va (VaSet
)
xt "39000,21500,44000,22500"
st "drs_address"
blo "39000,22300"
tm "WireNameMgr"
)
)
)
*73 (Net
uid 1220,0
decl (Decl
n "drs_address_mode"
t "std_logic"
o 18
suid 20,0
)
declText (MLText
uid 1221,0
va (VaSet
font "Courier New,8,0"
)
xt "29000,11000,45000,11800"
st "drs_address_mode  : std_logic
"
)
)
*74 (PortIoOut
uid 1228,0
shape (CompositeShape
uid 1229,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1230,0
sl 0
ro 270
xt "36500,20625,38000,21375"
)
(Line
uid 1231,0
sl 0
ro 270
xt "36000,21000,36500,21000"
pts [
"36000,21000"
"36500,21000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 1232,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1233,0
va (VaSet
)
xt "39000,20500,46200,21500"
st "drs_address_mode"
blo "39000,21300"
tm "WireNameMgr"
)
)
)
*75 (Wire
uid 227,0
shape (OrthoPolyLine
uid 228,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "32750,24000,36000,24000"
pts [
"36000,24000"
"32750,24000"
]
)
start &31
end &43
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 231,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 232,0
va (VaSet
isHidden 1
)
xt "39000,23000,43800,24000"
st "config_addr"
blo "39000,23800"
tm "WireNameMgr"
)
)
on &14
)
*76 (Wire
uid 233,0
shape (OrthoPolyLine
uid 234,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "32750,39000,39250,47000"
pts [
"39250,47000"
"34000,47000"
"34000,39000"
"32750,39000"
]
)
start &64
end &51
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 235,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 236,0
va (VaSet
)
xt "34000,46000,40300,47000"
st "ram_wren : (0:0)"
blo "34000,46800"
tm "WireNameMgr"
)
)
on &13
)
*77 (Wire
uid 237,0
shape (OrthoPolyLine
uid 238,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "32750,38000,39250,46000"
pts [
"39250,46000"
"35000,46000"
"35000,38000"
"32750,38000"
]
)
start &62
end &50
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 239,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 240,0
va (VaSet
)
xt "33000,37000,40900,38000"
st "ram_data_in : (15:0)"
blo "33000,37800"
tm "WireNameMgr"
)
)
on &15
)
*78 (Wire
uid 241,0
shape (OrthoPolyLine
uid 242,0
va (VaSet
vasetType 3
)
xt "4000,20000,6250,24000"
pts [
"4000,20000"
"5000,20000"
"5000,24000"
"6250,24000"
]
)
start &27
end &39
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 245,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 246,0
va (VaSet
isHidden 1
)
xt "6000,19000,7300,20000"
st "clk"
blo "6000,19800"
tm "WireNameMgr"
)
)
on &12
)
*79 (Wire
uid 255,0
shape (OrthoPolyLine
uid 256,0
va (VaSet
vasetType 3
)
xt "32750,32000,36000,32000"
pts [
"32750,32000"
"36000,32000"
]
)
start &46
end &36
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 259,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 260,0
va (VaSet
isHidden 1
)
xt "39000,30000,45600,31000"
st "config_data_valid"
blo "39000,30800"
tm "WireNameMgr"
)
)
on &16
)
*80 (Wire
uid 261,0
shape (OrthoPolyLine
uid 262,0
va (VaSet
vasetType 3
)
xt "32750,33000,36000,33000"
pts [
"32750,33000"
"36000,33000"
]
)
start &47
end &37
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 265,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 266,0
va (VaSet
isHidden 1
)
xt "39000,31000,43800,32000"
st "config_busy"
blo "39000,31800"
tm "WireNameMgr"
)
)
on &17
)
*81 (Wire
uid 267,0
shape (OrthoPolyLine
uid 268,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "32750,25000,36000,25000"
pts [
"36000,25000"
"32750,25000"
]
)
start &30
end &42
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 271,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 272,0
va (VaSet
isHidden 1
)
xt "39000,24000,43700,25000"
st "config_data"
blo "39000,24800"
tm "WireNameMgr"
)
)
on &18
)
*82 (Wire
uid 273,0
shape (OrthoPolyLine
uid 274,0
va (VaSet
vasetType 3
)
xt "32750,35000,36000,35000"
pts [
"32750,35000"
"36000,35000"
]
)
start &49
end &35
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 277,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 278,0
va (VaSet
isHidden 1
)
xt "39000,34000,42400,35000"
st "roi_array"
blo "39000,34800"
tm "WireNameMgr"
)
)
on &19
)
*83 (Wire
uid 279,0
shape (OrthoPolyLine
uid 280,0
va (VaSet
vasetType 3
)
xt "43000,38000,43000,41250"
pts [
"43000,38000"
"43000,41250"
]
)
end &61
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 283,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 284,0
va (VaSet
)
xt "44000,37000,45300,38000"
st "clk"
blo "44000,37800"
tm "WireNameMgr"
)
)
on &12
)
*84 (Wire
uid 285,0
shape (OrthoPolyLine
uid 286,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "32750,40000,39250,48000"
pts [
"32750,40000"
"33000,40000"
"33000,48000"
"39250,48000"
]
)
start &53
end &63
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 287,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 288,0
va (VaSet
)
xt "33000,47000,39200,48000"
st "ram_addr : (7:0)"
blo "33000,47800"
tm "WireNameMgr"
)
)
on &20
)
*85 (Wire
uid 289,0
shape (OrthoPolyLine
uid 290,0
va (VaSet
vasetType 3
)
xt "32750,30000,36000,30000"
pts [
"36000,30000"
"32750,30000"
]
)
start &29
end &41
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 293,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 294,0
va (VaSet
isHidden 1
)
xt "39000,29000,43800,30000"
st "config_start"
blo "39000,29800"
tm "WireNameMgr"
)
)
on &25
)
*86 (Wire
uid 295,0
shape (OrthoPolyLine
uid 296,0
va (VaSet
vasetType 3
)
xt "32750,27000,36000,27000"
pts [
"36000,27000"
"32750,27000"
]
)
start &32
end &44
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 299,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 300,0
va (VaSet
isHidden 1
)
xt "39000,26000,44300,27000"
st "config_wr_en"
blo "39000,26800"
tm "WireNameMgr"
)
)
on &21
)
*87 (Wire
uid 301,0
shape (OrthoPolyLine
uid 302,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "3000,39000,52000,56000"
pts [
"6250,39000"
"3000,39000"
"3000,56000"
"52000,56000"
"52000,44000"
"50750,44000"
]
)
start &52
end &65
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 303,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 304,0
va (VaSet
)
xt "33000,55000,41300,56000"
st "ram_data_out : (15:0)"
blo "33000,55800"
tm "WireNameMgr"
)
)
on &22
)
*88 (Wire
uid 305,0
shape (OrthoPolyLine
uid 306,0
va (VaSet
vasetType 3
)
xt "32750,34000,36000,34000"
pts [
"32750,34000"
"36000,34000"
]
)
start &48
end &34
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 309,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 310,0
va (VaSet
isHidden 1
)
xt "39000,33000,42700,34000"
st "dac_array"
blo "39000,33800"
tm "WireNameMgr"
)
)
on &23
)
*89 (Wire
uid 311,0
shape (OrthoPolyLine
uid 312,0
va (VaSet
vasetType 3
)
xt "32750,28000,36000,28000"
pts [
"36000,28000"
"32750,28000"
]
)
start &33
end &45
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 315,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 316,0
va (VaSet
isHidden 1
)
xt "39000,27000,44200,28000"
st "config_rd_en"
blo "39000,27800"
tm "WireNameMgr"
)
)
on &24
)
*90 (Wire
uid 321,0
shape (OrthoPolyLine
uid 322,0
va (VaSet
vasetType 3
)
xt "32750,29000,36000,29000"
pts [
"32750,29000"
"36000,29000"
]
)
start &40
end &28
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 325,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 326,0
va (VaSet
isHidden 1
)
xt "39000,28000,44100,29000"
st "config_ready"
blo "39000,28800"
tm "WireNameMgr"
)
)
on &26
)
*91 (Wire
uid 1084,0
shape (OrthoPolyLine
uid 1085,0
va (VaSet
vasetType 3
)
xt "32750,31000,36000,31000"
pts [
"32750,31000"
"36000,31000"
]
)
start &54
end &70
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1088,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1089,0
va (VaSet
isHidden 1
)
xt "34000,30000,39600,31000"
st "config_started"
blo "34000,30800"
tm "WireNameMgr"
)
)
on &69
)
*92 (Wire
uid 1208,0
shape (OrthoPolyLine
uid 1209,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "32750,22000,36000,22000"
pts [
"32750,22000"
"36000,22000"
]
)
start &55
end &72
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1212,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1213,0
va (VaSet
isHidden 1
)
xt "34000,21000,39000,22000"
st "drs_address"
blo "34000,21800"
tm "WireNameMgr"
)
)
on &71
)
*93 (Wire
uid 1222,0
shape (OrthoPolyLine
uid 1223,0
va (VaSet
vasetType 3
)
xt "32750,21000,36000,21000"
pts [
"32750,21000"
"36000,21000"
]
)
start &56
end &74
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1226,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1227,0
va (VaSet
isHidden 1
)
xt "34000,20000,41200,21000"
st "drs_address_mode"
blo "34000,20800"
tm "WireNameMgr"
)
)
on &73
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *94 (PackageList
uid 41,0
stg "VerticalLayoutStrategy"
textVec [
*95 (Text
uid 42,0
va (VaSet
font "arial,8,1"
)
xt "1000,1000,6400,2000"
st "Package List"
blo "1000,1800"
)
*96 (MLText
uid 43,0
va (VaSet
)
xt "1000,2000,16300,7000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
LIBRARY FACT_FAD_LIB;
USE FACT_FAD_LIB.fad_definitions.ALL;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 44,0
stg "VerticalLayoutStrategy"
textVec [
*97 (Text
uid 45,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,28100,1000"
st "Compiler Directives"
blo "20000,800"
)
*98 (Text
uid 46,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,1000,29600,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*99 (MLText
uid 47,0
va (VaSet
isHidden 1
)
xt "20000,2000,27500,4000"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*100 (Text
uid 48,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,4000,30100,5000"
st "Post-module directives:"
blo "20000,4800"
)
*101 (MLText
uid 49,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*102 (Text
uid 50,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,5000,29900,6000"
st "End-module directives:"
blo "20000,5800"
)
*103 (MLText
uid 51,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "0,0,1281,1002"
viewArea "-6400,12000,60443,65739"
cachedDiagramExtent "700,0,59000,77000"
pageSetupInfo (PageSetupInfo
ptrCmd "Brother HL-5270DN series,winspool,"
fileName "IP_129.217.159.90"
toPrinter 1
landscape 0
xMargin 17
yMargin 17
paperWidth 761
paperHeight 1077
windowsPaperWidth 761
windowsPaperHeight 1077
paperType "A4"
windowsPaperName "A4"
windowsPaperType 9
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
showPageNumbers 1
boundaryLineStyle 0
boundaryWidth 0
exportStdIncludeRefs 1
exportStdPackageRefs 1
)
hasePageBreakOrigin 1
pageBreakOrigin "0,0"
lastUid 1237,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,2000,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 2
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Arial,8,1"
)
xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*104 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,3500,5800,4500"
st "<library>"
blo "2200,4300"
tm "BdLibraryNameMgr"
)
*105 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,4500,5600,5500"
st "<block>"
blo "2200,5300"
tm "BlkNameMgr"
)
*106 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,5500,3200,6500"
st "I0"
blo "2200,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "2200,13500,2200,13500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*107 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,3500,3450,4500"
st "Library"
blo "550,4300"
)
*108 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,4500,7450,5500"
st "MWComponent"
blo "550,5300"
)
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va (VaSet
font "Arial,8,1"
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xt "550,5500,1550,6500"
st "I0"
blo "550,6300"
tm "InstanceNameMgr"
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)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
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xt "-6450,1500,-6450,1500"
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header ""
)
elements [
]
)
portVis (PortSigDisplay
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prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
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)
defaultSaComponent (SaComponent
shape (Rectangle
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fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
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xt "0,0,8000,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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blo "900,4300"
tm "BdLibraryNameMgr"
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va (VaSet
font "Arial,8,1"
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st "SaComponent"
blo "900,5300"
tm "CptNameMgr"
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*112 (Text
va (VaSet
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xt "900,5500,1900,6500"
st "I0"
blo "900,6300"
tm "InstanceNameMgr"
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ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
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xt "-6100,1500,-6100,1500"
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header ""
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elements [
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viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
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xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
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viewiconposition 0
portVis (PortSigDisplay
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archFileType "UNKNOWN"
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defaultVhdlComponent (VhdlComponent
shape (Rectangle
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vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
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xt "0,0,8000,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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blo "500,5300"
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xt "500,5500,1500,6500"
st "I0"
blo "500,6300"
tm "InstanceNameMgr"
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ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
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xt "-6500,1500,-6500,1500"
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header ""
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elements [
]
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portVis (PortSigDisplay
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entityPath ""
archName ""
archPath ""
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shape (Rectangle
va (VaSet
vasetType 1
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lineColor "0,32896,0"
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xt "-450,0,8450,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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blo "50,5300"
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va (VaSet
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xt "50,5500,1050,6500"
st "I0"
blo "50,6300"
tm "InstanceNameMgr"
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ga (GenericAssociation
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matrix (Matrix
text (MLText
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header ""
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elements [
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entityPath ""
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shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
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xt "0,0,8000,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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blo "3150,4800"
tm "HdlTextNameMgr"
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va (VaSet
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xt "3150,5000,3950,6000"
st "1"
blo "3150,5800"
tm "HdlTextNumberMgr"
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viewicon (ZoomableIcon
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va (VaSet
vasetType 1
fg "49152,49152,49152"
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xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
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viewiconposition 0
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defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
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xt "0,0,18000,5000"
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text (MLText
va (VaSet
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xt "200,200,2000,1200"
st "
Text
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tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
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)
)
defaultGlobalConnector (GlobalConnector
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vasetType 1
fg "65535,65535,0"
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xt "-1000,-1000,1000,1000"
radius 1000
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name (Text
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xt "-500,-500,500,500"
st "G"
blo "-500,300"
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defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
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"1000,1000"
]
va (VaSet
vasetType 1
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xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
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xt "-400,-400,400,400"
radius 400
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defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
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optionalChildren [
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sl 0
ro 270
xt "-2000,-375,-500,375"
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(Line
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ro 270
xt "-500,0,0,0"
pts [
"-500,0"
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)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
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)
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defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
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"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
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"500,0"
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)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
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sl 0
xt "500,-375,2000,375"
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(Line
sl 0
xt "0,0,500,0"
pts [
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"500,0"
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)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
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ss 0
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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xt "0,0,1900,1000"
st "sig0"
blo "0,800"
tm "WireNameMgr"
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)
)
defaultBus (Wire
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va (VaSet
vasetType 3
lineWidth 2
)
pts [
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ss 0
es 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
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va (VaSet
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xt "0,0,2400,1000"
st "dbus0"
blo "0,800"
tm "WireNameMgr"
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)
)
defaultBundle (Bundle
shape (OrthoPolyLine
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lineColor "32768,0,0"
lineWidth 2
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pts [
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ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
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stg "VerticalLayoutStrategy"
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xt "0,0,3000,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
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second (MLText
va (VaSet
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st "()"
tm "BundleContentsMgr"
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shape (RectFrame
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vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
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xt "0,0,10000,12000"
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portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
)
second (MLText
va (VaSet
)
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 2
)
xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,12600,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
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vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
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num (Text
va (VaSet
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xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
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decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
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font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*122 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
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]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 2
)
xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,7400,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*124 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
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defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
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xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Courier New,8,0"
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)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Arial,8,1"
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xt "27000,200,32400,1200"
st "Declarations"
blo "27000,1000"
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portLabel (Text
uid 3,0
va (VaSet
font "Arial,8,1"
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xt "27000,1200,29700,2200"
st "Ports:"
blo "27000,2000"
)
preUserLabel (Text
uid 4,0
va (VaSet
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font "Arial,8,1"
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xt "27000,200,30800,1200"
st "Pre User:"
blo "27000,1000"
)
preUserText (MLText
uid 5,0
va (VaSet
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font "Courier New,8,0"
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xt "27000,200,27000,200"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
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xt "27000,13400,34100,14400"
st "Diagram Signals:"
blo "27000,14200"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Arial,8,1"
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xt "27000,200,31700,1200"
st "Post User:"
blo "27000,1000"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "27000,200,27000,200"
tm "BdDeclarativeTextMgr"
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)
commonDM (CommonDM
ldm (LogicalDM
suid 20,0
usingSuid 1
emptyRow *125 (LEmptyRow
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uid 54,0
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*127 (TitleRowHdr
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*128 (FilterRowHdr
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*129 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*130 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*131 (GroupColHdr
tm "GroupColHdrMgr"
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*132 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
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*133 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
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*134 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
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*135 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
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*136 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
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*137 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
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decl (Decl
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t "STD_LOGIC"
o 1
suid 1,0
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uid 427,0
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*139 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ram_wren"
t "std_logic_VECTOR"
b "(0 DOWNTO 0)"
o 15
suid 2,0
)
)
uid 429,0
)
*140 (LeafLogPort
port (LogicalPort
decl (Decl
n "config_addr"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 2
suid 3,0
)
)
uid 431,0
)
*141 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ram_data_in"
t "std_logic_VECTOR"
b "(15 DOWNTO 0)"
o 13
suid 4,0
)
)
uid 433,0
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*142 (LeafLogPort
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m 1
decl (Decl
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o 7
suid 5,0
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uid 435,0
)
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decl (Decl
n "config_busy"
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o 6
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)
)
uid 437,0
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decl (Decl
n "config_data"
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b "(15 DOWNTO 0)"
o 11
suid 7,0
)
)
uid 439,0
)
*145 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "roi_array"
t "roi_array_type"
o 10
suid 8,0
)
)
uid 441,0
)
*146 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ram_addr"
t "std_logic_VECTOR"
b "(7 DOWNTO 0)"
o 12
suid 10,0
)
)
uid 443,0
)
*147 (LeafLogPort
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decl (Decl
n "config_wr_en"
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o 5
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uid 445,0
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m 4
decl (Decl
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b "(15 DOWNTO 0)"
o 14
suid 12,0
)
)
uid 447,0
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decl (Decl
n "dac_array"
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suid 13,0
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uid 449,0
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decl (Decl
n "config_rd_en"
t "std_logic"
o 3
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)
)
uid 451,0
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decl (Decl
n "config_start"
t "std_logic"
o 4
suid 15,0
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)
uid 453,0
)
*152 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "config_ready"
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o 8
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uid 457,0
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m 1
decl (Decl
n "config_started"
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o 16
suid 18,0
i "'0'"
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uid 1096,0
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*154 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "drs_address"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 17
suid 19,0
)
)
uid 1234,0
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*155 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "drs_address_mode"
t "std_logic"
o 18
suid 20,0
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)
uid 1236,0
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]
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pdm (PhysicalDM
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editShortBounds 1
uid 67,0
optionalChildren [
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sheetRow (SheetRow
headerVa (MVa
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fontColor "0,0,0"
font "Tahoma,10,0"
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cellVa (MVa
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fontColor "0,0,0"
font "Tahoma,10,0"
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groupVa (MVa
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font "Tahoma,10,0"
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optionalChildren [
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hidden 1
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dimension 20
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dimension 20
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dimension 20
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dimension 20
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pos 3
dimension 20
uid 438,0
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dimension 20
uid 440,0
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dimension 20
uid 442,0
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litem &146
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dimension 20
uid 444,0
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dimension 20
uid 446,0
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dimension 20
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dimension 20
uid 452,0
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dimension 20
uid 454,0
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dimension 20
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dimension 20
uid 1097,0
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uid 1235,0
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