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fg "0,65535,0"
)
xt "36250,1625,37000,2375"
)
tg (CPTG
uid 50,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 51,0
va (VaSet
)
xt "38000,1500,39300,2500"
st "clk"
blo "38000,2300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 52,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,12000,25500,12800"
st "clk                   : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*133 (CptPort
uid 53,0
ps "OnEdgeStrategy"
shape (Triangle
uid 54,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,3625,67750,4375"
)
tg (CPTG
uid 55,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 56,0
va (VaSet
)
xt "59800,3500,66000,4500"
st "data_out : (63:0)"
ju 2
blo "66000,4300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 57,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,12800,35500,13600"
st "data_out              : OUT    std_logic_vector (63 downto 0) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "data_out"
t "std_logic_vector"
b "(63 downto 0)"
preAdd 0
posAdd 0
o 2
suid 2,0
)
)
)
*134 (CptPort
uid 58,0
ps "OnEdgeStrategy"
shape (Triangle
uid 59,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,2625,67750,3375"
)
tg (CPTG
uid 60,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 61,0
va (VaSet
)
xt "51900,2500,66000,3500"
st "addr_out : (RAM_ADDR_WIDTH-1:0)"
ju 2
blo "66000,3300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 62,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,13600,42500,14400"
st "addr_out              : OUT    std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "addr_out"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 downto 0)"
preAdd 0
posAdd 0
o 3
suid 3,0
)
)
)
*135 (CptPort
uid 73,0
ps "OnEdgeStrategy"
shape (Triangle
uid 74,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,1625,67750,2375"
)
tg (CPTG
uid 75,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 76,0
va (VaSet
)
xt "60200,1500,66000,2500"
st "write_ea : (0:0)"
ju 2
blo "66000,2300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 77,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,14400,38500,15200"
st "write_ea              : OUT    std_logic_vector (0 downto 0) := \"0\" ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "write_ea"
t "std_logic_vector"
b "(0 downto 0)"
preAdd 0
posAdd 0
o 4
suid 6,0
i "\"0\""
)
)
)
*136 (CptPort
uid 78,0
ps "OnEdgeStrategy"
shape (Triangle
uid 391,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,18625,67750,19375"
)
tg (CPTG
uid 80,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 81,0
va (VaSet
)
xt "49700,18500,66000,19500"
st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
ju 2
blo "66000,19300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 82,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,15200,42500,16000"
st "ram_start_addr        : IN     std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 downto 0)"
preAdd 0
posAdd 0
o 5
suid 7,0
)
)
)
*137 (CptPort
uid 88,0
ps "OnEdgeStrategy"
shape (Triangle
uid 89,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,10625,37000,11375"
)
tg (CPTG
uid 90,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 91,0
va (VaSet
)
xt "38000,10500,43900,11500"
st "board_id : (3:0)"
blo "38000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 92,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,29600,35000,30400"
st "board_id              : IN     std_logic_vector (3 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 23
suid 9,0
)
)
)
*138 (CptPort
uid 93,0
ps "OnEdgeStrategy"
shape (Triangle
uid 94,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,11625,37000,12375"
)
tg (CPTG
uid 95,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 96,0
va (VaSet
)
xt "38000,11500,44800,12500"
st "trigger_id : (47:0)"
blo "38000,12300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 97,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,31200,35500,32000"
st "trigger_id            : IN     std_logic_vector (47 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "trigger_id"
t "std_logic_vector"
b "(47 downto 0)"
preAdd 0
posAdd 0
o 25
suid 10,0
)
)
)
*139 (CptPort
uid 98,0
ps "OnEdgeStrategy"
shape (Triangle
uid 99,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,6625,37000,7375"
)
tg (CPTG
uid 100,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 101,0
va (VaSet
)
xt "38000,6500,40800,7500"
st "trigger"
blo "38000,7300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 102,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,32000,25500,32800"
st "trigger               : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 26
suid 11,0
)
)
)
*140 (CommentText
uid 106,0
ps "EdgeToEdgeStrategy"
shape (Rectangle
uid 107,0
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "37000,2000,52000,6400"
)
oxt "37000,2000,52000,6000"
text (MLText
uid 108,0
va (VaSet
fg "0,0,32768"
)
xt "37200,2200,51100,6200"
st "
-- -- Uncomment the following library declaration if instantiating
-- -- any Xilinx primitives in this code.
-- library UNISIM;
-- use UNISIM.VComponents.all;
"
tm "CommentText"
wrapOption 3
visibleHeight 4400
visibleWidth 15000
)
included 1
excludeCommentLeader 1
)
*141 (CptPort
uid 285,0
ps "OnEdgeStrategy"
shape (Triangle
uid 286,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,12625,37000,13375"
)
tg (CPTG
uid 287,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 288,0
va (VaSet
)
xt "38000,12500,43700,13500"
st "crate_id : (1:0)"
blo "38000,13300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 289,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,30400,35000,31200"
st "crate_id              : IN     std_logic_vector (1 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
o 24
suid 12,0
)
)
)
*142 (CptPort
uid 402,0
ps "OnEdgeStrategy"
shape (Triangle
uid 403,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,14625,37000,15375"
)
tg (CPTG
uid 404,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 405,0
va (VaSet
)
xt "38000,14500,43300,15500"
st "ram_write_ea"
blo "38000,15300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 406,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,16000,25500,16800"
st "ram_write_ea          : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "ram_write_ea"
t "std_logic"
o 6
suid 16,0
)
)
)
*143 (CptPort
uid 407,0
ps "OnEdgeStrategy"
shape (Triangle
uid 408,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,20625,67750,21375"
)
tg (CPTG
uid 409,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 410,0
va (VaSet
)
xt "59700,20500,66000,21500"
st "ram_write_ready"
ju 2
blo "66000,21300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 411,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,16800,38500,17600"
st "ram_write_ready       : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_write_ready"
t "std_logic"
o 7
suid 17,0
i "'0'"
)
)
)
*144 (CptPort
uid 412,0
ps "OnEdgeStrategy"
shape (Triangle
uid 413,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,15625,37000,16375"
)
tg (CPTG
uid 414,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 415,0
va (VaSet
)
xt "38000,15500,41000,16500"
st "roi_max"
blo "38000,16300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 416,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,25600,27000,26400"
st "roi_max               : IN     roi_max_type  ;
"
)
thePort (LogicalPort
decl (Decl
n "roi_max"
t "roi_max_type"
o 18
suid 18,0
)
)
)
*145 (CptPort
uid 473,0
ps "OnEdgeStrategy"
shape (Triangle
uid 474,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,16625,37000,17375"
)
tg (CPTG
uid 475,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 476,0
va (VaSet
)
xt "38000,16500,41400,17500"
st "roi_array"
blo "38000,17300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 477,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,24800,28000,25600"
st "roi_array             : IN     roi_array_type  ;
"
)
thePort (LogicalPort
decl (Decl
n "roi_array"
t "roi_array_type"
o 17
suid 19,0
)
)
)
*146 (CptPort
uid 526,0
ps "OnEdgeStrategy"
shape (Triangle
uid 527,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,17625,37000,18375"
)
tg (CPTG
uid 528,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 529,0
va (VaSet
)
xt "38000,17500,47100,18500"
st "package_length : (15:0)"
blo "38000,18300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 530,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,28800,35500,29600"
st "package_length        : IN     std_logic_vector (15 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "package_length"
t "std_logic_vector"
b "(15 downto 0)"
o 22
suid 20,0
)
)
)
*147 (CptPort
uid 637,0
ps "OnEdgeStrategy"
shape (Triangle
uid 638,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,21625,67750,22375"
)
tg (CPTG
uid 639,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 640,0
va (VaSet
)
xt "62800,21500,66000,22500"
st "adc_oeb"
ju 2
blo "66000,22300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 641,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,36000,38500,36800"
st "adc_oeb               : OUT    std_logic                     := '1' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_oeb"
t "std_logic"
o 31
suid 23,0
i "'1'"
)
)
)
*148 (CptPort
uid 676,0
ps "OnEdgeStrategy"
shape (Triangle
uid 677,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,22625,67750,23375"
)
tg (CPTG
uid 678,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 679,0
va (VaSet
)
xt "57500,22500,66000,23500"
st "drs_channel_id : (3:0)"
ju 2
blo "66000,23300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 680,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,38400,44500,39200"
st "drs_channel_id        : OUT    std_logic_vector (3 downto 0) := (others => '0') ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 34
suid 25,0
i "(others => '0')"
)
)
)
*149 (CptPort
uid 681,0
ps "OnEdgeStrategy"
shape (Triangle
uid 682,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,23625,67750,24375"
)
tg (CPTG
uid 683,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 684,0
va (VaSet
)
xt "61600,23500,66000,24500"
st "drs_clk_en"
ju 2
blo "66000,24300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 685,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,40000,38500,40800"
st "drs_clk_en            : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_clk_en"
t "std_logic"
o 36
suid 26,0
i "'0'"
)
)
)
*150 (CptPort
uid 801,0
ps "OnEdgeStrategy"
shape (Triangle
uid 802,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,24625,67750,25375"
)
tg (CPTG
uid 803,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 804,0
va (VaSet
)
xt "59800,24500,66000,25500"
st "drs_read_s_cell"
ju 2
blo "66000,25300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 805,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,40800,38500,41600"
st "drs_read_s_cell       : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_read_s_cell"
t "std_logic"
o 37
suid 33,0
i "'0'"
)
)
)
*151 (CptPort
uid 806,0
ps "OnEdgeStrategy"
shape (Triangle
uid 807,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,20625,37000,21375"
)
tg (CPTG
uid 808,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 809,0
va (VaSet
)
xt "38000,20500,46800,21500"
st "drs_read_s_cell_ready"
blo "38000,21300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 810,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,41600,25500,42400"
st "drs_read_s_cell_ready : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "drs_read_s_cell_ready"
t "std_logic"
o 38
suid 34,0
)
)
)
*152 (CptPort
uid 811,0
ps "OnEdgeStrategy"
shape (Triangle
uid 812,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,21625,37000,22375"
)
tg (CPTG
uid 813,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 814,0
va (VaSet
)
xt "38000,21500,44400,22500"
st "drs_s_cell_array"
blo "38000,22300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 815,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,42400,30500,43200"
st "drs_s_cell_array      : IN     drs_s_cell_array_type 
"
)
thePort (LogicalPort
decl (Decl
n "drs_s_cell_array"
t "drs_s_cell_array_type"
o 39
suid 35,0
)
)
)
*153 (CptPort
uid 845,0
ps "OnEdgeStrategy"
shape (Triangle
uid 846,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,25625,67750,26375"
)
tg (CPTG
uid 847,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 848,0
va (VaSet
)
xt "61700,25500,66000,26500"
st "drs_dwrite"
ju 2
blo "66000,26300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 849,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,39200,38500,40000"
st "drs_dwrite            : OUT    std_logic                     := '1' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_dwrite"
t "std_logic"
o 35
suid 36,0
i "'1'"
)
)
)
*154 (CptPort
uid 898,0
ps "OnEdgeStrategy"
shape (Triangle
uid 899,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,22625,37000,23375"
)
tg (CPTG
uid 900,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 901,0
va (VaSet
)
xt "38000,22500,43900,23500"
st "adc_data_array"
blo "38000,23300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 902,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,35200,30500,36000"
st "adc_data_array        : IN     adc_data_array_type  ;
"
)
thePort (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 30
suid 37,0
)
)
)
*155 (CptPort
uid 958,0
ps "OnEdgeStrategy"
shape (Triangle
uid 959,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,23625,37000,24375"
)
tg (CPTG
uid 960,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 961,0
va (VaSet
)
xt "38000,23500,44500,24500"
st "config_ready_cm"
blo "38000,24300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 962,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,20800,25500,21600"
st "config_ready_cm       : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "config_ready_cm"
t "std_logic"
o 12
suid 39,0
)
)
)
*156 (CptPort
uid 963,0
ps "OnEdgeStrategy"
shape (Triangle
uid 964,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,27625,67750,28375"
)
tg (CPTG
uid 965,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 966,0
va (VaSet
)
xt "59800,27500,66000,28500"
st "config_start_cm"
ju 2
blo "66000,28300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 967,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,18400,38500,19200"
st "config_start_cm       : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "config_start_cm"
t "std_logic"
o 9
suid 40,0
i "'0'"
)
)
)
*157 (CptPort
uid 1018,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1019,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,24625,37000,25375"
)
tg (CPTG
uid 1020,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1021,0
va (VaSet
)
xt "38000,24500,41600,25500"
st "s_trigger"
blo "38000,25300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1022,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,32800,25500,33600"
st "s_trigger             : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "s_trigger"
t "std_logic"
o 27
suid 41,0
)
)
)
*158 (CptPort
uid 1048,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1049,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,25625,37000,26375"
)
tg (CPTG
uid 1050,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1051,0
va (VaSet
)
xt "38000,25500,44700,26500"
st "config_ready_mm"
blo "38000,26300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1052,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,20000,25500,20800"
st "config_ready_mm       : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "config_ready_mm"
t "std_logic"
o 11
suid 42,0
)
)
)
*159 (CptPort
uid 1053,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1054,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,26625,37000,27375"
)
tg (CPTG
uid 1055,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1056,0
va (VaSet
)
xt "38000,26500,44500,27500"
st "config_ready_spi"
blo "38000,27300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1057,0
va (VaSet
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)
xt "2000,21600,25500,22400"
st "config_ready_spi      : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "config_ready_spi"
t "std_logic"
o 13
suid 43,0
)
)
)
*160 (CptPort
uid 1085,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1086,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,27625,37000,28375"
)
tg (CPTG
uid 1087,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1088,0
va (VaSet
)
xt "38000,27500,43200,28500"
st "sensor_array"
blo "38000,28300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1089,0
va (VaSet
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)
xt "2000,26400,29500,27200"
st "sensor_array          : IN     sensor_array_type  ;
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)
thePort (LogicalPort
decl (Decl
n "sensor_array"
t "sensor_array_type"
o 19
suid 44,0
)
)
)
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uid 1090,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1091,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,28625,37000,29375"
)
tg (CPTG
uid 1092,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1093,0
va (VaSet
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xt "38000,28500,43300,29500"
st "sensor_ready"
blo "38000,29300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1094,0
va (VaSet
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)
xt "2000,27200,25500,28000"
st "sensor_ready          : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "sensor_ready"
t "std_logic"
o 20
suid 45,0
)
)
)
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uid 1122,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1123,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,28625,67750,29375"
)
tg (CPTG
uid 1124,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1125,0
va (VaSet
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xt "59600,28500,66000,29500"
st "config_start_mm"
ju 2
blo "66000,29300"
tm "CptPortNameMgr"
)
)
dt (MLText
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va (VaSet
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xt "2000,17600,38500,18400"
st "config_start_mm       : OUT    std_logic                     := '0' ;
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)
thePort (LogicalPort
m 1
decl (Decl
n "config_start_mm"
t "std_logic"
o 8
suid 46,0
i "'0'"
)
)
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ps "OnEdgeStrategy"
shape (Triangle
uid 1128,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "67000,29625,67750,30375"
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tg (CPTG
uid 1129,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "59800,29500,66000,30500"
st "config_start_spi"
ju 2
blo "66000,30300"
tm "CptPortNameMgr"
)
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xt "2000,19200,38500,20000"
st "config_start_spi      : OUT    std_logic                     := '0' ;
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)
thePort (LogicalPort
m 1
decl (Decl
n "config_start_spi"
t "std_logic"
o 10
suid 47,0
i "'0'"
)
)
)
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uid 1159,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1160,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "67000,30625,67750,31375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1162,0
va (VaSet
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xt "60400,30500,66000,31500"
st "config_started"
ju 2
blo "66000,31300"
tm "CptPortNameMgr"
)
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va (VaSet
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xt "2000,34400,38500,35200"
st "config_started        : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "config_started"
t "std_logic"
o 29
suid 48,0
i "'0'"
)
)
)
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uid 1164,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1165,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,29625,37000,30375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1167,0
va (VaSet
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xt "38000,29500,42600,30500"
st "new_config"
blo "38000,30300"
tm "CptPortNameMgr"
)
)
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va (VaSet
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xt "2000,33600,25500,34400"
st "new_config            : IN     std_logic  ;
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thePort (LogicalPort
decl (Decl
n "new_config"
t "std_logic"
o 28
suid 49,0
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)
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uid 1196,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1197,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,30625,37000,31375"
)
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1199,0
va (VaSet
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xt "38000,30500,45000,31500"
st "config_started_cm"
blo "38000,31300"
tm "CptPortNameMgr"
)
)
dt (MLText
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va (VaSet
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xt "2000,23200,25500,24000"
st "config_started_cm     : IN     std_logic  ;
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)
thePort (LogicalPort
decl (Decl
n "config_started_cm"
t "std_logic"
o 15
suid 50,0
)
)
)
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uid 1201,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1202,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,31625,37000,32375"
)
tg (CPTG
uid 1203,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "38000,31500,45200,32500"
st "config_started_mm"
blo "38000,32300"
tm "CptPortNameMgr"
)
)
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va (VaSet
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xt "2000,22400,25500,23200"
st "config_started_mm     : IN     std_logic  ;
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)
thePort (LogicalPort
decl (Decl
n "config_started_mm"
t "std_logic"
o 14
suid 51,0
)
)
)
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ps "OnEdgeStrategy"
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uid 1207,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "36250,32625,37000,33375"
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tg (CPTG
uid 1208,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "38000,32500,45000,33500"
st "config_started_spi"
blo "38000,33300"
tm "CptPortNameMgr"
)
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xt "2000,24000,25500,24800"
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)
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decl (Decl
n "config_started_spi"
t "std_logic"
o 16
suid 52,0
)
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ps "OnEdgeStrategy"
shape (Triangle
uid 1241,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "36250,33625,37000,34375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
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blo "38000,34300"
tm "CptPortNameMgr"
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va (VaSet
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xt "2000,28000,28000,28800"
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)
thePort (LogicalPort
decl (Decl
n "dac_array"
t "dac_array_type"
o 21
suid 53,0
)
)
)
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uid 1395,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1396,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,31625,67750,32375"
)
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "61500,31500,66000,32500"
st "adc_clk_en"
ju 2
blo "66000,32300"
tm "CptPortNameMgr"
)
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xt "2000,36800,38500,37600"
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)
thePort (LogicalPort
m 1
decl (Decl
n "adc_clk_en"
t "std_logic"
o 32
suid 54,0
i "'0'"
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uid 1427,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1428,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "36250,34625,37000,35375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
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xt "38000,34500,43500,35500"
st "adc_otr : (3:0)"
blo "38000,35300"
tm "CptPortNameMgr"
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xt "2000,37600,35000,38400"
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)
thePort (LogicalPort
decl (Decl
n "adc_otr"
t "std_logic_vector"
b "(3 downto 0)"
o 33
suid 55,0
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xt "37000,1000,67000,36000"
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xt "41200,29000,50900,30000"
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Created using Mentor Graphics HDL2Graphics(TM) Technology
on - 16:03:02 10.02.2010
from - D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hdl\\data_generator.vhd

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use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library fact_fad_lib;
use fact_fad_lib.fad_definitions.all;"
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