INCLUDE list {
 DEFAULT atom 1
}
DIALECT atom VHDL_2002
ARCHITECTURES list {
 {adc_buffer beha} list {
  TASK_SETTINGS list {
   PLUGIN_SETTINGS list {
    XilinxCoregen atom {TaskSetting appPath {$XILINX} TaskSetting lang VHDL TaskSetting libraryMode 0 TaskSetting family spartan3a TaskSetting synthesisTool MentorHDL TaskSetting busFormat B(n:m) TaskSetting createInLib FACT_FAD_lib TaskSetting replace 1 TaskSetting ignoreError 0 TaskSetting setDontTouch 0 TaskSetting additionalOpts {} TaskSetting vhdlConvention %(entity_name)_%(arch_name).vhd TaskSetting verConvention %(unit)_%(view).vhd}
   }
  }
 }
}
