DocumentHdrVersion "1.1"
Header (DocumentHdr
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(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "std_logic_arith"
)
(DmPackageRef
library "FACT_FAD_lib"
unitName "fad_definitions"
)
]
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(vvPair
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value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hdl"
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(vvPair
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(vvPair
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(vvPair
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(vvPair
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(vvPair
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(vvPair
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(vvPair
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(vvPair
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(vvPair
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(vvPair
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(vvPair
variable "f"
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(vvPair
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(vvPair
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(vvPair
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(vvPair
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(vvPair
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value "VHDL"
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(vvPair
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value "FACT_FAD_lib"
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(vvPair
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value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
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(vvPair
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(vvPair
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value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
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(vvPair
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value "$HDS_PROJECT_DIR/FACT_FAD_lib/work"
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(vvPair
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value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps"
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(vvPair
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value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
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(vvPair
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value "08"
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)
(vvPair
variable "month"
value "Aug"
)
(vvPair
variable "month_long"
value "August"
)
(vvPair
variable "p"
value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main\\symbol.sb"
)
(vvPair
variable "p_logical"
value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_main\\symbol.sb"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "<TBD>"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "sb"
)
(vvPair
variable "this_file"
value "symbol"
)
(vvPair
variable "this_file_logical"
value "symbol"
)
(vvPair
variable "time"
value "10:49:09"
)
(vvPair
variable "unit"
value "FAD_main"
)
(vvPair
variable "user"
value "dneise"
)
(vvPair
variable "version"
value "2009.2 (Build 10)"
)
(vvPair
variable "view"
value "symbol"
)
(vvPair
variable "year"
value "2010"
)
(vvPair
variable "yy"
value "10"
)
]
)
LanguageMgr "VhdlLangMgr"
uid 51,0
optionalChildren [
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uid 8,0
optionalChildren [
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uid 135,0
ps "OnEdgeStrategy"
shape (Triangle
uid 136,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,-3375,43750,-2625"
)
tg (CPTG
uid 137,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 138,0
va (VaSet
)
xt "38400,-3500,42000,-2500"
st "wiz_reset"
ju 2
blo "42000,-2700"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 140,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,36400,77500,37200"
st "wiz_reset       : OUT    std_logic                     := '1' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_reset"
t "std_logic"
o 43
suid 2,0
i "'1'"
)
)
)
*147 (CptPort
uid 163,0
ps "OnEdgeStrategy"
shape (Triangle
uid 164,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,42625,43750,43375"
)
tg (CPTG
uid 165,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 166,0
va (VaSet
)
xt "38000,42500,42000,43500"
st "led : (7:0)"
ju 2
blo "42000,43300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 168,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,27600,83500,28400"
st "led             : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 33
suid 7,0
i "(OTHERS => '0')"
)
)
)
*148 (CptPort
uid 464,0
ps "OnEdgeStrategy"
shape (Triangle
uid 465,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,4625,15000,5375"
)
tg (CPTG
uid 466,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 467,0
va (VaSet
)
xt "16000,4500,18800,5500"
st "trigger"
blo "16000,5300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 468,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,9200,64000,10000"
st "trigger         : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 10
suid 18,0
)
)
)
*149 (CptPort
uid 833,0
ps "OnEdgeStrategy"
shape (Triangle
uid 834,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,15625,15000,16375"
)
tg (CPTG
uid 835,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 836,0
va (VaSet
)
xt "16000,15500,19200,16500"
st "adc_oeb"
blo "16000,16300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 837,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,23600,77500,24400"
st "adc_oeb         : OUT    std_logic                     := '1' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_oeb"
t "std_logic"
o 28
suid 21,0
i "'1'"
)
)
)
*150 (CptPort
uid 923,0
ps "OnEdgeStrategy"
shape (Triangle
uid 924,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,6625,15000,7375"
)
tg (CPTG
uid 925,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 926,0
va (VaSet
)
xt "16000,6500,21900,7500"
st "board_id : (3:0)"
blo "16000,7300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 927,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,7600,74000,8400"
st "board_id        : IN     std_logic_vector (3 downto 0) ;"
)
thePort (LogicalPort
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 8
suid 24,0
)
)
)
*151 (CptPort
uid 928,0
ps "OnEdgeStrategy"
shape (Triangle
uid 929,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,7625,15000,8375"
)
tg (CPTG
uid 930,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 931,0
va (VaSet
)
xt "16000,7500,21700,8500"
st "crate_id : (1:0)"
blo "16000,8300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 932,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,8400,74000,9200"
st "crate_id        : IN     std_logic_vector (1 downto 0) ;"
)
thePort (LogicalPort
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
o 9
suid 25,0
)
)
)
*152 (CptPort
uid 1037,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1038,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,-6375,43750,-5625"
)
tg (CPTG
uid 1039,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1040,0
va (VaSet
)
xt "36000,-6500,42000,-5500"
st "wiz_addr : (9:0)"
ju 2
blo "42000,-5700"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1041,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,34000,74000,34800"
st "wiz_addr        : OUT    std_logic_vector (9 DOWNTO 0) ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 40
suid 26,0
)
)
)
*153 (CptPort
uid 1042,0
ps "OnEdgeStrategy"
shape (Diamond
uid 1043,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,-5375,43750,-4625"
)
tg (CPTG
uid 1044,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1045,0
va (VaSet
)
xt "35700,-5500,42000,-4500"
st "wiz_data : (15:0)"
ju 2
blo "42000,-4700"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1046,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,38800,73500,39600"
st "wiz_data        : INOUT  std_logic_vector (15 DOWNTO 0)"
)
thePort (LogicalPort
m 2
decl (Decl
n "wiz_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 46
suid 27,0
)
)
)
*154 (CptPort
uid 1047,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1048,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,625,43750,1375"
)
tg (CPTG
uid 1049,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1050,0
va (VaSet
)
xt "39300,500,42000,1500"
st "wiz_cs"
ju 2
blo "42000,1300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1051,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,34800,77500,35600"
st "wiz_cs          : OUT    std_logic                     := '1' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_cs"
t "std_logic"
o 41
suid 28,0
i "'1'"
)
)
)
*155 (CptPort
uid 1052,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1053,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,-1375,43750,-625"
)
tg (CPTG
uid 1054,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1055,0
va (VaSet
)
xt "39300,-1500,42000,-500"
st "wiz_wr"
ju 2
blo "42000,-700"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1056,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,37200,77500,38000"
st "wiz_wr          : OUT    std_logic                     := '1' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_wr"
t "std_logic"
o 44
suid 29,0
i "'1'"
)
)
)
*156 (CptPort
uid 1057,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1058,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,-2375,43750,-1625"
)
tg (CPTG
uid 1059,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1060,0
va (VaSet
)
xt "39400,-2500,42000,-1500"
st "wiz_rd"
ju 2
blo "42000,-1700"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1061,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,35600,77500,36400"
st "wiz_rd          : OUT    std_logic                     := '1' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_rd"
t "std_logic"
o 42
suid 30,0
i "'1'"
)
)
)
*157 (CptPort
uid 1062,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1063,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,-375,43750,375"
)
tg (CPTG
uid 1064,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1065,0
va (VaSet
)
xt "39300,-500,42000,500"
st "wiz_int"
ju 2
blo "42000,300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1066,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10000,64000,10800"
st "wiz_int         : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "wiz_int"
t "std_logic"
o 11
suid 31,0
)
)
)
*158 (CptPort
uid 1389,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1390,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,-4375,15000,-3625"
)
tg (CPTG
uid 1391,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1392,0
va (VaSet
)
xt "16000,-4500,20500,-3500"
st "CLK_25_PS"
blo "16000,-3700"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1393,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,13200,64000,14000"
st "CLK_25_PS       : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 15
suid 35,0
)
)
)
*159 (CptPort
uid 1725,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1726,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,-5375,15000,-4625"
)
tg (CPTG
uid 1727,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1728,0
va (VaSet
)
xt "16000,-5500,19100,-4500"
st "CLK_50"
blo "16000,-4700"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1729,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,14000,64000,14800"
st "CLK_50          : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_50"
t "std_logic"
o 16
suid 37,0
)
)
)
*160 (CptPort
uid 1755,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1756,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,-6375,15000,-5625"
)
tg (CPTG
uid 1757,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1758,0
va (VaSet
)
xt "16000,-6500,17900,-5500"
st "CLK"
blo "16000,-5700"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1759,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2000,64000,2800"
st "CLK             : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 38,0
)
)
)
*161 (CptPort
uid 1976,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1977,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,14625,15000,15375"
)
tg (CPTG
uid 1978,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1979,0
va (VaSet
)
xt "16000,14500,24000,15500"
st "adc_otr_array : (3:0)"
blo "16000,15300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1980,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6800,74000,7600"
st "adc_otr_array   : IN     std_logic_vector (3 DOWNTO 0) ;"
)
thePort (LogicalPort
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 7
suid 40,0
)
)
)
*162 (CptPort
uid 2282,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2283,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,20625,15000,21375"
)
tg (CPTG
uid 2284,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2285,0
va (VaSet
)
xt "16000,20500,21900,21500"
st "adc_data_array"
blo "16000,21300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2286,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6000,69500,6800"
st "adc_data_array  : IN     adc_data_array_type  ;"
)
thePort (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 6
suid 41,0
)
)
)
*163 (CptPort
uid 2448,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2449,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,34625,15000,35375"
)
tg (CPTG
uid 2450,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2451,0
va (VaSet
)
xt "16000,34500,24500,35500"
st "drs_channel_id : (3:0)"
blo "16000,35300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2452,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,26000,83500,26800"
st "drs_channel_id  : OUT    std_logic_vector (3 downto 0) := (others => '0') ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 31
suid 48,0
i "(others => '0')"
)
)
)
*164 (CptPort
uid 2453,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2454,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,35625,15000,36375"
)
tg (CPTG
uid 2455,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2456,0
va (VaSet
)
xt "16000,35500,20300,36500"
st "drs_dwrite"
blo "16000,36300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2457,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,26800,77500,27600"
st "drs_dwrite      : OUT    std_logic                     := '1' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_dwrite"
t "std_logic"
o 32
suid 49,0
i "'1'"
)
)
)
*165 (CptPort
uid 2710,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2711,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,30625,15000,31375"
)
tg (CPTG
uid 2712,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2713,0
va (VaSet
)
xt "16000,30500,21400,31500"
st "SROUT_in_0"
blo "16000,31300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2714,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2800,64000,3600"
st "SROUT_in_0      : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 2
suid 52,0
)
)
)
*166 (CptPort
uid 2715,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2716,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,31625,15000,32375"
)
tg (CPTG
uid 2717,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2718,0
va (VaSet
)
xt "16000,31500,21400,32500"
st "SROUT_in_1"
blo "16000,32300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2719,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,3600,64000,4400"
st "SROUT_in_1      : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 3
suid 53,0
)
)
)
*167 (CptPort
uid 2720,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2721,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,32625,15000,33375"
)
tg (CPTG
uid 2722,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2723,0
va (VaSet
)
xt "16000,32500,21400,33500"
st "SROUT_in_2"
blo "16000,33300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2724,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4400,64000,5200"
st "SROUT_in_2      : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 4
suid 54,0
)
)
)
*168 (CptPort
uid 2725,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2726,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,33625,15000,34375"
)
tg (CPTG
uid 2727,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2728,0
va (VaSet
)
xt "16000,33500,21400,34500"
st "SROUT_in_3"
blo "16000,34300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2729,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,5200,64000,6000"
st "SROUT_in_3      : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 5
suid 55,0
)
)
)
*169 (CptPort
uid 2987,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2988,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,36625,15000,37375"
)
tg (CPTG
uid 2989,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2990,0
va (VaSet
)
xt "16000,36500,20200,37500"
st "RSRLOAD"
blo "16000,37300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2991,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,21200,77500,22000"
st "RSRLOAD         : OUT    std_logic                     := '0' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "RSRLOAD"
t "std_logic"
o 25
suid 56,0
i "'0'"
)
)
)
*170 (CptPort
uid 2992,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2993,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,38625,15000,39375"
)
tg (CPTG
uid 2994,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2995,0
va (VaSet
)
xt "16000,38500,19000,39500"
st "SRCLK"
blo "16000,39300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2996,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,22000,77500,22800"
st "SRCLK           : OUT    std_logic                     := '0' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "SRCLK"
t "std_logic"
o 26
suid 57,0
i "'0'"
)
)
)
*171 (CptPort
uid 3631,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3632,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,23625,43750,24375"
)
tg (CPTG
uid 3633,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3634,0
va (VaSet
)
xt "40300,23500,42000,24500"
st "sclk"
ju 2
blo "42000,24300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 3635,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,30800,64000,31600"
st "sclk            : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "sclk"
t "std_logic"
o 37
suid 62,0
)
)
)
*172 (CptPort
uid 3636,0
ps "OnEdgeStrategy"
shape (Diamond
uid 3637,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,24625,43750,25375"
)
tg (CPTG
uid 3638,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3639,0
va (VaSet
)
xt "40600,24500,42000,25500"
st "sio"
ju 2
blo "42000,25300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 3640,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,38000,64000,38800"
st "sio             : INOUT  std_logic  ;"
)
thePort (LogicalPort
m 2
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 45
suid 63,0
)
)
)
*173 (CptPort
uid 3641,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3642,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,12625,43750,13375"
)
tg (CPTG
uid 3643,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3644,0
va (VaSet
)
xt "39200,12500,42000,13500"
st "dac_cs"
ju 2
blo "42000,13300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 3645,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,24400,64000,25200"
st "dac_cs          : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "dac_cs"
t "std_logic"
o 29
suid 64,0
)
)
)
*174 (CptPort
uid 3646,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3647,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,14625,43750,15375"
)
tg (CPTG
uid 3648,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3649,0
va (VaSet
)
xt "35500,14500,42000,15500"
st "sensor_cs : (3:0)"
ju 2
blo "42000,15300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 3650,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,31600,74000,32400"
st "sensor_cs       : OUT    std_logic_vector (3 DOWNTO 0) ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 38
suid 65,0
)
)
)
*175 (CptPort
uid 4067,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4068,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,25625,43750,26375"
)
tg (CPTG
uid 4069,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4070,0
va (VaSet
)
xt "40000,25500,42000,26500"
st "mosi"
ju 2
blo "42000,26300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4071,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,28400,77500,29200"
st "mosi            : OUT    std_logic                     := '0' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "mosi"
t "std_logic"
o 34
suid 66,0
i "'0'"
)
)
)
*176 (CptPort
uid 4144,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4145,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,43625,43750,44375"
)
tg (CPTG
uid 4146,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4147,0
va (VaSet
)
xt "39000,43500,42000,44500"
st "denable"
ju 2
blo "42000,44300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4148,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,25200,91000,26000"
st "denable         : OUT    std_logic                     := '0' ; -- default domino wave off"
)
thePort (LogicalPort
m 1
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 30
suid 67,0
i "'0'"
)
)
)
*177 (CptPort
uid 4323,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4324,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,44625,43750,45375"
)
tg (CPTG
uid 4325,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4326,0
va (VaSet
)
xt "37500,44500,42000,45500"
st "adc_clk_en"
ju 2
blo "42000,45300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4327,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,22800,77500,23600"
st "adc_clk_en      : OUT    std_logic                     := '0' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_clk_en"
t "std_logic"
o 27
suid 69,0
i "'0'"
)
)
)
*178 (CptPort
uid 4467,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4468,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,45625,43750,46375"
)
tg (CPTG
uid 4469,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4470,0
va (VaSet
)
xt "34300,45500,42000,46500"
st "LOCKED_extraOUT"
ju 2
blo "42000,46300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4471,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,15600,64000,16400"
st "LOCKED_extraOUT : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "LOCKED_extraOUT"
t "std_logic"
o 18
suid 70,0
)
)
)
*179 (CptPort
uid 4472,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4473,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,46625,43750,47375"
)
tg (CPTG
uid 4474,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4475,0
va (VaSet
)
xt "34200,46500,42000,47500"
st "PSDONE_extraOUT"
ju 2
blo "42000,47300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4476,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,17200,64000,18000"
st "PSDONE_extraOUT : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "PSDONE_extraOUT"
t "std_logic"
o 20
suid 71,0
)
)
)
*180 (CptPort
uid 4477,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4478,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,47625,43750,48375"
)
tg (CPTG
uid 4479,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4480,0
va (VaSet
)
xt "35000,47500,42000,48500"
st "PSINCDEC_OUT"
ju 2
blo "42000,48300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4481,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,18800,64000,19600"
st "PSINCDEC_OUT    : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "PSINCDEC_OUT"
t "std_logic"
o 22
suid 72,0
)
)
)
*181 (CptPort
uid 4482,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4483,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,48625,43750,49375"
)
tg (CPTG
uid 4484,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4485,0
va (VaSet
)
xt "37400,48500,42000,49500"
st "PSEN_OUT"
ju 2
blo "42000,49300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4486,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,18000,64000,18800"
st "PSEN_OUT        : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "PSEN_OUT"
t "std_logic"
o 21
suid 73,0
)
)
)
*182 (CptPort
uid 4487,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4488,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,49625,43750,50375"
)
tg (CPTG
uid 4489,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4490,0
va (VaSet
)
xt "37000,49500,42000,50500"
st "PSCLK_OUT"
ju 2
blo "42000,50300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4491,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,16400,64000,17200"
st "PSCLK_OUT       : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "PSCLK_OUT"
t "std_logic"
o 19
suid 74,0
)
)
)
*183 (CptPort
uid 4497,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4498,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,51625,43750,52375"
)
tg (CPTG
uid 4499,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4500,0
va (VaSet
)
xt "36800,51500,42000,52500"
st "DCM_locked"
ju 2
blo "42000,52300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4501,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,14800,64000,15600"
st "DCM_locked      : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "DCM_locked"
t "std_logic"
preAdd 0
posAdd 0
o 17
suid 76,0
)
)
)
*184 (CptPort
uid 4502,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4503,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,52625,43750,53375"
)
tg (CPTG
uid 4504,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4505,0
va (VaSet
)
xt "37200,52500,42000,53500"
st "offset : (7:0)"
ju 2
blo "42000,53300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4506,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,29200,83500,30000"
st "offset          : OUT    std_logic_vector (7 downto 0) := (OTHERS => '0') ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "offset"
t "std_logic_vector"
b "(7 downto 0)"
preAdd 0
posAdd 0
o 35
suid 77,0
i "(OTHERS => '0')"
)
)
)
*185 (CptPort
uid 4507,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4508,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,53625,43750,54375"
)
tg (CPTG
uid 4509,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4510,0
va (VaSet
)
xt "39100,53500,42000,54500"
st "shifting"
ju 2
blo "42000,54300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4511,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,32400,77500,34000"
st "-- status:
shifting        : OUT    std_logic                     := '0' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "shifting"
t "std_logic"
prec "-- status:"
preAdd 0
posAdd 0
o 39
suid 78,0
i "'0'"
)
)
)
*186 (CptPort
uid 4512,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4513,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,54625,43750,55375"
)
tg (CPTG
uid 4514,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4515,0
va (VaSet
)
xt "39800,54500,42000,55500"
st "ready"
ju 2
blo "42000,55300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4516,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,30000,77500,30800"
st "ready           : OUT    std_logic                     := '0' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "ready"
t "std_logic"
preAdd 0
posAdd 0
o 36
suid 79,0
i "'0'"
)
)
)
*187 (CptPort
uid 4517,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4518,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,55625,43750,56375"
)
tg (CPTG
uid 4519,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4520,0
va (VaSet
)
xt "37600,55500,42000,56500"
st "PS_DIR_IN"
ju 2
blo "42000,56300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4521,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,19600,64000,20400"
st "PS_DIR_IN       : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "PS_DIR_IN"
t "std_logic"
o 23
suid 80,0
)
)
)
*188 (CptPort
uid 4522,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4523,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,56625,43750,57375"
)
tg (CPTG
uid 4524,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4525,0
va (VaSet
)
xt "37800,56500,42000,57500"
st "PS_DO_IN"
ju 2
blo "42000,57300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4526,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,20400,64000,21200"
st "PS_DO_IN        : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "PS_DO_IN"
t "std_logic"
o 24
suid 81,0
)
)
)
*189 (CptPort
uid 4579,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4580,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,57625,43750,58375"
)
tg (CPTG
uid 4581,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4582,0
va (VaSet
)
xt "37200,57500,42000,58500"
st "CLK50_OUT"
ju 2
blo "42000,58300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4583,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,12400,64000,13200"
st "CLK50_OUT       : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK50_OUT"
t "std_logic"
o 14
suid 82,0
)
)
)
*190 (CptPort
uid 4584,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4585,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,58625,43750,59375"
)
tg (CPTG
uid 4586,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4587,0
va (VaSet
)
xt "37200,58500,42000,59500"
st "CLK25_OUT"
ju 2
blo "42000,59300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4588,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10800,64000,11600"
st "CLK25_OUT       : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK25_OUT"
t "std_logic"
o 12
suid 83,0
)
)
)
*191 (CptPort
uid 4589,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4590,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,59625,43750,60375"
)
tg (CPTG
uid 4591,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4592,0
va (VaSet
)
xt "35800,59500,42000,60500"
st "CLK25_PSOUT"
ju 2
blo "42000,60300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4593,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,11600,64000,12400"
st "CLK25_PSOUT     : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK25_PSOUT"
t "std_logic"
o 13
suid 84,0
)
)
)
]
shape (Rectangle
uid 4141,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,-8000,43000,61000"
)
oxt "15000,-8000,43000,45000"
biTextGroup (BiTextGroup
uid 10,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
uid 11,0
va (VaSet
font "Arial,8,1"
)
xt "15200,45000,21400,46000"
st "FACT_FAD_lib"
blo "15200,45800"
)
second (Text
uid 12,0
va (VaSet
font "Arial,8,1"
)
xt "15200,46000,19400,47000"
st "FAD_main"
blo "15200,46800"
)
)
gi *192 (GenericInterface
uid 13,0
ps "CenterOffsetStrategy"
matrix (Matrix
uid 14,0
text (MLText
uid 15,0
va (VaSet
font "Courier New,8,0"
)
xt "0,12000,15500,14400"
st "Generic Declarations

RAMADDRWIDTH64b integer 12  "
)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
elements [
(GiElement
name "RAMADDRWIDTH64b"
type "integer"
value "12"
)
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
)
portVis (PortSigDisplay
)
)
*193 (Grouping
uid 16,0
optionalChildren [
*194 (CommentText
uid 18,0
shape (Rectangle
uid 19,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
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