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library "ieee"
unitName "std_logic_1164"
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(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_ARITH"
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(DmPackageRef
library "ieee"
unitName "STD_LOGIC_UNSIGNED"
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(DmPackageRef
library "fact_fad_lib"
unitName "fad_definitions"
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library "UNISIM"
unitName "VComponents"
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(DmPackageRef
library "IEEE"
unitName "NUMERIC_STD"
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(DmPackageRef
library "IEEE"
unitName "std_logic_signed"
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libraryRefs [
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version "29.1"
appVersion "2009.2 (Build 10)"
noEmbeddedEditors 1
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(vvPair
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variable "module_name"
value "FAD_main"
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(vvPair
variable "month"
value "Aug"
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(vvPair
variable "month_long"
value "August"
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(vvPair
variable "p"
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variable "task_DesignCompilerPath"
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variable "task_ModelSimPath"
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variable "task_NC-SimPath"
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(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
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(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
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(vvPair
variable "task_VCSPath"
value "<TBD>"
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variable "this_ext"
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(vvPair
variable "this_file"
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variable "this_file_logical"
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variable "unit"
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tg (CPTG
uid 1362,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1363,0
va (VaSet
)
xt "24900,48500,39000,49500"
st "addr_out : (RAM_ADDR_WIDTH-1:0)"
ju 2
blo "39000,49300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "addr_out"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 downto 0)"
preAdd 0
posAdd 0
o 3
suid 3,0
)
)
)
*26 (CptPort
uid 1372,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1373,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,47625,40750,48375"
)
tg (CPTG
uid 1374,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1375,0
va (VaSet
)
xt "33200,47500,39000,48500"
st "write_ea : (0:0)"
ju 2
blo "39000,48300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "write_ea"
t "std_logic_vector"
b "(0 downto 0)"
preAdd 0
posAdd 0
o 4
suid 6,0
i "\"0\""
)
)
)
*27 (CptPort
uid 1376,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2344,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,62625,40750,63375"
)
tg (CPTG
uid 1378,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1379,0
va (VaSet
)
xt "22700,62500,39000,63500"
st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
ju 2
blo "39000,63300"
)
)
thePort (LogicalPort
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 downto 0)"
preAdd 0
posAdd 0
o 5
suid 7,0
)
)
)
*28 (CptPort
uid 1384,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1385,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,85625,19000,86375"
)
tg (CPTG
uid 1386,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1387,0
va (VaSet
)
xt "20000,85500,25900,86500"
st "board_id : (3:0)"
blo "20000,86300"
)
)
thePort (LogicalPort
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 23
suid 9,0
)
)
)
*29 (CptPort
uid 1388,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1389,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,67625,19000,68375"
)
tg (CPTG
uid 1390,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1391,0
va (VaSet
)
xt "20000,67500,26800,68500"
st "trigger_id : (47:0)"
blo "20000,68300"
)
)
thePort (LogicalPort
decl (Decl
n "trigger_id"
t "std_logic_vector"
b "(47 downto 0)"
preAdd 0
posAdd 0
o 25
suid 10,0
)
)
)
*30 (CptPort
uid 1392,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1393,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,68625,19000,69375"
)
tg (CPTG
uid 1394,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1395,0
va (VaSet
)
xt "20000,68500,22800,69500"
st "trigger"
blo "20000,69300"
)
)
thePort (LogicalPort
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 26
suid 11,0
)
)
)
*31 (CptPort
uid 1676,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1677,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,86625,19000,87375"
)
tg (CPTG
uid 1678,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1679,0
va (VaSet
)
xt "20000,86500,25700,87500"
st "crate_id : (1:0)"
blo "20000,87300"
)
)
thePort (LogicalPort
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
o 24
suid 12,0
)
)
)
*32 (CptPort
uid 2562,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2563,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,63625,40750,64375"
)
tg (CPTG
uid 2564,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2565,0
va (VaSet
)
xt "33700,63500,39000,64500"
st "ram_write_ea"
ju 2
blo "39000,64300"
)
)
thePort (LogicalPort
decl (Decl
n "ram_write_ea"
t "std_logic"
o 6
suid 16,0
)
)
)
*33 (CptPort
uid 2566,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2567,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,64625,40750,65375"
)
tg (CPTG
uid 2568,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2569,0
va (VaSet
)
xt "32700,64500,39000,65500"
st "ram_write_ready"
ju 2
blo "39000,65300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_write_ready"
t "std_logic"
o 7
suid 17,0
i "'0'"
)
)
)
*34 (CptPort
uid 2570,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2571,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,73625,40750,74375"
)
tg (CPTG
uid 2572,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2573,0
va (VaSet
)
xt "36000,73500,39000,74500"
st "roi_max"
ju 2
blo "39000,74300"
)
)
thePort (LogicalPort
decl (Decl
n "roi_max"
t "roi_max_type"
o 18
suid 18,0
)
)
)
*35 (CptPort
uid 2614,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2615,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,79625,40750,80375"
)
tg (CPTG
uid 2616,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2617,0
va (VaSet
)
xt "35600,79500,39000,80500"
st "roi_array"
ju 2
blo "39000,80300"
)
)
thePort (LogicalPort
decl (Decl
n "roi_array"
t "roi_array_type"
o 17
suid 19,0
)
)
)
*36 (CptPort
uid 2624,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2625,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,74625,40750,75375"
)
tg (CPTG
uid 2626,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2627,0
va (VaSet
)
xt "29900,74500,39000,75500"
st "package_length : (15:0)"
ju 2
blo "39000,75300"
)
)
thePort (LogicalPort
decl (Decl
n "package_length"
t "std_logic_vector"
b "(15 downto 0)"
o 22
suid 20,0
)
)
)
*37 (CptPort
uid 2760,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2761,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,81625,19000,82375"
)
tg (CPTG
uid 2762,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2763,0
va (VaSet
)
xt "20000,81500,23200,82500"
st "adc_oeb"
blo "20000,82300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_oeb"
t "std_logic"
o 31
suid 23,0
i "'1'"
)
)
)
*38 (CptPort
uid 2764,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2765,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,76625,19000,77375"
)
tg (CPTG
uid 2766,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2767,0
va (VaSet
)
xt "20000,76500,25500,77500"
st "adc_otr : (3:0)"
blo "20000,77300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_otr"
t "std_logic_vector"
b "(3 downto 0)"
o 33
suid 24,0
)
)
)
*39 (CptPort
uid 3918,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3919,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,56625,19000,57375"
)
tg (CPTG
uid 3920,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3921,0
va (VaSet
)
xt "20000,56500,28500,57500"
st "drs_channel_id : (3:0)"
blo "20000,57300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 34
suid 25,0
i "(others => '0')"
)
)
)
*40 (CptPort
uid 3922,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3923,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,52625,19000,53375"
)
tg (CPTG
uid 3924,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3925,0
va (VaSet
)
xt "20000,52500,24400,53500"
st "drs_clk_en"
blo "20000,53300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_clk_en"
t "std_logic"
o 36
suid 26,0
i "'0'"
)
)
)
*41 (CptPort
uid 3926,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3927,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,58625,19000,59375"
)
tg (CPTG
uid 3928,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3929,0
va (VaSet
)
xt "20000,58500,24300,59500"
st "drs_dwrite"
blo "20000,59300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_dwrite"
t "std_logic"
o 35
suid 36,0
i "'1'"
)
)
)
*42 (CptPort
uid 3930,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3931,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,49625,19000,50375"
)
tg (CPTG
uid 3932,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3933,0
va (VaSet
)
xt "20000,49500,26200,50500"
st "drs_read_s_cell"
blo "20000,50300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_read_s_cell"
t "std_logic"
o 37
suid 33,0
i "'0'"
)
)
)
*43 (CptPort
uid 3934,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3935,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,50625,19000,51375"
)
tg (CPTG
uid 3936,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3937,0
va (VaSet
)
xt "20000,50500,28800,51500"
st "drs_read_s_cell_ready"
blo "20000,51300"
)
)
thePort (LogicalPort
decl (Decl
n "drs_read_s_cell_ready"
t "std_logic"
o 38
suid 34,0
)
)
)
*44 (CptPort
uid 3938,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3939,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,51625,19000,52375"
)
tg (CPTG
uid 3940,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3941,0
va (VaSet
)
xt "20000,51500,26400,52500"
st "drs_s_cell_array"
blo "20000,52300"
)
)
thePort (LogicalPort
decl (Decl
n "drs_s_cell_array"
t "drs_s_cell_array_type"
o 39
suid 35,0
)
)
)
*45 (CptPort
uid 4246,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4247,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,75625,19000,76375"
)
tg (CPTG
uid 4248,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4249,0
va (VaSet
)
xt "20000,75500,25900,76500"
st "adc_data_array"
blo "20000,76300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 30
suid 37,0
)
)
)
*46 (CptPort
uid 5174,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5175,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,82625,40750,83375"
)
tg (CPTG
uid 5176,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5177,0
va (VaSet
)
xt "32500,82500,39000,83500"
st "config_ready_cm"
ju 2
blo "39000,83300"
)
)
thePort (LogicalPort
decl (Decl
n "config_ready_cm"
t "std_logic"
o 12
suid 39,0
)
)
)
*47 (CptPort
uid 5178,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5179,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,80625,40750,81375"
)
tg (CPTG
uid 5180,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5181,0
va (VaSet
)
xt "32800,80500,39000,81500"
st "config_start_cm"
ju 2
blo "39000,81300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_start_cm"
t "std_logic"
o 9
suid 40,0
i "'0'"
)
)
)
*48 (CptPort
uid 5271,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5272,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,52625,40750,53375"
)
tg (CPTG
uid 5273,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5274,0
va (VaSet
)
xt "35400,52500,39000,53500"
st "s_trigger"
ju 2
blo "39000,53300"
)
)
thePort (LogicalPort
decl (Decl
n "s_trigger"
t "std_logic"
o 27
suid 41,0
)
)
)
*49 (CptPort
uid 5392,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5393,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,71625,40750,72375"
)
tg (CPTG
uid 5394,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5395,0
va (VaSet
)
xt "32300,71500,39000,72500"
st "config_ready_mm"
ju 2
blo "39000,72300"
)
)
thePort (LogicalPort
decl (Decl
n "config_ready_mm"
t "std_logic"
o 11
suid 42,0
)
)
)
*50 (CptPort
uid 5396,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5397,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,84625,40750,85375"
)
tg (CPTG
uid 5398,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5399,0
va (VaSet
)
xt "32500,84500,39000,85500"
st "config_ready_spi"
ju 2
blo "39000,85300"
)
)
thePort (LogicalPort
decl (Decl
n "config_ready_spi"
t "std_logic"
o 13
suid 43,0
)
)
)
*51 (CptPort
uid 5464,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5465,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,88625,40750,89375"
)
tg (CPTG
uid 5466,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5467,0
va (VaSet
)
xt "33800,88500,39000,89500"
st "sensor_array"
ju 2
blo "39000,89300"
)
)
thePort (LogicalPort
decl (Decl
n "sensor_array"
t "sensor_array_type"
o 19
suid 44,0
)
)
)
*52 (CptPort
uid 5468,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5469,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,89625,40750,90375"
)
tg (CPTG
uid 5470,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5471,0
va (VaSet
)
xt "33700,89500,39000,90500"
st "sensor_ready"
ju 2
blo "39000,90300"
)
)
thePort (LogicalPort
decl (Decl
n "sensor_ready"
t "std_logic"
o 20
suid 45,0
)
)
)
*53 (CptPort
uid 5735,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5736,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,69625,40750,70375"
)
tg (CPTG
uid 5737,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5738,0
va (VaSet
)
xt "32600,69500,39000,70500"
st "config_start_mm"
ju 2
blo "39000,70300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_start_mm"
t "std_logic"
o 8
suid 46,0
i "'0'"
)
)
)
*54 (CptPort
uid 5739,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5740,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,86625,40750,87375"
)
tg (CPTG
uid 5741,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5742,0
va (VaSet
)
xt "32800,86500,39000,87500"
st "config_start_spi"
ju 2
blo "39000,87300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_start_spi"
t "std_logic"
o 10
suid 47,0
i "'0'"
)
)
)
*55 (CptPort
uid 5916,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5917,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,54625,40750,55375"
)
tg (CPTG
uid 5918,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5919,0
va (VaSet
)
xt "33400,54500,39000,55500"
st "config_started"
ju 2
blo "39000,55300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_started"
t "std_logic"
o 29
suid 48,0
i "'0'"
)
)
)
*56 (CptPort
uid 5920,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5921,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,53625,40750,54375"
)
tg (CPTG
uid 5922,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5923,0
va (VaSet
)
xt "34400,53500,39000,54500"
st "new_config"
ju 2
blo "39000,54300"
)
)
thePort (LogicalPort
decl (Decl
n "new_config"
t "std_logic"
o 28
suid 49,0
)
)
)
*57 (CptPort
uid 5974,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5975,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,81625,40750,82375"
)
tg (CPTG
uid 5976,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5977,0
va (VaSet
)
xt "32000,81500,39000,82500"
st "config_started_cm"
ju 2
blo "39000,82300"
)
)
thePort (LogicalPort
decl (Decl
n "config_started_cm"
t "std_logic"
o 15
suid 50,0
)
)
)
*58 (CptPort
uid 5978,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5979,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,70625,40750,71375"
)
tg (CPTG
uid 5980,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5981,0
va (VaSet
)
xt "31800,70500,39000,71500"
st "config_started_mm"
ju 2
blo "39000,71300"
)
)
thePort (LogicalPort
decl (Decl
n "config_started_mm"
t "std_logic"
o 14
suid 51,0
)
)
)
*59 (CptPort
uid 5982,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5983,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,85625,40750,86375"
)
tg (CPTG
uid 5984,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5985,0
va (VaSet
)
xt "32000,85500,39000,86500"
st "config_started_spi"
ju 2
blo "39000,86300"
)
)
thePort (LogicalPort
decl (Decl
n "config_started_spi"
t "std_logic"
o 16
suid 52,0
)
)
)
*60 (CptPort
uid 6060,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6061,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,78625,40750,79375"
)
tg (CPTG
uid 6062,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6063,0
va (VaSet
)
xt "35300,78500,39000,79500"
st "dac_array"
ju 2
blo "39000,79300"
)
)
thePort (LogicalPort
decl (Decl
n "dac_array"
t "dac_array_type"
o 21
suid 53,0
)
)
)
*61 (CptPort
uid 9000,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9001,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,82625,19000,83375"
)
tg (CPTG
uid 9002,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9003,0
va (VaSet
)
xt "20000,82500,24500,83500"
st "adc_clk_en"
blo "20000,83300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_clk_en"
t "std_logic"
o 32
suid 54,0
i "'0'"
)
)
)
]
shape (Rectangle
uid 1400,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "19000,47000,40000,92000"
)
oxt "37000,1000,51000,21000"
ttg (MlTextGroup
uid 1401,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*62 (Text
uid 1402,0
va (VaSet
font "Arial,8,1"
)
xt "19300,91000,25500,92000"
st "FACT_FAD_lib"
blo "19300,91800"
tm "BdLibraryNameMgr"
)
*63 (Text
uid 1403,0
va (VaSet
font "Arial,8,1"
)
xt "19300,92000,25700,93000"
st "data_generator"
blo "19300,92800"
tm "CptNameMgr"
)
*64 (Text
uid 1404,0
va (VaSet
font "Arial,8,1"
)
xt "19300,93000,28900,94000"
st "I_main_data_generator"
blo "19300,93800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1405,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1406,0
text (MLText
uid 1407,0
va (VaSet
font "Courier New,8,0"
)
xt "19000,46200,45500,47000"
st "RAM_ADDR_WIDTH = RAMADDRWIDTH64b    ( integer )  "
)
header ""
)
elements [
(GiElement
name "RAM_ADDR_WIDTH"
type "integer"
value "RAMADDRWIDTH64b"
)
]
)
viewicon (ZoomableIcon
uid 1408,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "19250,90250,20750,91750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*65 (Net
uid 1409,0
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 8
suid 28,0
)
declText (MLText
uid 1410,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,23800,-74500,24600"
st "board_id               : std_logic_vector(3 downto 0)
"
)
)
*66 (Net
uid 1423,0
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 10
suid 29,0
)
declText (MLText
uid 1424,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,25400,-84500,26200"
st "trigger                : std_logic
"
)
)
*67 (PortIoIn
uid 1443,0
shape (CompositeShape
uid 1444,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1445,0
sl 0
ro 270
xt "-28000,68625,-26500,69375"
)
(Line
uid 1446,0
sl 0
ro 270
xt "-26500,69000,-26000,69000"
pts [
"-26500,69000"
"-26000,69000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 1447,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1448,0
va (VaSet
)
xt "-31800,68500,-29000,69500"
st "trigger"
ju 2
blo "-29000,69300"
tm "WireNameMgr"
)
)
)
*68 (SaComponent
uid 1606,0
optionalChildren [
*69 (CptPort
uid 1542,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1543,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,51625,127000,52375"
)
tg (CPTG
uid 1544,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1545,0
va (VaSet
)
xt "128000,51500,129300,52500"
st "clk"
blo "128000,52300"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*70 (CptPort
uid 1546,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1547,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,51625,148750,52375"
)
tg (CPTG
uid 1548,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1549,0
va (VaSet
)
xt "143400,51500,147000,52500"
st "wiz_reset"
ju 2
blo "147000,52300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_reset"
t "std_logic"
preAdd 0
posAdd 0
o 2
suid 2,0
i "'1'"
)
)
)
*71 (CptPort
uid 1550,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1551,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,59625,148750,60375"
)
tg (CPTG
uid 1552,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1553,0
va (VaSet
)
xt "142500,59500,147000,60500"
st "addr : (9:0)"
ju 2
blo "147000,60300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
preAdd 0
posAdd 0
o 3
suid 3,0
)
)
)
*72 (CptPort
uid 1554,0
ps "OnEdgeStrategy"
shape (Diamond
uid 1555,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,60625,148750,61375"
)
tg (CPTG
uid 1556,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1557,0
va (VaSet
)
xt "142200,60500,147000,61500"
st "data : (15:0)"
ju 2
blo "147000,61300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
preAdd 0
posAdd 0
o 4
suid 4,0
)
)
)
*73 (CptPort
uid 1558,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1559,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,52625,148750,53375"
)
tg (CPTG
uid 1560,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1561,0
va (VaSet
)
xt "145800,52500,147000,53500"
st "cs"
ju 2
blo "147000,53300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "cs"
t "std_logic"
preAdd 0
posAdd 0
o 5
suid 5,0
i "'1'"
)
)
)
*74 (CptPort
uid 1562,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1563,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,53625,148750,54375"
)
tg (CPTG
uid 1564,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1565,0
va (VaSet
)
xt "145800,53500,147000,54500"
st "wr"
ju 2
blo "147000,54300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wr"
t "std_logic"
preAdd 0
posAdd 0
o 6
suid 6,0
i "'1'"
)
)
)
*75 (CptPort
uid 1570,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1571,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,54625,148750,55375"
)
tg (CPTG
uid 1572,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1573,0
va (VaSet
)
xt "145900,54500,147000,55500"
st "rd"
ju 2
blo "147000,55300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rd"
t "std_logic"
preAdd 0
posAdd 0
o 8
suid 8,0
i "'1'"
)
)
)
*76 (CptPort
uid 1574,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1575,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,55625,148750,56375"
)
tg (CPTG
uid 1576,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1577,0
va (VaSet
)
xt "145800,55500,147000,56500"
st "int"
ju 2
blo "147000,56300"
)
)
thePort (LogicalPort
decl (Decl
n "int"
t "std_logic"
preAdd 0
posAdd 0
o 9
suid 9,0
)
)
)
*77 (CptPort
uid 1578,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1579,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,69625,127000,70375"
)
tg (CPTG
uid 1580,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1581,0
va (VaSet
)
xt "128000,69500,135900,70500"
st "write_length : (16:0)"
blo "128000,70300"
)
)
thePort (LogicalPort
decl (Decl
n "write_length"
t "std_logic_vector"
b "(16 DOWNTO 0)"
preAdd 0
posAdd 0
o 10
suid 10,0
)
)
)
*78 (CptPort
uid 1582,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1583,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,70625,127000,71375"
)
tg (CPTG
uid 1584,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1585,0
va (VaSet
)
xt "128000,70500,144300,71500"
st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
blo "128000,71300"
)
)
thePort (LogicalPort
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 11
suid 11,0
)
)
)
*79 (CptPort
uid 1586,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1587,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,54625,127000,55375"
)
tg (CPTG
uid 1588,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1589,0
va (VaSet
)
xt "128000,54500,134500,55500"
st "ram_data : (15:0)"
blo "128000,55300"
)
)
thePort (LogicalPort
decl (Decl
n "ram_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
preAdd 0
posAdd 0
o 12
suid 12,0
)
)
)
*80 (CptPort
uid 1590,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1591,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,53625,127000,54375"
)
tg (CPTG
uid 1592,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1593,0
va (VaSet
)
xt "128000,53500,142400,54500"
st "ram_addr : (RAM_ADDR_WIDTH-1:0)"
blo "128000,54300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 13
suid 13,0
)
)
)
*81 (CptPort
uid 1594,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1595,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,68625,127000,69375"
)
tg (CPTG
uid 1596,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1597,0
va (VaSet
)
xt "128000,68500,132100,69500"
st "data_valid"
blo "128000,69300"
)
)
thePort (LogicalPort
decl (Decl
n "data_valid"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 14,0
)
)
)
*82 (CptPort
uid 1598,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1599,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,67625,127000,68375"
)
tg (CPTG
uid 1600,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1601,0
va (VaSet
)
xt "128000,67500,129900,68500"
st "busy"
blo "128000,68300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "busy"
t "std_logic"
preAdd 0
posAdd 0
o 16
suid 15,0
i "'1'"
)
)
)
*83 (CptPort
uid 2218,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2219,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,71625,127000,72375"
)
tg (CPTG
uid 2220,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2221,0
va (VaSet
)
xt "128000,71500,135800,72500"
st "fifo_channels : (3:0)"
blo "128000,72300"
)
)
thePort (LogicalPort
decl (Decl
n "fifo_channels"
t "std_logic_vector"
b "(3 downto 0)"
o 19
suid 20,0
)
)
)
*84 (CptPort
uid 2222,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2223,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,72625,127000,73375"
)
tg (CPTG
uid 2224,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2225,0
va (VaSet
)
xt "128000,72500,133700,73500"
st "write_end_flag"
blo "128000,73300"
)
)
thePort (LogicalPort
decl (Decl
n "write_end_flag"
t "std_logic"
o 18
suid 18,0
)
)
)
*85 (CptPort
uid 2226,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2227,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,73625,127000,74375"
)
tg (CPTG
uid 2228,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2229,0
va (VaSet
)
xt "128000,73500,134800,74500"
st "write_header_flag"
blo "128000,74300"
)
)
thePort (LogicalPort
decl (Decl
n "write_header_flag"
t "std_logic"
o 17
suid 19,0
)
)
)
*86 (CptPort
uid 5216,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5217,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,70625,148750,71375"
)
tg (CPTG
uid 5218,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5219,0
va (VaSet
)
xt "143000,70500,147000,71500"
st "led : (7:0)"
ju 2
blo "147000,71300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 7
suid 22,0
i "(OTHERS => '0')"
)
)
)
*87 (CptPort
uid 5275,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5276,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,58625,127000,59375"
)
tg (CPTG
uid 5277,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5278,0
va (VaSet
)
xt "128000,58500,131600,59500"
st "s_trigger"
blo "128000,59300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "s_trigger"
t "std_logic"
o 20
suid 23,0
i "'0'"
)
)
)
*88 (CptPort
uid 5924,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5925,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,78625,127000,79375"
)
tg (CPTG
uid 5926,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5927,0
va (VaSet
)
xt "128000,78500,135000,79500"
st "config_addr : (7:0)"
blo "128000,79300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_addr"
t "std_logic_vector"
b "(7 downto 0)"
o 23
suid 24,0
)
)
)
*89 (CptPort
uid 5928,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5929,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,83625,127000,84375"
)
tg (CPTG
uid 5930,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5931,0
va (VaSet
)
xt "128000,83500,132800,84500"
st "config_busy"
blo "128000,84300"
)
)
thePort (LogicalPort
decl (Decl
n "config_busy"
t "std_logic"
o 27
suid 25,0
)
)
)
*90 (CptPort
uid 5932,0
ps "OnEdgeStrategy"
shape (Diamond
uid 6051,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,79625,127000,80375"
)
tg (CPTG
uid 5934,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5935,0
va (VaSet
)
xt "128000,79500,135700,80500"
st "config_data : (15:0)"
blo "128000,80300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "config_data"
t "std_logic_vector"
b "(15 downto 0)"
o 24
suid 26,0
i "(others => 'Z')"
)
)
)
*91 (CptPort
uid 5936,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5937,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,60625,127000,61375"
)
tg (CPTG
uid 5938,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5939,0
va (VaSet
)
xt "128000,60500,133600,61500"
st "config_started"
blo "128000,61300"
)
)
thePort (LogicalPort
decl (Decl
n "config_started"
t "std_logic"
o 22
suid 27,0
)
)
)
*92 (CptPort
uid 5940,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5941,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,81625,127000,82375"
)
tg (CPTG
uid 5942,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5943,0
va (VaSet
)
xt "128000,81500,133300,82500"
st "config_wr_en"
blo "128000,82300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_wr_en"
t "std_logic"
o 25
suid 28,0
i "'0'"
)
)
)
*93 (CptPort
uid 5944,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5945,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,59625,127000,60375"
)
tg (CPTG
uid 5946,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5947,0
va (VaSet
)
xt "128000,59500,132600,60500"
st "new_config"
blo "128000,60300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "new_config"
t "std_logic"
o 21
suid 29,0
i "'0'"
)
)
)
*94 (CptPort
uid 5970,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5971,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,82625,127000,83375"
)
tg (CPTG
uid 5972,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5973,0
va (VaSet
)
xt "128000,82500,133200,83500"
st "config_rd_en"
blo "128000,83300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_rd_en"
t "std_logic"
o 26
suid 30,0
i "'0'"
)
)
)
*95 (CptPort
uid 6356,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6357,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,74625,148750,75375"
)
tg (CPTG
uid 6358,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6359,0
va (VaSet
)
xt "144000,74500,147000,75500"
st "denable"
ju 2
blo "147000,75300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 28
suid 31,0
i "'0'"
)
)
)
*96 (CptPort
uid 6446,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6447,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,75625,148750,76375"
)
tg (CPTG
uid 6448,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6449,0
va (VaSet
)
xt "141600,75500,147000,76500"
st "dwrite_enable"
ju 2
blo "147000,76300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dwrite_enable"
t "std_logic"
eolc "-- default DWRITE low."
preAdd 0
posAdd 0
o 29
suid 32,0
i "'0'"
)
)
)
*97 (CptPort
uid 8406,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8407,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,74625,127000,75375"
)
tg (CPTG
uid 8408,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8409,0
va (VaSet
)
xt "128000,74500,133600,75500"
st "data_valid_ack"
blo "128000,75300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data_valid_ack"
t "std_logic"
o 15
suid 34,0
i "'0'"
)
)
)
*98 (CptPort
uid 8748,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8749,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,76625,148750,77375"
)
tg (CPTG
uid 8750,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8751,0
va (VaSet
)
xt "142300,76500,147000,77500"
st "sclk_enable"
ju 2
blo "147000,77300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sclk_enable"
t "std_logic"
eolc "-- default DWRITE HIGH."
posAdd 0
o 30
suid 35,0
i "'1'"
)
)
)
*99 (CptPort
uid 9223,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9224,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,80625,148750,81375"
)
tg (CPTG
uid 9225,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9226,0
va (VaSet
)
xt "142100,80500,147000,81500"
st "ps_direction"
ju 2
blo "147000,81300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ps_direction"
t "std_logic"
eolc "-- default phase shift upwards"
posAdd 0
o 31
suid 36,0
i "'1'"
)
)
)
*100 (CptPort
uid 9227,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9228,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,81625,148750,82375"
)
tg (CPTG
uid 9229,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9230,0
va (VaSet
)
xt "140000,81500,147000,82500"
st "ps_do_phase_shift"
ju 2
blo "147000,82300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ps_do_phase_shift"
t "std_logic"
eolc "--pulse this to phase shift once"
preAdd 0
posAdd 0
o 32
suid 37,0
i "'0'"
)
)
)
*101 (CptPort
uid 9933,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9934,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,82625,148750,83375"
)
tg (CPTG
uid 9935,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9936,0
va (VaSet
)
xt "143700,82500,147000,83500"
st "ps_reset"
ju 2
blo "147000,83300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ps_reset"
t "std_logic"
eolc "-- pulse this to reset the variable phase shift"
posAdd 0
o 33
suid 38,0
i "'0'"
)
)
)
*102 (CptPort
uid 9937,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9938,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,84625,148750,85375"
)
tg (CPTG
uid 9939,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9940,0
va (VaSet
)
xt "142000,84500,147000,85500"
st "srclk_enable"
ju 2
blo "147000,85300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "srclk_enable"
t "std_logic"
eolc "-- default SRCLK on."
posAdd 0
o 34
suid 39,0
i "'1'"
)
)
)
]
shape (Rectangle
uid 1607,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "127000,51000,148000,89000"
)
oxt "43000,2000,56000,22000"
ttg (MlTextGroup
uid 1608,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*103 (Text
uid 1609,0
va (VaSet
font "Arial,8,1"
)
xt "126700,87000,132900,88000"
st "FACT_FAD_lib"
blo "126700,87800"
tm "BdLibraryNameMgr"
)
*104 (Text
uid 1610,0
va (VaSet
font "Arial,8,1"
)
xt "126700,88000,132400,89000"
st "w5300_modul"
blo "126700,88800"
tm "CptNameMgr"
)
*105 (Text
uid 1611,0
va (VaSet
font "Arial,8,1"
)
xt "126700,89000,133400,90000"
st "I_main_ethernet"
blo "126700,89800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1612,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1613,0
text (MLText
uid 1614,0
va (VaSet
font "Courier New,8,0"
)
xt "127000,50200,154500,51000"
st "RAM_ADDR_WIDTH = RAMADDRWIDTH64b+2    ( integer )  "
)
header ""
)
elements [
(GiElement
name "RAM_ADDR_WIDTH"
type "integer"
value "RAMADDRWIDTH64b+2"
)
]
)
viewicon (ZoomableIcon
uid 1615,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "127250,87250,128750,88750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*106 (Net
uid 1680,0
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
o 9
suid 30,0
)
declText (MLText
uid 1681,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,24600,-74500,25400"
st "crate_id               : std_logic_vector(1 downto 0)
"
)
)
*107 (SaComponent
uid 1768,0
optionalChildren [
*108 (CptPort
uid 1760,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1761,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-7000,63625,-6250,64375"
)
tg (CPTG
uid 1762,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1763,0
va (VaSet
)
xt "-14800,63500,-8000,64500"
st "trigger_id : (47:0)"
ju 2
blo "-8000,64300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "trigger_id"
t "std_logic_vector"
b "(47 downto 0)"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*109 (CptPort
uid 1764,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1765,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,63625,-18000,64375"
)
tg (CPTG
uid 1766,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1767,0
va (VaSet
)
xt "-17000,63500,-14200,64500"
st "trigger"
blo "-17000,64300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 2
suid 2,0
)
)
)
*110 (CptPort
uid 6207,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6208,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,62625,-18000,63375"
)
tg (CPTG
uid 6209,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6210,0
va (VaSet
)
xt "-17000,62500,-15700,63500"
st "clk"
blo "-17000,63300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "clk"
t "std_logic"
o 3
suid 3,0
)
)
)
]
shape (Rectangle
uid 1769,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-18000,62000,-7000,67000"
)
oxt "32000,2000,43000,12000"
ttg (MlTextGroup
uid 1770,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*111 (Text
uid 1771,0
va (VaSet
font "Arial,8,1"
)
xt "-6300,65000,300,66000"
st "FACT_FAD_LIB"
blo "-6300,65800"
tm "BdLibraryNameMgr"
)
*112 (Text
uid 1772,0
va (VaSet
font "Arial,8,1"
)
xt "-6300,66000,300,67000"
st "trigger_counter"
blo "-6300,66800"
tm "CptNameMgr"
)
*113 (Text
uid 1773,0
va (VaSet
font "Arial,8,1"
)
xt "-6300,67000,1300,68000"
st "I_main_ext_trigger"
blo "-6300,67800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1774,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1775,0
text (MLText
uid 1776,0
va (VaSet
font "Courier New,8,0"
)
xt "-18000,61000,-18000,61000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 1777,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-17750,65250,-16250,66750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*114 (Net
uid 1981,0
lang 2
decl (Decl
n "trigger_id"
t "std_logic_vector"
b "(47 downto 0)"
preAdd 0
posAdd 0
o 72
suid 34,0
)
declText (MLText
uid 1982,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,97800,-70500,98600"
st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)
"
)
)
*115 (Net
uid 2297,0
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAMADDRWIDTH64b-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 64
suid 36,0
)
declText (MLText
uid 2298,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,89000,-63000,89800"
st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
"
)
)
*116 (SaComponent
uid 2311,0
optionalChildren [
*117 (CptPort
uid 2307,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2308,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,69625,72000,70375"
)
tg (CPTG
uid 2309,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2310,0
va (VaSet
font "arial,8,0"
)
xt "73000,69500,91400,70500"
st "ram_start_addr : (RAM_ADDR_WIDTH_64B-1:0)"
blo "73000,70300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH_64B-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 18
suid 1,0
i "(others => '0')"
)
)
)
*118 (CptPort
uid 2351,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2352,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,67625,72000,68375"
)
tg (CPTG
uid 2353,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2354,0
va (VaSet
font "arial,8,0"
)
xt "73000,67500,74300,68500"
st "clk"
blo "73000,68300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "clk"
t "std_logic"
o 1
suid 2,0
)
)
)
*119 (CptPort
uid 2361,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2362,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,76625,72000,77375"
)
tg (CPTG
uid 2363,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2364,0
va (VaSet
font "arial,8,0"
)
xt "73000,76500,78100,77500"
st "config_ready"
blo "73000,77300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "config_ready"
t "std_logic"
o 6
suid 5,0
i "'0'"
)
)
)
*120 (CptPort
uid 2365,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2366,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,74625,72000,75375"
)
tg (CPTG
uid 2367,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2368,0
va (VaSet
font "arial,8,0"
)
xt "73000,74500,77800,75500"
st "config_start"
blo "73000,75300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "config_start"
t "std_logic"
o 2
suid 3,0
)
)
)
*121 (CptPort
uid 2369,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2370,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,70625,72000,71375"
)
tg (CPTG
uid 2371,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2372,0
va (VaSet
font "arial,8,0"
)
xt "73000,70500,78300,71500"
st "ram_write_ea"
blo "73000,71300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "ram_write_ea"
t "std_logic"
o 5
suid 4,0
i "'0'"
)
)
)
*122 (CptPort
uid 2373,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2374,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,71625,72000,72375"
)
tg (CPTG
uid 2375,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2376,0
va (VaSet
font "arial,8,0"
)
xt "73000,71500,79300,72500"
st "ram_write_ready"
blo "73000,72300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "ram_write_ready"
t "std_logic"
o 3
suid 12,0
)
)
)
*123 (CptPort
uid 2377,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2378,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,77625,72000,78375"
)
tg (CPTG
uid 2379,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2380,0
va (VaSet
font "arial,8,0"
)
xt "73000,77500,76000,78500"
st "roi_max"
blo "73000,78300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "roi_max"
t "roi_max_type"
posAdd 0
o 8
suid 14,0
i "(others => conv_std_logic_vector (0, 11))"
)
)
)
*124 (CptPort
uid 2381,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2382,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103000,67625,103750,68375"
)
tg (CPTG
uid 2383,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2384,0
va (VaSet
font "arial,8,0"
)
xt "98600,67500,102000,68500"
st "wiz_busy"
ju 2
blo "102000,68300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "wiz_busy"
t "std_logic"
o 16
suid 13,0
)
)
)
*125 (CptPort
uid 2385,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2386,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103000,71625,103750,72375"
)
tg (CPTG
uid 2387,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2388,0
va (VaSet
font "arial,8,0"
)
xt "90200,71500,102000,72500"
st "wiz_number_of_channels : (3:0)"
ju 2
blo "102000,72300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_number_of_channels"
t "std_logic_vector"
b "(3 downto 0)"
o 12
suid 6,0
i "(others => '0')"
)
)
)
*126 (CptPort
uid 2389,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2390,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103000,70625,103750,71375"
)
tg (CPTG
uid 2391,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2392,0
va (VaSet
font "arial,8,0"
)
xt "82100,70500,102000,71500"
st "wiz_ram_start_addr : (RAM_ADDR_WIDTH_16B-1:0)"
ju 2
blo "102000,71300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH_16B-1 downto 0)"
preAdd 0
o 10
suid 7,0
i "(others => '0')"
)
)
)
*127 (CptPort
uid 2393,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2394,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103000,68625,103750,69375"
)
tg (CPTG
uid 2395,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2396,0
va (VaSet
font "arial,8,0"
)
xt "96900,68500,102000,69500"
st "wiz_write_ea"
ju 2
blo "102000,69300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_write_ea"
t "std_logic"
o 13
suid 8,0
i "'0'"
)
)
)
*128 (CptPort
uid 2397,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2398,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103000,72625,103750,73375"
)
tg (CPTG
uid 2399,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2400,0
va (VaSet
font "arial,8,0"
)
xt "96500,72500,102000,73500"
st "wiz_write_end"
ju 2
blo "102000,73300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_write_end"
t "std_logic"
o 15
suid 9,0
i "'0'"
)
)
)
*129 (CptPort
uid 2401,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2402,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103000,73625,103750,74375"
)
tg (CPTG
uid 2403,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2404,0
va (VaSet
font "arial,8,0"
)
xt "95400,73500,102000,74500"
st "wiz_write_header"
ju 2
blo "102000,74300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_write_header"
t "std_logic"
o 14
suid 10,0
i "'0'"
)
)
)
*130 (CptPort
uid 2405,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2406,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103000,69625,103750,70375"
)
tg (CPTG
uid 2407,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2408,0
va (VaSet
font "arial,8,0"
)
xt "92600,69500,102000,70500"
st "wiz_write_length : (16:0)"
ju 2
blo "102000,70300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_write_length"
t "std_logic_vector"
b "(16 downto 0)"
o 11
suid 11,0
i "(others => '0')"
)
)
)
*131 (CptPort
uid 2454,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2455,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,84625,72000,85375"
)
tg (CPTG
uid 2456,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2457,0
va (VaSet
font "arial,8,0"
)
xt "73000,84500,76400,85500"
st "roi_array"
blo "73000,85300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "roi_array"
t "roi_array_type"
o 4
suid 15,0
)
)
)
*132 (CptPort
uid 2628,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2629,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,78625,72000,79375"
)
tg (CPTG
uid 2630,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2631,0
va (VaSet
font "arial,8,0"
)
xt "73000,78500,82100,79500"
st "package_length : (15:0)"
blo "73000,79300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "package_length"
t "std_logic_vector"
b "(15 downto 0)"
o 9
suid 18,0
i "(others => '0')"
)
)
)
*133 (CptPort
uid 5991,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5992,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,75625,72000,76375"
)
tg (CPTG
uid 5993,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5994,0
va (VaSet
font "arial,8,0"
)
xt "73000,75500,78600,76500"
st "config_started"
blo "73000,76300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "config_started"
t "std_logic"
o 7
suid 21,0
i "'0'"
)
)
)
*134 (CptPort
uid 8410,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8411,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103000,74625,103750,75375"
)
tg (CPTG
uid 8412,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8413,0
va (VaSet
font "arial,8,0"
)
xt "99000,74500,102000,75500"
st "wiz_ack"
ju 2
blo "102000,75300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "wiz_ack"
t "std_logic"
o 17
suid 22,0
)
)
)
]
shape (Rectangle
uid 2312,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "72000,67000,103000,87000"
)
oxt "15000,6000,23000,16000"
ttg (MlTextGroup
uid 2313,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*135 (Text
uid 2314,0
va (VaSet
font "arial,8,1"
)
xt "72350,87000,78550,88000"
st "FACT_FAD_lib"
blo "72350,87800"
tm "BdLibraryNameMgr"
)
*136 (Text
uid 2315,0
va (VaSet
font "arial,8,1"
)
xt "72350,88000,79650,89000"
st "memory_manager"
blo "72350,88800"
tm "CptNameMgr"
)
*137 (Text
uid 2316,0
va (VaSet
font "arial,8,1"
)
xt "72350,89000,82850,90000"
st "I_main_memory_manager"
blo "72350,89800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2317,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2318,0
text (MLText
uid 2319,0
va (VaSet
font "Courier New,8,0"
)
xt "72000,65400,101500,67000"
st "RAM_ADDR_WIDTH_64B = RAMADDRWIDTH64b      ( integer )  
RAM_ADDR_WIDTH_16B = RAMADDRWIDTH64b+2    ( integer )  "
)
header ""
)
elements [
(GiElement
name "RAM_ADDR_WIDTH_64B"
type "integer"
value "RAMADDRWIDTH64b"
)
(GiElement
name "RAM_ADDR_WIDTH_16B"
type "integer"
value "RAMADDRWIDTH64b+2"
)
]
)
viewicon (ZoomableIcon
uid 2320,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "72250,85250,73750,86750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*138 (Net
uid 2468,0
lang 2
decl (Decl
n "wiz_busy"
t "std_logic"
o 73
suid 38,0
)
declText (MLText
uid 2469,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,99400,-80500,100200"
st "SIGNAL wiz_busy               : std_logic
"
)
)
*139 (Net
uid 2474,0
lang 2
decl (Decl
n "wiz_write_ea"
t "std_logic"
o 76
suid 39,0
i "'0'"
)
declText (MLText
uid 2475,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,101800,-59500,102600"
st "SIGNAL wiz_write_ea           : std_logic                                    := '0'
"
)
)
*140 (Net
uid 2480,0
lang 2
decl (Decl
n "wiz_write_length"
t "std_logic_vector"
b "(16 downto 0)"
o 79
suid 40,0
i "(others => '0')"
)
declText (MLText
uid 2481,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,104200,-53500,105000"
st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')
"
)
)
*141 (Net
uid 2486,0
lang 2
decl (Decl
n "wiz_ram_start_addr"
t "std_logic_vector"
b "(RAMADDRWIDTH64b+1 DOWNTO 0)"
preAdd 0
o 75
suid 41,0
i "(others => '0')"
)
declText (MLText
uid 2487,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,101000,-53500,101800"
st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')
"
)
)
*142 (Net
uid 2492,0
lang 2
decl (Decl
n "wiz_number_of_channels"
t "std_logic_vector"
b "(3 downto 0)"
o 74
suid 42,0
i "(others => '0')"
)
declText (MLText
uid 2493,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,100200,-53500,101000"
st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')
"
)
)
*143 (Net
uid 2498,0
lang 2
decl (Decl
n "wiz_write_end"
t "std_logic"
o 77
suid 43,0
i "'0'"
)
declText (MLText
uid 2499,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,102600,-59500,103400"
st "SIGNAL wiz_write_end          : std_logic                                    := '0'
"
)
)
*144 (Net
uid 2504,0
lang 2
decl (Decl
n "wiz_write_header"
t "std_logic"
o 78
suid 44,0
i "'0'"
)
declText (MLText
uid 2505,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,103400,-59500,104200"
st "SIGNAL wiz_write_header       : std_logic                                    := '0'
"
)
)
*145 (Net
uid 2574,0
decl (Decl
n "ram_write_ea"
t "std_logic"
o 65
suid 48,0
)
declText (MLText
uid 2575,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,89800,-80500,90600"
st "SIGNAL ram_write_ea           : std_logic
"
)
)
*146 (Net
uid 2580,0
decl (Decl
n "ram_write_ready"
t "std_logic"
o 66
suid 49,0
i "'0'"
)
declText (MLText
uid 2581,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,90600,-59500,91400"
st "SIGNAL ram_write_ready        : std_logic                                    := '0'
"
)
)
*147 (Net
uid 2586,0
decl (Decl
n "config_start"
t "std_logic"
o 44
suid 50,0
i "'0'"
)
declText (MLText
uid 2587,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,68200,-59500,69000"
st "SIGNAL config_start           : std_logic                                    := '0'
"
)
)
*148 (Net
uid 2592,0
decl (Decl
n "config_ready"
t "std_logic"
o 41
suid 51,0
)
declText (MLText
uid 2593,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,65800,-80500,66600"
st "SIGNAL config_ready           : std_logic
"
)
)
*149 (Net
uid 2598,0
decl (Decl
n "roi_max"
t "roi_max_type"
o 68
suid 52,0
)
declText (MLText
uid 2599,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,92200,-79000,93000"
st "SIGNAL roi_max                : roi_max_type
"
)
)
*150 (Net
uid 2640,0
decl (Decl
n "package_length"
t "std_logic_vector"
b "(15 downto 0)"
o 61
suid 54,0
)
declText (MLText
uid 2641,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,84200,-70500,85000"
st "SIGNAL package_length         : std_logic_vector(15 downto 0)
"
)
)
*151 (Net
uid 2776,0
decl (Decl
n "adc_oeb"
t "std_logic"
o 16
suid 57,0
i "'1'"
)
declText (MLText
uid 2777,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,39800,-63000,40600"
st "adc_oeb                : std_logic                                    := '1'
"
)
)
*152 (PortIoOut
uid 2798,0
shape (CompositeShape
uid 2799,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2800,0
sl 0
ro 90
xt "-28000,81625,-26500,82375"
)
(Line
uid 2801,0
sl 0
ro 90
xt "-26500,82000,-26000,82000"
pts [
"-26000,82000"
"-26500,82000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 2802,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2803,0
va (VaSet
)
xt "-32200,81500,-29000,82500"
st "adc_oeb"
ju 2
blo "-29000,82300"
tm "WireNameMgr"
)
)
)
*153 (PortIoIn
uid 2804,0
shape (CompositeShape
uid 2805,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2806,0
sl 0
ro 270
xt "-28000,76625,-26500,77375"
)
(Line
uid 2807,0
sl 0
ro 270
xt "-26500,77000,-26000,77000"
pts [
"-26500,77000"
"-26000,77000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 2808,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2809,0
va (VaSet
)
xt "-34400,76500,-29000,77500"
st "adc_otr_array"
ju 2
blo "-29000,77300"
tm "WireNameMgr"
)
)
)
*154 (Net
uid 2924,0
decl (Decl
n "roi_array"
t "roi_array_type"
o 67
suid 65,0
)
declText (MLText
uid 2925,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,91400,-78000,92200"
st "SIGNAL roi_array              : roi_array_type
"
)
)
*155 (PortIoIn
uid 2950,0
shape (CompositeShape
uid 2951,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2952,0
sl 0
ro 270
xt "-28000,85625,-26500,86375"
)
(Line
uid 2953,0
sl 0
ro 270
xt "-26500,86000,-26000,86000"
pts [
"-26500,86000"
"-26000,86000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 2954,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2955,0
va (VaSet
)
xt "-32300,85500,-29000,86500"
st "board_id"
ju 2
blo "-29000,86300"
tm "WireNameMgr"
)
)
)
*156 (PortIoIn
uid 2956,0
shape (CompositeShape
uid 2957,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2958,0
sl 0
ro 270
xt "-28000,86625,-26500,87375"
)
(Line
uid 2959,0
sl 0
ro 270
xt "-26500,87000,-26000,87000"
pts [
"-26500,87000"
"-26000,87000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 2960,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2961,0
va (VaSet
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xt "-32100,86500,-29000,87500"
st "crate_id"
ju 2
blo "-29000,87300"
tm "WireNameMgr"
)
)
)
*157 (Grouping
uid 3137,0
optionalChildren [
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uid 3139,0
shape (Rectangle
uid 3140,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
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xt "125000,175000,142000,176000"
)
oxt "18000,70000,35000,71000"
text (MLText
uid 3141,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "125200,175000,134900,176000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*159 (CommentText
uid 3142,0
shape (Rectangle
uid 3143,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
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xt "142000,171000,146000,172000"
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oxt "35000,66000,39000,67000"
text (MLText
uid 3144,0
va (VaSet
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bg "0,0,32768"
)
xt "142200,171000,145200,172000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*160 (CommentText
uid 3145,0
shape (Rectangle
uid 3146,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "125000,173000,142000,174000"
)
oxt "18000,68000,35000,69000"
text (MLText
uid 3147,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "125200,173000,135200,174000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*161 (CommentText
uid 3148,0
shape (Rectangle
uid 3149,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "121000,173000,125000,174000"
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oxt "14000,68000,18000,69000"
text (MLText
uid 3150,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "121200,173000,123300,174000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*162 (CommentText
uid 3151,0
shape (Rectangle
uid 3152,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "142000,172000,162000,176000"
)
oxt "35000,67000,55000,71000"
text (MLText
uid 3153,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "142200,172200,151400,173200"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
titleBlock 1
)
*163 (CommentText
uid 3154,0
shape (Rectangle
uid 3155,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "146000,171000,162000,172000"
)
oxt "39000,66000,55000,67000"
text (MLText
uid 3156,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "146200,171000,150700,172000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
titleBlock 1
)
*164 (CommentText
uid 3157,0
shape (Rectangle
uid 3158,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "121000,171000,142000,173000"
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oxt "14000,66000,35000,68000"
text (MLText
uid 3159,0
va (VaSet
fg "32768,0,0"
)
xt "128700,171000,134300,173000"
st "
TU Dortmund 
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ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
titleBlock 1
)
*165 (CommentText
uid 3160,0
shape (Rectangle
uid 3161,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
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xt "121000,174000,125000,175000"
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oxt "14000,69000,18000,70000"
text (MLText
uid 3162,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
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xt "121200,174000,123300,175000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*166 (CommentText
uid 3163,0
shape (Rectangle
uid 3164,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "121000,175000,125000,176000"
)
oxt "14000,70000,18000,71000"
text (MLText
uid 3165,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "121200,175000,123900,176000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
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position 1
ignorePrefs 1
titleBlock 1
)
*167 (CommentText
uid 3166,0
shape (Rectangle
uid 3167,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
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xt "125000,174000,142000,175000"
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oxt "18000,69000,35000,70000"
text (MLText
uid 3168,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
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xt "125200,174000,137600,175000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
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)
position 1
ignorePrefs 1
titleBlock 1
)
]
shape (GroupingShape
uid 3138,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
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xt "121000,171000,162000,176000"
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oxt "14000,66000,55000,71000"
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*168 (Net
uid 3894,0
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 12
suid 81,0
)
declText (MLText
uid 3895,0
va (VaSet
font "Courier New,8,0"
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xt "-103000,29400,-84500,30200"
st "CLK_25_PS              : std_logic
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)
)
*169 (PortIoOut
uid 3978,0
shape (CompositeShape
uid 3979,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
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uid 3980,0
sl 0
ro 90
xt "-28000,28625,-26500,29375"
)
(Line
uid 3981,0
sl 0
ro 90
xt "-26500,29000,-26000,29000"
pts [
"-26000,29000"
"-26500,29000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3982,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3983,0
va (VaSet
)
xt "-33500,28500,-29000,29500"
st "CLK_25_PS"
ju 2
blo "-29000,29300"
tm "WireNameMgr"
)
)
)
*170 (Net
uid 4068,0
decl (Decl
n "CLK_50"
t "std_logic"
o 13
suid 90,0
)
declText (MLText
uid 4069,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,30200,-84500,31000"
st "CLK_50                 : std_logic
"
)
)
*171 (Net
uid 4204,0
decl (Decl
n "CLK_25"
t "std_logic"
o 32
suid 91,0
)
declText (MLText
uid 4205,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,57800,-80500,58600"
st "SIGNAL CLK_25                 : std_logic
"
)
)
*172 (PortIoOut
uid 4220,0
shape (CompositeShape
uid 4221,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4222,0
sl 0
ro 90
xt "-28000,33625,-26500,34375"
)
(Line
uid 4223,0
sl 0
ro 90
xt "-26500,34000,-26000,34000"
pts [
"-26000,34000"
"-26500,34000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4224,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4225,0
va (VaSet
)
xt "-32100,33500,-29000,34500"
st "CLK_50"
ju 2
blo "-29000,34300"
tm "WireNameMgr"
)
)
)
*173 (Net
uid 4232,0
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 92,0
)
declText (MLText
uid 4233,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,18200,-84500,19000"
st "CLK                    : std_logic
"
)
)
*174 (Net
uid 4260,0
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 7
suid 95,0
)
declText (MLText
uid 4261,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,23000,-74500,23800"
st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)
"
)
)
*175 (Net
uid 4270,0
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 6
suid 96,0
)
declText (MLText
uid 4271,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,22200,-79000,23000"
st "adc_data_array         : adc_data_array_type
"
)
)
*176 (PortIoIn
uid 4307,0
shape (CompositeShape
uid 4308,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4309,0
sl 0
ro 270
xt "-28000,75625,-26500,76375"
)
(Line
uid 4310,0
sl 0
ro 270
xt "-26500,76000,-26000,76000"
pts [
"-26500,76000"
"-26000,76000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4311,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4312,0
va (VaSet
)
xt "-34900,75500,-29000,76500"
st "adc_data_array"
ju 2
blo "-29000,76300"
tm "WireNameMgr"
)
)
)
*177 (Net
uid 4399,0
decl (Decl
n "drs_clk_en"
t "std_logic"
o 54
suid 97,0
i "'0'"
)
declText (MLText
uid 4400,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,78600,-59500,79400"
st "SIGNAL drs_clk_en             : std_logic                                    := '0'
"
)
)
*178 (Net
uid 4405,0
decl (Decl
n "drs_s_cell_array"
t "drs_s_cell_array_type"
o 57
suid 98,0
)
declText (MLText
uid 4406,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,81000,-74500,81800"
st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type
"
)
)
*179 (Net
uid 4417,0
decl (Decl
n "drs_read_s_cell"
t "std_logic"
o 55
suid 100,0
i "'0'"
)
declText (MLText
uid 4418,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,79400,-59500,80200"
st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'
"
)
)
*180 (Net
uid 4535,0
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 19
suid 109,0
i "(others => '0')"
)
declText (MLText
uid 4536,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,42200,-57000,43000"
st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')
"
)
)
*181 (Net
uid 4543,0
decl (Decl
n "drs_dwrite"
t "std_logic"
o 20
suid 110,0
i "'1'"
)
declText (MLText
uid 4544,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,43000,-63000,43800"
st "drs_dwrite             : std_logic                                    := '1'
"
)
)
*182 (PortIoOut
uid 4551,0
shape (CompositeShape
uid 4552,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4553,0
sl 0
ro 90
xt "-39000,99625,-37500,100375"
)
(Line
uid 4554,0
sl 0
ro 90
xt "-37500,100000,-37000,100000"
pts [
"-37000,100000"
"-37500,100000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4555,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4556,0
va (VaSet
)
xt "-45900,99500,-40000,100500"
st "drs_channel_id"
ju 2
blo "-40000,100300"
tm "WireNameMgr"
)
)
)
*183 (PortIoOut
uid 4557,0
shape (CompositeShape
uid 4558,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4559,0
sl 0
ro 90
xt "-28000,59625,-26500,60375"
)
(Line
uid 4560,0
sl 0
ro 90
xt "-26500,60000,-26000,60000"
pts [
"-26000,60000"
"-26500,60000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4561,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4562,0
va (VaSet
)
xt "-33300,59500,-29000,60500"
st "drs_dwrite"
ju 2
blo "-29000,60300"
tm "WireNameMgr"
)
)
)
*184 (Net
uid 4669,0
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 2
suid 112,0
)
declText (MLText
uid 4670,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,19000,-84500,19800"
st "SROUT_in_0             : std_logic
"
)
)
*185 (Net
uid 4677,0
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 3
suid 113,0
)
declText (MLText
uid 4678,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,19800,-84500,20600"
st "SROUT_in_1             : std_logic
"
)
)
*186 (Net
uid 4685,0
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 4
suid 114,0
)
declText (MLText
uid 4686,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,20600,-84500,21400"
st "SROUT_in_2             : std_logic
"
)
)
*187 (Net
uid 4693,0
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 5
suid 115,0
)
declText (MLText
uid 4694,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,21400,-84500,22200"
st "SROUT_in_3             : std_logic
"
)
)
*188 (PortIoIn
uid 4701,0
shape (CompositeShape
uid 4702,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4703,0
sl 0
ro 270
xt "-28000,46625,-26500,47375"
)
(Line
uid 4704,0
sl 0
ro 270
xt "-26500,47000,-26000,47000"
pts [
"-26500,47000"
"-26000,47000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4705,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4706,0
va (VaSet
)
xt "-34400,46500,-29000,47500"
st "SROUT_in_0"
ju 2
blo "-29000,47300"
tm "WireNameMgr"
)
)
)
*189 (PortIoIn
uid 4707,0
shape (CompositeShape
uid 4708,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4709,0
sl 0
ro 270
xt "-28000,47625,-26500,48375"
)
(Line
uid 4710,0
sl 0
ro 270
xt "-26500,48000,-26000,48000"
pts [
"-26500,48000"
"-26000,48000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4711,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4712,0
va (VaSet
)
xt "-34400,47500,-29000,48500"
st "SROUT_in_1"
ju 2
blo "-29000,48300"
tm "WireNameMgr"
)
)
)
*190 (PortIoIn
uid 4713,0
shape (CompositeShape
uid 4714,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4715,0
sl 0
ro 270
xt "-28000,48625,-26500,49375"
)
(Line
uid 4716,0
sl 0
ro 270
xt "-26500,49000,-26000,49000"
pts [
"-26500,49000"
"-26000,49000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4717,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4718,0
va (VaSet
)
xt "-34400,48500,-29000,49500"
st "SROUT_in_2"
ju 2
blo "-29000,49300"
tm "WireNameMgr"
)
)
)
*191 (PortIoIn
uid 4719,0
shape (CompositeShape
uid 4720,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4721,0
sl 0
ro 270
xt "-28000,49625,-26500,50375"
)
(Line
uid 4722,0
sl 0
ro 270
xt "-26500,50000,-26000,50000"
pts [
"-26500,50000"
"-26000,50000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4723,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4724,0
va (VaSet
)
xt "-34400,49500,-29000,50500"
st "SROUT_in_3"
ju 2
blo "-29000,50300"
tm "WireNameMgr"
)
)
)
*192 (Net
uid 4741,0
decl (Decl
n "drs_read_s_cell_ready"
t "std_logic"
o 56
suid 116,0
)
declText (MLText
uid 4742,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,80200,-80500,81000"
st "SIGNAL drs_read_s_cell_ready  : std_logic
"
)
)
*193 (SaComponent
uid 4903,0
optionalChildren [
*194 (CptPort
uid 4867,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4868,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,44625,-18000,45375"
)
tg (CPTG
uid 4869,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4870,0
va (VaSet
)
xt "-17000,44500,-15100,45500"
st "CLK"
blo "-17000,45300"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
)
)
)
*195 (CptPort
uid 4871,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4872,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "1000,52625,1750,53375"
)
tg (CPTG
uid 4873,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4874,0
va (VaSet
)
xt "-7500,52500,0,53500"
st "start_endless_mode"
ju 2
blo "0,53300"
)
)
thePort (LogicalPort
decl (Decl
n "start_endless_mode"
t "std_logic"
o 2
)
)
)
*196 (CptPort
uid 4875,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4876,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "1000,49625,1750,50375"
)
tg (CPTG
uid 4877,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4878,0
va (VaSet
)
xt "-10200,49500,0,50500"
st "start_read_stop_pos_mode"
ju 2
blo "0,50300"
)
)
thePort (LogicalPort
decl (Decl
n "start_read_stop_pos_mode"
t "std_logic"
o 3
)
)
)
*197 (CptPort
uid 4879,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4880,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,46625,-18000,47375"
)
tg (CPTG
uid 4881,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4882,0
va (VaSet
)
xt "-17000,46500,-11600,47500"
st "SROUT_in_0"
blo "-17000,47300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 4
)
)
)
*198 (CptPort
uid 4883,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4884,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,47625,-18000,48375"
)
tg (CPTG
uid 4885,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4886,0
va (VaSet
)
xt "-17000,47500,-11600,48500"
st "SROUT_in_1"
blo "-17000,48300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 5
)
)
)
*199 (CptPort
uid 4887,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4888,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,48625,-18000,49375"
)
tg (CPTG
uid 4889,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4890,0
va (VaSet
)
xt "-17000,48500,-11600,49500"
st "SROUT_in_2"
blo "-17000,49300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 6
)
)
)
*200 (CptPort
uid 4891,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4892,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,49625,-18000,50375"
)
tg (CPTG
uid 4893,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4894,0
va (VaSet
)
xt "-17000,49500,-11600,50500"
st "SROUT_in_3"
blo "-17000,50300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 7
)
)
)
*201 (CptPort
uid 4895,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4896,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "1000,51625,1750,52375"
)
tg (CPTG
uid 4897,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4898,0
va (VaSet
)
xt "-3400,51500,0,52500"
st "stop_pos"
ju 2
blo "0,52300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "stop_pos"
t "drs_s_cell_array_type"
o 8
)
)
)
*202 (CptPort
uid 4899,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4900,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "1000,50625,1750,51375"
)
tg (CPTG
uid 4901,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4902,0
va (VaSet
)
xt "-5700,50500,0,51500"
st "stop_pos_valid"
ju 2
blo "0,51300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "stop_pos_valid"
t "std_logic"
o 9
i "'0'"
)
)
)
*203 (CptPort
uid 4938,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4939,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,50625,-18000,51375"
)
tg (CPTG
uid 4940,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4941,0
va (VaSet
)
xt "-17000,50500,-12800,51500"
st "RSRLOAD"
blo "-17000,51300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "RSRLOAD"
t "std_logic"
o 10
i "'0'"
)
)
)
*204 (CptPort
uid 4942,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4943,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,51625,-18000,52375"
)
tg (CPTG
uid 4944,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4945,0
va (VaSet
)
xt "-17000,51500,-14000,52500"
st "SRCLK"
blo "-17000,52300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SRCLK"
t "std_logic"
o 11
i "'0'"
)
)
)
]
shape (Rectangle
uid 4904,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-18000,44000,1000,54000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 4905,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*205 (Text
uid 4906,0
va (VaSet
font "Arial,8,1"
)
xt "-17400,54000,-10800,55000"
st "FACT_FAD_LIB"
blo "-17400,54800"
tm "BdLibraryNameMgr"
)
*206 (Text
uid 4907,0
va (VaSet
font "Arial,8,1"
)
xt "-17400,55000,-12700,56000"
st "drs_pulser"
blo "-17400,55800"
tm "CptNameMgr"
)
*207 (Text
uid 4908,0
va (VaSet
font "Arial,8,1"
)
xt "-17400,56000,-9900,57000"
st "I_main_drs_pulser"
blo "-17400,56800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4909,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4910,0
text (MLText
uid 4911,0
va (VaSet
font "Courier New,8,0"
)
xt "-8500,46000,-8500,46000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 4912,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-17750,52250,-16250,53750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*208 (Net
uid 4946,0
decl (Decl
n "RSRLOAD"
t "std_logic"
o 14
suid 117,0
i "'0'"
)
declText (MLText
uid 4947,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,37400,-63000,38200"
st "RSRLOAD                : std_logic                                    := '0'
"
)
)
*209 (PortIoOut
uid 4954,0
shape (CompositeShape
uid 4955,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4956,0
sl 0
ro 90
xt "-28000,50625,-26500,51375"
)
(Line
uid 4957,0
sl 0
ro 90
xt "-26500,51000,-26000,51000"
pts [
"-26000,51000"
"-26500,51000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4958,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4959,0
va (VaSet
)
xt "-33200,50500,-29000,51500"
st "RSRLOAD"
ju 2
blo "-29000,51300"
tm "WireNameMgr"
)
)
)
*210 (Net
uid 4960,0
decl (Decl
n "SRCLK"
t "std_logic"
o 15
suid 118,0
i "'0'"
)
declText (MLText
uid 4961,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,38200,-63000,39000"
st "SRCLK                  : std_logic                                    := '0'
"
)
)
*211 (PortIoOut
uid 4968,0
shape (CompositeShape
uid 4969,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4970,0
sl 0
ro 90
xt "-35000,53625,-33500,54375"
)
(Line
uid 4971,0
sl 0
ro 90
xt "-33500,54000,-33000,54000"
pts [
"-33000,54000"
"-33500,54000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4972,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4973,0
va (VaSet
)
xt "-39000,53500,-36000,54500"
st "SRCLK"
ju 2
blo "-36000,54300"
tm "WireNameMgr"
)
)
)
*212 (SaComponent
uid 5072,0
optionalChildren [
*213 (CptPort
uid 5028,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5029,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "73250,99625,74000,100375"
)
tg (CPTG
uid 5030,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5031,0
va (VaSet
)
xt "75000,99500,76300,100500"
st "clk"
blo "75000,100300"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "STD_LOGIC"
o 1
suid 1,0
)
)
)
*214 (CptPort
uid 5032,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5033,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "92000,99625,92750,100375"
)
tg (CPTG
uid 5034,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5035,0
va (VaSet
)
xt "84000,99500,91000,100500"
st "config_addr : (7:0)"
ju 2
blo "91000,100300"
)
)
thePort (LogicalPort
decl (Decl
n "config_addr"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*215 (CptPort
uid 5036,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5037,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "92000,101625,92750,102375"
)
tg (CPTG
uid 5038,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5039,0
va (VaSet
)
xt "84400,101500,91000,102500"
st "config_data_valid"
ju 2
blo "91000,102300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_data_valid"
t "std_logic"
o 7
suid 3,0
)
)
)
*216 (CptPort
uid 5040,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5041,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "92000,105625,92750,106375"
)
tg (CPTG
uid 5042,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5043,0
va (VaSet
)
xt "86200,105500,91000,106500"
st "config_busy"
ju 2
blo "91000,106300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_busy"
t "std_logic"
o 6
suid 4,0
)
)
)
*217 (CptPort
uid 5044,0
ps "OnEdgeStrategy"
shape (Diamond
uid 5045,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "92000,100625,92750,101375"
)
tg (CPTG
uid 5046,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5047,0
va (VaSet
)
xt "83300,100500,91000,101500"
st "config_data : (15:0)"
ju 2
blo "91000,101300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "config_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 14
suid 5,0
)
)
)
*218 (CptPort
uid 5048,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5049,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "73250,101625,74000,102375"
)
tg (CPTG
uid 5050,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5051,0
va (VaSet
)
xt "75000,101500,78400,102500"
st "roi_array"
blo "75000,102300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "roi_array"
t "roi_array_type"
o 13
suid 6,0
)
)
)
*219 (CptPort
uid 5052,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5053,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "92000,103625,92750,104375"
)
tg (CPTG
uid 5054,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5055,0
va (VaSet
)
xt "85700,103500,91000,104500"
st "config_wr_en"
ju 2
blo "91000,104300"
)
)
thePort (LogicalPort
decl (Decl
n "config_wr_en"
t "std_logic"
o 5
suid 7,0
)
)
)
*220 (CptPort
uid 5056,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5057,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "73250,108625,74000,109375"
)
tg (CPTG
uid 5058,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5059,0
va (VaSet
)
xt "75000,108500,78700,109500"
st "dac_array"
blo "75000,109300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dac_array"
t "dac_array_type"
o 10
suid 8,0
)
)
)
*221 (CptPort
uid 5060,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5061,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "92000,104625,92750,105375"
)
tg (CPTG
uid 5062,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5063,0
va (VaSet
)
xt "85800,104500,91000,105500"
st "config_rd_en"
ju 2
blo "91000,105300"
)
)
thePort (LogicalPort
decl (Decl
n "config_rd_en"
t "std_logic"
o 3
suid 9,0
)
)
)
*222 (CptPort
uid 5064,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5065,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "73250,102625,74000,103375"
)
tg (CPTG
uid 5066,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5067,0
va (VaSet
)
xt "75000,102500,79800,103500"
st "config_start"
blo "75000,103300"
)
)
thePort (LogicalPort
decl (Decl
n "config_start"
t "std_logic"
o 4
suid 10,0
)
)
)
*223 (CptPort
uid 5068,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5069,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "73250,104625,74000,105375"
)
tg (CPTG
uid 5070,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5071,0
va (VaSet
)
xt "75000,104500,80100,105500"
st "config_ready"
blo "75000,105300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_ready"
t "std_logic"
o 8
suid 11,0
)
)
)
*224 (CptPort
uid 5995,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5996,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "73250,103625,74000,104375"
)
tg (CPTG
uid 5997,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5998,0
va (VaSet
)
xt "75000,103500,80600,104500"
st "config_started"
blo "75000,104300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_started"
t "std_logic"
o 9
suid 12,0
i "'0'"
)
)
)
*225 (CptPort
uid 8500,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8501,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "92000,109625,92750,110375"
)
tg (CPTG
uid 8502,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8503,0
va (VaSet
)
xt "83800,109500,91000,110500"
st "drs_address : (3:0)"
ju 2
blo "91000,110300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_address"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 11
suid 13,0
)
)
)
*226 (CptPort
uid 8504,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8505,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "92000,110625,92750,111375"
)
tg (CPTG
uid 8506,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8507,0
va (VaSet
)
xt "83800,110500,91000,111500"
st "drs_address_mode"
ju 2
blo "91000,111300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_address_mode"
t "std_logic"
o 12
suid 14,0
)
)
)
]
shape (Rectangle
uid 5073,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "74000,99000,92000,112000"
)
oxt "15000,13000,33000,26000"
ttg (MlTextGroup
uid 5074,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*227 (Text
uid 5075,0
va (VaSet
font "Arial,8,1"
)
xt "74200,112000,80400,113000"
st "FACT_FAD_lib"
blo "74200,112800"
tm "BdLibraryNameMgr"
)
*228 (Text
uid 5076,0
va (VaSet
font "Arial,8,1"
)
xt "74200,113000,79600,114000"
st "control_unit"
blo "74200,113800"
tm "CptNameMgr"
)
*229 (Text
uid 5077,0
va (VaSet
font "Arial,8,1"
)
xt "74200,114000,82400,115000"
st "I_main_control_unit"
blo "74200,114800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 5078,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 5079,0
text (MLText
uid 5080,0
va (VaSet
font "Courier New,8,0"
)
xt "59000,98800,59000,98800"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 5081,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "74250,110250,75750,111750"
iconName "BlockDiagram.png"
iconMaskName "BlockDiagram.msk"
ftype 1
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*230 (Net
uid 5088,0
decl (Decl
n "config_addr"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 36
suid 119,0
)
declText (MLText
uid 5089,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,61800,-71000,62600"
st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)
"
)
)
*231 (Net
uid 5096,0
decl (Decl
n "config_data_valid"
t "std_logic"
o 39
suid 120,0
)
declText (MLText
uid 5097,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,64200,-80500,65000"
st "SIGNAL config_data_valid      : std_logic
"
)
)
*232 (Net
uid 5104,0
decl (Decl
n "config_busy"
t "std_logic"
o 37
suid 121,0
)
declText (MLText
uid 5105,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,62600,-80500,63400"
st "SIGNAL config_busy            : std_logic
"
)
)
*233 (Net
uid 5112,0
decl (Decl
n "config_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 38
suid 122,0
)
declText (MLText
uid 5113,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,63400,-70500,64200"
st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)
"
)
)
*234 (Net
uid 5120,0
decl (Decl
n "config_wr_en"
t "std_logic"
o 51
suid 123,0
)
declText (MLText
uid 5121,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,73800,-80500,74600"
st "SIGNAL config_wr_en           : std_logic
"
)
)
*235 (Net
uid 5128,0
decl (Decl
n "config_rd_en"
t "std_logic"
o 40
suid 124,0
)
declText (MLText
uid 5129,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,65000,-80500,65800"
st "SIGNAL config_rd_en           : std_logic
"
)
)
*236 (Net
uid 5144,0
decl (Decl
n "dac_array"
t "dac_array_type"
o 52
suid 126,0
)
declText (MLText
uid 5145,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,74600,-78000,75400"
st "SIGNAL dac_array              : dac_array_type
"
)
)
*237 (Net
uid 5194,0
decl (Decl
n "config_start_cm"
t "std_logic"
o 45
suid 131,0
)
declText (MLText
uid 5195,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,69000,-80500,69800"
st "SIGNAL config_start_cm        : std_logic
"
)
)
*238 (Net
uid 5196,0
decl (Decl
n "config_ready_cm"
t "std_logic"
o 42
suid 132,0
)
declText (MLText
uid 5197,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,66600,-80500,67400"
st "SIGNAL config_ready_cm        : std_logic
"
)
)
*239 (Net
uid 5220,0
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 21
suid 133,0
i "(OTHERS => '0')"
)
declText (MLText
uid 5221,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,43800,-57000,44600"
st "led                    : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')
"
)
)
*240 (Net
uid 5279,0
decl (Decl
n "s_trigger"
t "std_logic"
o 69
suid 134,0
i "'0'"
)
declText (MLText
uid 5280,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,93000,-59500,93800"
st "SIGNAL s_trigger              : std_logic                                    := '0'
"
)
)
*241 (Net
uid 5472,0
decl (Decl
n "sensor_ready"
t "std_logic"
o 71
suid 140,0
)
declText (MLText
uid 5473,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,96200,-80500,97000"
st "SIGNAL sensor_ready           : std_logic
"
)
)
*242 (Net
uid 5478,0
decl (Decl
n "sensor_array"
t "sensor_array_type"
o 70
suid 141,0
)
declText (MLText
uid 5479,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,95400,-76500,96200"
st "SIGNAL sensor_array           : sensor_array_type
"
)
)
*243 (Net
uid 5588,0
decl (Decl
n "config_ready_spi"
t "std_logic"
o 43
suid 144,0
)
declText (MLText
uid 5589,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,67400,-80500,68200"
st "SIGNAL config_ready_spi       : std_logic
"
)
)
*244 (Net
uid 5632,0
lang 10
decl (Decl
n "adc_otr"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 34
suid 146,0
)
declText (MLText
uid 5633,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,60200,-71000,61000"
st "SIGNAL adc_otr                : std_logic_vector(3 DOWNTO 0)
"
)
)
*245 (Net
uid 5640,0
decl (Decl
n "adc_data_array_int"
t "adc_data_array_type"
o 33
suid 147,0
)
declText (MLText
uid 5641,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,59400,-75500,60200"
st "SIGNAL adc_data_array_int     : adc_data_array_type
"
)
)
*246 (SaComponent
uid 5678,0
optionalChildren [
*247 (CptPort
uid 5658,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5659,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,75625,-18000,76375"
)
tg (CPTG
uid 5660,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5661,0
va (VaSet
font "arial,8,0"
)
xt "-17000,75500,-11100,76500"
st "adc_data_array"
blo "-17000,76300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 2
suid 5,0
)
)
)
*248 (CptPort
uid 5662,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5663,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,75625,750,76375"
)
tg (CPTG
uid 5664,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5665,0
va (VaSet
font "arial,8,0"
)
xt "-8100,75500,-1000,76500"
st "adc_data_array_int"
ju 2
blo "-1000,76300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_data_array_int"
t "adc_data_array_type"
o 4
suid 6,0
)
)
)
*249 (CptPort
uid 5666,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5667,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,76625,750,77375"
)
tg (CPTG
uid 5668,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5669,0
va (VaSet
font "arial,8,0"
)
xt "-3900,76500,-1000,77500"
st "adc_otr"
ju 2
blo "-1000,77300"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "adc_otr"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 5
suid 7,0
)
)
)
*250 (CptPort
uid 5670,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5671,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,76625,-18000,77375"
)
tg (CPTG
uid 5672,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5673,0
va (VaSet
font "arial,8,0"
)
xt "-17000,76500,-11600,77500"
st "adc_otr_array"
blo "-17000,77300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 3
suid 8,0
)
)
)
*251 (CptPort
uid 5674,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5675,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,73625,-18000,74375"
)
tg (CPTG
uid 5676,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5677,0
va (VaSet
font "arial,8,0"
)
xt "-17000,73500,-14500,74500"
st "clk_ps"
blo "-17000,74300"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "clk_ps"
t "std_logic"
o 1
suid 9,0
)
)
)
]
shape (Rectangle
uid 5679,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-18000,73000,0,80000"
)
oxt "15000,6000,23000,11000"
ttg (MlTextGroup
uid 5680,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*252 (Text
uid 5681,0
va (VaSet
font "arial,8,1"
)
xt "900,77500,7100,78500"
st "FACT_FAD_lib"
blo "900,78300"
tm "BdLibraryNameMgr"
)
*253 (Text
uid 5682,0
va (VaSet
font "arial,8,1"
)
xt "900,78500,5700,79500"
st "adc_buffer"
blo "900,79300"
tm "CptNameMgr"
)
*254 (Text
uid 5683,0
va (VaSet
font "arial,8,1"
)
xt "900,79500,8500,80500"
st "I_main_adc_buffer"
blo "900,80300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 5684,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 5685,0
text (MLText
uid 5686,0
va (VaSet
font "Courier New,8,0"
)
xt "-38000,73300,-38000,73300"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 5687,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-17750,78250,-16250,79750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*255 (Net
uid 5743,0
decl (Decl
n "config_start_spi"
t "std_logic"
o 46
suid 149,0
i "'0'"
)
declText (MLText
uid 5744,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,69800,-59500,70600"
st "SIGNAL config_start_spi       : std_logic                                    := '0'
"
)
)
*256 (SaComponent
uid 5793,0
optionalChildren [
*257 (CptPort
uid 5753,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5754,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "20250,106625,21000,107375"
)
tg (CPTG
uid 5755,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5756,0
va (VaSet
)
xt "22000,106500,23700,107500"
st "sclk"
blo "22000,107300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sclk"
t "std_logic"
o 8
suid 1,0
)
)
)
*258 (CptPort
uid 5761,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5762,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,108625,37750,109375"
)
tg (CPTG
uid 5763,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5764,0
va (VaSet
)
xt "32300,108500,36000,109500"
st "dac_array"
ju 2
blo "36000,109300"
)
)
thePort (LogicalPort
decl (Decl
n "dac_array"
t "dac_array_type"
o 3
suid 10,0
)
)
)
*259 (CptPort
uid 5765,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5766,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,106625,37750,107375"
)
tg (CPTG
uid 5767,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5768,0
va (VaSet
)
xt "30900,106500,36000,107500"
st "config_ready"
ju 2
blo "36000,107300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_ready"
t "std_logic"
o 4
suid 11,0
)
)
)
*260 (CptPort
uid 5769,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5770,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,104625,37750,105375"
)
tg (CPTG
uid 5771,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5772,0
va (VaSet
)
xt "31200,104500,36000,105500"
st "config_start"
ju 2
blo "36000,105300"
)
)
thePort (LogicalPort
decl (Decl
n "config_start"
t "std_logic"
o 2
suid 12,0
)
)
)
*261 (CptPort
uid 5773,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5774,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,101625,37750,102375"
)
tg (CPTG
uid 5775,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5776,0
va (VaSet
)
xt "30800,101500,36000,102500"
st "sensor_array"
ju 2
blo "36000,102300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sensor_array"
t "sensor_array_type"
o 9
suid 13,0
)
)
)
*262 (CptPort
uid 5777,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5778,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,100625,37750,101375"
)
tg (CPTG
uid 5779,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5780,0
va (VaSet
)
xt "30700,100500,36000,101500"
st "sensor_ready"
ju 2
blo "36000,101300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sensor_ready"
t "std_logic"
o 11
suid 14,0
)
)
)
*263 (CptPort
uid 5781,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5782,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "20250,104625,21000,105375"
)
tg (CPTG
uid 5783,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5784,0
va (VaSet
)
xt "22000,104500,24800,105500"
st "dac_cs"
blo "22000,105300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dac_cs"
t "std_logic"
o 6
suid 15,0
)
)
)
*264 (CptPort
uid 5785,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5786,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "20250,103625,21000,104375"
)
tg (CPTG
uid 5787,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5788,0
va (VaSet
)
xt "22000,103500,28500,104500"
st "sensor_cs : (3:0)"
blo "22000,104300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 10
suid 16,0
)
)
)
*265 (CptPort
uid 5789,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5790,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "20250,100625,21000,101375"
)
tg (CPTG
uid 5791,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5792,0
va (VaSet
)
xt "22000,100500,26200,101500"
st "clk_50MHz"
blo "22000,101300"
)
)
thePort (LogicalPort
decl (Decl
n "clk_50MHz"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 17,0
)
)
)
*266 (CptPort
uid 5986,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5987,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,105625,37750,106375"
)
tg (CPTG
uid 5988,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5989,0
va (VaSet
)
xt "30400,105500,36000,106500"
st "config_started"
ju 2
blo "36000,106300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_started"
t "std_logic"
o 5
suid 18,0
i "'0'"
)
)
)
*267 (CptPort
uid 6154,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6155,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "20250,108625,21000,109375"
)
tg (CPTG
uid 6156,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6157,0
va (VaSet
)
xt "22000,108500,24000,109500"
st "mosi"
blo "22000,109300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "mosi"
t "std_logic"
o 7
suid 19,0
i "'0'"
)
)
)
*268 (CptPort
uid 6317,0
ps "OnEdgeStrategy"
shape (Diamond
uid 6318,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "20250,107625,21000,108375"
)
tg (CPTG
uid 6319,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6320,0
va (VaSet
)
xt "22000,107500,24000,108500"
st "miso"
blo "22000,108300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "miso"
t "std_logic"
preAdd 0
posAdd 0
o 12
suid 20,0
)
)
)
]
shape (Rectangle
uid 5794,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "21000,100000,37000,112000"
)
oxt "15000,12000,30000,26000"
ttg (MlTextGroup
uid 5795,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*269 (Text
uid 5796,0
va (VaSet
font "Arial,8,1"
)
xt "21200,112000,27400,113000"
st "FACT_FAD_lib"
blo "21200,112800"
tm "BdLibraryNameMgr"
)
*270 (Text
uid 5797,0
va (VaSet
font "Arial,8,1"
)
xt "21200,113000,26700,114000"
st "spi_interface"
blo "21200,113800"
tm "CptNameMgr"
)
*271 (Text
uid 5798,0
va (VaSet
font "Arial,8,1"
)
xt "21200,114000,30000,115000"
st "I_main_SPI_interface"
blo "21200,114800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 5799,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 5800,0
text (MLText
uid 5801,0
va (VaSet
font "Courier New,8,0"
)
xt "6000,100000,6000,100000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 5802,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "21250,110250,22750,111750"
iconName "BlockDiagram.png"
iconMaskName "BlockDiagram.msk"
ftype 1
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*272 (Net
uid 5811,0
decl (Decl
n "sclk"
t "std_logic"
o 23
suid 151,0
)
declText (MLText
uid 5812,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,47000,-84500,47800"
st "sclk                   : std_logic
"
)
)
*273 (Net
uid 5819,0
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 30
suid 152,0
)
declText (MLText
uid 5820,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,54200,-84500,55000"
st "sio                    : std_logic
"
)
)
*274 (Net
uid 5827,0
decl (Decl
n "dac_cs"
t "std_logic"
o 17
suid 153,0
)
declText (MLText
uid 5828,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,40600,-84500,41400"
st "dac_cs                 : std_logic
"
)
)
*275 (Net
uid 5835,0
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 24
suid 154,0
)
declText (MLText
uid 5836,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,47800,-74500,48600"
st "sensor_cs              : std_logic_vector(3 DOWNTO 0)
"
)
)
*276 (PortIoOut
uid 5843,0
shape (CompositeShape
uid 5844,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 5845,0
sl 0
ro 90
xt "-20000,111625,-18500,112375"
)
(Line
uid 5846,0
sl 0
ro 90
xt "-18500,112000,-18000,112000"
pts [
"-18000,112000"
"-18500,112000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 5847,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5848,0
va (VaSet
)
xt "-22700,111500,-21000,112500"
st "sclk"
ju 2
blo "-21000,112300"
tm "WireNameMgr"
)
)
)
*277 (PortIoInOut
uid 5849,0
shape (CompositeShape
uid 5850,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
uid 5851,0
sl 0
ro 180
xt "10000,107625,11500,108375"
)
(Line
uid 5852,0
sl 0
ro 180
xt "11500,108000,12000,108000"
pts [
"12000,108000"
"11500,108000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 5853,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5854,0
va (VaSet
)
xt "7600,107500,9000,108500"
st "sio"
ju 2
blo "9000,108300"
tm "WireNameMgr"
)
)
)
*278 (PortIoOut
uid 5855,0
shape (CompositeShape
uid 5856,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 5857,0
sl 0
ro 90
xt "10000,104625,11500,105375"
)
(Line
uid 5858,0
sl 0
ro 90
xt "11500,105000,12000,105000"
pts [
"12000,105000"
"11500,105000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 5859,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5860,0
va (VaSet
)
xt "6200,104500,9000,105500"
st "dac_cs"
ju 2
blo "9000,105300"
tm "WireNameMgr"
)
)
)
*279 (PortIoOut
uid 5861,0
shape (CompositeShape
uid 5862,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 5863,0
sl 0
ro 90
xt "10000,103625,11500,104375"
)
(Line
uid 5864,0
sl 0
ro 90
xt "11500,104000,12000,104000"
pts [
"12000,104000"
"11500,104000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 5865,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5866,0
va (VaSet
)
xt "5100,103500,9000,104500"
st "sensor_cs"
ju 2
blo "9000,104300"
tm "WireNameMgr"
)
)
)
*280 (Net
uid 5948,0
decl (Decl
n "new_config"
t "std_logic"
o 60
suid 155,0
i "'0'"
)
declText (MLText
uid 5949,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,83400,-59500,84200"
st "SIGNAL new_config             : std_logic                                    := '0'
"
)
)
*281 (Net
uid 5960,0
decl (Decl
n "config_started"
t "std_logic"
o 47
suid 156,0
)
declText (MLText
uid 5961,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,70600,-80500,71400"
st "SIGNAL config_started         : std_logic
"
)
)
*282 (Net
uid 6012,0
decl (Decl
n "config_started_spi"
t "std_logic"
o 50
suid 159,0
i "'0'"
)
declText (MLText
uid 6013,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,73000,-59500,73800"
st "SIGNAL config_started_spi     : std_logic                                    := '0'
"
)
)
*283 (Net
uid 6014,0
decl (Decl
n "config_started_cu"
t "std_logic"
o 48
suid 160,0
i "'0'"
)
declText (MLText
uid 6015,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,71400,-59500,72200"
st "SIGNAL config_started_cu      : std_logic                                    := '0'
"
)
)
*284 (Net
uid 6016,0
decl (Decl
n "config_started_mm"
t "std_logic"
o 49
suid 161,0
)
declText (MLText
uid 6017,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,72200,-80500,73000"
st "SIGNAL config_started_mm      : std_logic
"
)
)
*285 (Net
uid 6158,0
decl (Decl
n "mosi"
t "std_logic"
o 22
suid 162,0
i "'0'"
)
declText (MLText
uid 6159,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,44600,-63000,45400"
st "mosi                   : std_logic                                    := '0'
"
)
)
*286 (PortIoOut
uid 6166,0
shape (CompositeShape
uid 6167,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 6168,0
sl 0
ro 90
xt "10000,108625,11500,109375"
)
(Line
uid 6169,0
sl 0
ro 90
xt "11500,109000,12000,109000"
pts [
"12000,109000"
"11500,109000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 6170,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6171,0
va (VaSet
)
xt "7000,108500,9000,109500"
st "mosi"
ju 2
blo "9000,109300"
tm "WireNameMgr"
)
)
)
*287 (Net
uid 6360,0
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 18
suid 166,0
i "'0'"
)
declText (MLText
uid 6361,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,41400,-49500,42200"
st "denable                : std_logic                                    := '0' -- default domino wave off
"
)
)
*288 (PortIoOut
uid 6368,0
shape (CompositeShape
uid 6369,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 6370,0
sl 0
ro 270
xt "153500,74625,155000,75375"
)
(Line
uid 6371,0
sl 0
ro 270
xt "153000,75000,153500,75000"
pts [
"153000,75000"
"153500,75000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 6372,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6373,0
va (VaSet
)
xt "156000,74500,159000,75500"
st "denable"
blo "156000,75300"
tm "WireNameMgr"
)
)
)
*289 (Net
uid 6450,0
decl (Decl
n "dwrite_enable"
t "std_logic"
o 59
suid 167,0
i "'1'"
)
declText (MLText
uid 6451,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,82600,-59500,83400"
st "SIGNAL dwrite_enable          : std_logic                                    := '1'
"
)
)
*290 (MWC
uid 6529,0
optionalChildren [
*291 (CptPort
uid 6501,0
optionalChildren [
*292 (Line
uid 6505,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "1000,60000,2000,60000"
pts [
"1000,60000"
"2000,60000"
]
)
*293 (Property
uid 6506,0
pclass "_MW_GEOM_"
pname "fixed"
ptn "String"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 6502,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "250,59625,1000,60375"
)
tg (CPTG
uid 6503,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6504,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "21669,299342,23469,300342"
st "dout"
blo "21669,300142"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dout"
t "std_logic"
o 20
suid 1,0
i "'1'"
)
)
)
*294 (CptPort
uid 6507,0
optionalChildren [
*295 (Line
uid 6511,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "6000,59000,7000,59000"
pts [
"7000,59000"
"6000,59000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 6508,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "7000,58625,7750,59375"
)
tg (CPTG
uid 6509,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6510,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "24635,298294,26435,299294"
st "din0"
ju 2
blo "26435,299094"
)
)
thePort (LogicalPort
decl (Decl
n "din0"
t "std_logic"
o 58
suid 2,0
i "'1'"
)
)
)
*296 (CptPort
uid 6512,0
optionalChildren [
*297 (Line
uid 6516,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "6000,61000,7000,61000"
pts [
"7000,61000"
"6000,61000"
]
)
]
ps "OnEdgeStrategy"
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n "drs_channel_internal"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 84
suid 187,0
i "(others => '0')"
)
declText (MLText
uid 8584,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,77800,-53500,78600"
st "SIGNAL drs_channel_internal   : std_logic_vector(3 DOWNTO 0)                 := (others => '0')
"
)
)
*345 (MWC
uid 8721,0
optionalChildren [
*346 (CptPort
uid 8693,0
optionalChildren [
*347 (Line
uid 8697,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-13000,112000,-12000,112000"
pts [
"-13000,112000"
"-12000,112000"
]
)
*348 (Property
uid 8698,0
pclass "_MW_GEOM_"
pname "fixed"
ptn "String"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 8694,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-13750,111625,-13000,112375"
)
tg (CPTG
uid 8695,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8696,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-14331,341342,-12531,342342"
st "dout"
blo "-14331,342142"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dout"
t "std_logic"
o 23
suid 1,0
)
)
)
*349 (CptPort
uid 8699,0
optionalChildren [
*350 (Line
uid 8703,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-7999,113000,-7000,113000"
pts [
"-7000,113000"
"-7999,113000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 8700,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-7000,112625,-6250,113375"
)
tg (CPTG
uid 8701,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8702,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-11365,342294,-9565,343294"
st "din0"
ju 2
blo "-9565,343094"
)
)
thePort (LogicalPort
decl (Decl
n "din0"
t "std_logic"
o 86
suid 2,0
)
)
)
*351 (CptPort
uid 8704,0
optionalChildren [
*352 (Line
uid 8708,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-8000,111000,-7000,111000"
pts [
"-7000,111000"
"-8000,111000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 8705,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-7000,110625,-6250,111375"
)
tg (CPTG
uid 8706,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8707,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-11250,340700,-9450,341700"
st "din1"
ju 2
blo "-9450,341500"
)
)
thePort (LogicalPort
decl (Decl
n "din1"
t "std_logic"
o 85
suid 3,0
)
)
)
*353 (CommentGraphic
uid 8709,0
optionalChildren [
*354 (Property
uid 8711,0
pclass "_MW_GEOM_"
pname "expand"
ptn "String"
)
]
shape (PolyLine2D
pts [
"-8000,110000"
"-8000,110000"
]
uid 8710,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "-8000,110000,-8000,110000"
)
oxt "11000,6000,11000,6000"
)
*355 (CommentGraphic
uid 8712,0
optionalChildren [
*356 (Property
uid 8714,0
pclass "_MW_GEOM_"
pname "expand"
ptn "String"
)
]
shape (PolyLine2D
pts [
"-8000,114000"
"-8000,114000"
]
uid 8713,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "-8000,114000,-8000,114000"
)
oxt "11000,10000,11000,10000"
)
*357 (Grouping
uid 8715,0
optionalChildren [
*358 (CommentGraphic
uid 8717,0
shape (PolyLine2D
pts [
"-10000,110000"
"-8000,110000"
"-8000,114000"
"-10000,114000"
]
uid 8718,0
layer 0
sl 0
va (VaSet
vasetType 1
fg "0,65535,65535"
lineColor "26368,26368,26368"
)
xt "-10000,110000,-8000,114000"
)
oxt "9000,6000,11000,10000"
)
*359 (CommentGraphic
uid 8719,0
shape (Arc2D
pts [
"-10000,114000"
"-12000,112000"
"-10000,110000"
]
uid 8720,0
layer 0
sl 0
va (VaSet
vasetType 1
fg "0,65535,65535"
lineColor "26368,26368,26368"
)
xt "-12000,110000,-10000,114000"
)
oxt "7000,6000,9000,10000"
)
]
shape (GroupingShape
uid 8716,0
sl 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "-12000,110000,-8000,114000"
)
oxt "7000,6000,11000,10000"
)
]
shape (Rectangle
uid 8722,0
va (VaSet
vasetType 1
transparent 1
fg "65535,65535,65535"
lineWidth -1
)
xt "-13000,110000,-7000,114000"
fos 1
)
showPorts 0
oxt "6000,6000,12000,10000"
ttg (MlTextGroup
uid 8723,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*360 (Text
uid 8724,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-11500,112500,-6700,113500"
st "moduleware"
blo "-11500,113300"
)
*361 (Text
uid 8725,0
va (VaSet
font "arial,8,0"
)
xt "-11500,113500,-9900,114500"
st "and"
blo "-11500,114300"
)
*362 (Text
uid 8726,0
va (VaSet
font "arial,8,0"
)
xt "-11500,114500,-9700,115500"
st "U_1"
blo "-11500,115300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 8727,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 8728,0
text (MLText
uid 8729,0
va (VaSet
font "arial,8,0"
)
xt "-28000,101000,-28000,101000"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
de 1
visOptions (mwParamsVisibilityOptions
)
)
*363 (Net
uid 8730,0
decl (Decl
n "sclk1"
t "std_logic"
o 85
suid 191,0
)
declText (MLText
uid 8731,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,93800,-80500,94600"
st "SIGNAL sclk1                  : std_logic
"
)
)
*364 (Net
uid 8746,0
decl (Decl
n "sclk_enable"
t "std_logic"
o 86
suid 194,0
)
declText (MLText
uid 8747,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,94600,-80500,95400"
st "SIGNAL sclk_enable            : std_logic
"
)
)
*365 (Net
uid 9004,0
decl (Decl
n "adc_clk_en"
t "std_logic"
o 87
suid 195,0
i "'0'"
)
declText (MLText
uid 9005,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,39000,-63000,39800"
st "adc_clk_en             : std_logic                                    := '0'
"
)
)
*366 (PortIoOut
uid 9012,0
shape (CompositeShape
uid 9013,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 9014,0
sl 0
ro 90
xt "-28000,82625,-26500,83375"
)
(Line
uid 9015,0
sl 0
ro 90
xt "-26500,83000,-26000,83000"
pts [
"-26000,83000"
"-26500,83000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 9016,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9017,0
va (VaSet
)
xt "-33500,82500,-29000,83500"
st "adc_clk_en"
ju 2
blo "-29000,83300"
tm "WireNameMgr"
)
)
)
*367 (SaComponent
uid 9175,0
optionalChildren [
*368 (CptPort
uid 9120,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9121,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-2000,18625,-1250,19375"
)
tg (CPTG
uid 9122,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9123,0
va (VaSet
font "arial,8,0"
)
xt "-6100,18500,-3000,19500"
st "CLK_50"
ju 2
blo "-3000,19300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_50"
t "std_logic"
o 7
suid 2,0
)
)
)
*369 (CptPort
uid 9124,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9125,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-2000,19625,-1250,20375"
)
tg (CPTG
uid 9126,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9127,0
va (VaSet
font "arial,8,0"
)
xt "-6100,19500,-3000,20500"
st "CLK_25"
ju 2
blo "-3000,20300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_25"
t "std_logic"
o 5
suid 3,0
)
)
)
*370 (CptPort
uid 9128,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9129,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-20750,18625,-20000,19375"
)
tg (CPTG
uid 9130,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9131,0
va (VaSet
font "arial,8,0"
)
xt "-19000,18500,-17100,19500"
st "CLK"
blo "-19000,19300"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 6,0
)
)
)
*371 (CptPort
uid 9132,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9133,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-2000,2625,-1250,3375"
)
tg (CPTG
uid 9134,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9135,0
va (VaSet
font "arial,8,0"
)
xt "-5200,2500,-3000,3500"
st "ready"
ju 2
blo "-3000,3300"
)
t (Text
uid 9136,0
va (VaSet
font "arial,8,0"
)
xt "-4200,3500,-3000,4500"
st "'0'"
ju 2
blo "-3000,4300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ready"
t "std_logic"
preAdd 0
posAdd 0
o 15
suid 14,0
i "'0'"
)
)
)
*372 (CptPort
uid 9137,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9138,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-2000,4625,-1250,5375"
)
tg (CPTG
uid 9139,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9140,0
va (VaSet
font "arial,8,0"
)
xt "-5900,4500,-3000,5500"
st "shifting"
ju 2
blo "-3000,5300"
)
t (Text
uid 9141,0
va (VaSet
font "arial,8,0"
)
xt "-4200,5500,-3000,6500"
st "'0'"
ju 2
blo "-3000,6300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "shifting"
t "std_logic"
prec "-- status:"
preAdd 0
posAdd 0
o 16
suid 15,0
i "'0'"
)
)
)
*373 (CptPort
uid 9142,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9143,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-2000,6625,-1250,7375"
)
tg (CPTG
uid 9144,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9145,0
va (VaSet
font "arial,8,0"
)
xt "-7800,6500,-3000,7500"
st "offset : (7:0)"
ju 2
blo "-3000,7300"
)
t (Text
uid 9146,0
va (VaSet
font "arial,8,0"
)
xt "-9900,7500,-3000,8500"
st "(OTHERS => '0')"
ju 2
blo "-3000,8300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "offset"
t "std_logic_vector"
b "(7 downto 0)"
preAdd 0
posAdd 0
o 14
suid 16,0
i "(OTHERS => '0')"
)
)
)
*374 (CptPort
uid 9147,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9148,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-2000,9625,-1250,10375"
)
tg (CPTG
uid 9149,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9150,0
va (VaSet
font "arial,8,0"
)
xt "-8200,9500,-3000,10500"
st "DCM_locked"
ju 2
blo "-3000,10300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "DCM_locked"
t "std_logic"
preAdd 0
posAdd 0
o 8
suid 17,0
)
)
)
*375 (CptPort
uid 9155,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9156,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-2000,11625,-1250,12375"
)
tg (CPTG
uid 9157,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9158,0
va (VaSet
font "arial,8,0"
)
xt "-8000,11500,-3000,12500"
st "PSCLK_OUT"
ju 2
blo "-3000,12300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "PSCLK_OUT"
t "std_logic"
o 10
suid 19,0
)
)
)
*376 (CptPort
uid 9159,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9160,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-2000,12625,-1250,13375"
)
tg (CPTG
uid 9161,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9162,0
va (VaSet
font "arial,8,0"
)
xt "-7600,12500,-3000,13500"
st "PSEN_OUT"
ju 2
blo "-3000,13300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "PSEN_OUT"
t "std_logic"
o 12
suid 20,0
)
)
)
*377 (CptPort
uid 9163,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9164,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-2000,13625,-1250,14375"
)
tg (CPTG
uid 9165,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9166,0
va (VaSet
font "arial,8,0"
)
xt "-10000,13500,-3000,14500"
st "PSINCDEC_OUT"
ju 2
blo "-3000,14300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "PSINCDEC_OUT"
t "std_logic"
o 13
suid 21,0
)
)
)
*378 (CptPort
uid 9167,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9168,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-2000,14625,-1250,15375"
)
tg (CPTG
uid 9169,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9170,0
va (VaSet
font "arial,8,0"
)
xt "-10800,14500,-3000,15500"
st "PSDONE_extraOUT"
ju 2
blo "-3000,15300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "PSDONE_extraOUT"
t "std_logic"
o 11
suid 22,0
)
)
)
*379 (CptPort
uid 9171,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9172,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-2000,15625,-1250,16375"
)
tg (CPTG
uid 9173,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9174,0
va (VaSet
font "arial,8,0"
)
xt "-10700,15500,-3000,16500"
st "LOCKED_extraOUT"
ju 2
blo "-3000,16300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "LOCKED_extraOUT"
t "std_logic"
o 9
suid 23,0
)
)
)
*380 (CptPort
uid 9211,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9212,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-2000,20625,-1250,21375"
)
tg (CPTG
uid 9213,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9214,0
va (VaSet
font "arial,8,0"
)
xt "-7500,20500,-3000,21500"
st "CLK_25_PS"
ju 2
blo "-3000,21300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 6
suid 24,0
)
)
)
*381 (CptPort
uid 9215,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9216,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-20750,11625,-20000,12375"
)
tg (CPTG
uid 9217,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9218,0
va (VaSet
font "arial,8,0"
)
xt "-19000,11500,-15700,12500"
st "direction"
blo "-19000,12300"
)
)
thePort (LogicalPort
decl (Decl
n "direction"
t "std_logic"
o 3
suid 26,0
)
)
)
*382 (CptPort
uid 9219,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9220,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-20750,12625,-20000,13375"
)
tg (CPTG
uid 9221,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9222,0
va (VaSet
font "arial,8,0"
)
xt "-19000,12500,-16000,13500"
st "do_shift"
blo "-19000,13300"
)
)
thePort (LogicalPort
decl (Decl
n "do_shift"
t "std_logic"
o 4
suid 25,0
)
)
)
*383 (CptPort
uid 10030,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10031,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-20750,20625,-20000,21375"
)
tg (CPTG
uid 10032,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10033,0
va (VaSet
font "arial,8,0"
)
xt "-19000,20500,-15800,21500"
st "RST_IN"
blo "-19000,21300"
)
)
thePort (LogicalPort
decl (Decl
n "RST_IN"
t "std_logic"
o 2
suid 27,0
)
)
)
]
shape (Rectangle
uid 9176,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-20000,1000,-2000,23000"
)
oxt "28000,10000,46000,33000"
ttg (MlTextGroup
uid 9177,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*384 (Text
uid 9178,0
va (VaSet
font "arial,8,1"
)
xt "-18800,6000,-12600,7000"
st "FACT_FAD_lib"
blo "-18800,6800"
tm "BdLibraryNameMgr"
)
*385 (Text
uid 9179,0
va (VaSet
font "arial,8,1"
)
xt "-18800,7000,-8800,8000"
st "clock_generator_var_ps"
blo "-18800,7800"
tm "CptNameMgr"
)
*386 (Text
uid 9180,0
va (VaSet
font "arial,8,1"
)
xt "-18800,8000,-17000,9000"
st "U_2"
blo "-18800,8800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 9181,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 9182,0
text (MLText
uid 9183,0
va (VaSet
font "Courier New,8,0"
)
xt "-35000,3000,-35000,3000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 9184,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-19750,21250,-18250,22750"
iconName "BlockDiagram.png"
iconMaskName "BlockDiagram.msk"
ftype 1
)
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*387 (Net
uid 9231,0
decl (Decl
n "ps_direction"
t "std_logic"
eolc "-- default phase shift upwards"
posAdd 0
o 88
suid 196,0
i "'1'"
)
declText (MLText
uid 9232,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,85000,-44000,85800"
st "SIGNAL ps_direction           : std_logic                                    := '1' -- default phase shift upwards
"
)
)
*388 (Net
uid 9239,0
decl (Decl
n "ps_do_phase_shift"
t "std_logic"
eolc "--pulse this to phase shift once"
preAdd 0
posAdd 0
o 89
suid 197,0
i "'0'"
)
declText (MLText
uid 9240,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,85800,-43000,86600"
st "SIGNAL ps_do_phase_shift      : std_logic                                    := '0' --pulse this to phase shift once
"
)
)
*389 (Net
uid 9267,0
decl (Decl
n "LOCKED_extraOUT"
t "std_logic"
o 90
suid 200,0
)
declText (MLText
uid 9268,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,31800,-84500,32600"
st "LOCKED_extraOUT        : std_logic
"
)
)
*390 (PortIoOut
uid 9275,0
shape (CompositeShape
uid 9276,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 9277,0
sl 0
ro 270
xt "8500,15625,10000,16375"
)
(Line
uid 9278,0
sl 0
ro 270
xt "8000,16000,8500,16000"
pts [
"8000,16000"
"8500,16000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 9279,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9280,0
va (VaSet
)
xt "11000,15500,18700,16500"
st "LOCKED_extraOUT"
blo "11000,16300"
tm "WireNameMgr"
)
)
)
*391 (Net
uid 9281,0
decl (Decl
n "PSDONE_extraOUT"
t "std_logic"
o 91
suid 201,0
)
declText (MLText
uid 9282,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,33400,-84500,34200"
st "PSDONE_extraOUT        : std_logic
"
)
)
*392 (PortIoOut
uid 9289,0
shape (CompositeShape
uid 9290,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 9291,0
sl 0
ro 270
xt "8500,14625,10000,15375"
)
(Line
uid 9292,0
sl 0
ro 270
xt "8000,15000,8500,15000"
pts [
"8000,15000"
"8500,15000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 9293,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9294,0
va (VaSet
)
xt "11000,14500,18800,15500"
st "PSDONE_extraOUT"
blo "11000,15300"
tm "WireNameMgr"
)
)
)
*393 (Net
uid 9295,0
decl (Decl
n "PSINCDEC_OUT"
t "std_logic"
o 92
suid 202,0
)
declText (MLText
uid 9296,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,35000,-84500,35800"
st "PSINCDEC_OUT           : std_logic
"
)
)
*394 (PortIoOut
uid 9303,0
shape (CompositeShape
uid 9304,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 9305,0
sl 0
ro 270
xt "8500,13625,10000,14375"
)
(Line
uid 9306,0
sl 0
ro 270
xt "8000,14000,8500,14000"
pts [
"8000,14000"
"8500,14000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 9307,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9308,0
va (VaSet
)
xt "11000,13500,18000,14500"
st "PSINCDEC_OUT"
blo "11000,14300"
tm "WireNameMgr"
)
)
)
*395 (Net
uid 9309,0
decl (Decl
n "PSEN_OUT"
t "std_logic"
o 93
suid 203,0
)
declText (MLText
uid 9310,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,34200,-84500,35000"
st "PSEN_OUT               : std_logic
"
)
)
*396 (PortIoOut
uid 9317,0
shape (CompositeShape
uid 9318,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 9319,0
sl 0
ro 270
xt "8500,12625,10000,13375"
)
(Line
uid 9320,0
sl 0
ro 270
xt "8000,13000,8500,13000"
pts [
"8000,13000"
"8500,13000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 9321,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9322,0
va (VaSet
)
xt "11000,12500,15600,13500"
st "PSEN_OUT"
blo "11000,13300"
tm "WireNameMgr"
)
)
)
*397 (Net
uid 9323,0
decl (Decl
n "PSCLK_OUT"
t "std_logic"
o 94
suid 204,0
)
declText (MLText
uid 9324,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,32600,-84500,33400"
st "PSCLK_OUT              : std_logic
"
)
)
*398 (PortIoOut
uid 9331,0
shape (CompositeShape
uid 9332,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 9333,0
sl 0
ro 270
xt "8500,11625,10000,12375"
)
(Line
uid 9334,0
sl 0
ro 270
xt "8000,12000,8500,12000"
pts [
"8000,12000"
"8500,12000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 9335,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9336,0
va (VaSet
)
xt "11000,11500,16000,12500"
st "PSCLK_OUT"
blo "11000,12300"
tm "WireNameMgr"
)
)
)
*399 (Net
uid 9351,0
decl (Decl
n "DCM_locked"
t "std_logic"
preAdd 0
posAdd 0
o 96
suid 206,0
)
declText (MLText
uid 9352,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,31000,-84500,31800"
st "DCM_locked             : std_logic
"
)
)
*400 (PortIoOut
uid 9359,0
shape (CompositeShape
uid 9360,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 9361,0
sl 0
ro 270
xt "8500,9625,10000,10375"
)
(Line
uid 9362,0
sl 0
ro 270
xt "8000,10000,8500,10000"
pts [
"8000,10000"
"8500,10000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 9363,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9364,0
va (VaSet
)
xt "11000,9500,16200,10500"
st "DCM_locked"
blo "11000,10300"
tm "WireNameMgr"
)
)
)
*401 (Net
uid 9365,0
decl (Decl
n "offset"
t "std_logic_vector"
b "(7 downto 0)"
preAdd 0
posAdd 0
o 97
suid 207,0
i "(OTHERS => '0')"
)
declText (MLText
uid 9366,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,45400,-57000,46200"
st "offset                 : std_logic_vector(7 downto 0)                 := (OTHERS => '0')
"
)
)
*402 (PortIoOut
uid 9374,0
shape (CompositeShape
uid 9375,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 9376,0
sl 0
ro 270
xt "8500,6625,10000,7375"
)
(Line
uid 9377,0
sl 0
ro 270
xt "8000,7000,8500,7000"
pts [
"8000,7000"
"8500,7000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 9378,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9379,0
va (VaSet
)
xt "11000,6500,13200,7500"
st "offset"
blo "11000,7300"
tm "WireNameMgr"
)
)
)
*403 (Net
uid 9380,0
decl (Decl
n "shifting"
t "std_logic"
prec "-- status:"
preAdd 0
posAdd 0
o 98
suid 208,0
i "'0'"
)
declText (MLText
uid 9381,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,48600,-63000,50200"
st "-- status:
shifting               : std_logic                                    := '0'
"
)
)
*404 (PortIoOut
uid 9389,0
shape (CompositeShape
uid 9390,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 9391,0
sl 0
ro 270
xt "8500,4625,10000,5375"
)
(Line
uid 9392,0
sl 0
ro 270
xt "8000,5000,8500,5000"
pts [
"8000,5000"
"8500,5000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 9393,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9394,0
va (VaSet
)
xt "11000,4500,13900,5500"
st "shifting"
blo "11000,5300"
tm "WireNameMgr"
)
)
)
*405 (Net
uid 9395,0
decl (Decl
n "ready"
t "std_logic"
preAdd 0
posAdd 0
o 99
suid 209,0
i "'0'"
)
declText (MLText
uid 9396,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,46200,-63000,47000"
st "ready                  : std_logic                                    := '0'
"
)
)
*406 (PortIoOut
uid 9404,0
shape (CompositeShape
uid 9405,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 9406,0
sl 0
ro 270
xt "8500,2625,10000,3375"
)
(Line
uid 9407,0
sl 0
ro 270
xt "8000,3000,8500,3000"
pts [
"8000,3000"
"8500,3000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 9408,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9409,0
va (VaSet
)
xt "11000,2500,13200,3500"
st "ready"
blo "11000,3300"
tm "WireNameMgr"
)
)
)
*407 (MWC
uid 9430,0
optionalChildren [
*408 (CptPort
uid 9410,0
optionalChildren [
*409 (Line
uid 9414,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-3000,-12000,-2999,-12000"
pts [
"-3000,-12000"
"-2999,-12000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 9411,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-3750,-12375,-3000,-11625"
)
tg (CPTG
uid 9412,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9413,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-27800,-33500,-27000,-32500"
st "s"
blo "-27800,-32700"
)
s (Text
uid 9439,0
sl 0
va (VaSet
font "arial,8,0"
)
xt "-27800,-32500,-27800,-32500"
blo "-27800,-32500"
)
)
thePort (LogicalPort
decl (Decl
n "s"
t "std_logic"
eolc "--pulse this to phase shift once"
preAdd 0
posAdd 0
o 89
suid 1,0
i "'0'"
)
)
)
*410 (CptPort
uid 9415,0
optionalChildren [
*411 (Line
uid 9419,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "0,-12000,0,-12000"
pts [
"0,-12000"
"0,-12000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 9416,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "0,-12375,750,-11625"
)
tg (CPTG
uid 9417,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9418,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-30000,-34500,-29400,-33500"
st "t"
ju 2
blo "-29400,-33700"
)
s (Text
uid 9440,0
sl 0
va (VaSet
font "arial,8,0"
)
xt "-29400,-33500,-29400,-33500"
ju 2
blo "-29400,-33500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "t"
t "std_logic"
o 100
suid 2,0
)
)
)
*412 (CommentGraphic
uid 9420,0
shape (PolyLine2D
pts [
"-3000,-12000"
"-2000,-13000"
]
uid 9421,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "-3000,-13000,-2000,-12000"
)
oxt "6000,6000,7000,7000"
)
*413 (CommentGraphic
uid 9422,0
shape (PolyLine2D
pts [
"-3000,-12000"
"-2000,-11000"
]
uid 9423,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "-3000,-12000,-2000,-11000"
)
oxt "6000,7000,7000,8000"
)
*414 (CommentGraphic
uid 9424,0
shape (PolyLine2D
pts [
"-2012,-11671"
"-1012,-11671"
]
uid 9425,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "-2012,-11671,-1012,-11671"
)
oxt "6988,7329,7988,7329"
)
*415 (CommentGraphic
uid 9426,0
shape (PolyLine2D
pts [
"-1000,-12000"
"0,-12000"
]
uid 9427,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "-1000,-12000,0,-12000"
)
oxt "8000,7000,9000,7000"
)
*416 (CommentGraphic
uid 9428,0
shape (PolyLine2D
pts [
"-2024,-12270"
"-1024,-12270"
]
uid 9429,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "-2024,-12270,-1024,-12270"
)
oxt "6976,6730,7976,6730"
)
]
shape (Rectangle
uid 9431,0
va (VaSet
vasetType 1
transparent 1
fg "0,65535,0"
lineColor "65535,65535,65535"
lineWidth -1
)
xt "-3000,-13000,0,-11000"
fos 1
)
showPorts 0
oxt "6000,6000,9000,8000"
ttg (MlTextGroup
uid 9432,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*417 (Text
uid 9433,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-2650,-11900,2150,-10900"
st "moduleware"
blo "-2650,-11100"
)
*418 (Text
uid 9434,0
va (VaSet
font "arial,8,0"
)
xt "-2650,-10900,2050,-9900"
st "assignment"
blo "-2650,-10100"
)
*419 (Text
uid 9435,0
va (VaSet
font "arial,8,0"
)
xt "-2650,-9900,-850,-8900"
st "U_3"
blo "-2650,-9100"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 9436,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 9437,0
text (MLText
uid 9438,0
va (VaSet
font "arial,8,0"
)
xt "-8000,-32600,-8000,-32600"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
*420 (MWC
uid 9472,0
optionalChildren [
*421 (CptPort
uid 9481,0
optionalChildren [
*422 (Line
uid 9486,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-3000,-8000,-2999,-8000"
pts [
"-3000,-8000"
"-2999,-8000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 9482,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-3750,-8375,-3000,-7625"
)
tg (CPTG
uid 9483,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9484,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-27800,-29500,-27000,-28500"
st "s"
blo "-27800,-28700"
)
s (Text
uid 9485,0
sl 0
va (VaSet
font "arial,8,0"
)
xt "-27800,-28500,-27800,-28500"
blo "-27800,-28500"
)
)
thePort (LogicalPort
decl (Decl
n "s"
t "std_logic"
eolc "-- default phase shift upwards"
posAdd 0
o 88
i "'1'"
)
)
)
*423 (CptPort
uid 9487,0
optionalChildren [
*424 (Line
uid 9492,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "0,-8000,0,-8000"
pts [
"0,-8000"
"0,-8000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 9488,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "0,-8375,750,-7625"
)
tg (CPTG
uid 9489,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9490,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-30000,-30500,-29400,-29500"
st "t"
ju 2
blo "-29400,-29700"
)
s (Text
uid 9491,0
sl 0
va (VaSet
font "arial,8,0"
)
xt "-29400,-29500,-29400,-29500"
ju 2
blo "-29400,-29500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "t"
t "std_logic"
o 101
)
)
)
*425 (CommentGraphic
uid 9493,0
shape (PolyLine2D
pts [
"-3000,-8000"
"-2000,-9000"
]
uid 9494,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "-3000,-9000,-2000,-8000"
)
oxt "6000,6000,7000,7000"
)
*426 (CommentGraphic
uid 9495,0
shape (PolyLine2D
pts [
"-3000,-8000"
"-2000,-7000"
]
uid 9496,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "-3000,-8000,-2000,-7000"
)
oxt "6000,7000,7000,8000"
)
*427 (CommentGraphic
uid 9497,0
shape (PolyLine2D
pts [
"-2012,-7671"
"-1012,-7671"
]
uid 9498,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "-2012,-7671,-1012,-7671"
)
oxt "6988,7329,7988,7329"
)
*428 (CommentGraphic
uid 9499,0
shape (PolyLine2D
pts [
"-1000,-8000"
"0,-8000"
]
uid 9500,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "-1000,-8000,0,-8000"
)
oxt "8000,7000,9000,7000"
)
*429 (CommentGraphic
uid 9501,0
shape (PolyLine2D
pts [
"-2024,-8270"
"-1024,-8270"
]
uid 9502,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "-2024,-8270,-1024,-8270"
)
oxt "6976,6730,7976,6730"
)
]
shape (Rectangle
uid 9473,0
va (VaSet
vasetType 1
transparent 1
fg "0,65535,0"
lineColor "65535,65535,65535"
lineWidth -1
)
xt "-3000,-9000,0,-7000"
fos 1
)
showPorts 0
oxt "6000,6000,9000,8000"
ttg (MlTextGroup
uid 9474,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*430 (Text
uid 9475,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-2650,-7900,2150,-6900"
st "moduleware"
blo "-2650,-7100"
)
*431 (Text
uid 9476,0
va (VaSet
font "arial,8,0"
)
xt "-2650,-6900,2050,-5900"
st "assignment"
blo "-2650,-6100"
)
*432 (Text
uid 9477,0
va (VaSet
font "arial,8,0"
)
xt "-2650,-5900,-850,-4900"
st "U_5"
blo "-2650,-5100"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 9478,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 9479,0
text (MLText
uid 9480,0
va (VaSet
font "arial,8,0"
)
xt "-8000,-28600,-8000,-28600"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
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visOptions (mwParamsVisibilityOptions
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va (VaSet
)
xt "37000,8500,43200,9500"
st "CLK25_PSOUT"
blo "37000,9300"
tm "WireNameMgr"
)
)
)
*481 (Net
uid 9799,0
decl (Decl
n "CLK25_PSOUT"
t "std_logic"
o 104
suid 220,0
)
declText (MLText
uid 9800,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,27800,-84500,28600"
st "CLK25_PSOUT            : std_logic
"
)
)
*482 (Net
uid 9941,0
decl (Decl
n "ps_reset"
t "std_logic"
eolc "-- pulse this to reset the variable phase shift"
posAdd 0
o 104
suid 221,0
i "'0'"
)
declText (MLText
uid 9942,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,86600,-35500,87400"
st "SIGNAL ps_reset               : std_logic                                    := '0' -- pulse this to reset the variable phase shift
"
)
)
*483 (Net
uid 9949,0
decl (Decl
n "srclk_enable"
t "std_logic"
o 105
suid 222,0
i "'0'"
)
declText (MLText
uid 9950,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,97000,-59500,97800"
st "SIGNAL srclk_enable           : std_logic                                    := '0'
"
)
)
*484 (MWC
uid 9957,0
optionalChildren [
*485 (CptPort
uid 9966,0
optionalChildren [
*486 (Line
uid 9970,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-32000,54000,-31000,54000"
pts [
"-32000,54000"
"-31000,54000"
]
)
*487 (Property
uid 9971,0
pclass "_MW_GEOM_"
pname "fixed"
ptn "String"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 9967,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-32750,53625,-32000,54375"
)
tg (CPTG
uid 9968,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9969,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-11331,293342,-9531,294342"
st "dout"
blo "-11331,294142"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dout"
t "std_logic"
o 15
i "'0'"
)
)
)
*488 (CptPort
uid 9972,0
optionalChildren [
*489 (Line
uid 9976,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-26999,53000,-26000,53000"
pts [
"-26000,53000"
"-26999,53000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 9973,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-26000,52625,-25250,53375"
)
tg (CPTG
uid 9974,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9975,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-8365,292294,-6565,293294"
st "din0"
ju 2
blo "-6565,293094"
)
)
thePort (LogicalPort
decl (Decl
n "din0"
t "std_logic"
o 106
i "'0'"
)
)
)
*490 (CptPort
uid 9977,0
optionalChildren [
*491 (Line
uid 9981,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-27000,55000,-26000,55000"
pts [
"-26000,55000"
"-27000,55000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 9978,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-26000,54625,-25250,55375"
)
tg (CPTG
uid 9979,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9980,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-8250,294700,-6450,295700"
st "din1"
ju 2
blo "-6450,295500"
)
)
thePort (LogicalPort
decl (Decl
n "din1"
t "std_logic"
o 105
i "'0'"
)
)
)
*492 (CommentGraphic
uid 9982,0
optionalChildren [
*493 (Property
uid 9984,0
pclass "_MW_GEOM_"
pname "expand"
ptn "String"
)
]
shape (PolyLine2D
pts [
"-27000,56000"
"-27000,56000"
]
uid 9983,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "-27000,56000,-27000,56000"
)
oxt "11000,10000,11000,10000"
)
*494 (CommentGraphic
uid 9985,0
optionalChildren [
*495 (Property
uid 9987,0
pclass "_MW_GEOM_"
pname "expand"
ptn "String"
)
]
shape (PolyLine2D
pts [
"-27000,52000"
"-27000,52000"
]
uid 9986,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "-27000,52000,-27000,52000"
)
oxt "11000,6000,11000,6000"
)
*496 (Grouping
uid 9988,0
optionalChildren [
*497 (CommentGraphic
uid 9990,0
shape (PolyLine2D
pts [
"-29000,52000"
"-27000,52000"
"-27000,56000"
"-29000,56000"
]
uid 9991,0
layer 0
sl 0
va (VaSet
vasetType 1
fg "0,65535,65535"
lineColor "26368,26368,26368"
)
xt "-29000,52000,-27000,56000"
)
oxt "9000,6000,11000,10000"
)
*498 (CommentGraphic
uid 9992,0
shape (Arc2D
pts [
"-29000,56000"
"-31000,54000"
"-29000,52000"
]
uid 9993,0
layer 0
sl 0
va (VaSet
vasetType 1
fg "0,65535,65535"
lineColor "26368,26368,26368"
)
xt "-31000,52000,-29000,56000"
)
oxt "7000,6000,9000,10000"
)
]
shape (GroupingShape
uid 9989,0
sl 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "-31000,52000,-27000,56000"
)
oxt "7000,6000,11000,10000"
)
]
shape (Rectangle
uid 9958,0
va (VaSet
vasetType 1
transparent 1
fg "65535,65535,65535"
lineWidth -1
)
xt "-32000,52000,-26000,56000"
fos 1
)
showPorts 0
oxt "6000,6000,12000,10000"
ttg (MlTextGroup
uid 9959,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*499 (Text
uid 9960,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-29500,52500,-24700,53500"
st "moduleware"
blo "-29500,53300"
)
*500 (Text
uid 9961,0
va (VaSet
font "arial,8,0"
)
xt "-29500,53500,-27900,54500"
st "and"
blo "-29500,54300"
)
*501 (Text
uid 9962,0
va (VaSet
font "arial,8,0"
)
xt "-29500,54500,-28500,55500"
st "I6"
blo "-29500,55300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 9963,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 9964,0
text (MLText
uid 9965,0
va (VaSet
font "arial,8,0"
)
xt "-47000,43000,-47000,43000"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
de 1
visOptions (mwParamsVisibilityOptions
)
)
*502 (Net
uid 10008,0
decl (Decl
n "SRCLK1"
t "std_logic"
o 106
suid 224,0
i "'0'"
)
declText (MLText
uid 10009,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,58600,-59500,59400"
st "SIGNAL SRCLK1                 : std_logic                                    := '0'
"
)
)
*503 (Wire
uid 322,0
shape (OrthoPolyLine
uid 323,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "40750,48000,76250,48000"
pts [
"40750,48000"
"55000,48000"
"76250,48000"
]
)
start &26
end &313
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 324,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 325,0
va (VaSet
)
xt "42000,47000,47800,48000"
st "write_ea : (0:0)"
blo "42000,47800"
tm "WireNameMgr"
)
)
on &2
)
*504 (Wire
uid 328,0
shape (OrthoPolyLine
uid 329,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "40750,49000,76250,49000"
pts [
"40750,49000"
"55000,49000"
"76250,49000"
]
)
start &25
end &312
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 330,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 331,0
va (VaSet
)
xt "42000,48000,56500,49000"
st "addr_out : (RAMADDRWIDTH64b-1:0)"
blo "42000,48800"
tm "WireNameMgr"
)
)
on &3
)
*505 (Wire
uid 334,0
shape (OrthoPolyLine
uid 335,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "40750,50000,76250,50000"
pts [
"40750,50000"
"55000,50000"
"76250,50000"
]
)
start &24
end &311
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 336,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 337,0
va (VaSet
)
xt "42000,49000,48200,50000"
st "data_out : (63:0)"
blo "42000,49800"
tm "WireNameMgr"
)
)
on &4
)
*506 (Wire
uid 364,0
shape (OrthoPolyLine
uid 365,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "91750,49000,126250,54000"
pts [
"126250,54000"
"113000,54000"
"113000,49000"
"91750,49000"
]
)
start &80
end &315
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 366,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 367,0
va (VaSet
)
xt "94000,48000,109000,49000"
st "ram_addr : (RAMADDRWIDTH64b+1:0)"
blo "94000,48800"
tm "WireNameMgr"
)
)
on &5
)
*507 (Wire
uid 370,0
shape (OrthoPolyLine
uid 371,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "91750,50000,126250,55000"
pts [
"126250,55000"
"112000,55000"
"112000,50000"
"91750,50000"
]
)
start &79
end &316
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 372,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 373,0
va (VaSet
)
xt "95000,50000,101500,51000"
st "ram_data : (15:0)"
blo "95000,50800"
tm "WireNameMgr"
)
)
on &6
)
*508 (Wire
uid 376,0
shape (OrthoPolyLine
uid 377,0
va (VaSet
vasetType 3
)
xt "148750,52000,153000,52000"
pts [
"148750,52000"
"153000,52000"
]
)
start &70
end &14
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 380,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 381,0
va (VaSet
isHidden 1
)
xt "150000,51000,153600,52000"
st "wiz_reset"
blo "150000,51800"
tm "WireNameMgr"
)
)
on &7
)
*509 (Wire
uid 384,0
shape (OrthoPolyLine
uid 385,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "148750,60000,153000,60000"
pts [
"148750,60000"
"153000,60000"
]
)
start &71
end &15
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 388,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 389,0
va (VaSet
isHidden 1
)
xt "150000,59000,153400,60000"
st "wiz_addr"
blo "150000,59800"
tm "WireNameMgr"
)
)
on &8
)
*510 (Wire
uid 392,0
shape (OrthoPolyLine
uid 393,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "148750,61000,153000,61000"
pts [
"148750,61000"
"153000,61000"
]
)
start &72
end &16
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 396,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 397,0
va (VaSet
isHidden 1
)
xt "150000,60000,153300,61000"
st "wiz_data"
blo "150000,60800"
tm "WireNameMgr"
)
)
on &9
)
*511 (Wire
uid 400,0
shape (OrthoPolyLine
uid 401,0
va (VaSet
vasetType 3
)
xt "148750,53000,153000,53000"
pts [
"148750,53000"
"153000,53000"
]
)
start &73
end &17
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 404,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 405,0
va (VaSet
isHidden 1
)
xt "150000,52000,152700,53000"
st "wiz_cs"
blo "150000,52800"
tm "WireNameMgr"
)
)
on &10
)
*512 (Wire
uid 408,0
shape (OrthoPolyLine
uid 409,0
va (VaSet
vasetType 3
)
xt "148750,54000,153000,54000"
pts [
"148750,54000"
"153000,54000"
]
)
start &74
end &18
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 412,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 413,0
va (VaSet
isHidden 1
)
xt "150000,53000,152700,54000"
st "wiz_wr"
blo "150000,53800"
tm "WireNameMgr"
)
)
on &11
)
*513 (Wire
uid 424,0
shape (OrthoPolyLine
uid 425,0
va (VaSet
vasetType 3
)
xt "148750,55000,153000,55000"
pts [
"148750,55000"
"153000,55000"
]
)
start &75
end &20
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 428,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 429,0
va (VaSet
isHidden 1
)
xt "150000,54000,152600,55000"
st "wiz_rd"
blo "150000,54800"
tm "WireNameMgr"
)
)
on &12
)
*514 (Wire
uid 432,0
shape (OrthoPolyLine
uid 433,0
va (VaSet
vasetType 3
)
xt "148750,56000,153000,56000"
pts [
"153000,56000"
"148750,56000"
]
)
start &21
end &76
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 436,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 437,0
va (VaSet
isHidden 1
)
xt "150000,55000,152700,56000"
st "wiz_int"
blo "150000,55800"
tm "WireNameMgr"
)
)
on &13
)
*515 (Wire
uid 1411,0
shape (OrthoPolyLine
uid 1412,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-26000,86000,18250,86000"
pts [
"-26000,86000"
"18250,86000"
]
)
start &155
end &28
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1415,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1416,0
va (VaSet
)
xt "-24000,85000,-20700,86000"
st "board_id"
blo "-24000,85800"
tm "WireNameMgr"
)
)
on &65
)
*516 (Wire
uid 1425,0
optionalChildren [
*517 (BdJunction
uid 4391,0
ps "OnConnectorStrategy"
shape (Circle
uid 4392,0
va (VaSet
vasetType 1
)
xt "-22400,68600,-21600,69400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 1426,0
va (VaSet
vasetType 3
)
xt "-26000,69000,18250,69000"
pts [
"-26000,69000"
"18250,69000"
]
)
start &67
end &30
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1429,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1430,0
va (VaSet
isHidden 1
)
xt "5000,63000,7800,64000"
st "trigger"
blo "5000,63800"
tm "WireNameMgr"
)
)
on &66
)
*518 (Wire
uid 1682,0
shape (OrthoPolyLine
uid 1683,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-26000,87000,18250,87000"
pts [
"-26000,87000"
"18250,87000"
]
)
start &156
end &31
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1686,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1687,0
va (VaSet
)
xt "-24000,86000,-20900,87000"
st "crate_id"
blo "-24000,86800"
tm "WireNameMgr"
)
)
on &106
)
*519 (Wire
uid 1983,0
shape (OrthoPolyLine
uid 1984,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-6250,64000,18250,68000"
pts [
"-6250,64000"
"6000,64000"
"6000,68000"
"18250,68000"
]
)
start &108
end &29
sat 32
eat 32
sty 1
st 0
sf 1
tg (WTG
uid 1985,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1986,0
va (VaSet
)
xt "11000,67000,17800,68000"
st "trigger_id : (47:0)"
blo "11000,67800"
tm "WireNameMgr"
)
)
on &114
)
*520 (Wire
uid 2299,0
shape (OrthoPolyLine
uid 2300,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "40750,63000,71250,70000"
pts [
"71250,70000"
"67000,70000"
"67000,63000"
"40750,63000"
]
)
start &117
end &27
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2303,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2304,0
va (VaSet
)
xt "42000,62000,58700,63000"
st "ram_start_addr : (RAMADDRWIDTH64b-1:0)"
blo "42000,62800"
tm "WireNameMgr"
)
)
on &115
)
*521 (Wire
uid 2470,0
shape (OrthoPolyLine
uid 2471,0
va (VaSet
vasetType 3
)
xt "103750,68000,126250,68000"
pts [
"103750,68000"
"115000,68000"
"126250,68000"
]
)
start &124
end &82
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2472,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2473,0
va (VaSet
)
xt "104000,67000,107400,68000"
st "wiz_busy"
blo "104000,67800"
tm "WireNameMgr"
)
)
on &138
)
*522 (Wire
uid 2476,0
shape (OrthoPolyLine
uid 2477,0
va (VaSet
vasetType 3
)
xt "103750,69000,126250,69000"
pts [
"103750,69000"
"115000,69000"
"126250,69000"
]
)
start &127
end &81
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2478,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2479,0
va (VaSet
)
xt "104000,68000,109100,69000"
st "wiz_write_ea"
blo "104000,68800"
tm "WireNameMgr"
)
)
on &139
)
*523 (Wire
uid 2482,0
shape (OrthoPolyLine
uid 2483,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "103750,70000,126250,70000"
pts [
"103750,70000"
"115000,70000"
"126250,70000"
]
)
start &130
end &77
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2484,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2485,0
va (VaSet
)
xt "104000,69000,113400,70000"
st "wiz_write_length : (16:0)"
blo "104000,69800"
tm "WireNameMgr"
)
)
on &140
)
*524 (Wire
uid 2488,0
shape (OrthoPolyLine
uid 2489,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "103750,71000,126250,71000"
pts [
"103750,71000"
"115000,71000"
"126250,71000"
]
)
start &126
end &78
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2490,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2491,0
va (VaSet
)
xt "104000,70000,122800,71000"
st "wiz_ram_start_addr : (RAMADDRWIDTH64b+1:0)"
blo "104000,70800"
tm "WireNameMgr"
)
)
on &141
)
*525 (Wire
uid 2494,0
shape (OrthoPolyLine
uid 2495,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "103750,72000,126250,72000"
pts [
"103750,72000"
"115000,72000"
"126250,72000"
]
)
start &125
end &83
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2496,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2497,0
va (VaSet
)
xt "104000,71000,115800,72000"
st "wiz_number_of_channels : (3:0)"
blo "104000,71800"
tm "WireNameMgr"
)
)
on &142
)
*526 (Wire
uid 2500,0
shape (OrthoPolyLine
uid 2501,0
va (VaSet
vasetType 3
)
xt "103750,73000,126250,73000"
pts [
"103750,73000"
"115000,73000"
"126250,73000"
]
)
start &128
end &84
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2502,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2503,0
va (VaSet
)
xt "104000,72000,109500,73000"
st "wiz_write_end"
blo "104000,72800"
tm "WireNameMgr"
)
)
on &143
)
*527 (Wire
uid 2506,0
shape (OrthoPolyLine
uid 2507,0
va (VaSet
vasetType 3
)
xt "103750,74000,126250,74000"
pts [
"103750,74000"
"115000,74000"
"126250,74000"
]
)
start &129
end &85
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2508,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2509,0
va (VaSet
)
xt "104000,73000,110600,74000"
st "wiz_write_header"
blo "104000,73800"
tm "WireNameMgr"
)
)
on &144
)
*528 (Wire
uid 2576,0
shape (OrthoPolyLine
uid 2577,0
va (VaSet
vasetType 3
)
xt "40750,64000,71250,71000"
pts [
"40750,64000"
"66000,64000"
"66000,71000"
"71250,71000"
]
)
start &32
end &121
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2578,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2579,0
va (VaSet
)
xt "42000,63000,47300,64000"
st "ram_write_ea"
blo "42000,63800"
tm "WireNameMgr"
)
)
on &145
)
*529 (Wire
uid 2582,0
shape (OrthoPolyLine
uid 2583,0
va (VaSet
vasetType 3
)
xt "40750,65000,71250,72000"
pts [
"40750,65000"
"65000,65000"
"65000,72000"
"71250,72000"
]
)
start &33
end &122
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2584,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2585,0
va (VaSet
)
xt "42000,64000,48300,65000"
st "ram_write_ready"
blo "42000,64800"
tm "WireNameMgr"
)
)
on &146
)
*530 (Wire
uid 2588,0
shape (OrthoPolyLine
uid 2589,0
va (VaSet
vasetType 3
)
xt "40750,70000,71250,75000"
pts [
"40750,70000"
"64000,70000"
"64000,75000"
"71250,75000"
]
)
start &53
end &120
ss 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2590,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2591,0
va (VaSet
)
xt "41000,69000,45800,70000"
st "config_start"
blo "41000,69800"
tm "WireNameMgr"
)
)
on &147
)
*531 (Wire
uid 2594,0
shape (OrthoPolyLine
uid 2595,0
va (VaSet
vasetType 3
)
xt "40750,72000,71250,77000"
pts [
"40750,72000"
"62000,72000"
"62000,77000"
"71250,77000"
]
)
start &49
end &119
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2596,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2597,0
va (VaSet
)
xt "41000,71000,46100,72000"
st "config_ready"
blo "41000,71800"
tm "WireNameMgr"
)
)
on &148
)
*532 (Wire
uid 2600,0
shape (OrthoPolyLine
uid 2601,0
va (VaSet
vasetType 3
)
xt "40750,74000,71250,78000"
pts [
"40750,74000"
"61000,74000"
"61000,78000"
"71250,78000"
]
)
start &34
end &123
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2602,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2603,0
va (VaSet
)
xt "41000,73000,44000,74000"
st "roi_max"
blo "41000,73800"
tm "WireNameMgr"
)
)
on &149
)
*533 (Wire
uid 2642,0
shape (OrthoPolyLine
uid 2643,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "40750,75000,71250,79000"
pts [
"40750,75000"
"60000,75000"
"60000,79000"
"71250,79000"
]
)
start &36
end &132
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2644,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2645,0
va (VaSet
)
xt "41000,74000,50100,75000"
st "package_length : (15:0)"
blo "41000,74800"
tm "WireNameMgr"
)
)
on &150
)
*534 (Wire
uid 2778,0
shape (OrthoPolyLine
uid 2779,0
va (VaSet
vasetType 3
)
xt "-26000,82000,18250,82000"
pts [
"18250,82000"
"-26000,82000"
]
)
start &37
end &152
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2782,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2783,0
va (VaSet
isHidden 1
)
xt "-20000,76000,-16800,77000"
st "adc_oeb"
blo "-20000,76800"
tm "WireNameMgr"
)
)
on &151
)
*535 (Wire
uid 2786,0
shape (OrthoPolyLine
uid 2787,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-26000,77000,-18750,77000"
pts [
"-26000,77000"
"-18750,77000"
]
)
start &153
end &250
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2790,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2791,0
va (VaSet
isHidden 1
)
xt "-57000,70000,-51600,71000"
st "adc_otr_array"
blo "-57000,70800"
tm "WireNameMgr"
)
)
on &174
)
*536 (Wire
uid 2876,0
shape (OrthoPolyLine
uid 2877,0
va (VaSet
vasetType 3
)
xt "-22000,64000,-18750,69000"
pts [
"-22000,69000"
"-22000,64000"
"-18750,64000"
]
)
start &517
end &109
es 0
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 2880,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2881,0
ro 270
va (VaSet
)
xt "-23000,64200,-22000,67000"
st "trigger"
blo "-22200,67000"
tm "WireNameMgr"
)
)
on &66
)
*537 (Wire
uid 3888,0
optionalChildren [
*538 (BdJunction
uid 4230,0
ps "OnConnectorStrategy"
shape (Circle
uid 4231,0
va (VaSet
vasetType 1
)
xt "4600,18600,5400,19400"
radius 400
)
)
*539 (BdJunction
uid 4244,0
ps "OnConnectorStrategy"
shape (Circle
uid 4245,0
va (VaSet
vasetType 1
)
xt "108600,18600,109400,19400"
radius 400
)
)
*540 (BdJunction
uid 9677,0
ps "OnConnectorStrategy"
shape (Circle
uid 9678,0
va (VaSet
vasetType 1
)
xt "23600,18600,24400,19400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 3889,0
va (VaSet
vasetType 3
lineColor "0,0,65535"
)
xt "-1250,19000,126250,52000"
pts [
"-1250,19000"
"123000,19000"
"123000,52000"
"126250,52000"
]
)
start &368
end &69
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3890,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3891,0
va (VaSet
)
xt "750,18000,3850,19000"
st "CLK_50"
blo "750,18800"
tm "WireNameMgr"
)
)
on &170
)
*541 (Wire
uid 3984,0
optionalChildren [
*542 (BdJunction
uid 9751,0
ps "OnConnectorStrategy"
shape (Circle
uid 9752,0
va (VaSet
vasetType 1
)
xt "1600,25600,2400,26400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 3985,0
va (VaSet
vasetType 3
lineColor "49152,0,0"
)
xt "-26000,21000,2000,29000"
pts [
"-26000,29000"
"2000,29000"
"2000,21000"
"-1250,21000"
]
)
start &169
end &380
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3986,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3987,0
va (VaSet
isHidden 1
)
xt "-27000,30000,-22500,31000"
st "CLK_25_PS"
blo "-27000,30800"
tm "WireNameMgr"
)
)
on &168
)
*543 (Wire
uid 4042,0
shape (OrthoPolyLine
uid 4043,0
va (VaSet
vasetType 3
)
xt "-26000,19000,-20750,19000"
pts [
"-26000,19000"
"-20750,19000"
]
)
start &1
end &370
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4044,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4045,0
va (VaSet
isHidden 1
)
xt "-25000,32000,-23100,33000"
st "CLK"
blo "-25000,32800"
tm "WireNameMgr"
)
)
on &173
)
*544 (Wire
uid 4226,0
shape (OrthoPolyLine
uid 4227,0
va (VaSet
vasetType 3
lineColor "0,0,65535"
)
xt "-26000,19000,5000,34000"
pts [
"-26000,34000"
"5000,34000"
"5000,19000"
]
)
start &172
end &538
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4228,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4229,0
va (VaSet
isHidden 1
)
xt "-27000,30000,-23900,31000"
st "CLK_50"
blo "-27000,30800"
tm "WireNameMgr"
)
)
on &170
)
*545 (Wire
uid 4240,0
shape (OrthoPolyLine
uid 4241,0
va (VaSet
vasetType 3
lineColor "0,0,65535"
)
xt "91750,19000,109000,44000"
pts [
"91750,44000"
"109000,44000"
"109000,19000"
]
)
start &314
end &539
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4242,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4243,0
va (VaSet
)
xt "93000,44000,96100,45000"
st "CLK_50"
blo "93000,44800"
tm "WireNameMgr"
)
)
on &170
)
*546 (Wire
uid 4272,0
shape (OrthoPolyLine
uid 4273,0
va (VaSet
vasetType 3
)
xt "-26000,76000,-18750,76000"
pts [
"-26000,76000"
"-18750,76000"
]
)
start &176
end &247
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4274,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4275,0
va (VaSet
isHidden 1
)
xt "-56000,70000,-50100,71000"
st "adc_data_array"
blo "-56000,70800"
tm "WireNameMgr"
)
)
on &175
)
*547 (Wire
uid 4401,0
shape (OrthoPolyLine
uid 4402,0
va (VaSet
vasetType 3
)
xt "1750,53000,18250,53000"
pts [
"18250,53000"
"1750,53000"
]
)
start &40
end &195
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 4403,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4404,0
va (VaSet
)
xt "13250,52000,17650,53000"
st "drs_clk_en"
blo "13250,52800"
tm "WireNameMgr"
)
)
on &177
)
*548 (Wire
uid 4407,0
shape (OrthoPolyLine
uid 4408,0
va (VaSet
vasetType 3
)
xt "1750,52000,18250,52000"
pts [
"18250,52000"
"1750,52000"
]
)
start &44
end &201
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 4409,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4410,0
va (VaSet
)
xt "11250,51000,17650,52000"
st "drs_s_cell_array"
blo "11250,51800"
tm "WireNameMgr"
)
)
on &178
)
*549 (Wire
uid 4419,0
shape (OrthoPolyLine
uid 4420,0
va (VaSet
vasetType 3
)
xt "1750,50000,18250,50000"
pts [
"18250,50000"
"1750,50000"
]
)
start &42
end &196
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 4421,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4422,0
va (VaSet
)
xt "11250,49000,17450,50000"
st "drs_read_s_cell"
blo "11250,49800"
tm "WireNameMgr"
)
)
on &179
)
*550 (Wire
uid 4537,0
shape (OrthoPolyLine
uid 4538,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-37000,100000,-33000,100000"
pts [
"-33000,100000"
"-37000,100000"
]
)
start &326
end &182
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4541,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4542,0
va (VaSet
isHidden 1
)
xt "-71000,99000,-65100,100000"
st "drs_channel_id"
blo "-71000,99800"
tm "WireNameMgr"
)
)
on &180
)
*551 (Wire
uid 4545,0
shape (OrthoPolyLine
uid 4546,0
va (VaSet
vasetType 3
)
xt "-26000,60000,1000,60000"
pts [
"1000,60000"
"-26000,60000"
]
)
start &291
end &183
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4549,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4550,0
va (VaSet
)
xt "-18000,59000,-13700,60000"
st "drs_dwrite"
blo "-18000,59800"
tm "WireNameMgr"
)
)
on &181
)
*552 (Wire
uid 4671,0
shape (OrthoPolyLine
uid 4672,0
va (VaSet
vasetType 3
)
xt "-26000,47000,-18750,47000"
pts [
"-26000,47000"
"-18750,47000"
]
)
start &188
end &197
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4675,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4676,0
va (VaSet
isHidden 1
)
xt "-25000,46000,-19600,47000"
st "SROUT_in_0"
blo "-25000,46800"
tm "WireNameMgr"
)
)
on &184
)
*553 (Wire
uid 4679,0
shape (OrthoPolyLine
uid 4680,0
va (VaSet
vasetType 3
)
xt "-26000,48000,-18750,48000"
pts [
"-26000,48000"
"-18750,48000"
]
)
start &189
end &198
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4683,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4684,0
va (VaSet
isHidden 1
)
xt "-25000,47000,-19600,48000"
st "SROUT_in_1"
blo "-25000,47800"
tm "WireNameMgr"
)
)
on &185
)
*554 (Wire
uid 4687,0
shape (OrthoPolyLine
uid 4688,0
va (VaSet
vasetType 3
)
xt "-26000,49000,-18750,49000"
pts [
"-26000,49000"
"-18750,49000"
]
)
start &190
end &199
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4691,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4692,0
va (VaSet
isHidden 1
)
xt "-25000,48000,-19600,49000"
st "SROUT_in_2"
blo "-25000,48800"
tm "WireNameMgr"
)
)
on &186
)
*555 (Wire
uid 4695,0
shape (OrthoPolyLine
uid 4696,0
va (VaSet
vasetType 3
)
xt "-26000,50000,-18750,50000"
pts [
"-26000,50000"
"-18750,50000"
]
)
start &191
end &200
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4699,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4700,0
va (VaSet
isHidden 1
)
xt "-25000,49000,-19600,50000"
st "SROUT_in_3"
blo "-25000,49800"
tm "WireNameMgr"
)
)
on &187
)
*556 (Wire
uid 4743,0
shape (OrthoPolyLine
uid 4744,0
va (VaSet
vasetType 3
)
xt "1750,51000,18250,51000"
pts [
"1750,51000"
"18250,51000"
]
)
start &202
end &43
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 4747,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4748,0
va (VaSet
)
xt "3750,50000,12550,51000"
st "drs_read_s_cell_ready"
blo "3750,50800"
tm "WireNameMgr"
)
)
on &192
)
*557 (Wire
uid 4757,0
optionalChildren [
*558 (BdJunction
uid 6076,0
ps "OnConnectorStrategy"
shape (Circle
uid 6077,0
va (VaSet
vasetType 1
)
xt "14600,37600,15400,38400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 4758,0
va (VaSet
vasetType 3
lineColor "0,32896,0"
)
xt "-22000,38000,15000,45000"
pts [
"-18750,45000"
"-22000,45000"
"-22000,38000"
"15000,38000"
]
)
start &194
end *559 (BdJunction
uid 6080,0
ps "OnConnectorStrategy"
shape (Circle
uid 6081,0
va (VaSet
vasetType 1
)
xt "14600,37600,15400,38400"
radius 400
)
)
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4759,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4760,0
va (VaSet
)
xt "-22750,44000,-19650,45000"
st "CLK_25"
blo "-22750,44800"
tm "WireNameMgr"
)
)
on &171
)
*560 (Wire
uid 4948,0
shape (OrthoPolyLine
uid 4949,0
va (VaSet
vasetType 3
)
xt "-26000,51000,-18750,51000"
pts [
"-18750,51000"
"-26000,51000"
]
)
start &203
end &209
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4952,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4953,0
va (VaSet
isHidden 1
)
xt "-24000,50000,-19800,51000"
st "RSRLOAD"
blo "-24000,50800"
tm "WireNameMgr"
)
)
on &208
)
*561 (Wire
uid 4962,0
shape (OrthoPolyLine
uid 4963,0
va (VaSet
vasetType 3
)
xt "-33000,54000,-32000,54000"
pts [
"-32000,54000"
"-33000,54000"
]
)
start &485
end &211
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4966,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4967,0
va (VaSet
isHidden 1
)
xt "-33000,53000,-30000,54000"
st "SRCLK"
blo "-33000,53800"
tm "WireNameMgr"
)
)
on &210
)
*562 (Wire
uid 5090,0
shape (OrthoPolyLine
uid 5091,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "92750,79000,126250,100000"
pts [
"126250,79000"
"116000,79000"
"116000,100000"
"92750,100000"
]
)
start &88
end &214
sat 32
eat 32
sty 1
st 0
sf 1
tg (WTG
uid 5094,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5095,0
va (VaSet
)
xt "119000,78000,126000,79000"
st "config_addr : (7:0)"
blo "119000,78800"
tm "WireNameMgr"
)
)
on &230
)
*563 (Wire
uid 5098,0
shape (OrthoPolyLine
uid 5099,0
va (VaSet
vasetType 3
)
xt "92750,102000,103000,102000"
pts [
"92750,102000"
"103000,102000"
]
)
start &215
sat 32
eat 16
st 0
sf 1
tg (WTG
uid 5102,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5103,0
va (VaSet
)
xt "94000,101000,100600,102000"
st "config_data_valid"
blo "94000,101800"
tm "WireNameMgr"
)
)
on &231
)
*564 (Wire
uid 5106,0
shape (OrthoPolyLine
uid 5107,0
va (VaSet
vasetType 3
)
xt "92750,84000,126250,106000"
pts [
"92750,106000"
"121000,106000"
"121000,84000"
"126250,84000"
]
)
start &216
end &89
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5110,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5111,0
va (VaSet
)
xt "94750,105000,99550,106000"
st "config_busy"
blo "94750,105800"
tm "WireNameMgr"
)
)
on &232
)
*565 (Wire
uid 5114,0
shape (OrthoPolyLine
uid 5115,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "92750,80000,126250,101000"
pts [
"92750,101000"
"117000,101000"
"117000,80000"
"126250,80000"
]
)
start &217
end &90
sat 32
eat 32
sty 1
st 0
sf 1
tg (WTG
uid 5118,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5119,0
va (VaSet
)
xt "94000,100000,101700,101000"
st "config_data : (15:0)"
blo "94000,100800"
tm "WireNameMgr"
)
)
on &233
)
*566 (Wire
uid 5122,0
shape (OrthoPolyLine
uid 5123,0
va (VaSet
vasetType 3
)
xt "92750,82000,126250,104000"
pts [
"126250,82000"
"119000,82000"
"119000,104000"
"92750,104000"
]
)
start &92
end &219
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5126,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5127,0
va (VaSet
)
xt "121000,81000,126300,82000"
st "config_wr_en"
blo "121000,81800"
tm "WireNameMgr"
)
)
on &234
)
*567 (Wire
uid 5130,0
shape (OrthoPolyLine
uid 5131,0
va (VaSet
vasetType 3
)
xt "92750,83000,126250,105000"
pts [
"126250,83000"
"120000,83000"
"120000,105000"
"92750,105000"
]
)
start &94
end &221
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5134,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5135,0
va (VaSet
)
xt "121000,82000,126200,83000"
st "config_rd_en"
blo "121000,82800"
tm "WireNameMgr"
)
)
on &235
)
*568 (Wire
uid 5138,0
optionalChildren [
*569 (BdJunction
uid 5400,0
ps "OnConnectorStrategy"
shape (Circle
uid 5401,0
va (VaSet
vasetType 1
)
xt "57600,84600,58400,85400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 5139,0
va (VaSet
vasetType 3
)
xt "40750,80000,73250,102000"
pts [
"73250,102000"
"58000,102000"
"58000,80000"
"40750,80000"
]
)
start &218
end &35
ss 0
es 0
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5142,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5143,0
va (VaSet
)
xt "42000,79000,45400,80000"
st "roi_array"
blo "42000,79800"
tm "WireNameMgr"
)
)
on &154
)
*570 (Wire
uid 5146,0
shape (OrthoPolyLine
uid 5147,0
va (VaSet
vasetType 3
)
xt "37750,109000,73250,109000"
pts [
"73250,109000"
"37750,109000"
]
)
start &220
end &258
es 0
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5150,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5151,0
va (VaSet
)
xt "39000,108000,42700,109000"
st "dac_array"
blo "39000,108800"
tm "WireNameMgr"
)
)
on &236
)
*571 (Wire
uid 5168,0
shape (OrthoPolyLine
uid 5169,0
va (VaSet
vasetType 3
)
xt "58000,85000,71250,85000"
pts [
"58000,85000"
"71250,85000"
]
)
start &569
end &131
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 5172,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5173,0
va (VaSet
)
xt "68000,84000,71400,85000"
st "roi_array"
blo "68000,84800"
tm "WireNameMgr"
)
)
on &154
)
*572 (Wire
uid 5184,0
shape (OrthoPolyLine
uid 5185,0
va (VaSet
vasetType 3
)
xt "40750,81000,73250,103000"
pts [
"73250,103000"
"57000,103000"
"57000,81000"
"40750,81000"
]
)
start &222
end &47
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5186,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5187,0
va (VaSet
)
xt "66000,102000,72200,103000"
st "config_start_cm"
blo "66000,102800"
tm "WireNameMgr"
)
)
on &237
)
*573 (Wire
uid 5190,0
shape (OrthoPolyLine
uid 5191,0
va (VaSet
vasetType 3
)
xt "40750,83000,73250,105000"
pts [
"73250,105000"
"55000,105000"
"55000,83000"
"40750,83000"
]
)
start &223
end &46
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5192,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5193,0
va (VaSet
)
xt "66000,104000,72500,105000"
st "config_ready_cm"
blo "66000,104800"
tm "WireNameMgr"
)
)
on &238
)
*574 (Wire
uid 5222,0
shape (OrthoPolyLine
uid 5223,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "148750,71000,153000,71000"
pts [
"148750,71000"
"153000,71000"
]
)
start &86
end &19
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5224,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5225,0
va (VaSet
isHidden 1
)
xt "150750,70000,152150,71000"
st "led"
blo "150750,70800"
tm "WireNameMgr"
)
)
on &239
)
*575 (Wire
uid 5281,0
shape (OrthoPolyLine
uid 5282,0
va (VaSet
vasetType 3
)
xt "40750,53000,126250,59000"
pts [
"126250,59000"
"73000,59000"
"73000,53000"
"40750,53000"
]
)
start &87
end &48
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 5283,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5284,0
va (VaSet
)
xt "121250,58000,124850,59000"
st "s_trigger"
blo "121250,58800"
tm "WireNameMgr"
)
)
on &240
)
*576 (Wire
uid 5404,0
shape (OrthoPolyLine
uid 5405,0
va (VaSet
vasetType 3
)
xt "37750,85000,48000,107000"
pts [
"37750,107000"
"48000,107000"
"48000,85000"
"40750,85000"
]
)
start &259
end &50
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5406,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5407,0
va (VaSet
)
xt "39000,106000,45500,107000"
st "config_ready_spi"
blo "39000,106800"
tm "WireNameMgr"
)
)
on &243
)
*577 (Wire
uid 5474,0
shape (OrthoPolyLine
uid 5475,0
va (VaSet
vasetType 3
)
xt "37750,90000,44000,101000"
pts [
"37750,101000"
"44000,101000"
"44000,90000"
"40750,90000"
]
)
start &262
end &52
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5476,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5477,0
va (VaSet
)
xt "39750,100000,45050,101000"
st "sensor_ready"
blo "39750,100800"
tm "WireNameMgr"
)
)
on &241
)
*578 (Wire
uid 5480,0
shape (OrthoPolyLine
uid 5481,0
va (VaSet
vasetType 3
)
xt "37750,89000,45000,102000"
pts [
"37750,102000"
"45000,102000"
"45000,89000"
"40750,89000"
]
)
start &261
end &51
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5482,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5483,0
va (VaSet
)
xt "39750,101000,44950,102000"
st "sensor_array"
blo "39750,101800"
tm "WireNameMgr"
)
)
on &242
)
*579 (Wire
uid 5582,0
shape (OrthoPolyLine
uid 5583,0
va (VaSet
vasetType 3
lineColor "0,0,65535"
)
xt "69000,100000,73250,100000"
pts [
"69000,100000"
"73250,100000"
]
)
end &213
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 5586,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5587,0
va (VaSet
)
xt "70000,99000,73100,100000"
st "CLK_50"
blo "70000,99800"
tm "WireNameMgr"
)
)
on &170
)
*580 (Wire
uid 5602,0
optionalChildren [
&559
*581 (BdJunction
uid 6086,0
ps "OnConnectorStrategy"
shape (Circle
uid 6087,0
va (VaSet
vasetType 1
)
xt "67600,43600,68400,44400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 5603,0
va (VaSet
vasetType 3
lineColor "0,32896,0"
)
xt "15000,38000,76250,48000"
pts [
"18250,48000"
"15000,48000"
"15000,38000"
"68000,38000"
"68000,44000"
"76250,44000"
]
)
start &23
end &310
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5604,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5605,0
va (VaSet
)
xt "15000,47000,18100,48000"
st "CLK_25"
blo "15000,47800"
tm "WireNameMgr"
)
)
on &171
)
*582 (Wire
uid 5626,0
shape (OrthoPolyLine
uid 5627,0
va (VaSet
vasetType 3
)
xt "750,76000,18250,76000"
pts [
"18250,76000"
"750,76000"
]
)
start &45
end &248
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 5630,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5631,0
va (VaSet
)
xt "11250,75000,18350,76000"
st "adc_data_array_int"
blo "11250,75800"
tm "WireNameMgr"
)
)
on &245
)
*583 (Wire
uid 5634,0
shape (OrthoPolyLine
uid 5635,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "750,77000,18250,77000"
pts [
"18250,77000"
"750,77000"
]
)
start &38
end &249
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 5638,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5639,0
va (VaSet
)
xt "11250,76000,16750,77000"
st "adc_otr : (3:0)"
blo "11250,76800"
tm "WireNameMgr"
)
)
on &244
)
*584 (Wire
uid 5646,0
shape (OrthoPolyLine
uid 5647,0
va (VaSet
vasetType 3
lineColor "49152,0,0"
)
xt "-26000,74000,-18750,74000"
pts [
"-26000,74000"
"-18750,74000"
]
)
end &251
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 5652,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5653,0
va (VaSet
)
xt "-25000,73000,-20500,74000"
st "CLK_25_PS"
blo "-25000,73800"
tm "WireNameMgr"
)
)
on &168
)
*585 (Wire
uid 5745,0
shape (OrthoPolyLine
uid 5746,0
va (VaSet
vasetType 3
)
xt "37750,87000,46000,105000"
pts [
"40750,87000"
"46000,87000"
"46000,105000"
"37750,105000"
]
)
start &54
end &260
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 5749,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5750,0
va (VaSet
)
xt "39000,104000,45200,105000"
st "config_start_spi"
blo "39000,104800"
tm "WireNameMgr"
)
)
on &255
)
*586 (Wire
uid 5805,0
shape (OrthoPolyLine
uid 5806,0
va (VaSet
vasetType 3
)
xt "16000,101000,20250,101000"
pts [
"16000,101000"
"20250,101000"
]
)
end &265
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 5809,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5810,0
va (VaSet
)
xt "17000,100000,20100,101000"
st "CLK_50"
blo "17000,100800"
tm "WireNameMgr"
)
)
on &170
)
*587 (Wire
uid 5813,0
shape (OrthoPolyLine
uid 5814,0
va (VaSet
vasetType 3
)
xt "-18000,112000,-13000,112000"
pts [
"-13000,112000"
"-18000,112000"
]
)
start &346
end &276
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5817,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5818,0
va (VaSet
isHidden 1
)
xt "-17000,111000,-15300,112000"
st "sclk"
blo "-17000,111800"
tm "WireNameMgr"
)
)
on &272
)
*588 (Wire
uid 5821,0
shape (OrthoPolyLine
uid 5822,0
va (VaSet
vasetType 3
)
xt "12000,108000,20250,108000"
pts [
"20250,108000"
"12000,108000"
]
)
start &268
end &277
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5825,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5826,0
va (VaSet
isHidden 1
)
xt "13000,107000,14400,108000"
st "sio"
blo "13000,107800"
tm "WireNameMgr"
)
)
on &273
)
*589 (Wire
uid 5829,0
shape (OrthoPolyLine
uid 5830,0
va (VaSet
vasetType 3
)
xt "12000,105000,20250,105000"
pts [
"20250,105000"
"12000,105000"
]
)
start &263
end &278
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5833,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5834,0
va (VaSet
isHidden 1
)
xt "13000,104000,15800,105000"
st "dac_cs"
blo "13000,104800"
tm "WireNameMgr"
)
)
on &274
)
*590 (Wire
uid 5837,0
shape (OrthoPolyLine
uid 5838,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "12000,104000,20250,104000"
pts [
"20250,104000"
"12000,104000"
]
)
start &264
end &279
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5841,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5842,0
va (VaSet
isHidden 1
)
xt "13000,103000,16900,104000"
st "sensor_cs"
blo "13000,103800"
tm "WireNameMgr"
)
)
on &275
)
*591 (Wire
uid 5950,0
shape (OrthoPolyLine
uid 5951,0
va (VaSet
vasetType 3
)
xt "40750,54000,126250,60000"
pts [
"126250,60000"
"72000,60000"
"72000,54000"
"40750,54000"
]
)
start &93
end &56
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 5952,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5953,0
va (VaSet
)
xt "120250,59000,124850,60000"
st "new_config"
blo "120250,59800"
tm "WireNameMgr"
)
)
on &280
)
*592 (Wire
uid 5962,0
shape (OrthoPolyLine
uid 5963,0
va (VaSet
vasetType 3
)
xt "40750,55000,126250,61000"
pts [
"126250,61000"
"71000,61000"
"71000,55000"
"40750,55000"
]
)
start &91
end &55
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 5964,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5965,0
va (VaSet
)
xt "119250,60000,124850,61000"
st "config_started"
blo "119250,60800"
tm "WireNameMgr"
)
)
on &281
)
*593 (Wire
uid 6002,0
shape (OrthoPolyLine
uid 6003,0
va (VaSet
vasetType 3
)
xt "40750,82000,73250,104000"
pts [
"73250,104000"
"56000,104000"
"56000,82000"
"40750,82000"
]
)
start &224
end &57
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 6004,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6005,0
va (VaSet
)
xt "66250,103000,73050,104000"
st "config_started_cu"
blo "66250,103800"
tm "WireNameMgr"
)
)
on &283
)
*594 (Wire
uid 6008,0
shape (OrthoPolyLine
uid 6009,0
va (VaSet
vasetType 3
)
xt "37750,86000,47000,106000"
pts [
"37750,106000"
"47000,106000"
"47000,86000"
"40750,86000"
]
)
start &266
end &59
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 6010,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6011,0
va (VaSet
)
xt "39000,105000,46000,106000"
st "config_started_spi"
blo "39000,105800"
tm "WireNameMgr"
)
)
on &282
)
*595 (Wire
uid 6018,0
shape (OrthoPolyLine
uid 6019,0
va (VaSet
vasetType 3
)
xt "40750,71000,71250,76000"
pts [
"40750,71000"
"63000,71000"
"63000,76000"
"71250,76000"
]
)
start &58
end &133
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 6020,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6021,0
va (VaSet
)
xt "41000,70000,48200,71000"
st "config_started_mm"
blo "41000,70800"
tm "WireNameMgr"
)
)
on &284
)
*596 (Wire
uid 6064,0
shape (OrthoPolyLine
uid 6065,0
va (VaSet
vasetType 3
)
xt "40750,79000,47000,79000"
pts [
"47000,79000"
"40750,79000"
]
)
end &60
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 6068,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6069,0
va (VaSet
)
xt "42000,78000,45700,79000"
st "dac_array"
blo "42000,78800"
tm "WireNameMgr"
)
)
on &236
)
*597 (Wire
uid 6072,0
optionalChildren [
*598 (BdJunction
uid 9745,0
ps "OnConnectorStrategy"
shape (Circle
uid 9746,0
va (VaSet
vasetType 1
)
xt "14600,20600,15400,21400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 6073,0
va (VaSet
vasetType 3
lineColor "0,32896,0"
)
xt "-1250,20000,15000,38000"
pts [
"-1250,20000"
"15000,20000"
"15000,38000"
]
)
start &369
end &558
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6074,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6075,0
va (VaSet
)
xt "750,19000,3850,20000"
st "CLK_25"
blo "750,19800"
tm "WireNameMgr"
)
)
on &171
)
*599 (Wire
uid 6082,0
shape (OrthoPolyLine
uid 6083,0
va (VaSet
vasetType 3
lineColor "0,32896,0"
)
xt "68000,44000,71250,68000"
pts [
"71250,68000"
"68000,68000"
"68000,44000"
]
)
start &118
end &581
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6084,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6085,0
va (VaSet
)
xt "68000,67000,71100,68000"
st "CLK_25"
blo "68000,67800"
tm "WireNameMgr"
)
)
on &171
)
*600 (Wire
uid 6160,0
shape (OrthoPolyLine
uid 6161,0
va (VaSet
vasetType 3
)
xt "12000,109000,20250,109000"
pts [
"20250,109000"
"12000,109000"
]
)
start &267
end &286
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6164,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6165,0
va (VaSet
isHidden 1
)
xt "13000,108000,15000,109000"
st "mosi"
blo "13000,108800"
tm "WireNameMgr"
)
)
on &285
)
*601 (Wire
uid 6276,0
shape (OrthoPolyLine
uid 6277,0
va (VaSet
vasetType 3
)
xt "-27000,63000,-18750,63000"
pts [
"-27000,63000"
"-18750,63000"
]
)
end &110
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 6280,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6281,0
va (VaSet
)
xt "-24000,62000,-19500,63000"
st "CLK_25_PS"
blo "-24000,62800"
tm "WireNameMgr"
)
)
on &168
)
*602 (Wire
uid 6362,0
shape (OrthoPolyLine
uid 6363,0
va (VaSet
vasetType 3
)
xt "148750,75000,153000,75000"
pts [
"148750,75000"
"153000,75000"
]
)
start &95
end &288
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6366,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6367,0
va (VaSet
isHidden 1
)
xt "150000,74000,153000,75000"
st "denable"
blo "150000,74800"
tm "WireNameMgr"
)
)
on &287
)
*603 (Wire
uid 6452,0
shape (OrthoPolyLine
uid 6453,0
va (VaSet
vasetType 3
)
xt "148750,76000,154000,76000"
pts [
"148750,76000"
"154000,76000"
]
)
start &96
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6456,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6457,0
va (VaSet
)
xt "155000,76000,160400,77000"
st "dwrite_enable"
blo "155000,76800"
tm "WireNameMgr"
)
)
on &289
)
*604 (Wire
uid 6540,0
shape (OrthoPolyLine
uid 6541,0
va (VaSet
vasetType 3
)
xt "7000,59000,18250,59000"
pts [
"7000,59000"
"18250,59000"
]
)
start &294
end &41
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6542,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6543,0
va (VaSet
)
xt "7000,58000,9400,59000"
st "dwrite"
blo "7000,58800"
tm "WireNameMgr"
)
)
on &308
)
*605 (Wire
uid 6548,0
shape (OrthoPolyLine
uid 6549,0
va (VaSet
vasetType 3
)
xt "7000,61000,15000,61000"
pts [
"7000,61000"
"15000,61000"
]
)
start &296
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6552,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6553,0
va (VaSet
)
xt "7000,60000,12400,61000"
st "dwrite_enable"
blo "7000,60800"
tm "WireNameMgr"
)
)
on &289
)
*606 (Wire
uid 8416,0
shape (OrthoPolyLine
uid 8417,0
va (VaSet
vasetType 3
)
xt "103750,75000,126250,75000"
pts [
"103750,75000"
"126250,75000"
]
)
start &134
end &97
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 8418,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8419,0
va (VaSet
)
xt "104000,74000,107000,75000"
st "wiz_ack"
blo "104000,74800"
tm "WireNameMgr"
)
)
on &320
)
*607 (Wire
uid 8510,0
shape (OrthoPolyLine
uid 8511,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "92750,110000,102000,110000"
pts [
"92750,110000"
"102000,110000"
]
)
start &225
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 8514,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8515,0
va (VaSet
)
xt "94000,109000,101200,110000"
st "drs_address : (3:0)"
blo "94000,109800"
tm "WireNameMgr"
)
)
on &321
)
*608 (Wire
uid 8518,0
shape (OrthoPolyLine
uid 8519,0
va (VaSet
vasetType 3
)
xt "92750,111000,102000,111000"
pts [
"92750,111000"
"102000,111000"
]
)
start &226
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 8522,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8523,0
va (VaSet
)
xt "94000,110000,101200,111000"
st "drs_address_mode"
blo "94000,110800"
tm "WireNameMgr"
)
)
on &322
)
*609 (Wire
uid 8577,0
shape (OrthoPolyLine
uid 8578,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "7000,57000,18250,57000"
pts [
"18250,57000"
"7000,57000"
]
)
start &39
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 8581,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8582,0
va (VaSet
)
xt "8000,56000,18400,57000"
st "drs_channel_internal : (3:0)"
blo "8000,56800"
tm "WireNameMgr"
)
)
on &344
)
*610 (Wire
uid 8587,0
shape (OrthoPolyLine
uid 8588,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-29000,101000,-20000,101000"
pts [
"-20000,101000"
"-29000,101000"
]
)
end &324
sat 16
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 8591,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8592,0
va (VaSet
)
xt "-29000,100000,-20800,101000"
st "drs_channel_internal"
blo "-29000,100800"
tm "WireNameMgr"
)
)
on &344
)
*611 (Wire
uid 8595,0
shape (OrthoPolyLine
uid 8596,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-29000,99000,-20000,99000"
pts [
"-20000,99000"
"-29000,99000"
]
)
end &329
sat 16
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 8599,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8600,0
va (VaSet
)
xt "-29000,98000,-24000,99000"
st "drs_address"
blo "-29000,98800"
tm "WireNameMgr"
)
)
on &321
)
*612 (Wire
uid 8603,0
shape (OrthoPolyLine
uid 8604,0
va (VaSet
vasetType 3
)
xt "-31000,103000,-20000,107000"
pts [
"-20000,107000"
"-31000,107000"
"-31000,103000"
]
)
end &331
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 8607,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8608,0
va (VaSet
)
xt "-29000,106000,-21800,107000"
st "drs_address_mode"
blo "-29000,106800"
tm "WireNameMgr"
)
)
on &322
)
*613 (Wire
uid 8732,0
shape (OrthoPolyLine
uid 8733,0
va (VaSet
vasetType 3
)
xt "-7000,107000,20250,111000"
pts [
"20250,107000"
"-1000,107000"
"-1000,111000"
"-7000,111000"
]
)
start &257
end &351
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 8734,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8735,0
va (VaSet
)
xt "17250,106000,19350,107000"
st "sclk1"
blo "17250,106800"
tm "WireNameMgr"
)
)
on &363
)
*614 (Wire
uid 8738,0
shape (OrthoPolyLine
uid 8739,0
va (VaSet
vasetType 3
)
xt "-7000,113000,4000,113000"
pts [
"4000,113000"
"-7000,113000"
]
)
end &349
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 8742,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8743,0
va (VaSet
)
xt "-5000,112000,-300,113000"
st "sclk_enable"
blo "-5000,112800"
tm "WireNameMgr"
)
)
on &364
)
*615 (Wire
uid 8752,0
shape (OrthoPolyLine
uid 8753,0
va (VaSet
vasetType 3
)
xt "148750,77000,154000,77000"
pts [
"148750,77000"
"154000,77000"
]
)
start &98
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 8756,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8757,0
va (VaSet
)
xt "155000,77000,159700,78000"
st "sclk_enable"
blo "155000,77800"
tm "WireNameMgr"
)
)
on &364
)
*616 (Wire
uid 9006,0
shape (OrthoPolyLine
uid 9007,0
va (VaSet
vasetType 3
)
xt "-26000,83000,18250,83000"
pts [
"18250,83000"
"-26000,83000"
]
)
start &61
end &366
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9010,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9011,0
va (VaSet
isHidden 1
)
xt "-25000,82000,-20500,83000"
st "adc_clk_en"
blo "-25000,82800"
tm "WireNameMgr"
)
)
on &365
)
*617 (Wire
uid 9233,0
shape (OrthoPolyLine
uid 9234,0
va (VaSet
vasetType 3
)
xt "148750,81000,154000,81000"
pts [
"148750,81000"
"154000,81000"
]
)
start &99
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 9237,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9238,0
va (VaSet
)
xt "155000,81000,159900,82000"
st "ps_direction"
blo "155000,81800"
tm "WireNameMgr"
)
)
on &387
)
*618 (Wire
uid 9241,0
shape (OrthoPolyLine
uid 9242,0
va (VaSet
vasetType 3
)
xt "148750,82000,154000,82000"
pts [
"148750,82000"
"154000,82000"
]
)
start &100
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 9245,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9246,0
va (VaSet
)
xt "155000,82000,162000,83000"
st "ps_do_phase_shift"
blo "155000,82800"
tm "WireNameMgr"
)
)
on &388
)
*619 (Wire
uid 9253,0
optionalChildren [
*620 (BdJunction
uid 9507,0
ps "OnConnectorStrategy"
shape (Circle
uid 9508,0
va (VaSet
vasetType 1
)
xt "-24400,11600,-23600,12400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 9254,0
va (VaSet
vasetType 3
)
xt "-26000,12000,-20750,12000"
pts [
"-26000,12000"
"-20750,12000"
]
)
end &381
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 9257,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9258,0
va (VaSet
)
xt "-31000,11000,-26100,12000"
st "ps_direction"
blo "-31000,11800"
tm "WireNameMgr"
)
)
on &387
)
*621 (Wire
uid 9261,0
optionalChildren [
*622 (BdJunction
uid 9513,0
ps "OnConnectorStrategy"
shape (Circle
uid 9514,0
va (VaSet
vasetType 1
)
xt "-25400,12600,-24600,13400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 9262,0
va (VaSet
vasetType 3
)
xt "-26000,13000,-20750,13000"
pts [
"-26000,13000"
"-20750,13000"
]
)
end &382
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 9265,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9266,0
va (VaSet
)
xt "-34000,12000,-27000,13000"
st "ps_do_phase_shift"
blo "-34000,12800"
tm "WireNameMgr"
)
)
on &388
)
*623 (Wire
uid 9269,0
shape (OrthoPolyLine
uid 9270,0
va (VaSet
vasetType 3
)
xt "-1250,16000,8000,16000"
pts [
"-1250,16000"
"8000,16000"
]
)
start &379
end &390
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9273,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9274,0
va (VaSet
isHidden 1
)
xt "0,15000,7700,16000"
st "LOCKED_extraOUT"
blo "0,15800"
tm "WireNameMgr"
)
)
on &389
)
*624 (Wire
uid 9283,0
shape (OrthoPolyLine
uid 9284,0
va (VaSet
vasetType 3
)
xt "-1250,15000,8000,15000"
pts [
"-1250,15000"
"8000,15000"
]
)
start &378
end &392
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9287,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9288,0
va (VaSet
isHidden 1
)
xt "0,14000,7800,15000"
st "PSDONE_extraOUT"
blo "0,14800"
tm "WireNameMgr"
)
)
on &391
)
*625 (Wire
uid 9297,0
shape (OrthoPolyLine
uid 9298,0
va (VaSet
vasetType 3
)
xt "-1250,14000,8000,14000"
pts [
"-1250,14000"
"8000,14000"
]
)
start &377
end &394
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9301,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9302,0
va (VaSet
isHidden 1
)
xt "0,13000,7000,14000"
st "PSINCDEC_OUT"
blo "0,13800"
tm "WireNameMgr"
)
)
on &393
)
*626 (Wire
uid 9311,0
shape (OrthoPolyLine
uid 9312,0
va (VaSet
vasetType 3
)
xt "-1250,13000,8000,13000"
pts [
"-1250,13000"
"8000,13000"
]
)
start &376
end &396
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9315,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9316,0
va (VaSet
isHidden 1
)
xt "0,12000,4600,13000"
st "PSEN_OUT"
blo "0,12800"
tm "WireNameMgr"
)
)
on &395
)
*627 (Wire
uid 9325,0
shape (OrthoPolyLine
uid 9326,0
va (VaSet
vasetType 3
)
xt "-1250,12000,8000,12000"
pts [
"-1250,12000"
"8000,12000"
]
)
start &375
end &398
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9329,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9330,0
va (VaSet
isHidden 1
)
xt "0,11000,5000,12000"
st "PSCLK_OUT"
blo "0,11800"
tm "WireNameMgr"
)
)
on &397
)
*628 (Wire
uid 9353,0
shape (OrthoPolyLine
uid 9354,0
va (VaSet
vasetType 3
)
xt "-1250,10000,8000,10000"
pts [
"-1250,10000"
"8000,10000"
]
)
start &374
end &400
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9357,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9358,0
va (VaSet
isHidden 1
)
xt "0,9000,5200,10000"
st "DCM_locked"
blo "0,9800"
tm "WireNameMgr"
)
)
on &399
)
*629 (Wire
uid 9367,0
shape (OrthoPolyLine
uid 9368,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-1250,7000,8000,7000"
pts [
"-1250,7000"
"8000,7000"
]
)
start &373
end &402
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9371,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9372,0
va (VaSet
isHidden 1
)
xt "0,6000,2200,7000"
st "offset"
blo "0,6800"
tm "WireNameMgr"
)
)
on &401
)
*630 (Wire
uid 9382,0
shape (OrthoPolyLine
uid 9383,0
va (VaSet
vasetType 3
)
xt "-1250,5000,8000,5000"
pts [
"-1250,5000"
"8000,5000"
]
)
start &372
end &404
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9386,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9387,0
va (VaSet
isHidden 1
)
xt "0,4000,2900,5000"
st "shifting"
blo "0,4800"
tm "WireNameMgr"
)
)
on &403
)
*631 (Wire
uid 9397,0
shape (OrthoPolyLine
uid 9398,0
va (VaSet
vasetType 3
)
xt "-1250,3000,8000,3000"
pts [
"-1250,3000"
"8000,3000"
]
)
start &371
end &406
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9401,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9402,0
va (VaSet
isHidden 1
)
xt "0,2000,2200,3000"
st "ready"
blo "0,2800"
tm "WireNameMgr"
)
)
on &405
)
*632 (Wire
uid 9503,0
shape (OrthoPolyLine
uid 9504,0
va (VaSet
vasetType 3
)
xt "-24000,-8000,-3000,12000"
pts [
"-24000,12000"
"-24000,-8000"
"-3000,-8000"
]
)
start &620
end &421
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9505,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9506,0
va (VaSet
)
xt "-9000,-9000,-4100,-8000"
st "ps_direction"
blo "-9000,-8200"
tm "WireNameMgr"
)
)
on &387
)
*633 (Wire
uid 9509,0
shape (OrthoPolyLine
uid 9510,0
va (VaSet
vasetType 3
)
xt "-25000,-12000,-3000,13000"
pts [
"-25000,13000"
"-25000,-12000"
"-3000,-12000"
]
)
start &622
end &408
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9511,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9512,0
va (VaSet
)
xt "-11000,-13000,-4000,-12000"
st "ps_do_phase_shift"
blo "-11000,-12200"
tm "WireNameMgr"
)
)
on &388
)
*634 (Wire
uid 9517,0
shape (OrthoPolyLine
uid 9518,0
va (VaSet
vasetType 3
)
xt "0,-12000,8000,-1000"
pts [
"0,-12000"
"4000,-12000"
"4000,-1000"
"8000,-1000"
]
)
start &410
end &433
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9521,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9522,0
va (VaSet
isHidden 1
)
xt "1000,-13000,5200,-12000"
st "PS_DO_IN"
blo "1000,-12200"
tm "WireNameMgr"
)
)
on &436
)
*635 (Wire
uid 9539,0
shape (OrthoPolyLine
uid 9540,0
va (VaSet
vasetType 3
)
xt "0,-8000,8000,0"
pts [
"0,-8000"
"5000,-8000"
"5000,0"
"8000,0"
]
)
start &423
end &434
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9543,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9544,0
va (VaSet
isHidden 1
)
xt "1000,-9000,5400,-8000"
st "PS_DIR_IN"
blo "1000,-8200"
tm "WireNameMgr"
)
)
on &435
)
*636 (Wire
uid 9673,0
shape (OrthoPolyLine
uid 9674,0
va (VaSet
vasetType 3
)
xt "24000,0,28000,19000"
pts [
"24000,19000"
"24000,0"
"28000,0"
]
)
start &540
end &438
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9675,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9676,0
va (VaSet
)
xt "24000,-1000,27100,0"
st "CLK_50"
blo "24000,-200"
tm "WireNameMgr"
)
)
on &170
)
*637 (Wire
uid 9741,0
shape (OrthoPolyLine
uid 9742,0
va (VaSet
vasetType 3
)
xt "15000,5000,28000,21000"
pts [
"15000,21000"
"25000,21000"
"25000,5000"
"28000,5000"
]
)
start &598
end &451
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9743,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9744,0
va (VaSet
)
xt "24000,4000,27100,5000"
st "CLK_25"
blo "24000,4800"
tm "WireNameMgr"
)
)
on &171
)
*638 (Wire
uid 9747,0
shape (OrthoPolyLine
uid 9748,0
va (VaSet
vasetType 3
)
xt "2000,9000,28000,26000"
pts [
"2000,26000"
"26000,26000"
"26000,9000"
"28000,9000"
]
)
start &542
end &464
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9749,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9750,0
va (VaSet
)
xt "22000,8000,26500,9000"
st "CLK_25_PS"
blo "22000,8800"
tm "WireNameMgr"
)
)
on &168
)
*639 (Wire
uid 9755,0
shape (OrthoPolyLine
uid 9756,0
va (VaSet
vasetType 3
)
xt "31000,0,34000,0"
pts [
"31000,0"
"34000,0"
]
)
start &440
end &476
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9759,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9760,0
va (VaSet
isHidden 1
)
xt "32000,-1000,36800,0"
st "CLK50_OUT"
blo "32000,-200"
tm "WireNameMgr"
)
)
on &477
)
*640 (Wire
uid 9771,0
shape (OrthoPolyLine
uid 9772,0
va (VaSet
vasetType 3
)
xt "31000,5000,34000,5000"
pts [
"31000,5000"
"34000,5000"
]
)
start &453
end &478
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9775,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9776,0
va (VaSet
isHidden 1
)
xt "32000,4000,36800,5000"
st "CLK25_OUT"
blo "32000,4800"
tm "WireNameMgr"
)
)
on &479
)
*641 (Wire
uid 9787,0
shape (OrthoPolyLine
uid 9788,0
va (VaSet
vasetType 3
)
xt "31000,9000,34000,9000"
pts [
"31000,9000"
"34000,9000"
]
)
start &466
end &480
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9791,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9792,0
va (VaSet
isHidden 1
)
xt "32000,8000,38200,9000"
st "CLK25_PSOUT"
blo "32000,8800"
tm "WireNameMgr"
)
)
on &481
)
*642 (Wire
uid 9943,0
shape (OrthoPolyLine
uid 9944,0
va (VaSet
vasetType 3
)
xt "148750,83000,154000,83000"
pts [
"148750,83000"
"154000,83000"
]
)
start &101
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 9947,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9948,0
va (VaSet
)
xt "155000,83000,158300,84000"
st "ps_reset"
blo "155000,83800"
tm "WireNameMgr"
)
)
on &482
)
*643 (Wire
uid 9951,0
shape (OrthoPolyLine
uid 9952,0
va (VaSet
vasetType 3
)
xt "148750,85000,154000,85000"
pts [
"148750,85000"
"154000,85000"
]
)
start &102
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 9955,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9956,0
va (VaSet
)
xt "155000,85000,160000,86000"
st "srclk_enable"
blo "155000,85800"
tm "WireNameMgr"
)
)
on &483
)
*644 (Wire
uid 10010,0
shape (OrthoPolyLine
uid 10011,0
va (VaSet
vasetType 3
)
xt "-26000,52000,-18750,53000"
pts [
"-18750,52000"
"-24000,52000"
"-24000,53000"
"-26000,53000"
]
)
start &204
end &488
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 10014,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10015,0
va (VaSet
)
xt "-22750,51000,-19350,52000"
st "SRCLK1"
blo "-22750,51800"
tm "WireNameMgr"
)
)
on &502
)
*645 (Wire
uid 10018,0
shape (OrthoPolyLine
uid 10019,0
va (VaSet
vasetType 3
)
xt "-26000,55000,-23000,55000"
pts [
"-23000,55000"
"-26000,55000"
]
)
end &490
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10022,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10023,0
va (VaSet
)
xt "-25000,55000,-20000,56000"
st "srclk_enable"
blo "-25000,55800"
tm "WireNameMgr"
)
)
on &483
)
*646 (Wire
uid 10036,0
shape (OrthoPolyLine
uid 10037,0
va (VaSet
vasetType 3
)
xt "-26000,21000,-20750,21000"
pts [
"-26000,21000"
"-20750,21000"
]
)
end &383
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 10040,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10041,0
va (VaSet
)
xt "-25000,20000,-21700,21000"
st "ps_reset"
blo "-25000,20800"
tm "WireNameMgr"
)
)
on &482
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *647 (PackageList
uid 41,0
stg "VerticalLayoutStrategy"
textVec [
*648 (Text
uid 42,0
va (VaSet
font "arial,8,1"
)
xt "-87000,1000,-81600,2000"
st "Package List"
blo "-87000,1800"
)
*649 (MLText
uid 43,0
va (VaSet
)
xt "-87000,2000,-72600,14000"
st "library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_UNSIGNED.all;

library fact_fad_lib;
use fact_fad_lib.fad_definitions.all;

library UNISIM;
use UNISIM.VComponents.all;
USE IEEE.NUMERIC_STD.all;
USE IEEE.std_logic_signed.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 44,0
stg "VerticalLayoutStrategy"
textVec [
*650 (Text
uid 45,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,28100,1000"
st "Compiler Directives"
blo "20000,800"
)
*651 (Text
uid 46,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,1000,29600,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*652 (MLText
uid 47,0
va (VaSet
isHidden 1
)
xt "20000,2000,27500,4000"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*653 (Text
uid 48,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,4000,30100,5000"
st "Post-module directives:"
blo "20000,4800"
)
*654 (MLText
uid 49,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*655 (Text
uid 50,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,5000,29900,6000"
st "End-module directives:"
blo "20000,5800"
)
*656 (MLText
uid 51,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "1280,0,2561,1024"
viewArea "-71804,-21787,15728,50400"
cachedDiagramExtent "-105000,-60500,162300,343294"
pageSetupInfo (PageSetupInfo
ptrCmd "eDocPrintPro,winspool,"
fileName "eDocPort"
toPrinter 1
colour 1
xMargin 0
yMargin 0
paperWidth 1523
paperHeight 1077
windowsPaperWidth 1523
windowsPaperHeight 1077
paperType "A3"
windowsPaperName "A3"
windowsPaperType 8
useAdjustTo 0
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
exportStdIncludeRefs 1
exportStdPackageRefs 1
)
hasePageBreakOrigin 1
pageBreakOrigin "-73000,0"
lastUid 10041,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,2000,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Arial,8,1"
)
xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*657 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,3500,5800,4500"
st "<library>"
blo "2200,4300"
tm "BdLibraryNameMgr"
)
*658 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,4500,5600,5500"
st "<block>"
blo "2200,5300"
tm "BlkNameMgr"
)
*659 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,5500,4000,6500"
st "U_0"
blo "2200,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "2200,13500,2200,13500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*660 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,3500,3450,4500"
st "Library"
blo "550,4300"
)
*661 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,4500,7450,5500"
st "MWComponent"
blo "550,5300"
)
*662 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,5500,2350,6500"
st "U_0"
blo "550,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6450,1500,-6450,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*663 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,3500,3800,4500"
st "Library"
blo "900,4300"
tm "BdLibraryNameMgr"
)
*664 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,4500,7100,5500"
st "SaComponent"
blo "900,5300"
tm "CptNameMgr"
)
*665 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,5500,2700,6500"
st "U_0"
blo "900,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6100,1500,-6100,1500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*666 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,3500,3400,4500"
st "Library"
blo "500,4300"
)
*667 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,4500,7500,5500"
st "VhdlComponent"
blo "500,5300"
)
*668 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,5500,2300,6500"
st "U_0"
blo "500,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6500,1500,-6500,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-450,0,8450,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*669 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,3500,2950,4500"
st "Library"
blo "50,4300"
)
*670 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,4500,7950,5500"
st "VerilogComponent"
blo "50,5300"
)
*671 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,5500,1850,6500"
st "U_0"
blo "50,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6950,1500,-6950,1500"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*672 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,4000,4850,5000"
st "eb1"
blo "3150,4800"
tm "HdlTextNameMgr"
)
*673 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,5000,3950,6000"
st "1"
blo "3150,5800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,2000,1200"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
font "Arial,8,1"
)
xt "-500,-500,500,500"
st "G"
blo "-500,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,1900,1000"
st "sig0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,2400,1000"
st "dbus0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineColor "32768,0,0"
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,3000,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1000,1000,2000"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
)
second (MLText
va (VaSet
)
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,12600,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*674 (Text
va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*675 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,7400,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*676 (Text
va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*677 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Courier New,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Arial,8,1"
)
xt "-105000,16200,-99600,17200"
st "Declarations"
blo "-105000,17000"
)
portLabel (Text
uid 3,0
va (VaSet
font "Arial,8,1"
)
xt "-105000,17200,-102300,18200"
st "Ports:"
blo "-105000,18000"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "Arial,8,1"
)
xt "-105000,55800,-101200,56800"
st "Pre User:"
blo "-105000,56600"
)
preUserText (MLText
uid 5,0
va (VaSet
font "Courier New,8,0"
)
xt "-103000,32800,-83000,34400"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Arial,8,1"
)
xt "-105000,56800,-97900,57800"
st "Diagram Signals:"
blo "-105000,57600"
)
postUserLabel (Text
uid 7,0
va (VaSet
font "Arial,8,1"
)
xt "-105000,105800,-100300,106800"
st "Post User:"
blo "-105000,106600"
)
postUserText (MLText
uid 8,0
va (VaSet
font "Courier New,8,0"
)
xt "-105000,16200,-105000,16200"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 226,0
usingSuid 1
emptyRow *678 (LEmptyRow
)
uid 54,0
optionalChildren [
*679 (RefLabelRowHdr
)
*680 (TitleRowHdr
)
*681 (FilterRowHdr
)
*682 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*683 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*684 (GroupColHdr
tm "GroupColHdrMgr"
)
*685 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*686 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*687 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*688 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*689 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*690 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*691 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "write_ea"
t "std_logic_vector"
b "(0 downto 0)"
o 80
suid 2,0
i "\"0\""
)
)
uid 516,0
)
*692 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "addr_out"
t "std_logic_vector"
b "(RAMADDRWIDTH64b-1 DOWNTO 0)"
o 35
suid 3,0
)
)
uid 518,0
)
*693 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "data_out"
t "std_logic_vector"
b "(63 DOWNTO 0)"
o 53
suid 4,0
)
)
uid 520,0
)
*694 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ram_addr"
t "std_logic_vector"
b "(RAMADDRWIDTH64b+1 DOWNTO 0)"
o 62
suid 9,0
)
)
uid 530,0
)
*695 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ram_data"
t "std_logic_vector"
b "(15 downto 0)"
o 63
suid 10,0
)
)
uid 532,0
)
*696 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "wiz_reset"
t "std_logic"
o 28
suid 11,0
i "'1'"
)
)
uid 534,0
)
*697 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "wiz_addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 25
suid 12,0
)
)
uid 536,0
)
*698 (LeafLogPort
port (LogicalPort
m 2
decl (Decl
n "wiz_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 31
suid 13,0
)
)
uid 538,0
)
*699 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "wiz_cs"
t "std_logic"
o 26
suid 14,0
i "'1'"
)
)
uid 540,0
)
*700 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "wiz_wr"
t "std_logic"
o 29
suid 15,0
i "'1'"
)
)
uid 542,0
)
*701 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "wiz_rd"
t "std_logic"
o 27
suid 17,0
i "'1'"
)
)
uid 546,0
)
*702 (LeafLogPort
port (LogicalPort
decl (Decl
n "wiz_int"
t "std_logic"
o 11
suid 18,0
)
)
uid 548,0
)
*703 (LeafLogPort
port (LogicalPort
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 8
suid 28,0
)
)
uid 1455,0
)
*704 (LeafLogPort
port (LogicalPort
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 10
suid 29,0
)
)
uid 1457,0
)
*705 (LeafLogPort
port (LogicalPort
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
o 9
suid 30,0
)
)
uid 1694,0
)
*706 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "trigger_id"
t "std_logic_vector"
b "(47 downto 0)"
preAdd 0
posAdd 0
o 72
suid 34,0
)
)
uid 1993,0
)
*707 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAMADDRWIDTH64b-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 64
suid 36,0
)
)
uid 2305,0
)
*708 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "wiz_busy"
t "std_logic"
o 73
suid 38,0
)
)
uid 2510,0
)
*709 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "wiz_write_ea"
t "std_logic"
o 76
suid 39,0
i "'0'"
)
)
uid 2512,0
)
*710 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "wiz_write_length"
t "std_logic_vector"
b "(16 downto 0)"
o 79
suid 40,0
i "(others => '0')"
)
)
uid 2514,0
)
*711 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "wiz_ram_start_addr"
t "std_logic_vector"
b "(RAMADDRWIDTH64b+1 DOWNTO 0)"
preAdd 0
o 75
suid 41,0
i "(others => '0')"
)
)
uid 2516,0
)
*712 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "wiz_number_of_channels"
t "std_logic_vector"
b "(3 downto 0)"
o 74
suid 42,0
i "(others => '0')"
)
)
uid 2518,0
)
*713 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "wiz_write_end"
t "std_logic"
o 77
suid 43,0
i "'0'"
)
)
uid 2520,0
)
*714 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "wiz_write_header"
t "std_logic"
o 78
suid 44,0
i "'0'"
)
)
uid 2522,0
)
*715 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ram_write_ea"
t "std_logic"
o 65
suid 48,0
)
)
uid 2604,0
)
*716 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ram_write_ready"
t "std_logic"
o 66
suid 49,0
i "'0'"
)
)
uid 2606,0
)
*717 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "config_start"
t "std_logic"
o 44
suid 50,0
i "'0'"
)
)
uid 2608,0
)
*718 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "config_ready"
t "std_logic"
o 41
suid 51,0
)
)
uid 2610,0
)
*719 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "roi_max"
t "roi_max_type"
o 68
suid 52,0
)
)
uid 2612,0
)
*720 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "package_length"
t "std_logic_vector"
b "(15 downto 0)"
o 61
suid 54,0
)
)
uid 2646,0
)
*721 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "adc_oeb"
t "std_logic"
o 16
suid 57,0
i "'1'"
)
)
uid 2812,0
)
*722 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "roi_array"
t "roi_array_type"
o 67
suid 65,0
)
)
uid 2962,0
)
*723 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 12
suid 81,0
)
)
uid 3902,0
)
*724 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "CLK_50"
t "std_logic"
o 13
suid 90,0
)
)
uid 4070,0
)
*725 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "CLK_25"
t "std_logic"
o 32
suid 91,0
)
)
uid 4212,0
)
*726 (LeafLogPort
port (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 92,0
)
)
uid 4234,0
)
*727 (LeafLogPort
port (LogicalPort
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 7
suid 95,0
)
)
uid 4262,0
)
*728 (LeafLogPort
port (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 6
suid 96,0
)
)
uid 4276,0
)
*729 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_clk_en"
t "std_logic"
o 54
suid 97,0
i "'0'"
)
)
uid 4563,0
)
*730 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_s_cell_array"
t "drs_s_cell_array_type"
o 57
suid 98,0
)
)
uid 4565,0
)
*731 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_read_s_cell"
t "std_logic"
o 55
suid 100,0
i "'0'"
)
)
uid 4569,0
)
*732 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 19
suid 109,0
i "(others => '0')"
)
)
uid 4585,0
)
*733 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "drs_dwrite"
t "std_logic"
o 20
suid 110,0
i "'1'"
)
)
uid 4587,0
)
*734 (LeafLogPort
port (LogicalPort
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 2
suid 112,0
)
)
uid 4733,0
)
*735 (LeafLogPort
port (LogicalPort
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 3
suid 113,0
)
)
uid 4735,0
)
*736 (LeafLogPort
port (LogicalPort
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 4
suid 114,0
)
)
uid 4737,0
)
*737 (LeafLogPort
port (LogicalPort
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 5
suid 115,0
)
)
uid 4739,0
)
*738 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_read_s_cell_ready"
t "std_logic"
o 56
suid 116,0
)
)
uid 4749,0
)
*739 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "RSRLOAD"
t "std_logic"
o 14
suid 117,0
i "'0'"
)
)
uid 4974,0
)
*740 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "SRCLK"
t "std_logic"
o 15
suid 118,0
i "'0'"
)
)
uid 4976,0
)
*741 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "config_addr"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 36
suid 119,0
)
)
uid 5198,0
)
*742 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "config_data_valid"
t "std_logic"
o 39
suid 120,0
)
)
uid 5200,0
)
*743 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "config_busy"
t "std_logic"
o 37
suid 121,0
)
)
uid 5202,0
)
*744 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "config_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 38
suid 122,0
)
)
uid 5204,0
)
*745 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "config_wr_en"
t "std_logic"
o 51
suid 123,0
)
)
uid 5206,0
)
*746 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "config_rd_en"
t "std_logic"
o 40
suid 124,0
)
)
uid 5208,0
)
*747 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dac_array"
t "dac_array_type"
o 52
suid 126,0
)
)
uid 5210,0
)
*748 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "config_start_cm"
t "std_logic"
o 45
suid 131,0
)
)
uid 5212,0
)
*749 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "config_ready_cm"
t "std_logic"
o 42
suid 132,0
)
)
uid 5214,0
)
*750 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 21
suid 133,0
i "(OTHERS => '0')"
)
)
uid 5226,0
)
*751 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "s_trigger"
t "std_logic"
o 69
suid 134,0
i "'0'"
)
)
uid 5285,0
)
*752 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sensor_ready"
t "std_logic"
o 71
suid 140,0
)
)
uid 5502,0
)
*753 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sensor_array"
t "sensor_array_type"
o 70
suid 141,0
)
)
uid 5504,0
)
*754 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "config_ready_spi"
t "std_logic"
o 43
suid 144,0
)
)
uid 5600,0
)
*755 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "adc_otr"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 34
suid 146,0
)
)
uid 5642,0
)
*756 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_data_array_int"
t "adc_data_array_type"
o 33
suid 147,0
)
)
uid 5644,0
)
*757 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "config_start_spi"
t "std_logic"
o 46
suid 149,0
i "'0'"
)
)
uid 5751,0
)
*758 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "sclk"
t "std_logic"
o 23
suid 151,0
)
)
uid 5867,0
)
*759 (LeafLogPort
port (LogicalPort
m 2
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 30
suid 152,0
)
)
uid 5869,0
)
*760 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "dac_cs"
t "std_logic"
o 17
suid 153,0
)
)
uid 5871,0
)
*761 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 24
suid 154,0
)
)
uid 5873,0
)
*762 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "new_config"
t "std_logic"
o 60
suid 155,0
i "'0'"
)
)
uid 5966,0
)
*763 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "config_started"
t "std_logic"
o 47
suid 156,0
)
)
uid 5968,0
)
*764 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "config_started_spi"
t "std_logic"
o 50
suid 159,0
i "'0'"
)
)
uid 6022,0
)
*765 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "config_started_cu"
t "std_logic"
o 48
suid 160,0
i "'0'"
)
)
uid 6024,0
)
*766 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "config_started_mm"
t "std_logic"
o 49
suid 161,0
)
)
uid 6026,0
)
*767 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "mosi"
t "std_logic"
o 22
suid 162,0
i "'0'"
)
)
uid 6172,0
)
*768 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 18
suid 166,0
i "'0'"
)
)
uid 6374,0
)
*769 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dwrite_enable"
t "std_logic"
o 59
suid 167,0
i "'1'"
)
)
uid 6464,0
)
*770 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dwrite"
t "std_logic"
o 58
suid 169,0
i "'1'"
)
)
uid 6554,0
)
*771 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "wiz_ack"
t "std_logic"
o 81
suid 183,0
)
)
uid 8420,0
)
*772 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_address"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 82
suid 184,0
i "(others => '0')"
)
)
uid 8609,0
)
*773 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_address_mode"
t "std_logic"
o 83
suid 185,0
)
)
uid 8611,0
)
*774 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_channel_internal"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 84
suid 187,0
i "(others => '0')"
)
)
uid 8613,0
)
*775 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sclk1"
t "std_logic"
o 85
suid 191,0
)
)
uid 8758,0
)
*776 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sclk_enable"
t "std_logic"
o 86
suid 194,0
)
)
uid 8760,0
)
*777 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "adc_clk_en"
t "std_logic"
o 87
suid 195,0
i "'0'"
)
)
uid 9018,0
)
*778 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ps_direction"
t "std_logic"
eolc "-- default phase shift upwards"
posAdd 0
o 88
suid 196,0
i "'1'"
)
)
uid 9247,0
)
*779 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ps_do_phase_shift"
t "std_logic"
eolc "--pulse this to phase shift once"
preAdd 0
posAdd 0
o 89
suid 197,0
i "'0'"
)
)
uid 9249,0
)
*780 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "LOCKED_extraOUT"
t "std_logic"
o 90
suid 200,0
)
)
uid 9555,0
)
*781 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "PSDONE_extraOUT"
t "std_logic"
o 91
suid 201,0
)
)
uid 9557,0
)
*782 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "PSINCDEC_OUT"
t "std_logic"
o 92
suid 202,0
)
)
uid 9559,0
)
*783 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "PSEN_OUT"
t "std_logic"
o 93
suid 203,0
)
)
uid 9561,0
)
*784 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "PSCLK_OUT"
t "std_logic"
o 94
suid 204,0
)
)
uid 9563,0
)
*785 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "DCM_locked"
t "std_logic"
preAdd 0
posAdd 0
o 96
suid 206,0
)
)
uid 9567,0
)
*786 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "offset"
t "std_logic_vector"
b "(7 downto 0)"
preAdd 0
posAdd 0
o 97
suid 207,0
i "(OTHERS => '0')"
)
)
uid 9569,0
)
*787 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "shifting"
t "std_logic"
prec "-- status:"
preAdd 0
posAdd 0
o 98
suid 208,0
i "'0'"
)
)
uid 9571,0
)
*788 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "ready"
t "std_logic"
preAdd 0
posAdd 0
o 99
suid 209,0
i "'0'"
)
)
uid 9573,0
)
*789 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "PS_DIR_IN"
t "std_logic"
o 101
suid 213,0
)
)
uid 9575,0
)
*790 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "PS_DO_IN"
t "std_logic"
o 100
suid 214,0
)
)
uid 9577,0
)
*791 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "CLK50_OUT"
t "std_logic"
o 102
suid 216,0
)
)
uid 9801,0
)
*792 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "CLK25_OUT"
t "std_logic"
o 103
suid 218,0
)
)
uid 9803,0
)
*793 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "CLK25_PSOUT"
t "std_logic"
o 104
suid 220,0
)
)
uid 9805,0
)
*794 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ps_reset"
t "std_logic"
eolc "-- pulse this to reset the variable phase shift"
posAdd 0
o 104
suid 221,0
i "'0'"
)
)
uid 10024,0
)
*795 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "srclk_enable"
t "std_logic"
o 105
suid 222,0
i "'0'"
)
)
uid 10026,0
)
*796 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SRCLK1"
t "std_logic"
o 106
suid 224,0
i "'0'"
)
)
uid 10028,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 67,0
optionalChildren [
*797 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *798 (MRCItem
litem &678
pos 106
dimension 20
)
uid 69,0
optionalChildren [
*799 (MRCItem
litem &679
pos 0
dimension 20
uid 70,0
)
*800 (MRCItem
litem &680
pos 1
dimension 23
uid 71,0
)
*801 (MRCItem
litem &681
pos 2
hidden 1
dimension 20
uid 72,0
)
*802 (MRCItem
litem &691
pos 31
dimension 20
uid 517,0
)
*803 (MRCItem
litem &692
pos 32
dimension 20
uid 519,0
)
*804 (MRCItem
litem &693
pos 33
dimension 20
uid 521,0
)
*805 (MRCItem
litem &694
pos 34
dimension 20
uid 531,0
)
*806 (MRCItem
litem &695
pos 35
dimension 20
uid 533,0
)
*807 (MRCItem
litem &696
pos 0
dimension 20
uid 535,0
)
*808 (MRCItem
litem &697
pos 1
dimension 20
uid 537,0
)
*809 (MRCItem
litem &698
pos 2
dimension 20
uid 539,0
)
*810 (MRCItem
litem &699
pos 3
dimension 20
uid 541,0
)
*811 (MRCItem
litem &700
pos 4
dimension 20
uid 543,0
)
*812 (MRCItem
litem &701
pos 5
dimension 20
uid 547,0
)
*813 (MRCItem
litem &702
pos 6
dimension 20
uid 549,0
)
*814 (MRCItem
litem &703
pos 8
dimension 20
uid 1456,0
)
*815 (MRCItem
litem &704
pos 7
dimension 20
uid 1458,0
)
*816 (MRCItem
litem &705
pos 9
dimension 20
uid 1695,0
)
*817 (MRCItem
litem &706
pos 36
dimension 20
uid 1994,0
)
*818 (MRCItem
litem &707
pos 37
dimension 20
uid 2306,0
)
*819 (MRCItem
litem &708
pos 38
dimension 20
uid 2511,0
)
*820 (MRCItem
litem &709
pos 39
dimension 20
uid 2513,0
)
*821 (MRCItem
litem &710
pos 40
dimension 20
uid 2515,0
)
*822 (MRCItem
litem &711
pos 41
dimension 20
uid 2517,0
)
*823 (MRCItem
litem &712
pos 42
dimension 20
uid 2519,0
)
*824 (MRCItem
litem &713
pos 43
dimension 20
uid 2521,0
)
*825 (MRCItem
litem &714
pos 44
dimension 20
uid 2523,0
)
*826 (MRCItem
litem &715
pos 45
dimension 20
uid 2605,0
)
*827 (MRCItem
litem &716
pos 46
dimension 20
uid 2607,0
)
*828 (MRCItem
litem &717
pos 47
dimension 20
uid 2609,0
)
*829 (MRCItem
litem &718
pos 48
dimension 20
uid 2611,0
)
*830 (MRCItem
litem &719
pos 49
dimension 20
uid 2613,0
)
*831 (MRCItem
litem &720
pos 50
dimension 20
uid 2647,0
)
*832 (MRCItem
litem &721
pos 10
dimension 20
uid 2813,0
)
*833 (MRCItem
litem &722
pos 51
dimension 20
uid 2963,0
)
*834 (MRCItem
litem &723
pos 11
dimension 20
uid 3903,0
)
*835 (MRCItem
litem &724
pos 12
dimension 20
uid 4071,0
)
*836 (MRCItem
litem &725
pos 52
dimension 20
uid 4213,0
)
*837 (MRCItem
litem &726
pos 13
dimension 20
uid 4235,0
)
*838 (MRCItem
litem &727
pos 14
dimension 20
uid 4263,0
)
*839 (MRCItem
litem &728
pos 15
dimension 20
uid 4277,0
)
*840 (MRCItem
litem &729
pos 53
dimension 20
uid 4564,0
)
*841 (MRCItem
litem &730
pos 54
dimension 20
uid 4566,0
)
*842 (MRCItem
litem &731
pos 55
dimension 20
uid 4570,0
)
*843 (MRCItem
litem &732
pos 16
dimension 20
uid 4586,0
)
*844 (MRCItem
litem &733
pos 17
dimension 20
uid 4588,0
)
*845 (MRCItem
litem &734
pos 18
dimension 20
uid 4734,0
)
*846 (MRCItem
litem &735
pos 19
dimension 20
uid 4736,0
)
*847 (MRCItem
litem &736
pos 20
dimension 20
uid 4738,0
)
*848 (MRCItem
litem &737
pos 21
dimension 20
uid 4740,0
)
*849 (MRCItem
litem &738
pos 56
dimension 20
uid 4750,0
)
*850 (MRCItem
litem &739
pos 22
dimension 20
uid 4975,0
)
*851 (MRCItem
litem &740
pos 23
dimension 20
uid 4977,0
)
*852 (MRCItem
litem &741
pos 57
dimension 20
uid 5199,0
)
*853 (MRCItem
litem &742
pos 58
dimension 20
uid 5201,0
)
*854 (MRCItem
litem &743
pos 59
dimension 20
uid 5203,0
)
*855 (MRCItem
litem &744
pos 60
dimension 20
uid 5205,0
)
*856 (MRCItem
litem &745
pos 61
dimension 20
uid 5207,0
)
*857 (MRCItem
litem &746
pos 62
dimension 20
uid 5209,0
)
*858 (MRCItem
litem &747
pos 63
dimension 20
uid 5211,0
)
*859 (MRCItem
litem &748
pos 64
dimension 20
uid 5213,0
)
*860 (MRCItem
litem &749
pos 65
dimension 20
uid 5215,0
)
*861 (MRCItem
litem &750
pos 24
dimension 20
uid 5227,0
)
*862 (MRCItem
litem &751
pos 66
dimension 20
uid 5286,0
)
*863 (MRCItem
litem &752
pos 67
dimension 20
uid 5503,0
)
*864 (MRCItem
litem &753
pos 68
dimension 20
uid 5505,0
)
*865 (MRCItem
litem &754
pos 69
dimension 20
uid 5601,0
)
*866 (MRCItem
litem &755
pos 70
dimension 20
uid 5643,0
)
*867 (MRCItem
litem &756
pos 71
dimension 20
uid 5645,0
)
*868 (MRCItem
litem &757
pos 72
dimension 20
uid 5752,0
)
*869 (MRCItem
litem &758
pos 25
dimension 20
uid 5868,0
)
*870 (MRCItem
litem &759
pos 26
dimension 20
uid 5870,0
)
*871 (MRCItem
litem &760
pos 27
dimension 20
uid 5872,0
)
*872 (MRCItem
litem &761
pos 28
dimension 20
uid 5874,0
)
*873 (MRCItem
litem &762
pos 73
dimension 20
uid 5967,0
)
*874 (MRCItem
litem &763
pos 74
dimension 20
uid 5969,0
)
*875 (MRCItem
litem &764
pos 75
dimension 20
uid 6023,0
)
*876 (MRCItem
litem &765
pos 76
dimension 20
uid 6025,0
)
*877 (MRCItem
litem &766
pos 77
dimension 20
uid 6027,0
)
*878 (MRCItem
litem &767
pos 29
dimension 20
uid 6173,0
)
*879 (MRCItem
litem &768
pos 30
dimension 20
uid 6375,0
)
*880 (MRCItem
litem &769
pos 78
dimension 20
uid 6465,0
)
*881 (MRCItem
litem &770
pos 79
dimension 20
uid 6555,0
)
*882 (MRCItem
litem &771
pos 80
dimension 20
uid 8421,0
)
*883 (MRCItem
litem &772
pos 81
dimension 20
uid 8610,0
)
*884 (MRCItem
litem &773
pos 82
dimension 20
uid 8612,0
)
*885 (MRCItem
litem &774
pos 83
dimension 20
uid 8614,0
)
*886 (MRCItem
litem &775
pos 84
dimension 20
uid 8759,0
)
*887 (MRCItem
litem &776
pos 85
dimension 20
uid 8761,0
)
*888 (MRCItem
litem &777
pos 86
dimension 20
uid 9019,0
)
*889 (MRCItem
litem &778
pos 87
dimension 20
uid 9248,0
)
*890 (MRCItem
litem &779
pos 88
dimension 20
uid 9250,0
)
*891 (MRCItem
litem &780
pos 89
dimension 20
uid 9556,0
)
*892 (MRCItem
litem &781
pos 90
dimension 20
uid 9558,0
)
*893 (MRCItem
litem &782
pos 91
dimension 20
uid 9560,0
)
*894 (MRCItem
litem &783
pos 92
dimension 20
uid 9562,0
)
*895 (MRCItem
litem &784
pos 93
dimension 20
uid 9564,0
)
*896 (MRCItem
litem &785
pos 94
dimension 20
uid 9568,0
)
*897 (MRCItem
litem &786
pos 95
dimension 20
uid 9570,0
)
*898 (MRCItem
litem &787
pos 96
dimension 20
uid 9572,0
)
*899 (MRCItem
litem &788
pos 97
dimension 20
uid 9574,0
)
*900 (MRCItem
litem &789
pos 98
dimension 20
uid 9576,0
)
*901 (MRCItem
litem &790
pos 99
dimension 20
uid 9578,0
)
*902 (MRCItem
litem &791
pos 100
dimension 20
uid 9802,0
)
*903 (MRCItem
litem &792
pos 101
dimension 20
uid 9804,0
)
*904 (MRCItem
litem &793
pos 102
dimension 20
uid 9806,0
)
*905 (MRCItem
litem &794
pos 103
dimension 20
uid 10025,0
)
*906 (MRCItem
litem &795
pos 104
dimension 20
uid 10027,0
)
*907 (MRCItem
litem &796
pos 105
dimension 20
uid 10029,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 73,0
optionalChildren [
*908 (MRCItem
litem &682
pos 0
dimension 20
uid 74,0
)
*909 (MRCItem
litem &684
pos 1
dimension 50
uid 75,0
)
*910 (MRCItem
litem &685
pos 2
dimension 100
uid 76,0
)
*911 (MRCItem
litem &686
pos 3
dimension 50
uid 77,0
)
*912 (MRCItem
litem &687
pos 4
dimension 100
uid 78,0
)
*913 (MRCItem
litem &688
pos 5
dimension 100
uid 79,0
)
*914 (MRCItem
litem &689
pos 6
dimension 50
uid 80,0
)
*915 (MRCItem
litem &690
pos 7
dimension 80
uid 81,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 68,0
vaOverrides [
]
)
]
)
uid 53,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *916 (LEmptyRow
)
uid 83,0
optionalChildren [
*917 (RefLabelRowHdr
)
*918 (TitleRowHdr
)
*919 (FilterRowHdr
)
*920 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*921 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*922 (GroupColHdr
tm "GroupColHdrMgr"
)
*923 (NameColHdr
tm "GenericNameColHdrMgr"
)
*924 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*925 (InitColHdr
tm "GenericValueColHdrMgr"
)
*926 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*927 (EolColHdr
tm "GenericEolColHdrMgr"
)
*928 (LogGeneric
generic (GiElement
name "RAMADDRWIDTH64b"
type "integer"
value "12"
)
uid 6712,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 95,0
optionalChildren [
*929 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *930 (MRCItem
litem &916
pos 1
dimension 20
)
uid 97,0
optionalChildren [
*931 (MRCItem
litem &917
pos 0
dimension 20
uid 98,0
)
*932 (MRCItem
litem &918
pos 1
dimension 23
uid 99,0
)
*933 (MRCItem
litem &919
pos 2
hidden 1
dimension 20
uid 100,0
)
*934 (MRCItem
litem &928
pos 0
dimension 20
uid 6713,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 101,0
optionalChildren [
*935 (MRCItem
litem &920
pos 0
dimension 20
uid 102,0
)
*936 (MRCItem
litem &922
pos 1
dimension 50
uid 103,0
)
*937 (MRCItem
litem &923
pos 2
dimension 186
uid 104,0
)
*938 (MRCItem
litem &924
pos 3
dimension 96
uid 105,0
)
*939 (MRCItem
litem &925
pos 4
dimension 50
uid 106,0
)
*940 (MRCItem
litem &926
pos 5
dimension 50
uid 107,0
)
*941 (MRCItem
litem &927
pos 6
dimension 80
uid 108,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 96,0
vaOverrides [
]
)
]
)
uid 82,0
type 1
)
activeModelName "BlockDiag"
)
