DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "std_logic_arith"
)
]
libraryRefs [
"ieee"
]
)
version "24.1"
appVersion "2009.2 (Build 10)"
model (Symbol
commonDM (CommonDM
ldm (LogicalDM
suid 68,0
usingSuid 1
emptyRow *1 (LEmptyRow
)
uid 53,0
optionalChildren [
*2 (RefLabelRowHdr
)
*3 (TitleRowHdr
)
*4 (FilterRowHdr
)
*5 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*6 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*7 (GroupColHdr
tm "GroupColHdrMgr"
)
*8 (NameColHdr
tm "NameColHdrMgr"
)
*9 (ModeColHdr
tm "ModeColHdrMgr"
)
*10 (TypeColHdr
tm "TypeColHdrMgr"
)
*11 (BoundsColHdr
tm "BoundsColHdrMgr"
)
*12 (InitColHdr
tm "InitColHdrMgr"
)
*13 (EolColHdr
tm "EolColHdrMgr"
)
*14 (LogPort
port (LogicalPort
m 1
decl (Decl
n "RSRLOAD"
t "std_logic"
o 35
suid 11,0
i "'0'"
)
)
uid 690,0
)
*15 (LogPort
port (LogicalPort
decl (Decl
n "X_50M"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 13
suid 15,0
)
)
uid 1111,0
)
*16 (LogPort
port (LogicalPort
decl (Decl
n "TRG"
t "STD_LOGIC"
o 11
suid 16,0
)
)
uid 1113,0
)
*17 (LogPort
port (LogicalPort
m 1
decl (Decl
n "A_CLK"
t "std_logic_vector"
b "(3 downto 0)"
o 16
suid 17,0
)
)
uid 1115,0
)
*18 (LogPort
port (LogicalPort
m 1
decl (Decl
n "OE_ADC"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 30
suid 18,0
)
)
uid 1155,0
)
*19 (LogPort
port (LogicalPort
decl (Decl
n "A_OTR"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 5
suid 19,0
)
)
uid 1157,0
)
*20 (LogPort
port (LogicalPort
decl (Decl
n "A0_D"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 1
suid 20,0
)
)
uid 1159,0
)
*21 (LogPort
port (LogicalPort
decl (Decl
n "A1_D"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 2
suid 21,0
)
)
uid 1161,0
)
*22 (LogPort
port (LogicalPort
decl (Decl
n "A2_D"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 3
suid 22,0
)
)
uid 1163,0
)
*23 (LogPort
port (LogicalPort
decl (Decl
n "A3_D"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 4
suid 23,0
)
)
uid 1165,0
)
*24 (LogPort
port (LogicalPort
m 1
decl (Decl
n "D0_SRCLK"
t "STD_LOGIC"
o 17
suid 24,0
)
)
uid 1220,0
)
*25 (LogPort
port (LogicalPort
m 1
decl (Decl
n "D1_SRCLK"
t "STD_LOGIC"
o 18
suid 25,0
)
)
uid 1222,0
)
*26 (LogPort
port (LogicalPort
m 1
decl (Decl
n "D2_SRCLK"
t "STD_LOGIC"
o 19
suid 26,0
)
)
uid 1224,0
)
*27 (LogPort
port (LogicalPort
m 1
decl (Decl
n "D3_SRCLK"
t "STD_LOGIC"
o 20
suid 27,0
)
)
uid 1226,0
)
*28 (LogPort
port (LogicalPort
decl (Decl
n "D0_SROUT"
t "std_logic"
o 6
suid 28,0
)
)
uid 1271,0
)
*29 (LogPort
port (LogicalPort
decl (Decl
n "D1_SROUT"
t "std_logic"
o 7
suid 29,0
)
)
uid 1273,0
)
*30 (LogPort
port (LogicalPort
decl (Decl
n "D2_SROUT"
t "std_logic"
o 8
suid 30,0
)
)
uid 1275,0
)
*31 (LogPort
port (LogicalPort
decl (Decl
n "D3_SROUT"
t "std_logic"
o 9
suid 31,0
)
)
uid 1277,0
)
*32 (LogPort
port (LogicalPort
m 1
decl (Decl
n "D_A"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 24
suid 32,0
i "(others => '0')"
)
)
uid 1279,0
)
*33 (LogPort
port (LogicalPort
m 1
decl (Decl
n "DWRITE"
t "std_logic"
o 23
suid 33,0
i "'0'"
)
)
uid 1281,0
)
*34 (LogPort
port (LogicalPort
m 1
decl (Decl
n "DAC_CS"
t "std_logic"
o 21
suid 34,0
)
)
uid 1338,0
)
*35 (LogPort
port (LogicalPort
m 1
decl (Decl
n "T0_CS"
t "std_logic"
o 38
suid 35,0
)
)
uid 1340,0
)
*36 (LogPort
port (LogicalPort
m 1
decl (Decl
n "T1_CS"
t "std_logic"
o 39
suid 36,0
)
)
uid 1342,0
)
*37 (LogPort
port (LogicalPort
m 1
decl (Decl
n "T2_CS"
t "std_logic"
o 40
suid 37,0
)
)
uid 1344,0
)
*38 (LogPort
port (LogicalPort
m 1
decl (Decl
n "T3_CS"
t "std_logic"
o 41
suid 38,0
)
)
uid 1346,0
)
*39 (LogPort
port (LogicalPort
m 1
decl (Decl
n "S_CLK"
t "std_logic"
o 37
suid 39,0
)
)
uid 1348,0
)
*40 (LogPort
port (LogicalPort
m 1
decl (Decl
n "W_A"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 43
suid 40,0
)
)
uid 1350,0
)
*41 (LogPort
port (LogicalPort
m 2
decl (Decl
n "W_D"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 49
suid 41,0
)
)
uid 1352,0
)
*42 (LogPort
port (LogicalPort
m 1
decl (Decl
n "W_RES"
t "std_logic"
o 46
suid 42,0
i "'1'"
)
)
uid 1354,0
)
*43 (LogPort
port (LogicalPort
m 1
decl (Decl
n "W_RD"
t "std_logic"
o 45
suid 43,0
i "'1'"
)
)
uid 1356,0
)
*44 (LogPort
port (LogicalPort
m 1
decl (Decl
n "W_WR"
t "std_logic"
o 47
suid 44,0
i "'1'"
)
)
uid 1358,0
)
*45 (LogPort
port (LogicalPort
decl (Decl
n "W_INT"
t "std_logic"
o 12
suid 45,0
)
)
uid 1360,0
)
*46 (LogPort
port (LogicalPort
m 1
decl (Decl
n "W_CS"
t "std_logic"
o 44
suid 46,0
i "'1'"
)
)
uid 1362,0
)
*47 (LogPort
port (LogicalPort
m 1
decl (Decl
n "MOSI"
t "std_logic"
o 29
suid 47,0
i "'0'"
)
)
uid 1617,0
)
*48 (LogPort
port (LogicalPort
m 2
decl (Decl
n "MISO"
t "std_logic"
preAdd 0
posAdd 0
o 48
suid 48,0
)
)
uid 1619,0
)
*49 (LogPort
port (LogicalPort
m 1
decl (Decl
n "TRG_V"
t "std_logic"
o 42
suid 49,0
)
)
uid 1655,0
)
*50 (LogPort
port (LogicalPort
m 1
decl (Decl
n "RS485_C_RE"
t "std_logic"
o 32
suid 50,0
)
)
uid 1657,0
)
*51 (LogPort
port (LogicalPort
m 1
decl (Decl
n "RS485_C_DE"
t "std_logic"
o 31
suid 51,0
)
)
uid 1659,0
)
*52 (LogPort
port (LogicalPort
m 1
decl (Decl
n "RS485_E_RE"
t "std_logic"
o 34
suid 52,0
)
)
uid 1661,0
)
*53 (LogPort
port (LogicalPort
m 1
decl (Decl
n "RS485_E_DE"
t "std_logic"
o 33
suid 53,0
)
)
uid 1663,0
)
*54 (LogPort
port (LogicalPort
m 1
decl (Decl
n "DENABLE"
t "std_logic"
o 22
suid 54,0
i "'0'"
)
)
uid 1665,0
)
*55 (LogPort
port (LogicalPort
m 1
decl (Decl
n "SRIN"
t "std_logic"
o 36
suid 55,0
)
)
uid 1667,0
)
*56 (LogPort
port (LogicalPort
m 1
decl (Decl
n "EE_CS"
t "std_logic"
o 27
suid 56,0
)
)
uid 1669,0
)
*57 (LogPort
port (LogicalPort
m 1
decl (Decl
n "D_T"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 25
suid 61,0
i "(OTHERS => '0')"
)
)
uid 2067,0
)
*58 (LogPort
port (LogicalPort
m 1
decl (Decl
n "LED"
t "std_logic_vector"
b "( 2 DOWNTO 0 )"
o 28
suid 62,0
i "(others => '1')"
)
)
uid 2374,0
)
*59 (LogPort
port (LogicalPort
decl (Decl
n "D_PLLLCK"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 10
suid 64,0
)
)
uid 2918,0
)
*60 (LogPort
port (LogicalPort
m 1
decl (Decl
n "D_T2"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 26
suid 65,0
i "(others => '0')"
)
)
uid 2948,0
)
*61 (LogPort
port (LogicalPort
m 1
decl (Decl
n "A1_T"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 15
suid 66,0
i "(OTHERS => '0')"
)
)
uid 3025,0
)
*62 (LogPort
port (LogicalPort
m 1
decl (Decl
n "A0_T"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 14
suid 68,0
i "(others => '0')"
)
)
uid 3455,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 66,0
optionalChildren [
*63 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *64 (MRCItem
litem &1
pos 3
dimension 20
)
uid 68,0
optionalChildren [
*65 (MRCItem
litem &2
pos 0
dimension 20
uid 69,0
)
*66 (MRCItem
litem &3
pos 1
dimension 23
uid 70,0
)
*67 (MRCItem
litem &4
pos 2
hidden 1
dimension 20
uid 71,0
)
*68 (MRCItem
litem &14
pos 0
dimension 20
uid 689,0
)
*69 (MRCItem
litem &15
pos 2
dimension 20
uid 1110,0
)
*70 (MRCItem
litem &16
pos 3
dimension 20
uid 1112,0
)
*71 (MRCItem
litem &17
pos 4
dimension 20
uid 1114,0
)
*72 (MRCItem
litem &18
pos 5
dimension 20
uid 1154,0
)
*73 (MRCItem
litem &19
pos 6
dimension 20
uid 1156,0
)
*74 (MRCItem
litem &20
pos 7
dimension 20
uid 1158,0
)
*75 (MRCItem
litem &21
pos 8
dimension 20
uid 1160,0
)
*76 (MRCItem
litem &22
pos 9
dimension 20
uid 1162,0
)
*77 (MRCItem
litem &23
pos 10
dimension 20
uid 1164,0
)
*78 (MRCItem
litem &24
pos 11
dimension 20
uid 1219,0
)
*79 (MRCItem
litem &25
pos 12
dimension 20
uid 1221,0
)
*80 (MRCItem
litem &26
pos 13
dimension 20
uid 1223,0
)
*81 (MRCItem
litem &27
pos 14
dimension 20
uid 1225,0
)
*82 (MRCItem
litem &28
pos 15
dimension 20
uid 1270,0
)
*83 (MRCItem
litem &29
pos 16
dimension 20
uid 1272,0
)
*84 (MRCItem
litem &30
pos 17
dimension 20
uid 1274,0
)
*85 (MRCItem
litem &31
pos 18
dimension 20
uid 1276,0
)
*86 (MRCItem
litem &32
pos 19
dimension 20
uid 1278,0
)
*87 (MRCItem
litem &33
pos 20
dimension 20
uid 1280,0
)
*88 (MRCItem
litem &34
pos 1
dimension 20
uid 1337,0
)
*89 (MRCItem
litem &35
pos 21
dimension 20
uid 1339,0
)
*90 (MRCItem
litem &36
pos 22
dimension 20
uid 1341,0
)
*91 (MRCItem
litem &37
pos 23
dimension 20
uid 1343,0
)
*92 (MRCItem
litem &38
pos 24
dimension 20
uid 1345,0
)
*93 (MRCItem
litem &39
pos 25
dimension 20
uid 1347,0
)
*94 (MRCItem
litem &40
pos 26
dimension 20
uid 1349,0
)
*95 (MRCItem
litem &41
pos 27
dimension 20
uid 1351,0
)
*96 (MRCItem
litem &42
pos 28
dimension 20
uid 1353,0
)
*97 (MRCItem
litem &43
pos 29
dimension 20
uid 1355,0
)
*98 (MRCItem
litem &44
pos 30
dimension 20
uid 1357,0
)
*99 (MRCItem
litem &45
pos 31
dimension 20
uid 1359,0
)
*100 (MRCItem
litem &46
pos 32
dimension 20
uid 1361,0
)
*101 (MRCItem
litem &47
pos 33
dimension 20
uid 1616,0
)
*102 (MRCItem
litem &48
pos 34
dimension 20
uid 1618,0
)
*103 (MRCItem
litem &49
pos 35
dimension 20
uid 1654,0
)
*104 (MRCItem
litem &50
pos 36
dimension 20
uid 1656,0
)
*105 (MRCItem
litem &51
pos 37
dimension 20
uid 1658,0
)
*106 (MRCItem
litem &52
pos 38
dimension 20
uid 1660,0
)
*107 (MRCItem
litem &53
pos 39
dimension 20
uid 1662,0
)
*108 (MRCItem
litem &54
pos 40
dimension 20
uid 1664,0
)
*109 (MRCItem
litem &55
pos 41
dimension 20
uid 1666,0
)
*110 (MRCItem
litem &56
pos 42
dimension 20
uid 1668,0
)
*111 (MRCItem
litem &57
pos 44
dimension 20
uid 2066,0
)
*112 (MRCItem
litem &58
pos 43
dimension 20
uid 2373,0
)
*113 (MRCItem
litem &59
pos 45
dimension 20
uid 2917,0
)
*114 (MRCItem
litem &60
pos 46
dimension 20
uid 2947,0
)
*115 (MRCItem
litem &61
pos 47
dimension 20
uid 3024,0
)
*116 (MRCItem
litem &62
pos 48
dimension 20
uid 3454,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 72,0
optionalChildren [
*117 (MRCItem
litem &5
pos 0
dimension 20
uid 73,0
)
*118 (MRCItem
litem &7
pos 1
dimension 50
uid 74,0
)
*119 (MRCItem
litem &8
pos 2
dimension 100
uid 75,0
)
*120 (MRCItem
litem &9
pos 3
dimension 50
uid 76,0
)
*121 (MRCItem
litem &10
pos 4
dimension 100
uid 77,0
)
*122 (MRCItem
litem &11
pos 5
dimension 100
uid 78,0
)
*123 (MRCItem
litem &12
pos 6
dimension 50
uid 79,0
)
*124 (MRCItem
litem &13
pos 7
dimension 80
uid 80,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 67,0
vaOverrides [
]
)
]
)
uid 52,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *125 (LEmptyRow
)
uid 82,0
optionalChildren [
*126 (RefLabelRowHdr
)
*127 (TitleRowHdr
)
*128 (FilterRowHdr
)
*129 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*130 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*131 (GroupColHdr
tm "GroupColHdrMgr"
)
*132 (NameColHdr
tm "GenericNameColHdrMgr"
)
*133 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*134 (InitColHdr
tm "GenericValueColHdrMgr"
)
*135 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*136 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 94,0
optionalChildren [
*137 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *138 (MRCItem
litem &125
pos 3
dimension 20
)
uid 96,0
optionalChildren [
*139 (MRCItem
litem &126
pos 0
dimension 20
uid 97,0
)
*140 (MRCItem
litem &127
pos 1
dimension 23
uid 98,0
)
*141 (MRCItem
litem &128
pos 2
hidden 1
dimension 20
uid 99,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 100,0
optionalChildren [
*142 (MRCItem
litem &129
pos 0
dimension 20
uid 101,0
)
*143 (MRCItem
litem &131
pos 1
dimension 50
uid 102,0
)
*144 (MRCItem
litem &132
pos 2
dimension 100
uid 103,0
)
*145 (MRCItem
litem &133
pos 3
dimension 100
uid 104,0
)
*146 (MRCItem
litem &134
pos 4
dimension 50
uid 105,0
)
*147 (MRCItem
litem &135
pos 5
dimension 50
uid 106,0
)
*148 (MRCItem
litem &136
pos 6
dimension 80
uid 107,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 95,0
vaOverrides [
]
)
]
)
uid 81,0
type 1
)
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user"
)
(vvPair
variable "SourceDir"
value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "symbol"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board"
)
(vvPair
variable "d_logical"
value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_Board"
)
(vvPair
variable "date"
value "27.08.2010"
)
(vvPair
variable "day"
value "Fr"
)
(vvPair
variable "day_long"
value "Freitag"
)
(vvPair
variable "dd"
value "27"
)
(vvPair
variable "entity_name"
value "FAD_Board"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "symbol.sb"
)
(vvPair
variable "f_logical"
value "symbol.sb"
)
(vvPair
variable "f_noext"
value "symbol"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "E5B-LABOR6"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_lib"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/work"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "mm"
value "08"
)
(vvPair
variable "module_name"
value "FAD_Board"
)
(vvPair
variable "month"
value "Aug"
)
(vvPair
variable "month_long"
value "August"
)
(vvPair
variable "p"
value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb"
)
(vvPair
variable "p_logical"
value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "<TBD>"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "sb"
)
(vvPair
variable "this_file"
value "symbol"
)
(vvPair
variable "this_file_logical"
value "symbol"
)
(vvPair
variable "time"
value "17:10:56"
)
(vvPair
variable "unit"
value "FAD_Board"
)
(vvPair
variable "user"
value "dneise"
)
(vvPair
variable "version"
value "2009.2 (Build 10)"
)
(vvPair
variable "view"
value "symbol"
)
(vvPair
variable "year"
value "2010"
)
(vvPair
variable "yy"
value "10"
)
]
)
LanguageMgr "VhdlLangMgr"
uid 51,0
optionalChildren [
*149 (SymbolBody
uid 8,0
optionalChildren [
*150 (CptPort
uid 693,0
ps "OnEdgeStrategy"
shape (Triangle
uid 694,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,21625,33750,22375"
)
tg (CPTG
uid 695,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 696,0
va (VaSet
)
xt "27800,21500,32000,22500"
st "RSRLOAD"
ju 2
blo "32000,22300"
tm "CptPortNameMgr"
)
t (Text
uid 697,0
va (VaSet
)
xt "30800,22500,32000,23500"
st "'0'"
ju 2
blo "32000,23300"
tm "InitValueDelayMgr"
)
)
dt (MLText
uid 698,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,29200,76000,30000"
st "RSRLOAD    : OUT    std_logic                       := '0' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "RSRLOAD"
t "std_logic"
o 35
suid 11,0
i "'0'"
)
)
)
*151 (CptPort
uid 1116,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1117,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,11625,15000,12375"
)
tg (CPTG
uid 1118,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1119,0
va (VaSet
)
xt "16000,11500,18800,12500"
st "X_50M"
blo "16000,12300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1120,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,11600,61500,12400"
st "X_50M      : IN     STD_LOGIC  ;"
)
thePort (LogicalPort
decl (Decl
n "X_50M"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 13
suid 15,0
)
)
)
*152 (CptPort
uid 1121,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1122,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,13625,15000,14375"
)
tg (CPTG
uid 1123,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1124,0
va (VaSet
)
xt "16000,13500,18100,14500"
st "TRG"
blo "16000,14300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1125,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10000,61500,10800"
st "TRG        : IN     STD_LOGIC  ;"
)
thePort (LogicalPort
decl (Decl
n "TRG"
t "STD_LOGIC"
o 11
suid 16,0
)
)
)
*153 (CptPort
uid 1126,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1127,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,25625,33750,26375"
)
tg (CPTG
uid 1128,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1129,0
va (VaSet
)
xt "26600,25500,32000,26500"
st "A_CLK : (3:0)"
ju 2
blo "32000,26300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1130,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,14000,71500,14800"
st "A_CLK      : OUT    std_logic_vector (3 downto 0) ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "A_CLK"
t "std_logic_vector"
b "(3 downto 0)"
o 16
suid 17,0
)
)
)
*154 (CptPort
uid 1166,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1167,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,27625,33750,28375"
)
tg (CPTG
uid 1168,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1169,0
va (VaSet
)
xt "28400,27500,32000,28500"
st "OE_ADC"
ju 2
blo "32000,28300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1170,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,25200,61500,26000"
st "OE_ADC     : OUT    STD_LOGIC  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "OE_ADC"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 30
suid 18,0
)
)
)
*155 (CptPort
uid 1171,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1172,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,15625,15000,16375"
)
tg (CPTG
uid 1173,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1174,0
va (VaSet
)
xt "16000,15500,21600,16500"
st "A_OTR : (3:0)"
blo "16000,16300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1175,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,5200,71500,6000"
st "A_OTR      : IN     std_logic_vector (3 DOWNTO 0) ;"
)
thePort (LogicalPort
decl (Decl
n "A_OTR"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 5
suid 19,0
)
)
)
*156 (CptPort
uid 1176,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1177,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,17625,15000,18375"
)
tg (CPTG
uid 1178,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1179,0
va (VaSet
)
xt "16000,17500,21300,18500"
st "A0_D : (11:0)"
blo "16000,18300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1180,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2000,72000,2800"
st "A0_D       : IN     std_logic_vector (11 DOWNTO 0) ;"
)
thePort (LogicalPort
decl (Decl
n "A0_D"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 1
suid 20,0
)
)
)
*157 (CptPort
uid 1181,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1182,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,19625,15000,20375"
)
tg (CPTG
uid 1183,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1184,0
va (VaSet
)
xt "16000,19500,21300,20500"
st "A1_D : (11:0)"
blo "16000,20300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1185,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2800,72000,3600"
st "A1_D       : IN     std_logic_vector (11 DOWNTO 0) ;"
)
thePort (LogicalPort
decl (Decl
n "A1_D"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 2
suid 21,0
)
)
)
*158 (CptPort
uid 1186,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1187,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,21625,15000,22375"
)
tg (CPTG
uid 1188,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1189,0
va (VaSet
)
xt "16000,21500,21300,22500"
st "A2_D : (11:0)"
blo "16000,22300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1190,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,3600,72000,4400"
st "A2_D       : IN     std_logic_vector (11 DOWNTO 0) ;"
)
thePort (LogicalPort
decl (Decl
n "A2_D"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 3
suid 22,0
)
)
)
*159 (CptPort
uid 1191,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1192,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,23625,15000,24375"
)
tg (CPTG
uid 1193,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1194,0
va (VaSet
)
xt "16000,23500,21300,24500"
st "A3_D : (11:0)"
blo "16000,24300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1195,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4400,72000,5200"
st "A3_D       : IN     std_logic_vector (11 DOWNTO 0) ;"
)
thePort (LogicalPort
decl (Decl
n "A3_D"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 4
suid 23,0
)
)
)
*160 (CptPort
uid 1227,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1777,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,83625,33750,84375"
)
tg (CPTG
uid 1229,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1230,0
va (VaSet
)
xt "27600,83500,32000,84500"
st "D0_SRCLK"
ju 2
blo "32000,84300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1231,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,14800,61500,15600"
st "D0_SRCLK   : OUT    STD_LOGIC  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "D0_SRCLK"
t "STD_LOGIC"
o 17
suid 24,0
)
)
)
*161 (CptPort
uid 1232,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1778,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,85625,33750,86375"
)
tg (CPTG
uid 1234,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1235,0
va (VaSet
)
xt "27600,85500,32000,86500"
st "D1_SRCLK"
ju 2
blo "32000,86300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1236,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,15600,61500,16400"
st "D1_SRCLK   : OUT    STD_LOGIC  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "D1_SRCLK"
t "STD_LOGIC"
o 18
suid 25,0
)
)
)
*162 (CptPort
uid 1237,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1779,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,87625,33750,88375"
)
tg (CPTG
uid 1239,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1240,0
va (VaSet
)
xt "27600,87500,32000,88500"
st "D2_SRCLK"
ju 2
blo "32000,88300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1241,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,16400,61500,17200"
st "D2_SRCLK   : OUT    STD_LOGIC  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "D2_SRCLK"
t "STD_LOGIC"
o 19
suid 26,0
)
)
)
*163 (CptPort
uid 1242,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1780,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,89625,33750,90375"
)
tg (CPTG
uid 1244,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1245,0
va (VaSet
)
xt "27600,89500,32000,90500"
st "D3_SRCLK"
ju 2
blo "32000,90300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1246,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,17200,61500,18000"
st "D3_SRCLK   : OUT    STD_LOGIC  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "D3_SRCLK"
t "STD_LOGIC"
o 20
suid 27,0
)
)
)
*164 (CptPort
uid 1282,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1283,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,33625,15000,34375"
)
tg (CPTG
uid 1284,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1285,0
va (VaSet
)
xt "16000,33500,20600,34500"
st "D0_SROUT"
blo "16000,34300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1286,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6000,61500,6800"
st "D0_SROUT   : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "D0_SROUT"
t "std_logic"
o 6
suid 28,0
)
)
)
*165 (CptPort
uid 1287,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1288,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,35625,15000,36375"
)
tg (CPTG
uid 1289,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1290,0
va (VaSet
)
xt "16000,35500,20600,36500"
st "D1_SROUT"
blo "16000,36300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1291,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6800,61500,7600"
st "D1_SROUT   : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "D1_SROUT"
t "std_logic"
o 7
suid 29,0
)
)
)
*166 (CptPort
uid 1292,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1293,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,37625,15000,38375"
)
tg (CPTG
uid 1294,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1295,0
va (VaSet
)
xt "16000,37500,20600,38500"
st "D2_SROUT"
blo "16000,38300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1296,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,7600,61500,8400"
st "D2_SROUT   : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "D2_SROUT"
t "std_logic"
o 8
suid 30,0
)
)
)
*167 (CptPort
uid 1297,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1298,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,39625,15000,40375"
)
tg (CPTG
uid 1299,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1300,0
va (VaSet
)
xt "16000,39500,20600,40500"
st "D3_SROUT"
blo "16000,40300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1301,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,8400,61500,9200"
st "D3_SROUT   : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "D3_SROUT"
t "std_logic"
o 9
suid 31,0
)
)
)
*168 (CptPort
uid 1302,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1303,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,29625,33750,30375"
)
tg (CPTG
uid 1304,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1305,0
va (VaSet
)
xt "27500,29500,32000,30500"
st "D_A : (3:0)"
ju 2
blo "32000,30300"
tm "CptPortNameMgr"
)
t (Text
uid 1306,0
va (VaSet
)
xt "26300,30500,32000,31500"
st "(others => '0')"
ju 2
blo "32000,31300"
tm "InitValueDelayMgr"
)
)
dt (MLText
uid 1307,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,20400,82000,21200"
st "D_A        : OUT    std_logic_vector (3 DOWNTO 0)   := (others => '0') ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "D_A"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 24
suid 32,0
i "(others => '0')"
)
)
)
*169 (CptPort
uid 1308,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1309,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,31625,33750,32375"
)
tg (CPTG
uid 1310,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1311,0
va (VaSet
)
xt "28500,31500,32000,32500"
st "DWRITE"
ju 2
blo "32000,32300"
tm "CptPortNameMgr"
)
t (Text
uid 1312,0
va (VaSet
)
xt "30800,32500,32000,33500"
st "'0'"
ju 2
blo "32000,33300"
tm "InitValueDelayMgr"
)
)
dt (MLText
uid 1313,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,19600,76000,20400"
st "DWRITE     : OUT    std_logic                       := '0' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "DWRITE"
t "std_logic"
o 23
suid 33,0
i "'0'"
)
)
)
*170 (CptPort
uid 1363,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1364,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,33625,33750,34375"
)
tg (CPTG
uid 1365,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1366,0
va (VaSet
)
xt "28400,33500,32000,34500"
st "DAC_CS"
ju 2
blo "32000,34300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1367,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,18000,61500,18800"
st "DAC_CS     : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "DAC_CS"
t "std_logic"
o 21
suid 34,0
)
)
)
*171 (CptPort
uid 1368,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1369,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,35625,33750,36375"
)
tg (CPTG
uid 1370,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1371,0
va (VaSet
)
xt "29200,35500,32000,36500"
st "T0_CS"
ju 2
blo "32000,36300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1372,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,31600,61500,32400"
st "T0_CS      : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "T0_CS"
t "std_logic"
o 38
suid 35,0
)
)
)
*172 (CptPort
uid 1373,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1374,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,37625,33750,38375"
)
tg (CPTG
uid 1375,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1376,0
va (VaSet
)
xt "29200,37500,32000,38500"
st "T1_CS"
ju 2
blo "32000,38300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1377,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,32400,61500,33200"
st "T1_CS      : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "T1_CS"
t "std_logic"
o 39
suid 36,0
)
)
)
*173 (CptPort
uid 1378,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1379,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,39625,33750,40375"
)
tg (CPTG
uid 1380,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1381,0
va (VaSet
)
xt "29200,39500,32000,40500"
st "T2_CS"
ju 2
blo "32000,40300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1382,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,33200,61500,34000"
st "T2_CS      : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "T2_CS"
t "std_logic"
o 40
suid 37,0
)
)
)
*174 (CptPort
uid 1383,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1384,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,41625,33750,42375"
)
tg (CPTG
uid 1385,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1386,0
va (VaSet
)
xt "29200,41500,32000,42500"
st "T3_CS"
ju 2
blo "32000,42300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1387,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,34000,61500,34800"
st "T3_CS      : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "T3_CS"
t "std_logic"
o 41
suid 38,0
)
)
)
*175 (CptPort
uid 1388,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1389,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,43625,33750,44375"
)
tg (CPTG
uid 1390,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1391,0
va (VaSet
)
xt "29200,43500,32000,44500"
st "S_CLK"
ju 2
blo "32000,44300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1392,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,30800,61500,31600"
st "S_CLK      : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "S_CLK"
t "std_logic"
o 37
suid 39,0
)
)
)
*176 (CptPort
uid 1393,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1394,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,45625,33750,46375"
)
tg (CPTG
uid 1395,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1396,0
va (VaSet
)
xt "27400,45500,32000,46500"
st "W_A : (9:0)"
ju 2
blo "32000,46300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1397,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,35600,71500,36400"
st "W_A        : OUT    std_logic_vector (9 DOWNTO 0) ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "W_A"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 43
suid 40,0
)
)
)
*177 (CptPort
uid 1398,0
ps "OnEdgeStrategy"
shape (Diamond
uid 1399,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,47625,33750,48375"
)
tg (CPTG
uid 1400,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1401,0
va (VaSet
)
xt "26900,47500,32000,48500"
st "W_D : (15:0)"
ju 2
blo "32000,48300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1402,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,40400,71000,41200"
st "W_D        : INOUT  std_logic_vector (15 DOWNTO 0)"
)
thePort (LogicalPort
m 2
decl (Decl
n "W_D"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 49
suid 41,0
)
)
)
*178 (CptPort
uid 1403,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1404,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,49625,33750,50375"
)
tg (CPTG
uid 1405,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1406,0
va (VaSet
)
xt "28900,49500,32000,50500"
st "W_RES"
ju 2
blo "32000,50300"
tm "CptPortNameMgr"
)
t (Text
uid 1407,0
va (VaSet
)
xt "30800,50500,32000,51500"
st "'1'"
ju 2
blo "32000,51300"
tm "InitValueDelayMgr"
)
)
dt (MLText
uid 1408,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,38000,76000,38800"
st "W_RES      : OUT    std_logic                       := '1' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "W_RES"
t "std_logic"
o 46
suid 42,0
i "'1'"
)
)
)
*179 (CptPort
uid 1409,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1410,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,51625,33750,52375"
)
tg (CPTG
uid 1411,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1412,0
va (VaSet
)
xt "29300,51500,32000,52500"
st "W_RD"
ju 2
blo "32000,52300"
tm "CptPortNameMgr"
)
t (Text
uid 1413,0
va (VaSet
)
xt "30800,52500,32000,53500"
st "'1'"
ju 2
blo "32000,53300"
tm "InitValueDelayMgr"
)
)
dt (MLText
uid 1414,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,37200,76000,38000"
st "W_RD       : OUT    std_logic                       := '1' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "W_RD"
t "std_logic"
o 45
suid 43,0
i "'1'"
)
)
)
*180 (CptPort
uid 1415,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1416,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,53625,33750,54375"
)
tg (CPTG
uid 1417,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1418,0
va (VaSet
)
xt "29200,53500,32000,54500"
st "W_WR"
ju 2
blo "32000,54300"
tm "CptPortNameMgr"
)
t (Text
uid 1419,0
va (VaSet
)
xt "30800,54500,32000,55500"
st "'1'"
ju 2
blo "32000,55300"
tm "InitValueDelayMgr"
)
)
dt (MLText
uid 1420,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,38800,76000,39600"
st "W_WR       : OUT    std_logic                       := '1' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "W_WR"
t "std_logic"
o 47
suid 44,0
i "'1'"
)
)
)
*181 (CptPort
uid 1421,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1422,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,41625,15000,42375"
)
tg (CPTG
uid 1423,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1424,0
va (VaSet
)
xt "16000,41500,18800,42500"
st "W_INT"
blo "16000,42300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1425,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10800,61500,11600"
st "W_INT      : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "W_INT"
t "std_logic"
o 12
suid 45,0
)
)
)
*182 (CptPort
uid 1426,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1427,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,55625,33750,56375"
)
tg (CPTG
uid 1428,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1429,0
va (VaSet
)
xt "29400,55500,32000,56500"
st "W_CS"
ju 2
blo "32000,56300"
tm "CptPortNameMgr"
)
t (Text
uid 1430,0
va (VaSet
)
xt "30800,56500,32000,57500"
st "'1'"
ju 2
blo "32000,57300"
tm "InitValueDelayMgr"
)
)
dt (MLText
uid 1431,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,36400,76000,37200"
st "W_CS       : OUT    std_logic                       := '1' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "W_CS"
t "std_logic"
o 44
suid 46,0
i "'1'"
)
)
)
*183 (CptPort
uid 1620,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1621,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,57625,33750,58375"
)
tg (CPTG
uid 1622,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1623,0
va (VaSet
)
xt "29600,57500,32000,58500"
st "MOSI"
ju 2
blo "32000,58300"
tm "CptPortNameMgr"
)
t (Text
uid 1624,0
va (VaSet
)
xt "30800,58500,32000,59500"
st "'0'"
ju 2
blo "32000,59300"
tm "InitValueDelayMgr"
)
)
dt (MLText
uid 1625,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,24400,76000,25200"
st "MOSI       : OUT    std_logic                       := '0' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "MOSI"
t "std_logic"
o 29
suid 47,0
i "'0'"
)
)
)
*184 (CptPort
uid 1626,0
ps "OnEdgeStrategy"
shape (Diamond
uid 1627,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,59625,33750,60375"
)
tg (CPTG
uid 1628,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1629,0
va (VaSet
)
xt "29600,59500,32000,60500"
st "MISO"
ju 2
blo "32000,60300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1630,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,39600,61500,40400"
st "MISO       : INOUT  std_logic  ;"
)
thePort (LogicalPort
m 2
decl (Decl
n "MISO"
t "std_logic"
preAdd 0
posAdd 0
o 48
suid 48,0
)
)
)
*185 (CptPort
uid 1676,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1677,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,61625,33750,62375"
)
tg (CPTG
uid 1678,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1679,0
va (VaSet
)
xt "29000,61500,32000,62500"
st "TRG_V"
ju 2
blo "32000,62300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1680,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,34800,61500,35600"
st "TRG_V      : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "TRG_V"
t "std_logic"
o 42
suid 49,0
)
)
)
*186 (CptPort
uid 1681,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1682,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,63625,33750,64375"
)
tg (CPTG
uid 1683,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1684,0
va (VaSet
)
xt "26400,63500,32000,64500"
st "RS485_C_RE"
ju 2
blo "32000,64300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1685,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,26800,61500,27600"
st "RS485_C_RE : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "RS485_C_RE"
t "std_logic"
o 32
suid 50,0
)
)
)
*187 (CptPort
uid 1686,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1687,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,65625,33750,66375"
)
tg (CPTG
uid 1688,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1689,0
va (VaSet
)
xt "26400,65500,32000,66500"
st "RS485_C_DE"
ju 2
blo "32000,66300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1690,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,26000,61500,26800"
st "RS485_C_DE : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "RS485_C_DE"
t "std_logic"
o 31
suid 51,0
)
)
)
*188 (CptPort
uid 1691,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1692,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,67625,33750,68375"
)
tg (CPTG
uid 1693,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1694,0
va (VaSet
)
xt "26500,67500,32000,68500"
st "RS485_E_RE"
ju 2
blo "32000,68300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1695,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,28400,61500,29200"
st "RS485_E_RE : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "RS485_E_RE"
t "std_logic"
o 34
suid 52,0
)
)
)
*189 (CptPort
uid 1696,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1697,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,69625,33750,70375"
)
tg (CPTG
uid 1698,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1699,0
va (VaSet
)
xt "26500,69500,32000,70500"
st "RS485_E_DE"
ju 2
blo "32000,70300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1700,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,27600,61500,28400"
st "RS485_E_DE : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "RS485_E_DE"
t "std_logic"
o 33
suid 53,0
)
)
)
*190 (CptPort
uid 1701,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1702,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,71625,33750,72375"
)
tg (CPTG
uid 1703,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1704,0
va (VaSet
)
xt "28000,71500,32000,72500"
st "DENABLE"
ju 2
blo "32000,72300"
tm "CptPortNameMgr"
)
t (Text
uid 1919,0
va (VaSet
)
xt "30800,72500,32000,73500"
st "'0'"
ju 2
blo "32000,73300"
tm "InitValueDelayMgr"
)
)
dt (MLText
uid 1705,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,18800,76000,19600"
st "DENABLE    : OUT    std_logic                       := '0' ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "DENABLE"
t "std_logic"
o 22
suid 54,0
i "'0'"
)
)
)
*191 (CptPort
uid 1706,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1707,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,73625,33750,74375"
)
tg (CPTG
uid 1708,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1709,0
va (VaSet
)
xt "29700,73500,32000,74500"
st "SRIN"
ju 2
blo "32000,74300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1710,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,30000,61500,30800"
st "SRIN       : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "SRIN"
t "std_logic"
o 36
suid 55,0
)
)
)
*192 (CptPort
uid 1711,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1712,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,75625,33750,76375"
)
tg (CPTG
uid 1713,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1714,0
va (VaSet
)
xt "29100,75500,32000,76500"
st "EE_CS"
ju 2
blo "32000,76300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1715,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,22800,61500,23600"
st "EE_CS      : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "EE_CS"
t "std_logic"
o 27
suid 56,0
)
)
)
*193 (CptPort
uid 2068,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2069,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,91625,33750,92375"
)
tg (CPTG
uid 2070,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2071,0
va (VaSet
)
xt "27500,91500,32000,92500"
st "D_T : (7:0)"
ju 2
blo "32000,92300"
tm "CptPortNameMgr"
)
t (Text
uid 2072,0
va (VaSet
)
xt "25100,92500,32000,93500"
st "(OTHERS => '0')"
ju 2
blo "32000,93300"
tm "InitValueDelayMgr"
)
)
dt (MLText
uid 2073,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,21200,82000,22000"
st "D_T        : OUT    std_logic_vector (7 DOWNTO 0)   := (OTHERS => '0') ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "D_T"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 25
suid 61,0
i "(OTHERS => '0')"
)
)
)
*194 (CptPort
uid 2375,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2376,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,93625,33750,94375"
)
tg (CPTG
uid 2377,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2378,0
va (VaSet
)
xt "27500,93500,32000,94500"
st "LED : (2:0)"
ju 2
blo "32000,94300"
tm "CptPortNameMgr"
)
t (Text
uid 2379,0
va (VaSet
)
xt "26300,94500,32000,95500"
st "(others => '1')"
ju 2
blo "32000,95300"
tm "InitValueDelayMgr"
)
)
dt (MLText
uid 2380,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,23600,82000,24400"
st "LED        : OUT    std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "LED"
t "std_logic_vector"
b "( 2 DOWNTO 0 )"
o 28
suid 62,0
i "(others => '1')"
)
)
)
*195 (CptPort
uid 2919,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2920,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,45625,15000,46375"
)
tg (CPTG
uid 2921,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2922,0
va (VaSet
)
xt "16000,45500,22800,46500"
st "D_PLLLCK : (3:0)"
blo "16000,46300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2923,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,9200,71500,10000"
st "D_PLLLCK   : IN     std_logic_vector (3 DOWNTO 0) ;"
)
thePort (LogicalPort
decl (Decl
n "D_PLLLCK"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 10
suid 64,0
)
)
)
*196 (CptPort
uid 2949,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2950,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,95625,33750,96375"
)
tg (CPTG
uid 2951,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2952,0
va (VaSet
)
xt "27100,95500,32000,96500"
st "D_T2 : (3:0)"
ju 2
blo "32000,96300"
tm "CptPortNameMgr"
)
t (Text
uid 2953,0
va (VaSet
)
xt "26300,96500,32000,97500"
st "(others => '0')"
ju 2
blo "32000,97300"
tm "InitValueDelayMgr"
)
)
dt (MLText
uid 2954,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,22000,82000,22800"
st "D_T2       : OUT    std_logic_vector (3 DOWNTO 0)   := (others => '0') ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "D_T2"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 26
suid 65,0
i "(others => '0')"
)
)
)
*197 (CptPort
uid 3026,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3027,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,97625,33750,98375"
)
tg (CPTG
uid 3028,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3029,0
va (VaSet
)
xt "27200,97500,32000,98500"
st "A1_T : (7:0)"
ju 2
blo "32000,98300"
tm "CptPortNameMgr"
)
t (Text
uid 3123,0
va (VaSet
)
xt "25100,98500,32000,99500"
st "(OTHERS => '0')"
ju 2
blo "32000,99300"
tm "InitValueDelayMgr"
)
)
dt (MLText
uid 3030,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,13200,82000,14000"
st "A1_T       : OUT    std_logic_vector (7 DOWNTO 0)   := (OTHERS => '0') ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "A1_T"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 15
suid 66,0
i "(OTHERS => '0')"
)
)
)
*198 (CptPort
uid 3456,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3457,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,99625,33750,100375"
)
tg (CPTG
uid 3458,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3459,0
va (VaSet
)
xt "27200,99500,32000,100500"
st "A0_T : (7:0)"
ju 2
blo "32000,100300"
tm "CptPortNameMgr"
)
t (Text
uid 3460,0
va (VaSet
)
xt "26300,100500,32000,101500"
st "(others => '0')"
ju 2
blo "32000,101300"
tm "InitValueDelayMgr"
)
)
dt (MLText
uid 3461,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,12400,82000,13200"
st "A0_T       : OUT    std_logic_vector (7 DOWNTO 0)   := (others => '0') ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "A0_T"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 14
suid 68,0
i "(others => '0')"
)
)
)
]
shape (Rectangle
uid 9,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,6000,33000,101000"
)
oxt "15000,6000,33000,26000"
biTextGroup (BiTextGroup
uid 10,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
uid 11,0
va (VaSet
font "Arial,8,1"
)
xt "22200,15000,28400,16000"
st "FACT_FAD_lib"
blo "22200,15800"
)
second (Text
uid 12,0
va (VaSet
font "Arial,8,1"
)
xt "22200,16000,26900,17000"
st "FAD_Board"
blo "22200,16800"
)
)
gi *199 (GenericInterface
uid 13,0
ps "CenterOffsetStrategy"
matrix (Matrix
uid 14,0
text (MLText
uid 15,0
va (VaSet
font "Courier New,8,0"
)
xt "0,12000,11500,12800"
st "Generic Declarations"
)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
elements [
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
sIVOD 1
)
portVis (PortSigDisplay
sIVOD 1
)
)
*200 (Grouping
uid 16,0
optionalChildren [
*201 (CommentText
uid 18,0
shape (Rectangle
uid 19,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,48000,53000,49000"
)
oxt "18000,70000,35000,71000"
text (MLText
uid 20,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,48000,45900,49000"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*202 (CommentText
uid 21,0
shape (Rectangle
uid 22,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,44000,57000,45000"
)
oxt "35000,66000,39000,67000"
text (MLText
uid 23,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,44000,56200,45000"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*203 (CommentText
uid 24,0
shape (Rectangle
uid 25,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,46000,53000,47000"
)
oxt "18000,68000,35000,69000"
text (MLText
uid 26,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,46000,46200,47000"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*204 (CommentText
uid 27,0
shape (Rectangle
uid 28,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,46000,36000,47000"
)
oxt "14000,68000,18000,69000"
text (MLText
uid 29,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,46000,34300,47000"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*205 (CommentText
uid 30,0
shape (Rectangle
uid 31,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,45000,73000,49000"
)
oxt "35000,67000,55000,71000"
text (MLText
uid 32,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,45200,62400,46200"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
titleBlock 1
)
*206 (CommentText
uid 33,0
shape (Rectangle
uid 34,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "57000,44000,73000,45000"
)
oxt "39000,66000,55000,67000"
text (MLText
uid 35,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "57200,44000,61700,45000"
st "
%project_name
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
titleBlock 1
)
*207 (CommentText
uid 36,0
shape (Rectangle
uid 37,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,44000,53000,46000"
)
oxt "14000,66000,35000,68000"
text (MLText
uid 38,0
va (VaSet
fg "32768,0,0"
)
xt "39700,44000,45300,46000"
st "
TU Dortmund 
Physik / EE
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
titleBlock 1
)
*208 (CommentText
uid 39,0
shape (Rectangle
uid 40,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,47000,36000,48000"
)
oxt "14000,69000,18000,70000"
text (MLText
uid 41,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,47000,34300,48000"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*209 (CommentText
uid 42,0
shape (Rectangle
uid 43,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,48000,36000,49000"
)
oxt "14000,70000,18000,71000"
text (MLText
uid 44,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,48000,34900,49000"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*210 (CommentText
uid 45,0
shape (Rectangle
uid 46,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,47000,53000,48000"
)
oxt "18000,69000,35000,70000"
text (MLText
uid 47,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,47000,49400,48000"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
]
shape (GroupingShape
uid 17,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "32000,44000,73000,49000"
)
oxt "14000,66000,55000,71000"
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *211 (PackageList
uid 48,0
stg "VerticalLayoutStrategy"
textVec [
*212 (Text
uid 49,0
va (VaSet
font "Arial,8,1"
)
xt "0,0,5400,1000"
st "Package List"
blo "0,800"
)
*213 (MLText
uid 50,0
va (VaSet
)
xt "0,1000,10900,4000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;"
tm "PackageList"
)
]
)
windowSize "0,0,1015,690"
viewArea "0,0,0,0"
cachedDiagramExtent "0,0,0,0"
pageBreakOrigin "0,0"
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,2000,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Arial,8,1"
)
xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
parentGraphicsRef (HdmGraphicsRef
libraryName ""
entityName ""
viewName ""
)
defaultSymbolBody (SymbolBody
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,6000,33000,26000"
)
biTextGroup (BiTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
font "Arial,8,1"
)
xt "22200,15000,25800,16000"
st "<library>"
blo "22200,15800"
)
second (Text
va (VaSet
font "Arial,8,1"
)
xt "22200,16000,24800,17000"
st "<cell>"
blo "22200,16800"
)
)
gi *214 (GenericInterface
ps "CenterOffsetStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "0,12000,11500,12800"
st "Generic Declarations"
)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
elements [
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
sIVOD 1
)
portVis (PortSigDisplay
sIVOD 1
)
)
defaultCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "In0"
blo "0,1550"
tm "CptPortNameMgr"
)
)
dt (MLText
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "In0"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
defaultCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
bg "0,0,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,2800,1750"
st "Buffer0"
blo "0,1550"
tm "CptPortNameMgr"
)
)
dt (MLText
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Buffer0"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
DeclarativeBlock *215 (SymDeclBlock
uid 1,0
stg "SymDeclLayoutStrategy"
declLabel (Text
uid 2,0
va (VaSet
font "Arial,8,1"
)
xt "42000,0,47400,1000"
st "Declarations"
blo "42000,800"
)
portLabel (Text
uid 3,0
va (VaSet
font "Arial,8,1"
)
xt "42000,1000,44700,2000"
st "Ports:"
blo "42000,1800"
)
externalLabel (Text
uid 4,0
va (VaSet
font "Arial,8,1"
)
xt "42000,41200,44400,42200"
st "User:"
blo "42000,42000"
)
internalLabel (Text
uid 6,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "42000,0,47800,1000"
st "Internal User:"
blo "42000,800"
)
externalText (MLText
uid 5,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,42200,44000,42200"
tm "SyDeclarativeTextMgr"
)
internalText (MLText
uid 7,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "42000,0,42000,0"
tm "SyDeclarativeTextMgr"
)
)
lastUid 3530,0
activeModelName "Symbol:CDM"
)
