DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_ARITH"
)
(DmPackageRef
library "ieee"
unitName "STD_LOGIC_UNSIGNED"
)
(DmPackageRef
library "FACT_FAD_lib"
unitName "fad_definitions"
)
]
libraryRefs [
"ieee"
"FACT_FAD_lib"
]
)
version "24.1"
appVersion "2009.2 (Build 10)"
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i "'0'"
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uid 324,0
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)
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n "roi_max"
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*56 (MRCItem
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*57 (MRCItem
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*58 (MRCItem
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*59 (MRCItem
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pos 4
dimension 100
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*60 (MRCItem
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*61 (MRCItem
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pos 6
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*62 (MRCItem
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fixedCol 4
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ldm (LogicalDM
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tm "GenericValueColHdrMgr"
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tm "GenericEolColHdrMgr"
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value "12"
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uid 922,0
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value "14"
)
uid 924,0
)
]
)
pdm (PhysicalDM
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uid 101,0
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fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
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uid 103,0
optionalChildren [
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litem &64
pos 0
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)
*80 (MRCItem
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*81 (MRCItem
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pos 2
hidden 1
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*82 (MRCItem
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pos 0
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*83 (MRCItem
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pos 1
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uid 925,0
)
]
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sheetCol (SheetCol
propVa (MVa
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font "Tahoma,10,0"
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uid 107,0
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litem &67
pos 0
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uid 108,0
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*86 (MRCItem
litem &70
pos 2
dimension 100
uid 110,0
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*87 (MRCItem
litem &71
pos 3
dimension 100
uid 111,0
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*88 (MRCItem
litem &72
pos 4
dimension 50
uid 112,0
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*89 (MRCItem
litem &73
pos 5
dimension 50
uid 113,0
)
*90 (MRCItem
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pos 6
dimension 80
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)
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)
fixedCol 3
fixedRow 2
name "Ports"
uid 102,0
vaOverrides [
]
)
]
)
uid 88,0
type 1
)
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager\\symbol.sb.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager\\symbol.sb.user"
)
(vvPair
variable "SourceDir"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "symbol"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager"
)
(vvPair
variable "d_logical"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager"
)
(vvPair
variable "date"
value "02.07.2010"
)
(vvPair
variable "day"
value "Fr"
)
(vvPair
variable "day_long"
value "Freitag"
)
(vvPair
variable "dd"
value "02"
)
(vvPair
variable "entity_name"
value "memory_manager"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "symbol.sb"
)
(vvPair
variable "f_logical"
value "symbol.sb"
)
(vvPair
variable "f_noext"
value "symbol"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "TU-CC4900F8C7D2"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_lib"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/work"
)
(vvPair
variable "library_downstream_PrecisionSynthesisDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "mm"
value "07"
)
(vvPair
variable "module_name"
value "memory_manager"
)
(vvPair
variable "month"
value "Jul"
)
(vvPair
variable "month_long"
value "Juli"
)
(vvPair
variable "p"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager\\symbol.sb"
)
(vvPair
variable "p_logical"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager\\symbol.sb"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "<TBD>"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "sb"
)
(vvPair
variable "this_file"
value "symbol"
)
(vvPair
variable "this_file_logical"
value "symbol"
)
(vvPair
variable "time"
value "10:38:11"
)
(vvPair
variable "unit"
value "memory_manager"
)
(vvPair
variable "user"
value "dneise"
)
(vvPair
variable "version"
value "2009.2 (Build 10)"
)
(vvPair
variable "view"
value "symbol"
)
(vvPair
variable "year"
value "2010"
)
(vvPair
variable "yy"
value "10"
)
]
)
LanguageMgr "VhdlLangMgr"
uid 58,0
optionalChildren [
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uid 8,0
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uid 51,0
ps "OnEdgeStrategy"
shape (Triangle
uid 52,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,7625,15000,8375"
)
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
font "arial,8,0"
)
xt "16000,7500,21900,8500"
st "ram_start_addr"
blo "16000,8300"
tm "CptPortNameMgr"
)
)
dt (MLText
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va (VaSet
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)
xt "44000,15600,95500,16400"
st "ram_start_addr         : OUT    std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0')
"
)
thePort (LogicalPort
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m 1
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
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preAdd 0
posAdd 0
o 18
suid 1,0
i "(others => '0')"
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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xt "14250,8625,15000,9375"
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tg (CPTG
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xt "16000,8500,17300,9500"
st "clk"
blo "16000,9300"
tm "CptPortNameMgr"
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)
dt (MLText
uid 142,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2000,68000,2800"
st "clk                    : IN     std_logic  ;
"
)
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lang 2
decl (Decl
n "clk"
t "std_logic"
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ps "EdgeToEdgeStrategy"
shape (Rectangle
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layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "42000,5600,57000,10600"
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oxt "0,0,15000,5000"
text (MLText
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va (VaSet
fg "0,0,32768"
font "arial,8,0"
)
xt "42200,5800,54900,9800"
st "
-- library UNISIM;
-- use UNISIM.VComponents.all;
-- USE IEEE.NUMERIC_STD.all;

-- RAM_ADDR_WIDTH_64B is used for
-- output ram_start_addr

-- RAM_ADDR_WIDTH_16B is used for
-- output wiz_ram_start_addr
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
included 1
excludeCommentLeader 1
)
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uid 194,0
ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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fg "0,65535,0"
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xt "14250,9625,15000,10375"
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tg (CPTG
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va (VaSet
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xt "16000,9500,20800,10500"
st "config_start"
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tm "CptPortNameMgr"
)
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xt "44000,2800,68000,3600"
st "config_start           : IN     std_logic  ;
"
)
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lang 2
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n "config_start"
t "std_logic"
o 2
suid 3,0
)
)
)
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
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fg "0,65535,0"
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xt "43000,6625,43750,7375"
)
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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)
xt "36700,6500,42000,7500"
st "ram_write_ea"
ju 2
blo "42000,7300"
tm "CptPortNameMgr"
)
)
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va (VaSet
font "Courier New,8,0"
)
xt "44000,5200,90500,6000"
st "ram_write_ea           : OUT    std_logic                                        := '0' ;
"
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "ram_write_ea"
t "std_logic"
o 5
suid 4,0
i "'0'"
)
)
)
*97 (CptPort
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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fg "0,65535,0"
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xt "43000,7625,43750,8375"
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stg "RightVerticalLayoutStrategy"
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va (VaSet
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xt "36900,7500,42000,8500"
st "config_ready"
ju 2
blo "42000,8300"
tm "CptPortNameMgr"
)
)
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va (VaSet
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)
xt "44000,6000,90500,6800"
st "config_ready           : OUT    std_logic                                        := '0' ;
"
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "config_ready"
t "std_logic"
o 6
suid 5,0
i "'0'"
)
)
)
*98 (CptPort
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ps "OnEdgeStrategy"
shape (Triangle
uid 409,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,10625,15000,11375"
)
tg (CPTG
uid 286,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 287,0
va (VaSet
font "arial,8,0"
)
xt "16000,10500,25600,11500"
st "wiz_number_of_channels"
blo "16000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 288,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10800,96500,11600"
st "wiz_number_of_channels : OUT    std_logic_vector (3 downto 0)                    := (others => '0') ;
"
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_number_of_channels"
t "std_logic_vector"
b "(3 downto 0)"
o 12
suid 6,0
i "(others => '0')"
)
)
)
*99 (CptPort
uid 289,0
ps "OnEdgeStrategy"
shape (Triangle
uid 290,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,8625,43750,9375"
)
tg (CPTG
uid 291,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 292,0
va (VaSet
font "arial,8,0"
)
xt "34600,8500,42000,9500"
st "wiz_ram_start_addr"
ju 2
blo "42000,9300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 293,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,9200,96500,10000"
st "wiz_ram_start_addr     : OUT    std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0') ;
"
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH_16B-1 downto 0)"
preAdd 0
o 10
suid 7,0
i "(others => '0')"
)
)
)
*100 (CptPort
uid 294,0
ps "OnEdgeStrategy"
shape (Triangle
uid 295,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,9625,43750,10375"
)
tg (CPTG
uid 296,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 297,0
va (VaSet
font "arial,8,0"
)
xt "36900,9500,42000,10500"
st "wiz_write_ea"
ju 2
blo "42000,10300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 298,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,11600,90500,12400"
st "wiz_write_ea           : OUT    std_logic                                        := '0' ;
"
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_write_ea"
t "std_logic"
o 13
suid 8,0
i "'0'"
)
)
)
*101 (CptPort
uid 299,0
ps "OnEdgeStrategy"
shape (Triangle
uid 300,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,10625,43750,11375"
)
tg (CPTG
uid 301,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 302,0
va (VaSet
font "arial,8,0"
)
xt "36500,10500,42000,11500"
st "wiz_write_end"
ju 2
blo "42000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 303,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,13200,90500,14000"
st "wiz_write_end          : OUT    std_logic                                        := '0' ;
"
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_write_end"
t "std_logic"
o 15
suid 9,0
i "'0'"
)
)
)
*102 (CptPort
uid 304,0
ps "OnEdgeStrategy"
shape (Triangle
uid 305,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,11625,43750,12375"
)
tg (CPTG
uid 306,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 307,0
va (VaSet
font "arial,8,0"
)
xt "35400,11500,42000,12500"
st "wiz_write_header"
ju 2
blo "42000,12300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 308,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,12400,90500,13200"
st "wiz_write_header       : OUT    std_logic                                        := '0' ;
"
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_write_header"
t "std_logic"
o 14
suid 10,0
i "'0'"
)
)
)
*103 (CptPort
uid 309,0
ps "OnEdgeStrategy"
shape (Triangle
uid 310,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,12625,43750,13375"
)
tg (CPTG
uid 311,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 312,0
va (VaSet
font "arial,8,0"
)
xt "35600,12500,42000,13500"
st "wiz_write_length"
ju 2
blo "42000,13300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 313,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10000,96500,10800"
st "wiz_write_length       : OUT    std_logic_vector (16 downto 0)                   := (others => '0') ;
"
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_write_length"
t "std_logic_vector"
b "(16 downto 0)"
o 11
suid 11,0
i "(others => '0')"
)
)
)
*104 (CptPort
uid 349,0
ps "OnEdgeStrategy"
shape (Triangle
uid 350,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,11625,15000,12375"
)
tg (CPTG
uid 351,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 352,0
va (VaSet
font "arial,8,0"
)
xt "16000,11500,22300,12500"
st "ram_write_ready"
blo "16000,12300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 353,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,3600,68000,4400"
st "ram_write_ready        : IN     std_logic  ;
"
)
thePort (LogicalPort
lang 2
decl (Decl
n "ram_write_ready"
t "std_logic"
o 3
suid 12,0
)
)
)
*105 (CptPort
uid 379,0
ps "OnEdgeStrategy"
shape (Triangle
uid 380,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,12625,15000,13375"
)
tg (CPTG
uid 381,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 382,0
va (VaSet
font "arial,8,0"
)
xt "16000,12500,19400,13500"
st "wiz_busy"
blo "16000,13300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 383,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,14000,68000,14800"
st "wiz_busy               : IN     std_logic  ;
"
)
thePort (LogicalPort
lang 2
decl (Decl
n "wiz_busy"
t "std_logic"
o 16
suid 13,0
)
)
)
*106 (CptPort
uid 433,0
ps "OnEdgeStrategy"
shape (Triangle
uid 434,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,13625,43750,14375"
)
tg (CPTG
uid 435,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 436,0
va (VaSet
font "arial,8,0"
)
xt "39000,13500,42000,14500"
st "roi_max"
ju 2
blo "42000,14300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 437,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,7600,109500,8400"
st "roi_max                : OUT    roi_max_type                                     := (others => conv_std_logic_vector (0, 11)) ;
"
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "roi_max"
t "roi_max_type"
posAdd 0
o 8
suid 14,0
i "(others => conv_std_logic_vector (0, 11))"
)
)
)
*107 (CptPort
uid 569,0
ps "OnEdgeStrategy"
shape (Triangle
uid 570,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,13625,15000,14375"
)
tg (CPTG
uid 571,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 572,0
va (VaSet
font "arial,8,0"
)
xt "16000,13500,19400,14500"
st "roi_array"
blo "16000,14300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 573,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4400,70500,5200"
st "roi_array              : IN     roi_array_type  ;
"
)
thePort (LogicalPort
lang 2
decl (Decl
n "roi_array"
t "roi_array_type"
o 4
suid 17,0
)
)
)
*108 (CptPort
uid 622,0
ps "OnEdgeStrategy"
shape (Triangle
uid 623,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,14625,43750,15375"
)
tg (CPTG
uid 624,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 625,0
va (VaSet
font "arial,8,0"
)
xt "35900,14500,42000,15500"
st "package_length"
ju 2
blo "42000,15300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 626,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,8400,96500,9200"
st "package_length         : OUT    std_logic_vector (15 downto 0)                   := (others => '0') ;
"
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "package_length"
t "std_logic_vector"
b "(15 downto 0)"
o 9
suid 18,0
i "(others => '0')"
)
)
)
*109 (CptPort
uid 804,0
ps "OnEdgeStrategy"
shape (Triangle
uid 805,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,15625,43750,16375"
)
tg (CPTG
uid 806,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 807,0
va (VaSet
font "arial,8,0"
)
xt "36400,15500,42000,16500"
st "config_started"
ju 2
blo "42000,16300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 808,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6800,90500,7600"
st "config_started         : OUT    std_logic                                        := '0' ;
"
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "config_started"
t "std_logic"
o 7
suid 21,0
i "'0'"
)
)
)
*110 (CptPort
uid 915,0
ps "OnEdgeStrategy"
shape (Triangle
uid 916,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,14625,15000,15375"
)
tg (CPTG
uid 917,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 918,0
va (VaSet
font "arial,8,0"
)
xt "16000,14500,19000,15500"
st "wiz_ack"
blo "16000,15300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 919,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,14800,68000,15600"
st "wiz_ack                : IN     std_logic  ;
"
)
thePort (LogicalPort
lang 2
decl (Decl
n "wiz_ack"
t "std_logic"
o 17
suid 22,0
)
)
)
]
shape (Rectangle
uid 9,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,6000,43000,17000"
)
oxt "15000,6000,23000,16000"
biTextGroup (BiTextGroup
uid 10,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
uid 11,0
va (VaSet
font "arial,8,1"
)
xt "15350,10000,21550,11000"
st "FACT_FAD_lib"
blo "15350,10800"
)
second (Text
uid 12,0
va (VaSet
font "arial,8,1"
)
xt "15350,11000,22650,12000"
st "memory_manager"
blo "15350,11800"
)
)
gi *111 (GenericInterface
uid 13,0
ps "CenterOffsetStrategy"
matrix (Matrix
uid 14,0
text (MLText
uid 15,0
va (VaSet
font "Courier New,8,0"
)
xt "-5000,7000,12000,10200"
st "Generic Declarations

RAM_ADDR_WIDTH_64B integer 12  
RAM_ADDR_WIDTH_16B integer 14  
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)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
elements [
(GiElement
name "RAM_ADDR_WIDTH_64B"
type "integer"
value "12"
)
(GiElement
name "RAM_ADDR_WIDTH_16B"
type "integer"
value "14"
)
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
sTC 0
sF 0
)
portVis (PortSigDisplay
sTC 0
sF 0
)
)
*112 (Grouping
uid 16,0
optionalChildren [
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uid 18,0
shape (Rectangle
uid 19,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,48000,53000,49000"
)
oxt "18000,70000,35000,71000"
text (MLText
uid 20,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,48000,45700,49000"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*114 (CommentText
uid 21,0
shape (Rectangle
uid 22,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,44000,57000,45000"
)
oxt "35000,66000,39000,67000"
text (MLText
uid 23,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,44000,56200,45000"
st "
Project:
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*115 (CommentText
uid 24,0
shape (Rectangle
uid 25,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,46000,53000,47000"
)
oxt "18000,68000,35000,69000"
text (MLText
uid 26,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,46000,46200,47000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
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uid 27,0
shape (Rectangle
uid 28,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,46000,36000,47000"
)
oxt "14000,68000,18000,69000"
text (MLText
uid 29,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,46000,34300,47000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*117 (CommentText
uid 30,0
shape (Rectangle
uid 31,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,45000,73000,49000"
)
oxt "35000,67000,55000,71000"
text (MLText
uid 32,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,45200,62400,46200"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
titleBlock 1
)
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uid 33,0
shape (Rectangle
uid 34,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "57000,44000,73000,45000"
)
oxt "39000,66000,55000,67000"
text (MLText
uid 35,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "57200,44000,61700,45000"
st "
%project_name
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
titleBlock 1
)
*119 (CommentText
uid 36,0
shape (Rectangle
uid 37,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,44000,53000,46000"
)
oxt "14000,66000,35000,68000"
text (MLText
uid 38,0
va (VaSet
fg "32768,0,0"
)
xt "39150,44500,45850,45500"
st "
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ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
titleBlock 1
)
*120 (CommentText
uid 39,0
shape (Rectangle
uid 40,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,47000,36000,48000"
)
oxt "14000,69000,18000,70000"
text (MLText
uid 41,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,47000,34300,48000"
st "
Path:
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*121 (CommentText
uid 42,0
shape (Rectangle
uid 43,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,48000,36000,49000"
)
oxt "14000,70000,18000,71000"
text (MLText
uid 44,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,48000,34900,49000"
st "
Edited:
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
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uid 45,0
shape (Rectangle
uid 46,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,47000,53000,48000"
)
oxt "18000,69000,35000,70000"
text (MLText
uid 47,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,47000,51400,48000"
st "
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"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
]
shape (GroupingShape
uid 17,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "32000,44000,73000,49000"
)
oxt "14000,66000,55000,71000"
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *123 (PackageList
uid 48,0
stg "VerticalLayoutStrategy"
textVec [
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uid 49,0
va (VaSet
font "arial,8,1"
)
xt "0,0,5400,1000"
st "Package List"
blo "0,800"
)
*125 (MLText
uid 50,0
va (VaSet
font "arial,8,0"
)
xt "0,1000,14400,8000"
st "library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_UNSIGNED.all;

library FACT_FAD_lib;
use FACT_FAD_lib.fad_definitions.all;"
tm "PackageList"
)
]
)
windowSize "0,0,1015,690"
viewArea "0,0,0,0"
cachedDiagramExtent "0,0,0,0"
pageBreakOrigin "0,0"
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
font "arial,8,0"
)
xt "200,200,2000,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "arial,8,1"
)
xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
parentGraphicsRef (HdmGraphicsRef
libraryName "FACT_FAD_lib"
entityName "FAD_main"
viewName "struct.bd"
)
defaultSymbolBody (SymbolBody
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,6000,33000,26000"
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biTextGroup (BiTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
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