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library "ieee"
unitName "std_logic_1164"
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library "ieee"
unitName "std_logic_arith"
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library "ieee"
unitName "std_logic_unsigned"
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(DmPackageRef
library "FACT_FAD_lib"
unitName "fad_definitions"
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(DmPackageRef
library "ieee"
unitName "std_logic_textio"
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library "std"
unitName "textio"
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duName "w5300_emulator"
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(Instance
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duName "max6662_emulator"
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duName "trigger_generator"
elements [
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(Instance
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duLibraryName "FACT_FAD_TB_lib"
duName "adc_emulator"
elements [
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embeddedInstances [
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number "1"
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libraryRefs [
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version "29.1"
appVersion "2009.2 (Build 10)"
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(vvPair
variable "HDSDir"
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(vvPair
variable "appl"
value "HDL Designer"
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(vvPair
variable "arch_name"
value "struct"
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(vvPair
variable "config"
value "%(unit)_config"
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value "25"
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variable "module_name"
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value "Juni"
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variable "package_name"
value "<Undefined Variable>"
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variable "project_name"
value "FACT_FAD"
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variable "series"
value "HDL Designer Series"
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(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
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value "$HDS_HOME/../Modeltech/win32"
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value "$HDS_HOME/../Precision/Mgc_home/bin"
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(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
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variable "this_file"
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variable "this_file_logical"
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(vvPair
variable "time"
value "08:17:47"
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(vvPair
variable "unit"
value "fad_main_tb"
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(vvPair
variable "user"
value "Benjamin Krumm"
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value "2009.2 (Build 10)"
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(vvPair
variable "view"
value "struct"
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value "2010"
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value "10"
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st "CLK_50"
blo "82000,22300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_50"
t "std_logic"
o 13
suid 37,0
)
)
)
*27 (CptPort
uid 165,0
ps "OnEdgeStrategy"
shape (Triangle
uid 166,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,20625,81000,21375"
)
tg (CPTG
uid 167,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 168,0
va (VaSet
)
xt "82000,20500,83900,21500"
st "CLK"
blo "82000,21300"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 38,0
)
)
)
*28 (CptPort
uid 169,0
ps "OnEdgeStrategy"
shape (Triangle
uid 170,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,41625,81000,42375"
)
tg (CPTG
uid 171,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 172,0
va (VaSet
)
xt "82000,41500,90000,42500"
st "adc_otr_array : (3:0)"
blo "82000,42300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 7
suid 40,0
)
)
)
*29 (CptPort
uid 173,0
ps "OnEdgeStrategy"
shape (Triangle
uid 174,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,47625,81000,48375"
)
tg (CPTG
uid 175,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 176,0
va (VaSet
)
xt "82000,47500,87900,48500"
st "adc_data_array"
blo "82000,48300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 6
suid 41,0
)
)
)
*30 (CptPort
uid 177,0
ps "OnEdgeStrategy"
shape (Triangle
uid 178,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,61625,81000,62375"
)
tg (CPTG
uid 179,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 180,0
va (VaSet
)
xt "82000,61500,90500,62500"
st "drs_channel_id : (3:0)"
blo "82000,62300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 19
suid 48,0
i "(others => '0')"
)
)
)
*31 (CptPort
uid 181,0
ps "OnEdgeStrategy"
shape (Triangle
uid 182,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,62625,81000,63375"
)
tg (CPTG
uid 183,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 184,0
va (VaSet
)
xt "82000,62500,86300,63500"
st "drs_dwrite"
blo "82000,63300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_dwrite"
t "std_logic"
o 20
suid 49,0
i "'1'"
)
)
)
*32 (CptPort
uid 185,0
ps "OnEdgeStrategy"
shape (Triangle
uid 186,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,57625,81000,58375"
)
tg (CPTG
uid 187,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 188,0
va (VaSet
)
xt "82000,57500,87400,58500"
st "SROUT_in_0"
blo "82000,58300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 2
suid 52,0
)
)
)
*33 (CptPort
uid 189,0
ps "OnEdgeStrategy"
shape (Triangle
uid 190,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,58625,81000,59375"
)
tg (CPTG
uid 191,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 192,0
va (VaSet
)
xt "82000,58500,87400,59500"
st "SROUT_in_1"
blo "82000,59300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 3
suid 53,0
)
)
)
*34 (CptPort
uid 193,0
ps "OnEdgeStrategy"
shape (Triangle
uid 194,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,59625,81000,60375"
)
tg (CPTG
uid 195,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 196,0
va (VaSet
)
xt "82000,59500,87400,60500"
st "SROUT_in_2"
blo "82000,60300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 4
suid 54,0
)
)
)
*35 (CptPort
uid 197,0
ps "OnEdgeStrategy"
shape (Triangle
uid 198,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,60625,81000,61375"
)
tg (CPTG
uid 199,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 200,0
va (VaSet
)
xt "82000,60500,87400,61500"
st "SROUT_in_3"
blo "82000,61300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 5
suid 55,0
)
)
)
*36 (CptPort
uid 201,0
ps "OnEdgeStrategy"
shape (Triangle
uid 202,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,63625,81000,64375"
)
tg (CPTG
uid 203,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 204,0
va (VaSet
)
xt "82000,63500,86200,64500"
st "RSRLOAD"
blo "82000,64300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "RSRLOAD"
t "std_logic"
o 14
suid 56,0
i "'0'"
)
)
)
*37 (CptPort
uid 205,0
ps "OnEdgeStrategy"
shape (Triangle
uid 206,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,65625,81000,66375"
)
tg (CPTG
uid 207,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 208,0
va (VaSet
)
xt "82000,65500,85000,66500"
st "SRCLK"
blo "82000,66300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SRCLK"
t "std_logic"
o 15
suid 57,0
i "'0'"
)
)
)
*38 (CptPort
uid 209,0
ps "OnEdgeStrategy"
shape (Triangle
uid 210,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,50625,109750,51375"
)
tg (CPTG
uid 211,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 212,0
va (VaSet
)
xt "106300,50500,108000,51500"
st "sclk"
ju 2
blo "108000,51300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sclk"
t "std_logic"
o 23
suid 62,0
)
)
)
*39 (CptPort
uid 213,0
ps "OnEdgeStrategy"
shape (Diamond
uid 214,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,51625,109750,52375"
)
tg (CPTG
uid 215,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 216,0
va (VaSet
)
xt "106600,51500,108000,52500"
st "sio"
ju 2
blo "108000,52300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 30
suid 63,0
)
)
)
*40 (CptPort
uid 217,0
ps "OnEdgeStrategy"
shape (Triangle
uid 218,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,39625,109750,40375"
)
tg (CPTG
uid 219,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 220,0
va (VaSet
)
xt "105200,39500,108000,40500"
st "dac_cs"
ju 2
blo "108000,40300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dac_cs"
t "std_logic"
o 17
suid 64,0
)
)
)
*41 (CptPort
uid 221,0
ps "OnEdgeStrategy"
shape (Triangle
uid 222,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,41625,109750,42375"
)
tg (CPTG
uid 223,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 224,0
va (VaSet
)
xt "101500,41500,108000,42500"
st "sensor_cs : (3:0)"
ju 2
blo "108000,42300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 24
suid 65,0
)
)
)
*42 (CptPort
uid 225,0
ps "OnEdgeStrategy"
shape (Triangle
uid 226,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,52625,109750,53375"
)
tg (CPTG
uid 227,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 228,0
va (VaSet
)
xt "106000,52500,108000,53500"
st "mosi"
ju 2
blo "108000,53300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "mosi"
t "std_logic"
o 22
suid 66,0
i "'0'"
)
)
)
*43 (CptPort
uid 229,0
ps "OnEdgeStrategy"
shape (Triangle
uid 230,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,70625,109750,71375"
)
tg (CPTG
uid 231,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 232,0
va (VaSet
)
xt "105000,70500,108000,71500"
st "denable"
ju 2
blo "108000,71300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 18
suid 67,0
i "'0'"
)
)
)
]
shape (Rectangle
uid 234,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "81000,19000,109000,73000"
)
oxt "15000,-8000,43000,46000"
ttg (MlTextGroup
uid 235,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*44 (Text
uid 236,0
va (VaSet
font "Arial,8,1"
)
xt "81200,73000,87400,74000"
st "FACT_FAD_lib"
blo "81200,73800"
tm "BdLibraryNameMgr"
)
*45 (Text
uid 237,0
va (VaSet
font "Arial,8,1"
)
xt "81200,74000,85400,75000"
st "FAD_main"
blo "81200,74800"
tm "CptNameMgr"
)
*46 (Text
uid 238,0
va (VaSet
font "Arial,8,1"
)
xt "81200,75000,88000,76000"
st "I_mainTB_FPGA"
blo "81200,75800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 239,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 240,0
text (MLText
uid 241,0
va (VaSet
font "Courier New,8,0"
)
xt "81000,18200,101000,19000"
st "RAMADDRWIDTH64b = 15    ( integer )  "
)
header ""
)
elements [
(GiElement
name "RAMADDRWIDTH64b"
type "integer"
value "15"
)
]
)
viewicon (ZoomableIcon
uid 242,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "81250,71250,82750,72750"
iconName "BlockDiagram.png"
iconMaskName "BlockDiagram.msk"
ftype 1
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*47 (SaComponent
uid 274,0
optionalChildren [
*48 (CptPort
uid 266,0
ps "OnEdgeStrategy"
shape (Triangle
uid 267,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,20625,58750,21375"
)
tg (CPTG
uid 268,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 269,0
va (VaSet
)
xt "55700,20500,57000,21500"
st "clk"
ju 2
blo "57000,21300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "clk"
t "STD_LOGIC"
o 1
i "'0'"
)
)
)
*49 (CptPort
uid 270,0
ps "OnEdgeStrategy"
shape (Triangle
uid 271,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,21625,58750,22375"
)
tg (CPTG
uid 272,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 273,0
va (VaSet
)
xt "55700,21500,57000,22500"
st "rst"
ju 2
blo "57000,22300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rst"
t "STD_LOGIC"
o 2
i "'0'"
)
)
)
]
shape (Rectangle
uid 275,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "50000,19000,58000,24000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 276,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*50 (Text
uid 277,0
va (VaSet
font "Arial,8,1"
)
xt "50150,24000,57850,25000"
st "FACT_FAD_TB_lib"
blo "50150,24800"
tm "BdLibraryNameMgr"
)
*51 (Text
uid 278,0
va (VaSet
font "Arial,8,1"
)
xt "50150,25000,56850,26000"
st "clock_generator"
blo "50150,25800"
tm "CptNameMgr"
)
*52 (Text
uid 279,0
va (VaSet
font "Arial,8,1"
)
xt "50150,26000,56750,27000"
st "I_mainTB_clock"
blo "50150,26800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 280,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 281,0
text (MLText
uid 282,0
va (VaSet
font "Courier New,8,0"
)
xt "50000,17400,68500,19000"
st "clock_period = 20 ns    ( time )  
reset_time   = 50 ns    ( time )  "
)
header ""
)
elements [
(GiElement
name "clock_period"
type "time"
value "20 ns"
)
(GiElement
name "reset_time"
type "time"
value "50 ns"
)
]
)
viewicon (ZoomableIcon
uid 283,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "50250,22250,51750,23750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*53 (Net
uid 284,0
decl (Decl
n "clk"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 1
suid 1,0
)
declText (MLText
uid 285,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,26800,20000,27600"
st "SIGNAL clk            : STD_LOGIC"
)
)
*54 (SaComponent
uid 306,0
optionalChildren [
*55 (CptPort
uid 290,0
ps "OnEdgeStrategy"
shape (Triangle
uid 291,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,20625,123000,21375"
)
tg (CPTG
uid 292,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 293,0
va (VaSet
)
xt "124000,20500,128500,21500"
st "addr : (9:0)"
blo "124000,21300"
)
)
thePort (LogicalPort
decl (Decl
n "addr"
t "std_logic_vector"
b "(9 downto 0)"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*56 (CptPort
uid 294,0
ps "OnEdgeStrategy"
shape (Diamond
uid 295,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,21625,123000,22375"
)
tg (CPTG
uid 296,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 297,0
va (VaSet
)
xt "124000,21500,128800,22500"
st "data : (15:0)"
blo "124000,22300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "data"
t "std_logic_vector"
b "(15 downto 0)"
preAdd 0
posAdd 0
o 2
suid 2,0
)
)
)
*57 (CptPort
uid 298,0
ps "OnEdgeStrategy"
shape (Triangle
uid 299,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,24625,123000,25375"
)
tg (CPTG
uid 300,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 301,0
va (VaSet
)
xt "124000,24500,125100,25500"
st "rd"
blo "124000,25300"
)
)
thePort (LogicalPort
decl (Decl
n "rd"
t "std_logic"
preAdd 0
posAdd 0
o 3
suid 3,0
)
)
)
*58 (CptPort
uid 302,0
ps "OnEdgeStrategy"
shape (Triangle
uid 303,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,25625,123000,26375"
)
tg (CPTG
uid 304,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 305,0
va (VaSet
)
xt "124000,25500,125200,26500"
st "wr"
blo "124000,26300"
)
)
thePort (LogicalPort
decl (Decl
n "wr"
t "std_logic"
preAdd 0
posAdd 0
o 4
suid 4,0
)
)
)
]
shape (Rectangle
uid 307,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "123000,19000,133000,31000"
)
oxt "29000,2000,39000,12000"
ttg (MlTextGroup
uid 308,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*59 (Text
uid 309,0
va (VaSet
font "Arial,8,1"
)
xt "123200,31000,130900,32000"
st "FACT_FAD_TB_lib"
blo "123200,31800"
tm "BdLibraryNameMgr"
)
*60 (Text
uid 310,0
va (VaSet
font "Arial,8,1"
)
xt "123200,32000,129800,33000"
st "w5300_emulator"
blo "123200,32800"
tm "CptNameMgr"
)
*61 (Text
uid 311,0
va (VaSet
font "Arial,8,1"
)
xt "123200,33000,130000,34000"
st "I_mainTB_w5300"
blo "123200,33800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 312,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 313,0
text (MLText
uid 314,0
va (VaSet
font "Courier New,8,0"
)
xt "123000,18000,123000,18000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 315,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "123250,29250,124750,30750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*62 (Net
uid 316,0
decl (Decl
n "wiz_addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 2
suid 2,0
)
declText (MLText
uid 317,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,36400,30000,37200"
st "SIGNAL wiz_addr       : std_logic_vector(9 DOWNTO 0)"
)
)
*63 (Net
uid 322,0
decl (Decl
n "wiz_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 3
suid 3,0
)
declText (MLText
uid 323,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,38000,30500,38800"
st "SIGNAL wiz_data       : std_logic_vector(15 DOWNTO 0)"
)
)
*64 (Net
uid 328,0
decl (Decl
n "wiz_rd"
t "std_logic"
o 4
suid 4,0
i "'1'"
)
declText (MLText
uid 329,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,39600,33500,40400"
st "SIGNAL wiz_rd         : std_logic                    := '1'"
)
)
*65 (Net
uid 334,0
decl (Decl
n "wiz_wr"
t "std_logic"
o 5
suid 5,0
i "'1'"
)
declText (MLText
uid 335,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,41200,33500,42000"
st "SIGNAL wiz_wr         : std_logic                    := '1'"
)
)
*66 (SaComponent
uid 362,0
optionalChildren [
*67 (CptPort
uid 350,0
ps "OnEdgeStrategy"
shape (Triangle
uid 351,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,50625,123000,51375"
)
tg (CPTG
uid 352,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 353,0
va (VaSet
)
xt "124000,50500,125700,51500"
st "sclk"
blo "124000,51300"
)
)
thePort (LogicalPort
decl (Decl
n "sclk"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*68 (CptPort
uid 354,0
ps "OnEdgeStrategy"
shape (Diamond
uid 355,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,51625,123000,52375"
)
tg (CPTG
uid 356,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 357,0
va (VaSet
)
xt "124000,51500,125400,52500"
st "sio"
blo "124000,52300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 2
suid 2,0
)
)
)
*69 (CptPort
uid 358,0
ps "OnEdgeStrategy"
shape (Triangle
uid 359,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "122250,47625,123000,48375"
)
tg (CPTG
uid 360,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 361,0
va (VaSet
)
xt "124000,47500,130500,48500"
st "sensor_cs : (3:0)"
blo "124000,48300"
)
)
thePort (LogicalPort
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 3
suid 3,0
)
)
)
]
shape (Rectangle
uid 363,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "123000,46000,133000,56000"
)
oxt "30000,3000,40000,13000"
ttg (MlTextGroup
uid 364,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*70 (Text
uid 365,0
va (VaSet
font "Arial,8,1"
)
xt "123200,56000,130900,57000"
st "FACT_FAD_TB_lib"
blo "123200,56800"
tm "BdLibraryNameMgr"
)
*71 (Text
uid 366,0
va (VaSet
font "Arial,8,1"
)
xt "123200,57000,130800,58000"
st "max6662_emulator"
blo "123200,57800"
tm "CptNameMgr"
)
*72 (Text
uid 367,0
va (VaSet
font "Arial,8,1"
)
xt "123200,58000,131000,59000"
st "I_mainTB_max6662"
blo "123200,58800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 368,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 369,0
text (MLText
uid 370,0
va (VaSet
font "Courier New,8,0"
)
xt "123000,45200,143000,46000"
st "DRS_TEMPERATURE = 51    ( integer )  "
)
header ""
)
elements [
(GiElement
name "DRS_TEMPERATURE"
type "integer"
value "51"
)
]
)
viewicon (ZoomableIcon
uid 371,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "123250,54250,124750,55750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*73 (Net
uid 372,0
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 6
suid 6,0
)
declText (MLText
uid 373,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,34000,30000,34800"
st "SIGNAL sensor_cs      : std_logic_vector(3 DOWNTO 0)"
)
)
*74 (Net
uid 378,0
decl (Decl
n "sclk"
t "std_logic"
o 7
suid 7,0
)
declText (MLText
uid 379,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,33200,20000,34000"
st "SIGNAL sclk           : std_logic"
)
)
*75 (Net
uid 384,0
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 8
suid 8,0
)
declText (MLText
uid 385,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,34800,20000,35600"
st "SIGNAL sio            : std_logic"
)
)
*76 (SaComponent
uid 414,0
optionalChildren [
*77 (CptPort
uid 410,0
ps "OnEdgeStrategy"
shape (Triangle
uid 411,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,31625,58750,32375"
)
tg (CPTG
uid 412,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 413,0
va (VaSet
)
xt "54200,31500,57000,32500"
st "trigger"
ju 2
blo "57000,32300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
]
shape (Rectangle
uid 415,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "50000,30000,58000,36000"
)
oxt "19000,4000,29000,14000"
ttg (MlTextGroup
uid 416,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*78 (Text
uid 417,0
va (VaSet
font "Arial,8,1"
)
xt "50200,36000,57900,37000"
st "FACT_FAD_TB_lib"
blo "50200,36800"
tm "BdLibraryNameMgr"
)
*79 (Text
uid 418,0
va (VaSet
font "Arial,8,1"
)
xt "50200,37000,57500,38000"
st "trigger_generator"
blo "50200,37800"
tm "CptNameMgr"
)
*80 (Text
uid 419,0
va (VaSet
font "Arial,8,1"
)
xt "50200,38000,57400,39000"
st "I_mainTB_trigger"
blo "50200,38800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 420,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 421,0
text (MLText
uid 422,0
va (VaSet
font "Courier New,8,0"
)
xt "50000,28400,68500,30000"
st "TRIGGER_RATE = 1 ms     ( time )  
PULSE_WIDTH  = 20 ns    ( time )  "
)
header ""
)
elements [
(GiElement
name "TRIGGER_RATE"
type "time"
value "1 ms"
)
(GiElement
name "PULSE_WIDTH"
type "time"
value "20 ns"
)
]
)
viewicon (ZoomableIcon
uid 423,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "50250,34250,51750,35750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*81 (Net
uid 424,0
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 9
suid 9,0
)
declText (MLText
uid 425,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,35600,20000,36400"
st "SIGNAL trigger        : std_logic"
)
)
*82 (HdlText
uid 430,0
optionalChildren [
*83 (EmbeddedText
uid 436,0
commentText (CommentText
uid 437,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 438,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "50000,45000,60000,49000"
)
oxt "0,0,18000,5000"
text (MLText
uid 439,0
va (VaSet
)
xt "50200,45200,60200,48200"
st "
-- eb_ID 1: hard-wired IDs
board_id <= \"0101\";
crate_id <= \"01\";

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4000
visibleWidth 10000
)
)
)
]
shape (Rectangle
uid 431,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "50000,40000,58000,45000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 432,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*84 (Text
uid 433,0
va (VaSet
font "Arial,8,1"
)
xt "51150,41000,57350,42000"
st "eb_mainTB_ID"
blo "51150,41800"
tm "HdlTextNameMgr"
)
*85 (Text
uid 434,0
va (VaSet
font "Arial,8,1"
)
xt "51150,42000,51950,43000"
st "1"
blo "51150,42800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
uid 435,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "50250,43250,51750,44750"
iconName "TextFile.png"
iconMaskName "TextFile.msk"
ftype 21
)
viewiconposition 0
)
*86 (Net
uid 440,0
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 10
suid 10,0
)
declText (MLText
uid 441,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,26000,30000,26800"
st "SIGNAL board_id       : std_logic_vector(3 downto 0)"
)
)
*87 (Net
uid 448,0
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
o 11
suid 11,0
)
declText (MLText
uid 449,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,27600,30000,28400"
st "SIGNAL crate_id       : std_logic_vector(1 downto 0)"
)
)
*88 (SaComponent
uid 508,0
optionalChildren [
*89 (CptPort
uid 489,0
ps "OnEdgeStrategy"
shape (Triangle
uid 490,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "29250,52625,30000,53375"
)
tg (CPTG
uid 491,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 492,0
va (VaSet
)
xt "31000,52500,32300,53500"
st "clk"
blo "31000,53300"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*90 (CptPort
uid 493,0
ps "OnEdgeStrategy"
shape (Triangle
uid 494,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,54625,40750,55375"
)
tg (CPTG
uid 495,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 496,0
va (VaSet
)
xt "34200,54500,39000,55500"
st "data : (11:0)"
ju 2
blo "39000,55300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data"
t "STD_LOGIC_VECTOR"
b "(11 DOWNTO 0)"
preAdd 0
posAdd 0
o 2
suid 2,0
)
)
)
*91 (CptPort
uid 497,0
ps "OnEdgeStrategy"
shape (Triangle
uid 498,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,52625,40750,53375"
)
tg (CPTG
uid 499,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 500,0
va (VaSet
)
xt "37700,52500,39000,53500"
st "otr"
ju 2
blo "39000,53300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "otr"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 3
suid 3,0
)
)
)
*92 (CptPort
uid 501,0
ps "OnEdgeStrategy"
shape (Triangle
uid 502,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,53625,40750,54375"
)
tg (CPTG
uid 503,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 504,0
va (VaSet
)
xt "37400,53500,39000,54500"
st "oeb"
ju 2
blo "39000,54300"
)
)
thePort (LogicalPort
decl (Decl
n "oeb"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 4
suid 4,0
)
)
)
]
shape (Rectangle
uid 509,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "30000,51000,40000,58000"
)
oxt "29000,7000,39000,17000"
ttg (MlTextGroup
uid 510,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*93 (Text
uid 511,0
va (VaSet
font "Arial,8,1"
)
xt "30200,58000,37900,59000"
st "FACT_FAD_TB_lib"
blo "30200,58800"
tm "BdLibraryNameMgr"
)
*94 (Text
uid 512,0
va (VaSet
font "Arial,8,1"
)
xt "30200,59000,36000,60000"
st "adc_emulator"
blo "30200,59800"
tm "CptNameMgr"
)
*95 (Text
uid 513,0
va (VaSet
font "Arial,8,1"
)
xt "30200,60000,36200,61000"
st "I_mainTB_adc"
blo "30200,60800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 514,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 515,0
text (MLText
uid 516,0
va (VaSet
font "Courier New,8,0"
)
xt "30000,50200,65500,51000"
st "INPUT_FILE = \"../memory_files/analog_input_ch0.txt\"    ( string )  "
)
header ""
)
elements [
(GiElement
name "INPUT_FILE"
type "string"
value "\"../memory_files/analog_input_ch0.txt\""
)
]
)
viewicon (ZoomableIcon
uid 517,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "30250,56250,31750,57750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*96 (HdlText
uid 518,0
optionalChildren [
*97 (EmbeddedText
uid 524,0
commentText (CommentText
uid 525,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 526,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "50000,57000,62000,67000"
)
oxt "0,0,18000,5000"
text (MLText
uid 527,0
va (VaSet
)
xt "50200,57200,62100,66200"
st "
-- eb_adc 2: ADC routing
adc_data_array(0) <= adc_data;
adc_data_array(1) <= adc_data;
adc_data_array(2) <= adc_data;
adc_data_array(3) <= adc_data;
adc_otr_array(0) <= adc_otr;
adc_otr_array(1) <= adc_otr;
adc_otr_array(2) <= adc_otr;
adc_otr_array(3) <= adc_otr;

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 10000
visibleWidth 12000
)
)
)
]
shape (Rectangle
uid 519,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "50000,51000,58000,57000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 520,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*98 (Text
uid 521,0
va (VaSet
font "Arial,8,1"
)
xt "51150,52000,57850,53000"
st "eb_mainTB_adc"
blo "51150,52800"
tm "HdlTextNameMgr"
)
*99 (Text
uid 522,0
va (VaSet
font "Arial,8,1"
)
xt "51150,53000,51950,54000"
st "2"
blo "51150,53800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
uid 523,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "50250,55250,51750,56750"
iconName "TextFile.png"
iconMaskName "TextFile.msk"
ftype 21
)
viewiconposition 0
)
*100 (Net
uid 528,0
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 12
suid 12,0
)
declText (MLText
uid 529,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,25200,30000,26000"
st "SIGNAL adc_otr_array  : std_logic_vector(3 DOWNTO 0)"
)
)
*101 (Net
uid 536,0
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 13
suid 13,0
)
declText (MLText
uid 537,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,22800,25500,23600"
st "SIGNAL adc_data_array : adc_data_array_type"
)
)
*102 (Net
uid 544,0
decl (Decl
n "adc_oeb"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 14,0
)
declText (MLText
uid 545,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,23600,20000,24400"
st "SIGNAL adc_oeb        : std_logic"
)
)
*103 (Net
uid 560,0
decl (Decl
n "adc_otr"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 16
suid 16,0
)
declText (MLText
uid 561,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,24400,20000,25200"
st "SIGNAL adc_otr        : STD_LOGIC"
)
)
*104 (Net
uid 568,0
decl (Decl
n "adc_data"
t "std_logic_vector"
b "(11 DOWNTO 0)"
preAdd 0
posAdd 0
o 17
suid 17,0
)
declText (MLText
uid 569,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,22000,30500,22800"
st "SIGNAL adc_data       : std_logic_vector(11 DOWNTO 0)"
)
)
*105 (Net
uid 767,0
decl (Decl
n "wiz_reset"
t "std_logic"
o 21
suid 23,0
i "'1'"
)
declText (MLText
uid 768,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,40400,33500,41200"
st "SIGNAL wiz_reset      : std_logic                    := '1'"
)
)
*106 (Net
uid 775,0
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 22
suid 24,0
i "(OTHERS => '0')"
)
declText (MLText
uid 776,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,31600,39500,32400"
st "SIGNAL led            : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"
)
)
*107 (Net
uid 783,0
decl (Decl
n "wiz_cs"
t "std_logic"
o 23
suid 25,0
i "'1'"
)
declText (MLText
uid 784,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,37200,33500,38000"
st "SIGNAL wiz_cs         : std_logic                    := '1'"
)
)
*108 (Net
uid 791,0
decl (Decl
n "wiz_int"
t "std_logic"
o 24
suid 26,0
)
declText (MLText
uid 792,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,38800,20000,39600"
st "SIGNAL wiz_int        : std_logic"
)
)
*109 (Net
uid 799,0
decl (Decl
n "dac_cs"
t "std_logic"
o 25
suid 27,0
)
declText (MLText
uid 800,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,28400,20000,29200"
st "SIGNAL dac_cs         : std_logic"
)
)
*110 (Net
uid 807,0
decl (Decl
n "mosi"
t "std_logic"
o 26
suid 28,0
i "'0'"
)
declText (MLText
uid 808,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,32400,33500,33200"
st "SIGNAL mosi           : std_logic                    := '0'"
)
)
*111 (Net
uid 815,0
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 27
suid 29,0
i "'0'"
)
declText (MLText
uid 816,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,29200,47000,30000"
st "SIGNAL denable        : std_logic                    := '0' -- default domino wave off"
)
)
*112 (Net
uid 823,0
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 28
suid 30,0
)
declText (MLText
uid 824,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,15600,20000,16400"
st "SIGNAL CLK_25_PS      : std_logic"
)
)
*113 (Net
uid 831,0
decl (Decl
n "CLK_50"
t "std_logic"
o 29
suid 31,0
)
declText (MLText
uid 832,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,16400,20000,17200"
st "SIGNAL CLK_50         : std_logic"
)
)
*114 (Net
uid 839,0
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 30
suid 32,0
i "(others => '0')"
)
declText (MLText
uid 840,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,30000,39500,30800"
st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')"
)
)
*115 (Net
uid 847,0
decl (Decl
n "drs_dwrite"
t "std_logic"
o 31
suid 33,0
i "'1'"
)
declText (MLText
uid 848,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,30800,33500,31600"
st "SIGNAL drs_dwrite     : std_logic                    := '1'"
)
)
*116 (Net
uid 855,0
decl (Decl
n "RSRLOAD"
t "std_logic"
o 32
suid 34,0
i "'0'"
)
declText (MLText
uid 856,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,17200,33500,18000"
st "SIGNAL RSRLOAD        : std_logic                    := '0'"
)
)
*117 (Net
uid 863,0
decl (Decl
n "SRCLK"
t "std_logic"
o 33
suid 35,0
i "'0'"
)
declText (MLText
uid 864,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,18000,33500,18800"
st "SIGNAL SRCLK          : std_logic                    := '0'"
)
)
*118 (Net
uid 871,0
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 30
suid 36,0
)
declText (MLText
uid 872,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,18800,20000,19600"
st "SIGNAL SROUT_in_0     : std_logic"
)
)
*119 (Net
uid 879,0
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 31
suid 37,0
)
declText (MLText
uid 880,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,19600,20000,20400"
st "SIGNAL SROUT_in_1     : std_logic"
)
)
*120 (Net
uid 887,0
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 32
suid 38,0
)
declText (MLText
uid 888,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,20400,20000,21200"
st "SIGNAL SROUT_in_2     : std_logic"
)
)
*121 (Net
uid 895,0
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 33
suid 39,0
)
declText (MLText
uid 896,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,21200,20000,22000"
st "SIGNAL SROUT_in_3     : std_logic"
)
)
*122 (Wire
uid 286,0
shape (OrthoPolyLine
uid 287,0
va (VaSet
vasetType 3
)
xt "58750,21000,80250,21000"
pts [
"58750,21000"
"80250,21000"
]
)
start &48
end &27
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 288,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 289,0
va (VaSet
)
xt "71000,20000,72300,21000"
st "clk"
blo "71000,20800"
tm "WireNameMgr"
)
)
on &53
)
*123 (Wire
uid 318,0
shape (OrthoPolyLine
uid 319,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,21000,122250,21000"
pts [
"109750,21000"
"122250,21000"
]
)
start &19
end &55
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 320,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 321,0
va (VaSet
)
xt "111000,20000,117000,21000"
st "wiz_addr : (9:0)"
blo "111000,20800"
tm "WireNameMgr"
)
)
on &62
)
*124 (Wire
uid 324,0
shape (OrthoPolyLine
uid 325,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,22000,122250,22000"
pts [
"109750,22000"
"122250,22000"
]
)
start &20
end &56
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 326,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 327,0
va (VaSet
)
xt "111000,21000,117300,22000"
st "wiz_data : (15:0)"
blo "111000,21800"
tm "WireNameMgr"
)
)
on &63
)
*125 (Wire
uid 330,0
shape (OrthoPolyLine
uid 331,0
va (VaSet
vasetType 3
)
xt "109750,25000,122250,25000"
pts [
"109750,25000"
"122250,25000"
]
)
start &23
end &57
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 332,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 333,0
va (VaSet
)
xt "111000,24000,113600,25000"
st "wiz_rd"
blo "111000,24800"
tm "WireNameMgr"
)
)
on &64
)
*126 (Wire
uid 336,0
shape (OrthoPolyLine
uid 337,0
va (VaSet
vasetType 3
)
xt "109750,26000,122250,26000"
pts [
"109750,26000"
"122250,26000"
]
)
start &22
end &58
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 338,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 339,0
va (VaSet
)
xt "111000,25000,113700,26000"
st "wiz_wr"
blo "111000,25800"
tm "WireNameMgr"
)
)
on &65
)
*127 (Wire
uid 374,0
shape (OrthoPolyLine
uid 375,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,42000,122250,48000"
pts [
"109750,42000"
"120000,42000"
"120000,48000"
"122250,48000"
]
)
start &41
end &69
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 376,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 377,0
va (VaSet
)
xt "111000,41000,117500,42000"
st "sensor_cs : (3:0)"
blo "111000,41800"
tm "WireNameMgr"
)
)
on &73
)
*128 (Wire
uid 380,0
shape (OrthoPolyLine
uid 381,0
va (VaSet
vasetType 3
)
xt "109750,51000,122250,51000"
pts [
"109750,51000"
"122250,51000"
]
)
start &38
end &67
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 382,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 383,0
va (VaSet
)
xt "111000,50000,112700,51000"
st "sclk"
blo "111000,50800"
tm "WireNameMgr"
)
)
on &74
)
*129 (Wire
uid 386,0
shape (OrthoPolyLine
uid 387,0
va (VaSet
vasetType 3
)
xt "109750,52000,122250,52000"
pts [
"109750,52000"
"122250,52000"
]
)
start &39
end &68
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 388,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 389,0
va (VaSet
)
xt "111000,51000,112400,52000"
st "sio"
blo "111000,51800"
tm "WireNameMgr"
)
)
on &75
)
*130 (Wire
uid 426,0
shape (OrthoPolyLine
uid 427,0
va (VaSet
vasetType 3
)
xt "58750,32000,80250,32000"
pts [
"58750,32000"
"80250,32000"
]
)
start &77
end &15
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 428,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 429,0
va (VaSet
)
xt "71000,31000,73800,32000"
st "trigger"
blo "71000,31800"
tm "WireNameMgr"
)
)
on &81
)
*131 (Wire
uid 442,0
shape (OrthoPolyLine
uid 443,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "58000,34000,80250,42000"
pts [
"80250,34000"
"64000,34000"
"64000,42000"
"58000,42000"
]
)
start &17
end &82
sat 32
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 446,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 447,0
va (VaSet
)
xt "71000,33000,76900,34000"
st "board_id : (3:0)"
blo "71000,33800"
tm "WireNameMgr"
)
)
on &86
)
*132 (Wire
uid 450,0
shape (OrthoPolyLine
uid 451,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "58000,35000,80250,43000"
pts [
"80250,35000"
"65000,35000"
"65000,43000"
"58000,43000"
]
)
start &18
end &82
sat 32
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 454,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 455,0
va (VaSet
)
xt "71000,34000,76700,35000"
st "crate_id : (1:0)"
blo "71000,34800"
tm "WireNameMgr"
)
)
on &87
)
*133 (Wire
uid 530,0
shape (OrthoPolyLine
uid 531,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "58000,42000,80250,53000"
pts [
"80250,42000"
"68000,42000"
"68000,53000"
"58000,53000"
]
)
start &28
end &96
sat 32
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 534,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 535,0
va (VaSet
)
xt "71000,41000,79000,42000"
st "adc_otr_array : (3:0)"
blo "71000,41800"
tm "WireNameMgr"
)
)
on &100
)
*134 (Wire
uid 538,0
shape (OrthoPolyLine
uid 539,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "58000,48000,80250,55000"
pts [
"80250,48000"
"70000,48000"
"70000,55000"
"58000,55000"
]
)
start &29
end &96
sat 32
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 542,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 543,0
va (VaSet
)
xt "71000,47000,76900,48000"
st "adc_data_array"
blo "71000,47800"
tm "WireNameMgr"
)
)
on &101
)
*135 (Wire
uid 546,0
shape (OrthoPolyLine
uid 547,0
va (VaSet
vasetType 3
)
xt "58000,43000,80250,54000"
pts [
"80250,43000"
"69000,43000"
"69000,54000"
"58000,54000"
]
)
start &16
end &96
sat 32
eat 1
st 0
sf 1
si 0
tg (WTG
uid 550,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 551,0
va (VaSet
)
xt "71000,42000,74200,43000"
st "adc_oeb"
blo "71000,42800"
tm "WireNameMgr"
)
)
on &102
)
*136 (Wire
uid 554,0
shape (OrthoPolyLine
uid 555,0
va (VaSet
vasetType 3
)
xt "40750,54000,50000,54000"
pts [
"50000,54000"
"40750,54000"
]
)
start &96
end &92
sat 2
eat 32
st 0
sf 1
tg (WTG
uid 558,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 559,0
va (VaSet
)
xt "42000,53000,45200,54000"
st "adc_oeb"
blo "42000,53800"
tm "WireNameMgr"
)
)
on &102
)
*137 (Wire
uid 562,0
shape (OrthoPolyLine
uid 563,0
va (VaSet
vasetType 3
)
xt "40750,53000,50000,53000"
pts [
"40750,53000"
"50000,53000"
]
)
start &91
end &96
sat 32
eat 1
st 0
sf 1
tg (WTG
uid 566,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 567,0
va (VaSet
)
xt "42000,52000,44900,53000"
st "adc_otr"
blo "42000,52800"
tm "WireNameMgr"
)
)
on &103
)
*138 (Wire
uid 570,0
shape (OrthoPolyLine
uid 571,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "40750,55000,50000,55000"
pts [
"40750,55000"
"50000,55000"
]
)
start &90
end &96
sat 32
eat 1
sty 1
st 0
sf 1
tg (WTG
uid 574,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 575,0
va (VaSet
)
xt "42000,54000,48400,55000"
st "adc_data : (11:0)"
blo "42000,54800"
tm "WireNameMgr"
)
)
on &104
)
*139 (Wire
uid 578,0
shape (OrthoPolyLine
uid 579,0
va (VaSet
vasetType 3
)
xt "25000,53000,29250,53000"
pts [
"29250,53000"
"25000,53000"
]
)
start &89
sat 32
eat 16
st 0
sf 1
tg (WTG
uid 582,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 583,0
va (VaSet
)
xt "26250,52000,27550,53000"
st "clk"
blo "26250,52800"
tm "WireNameMgr"
)
)
on &53
)
*140 (Wire
uid 769,0
shape (OrthoPolyLine
uid 770,0
va (VaSet
vasetType 3
)
xt "109750,24000,116000,24000"
pts [
"109750,24000"
"116000,24000"
]
)
start &13
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 773,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 774,0
va (VaSet
)
xt "111000,23000,114600,24000"
st "wiz_reset"
blo "111000,23800"
tm "WireNameMgr"
)
)
on &105
)
*141 (Wire
uid 777,0
shape (OrthoPolyLine
uid 778,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109750,70000,116000,70000"
pts [
"109750,70000"
"116000,70000"
]
)
start &14
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 781,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 782,0
va (VaSet
)
xt "111000,69000,115000,70000"
st "led : (7:0)"
blo "111000,69800"
tm "WireNameMgr"
)
)
on &106
)
*142 (Wire
uid 785,0
shape (OrthoPolyLine
uid 786,0
va (VaSet
vasetType 3
)
xt "109750,28000,116000,28000"
pts [
"109750,28000"
"116000,28000"
]
)
start &21
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 789,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 790,0
va (VaSet
)
xt "111000,27000,113700,28000"
st "wiz_cs"
blo "111000,27800"
tm "WireNameMgr"
)
)
on &107
)
*143 (Wire
uid 793,0
shape (OrthoPolyLine
uid 794,0
va (VaSet
vasetType 3
)
xt "109750,27000,116000,27000"
pts [
"116000,27000"
"109750,27000"
]
)
end &24
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 797,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 798,0
va (VaSet
)
xt "111000,26000,113700,27000"
st "wiz_int"
blo "111000,26800"
tm "WireNameMgr"
)
)
on &108
)
*144 (Wire
uid 801,0
shape (OrthoPolyLine
uid 802,0
va (VaSet
vasetType 3
)
xt "109750,40000,116000,40000"
pts [
"109750,40000"
"116000,40000"
]
)
start &40
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 805,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 806,0
va (VaSet
)
xt "111000,39000,113800,40000"
st "dac_cs"
blo "111000,39800"
tm "WireNameMgr"
)
)
on &109
)
*145 (Wire
uid 809,0
shape (OrthoPolyLine
uid 810,0
va (VaSet
vasetType 3
)
xt "109750,53000,116000,53000"
pts [
"109750,53000"
"116000,53000"
]
)
start &42
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 813,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 814,0
va (VaSet
)
xt "111000,52000,113000,53000"
st "mosi"
blo "111000,52800"
tm "WireNameMgr"
)
)
on &110
)
*146 (Wire
uid 817,0
shape (OrthoPolyLine
uid 818,0
va (VaSet
vasetType 3
)
xt "109750,71000,116000,71000"
pts [
"109750,71000"
"116000,71000"
]
)
start &43
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 821,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 822,0
va (VaSet
)
xt "111000,70000,114000,71000"
st "denable"
blo "111000,70800"
tm "WireNameMgr"
)
)
on &111
)
*147 (Wire
uid 825,0
shape (OrthoPolyLine
uid 826,0
va (VaSet
vasetType 3
)
xt "70000,23000,80250,23000"
pts [
"80250,23000"
"70000,23000"
]
)
start &25
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 829,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 830,0
va (VaSet
)
xt "71000,22000,75500,23000"
st "CLK_25_PS"
blo "71000,22800"
tm "WireNameMgr"
)
)
on &112
)
*148 (Wire
uid 833,0
shape (OrthoPolyLine
uid 834,0
va (VaSet
vasetType 3
)
xt "70000,22000,80250,22000"
pts [
"80250,22000"
"70000,22000"
]
)
start &26
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 837,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 838,0
va (VaSet
)
xt "71000,21000,74100,22000"
st "CLK_50"
blo "71000,21800"
tm "WireNameMgr"
)
)
on &113
)
*149 (Wire
uid 841,0
shape (OrthoPolyLine
uid 842,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "70000,62000,80250,62000"
pts [
"80250,62000"
"70000,62000"
]
)
start &30
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 845,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 846,0
va (VaSet
)
xt "71000,61000,79500,62000"
st "drs_channel_id : (3:0)"
blo "71000,61800"
tm "WireNameMgr"
)
)
on &114
)
*150 (Wire
uid 849,0
shape (OrthoPolyLine
uid 850,0
va (VaSet
vasetType 3
)
xt "70000,63000,80250,63000"
pts [
"80250,63000"
"70000,63000"
]
)
start &31
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 853,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 854,0
va (VaSet
)
xt "71000,62000,75300,63000"
st "drs_dwrite"
blo "71000,62800"
tm "WireNameMgr"
)
)
on &115
)
*151 (Wire
uid 857,0
shape (OrthoPolyLine
uid 858,0
va (VaSet
vasetType 3
)
xt "70000,64000,80250,64000"
pts [
"80250,64000"
"70000,64000"
]
)
start &36
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 861,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 862,0
va (VaSet
)
xt "71000,63000,75200,64000"
st "RSRLOAD"
blo "71000,63800"
tm "WireNameMgr"
)
)
on &116
)
*152 (Wire
uid 865,0
shape (OrthoPolyLine
uid 866,0
va (VaSet
vasetType 3
)
xt "70000,66000,80250,66000"
pts [
"80250,66000"
"70000,66000"
]
)
start &37
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 869,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 870,0
va (VaSet
)
xt "71000,65000,74000,66000"
st "SRCLK"
blo "71000,65800"
tm "WireNameMgr"
)
)
on &117
)
*153 (Wire
uid 873,0
shape (OrthoPolyLine
uid 874,0
va (VaSet
vasetType 3
)
xt "70000,58000,80250,58000"
pts [
"70000,58000"
"80250,58000"
]
)
end &32
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 877,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 878,0
va (VaSet
)
xt "71000,57000,76400,58000"
st "SROUT_in_0"
blo "71000,57800"
tm "WireNameMgr"
)
)
on &118
)
*154 (Wire
uid 881,0
shape (OrthoPolyLine
uid 882,0
va (VaSet
vasetType 3
)
xt "70000,59000,80250,59000"
pts [
"70000,59000"
"80250,59000"
]
)
end &33
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 885,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 886,0
va (VaSet
)
xt "71000,58000,76400,59000"
st "SROUT_in_1"
blo "71000,58800"
tm "WireNameMgr"
)
)
on &119
)
*155 (Wire
uid 889,0
shape (OrthoPolyLine
uid 890,0
va (VaSet
vasetType 3
)
xt "70000,60000,80250,60000"
pts [
"70000,60000"
"80250,60000"
]
)
end &34
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 893,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 894,0
va (VaSet
)
xt "71000,59000,76400,60000"
st "SROUT_in_2"
blo "71000,59800"
tm "WireNameMgr"
)
)
on &120
)
*156 (Wire
uid 897,0
shape (OrthoPolyLine
uid 898,0
va (VaSet
vasetType 3
)
xt "70000,61000,80250,61000"
pts [
"70000,61000"
"80250,61000"
]
)
end &35
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 901,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 902,0
va (VaSet
)
xt "71000,60000,76400,61000"
st "SROUT_in_3"
blo "71000,60800"
tm "WireNameMgr"
)
)
on &121
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *157 (PackageList
uid 41,0
stg "VerticalLayoutStrategy"
textVec [
*158 (Text
uid 42,0
va (VaSet
font "arial,8,1"
)
xt "0,0,5400,1000"
st "Package List"
blo "0,800"
)
*159 (MLText
uid 43,0
va (VaSet
)
xt "0,1000,14500,11000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

LIBRARY FACT_FAD_lib;
USE FACT_FAD_lib.fad_definitions.all;
USE ieee.std_logic_textio.all;
LIBRARY std;
USE std.textio.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 44,0
stg "VerticalLayoutStrategy"
textVec [
*160 (Text
uid 45,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,28100,1000"
st "Compiler Directives"
blo "20000,800"
)
*161 (Text
uid 46,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,1000,29600,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*162 (MLText
uid 47,0
va (VaSet
isHidden 1
)
xt "20000,2000,27500,4000"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*163 (Text
uid 48,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,4000,30100,5000"
st "Post-module directives:"
blo "20000,4800"
)
*164 (MLText
uid 49,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*165 (Text
uid 50,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,5000,29900,6000"
st "End-module directives:"
blo "20000,5800"
)
*166 (MLText
uid 51,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "0,22,1281,1024"
viewArea "18877,16600,102696,79721"
cachedDiagramExtent "0,0,146000,98000"
pageSetupInfo (PageSetupInfo
ptrCmd ""
toPrinter 1
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
exportStdIncludeRefs 1
exportStdPackageRefs 1
)
hasePageBreakOrigin 1
pageBreakOrigin "0,0"
lastUid 1311,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,2000,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 2
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Arial,8,1"
)
xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*167 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,3500,5800,4500"
st "<library>"
blo "2200,4300"
tm "BdLibraryNameMgr"
)
*168 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,4500,5600,5500"
st "<block>"
blo "2200,5300"
tm "BlkNameMgr"
)
*169 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,5500,3200,6500"
st "I0"
blo "2200,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "2200,13500,2200,13500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*170 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,3500,3450,4500"
st "Library"
blo "550,4300"
)
*171 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,4500,7450,5500"
st "MWComponent"
blo "550,5300"
)
*172 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,5500,1550,6500"
st "I0"
blo "550,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6450,1500,-6450,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*173 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,3500,3800,4500"
st "Library"
blo "900,4300"
tm "BdLibraryNameMgr"
)
*174 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,4500,7100,5500"
st "SaComponent"
blo "900,5300"
tm "CptNameMgr"
)
*175 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,5500,1900,6500"
st "I0"
blo "900,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6100,1500,-6100,1500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*176 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,3500,3400,4500"
st "Library"
blo "500,4300"
)
*177 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,4500,7500,5500"
st "VhdlComponent"
blo "500,5300"
)
*178 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,5500,1500,6500"
st "I0"
blo "500,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6500,1500,-6500,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-450,0,8450,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*179 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,3500,2950,4500"
st "Library"
blo "50,4300"
)
*180 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,4500,7950,5500"
st "VerilogComponent"
blo "50,5300"
)
*181 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,5500,1050,6500"
st "I0"
blo "50,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6950,1500,-6950,1500"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*182 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,4000,4850,5000"
st "eb1"
blo "3150,4800"
tm "HdlTextNameMgr"
)
*183 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,5000,3950,6000"
st "1"
blo "3150,5800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,2000,1200"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
font "Arial,8,1"
)
xt "-500,-500,500,500"
st "G"
blo "-500,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,1900,1000"
st "sig0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,2400,1000"
st "dbus0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineColor "32768,0,0"
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,3000,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1000,1000,2000"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
)
second (MLText
va (VaSet
)
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 2
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,12600,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*184 (Text
va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*185 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 2
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,7400,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*186 (Text
va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*187 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Courier New,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Arial,8,1"
)
xt "0,12600,5400,13600"
st "Declarations"
blo "0,13400"
)
portLabel (Text
uid 3,0
va (VaSet
font "Arial,8,1"
)
xt "0,13600,2700,14600"
st "Ports:"
blo "0,14400"
)
preUserLabel (Text
uid 4,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "0,12600,3800,13600"
st "Pre User:"
blo "0,13400"
)
preUserText (MLText
uid 5,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "0,12600,0,12600"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Arial,8,1"
)
xt "0,14600,7100,15600"
st "Diagram Signals:"
blo "0,15400"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "0,12600,4700,13600"
st "Post User:"
blo "0,13400"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "0,12600,0,12600"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 39,0
usingSuid 1
emptyRow *188 (LEmptyRow
)
uid 54,0
optionalChildren [
*189 (RefLabelRowHdr
)
*190 (TitleRowHdr
)
*191 (FilterRowHdr
)
*192 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*193 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*194 (GroupColHdr
tm "GroupColHdrMgr"
)
*195 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*196 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*197 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*198 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*199 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*200 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*201 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "clk"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
uid 340,0
)
*202 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 2
suid 2,0
)
)
uid 342,0
)
*203 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 3
suid 3,0
)
)
uid 344,0
)
*204 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_rd"
t "std_logic"
o 4
suid 4,0
i "'1'"
)
)
uid 346,0
)
*205 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_wr"
t "std_logic"
o 5
suid 5,0
i "'1'"
)
)
uid 348,0
)
*206 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 6
suid 6,0
)
)
uid 404,0
)
*207 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sclk"
t "std_logic"
o 7
suid 7,0
)
)
uid 406,0
)
*208 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 8
suid 8,0
)
)
uid 408,0
)
*209 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 9
suid 9,0
)
)
uid 456,0
)
*210 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 10
suid 10,0
)
)
uid 458,0
)
*211 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
o 11
suid 11,0
)
)
uid 460,0
)
*212 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 12
suid 12,0
)
)
uid 584,0
)
*213 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 13
suid 13,0
)
)
uid 586,0
)
*214 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_oeb"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 14,0
)
)
uid 588,0
)
*215 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_otr"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 16
suid 16,0
)
)
uid 590,0
)
*216 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_data"
t "std_logic_vector"
b "(11 DOWNTO 0)"
preAdd 0
posAdd 0
o 17
suid 17,0
)
)
uid 592,0
)
*217 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_reset"
t "std_logic"
o 21
suid 23,0
i "'1'"
)
)
uid 903,0
)
*218 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 22
suid 24,0
i "(OTHERS => '0')"
)
)
uid 905,0
)
*219 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_cs"
t "std_logic"
o 23
suid 25,0
i "'1'"
)
)
uid 907,0
)
*220 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_int"
t "std_logic"
o 24
suid 26,0
)
)
uid 909,0
)
*221 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dac_cs"
t "std_logic"
o 25
suid 27,0
)
)
uid 911,0
)
*222 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "mosi"
t "std_logic"
o 26
suid 28,0
i "'0'"
)
)
uid 913,0
)
*223 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 27
suid 29,0
i "'0'"
)
)
uid 915,0
)
*224 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 28
suid 30,0
)
)
uid 917,0
)
*225 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "CLK_50"
t "std_logic"
o 29
suid 31,0
)
)
uid 919,0
)
*226 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 30
suid 32,0
i "(others => '0')"
)
)
uid 921,0
)
*227 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_dwrite"
t "std_logic"
o 31
suid 33,0
i "'1'"
)
)
uid 923,0
)
*228 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "RSRLOAD"
t "std_logic"
o 32
suid 34,0
i "'0'"
)
)
uid 925,0
)
*229 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SRCLK"
t "std_logic"
o 33
suid 35,0
i "'0'"
)
)
uid 927,0
)
*230 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 30
suid 36,0
)
)
uid 929,0
)
*231 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 31
suid 37,0
)
)
uid 931,0
)
*232 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 32
suid 38,0
)
)
uid 933,0
)
*233 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 33
suid 39,0
)
)
uid 935,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 67,0
optionalChildren [
*234 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *235 (MRCItem
litem &188
pos 33
dimension 20
)
uid 69,0
optionalChildren [
*236 (MRCItem
litem &189
pos 0
dimension 20
uid 70,0
)
*237 (MRCItem
litem &190
pos 1
dimension 23
uid 71,0
)
*238 (MRCItem
litem &191
pos 2
hidden 1
dimension 20
uid 72,0
)
*239 (MRCItem
litem &201
pos 0
dimension 20
uid 341,0
)
*240 (MRCItem
litem &202
pos 1
dimension 20
uid 343,0
)
*241 (MRCItem
litem &203
pos 2
dimension 20
uid 345,0
)
*242 (MRCItem
litem &204
pos 3
dimension 20
uid 347,0
)
*243 (MRCItem
litem &205
pos 4
dimension 20
uid 349,0
)
*244 (MRCItem
litem &206
pos 5
dimension 20
uid 405,0
)
*245 (MRCItem
litem &207
pos 6
dimension 20
uid 407,0
)
*246 (MRCItem
litem &208
pos 7
dimension 20
uid 409,0
)
*247 (MRCItem
litem &209
pos 8
dimension 20
uid 457,0
)
*248 (MRCItem
litem &210
pos 9
dimension 20
uid 459,0
)
*249 (MRCItem
litem &211
pos 10
dimension 20
uid 461,0
)
*250 (MRCItem
litem &212
pos 11
dimension 20
uid 585,0
)
*251 (MRCItem
litem &213
pos 12
dimension 20
uid 587,0
)
*252 (MRCItem
litem &214
pos 13
dimension 20
uid 589,0
)
*253 (MRCItem
litem &215
pos 14
dimension 20
uid 591,0
)
*254 (MRCItem
litem &216
pos 15
dimension 20
uid 593,0
)
*255 (MRCItem
litem &217
pos 16
dimension 20
uid 904,0
)
*256 (MRCItem
litem &218
pos 17
dimension 20
uid 906,0
)
*257 (MRCItem
litem &219
pos 18
dimension 20
uid 908,0
)
*258 (MRCItem
litem &220
pos 19
dimension 20
uid 910,0
)
*259 (MRCItem
litem &221
pos 20
dimension 20
uid 912,0
)
*260 (MRCItem
litem &222
pos 21
dimension 20
uid 914,0
)
*261 (MRCItem
litem &223
pos 22
dimension 20
uid 916,0
)
*262 (MRCItem
litem &224
pos 23
dimension 20
uid 918,0
)
*263 (MRCItem
litem &225
pos 24
dimension 20
uid 920,0
)
*264 (MRCItem
litem &226
pos 25
dimension 20
uid 922,0
)
*265 (MRCItem
litem &227
pos 26
dimension 20
uid 924,0
)
*266 (MRCItem
litem &228
pos 27
dimension 20
uid 926,0
)
*267 (MRCItem
litem &229
pos 28
dimension 20
uid 928,0
)
*268 (MRCItem
litem &230
pos 29
dimension 20
uid 930,0
)
*269 (MRCItem
litem &231
pos 30
dimension 20
uid 932,0
)
*270 (MRCItem
litem &232
pos 31
dimension 20
uid 934,0
)
*271 (MRCItem
litem &233
pos 32
dimension 20
uid 936,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 73,0
optionalChildren [
*272 (MRCItem
litem &192
pos 0
dimension 20
uid 74,0
)
*273 (MRCItem
litem &194
pos 1
dimension 50
uid 75,0
)
*274 (MRCItem
litem &195
pos 2
dimension 100
uid 76,0
)
*275 (MRCItem
litem &196
pos 3
dimension 50
uid 77,0
)
*276 (MRCItem
litem &197
pos 4
dimension 100
uid 78,0
)
*277 (MRCItem
litem &198
pos 5
dimension 100
uid 79,0
)
*278 (MRCItem
litem &199
pos 6
dimension 50
uid 80,0
)
*279 (MRCItem
litem &200
pos 7
dimension 80
uid 81,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 68,0
vaOverrides [
]
)
]
)
uid 53,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *280 (LEmptyRow
)
uid 83,0
optionalChildren [
*281 (RefLabelRowHdr
)
*282 (TitleRowHdr
)
*283 (FilterRowHdr
)
*284 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*285 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*286 (GroupColHdr
tm "GroupColHdrMgr"
)
*287 (NameColHdr
tm "GenericNameColHdrMgr"
)
*288 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*289 (InitColHdr
tm "GenericValueColHdrMgr"
)
*290 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*291 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 95,0
optionalChildren [
*292 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *293 (MRCItem
litem &280
pos 0
dimension 20
)
uid 97,0
optionalChildren [
*294 (MRCItem
litem &281
pos 0
dimension 20
uid 98,0
)
*295 (MRCItem
litem &282
pos 1
dimension 23
uid 99,0
)
*296 (MRCItem
litem &283
pos 2
hidden 1
dimension 20
uid 100,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 101,0
optionalChildren [
*297 (MRCItem
litem &284
pos 0
dimension 20
uid 102,0
)
*298 (MRCItem
litem &286
pos 1
dimension 50
uid 103,0
)
*299 (MRCItem
litem &287
pos 2
dimension 100
uid 104,0
)
*300 (MRCItem
litem &288
pos 3
dimension 100
uid 105,0
)
*301 (MRCItem
litem &289
pos 4
dimension 50
uid 106,0
)
*302 (MRCItem
litem &290
pos 5
dimension 50
uid 107,0
)
*303 (MRCItem
litem &291
pos 6
dimension 80
uid 108,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 96,0
vaOverrides [
]
)
]
)
uid 82,0
type 1
)
activeModelName "BlockDiag"
)
