ARCHITECTURES list {
 {controlram_16bit_x256 controlram_16bit_x256_a} list {
  COREGEN_INFO list {
   COREGEN_VIEW atom 1
   PATH atom .hdlsidedata/controlRAM_16bit_x256_controlRAM_16bit_x256_a.vhd.info/Coregen/controlRAM_16bit_x256.xco
  }
  SYNTHESIS_FILE list {
   TECH_INFO atom {controlRAM_16bit_x256.ngc:Xilinx spartan3a}
   IS_ACTIVE atom 1
   PATH atom Synthesis/controlRAM_16bit_x256.ngc
  }
  TASK_SETTINGS list {
   PLUGIN_SETTINGS list {
    XilinxCoregen atom {TaskSetting appPath {$XILINX} TaskSetting lang VHDL TaskSetting libraryMode 1 TaskSetting family acr2 TaskSetting synthesisTool MentorHDL TaskSetting busFormat B(n:m) TaskSetting createInLib FACT_FAD_lib TaskSetting replace 1 TaskSetting ignoreError 0 TaskSetting setDontTouch 1 TaskSetting additionalOpts {} TaskSetting vhdlConvention %(entity_name)_%(arch_name).vhd TaskSetting verConvention %(unit)_%(view).vhd}
   }
  }
 }
}
INCLUDE list {
 DEFAULT atom 1
}
