DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
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(DmPackageRef
library "ieee"
unitName "std_logic_1164"
itemName "ALL"
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(DmPackageRef
library "ieee"
unitName "std_logic_arith"
itemName "ALL"
)
(DmPackageRef
library "ieee"
unitName "std_logic_unsigned"
itemName "ALL"
)
(DmPackageRef
library "FACT_FAD_LIB"
unitName "fad_definitions"
itemName "ALL"
)
]
libraryRefs [
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"FACT_FAD_LIB"
]
)
version "24.1"
appVersion "2009.2 (Build 10)"
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VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.user"
)
(vvPair
variable "SourceDir"
value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "symbol"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager"
)
(vvPair
variable "d_logical"
value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager"
)
(vvPair
variable "date"
value "12.07.2010"
)
(vvPair
variable "day"
value "Mo"
)
(vvPair
variable "day_long"
value "Montag"
)
(vvPair
variable "dd"
value "12"
)
(vvPair
variable "entity_name"
value "control_manager"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "symbol.sb"
)
(vvPair
variable "f_logical"
value "symbol.sb"
)
(vvPair
variable "f_noext"
value "symbol"
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(vvPair
variable "group"
value "UNKNOWN"
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(vvPair
variable "host"
value "TU-CC4900F8C7D2"
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(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_lib"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/work"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "mm"
value "07"
)
(vvPair
variable "module_name"
value "control_manager"
)
(vvPair
variable "month"
value "Jul"
)
(vvPair
variable "month_long"
value "Juli"
)
(vvPair
variable "p"
value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb"
)
(vvPair
variable "p_logical"
value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "<TBD>"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "sb"
)
(vvPair
variable "this_file"
value "symbol"
)
(vvPair
variable "this_file_logical"
value "symbol"
)
(vvPair
variable "time"
value "14:11:44"
)
(vvPair
variable "unit"
value "control_manager"
)
(vvPair
variable "user"
value "dneise"
)
(vvPair
variable "version"
value "2009.2 (Build 10)"
)
(vvPair
variable "view"
value "symbol"
)
(vvPair
variable "year"
value "2010"
)
(vvPair
variable "yy"
value "10"
)
]
)
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Created using Mentor Graphics HDL2Graphics(TM) Technology
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xt "0,750,1400,1750"
st "In0"
blo "0,1550"
tm "CptPortNameMgr"
)
)
dt (MLText
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "In0"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
defaultCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
bg "0,0,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,2800,1750"
st "Buffer0"
blo "0,1550"
tm "CptPortNameMgr"
)
)
dt (MLText
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Buffer0"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
DeclarativeBlock *129 (SymDeclBlock
uid 1,0
stg "SymDeclLayoutStrategy"
declLabel (Text
uid 2,0
va (VaSet
font "Arial,8,1"
)
xt "0,9000,5400,10000"
st "Declarations"
blo "0,9800"
)
portLabel (Text
uid 3,0
va (VaSet
font "Arial,8,1"
)
xt "0,10000,2700,11000"
st "Ports:"
blo "0,10800"
)
externalLabel (Text
uid 4,0
va (VaSet
font "Arial,8,1"
)
xt "0,25400,2400,26400"
st "User:"
blo "0,26200"
)
internalLabel (Text
uid 6,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "0,9000,5800,10000"
st "Internal User:"
blo "0,9800"
)
externalText (MLText
uid 5,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,26400,2000,26400"
tm "SyDeclarativeTextMgr"
)
internalText (MLText
uid 7,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "0,9000,0,9000"
tm "SyDeclarativeTextMgr"
)
)
lastUid 547,0
activeModelName "Symbol:CDM"
)
