Index: /firmware/FTU/FTU_top.vhd =================================================================== --- /firmware/FTU/FTU_top.vhd (revision 9927) +++ /firmware/FTU/FTU_top.vhd (revision 9928) @@ -27,4 +27,5 @@ library ftu_definitions; USE ftu_definitions.ftu_array_types.all; +USE ftu_definitions.ftu_constants.all; ---- Uncomment the following library declaration if instantiating @@ -174,15 +175,46 @@ component FTU_spi_interface port( - clk_50MHz : IN std_logic; - config_start : IN std_logic; - dac_array : IN dac_array_type; - config_ready : OUT std_logic; - config_started : OUT std_logic; - dac_cs : OUT std_logic; - mosi : OUT std_logic; - sclk : OUT std_logic - ); - end component; - + clk_50MHz : IN std_logic; + config_start : IN std_logic; + dac_array : IN dac_array_type; + config_ready : OUT std_logic; + config_started : OUT std_logic; + dac_cs : OUT std_logic; + mosi : OUT std_logic; + sclk : OUT std_logic + ); + end component; + + component FTU_rs485_control + port( + main_clk : IN std_logic; + brd_add : IN std_logic_vector(5 downto 0); + rx_d : IN std_logic; + rates_ready : IN std_logic; + DACs_ready : IN std_logic; + enables_ready : IN std_logic; + prescaling_ready : IN std_logic; + rate_array_rs485 : IN rate_array_type; + overflow_array_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0); + dac_array_rs485_in : IN dac_array_type; + enable_array_rs485_in : IN enable_array_type; + prescaling_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0); + rx_en : OUT std_logic; + tx_d : OUT std_logic; + tx_en : OUT std_logic; + new_DACs : OUT std_logic; + new_enables : OUT std_logic; + new_prescaling : OUT std_logic; + read_rates : OUT std_logic; + read_DACs : OUT std_logic; + read_enables : OUT std_logic; + read_prescaling : OUT std_logic; + --rs485_error : OUT std_logic; -- to be discussed! + dac_array_rs485_out : OUT dac_array_type; + enable_array_rs485_out : OUT enable_array_type; + prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0) + ); + end component; + component FTU_dual_port_ram port( @@ -362,4 +394,34 @@ ); + Inst_FTU_rs485_control : FTU_rs485_control + port map( + main_clk => clk_50M_sig, + brd_add => brd_add, + rx_d => rx, + rates_ready => '0', + DACs_ready => '0', + enables_ready => '0', + prescaling_ready => '0', + rate_array_rs485 => (0,0,0,0,0), + overflow_array_rs485_in => "00000000", + dac_array_rs485_in => DEFAULT_DAC, + enable_array_rs485_in => DEFAULT_ENABLE, + prescaling_rs485_in => conv_std_logic_vector(DEFAULT_PRESCALING,8), + rx_en => rx_en, + tx_d => tx, + tx_en => tx_en, + new_DACs => open, + new_enables => open, + new_prescaling => open, + read_rates => open, + read_DACs => open, + read_enables => open, + read_prescaling => open, + --rs485_error =>, -- to be discussed! + dac_array_rs485_out => open, + enable_array_rs485_out => open, + prescaling_rs485_out => open + ); + Inst_FTU_dual_port_ram : FTU_dual_port_ram port map( Index: /firmware/FTU/FTU_top_tb.vhd =================================================================== --- /firmware/FTU/FTU_top_tb.vhd (revision 9927) +++ /firmware/FTU/FTU_top_tb.vhd (revision 9928) @@ -98,5 +98,5 @@ signal trig_prim_p : STD_LOGIC := '0'; signal trig_prim_n : STD_LOGIC := '0'; - signal rx : STD_LOGIC := '0'; + signal rx : STD_LOGIC := '1'; --Outputs @@ -123,5 +123,6 @@ -- Clock period definitions constant ext_clk_period : TIME := 20 ns; - + constant baud_rate_period : TIME := 10 us; + begin @@ -205,5 +206,7 @@ stim_proc: process begin + --------------------------------------------------------------------------- -- FTU not yet initialized + --------------------------------------------------------------------------- wait for 10us; trigger_sig <= '1'; @@ -218,5 +221,7 @@ wait for 5ns; trigger_sig <= '0'; + --------------------------------------------------------------------------- -- now FTU is initialized + --------------------------------------------------------------------------- wait for 4us; trigger_sig <= '1'; @@ -231,4 +236,392 @@ wait for 5ns; trigger_sig <= '0'; + --------------------------------------------------------------------------- + -- test now RS485 + --------------------------------------------------------------------------- + wait for 100us; + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= '0'; --start delimiter bit 0 + wait for baud_rate_period; + rx <= '0'; --start delimiter bit 1 + wait for baud_rate_period; + rx <= '0'; --start delimiter bit 2 + wait for baud_rate_period; + rx <= '0'; --start delimiter bit 3 + wait for baud_rate_period; + rx <= '0'; --start delimiter bit 4 + wait for baud_rate_period; + rx <= '0'; --start delimiter bit 5 + wait for baud_rate_period; + rx <= '1'; --start delimiter bit 6 + wait for baud_rate_period; + rx <= '0'; --start delimiter bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + --------------------------------------------------------------------------- + wait for 1us; + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= '0'; --FTU address bit 0 + wait for baud_rate_period; + rx <= '0'; --FTU address bit 1 + wait for baud_rate_period; + rx <= '0'; --FTU address bit 2 + wait for baud_rate_period; + rx <= '0'; --FTU address bit 3 + wait for baud_rate_period; + rx <= '0'; --FTU address bit 4 + wait for baud_rate_period; + rx <= '0'; --FTU address bit 5 + wait for baud_rate_period; + rx <= '0'; --FTU address bit 6 + wait for baud_rate_period; + rx <= '0'; --FTU address bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + --------------------------------------------------------------------------- + wait for 10ns; + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= '0'; --FTM address bit 0 + wait for baud_rate_period; + rx <= '0'; --FTM address bit 1 + wait for baud_rate_period; + rx <= '0'; --FTM address bit 2 + wait for baud_rate_period; + rx <= '0'; --FTM address bit 3 + wait for baud_rate_period; + rx <= '0'; --FTM address bit 4 + wait for baud_rate_period; + rx <= '0'; --FTM address bit 5 + wait for baud_rate_period; + rx <= '1'; --FTM address bit 6 + wait for baud_rate_period; + rx <= '1'; --FTM address bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + --------------------------------------------------------------------------- + wait for 100ns; + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= '0'; --instruction bit 0 + wait for baud_rate_period; + rx <= '1'; --instruction bit 1 + wait for baud_rate_period; + rx <= '0'; --instruction bit 2 + wait for baud_rate_period; + rx <= '0'; --instruction bit 3 + wait for baud_rate_period; + rx <= '0'; --instruction bit 4 + wait for baud_rate_period; + rx <= '0'; --instruction bit 5 + wait for baud_rate_period; + rx <= '0'; --instruction bit 6 + wait for baud_rate_period; + rx <= '0'; --instruction bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + --------------------------------------------------------------------------- + wait for 200us; + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= '0'; --data1 bit 0 + wait for baud_rate_period; + rx <= '0'; --data1 bit 1 + wait for baud_rate_period; + rx <= '0'; --data1 bit 2 + wait for baud_rate_period; + rx <= '0'; --data1 bit 3 + wait for baud_rate_period; + rx <= '0'; --data1 bit 4 + wait for baud_rate_period; + rx <= '0'; --data1 bit 5 + wait for baud_rate_period; + rx <= '0'; --data1 bit 6 + wait for baud_rate_period; + rx <= '0'; --data1 bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + --------------------------------------------------------------------------- + wait for 100ns; + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= '0'; --data2 bit 0 + wait for baud_rate_period; + rx <= '0'; --data2 bit 1 + wait for baud_rate_period; + rx <= '0'; --data2 bit 2 + wait for baud_rate_period; + rx <= '0'; --data2 bit 3 + wait for baud_rate_period; + rx <= '0'; --data2 bit 4 + wait for baud_rate_period; + rx <= '0'; --data2 bit 5 + wait for baud_rate_period; + rx <= '0'; --data2 bit 6 + wait for baud_rate_period; + rx <= '0'; --data2 bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + --------------------------------------------------------------------------- + wait for 100ns; + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= '0'; --data3 bit 0 + wait for baud_rate_period; + rx <= '0'; --data3 bit 1 + wait for baud_rate_period; + rx <= '0'; --data3 bit 2 + wait for baud_rate_period; + rx <= '0'; --data3 bit 3 + wait for baud_rate_period; + rx <= '0'; --data3 bit 4 + wait for baud_rate_period; + rx <= '0'; --data3 bit 5 + wait for baud_rate_period; + rx <= '0'; --data3 bit 6 + wait for baud_rate_period; + rx <= '0'; --data3 bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + --------------------------------------------------------------------------- + wait for 100ns; + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= '0'; --data4 bit 0 + wait for baud_rate_period; + rx <= '0'; --data4 bit 1 + wait for baud_rate_period; + rx <= '0'; --data4 bit 2 + wait for baud_rate_period; + rx <= '0'; --data4 bit 3 + wait for baud_rate_period; + rx <= '0'; --data4 bit 4 + wait for baud_rate_period; + rx <= '0'; --data4 bit 5 + wait for baud_rate_period; + rx <= '0'; --data4 bit 6 + wait for baud_rate_period; + rx <= '0'; --data4 bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + --------------------------------------------------------------------------- + wait for 100ns; + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= '0'; --data5 bit 0 + wait for baud_rate_period; + rx <= '0'; --data5 bit 1 + wait for baud_rate_period; + rx <= '0'; --data5 bit 2 + wait for baud_rate_period; + rx <= '0'; --data5 bit 3 + wait for baud_rate_period; + rx <= '0'; --data5 bit 4 + wait for baud_rate_period; + rx <= '0'; --data5 bit 5 + wait for baud_rate_period; + rx <= '0'; --data5 bit 6 + wait for baud_rate_period; + rx <= '0'; --data5 bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + --------------------------------------------------------------------------- + wait for 100ns; + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= '0'; --data6 bit 0 + wait for baud_rate_period; + rx <= '0'; --data6 bit 1 + wait for baud_rate_period; + rx <= '0'; --data6 bit 2 + wait for baud_rate_period; + rx <= '0'; --data6 bit 3 + wait for baud_rate_period; + rx <= '0'; --data6 bit 4 + wait for baud_rate_period; + rx <= '0'; --data6 bit 5 + wait for baud_rate_period; + rx <= '0'; --data6 bit 6 + wait for baud_rate_period; + rx <= '0'; --data6 bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + --------------------------------------------------------------------------- + wait for 100ns; + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= '0'; --data7 bit 0 + wait for baud_rate_period; + rx <= '0'; --data7 bit 1 + wait for baud_rate_period; + rx <= '0'; --data7 bit 2 + wait for baud_rate_period; + rx <= '0'; --data7 bit 3 + wait for baud_rate_period; + rx <= '0'; --data7 bit 4 + wait for baud_rate_period; + rx <= '0'; --data7 bit 5 + wait for baud_rate_period; + rx <= '0'; --data7 bit 6 + wait for baud_rate_period; + rx <= '0'; --data7 bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + --------------------------------------------------------------------------- + wait for 100ns; + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= '0'; --data8 bit 0 + wait for baud_rate_period; + rx <= '0'; --data8 bit 1 + wait for baud_rate_period; + rx <= '0'; --data8 bit 2 + wait for baud_rate_period; + rx <= '0'; --data8 bit 3 + wait for baud_rate_period; + rx <= '0'; --data8 bit 4 + wait for baud_rate_period; + rx <= '0'; --data8 bit 5 + wait for baud_rate_period; + rx <= '0'; --data8 bit 6 + wait for baud_rate_period; + rx <= '0'; --data8 bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + --------------------------------------------------------------------------- + wait for 100ns; + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= '0'; --data9 bit 0 + wait for baud_rate_period; + rx <= '0'; --data9 bit 1 + wait for baud_rate_period; + rx <= '0'; --data9 bit 2 + wait for baud_rate_period; + rx <= '0'; --data9 bit 3 + wait for baud_rate_period; + rx <= '0'; --data9 bit 4 + wait for baud_rate_period; + rx <= '0'; --data9 bit 5 + wait for baud_rate_period; + rx <= '0'; --data9 bit 6 + wait for baud_rate_period; + rx <= '0'; --data9 bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + --------------------------------------------------------------------------- + wait for 100ns; + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= '0'; --data10 bit 0 + wait for baud_rate_period; + rx <= '0'; --data10 bit 1 + wait for baud_rate_period; + rx <= '0'; --data10 bit 2 + wait for baud_rate_period; + rx <= '0'; --data10 bit 3 + wait for baud_rate_period; + rx <= '0'; --data10 bit 4 + wait for baud_rate_period; + rx <= '0'; --data10 bit 5 + wait for baud_rate_period; + rx <= '0'; --data10 bit 6 + wait for baud_rate_period; + rx <= '0'; --data10 bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + --------------------------------------------------------------------------- + wait for 100ns; + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= '0'; --data11 bit 0 + wait for baud_rate_period; + rx <= '0'; --data11 bit 1 + wait for baud_rate_period; + rx <= '0'; --data11 bit 2 + wait for baud_rate_period; + rx <= '0'; --data11 bit 3 + wait for baud_rate_period; + rx <= '0'; --data11 bit 4 + wait for baud_rate_period; + rx <= '0'; --data11 bit 5 + wait for baud_rate_period; + rx <= '0'; --data11 bit 6 + wait for baud_rate_period; + rx <= '0'; --data11 bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + --------------------------------------------------------------------------- + wait for 100ns; + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= '0'; --check sum bit 0 + wait for baud_rate_period; + rx <= '0'; --check sum bit 1 + wait for baud_rate_period; + rx <= '0'; --check sum bit 2 + wait for baud_rate_period; + rx <= '0'; --check sum bit 3 + wait for baud_rate_period; + rx <= '0'; --check sum bit 4 + wait for baud_rate_period; + rx <= '0'; --check sum bit 5 + wait for baud_rate_period; + rx <= '0'; --check sum bit 6 + wait for baud_rate_period; + rx <= '0'; --check sum bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + --------------------------------------------------------------------------- + rx <= '1'; wait; Index: /firmware/FTU/ftu_definitions.vhd =================================================================== --- /firmware/FTU/ftu_definitions.vhd (revision 9927) +++ /firmware/FTU/ftu_definitions.vhd (revision 9928) @@ -58,5 +58,5 @@ constant INT_CLK_FREQUENCY : integer := 50000000; -- 50MHz constant COUNTER_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY - constant CNTR_FREQ_DIVIDER : integer := 500000; + constant CNTR_FREQ_DIVIDER : integer := 500000; -- for simulation, should normally be 1 --32byte dual-port RAM, port A: 8byte, port B: 16byte @@ -72,4 +72,10 @@ constant NO_OF_DAC_NOT_USED : integer := 3; constant NO_OF_COUNTER : integer := 5; + + --communication with FTM + constant RS485_BAUD_RATE : integer := 100000; -- bits / sec in our case + constant RS485_BLOCK_WIDTH : integer := 128; -- 16 byte protocol + constant RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter + constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192 end ftu_constants; Index: /firmware/FTU/rs485/FTU_rs485_control.vhd =================================================================== --- /firmware/FTU/rs485/FTU_rs485_control.vhd (revision 9928) +++ /firmware/FTU/rs485/FTU_rs485_control.vhd (revision 9928) @@ -0,0 +1,878 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Q. Weitzel, P. Vogler +-- +-- Create Date: 09/13/2010 +-- Design Name: +-- Module Name: FTU_rs485_control - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: top level entity of FTU RS485 module +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library ftu_definitions; +USE ftu_definitions.ftu_array_types.all; +USE ftu_definitions.ftu_constants.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTU_rs485_control is + port( + main_clk : IN std_logic; + brd_add : IN std_logic_vector(5 downto 0); + rx_d : IN std_logic; + rates_ready : IN std_logic; -- rate_array_rs485 has now valid rates for sending + DACs_ready : IN std_logic; -- dac_array_rs485_in is ok for sending + enables_ready : IN std_logic; -- enable_array_rs485_in is ok for sending + prescaling_ready : IN std_logic; -- prescaling byte is ok for sending + rate_array_rs485 : IN rate_array_type; + overflow_array_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0); + dac_array_rs485_in : IN dac_array_type; + enable_array_rs485_in : IN enable_array_type; + prescaling_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0); + rx_en : OUT std_logic; + tx_d : OUT std_logic; + tx_en : OUT std_logic; + new_DACs : OUT std_logic; -- new DACs arrived via RS485 + new_enables : OUT std_logic; -- new enables arrived via RS485 + new_prescaling : OUT std_logic; -- new prescaling arrived via RS485 + read_rates : OUT std_logic; -- FTM wants to read rates + read_DACs : OUT std_logic; -- FTM wants to read DACs + read_enables : OUT std_logic; -- FTM wants to read enable pattern + read_prescaling : OUT std_logic; -- FTM wants to read prescaling value + --rs485_error : OUT std_logic; -- to be discussed! + dac_array_rs485_out : OUT dac_array_type; + enable_array_rs485_out : OUT enable_array_type; + prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0) + ); +end FTU_rs485_control; + +architecture Behavioral of FTU_rs485_control is + + signal tx_start_sig : std_logic := '0'; + signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0'); + signal tx_busy_sig : std_logic; -- initialized in FTU_rs485_interface + + signal rx_valid_sig : std_logic; -- initialized in FTU_rs485_interface + signal rx_data_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTU_rs485_interface + signal rx_busy_sig : std_logic; -- initialized in FTU_rs485_interface + + signal block_valid_sig : std_logic; -- initialized in FTU_rs485_receiver + signal data_block_sig : std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0); -- initialized in FTU_rs485_receiver + + signal int_new_DACs_sig : std_logic; -- initialized in FTU_rs485_interpreter + signal int_new_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter + signal int_new_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter + signal int_read_rates_sig : std_logic; -- initialized in FTU_rs485_interpreter + signal int_read_DACs_sig : std_logic; -- initialized in FTU_rs485_interpreter + signal int_read_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter + signal int_read_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter + + signal txcnt : integer range 0 to (RS485_BLOCK_WIDTH / 8) := 0; -- count 16 1-byte frames + + component FTU_rs485_receiver + port( + rec_clk : in std_logic; + --rx_busy : in std_logic; + rec_din : in std_logic_vector(7 downto 0); + rec_den : in std_logic; + rec_dout : out std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0); + rec_valid : out std_logic + ); + end component; + + component FTU_rs485_interpreter + port( + clk : IN std_logic; + data_block : IN std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0); + block_valid : IN std_logic; + brd_add : IN std_logic_vector(5 downto 0); + int_new_DACs : OUT std_logic; + int_new_enables : OUT std_logic; + int_new_prescaling : OUT std_logic; + int_read_rates : OUT std_logic; + int_read_DACs : OUT std_logic; + int_read_enables : OUT std_logic; + int_read_prescaling : OUT std_logic; + dac_array_rs485_out : OUT dac_array_type; + enable_array_rs485_out : OUT enable_array_type; + prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0) + ); + end component; + + component FTU_rs485_interface + port( + clk : IN std_logic; + -- RS485 + rx_d : IN std_logic; + rx_en : OUT std_logic; + tx_d : OUT std_logic; + tx_en : OUT std_logic; + -- FPGA + rx_data : OUT std_logic_vector (7 DOWNTO 0); + rx_busy : OUT std_logic := '0'; + rx_valid : OUT std_logic := '0'; + tx_data : IN std_logic_vector (7 DOWNTO 0); + tx_busy : OUT std_logic := '0'; + tx_start : IN std_logic + ); + end component; + + type FTU_rs485_control_StateType is (RECEIVE, + READ_RATES_WAIT, READ_DAC_WAIT, READ_ENABLE_WAIT, READ_PRESCALING_WAIT, + SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT, + READ_RATES_TRANSMIT, READ_DAC_TRANSMIT, READ_ENABLE_TRANSMIT, READ_PRESCALING_TRANSMIT, + SET_DAC_TRANSMIT, SET_ENABLE_TRANSMIT, SET_PRESCALING_TRANSMIT); + signal FTU_rs485_control_State : FTU_rs485_control_StateType; + +begin + + Inst_FTU_rs485_receiver : FTU_rs485_receiver + port map( + rec_clk => main_clk, + --rx_busy =>, + rec_din => rx_data_sig, + rec_den => rx_valid_sig, + rec_dout => data_block_sig, + rec_valid => block_valid_sig + ); + + Inst_FTU_rs485_interpreter : FTU_rs485_interpreter + port map( + clk => main_clk, + data_block => data_block_sig, + block_valid => block_valid_sig, + brd_add => brd_add, + int_new_DACs => int_new_DACs_sig, + int_new_enables => int_new_enables_sig, + int_new_prescaling => int_new_prescaling_sig, + int_read_rates => int_read_rates_sig, + int_read_DACs => int_read_DACs_sig, + int_read_enables => int_read_enables_sig, + int_read_prescaling => int_read_prescaling_sig, + dac_array_rs485_out => dac_array_rs485_out, + enable_array_rs485_out => enable_array_rs485_out, + prescaling_rs485_out => prescaling_rs485_out + ); + + Inst_FTU_rs485_interface : FTU_rs485_interface + port map( + clk => main_clk, + -- RS485 + rx_d => rx_d, + rx_en => rx_en, + tx_d => tx_d, + tx_en => tx_en, + -- FPGA + rx_data => rx_data_sig, + rx_busy => rx_busy_sig, + rx_valid => rx_valid_sig, + tx_data => tx_data_sig, + tx_busy => tx_busy_sig, + tx_start => tx_start_sig + ); + + --FTU RS485 control finite state machine + + FTU_rs485_control_FSM: process (main_clk) + begin + if Rising_edge(main_clk) then + case FTU_rs485_control_State is + + when RECEIVE => -- default state, receiver on, no transmission + tx_start_sig <= '0'; + if (int_new_DACs_sig = '1') then + new_DACs <= '1'; + new_enables <= '0'; + new_prescaling <= '0'; + read_rates <= '0'; + read_DACs <= '0'; + read_enables <= '0'; + read_prescaling <= '0'; + FTU_rs485_control_State <= SET_DAC_WAIT; + elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '1') then + new_DACs <= '0'; + new_enables <= '1'; + new_prescaling <= '0'; + read_rates <= '0'; + read_DACs <= '0'; + read_enables <= '0'; + read_prescaling <= '0'; + FTU_rs485_control_State <= SET_ENABLE_WAIT; + elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '1') then + new_DACs <= '0'; + new_enables <= '0'; + new_prescaling <= '1'; + read_rates <= '0'; + read_DACs <= '0'; + read_enables <= '0'; + read_prescaling <= '0'; + FTU_rs485_control_State <= SET_PRESCALING_WAIT; + elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and + int_read_rates_sig = '1') then + new_DACs <= '0'; + new_enables <= '0'; + new_prescaling <= '0'; + read_rates <= '1'; + read_DACs <= '0'; + read_enables <= '0'; + read_prescaling <= '0'; + FTU_rs485_control_State <= READ_RATES_WAIT; + elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and + int_read_rates_sig = '0' and int_read_DACs_sig = '1') then + new_DACs <= '0'; + new_enables <= '0'; + new_prescaling <= '0'; + read_rates <= '0'; + read_DACs <= '1'; + read_enables <= '0'; + read_prescaling <= '0'; + FTU_rs485_control_State <= READ_DAC_WAIT; + elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and + int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '1') then + new_DACs <= '0'; + new_enables <= '0'; + new_prescaling <= '0'; + read_rates <= '0'; + read_DACs <= '0'; + read_enables <= '1'; + read_prescaling <= '0'; + FTU_rs485_control_State <= READ_ENABLE_WAIT; + elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and + int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '0' and int_read_prescaling_sig = '1') then + new_DACs <= '0'; + new_enables <= '0'; + new_prescaling <= '0'; + read_rates <= '0'; + read_DACs <= '0'; + read_enables <= '0'; + read_prescaling <= '1'; + FTU_rs485_control_State <= READ_PRESCALING_WAIT; + else + new_DACs <= '0'; + new_enables <= '0'; + new_prescaling <= '0'; + read_rates <= '0'; + read_DACs <= '0'; + read_enables <= '0'; + read_prescaling <= '0'; + FTU_rs485_control_State <= RECEIVE; + end if; + + when SET_DAC_WAIT=> -- wait until FTU control says "done" and then answer to FTM + if (DACs_ready = '1') then + new_DACs <= '0'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + else + new_DACs <= '1'; + FTU_rs485_control_State <= SET_DAC_WAIT; + end if; + + when SET_ENABLE_WAIT => -- wait until FTU control says "done" and then answer to FTM + if (enables_ready = '1') then + new_enables <= '0'; + FTU_rs485_control_State <= RECEIVE; + else + new_enables <= '1'; + FTU_rs485_control_State <= SET_ENABLE_WAIT; + end if; + + when SET_PRESCALING_WAIT => -- wait until FTU control says "done" and then answer to FTM + if (prescaling_ready = '1') then + new_prescaling <= '0'; + FTU_rs485_control_State <= RECEIVE; + else + new_prescaling <= '1'; + FTU_rs485_control_State <= SET_PRESCALING_WAIT; + end if; + + when READ_RATES_WAIT => -- wait until FTU control says "done" and then answer to FTM + if (rates_ready = '1') then + read_rates <= '0'; + FTU_rs485_control_State <= RECEIVE; + else + read_rates <= '1'; + FTU_rs485_control_State <= READ_RATES_WAIT; + end if; + + when READ_DAC_WAIT => -- wait until FTU control says "done" and then answer to FTM + if (DACs_ready = '1') then + read_DACs <= '0'; + FTU_rs485_control_State <= RECEIVE; + else + read_DACs <= '1'; + FTU_rs485_control_State <= READ_DAC_WAIT; + end if; + + when READ_ENABLE_WAIT => -- wait until FTU control says "done" and then answer to FTM + if (enables_ready = '1') then + read_enables <= '0'; + FTU_rs485_control_State <= RECEIVE; + else + read_enables <= '1'; + FTU_rs485_control_State <= READ_ENABLE_WAIT; + end if; + + when READ_PRESCALING_WAIT => -- wait until FTU control says "done" and then answer to FTM + if (prescaling_ready = '1') then + read_prescaling <= '0'; + FTU_rs485_control_State <= RECEIVE; + else + read_prescaling <= '1'; + FTU_rs485_control_State <= READ_PRESCALING_WAIT; + end if; + + when SET_DAC_TRANSMIT => + if tx_busy_sig = '0' then + if txcnt = 0 then -- start delimiter + txcnt <= txcnt + 1; + tx_data_sig <= RS485_START_DELIM; + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + elsif txcnt = 1 then -- FTM address + txcnt <= txcnt + 1; + tx_data_sig <= FTM_ADDRESS; + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + elsif txcnt = 2 then -- board address + txcnt <= txcnt + 1; + tx_data_sig <= "00" & brd_add; + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + elsif txcnt = 3 then -- mirrored command + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + elsif txcnt = 4 then -- data: DAC A low + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + elsif txcnt = 5 then -- data: DAC A high + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + elsif txcnt = 6 then -- data: DAC B low + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + elsif txcnt = 7 then -- data: DAC B high + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + elsif txcnt = 8 then -- data: DAC C low + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + elsif txcnt = 9 then -- data: DAC C high + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + elsif txcnt = 10 then -- data: DAC D low + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + elsif txcnt = 11 then -- data: DAC D high + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + elsif txcnt = 12 then -- data: DAC E low + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + elsif txcnt = 13 then -- data: DAC E high + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + elsif txcnt < 15 then -- data: not used + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + elsif txcnt = 15 then -- check sum + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + else -- transmission finished + txcnt <= 0; + FTU_rs485_control_State <= RECEIVE; + end if; + else + tx_start_sig <= '0'; + FTU_rs485_control_State <= SET_DAC_TRANSMIT; + end if; + + when SET_ENABLE_TRANSMIT => + if tx_busy_sig = '0' then + if txcnt = 0 then -- start delimiter + txcnt <= txcnt + 1; + tx_data_sig <= RS485_START_DELIM; + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; + elsif txcnt = 1 then -- FTM address + txcnt <= txcnt + 1; + tx_data_sig <= FTM_ADDRESS; + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; + elsif txcnt = 2 then -- board address + txcnt <= txcnt + 1; + tx_data_sig <= "00" & brd_add; + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; + elsif txcnt = 3 then -- mirrored command + txcnt <= txcnt + 1; + tx_data_sig <= "00000011"; + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; + elsif txcnt = 4 then -- data: enable pattern A7-0 + txcnt <= txcnt + 1; + tx_data_sig <= enable_array_rs485_in(0)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; + elsif txcnt = 5 then -- data: enable pattern A8 + txcnt <= txcnt + 1; + tx_data_sig <= enable_array_rs485_in(0)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; + elsif txcnt = 6 then -- data: enable pattern B7-0 + txcnt <= txcnt + 1; + tx_data_sig <= enable_array_rs485_in(1)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; + elsif txcnt = 7 then -- data: enable pattern B8 + txcnt <= txcnt + 1; + tx_data_sig <= enable_array_rs485_in(1)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; + elsif txcnt = 8 then -- data: enable pattern C7-0 + txcnt <= txcnt + 1; + tx_data_sig <= enable_array_rs485_in(2)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; + elsif txcnt = 9 then -- data: enable pattern C8 + txcnt <= txcnt + 1; + tx_data_sig <= enable_array_rs485_in(2)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; + elsif txcnt = 10 then -- data: enable pattern D7-0 + txcnt <= txcnt + 1; + tx_data_sig <= enable_array_rs485_in(3)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; + elsif txcnt = 11 then -- data: enable pattern D8 + txcnt <= txcnt + 1; + tx_data_sig <= enable_array_rs485_in(3)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; + elsif txcnt < 15 then -- data: not used + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; + elsif txcnt = 15 then -- check sum + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; + else -- transmission finished + txcnt <= 0; + FTU_rs485_control_State <= RECEIVE; + end if; + else + tx_start_sig <= '0'; + FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; + end if; + + when SET_PRESCALING_TRANSMIT => + if tx_busy_sig = '0' then + if txcnt = 0 then -- start delimiter + txcnt <= txcnt + 1; + tx_data_sig <= RS485_START_DELIM; + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; + elsif txcnt = 1 then -- FTM address + txcnt <= txcnt + 1; + tx_data_sig <= FTM_ADDRESS; + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; + elsif txcnt = 2 then -- board address + txcnt <= txcnt + 1; + tx_data_sig <= "00" & brd_add; + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; + elsif txcnt = 3 then -- mirrored command + txcnt <= txcnt + 1; + tx_data_sig <= "00000110"; + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; + elsif txcnt = 4 then -- data: prescaling + txcnt <= txcnt + 1; + tx_data_sig <= prescaling_rs485_in; + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; + elsif txcnt < 15 then -- data: not used + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; + elsif txcnt = 15 then -- check sum + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! + tx_start_sig <= '1'; + FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; + else -- transmission finished + txcnt <= 0; + FTU_rs485_control_State <= RECEIVE; + end if; + else + tx_start_sig <= '0'; + FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; + end if; + + when READ_RATES_TRANSMIT => + if tx_busy_sig = '0' then + if txcnt = 0 then -- start delimiter + txcnt <= txcnt + 1; + tx_data_sig <= RS485_START_DELIM; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + elsif txcnt = 1 then -- FTM address + txcnt <= txcnt + 1; + tx_data_sig <= FTM_ADDRESS; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + elsif txcnt = 2 then -- board address + txcnt <= txcnt + 1; + tx_data_sig <= "00" & brd_add; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + elsif txcnt = 3 then -- mirrored command + txcnt <= txcnt + 1; + tx_data_sig <= "00000010"; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + elsif txcnt = 4 then -- data: counter A low + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),16)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + elsif txcnt = 5 then -- data: counter A high + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),16)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + elsif txcnt = 6 then -- data: counter B low + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),16)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + elsif txcnt = 7 then -- data: counter B high + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),16)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + elsif txcnt = 8 then -- data: counter C low + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),16)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + elsif txcnt = 9 then -- data: counter C high + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),16)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + elsif txcnt = 10 then -- data: counter D low + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),16)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + elsif txcnt = 11 then -- data: counter D high + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),16)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + elsif txcnt = 12 then -- data: trigger counter low + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),16)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + elsif txcnt = 13 then -- data: trigger counter high + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),16)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + elsif txcnt = 14 then -- data: overflow register + txcnt <= txcnt + 1; + tx_data_sig <= overflow_array_rs485_in; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + elsif txcnt = 15 then -- check sum + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + else -- transmission finished + txcnt <= 0; + FTU_rs485_control_State <= RECEIVE; + end if; + else + tx_start_sig <= '0'; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; + end if; + + when READ_DAC_TRANSMIT => + if tx_busy_sig = '0' then + if txcnt = 0 then -- start delimiter + txcnt <= txcnt + 1; + tx_data_sig <= RS485_START_DELIM; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + elsif txcnt = 1 then -- FTM address + txcnt <= txcnt + 1; + tx_data_sig <= FTM_ADDRESS; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + elsif txcnt = 2 then -- board address + txcnt <= txcnt + 1; + tx_data_sig <= "00" & brd_add; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + elsif txcnt = 3 then -- mirrored command + txcnt <= txcnt + 1; + tx_data_sig <= "00000001"; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + elsif txcnt = 4 then -- data: DAC A low + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + elsif txcnt = 5 then -- data: DAC A high + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + elsif txcnt = 6 then -- data: DAC B low + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + elsif txcnt = 7 then -- data: DAC B high + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + elsif txcnt = 8 then -- data: DAC C low + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + elsif txcnt = 9 then -- data: DAC C high + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + elsif txcnt = 10 then -- data: DAC D low + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + elsif txcnt = 11 then -- data: DAC D high + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + elsif txcnt = 12 then -- data: DAC E low + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + elsif txcnt = 13 then -- data: DAC E high + txcnt <= txcnt + 1; + tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + elsif txcnt < 15 then -- data: not used + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + elsif txcnt = 15 then -- check sum + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + else -- transmission finished + txcnt <= 0; + FTU_rs485_control_State <= RECEIVE; + end if; + else + tx_start_sig <= '0'; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; + end if; + + when READ_ENABLE_TRANSMIT => + if tx_busy_sig = '0' then + if txcnt = 0 then -- start delimiter + txcnt <= txcnt + 1; + tx_data_sig <= RS485_START_DELIM; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; + elsif txcnt = 1 then -- FTM address + txcnt <= txcnt + 1; + tx_data_sig <= FTM_ADDRESS; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; + elsif txcnt = 2 then -- board address + txcnt <= txcnt + 1; + tx_data_sig <= "00" & brd_add; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; + elsif txcnt = 3 then -- mirrored command + txcnt <= txcnt + 1; + tx_data_sig <= "00000100"; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; + elsif txcnt = 4 then -- data: enable pattern A7-0 + txcnt <= txcnt + 1; + tx_data_sig <= enable_array_rs485_in(0)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; + elsif txcnt = 5 then -- data: enable pattern A8 + txcnt <= txcnt + 1; + tx_data_sig <= enable_array_rs485_in(0)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; + elsif txcnt = 6 then -- data: enable pattern B7-0 + txcnt <= txcnt + 1; + tx_data_sig <= enable_array_rs485_in(1)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; + elsif txcnt = 7 then -- data: enable pattern B8 + txcnt <= txcnt + 1; + tx_data_sig <= enable_array_rs485_in(1)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; + elsif txcnt = 8 then -- data: enable pattern C7-0 + txcnt <= txcnt + 1; + tx_data_sig <= enable_array_rs485_in(2)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; + elsif txcnt = 9 then -- data: enable pattern C8 + txcnt <= txcnt + 1; + tx_data_sig <= enable_array_rs485_in(2)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; + elsif txcnt = 10 then -- data: enable pattern D7-0 + txcnt <= txcnt + 1; + tx_data_sig <= enable_array_rs485_in(3)(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; + elsif txcnt = 11 then -- data: enable pattern D8 + txcnt <= txcnt + 1; + tx_data_sig <= enable_array_rs485_in(3)(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; + elsif txcnt < 15 then -- data: not used + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; + elsif txcnt = 15 then -- check sum + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; + else -- transmission finished + txcnt <= 0; + FTU_rs485_control_State <= RECEIVE; + end if; + else + tx_start_sig <= '0'; + FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; + end if; + + when READ_PRESCALING_TRANSMIT => + if tx_busy_sig = '0' then + if txcnt = 0 then -- start delimiter + txcnt <= txcnt + 1; + tx_data_sig <= RS485_START_DELIM; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; + elsif txcnt = 1 then -- FTM address + txcnt <= txcnt + 1; + tx_data_sig <= FTM_ADDRESS; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; + elsif txcnt = 2 then -- board address + txcnt <= txcnt + 1; + tx_data_sig <= "00" & brd_add; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; + elsif txcnt = 3 then -- mirrored command + txcnt <= txcnt + 1; + tx_data_sig <= "00000111"; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; + elsif txcnt = 4 then -- data: prescaling + txcnt <= txcnt + 1; + tx_data_sig <= prescaling_rs485_in; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; + elsif txcnt = 5 then -- data: overflow register + txcnt <= txcnt + 1; + tx_data_sig <= overflow_array_rs485_in; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; + elsif txcnt < 15 then -- data: not used + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; + elsif txcnt = 15 then -- check sum + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! + tx_start_sig <= '1'; + FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; + else -- transmission finished + txcnt <= 0; + FTU_rs485_control_State <= RECEIVE; + end if; + else + tx_start_sig <= '0'; + FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; + end if; + + end case; + end if; + end process FTU_rs485_control_FSM; + +end Behavioral; + Index: /firmware/FTU/rs485/FTU_rs485_interface.vhd =================================================================== --- /firmware/FTU/rs485/FTU_rs485_interface.vhd (revision 9928) +++ /firmware/FTU/rs485/FTU_rs485_interface.vhd (revision 9928) @@ -0,0 +1,126 @@ +-- +-- VHDL Architecture FACT_FAD_lib.rs485_interface.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 13:24:23 08.06.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- +-- modified for FTU design by Q. Weitzel, 30 July 2010 +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +library ftu_definitions; +USE ftu_definitions.ftu_array_types.all; +USE ftu_definitions.ftu_constants.all; + +ENTITY FTU_rs485_interface IS + GENERIC( + CLOCK_FREQUENCY : integer := INT_CLK_FREQUENCY; + BAUD_RATE : integer := RS485_BAUD_RATE + ); + PORT( + clk : IN std_logic; + -- RS485 + rx_d : IN std_logic; + rx_en : OUT std_logic; + tx_d : OUT std_logic; + tx_en : OUT std_logic; + -- FPGA + rx_data : OUT std_logic_vector (7 DOWNTO 0); + rx_busy : OUT std_logic := '0'; + rx_valid : OUT std_logic := '0'; + tx_data : IN std_logic_vector (7 DOWNTO 0); + tx_busy : OUT std_logic := '0'; + tx_start : IN std_logic + ); + +END FTU_rs485_interface; + +ARCHITECTURE beha OF FTU_rs485_interface IS + + signal flow_ctrl : std_logic := '0'; -- '0' -> RX enable, '1' -> TX enable + + --transmit + signal tx_start_f : std_logic := '0'; + signal tx_sr : std_logic_vector(10 downto 0) := (others => '1'); -- start bit, 8 data bits, 2 stop bits + signal tx_bitcnt : integer range 0 to 11 := 11; + signal tx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1); + + --receive + signal rx_dsr : std_logic_vector(3 downto 0) := (others => '1'); + signal rx_sr : std_logic_vector(7 downto 0) := (others => '0'); + signal rx_bitcnt : integer range 0 to 11 := 11; + signal rx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1); + +BEGIN + + -- Senden + tx_data_proc: process(clk) + begin + if rising_edge(clk) then + tx_start_f <= tx_start; + if (tx_start = '1' or tx_bitcnt < 11) then + flow_ctrl <= '1'; + else + flow_ctrl <= '0'; + end if; + if (tx_start = '1' and tx_start_f = '0') then -- steigende Flanke, los gehts + tx_cnt <= 0; -- Zaehler initialisieren + tx_bitcnt <= 0; + tx_sr <= "11" & tx_data & '0'; -- 2 x Stopbit, 8 Datenbits, Startbit, rechts gehts los + else + if (tx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then + tx_cnt <= tx_cnt + 1; + else -- naechstes Bit ausgeben + if (tx_bitcnt < 11) then + tx_cnt <= 0; + tx_bitcnt <= tx_bitcnt + 1; + tx_sr <= '1' & tx_sr(tx_sr'left downto 1); + end if; + end if; + end if; + end if; + end process; + + tx_en <= flow_ctrl; + tx_d <= tx_sr(0); -- LSB first + tx_busy <= '1' when (tx_start = '1' or tx_bitcnt < 11) else '0'; + + -- Empfangen + rx_data_proc: process(clk) + begin + if rising_edge(clk) then + rx_dsr <= rx_dsr(rx_dsr'left - 1 downto 0) & rx_d; + if (rx_bitcnt < 11) then -- Empfang laeuft + if (rx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then + rx_cnt <= rx_cnt + 1; + else + rx_cnt <= 0; + rx_bitcnt <= rx_bitcnt + 1; + if (rx_bitcnt < 9) then + rx_sr <= rx_dsr(rx_dsr'left - 1) & rx_sr(rx_sr'left downto 1); -- rechts schieben, weil LSB first + else + rx_valid <= '1'; + end if; + end if; + else + if (rx_dsr(3 downto 2) = "10") then -- warten auf Start bit + rx_valid <= '0'; + rx_cnt <= ((CLOCK_FREQUENCY / BAUD_RATE) - 1) / 2; + rx_bitcnt <= 0; + end if; + end if; + end if; + end process; + + rx_en <= flow_ctrl; + rx_data <= rx_sr; + rx_busy <= '1' when (rx_bitcnt < 11) else '0'; + +END ARCHITECTURE beha; Index: /firmware/FTU/rs485/FTU_rs485_interpreter.vhd =================================================================== --- /firmware/FTU/rs485/FTU_rs485_interpreter.vhd (revision 9928) +++ /firmware/FTU/rs485/FTU_rs485_interpreter.vhd (revision 9928) @@ -0,0 +1,199 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Q. Weitzel, P. Vogler +-- +-- Create Date: 09/13/2010 +-- Design Name: +-- Module Name: FTU_rs485_interpreter - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: command interpreter of FTU RS485 module +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library ftu_definitions; +USE ftu_definitions.ftu_array_types.all; +USE ftu_definitions.ftu_constants.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTU_rs485_interpreter is + port( + clk : IN std_logic; + data_block : IN std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0); + block_valid : IN std_logic; + brd_add : IN std_logic_vector(5 downto 0); + int_new_DACs : OUT std_logic := '0'; + int_new_enables : OUT std_logic := '0'; + int_new_prescaling : OUT std_logic := '0'; + int_read_rates : OUT std_logic := '0'; + int_read_DACs : OUT std_logic := '0'; + int_read_enables : OUT std_logic := '0'; + int_read_prescaling : OUT std_logic := '0'; + dac_array_rs485_out : OUT dac_array_type; + enable_array_rs485_out : OUT enable_array_type; + prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0) + ); +end FTU_rs485_interpreter; + +architecture Behavioral of FTU_rs485_interpreter is + + signal block_valid_sr : std_logic_vector(3 downto 0) := (others => '0'); + + signal dac_array_rs485_out_sig : dac_array_type := DEFAULT_DAC; + signal enable_array_rs485_out_sig : enable_array_type := DEFAULT_ENABLE; + signal prescaling_rs485_out_sig : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(DEFAULT_PRESCALING,8); + + type FTU_rs485_interpreter_StateType is (WAIT_FOR_DATA, CHECK_HEADER, DECODE); + signal FTU_rs485_interpreter_State : FTU_rs485_interpreter_StateType; + +begin + + FTU_rs485_interpreter_FSM: process (clk) + begin + if Rising_edge(clk) then + case FTU_rs485_interpreter_State is + + when WAIT_FOR_DATA => -- default state, waiting for valid 16-byte block + block_valid_sr <= block_valid_sr(2 downto 0) & block_valid; + int_new_DACs <= '0'; + int_new_enables <= '0'; + int_new_prescaling <= '0'; + int_read_rates <= '0'; + int_read_DACs <= '0'; + int_read_enables <= '0'; + int_read_prescaling <= '0'; + if (block_valid_sr(3 downto 2) = "01") then -- rising edge of valid signal + FTU_rs485_interpreter_State <= CHECK_HEADER; + else + FTU_rs485_interpreter_State <= WAIT_FOR_DATA; + end if; + + when CHECK_HEADER => -- check start delimiter and addresses + int_new_DACs <= '0'; + int_new_enables <= '0'; + int_new_prescaling <= '0'; + int_read_rates <= '0'; + int_read_DACs <= '0'; + int_read_enables <= '0'; + int_read_prescaling <= '0'; + if (data_block(7 downto 0) = RS485_START_DELIM) and + (data_block(15 downto 8) = ("00" & brd_add)) and + (data_block(23 downto 16) = FTM_ADDRESS) then + FTU_rs485_interpreter_State <= DECODE; + else + FTU_rs485_interpreter_State <= WAIT_FOR_DATA; + end if; + + when DECODE => -- decode instruction + if(data_block(31 downto 24) = "00000000") then + int_new_DACs <= '1'; + int_new_enables <= '0'; + int_new_prescaling <= '0'; + int_read_rates <= '0'; + int_read_DACs <= '0'; + int_read_enables <= '0'; + int_read_prescaling <= '0'; + dac_array_rs485_out_sig <= (conv_integer(unsigned(data_block(47 downto 32))), + conv_integer(unsigned(data_block(63 downto 48))), + conv_integer(unsigned(data_block(79 downto 64))), + conv_integer(unsigned(data_block(95 downto 80))), + 0,0,0, + conv_integer(unsigned(data_block(111 downto 96))) + ); + FTU_rs485_interpreter_State <= WAIT_FOR_DATA; + elsif (data_block(31 downto 24) = "00000001") then + int_new_DACs <= '0'; + int_new_enables <= '0'; + int_new_prescaling <= '0'; + int_read_rates <= '0'; + int_read_DACs <= '1'; + int_read_enables <= '0'; + int_read_prescaling <= '0'; + FTU_rs485_interpreter_State <= WAIT_FOR_DATA; + elsif (data_block(31 downto 24) = "00000010") then + int_new_DACs <= '0'; + int_new_enables <= '0'; + int_new_prescaling <= '0'; + int_read_rates <= '1'; + int_read_DACs <= '0'; + int_read_enables <= '0'; + int_read_prescaling <= '0'; + FTU_rs485_interpreter_State <= WAIT_FOR_DATA; + elsif (data_block(31 downto 24) = "00000011") then + int_new_DACs <= '0'; + int_new_enables <= '1'; + int_new_prescaling <= '0'; + int_read_rates <= '0'; + int_read_DACs <= '0'; + int_read_enables <= '0'; + int_read_prescaling <= '0'; + enable_array_rs485_out_sig <= (data_block(47 downto 32), + data_block(63 downto 48), + data_block(79 downto 64), + data_block(95 downto 80) + ); + FTU_rs485_interpreter_State <= WAIT_FOR_DATA; + elsif (data_block(31 downto 24) = "00000100") then + int_new_DACs <= '0'; + int_new_enables <= '0'; + int_new_prescaling <= '0'; + int_read_rates <= '0'; + int_read_DACs <= '0'; + int_read_enables <= '1'; + int_read_prescaling <= '0'; + FTU_rs485_interpreter_State <= WAIT_FOR_DATA; + elsif (data_block(31 downto 24) = "00000110") then + int_new_DACs <= '0'; + int_new_enables <= '0'; + int_new_prescaling <= '1'; + int_read_rates <= '0'; + int_read_DACs <= '0'; + int_read_enables <= '0'; + int_read_prescaling <= '0'; + prescaling_rs485_out_sig <= data_block(39 downto 32); + FTU_rs485_interpreter_State <= WAIT_FOR_DATA; + elsif (data_block(31 downto 24) = "00000111") then + int_new_DACs <= '0'; + int_new_enables <= '0'; + int_new_prescaling <= '0'; + int_read_rates <= '0'; + int_read_DACs <= '0'; + int_read_enables <= '0'; + int_read_prescaling <= '1'; + FTU_rs485_interpreter_State <= WAIT_FOR_DATA; + else + int_new_DACs <= '0'; + int_new_enables <= '0'; + int_new_prescaling <= '0'; + int_read_rates <= '0'; + int_read_DACs <= '0'; + int_read_enables <= '0'; + int_read_prescaling <= '0'; + FTU_rs485_interpreter_State <= WAIT_FOR_DATA; + end if; + + end case; + end if; + end process FTU_rs485_interpreter_FSM; + + dac_array_rs485_out <= dac_array_rs485_out_sig; + enable_array_rs485_out <= enable_array_rs485_out_sig; + prescaling_rs485_out <= prescaling_rs485_out_sig; + +end Behavioral; Index: /firmware/FTU/rs485/FTU_rs485_receiver.vhd =================================================================== --- /firmware/FTU/rs485/FTU_rs485_receiver.vhd (revision 9928) +++ /firmware/FTU/rs485/FTU_rs485_receiver.vhd (revision 9928) @@ -0,0 +1,60 @@ +-- +-- VHDL Architecture FACT_FAD_lib.rs485_receiver.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 12:16:57 11.06.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10) +-- +-- +-- modified for FTU design by Q. Weitzel, 13 September 2010 +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +library ftu_definitions; +USE ftu_definitions.ftu_constants.all; + +ENTITY FTU_rs485_receiver IS + generic( + RX_BYTES : integer := RS485_BLOCK_WIDTH / 8; -- no. of bytes to receive + RX_WIDTH : integer := RS485_BLOCK_WIDTH + ); + port( + rec_clk : in std_logic; + --rx_busy : in std_logic; + rec_din : in std_logic_vector(7 downto 0); + rec_den : in std_logic; + rec_dout : out std_logic_vector(RX_WIDTH - 1 downto 0) := (others => '0'); + rec_valid : out std_logic := '0' + ); +END ENTITY FTU_rs485_receiver; + +ARCHITECTURE beha OF FTU_rs485_receiver IS + + signal rxcnt : integer range 0 to RX_BYTES := 0; + signal rxsr : std_logic_vector(3 downto 0) := (others => '0'); + +BEGIN + + rx_data_proc: process (rec_clk) + begin + if rising_edge(rec_clk) then + rxsr <= rxsr(2 downto 0) & rec_den; + if (rxsr(3 downto 2) = "01") then -- identify rising edge + rec_dout((rxcnt*rec_din'length + rec_din'length - 1) downto (rxcnt*rec_din'length)) <= rec_din; + rxcnt <= rxcnt + 1; + if (rxcnt < RX_BYTES - 1) then + rec_valid <= '0'; + else + rxcnt <= 0; + rec_valid <= '1'; + end if; + end if; + end if; + end process rx_data_proc; + +END ARCHITECTURE beha;