Index: /firmware/FTU/FTU_control.vhd =================================================================== --- /firmware/FTU/FTU_control.vhd (revision 9938) +++ /firmware/FTU/FTU_control.vhd (revision 9939) @@ -35,27 +35,43 @@ entity FTU_control is port( - clk_50MHz : IN std_logic; - clk_ready : IN std_logic; - config_started : IN std_logic; - config_ready : IN std_logic; - ram_doa : IN STD_LOGIC_VECTOR(7 downto 0); - ram_dob : IN STD_LOGIC_VECTOR(15 downto 0); - rate_array : IN rate_array_type; - overflow_array : in STD_LOGIC_VECTOR(7 downto 0); - new_rates : IN std_logic; - reset : OUT std_logic; - config_start : OUT std_logic; - ram_ena : OUT std_logic; - ram_enb : OUT std_logic; - ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0); - ram_web : OUT STD_LOGIC_VECTOR(0 downto 0); - ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0); - ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0); - ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0); - ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0); - dac_array : OUT dac_array_type; - enable_array : OUT enable_array_type; - cntr_reset : OUT STD_LOGIC; - prescaling : OUT STD_LOGIC_VECTOR(7 downto 0) + clk_50MHz : IN std_logic; + clk_ready : IN std_logic; -- from DCM + config_started : IN std_logic; -- from DAC/SPI + config_ready : IN std_logic; -- from DAC/SPI + ram_doa : IN STD_LOGIC_VECTOR(7 downto 0); + ram_dob : IN STD_LOGIC_VECTOR(15 downto 0); + rate_array : IN rate_array_type; -- from counters + overflow_array : IN STD_LOGIC_VECTOR(7 downto 0); -- from counters + new_rates : IN std_logic; -- from counters + new_DACs : IN std_logic; -- from RS485 module + new_enables : IN std_logic; -- from RS485 module + new_prescaling : IN std_logic; -- from RS485 module + read_rates : IN std_logic; -- from RS485 module + read_DACs : IN std_logic; -- from RS485 module + read_enables : IN std_logic; -- from RS485 module + read_prescaling : IN std_logic; -- from RS485 module + dac_array_rs485_out : IN dac_array_type; -- from RS485 module + enable_array_rs485_out : IN enable_array_type; -- from RS485 module + prescaling_rs485_out : IN STD_LOGIC_VECTOR(7 downto 0); -- from RS485 module + reset : OUT std_logic; + config_start : OUT std_logic; + ram_ena : OUT std_logic; + ram_enb : OUT std_logic; + ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0); + ram_web : OUT STD_LOGIC_VECTOR(0 downto 0); + ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0); + ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0); + ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0); + ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0); + rate_array_rs485 : OUT rate_array_type := (0,0,0,0,0); -- to RS485 module + overflow_array_rs485_in : OUT STD_LOGIC_VECTOR(7 downto 0) := "00000000"; -- to RS485 module + rates_ready : OUT std_logic := '0'; -- to RS485 module + DACs_ready : OUT std_logic := '0'; -- to RS485 module + enables_ready : OUT std_logic := '0'; -- to RS485 module + prescaling_ready : OUT std_logic := '0'; -- to RS485 module + dac_array : OUT dac_array_type; + enable_array : OUT enable_array_type; + cntr_reset : OUT STD_LOGIC; + prescaling : OUT STD_LOGIC_VECTOR(7 downto 0) ); end FTU_control; @@ -90,5 +106,4 @@ --counter to loop through RAM signal ram_ada_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0; - signal ram_adb_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_B := 0; signal ram_dac_cntr : INTEGER range 0 to (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2) := 0; signal ram_enable_cntr : INTEGER range 0 to (NO_OF_ENABLE + 1) := 0; @@ -104,5 +119,8 @@ signal new_prescaling_in_RAM : STD_LOGIC := '0'; - type FTU_control_StateType is (IDLE, INIT, RUNNING, CONFIG_ENABLE, CONFIG_DAC, CONFIG_COUNTER, WRITE_RATES, RESET_ALL); + type FTU_control_StateType is (IDLE, INIT, RUNNING, + CONFIG_ENABLE, CONFIG_DAC, CONFIG_COUNTER, + WRITE_RATES, WRITE_DAC, WRITE_ENABLE, WRITE_PRESCALING, + READOUT_RATES, READOUT_DAC, READOUT_ENABLE, READOUT_PRESCALING); signal FTU_control_State : FTU_control_StateType; @@ -115,10 +133,11 @@ begin + reset_sig <= '0'; + if Rising_edge(clk_50MHz) then case FTU_control_State is - + when IDLE => -- wait for DCMs to lock - reset_sig <= '0'; config_start_sig <= '0'; ram_ena_sig <= '0'; @@ -126,8 +145,9 @@ if (clk_ready = '1') then FTU_control_State <= INIT; + else + FTU_control_State <= IDLE; end if; when INIT => -- load default config data to RAM, see also ftu_definitions.vhd for more info - reset_sig <= '0'; new_rates_busy <= '1'; config_start_sig <= '0'; @@ -189,9 +209,8 @@ when RUNNING => -- count triggers and react to commands from FTM cntr_reset_sig <= '0'; - reset_sig <= '0'; config_start_sig <= '0'; - if (new_rates_sig = '1') then + if (new_rates_sig = '1') then -- counters have finished a period FTU_control_State <= WRITE_RATES; - else + else -- update FTU settings if necessary if (new_DACs_in_RAM = '1') then ram_enb_sig <= '1'; @@ -206,6 +225,34 @@ ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A); FTU_control_State <= CONFIG_COUNTER; - else - FTU_control_State <= RUNNING; + else -- nothing to be updated, check new commands from RS485 + if (new_DACs = '1') then + FTU_control_State <= WRITE_DAC; + elsif (new_DACs = '0' and new_enables = '1') then + FTU_control_State <= WRITE_ENABLE; + elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '1') then + FTU_control_State <= WRITE_PRESCALING; + elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and + read_rates = '1') then + ram_enb_sig <= '1'; + ram_adb_sig <= conv_std_logic_vector(NO_OF_ENABLE, RAM_ADDR_WIDTH_B); + FTU_control_State <= READOUT_RATES; + elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and + read_rates = '0' and read_DACs = '1') then + ram_enb_sig <= '1'; + ram_adb_sig <= conv_std_logic_vector(NO_OF_ENABLE + NO_OF_COUNTER, RAM_ADDR_WIDTH_B); + FTU_control_State <= READOUT_DAC; + elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and + read_rates = '0' and read_DACs = '0' and read_enables = '1') then + ram_enb_sig <= '1'; + ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B); + FTU_control_State <= READOUT_ENABLE; + elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and + read_rates = '0' and read_DACs = '0' and read_enables = '0' and read_prescaling = '1') then + ram_ena_sig <= '1'; + ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A); + FTU_control_State <= READOUT_PRESCALING; + else + FTU_control_State <= RUNNING; --no commands from RS485 -> stay running + end if; end if; end if; @@ -219,4 +266,5 @@ prescaling_sig <= ram_doa; FTU_control_State <= CONFIG_COUNTER; + prescaling_ready <= '1'; else cntr_reset_sig <= '1'; @@ -226,4 +274,5 @@ ram_ena_sig <= '0'; new_rates_busy <= '0'; + prescaling_ready <= '0'; FTU_control_State <= RUNNING; end if; @@ -238,4 +287,5 @@ ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B); enable_array_sig(ram_enable_cntr - 1) <= ram_dob; + enables_ready <= '1'; FTU_control_State <= CONFIG_ENABLE; else @@ -246,4 +296,5 @@ cntr_reset_sig <= '1'; new_rates_busy <= '0'; + enables_ready <= '0'; FTU_control_State <= RUNNING; end if; @@ -257,14 +308,16 @@ ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); elsif (ram_dac_cntr > 0 and ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then - dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob)); + dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0))); ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); FTU_control_State <= CONFIG_DAC; elsif (ram_dac_cntr > 0 and ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED + 1)) then - dac_array_sig(ram_dac_cntr - 1 + NO_OF_DAC_NOT_USED) <= conv_integer(unsigned(ram_dob)); + dac_array_sig(ram_dac_cntr - 1 + NO_OF_DAC_NOT_USED) <= conv_integer(unsigned(ram_dob(11 downto 0))); ram_adb_sig <= (others => '0'); FTU_control_State <= CONFIG_DAC; + DACs_ready <= '1'; else ram_adb_sig <= (others => '0'); config_start_sig <= '1'; + DACs_ready <= '0'; FTU_control_State <= CONFIG_DAC; end if; @@ -286,5 +339,5 @@ when WRITE_RATES => -- write trigger/patch rates to RAM B and overflow register to RAM A - new_rates_busy <= '1'; + new_rates_busy <= '1'; ram_counter_cntr <= ram_counter_cntr + 1; if (ram_counter_cntr < NO_OF_COUNTER) then @@ -306,14 +359,181 @@ else ram_ena_sig <= '0'; - ram_wea_sig <= "0"; - ram_counter_cntr <= 0; + ram_wea_sig <= "0"; + ram_counter_cntr <= 0; new_rates_busy <= '0'; FTU_control_State <= RUNNING; end if; - - when RESET_ALL => -- reset/clear and start from scratch - reset_sig <= '1'; - config_start_sig <= '0'; - FTU_control_State <= IDLE; + + when WRITE_DAC => -- write new DAC values from RS485 to RAM + ram_dac_cntr <= ram_dac_cntr + 1; + if (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)) then + ram_enb_sig <= '1'; + ram_web_sig <= "1"; + ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr), RAM_ADDR_WIDTH_B); + ram_dib_sig <= conv_std_logic_vector(dac_array_rs485_out(ram_dac_cntr), 16); + FTU_control_State <= WRITE_DAC; + elsif (ram_dac_cntr = (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)) then + ram_enb_sig <= '1'; + ram_web_sig <= "1"; + ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr), RAM_ADDR_WIDTH_B); + ram_dib_sig <= conv_std_logic_vector(dac_array_rs485_out(ram_dac_cntr + NO_OF_DAC_NOT_USED), 16); + FTU_control_State <= WRITE_DAC; + else + ram_enb_sig <= '0'; + ram_web_sig <= "0"; + new_DACs_in_RAM <= '1'; + ram_dib_sig <= (others => '0'); + ram_adb_sig <= (others => '0'); + ram_dac_cntr <= 0; + FTU_control_State <= RUNNING; + end if; + + when WRITE_ENABLE => -- write new enable patterns from RS485 to RAM + ram_enable_cntr <= ram_enable_cntr + 1; + if (ram_enable_cntr < NO_OF_ENABLE) then + ram_enb_sig <= '1'; + ram_web_sig <= "1"; + ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr, RAM_ADDR_WIDTH_B); + ram_dib_sig <= enable_array_rs485_out(ram_enable_cntr); + else + ram_enb_sig <= '0'; + ram_web_sig <= "0"; + new_enables_in_RAM <= '1'; + ram_dib_sig <= (others => '0'); + ram_adb_sig <= (others => '0'); + ram_enable_cntr <= 0; + FTU_control_State <= RUNNING; + end if; + + when WRITE_PRESCALING => -- write new prescaling from RS485 to RAM + wait_cntr <= wait_cntr + 1; + if (wait_cntr = 0) then + ram_ena_sig <= '1'; + ram_wea_sig <= "1"; + ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A); + ram_dia_sig <= prescaling_rs485_out; + else + ram_ena_sig <= '0'; + ram_wea_sig <= "0"; + new_prescaling_in_RAM <= '1'; + ram_dia_sig <= (others => '0'); + ram_ada_sig <= (others => '0'); + wait_cntr <= 0; + FTU_control_State <= RUNNING; + end if; + + when READOUT_RATES => -- read most recent rate values from RAM and send them to RS485 module + ram_counter_cntr <= ram_counter_cntr + 1; + if (ram_counter_cntr = 0) then + ram_enb_sig <= '1'; + ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B); + FTU_control_State <= READOUT_RATES; + elsif (ram_counter_cntr < NO_OF_COUNTER) then + ram_ena_sig <= '1'; + ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A); + ram_enb_sig <= '1'; + ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B); + rate_array_rs485(ram_counter_cntr - 1) <= conv_integer(unsigned(ram_dob)); + FTU_control_State <= READOUT_RATES; + elsif (ram_counter_cntr = NO_Of_COUNTER) then + ram_enb_sig <= '0'; + ram_adb_sig <= (others => '0'); + rate_array_rs485(ram_counter_cntr - 1) <= conv_integer(unsigned(ram_dob)); + ram_ena_sig <= '1'; + ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A); + FTU_control_State <= READOUT_RATES; + elsif (ram_counter_cntr = NO_Of_COUNTER + 1) then + ram_enb_sig <= '0'; + ram_adb_sig <= (others => '0'); + ram_ena_sig <= '0'; + ram_ada_sig <= (others => '0'); + overflow_array_rs485_in <= ram_doa; + rates_ready <= '1'; + FTU_control_State <= READOUT_RATES; + else + ram_enb_sig <= '0'; + ram_adb_sig <= (others => '0'); + ram_ena_sig <= '0'; + ram_ada_sig <= (others => '0'); + ram_counter_cntr <= 0; + rates_ready <= '0'; + FTU_control_State <= RUNNING; + end if; + + when READOUT_DAC => -- read most recent DAC values from RAM and send them to RS485 module + ram_dac_cntr <= ram_dac_cntr + 1; + if (ram_dac_cntr = 0) then + ram_enb_sig <= '1'; + ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); + FTU_control_State <= READOUT_DAC; + elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then + ram_enb_sig <= '1'; + ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); + dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0))); + FTU_control_State <= READOUT_DAC; + elsif (ram_dac_cntr = (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then + ram_enb_sig <= '0'; + ram_adb_sig <= (others => '0'); + dac_array_sig(ram_dac_cntr + NO_OF_DAC_NOT_USED - 1) <= conv_integer(unsigned(ram_dob(11 downto 0))); + DACs_ready <= '1'; + FTU_control_State <= READOUT_DAC; + else + ram_enb_sig <= '0'; + ram_adb_sig <= (others => '0'); + DACs_ready <= '0'; + ram_dac_cntr <= 0; + FTU_control_State <= RUNNING; + end if; + + when READOUT_ENABLE => -- read most recent enable patterns from RAM and send them to RS485 module + ram_enable_cntr <= ram_enable_cntr + 1; + if (ram_enable_cntr = 0) then + ram_enb_sig <= '1'; + ram_adb_sig <= conv_std_logic_vector((ram_enable_cntr + 1), RAM_ADDR_WIDTH_B); + FTU_control_State <= READOUT_ENABLE; + elsif (ram_enable_cntr < NO_OF_ENABLE) then + ram_enb_sig <= '1'; + ram_adb_sig <= conv_std_logic_vector((ram_enable_cntr + 1), RAM_ADDR_WIDTH_B); + enable_array_sig(ram_enable_cntr - 1) <= ram_dob; + FTU_control_State <= READOUT_ENABLE; + elsif (ram_enable_cntr = NO_OF_ENABLE) then + ram_enb_sig <= '0'; + ram_adb_sig <= (others => '0'); + enable_array_sig(ram_enable_cntr - 1) <= ram_dob; + enables_ready <= '1'; + FTU_control_State <= READOUT_ENABLE; + else + ram_enb_sig <= '0'; + ram_adb_sig <= (others => '0'); + enables_ready <= '0'; + ram_enable_cntr <= 0; + FTU_control_State <= RUNNING; + end if; + + when READOUT_PRESCALING => -- read most recent prescaling value from RAM and send it to RS485 module + wait_cntr <= wait_cntr + 1; + if (wait_cntr = 0) then + ram_ena_sig <= '1'; + ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1, RAM_ADDR_WIDTH_A); + FTU_control_State <= READOUT_PRESCALING; + elsif (wait_cntr = 1) then + ram_ena_sig <= '1'; + ram_ada_sig <= (others => '0'); + prescaling_sig <= ram_doa; + FTU_control_State <= READOUT_PRESCALING; + elsif (wait_cntr = 2) then + ram_ena_sig <= '0'; + ram_ada_sig <= (others => '0'); + overflow_array_rs485_in <= ram_doa; + prescaling_ready <= '1'; + FTU_control_State <= READOUT_PRESCALING; + else + ram_ena_sig <= '0'; + ram_ada_sig <= (others => '0'); + prescaling_ready <= '0'; + wait_cntr <= 0; + FTU_control_State <= RUNNING; + end if; + end case; end if; @@ -330,15 +550,14 @@ reset <= reset_sig; - - config_start <= config_start_sig; - dac_array <= dac_array_sig; + + config_start <= config_start_sig; + dac_array <= dac_array_sig; enable_array <= enable_array_sig; - + prescaling <= prescaling_sig; + rate_array_sig <= rate_array; - - cntr_reset <= cntr_reset_sig; - prescaling <= prescaling_sig; - + cntr_reset <= cntr_reset_sig; + ram_ena <= ram_ena_sig; ram_enb <= ram_enb_sig; Index: /firmware/FTU/FTU_top.vhd =================================================================== --- /firmware/FTU/FTU_top.vhd (revision 9938) +++ /firmware/FTU/FTU_top.vhd (revision 9939) @@ -80,5 +80,4 @@ signal reset_sig : STD_LOGIC; -- initialized in FTU_control - signal dac_clr_sig : STD_LOGIC := '1'; -- not used in hardware, initialize to 1 at power up --single-ended trigger signals for rate counter @@ -124,4 +123,24 @@ signal ram_dob_sig : STD_LOGIC_VECTOR(15 downto 0); + --signals from RS485 module, all initialized in FTU_rs485_control (or deeper) + signal new_DACs_sig : std_logic; + signal new_enables_sig : std_logic; + signal new_prescaling_sig : std_logic; + signal read_rates_sig : std_logic; + signal read_DACs_sig : std_logic; + signal read_enables_sig : std_logic; + signal read_prescaling_sig : std_logic; + signal dac_array_rs485_out_sig : dac_array_type; + signal enable_array_rs485_out_sig : enable_array_type; + signal prescaling_rs485_out_sig : STD_LOGIC_VECTOR(7 downto 0); + + --signals to RS485 module, all initialized in FTU_control + signal rates_ready_sig : std_logic; + signal DACs_ready_sig : std_logic; + signal enables_ready_sig : std_logic; + signal prescaling_ready_sig : std_logic; + signal rate_array_rs485_sig : rate_array_type; + signal overflow_array_rs485_in_sig : STD_LOGIC_VECTOR(7 downto 0); + component FTU_clk_gen port( @@ -145,29 +164,45 @@ end component; - component FTU_control - port( - clk_50MHz : IN std_logic; - clk_ready : IN std_logic; - config_started : IN std_logic; - config_ready : IN std_logic; - ram_doa : IN STD_LOGIC_VECTOR(7 downto 0); - ram_dob : IN STD_LOGIC_VECTOR(15 downto 0); - rate_array : IN rate_array_type; - overflow_array : in STD_LOGIC_VECTOR(7 downto 0); - new_rates : IN std_logic; - reset : OUT std_logic; - config_start : OUT std_logic; - ram_ena : OUT std_logic; - ram_enb : OUT std_logic; - ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0); - ram_web : OUT STD_LOGIC_VECTOR(0 downto 0); - ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0); - ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0); - ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0); - ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0); - dac_array : OUT dac_array_type; - enable_array : OUT enable_array_type; - cntr_reset : OUT STD_LOGIC; - prescaling : OUT STD_LOGIC_VECTOR(7 downto 0) + component FTU_control -- comments: see entity file + port( + clk_50MHz : IN std_logic; + clk_ready : IN std_logic; + config_started : IN std_logic; + config_ready : IN std_logic; + ram_doa : IN STD_LOGIC_VECTOR(7 downto 0); + ram_dob : IN STD_LOGIC_VECTOR(15 downto 0); + rate_array : IN rate_array_type; + overflow_array : in STD_LOGIC_VECTOR(7 downto 0); + new_rates : IN std_logic; + new_DACs : IN std_logic; + new_enables : IN std_logic; + new_prescaling : IN std_logic; + read_rates : IN std_logic; + read_DACs : IN std_logic; + read_enables : IN std_logic; + read_prescaling : IN std_logic; + dac_array_rs485_out : IN dac_array_type; + enable_array_rs485_out : IN enable_array_type; + prescaling_rs485_out : IN STD_LOGIC_VECTOR(7 downto 0); + reset : OUT std_logic; + config_start : OUT std_logic; + ram_ena : OUT std_logic; + ram_enb : OUT std_logic; + ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0); + ram_web : OUT STD_LOGIC_VECTOR(0 downto 0); + ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0); + ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0); + ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0); + ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0); + rate_array_rs485 : OUT rate_array_type; + overflow_array_rs485_in : OUT STD_LOGIC_VECTOR(7 downto 0); + rates_ready : OUT std_logic; + DACs_ready : OUT std_logic; + enables_ready : OUT std_logic; + prescaling_ready : OUT std_logic; + dac_array : OUT dac_array_type; + enable_array : OUT enable_array_type; + cntr_reset : OUT STD_LOGIC; + prescaling : OUT STD_LOGIC_VECTOR(7 downto 0) ); end component; @@ -186,5 +221,5 @@ end component; - component FTU_rs485_control + component FTU_rs485_control -- comments: see entity file port( main_clk : IN std_logic; @@ -210,5 +245,4 @@ read_enables : OUT std_logic; read_prescaling : OUT std_logic; - --rs485_error : OUT std_logic; -- to be discussed! dac_array_rs485_out : OUT dac_array_type; enable_array_rs485_out : OUT enable_array_type; @@ -243,6 +277,7 @@ begin - clr <= dac_clr_sig; - + clr <= '1'; + TP_A <= "000000000000"; + enables_A <= enable_array_sig(0)(8 downto 0); enables_B <= enable_array_sig(1)(8 downto 0); @@ -251,4 +286,9 @@ new_rates_sig <= new_rate_A_sig and new_rate_B_sig and new_rate_C_sig and new_rate_D_sig and new_rate_t_sig; + + --these bits are not used, others come from rate counters + overflow_array(5) <= '0'; + overflow_array(6) <= '0'; + overflow_array(7) <= '0'; --differential input buffer for patch A @@ -357,27 +397,43 @@ Inst_FTU_control : FTU_control port map( - clk_50MHz => clk_50M_sig, - clk_ready => clk_ready_sig, - config_started => config_started_sig, - config_ready => config_ready_sig, - ram_doa => ram_doa_sig, - ram_dob => ram_dob_sig, - rate_array => rate_array_sig, - overflow_array => overflow_array, - new_rates => new_rates_sig, - reset => reset_sig, - config_start => config_start_sig, - ram_ena => ram_ena_sig, - ram_enb => ram_enb_sig, - ram_wea => ram_wea_sig, - ram_web => ram_web_sig, - ram_ada => ram_ada_sig, - ram_adb => ram_adb_sig, - ram_dia => ram_dia_sig, - ram_dib => ram_dib_sig, - dac_array => dac_array_sig, - enable_array => enable_array_sig, - cntr_reset => cntr_reset_sig, - prescaling => prescaling_sig + clk_50MHz => clk_50M_sig, + clk_ready => clk_ready_sig, + config_started => config_started_sig, + config_ready => config_ready_sig, + ram_doa => ram_doa_sig, + ram_dob => ram_dob_sig, + rate_array => rate_array_sig, + overflow_array => overflow_array, + new_rates => new_rates_sig, + new_DACs => new_DACs_sig, + new_enables => new_enables_sig, + new_prescaling => new_prescaling_sig, + read_rates => read_rates_sig, + read_DACs => read_DACs_sig, + read_enables => read_enables_sig, + read_prescaling => read_prescaling_sig, + dac_array_rs485_out => dac_array_rs485_out_sig, + enable_array_rs485_out => enable_array_rs485_out_sig, + prescaling_rs485_out => prescaling_rs485_out_sig, + reset => reset_sig, + config_start => config_start_sig, + ram_ena => ram_ena_sig, + ram_enb => ram_enb_sig, + ram_wea => ram_wea_sig, + ram_web => ram_web_sig, + ram_ada => ram_ada_sig, + ram_adb => ram_adb_sig, + ram_dia => ram_dia_sig, + ram_dib => ram_dib_sig, + rate_array_rs485 => rate_array_rs485_sig, + overflow_array_rs485_in => overflow_array_rs485_in_sig, + rates_ready => rates_ready_sig, + DACs_ready => DACs_ready_sig, + enables_ready => enables_ready_sig, + prescaling_ready => prescaling_ready_sig, + dac_array => dac_array_sig, + enable_array => enable_array_sig, + cntr_reset => cntr_reset_sig, + prescaling => prescaling_sig ); @@ -399,27 +455,26 @@ brd_add => brd_add, rx_d => rx, - rates_ready => '0', - DACs_ready => '0', - enables_ready => '0', - prescaling_ready => '0', - rate_array_rs485 => (0,0,0,0,0), - overflow_array_rs485_in => "00000000", - dac_array_rs485_in => DEFAULT_DAC, - enable_array_rs485_in => DEFAULT_ENABLE, - prescaling_rs485_in => conv_std_logic_vector(DEFAULT_PRESCALING,8), + rates_ready => rates_ready_sig, + DACs_ready => DACs_ready_sig, + enables_ready => enables_ready_sig, + prescaling_ready => prescaling_ready_sig, + rate_array_rs485 => rate_array_rs485_sig, + overflow_array_rs485_in => overflow_array_rs485_in_sig, + dac_array_rs485_in => dac_array_sig, + enable_array_rs485_in => enable_array_sig, + prescaling_rs485_in => prescaling_sig, rx_en => rx_en, tx_d => tx, tx_en => tx_en, - new_DACs => open, - new_enables => open, - new_prescaling => open, - read_rates => open, - read_DACs => open, - read_enables => open, - read_prescaling => open, - --rs485_error =>, -- to be discussed! - dac_array_rs485_out => open, - enable_array_rs485_out => open, - prescaling_rs485_out => open + new_DACs => new_DACs_sig, + new_enables => new_enables_sig, + new_prescaling => new_prescaling_sig, + read_rates => read_rates_sig, + read_DACs => read_DACs_sig, + read_enables => read_enables_sig, + read_prescaling => read_prescaling_sig, + dac_array_rs485_out => dac_array_rs485_out_sig, + enable_array_rs485_out => enable_array_rs485_out_sig, + prescaling_rs485_out => prescaling_rs485_out_sig ); Index: /firmware/FTU/FTU_top_tb.vhd =================================================================== --- /firmware/FTU/FTU_top_tb.vhd (revision 9938) +++ /firmware/FTU/FTU_top_tb.vhd (revision 9939) @@ -194,5 +194,5 @@ ); - -- Clock process definitions + -- Stimulus process for clock ext_clk_proc: process begin @@ -203,6 +203,6 @@ end process ext_clk_proc; - -- Stimulus process - stim_proc: process + -- Stimulus process for trigger + trigger_proc: process begin --------------------------------------------------------------------------- @@ -236,395 +236,91 @@ wait for 5ns; trigger_sig <= '0'; - --------------------------------------------------------------------------- - -- test now RS485 - --------------------------------------------------------------------------- - wait for 100us; - rx <= '0'; --start bit - wait for baud_rate_period; - rx <= '0'; --start delimiter bit 0 - wait for baud_rate_period; - rx <= '0'; --start delimiter bit 1 - wait for baud_rate_period; - rx <= '0'; --start delimiter bit 2 - wait for baud_rate_period; - rx <= '0'; --start delimiter bit 3 - wait for baud_rate_period; - rx <= '0'; --start delimiter bit 4 - wait for baud_rate_period; - rx <= '0'; --start delimiter bit 5 - wait for baud_rate_period; - rx <= '1'; --start delimiter bit 6 - wait for baud_rate_period; - rx <= '0'; --start delimiter bit 7 - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - --------------------------------------------------------------------------- + wait for 1430us; + trigger_sig <= '1'; + wait for 5ns; + trigger_sig <= '0'; + wait for 400us; + trigger_sig <= '1'; + wait for 5ns; + trigger_sig <= '0'; + wait; + end process trigger_proc; + + -- Stimulus process for RS485 + rs485_proc: process + + procedure assign_rs485 (data: std_logic_vector(7 downto 0)) is + begin + rx <= '0'; --start bit + wait for baud_rate_period; + rx <= data(0); --bit 0 + wait for baud_rate_period; + rx <= data(1); --bit 1 + wait for baud_rate_period; + rx <= data(2); --bit 2 + wait for baud_rate_period; + rx <= data(3); --bit 3 + wait for baud_rate_period; + rx <= data(4); --bit 4 + wait for baud_rate_period; + rx <= data(5); --bit 5 + wait for baud_rate_period; + rx <= data(6); --bit 6 + wait for baud_rate_period; + rx <= data(7); --bit 7 + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + rx <= '1'; --stop bit + wait for baud_rate_period; + end assign_rs485; + + begin + --------------------------------------------------------------------------- + -- wait until FTU is initialized + --------------------------------------------------------------------------- + wait for 150us; + --------------------------------------------------------------------------- + -- test one RS485 command (16 byte) + --------------------------------------------------------------------------- + assign_rs485("01000000"); --start delimiter wait for 1us; - rx <= '0'; --start bit - wait for baud_rate_period; - rx <= '0'; --FTU address bit 0 - wait for baud_rate_period; - rx <= '0'; --FTU address bit 1 - wait for baud_rate_period; - rx <= '0'; --FTU address bit 2 - wait for baud_rate_period; - rx <= '0'; --FTU address bit 3 - wait for baud_rate_period; - rx <= '0'; --FTU address bit 4 - wait for baud_rate_period; - rx <= '0'; --FTU address bit 5 - wait for baud_rate_period; - rx <= '0'; --FTU address bit 6 - wait for baud_rate_period; - rx <= '0'; --FTU address bit 7 - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - --------------------------------------------------------------------------- + assign_rs485("00000000"); --FTU address wait for 10ns; - rx <= '0'; --start bit - wait for baud_rate_period; - rx <= '0'; --FTM address bit 0 - wait for baud_rate_period; - rx <= '0'; --FTM address bit 1 - wait for baud_rate_period; - rx <= '0'; --FTM address bit 2 - wait for baud_rate_period; - rx <= '0'; --FTM address bit 3 - wait for baud_rate_period; - rx <= '0'; --FTM address bit 4 - wait for baud_rate_period; - rx <= '0'; --FTM address bit 5 - wait for baud_rate_period; - rx <= '1'; --FTM address bit 6 - wait for baud_rate_period; - rx <= '1'; --FTM address bit 7 - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - --------------------------------------------------------------------------- - wait for 100ns; - rx <= '0'; --start bit - wait for baud_rate_period; - rx <= '0'; --instruction bit 0 - wait for baud_rate_period; - rx <= '1'; --instruction bit 1 - wait for baud_rate_period; - rx <= '0'; --instruction bit 2 - wait for baud_rate_period; - rx <= '0'; --instruction bit 3 - wait for baud_rate_period; - rx <= '0'; --instruction bit 4 - wait for baud_rate_period; - rx <= '0'; --instruction bit 5 - wait for baud_rate_period; - rx <= '0'; --instruction bit 6 - wait for baud_rate_period; - rx <= '0'; --instruction bit 7 - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - --------------------------------------------------------------------------- + assign_rs485("11000000"); --FTM address + wait for 100ns; + assign_rs485("00000000"); --instruction wait for 200us; - rx <= '0'; --start bit - wait for baud_rate_period; - rx <= '0'; --data1 bit 0 - wait for baud_rate_period; - rx <= '0'; --data1 bit 1 - wait for baud_rate_period; - rx <= '0'; --data1 bit 2 - wait for baud_rate_period; - rx <= '0'; --data1 bit 3 - wait for baud_rate_period; - rx <= '0'; --data1 bit 4 - wait for baud_rate_period; - rx <= '0'; --data1 bit 5 - wait for baud_rate_period; - rx <= '0'; --data1 bit 6 - wait for baud_rate_period; - rx <= '0'; --data1 bit 7 - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - --------------------------------------------------------------------------- - wait for 100ns; - rx <= '0'; --start bit - wait for baud_rate_period; - rx <= '0'; --data2 bit 0 - wait for baud_rate_period; - rx <= '0'; --data2 bit 1 - wait for baud_rate_period; - rx <= '0'; --data2 bit 2 - wait for baud_rate_period; - rx <= '0'; --data2 bit 3 - wait for baud_rate_period; - rx <= '0'; --data2 bit 4 - wait for baud_rate_period; - rx <= '0'; --data2 bit 5 - wait for baud_rate_period; - rx <= '0'; --data2 bit 6 - wait for baud_rate_period; - rx <= '0'; --data2 bit 7 - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - --------------------------------------------------------------------------- - wait for 100ns; - rx <= '0'; --start bit - wait for baud_rate_period; - rx <= '0'; --data3 bit 0 - wait for baud_rate_period; - rx <= '0'; --data3 bit 1 - wait for baud_rate_period; - rx <= '0'; --data3 bit 2 - wait for baud_rate_period; - rx <= '0'; --data3 bit 3 - wait for baud_rate_period; - rx <= '0'; --data3 bit 4 - wait for baud_rate_period; - rx <= '0'; --data3 bit 5 - wait for baud_rate_period; - rx <= '0'; --data3 bit 6 - wait for baud_rate_period; - rx <= '0'; --data3 bit 7 - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - --------------------------------------------------------------------------- - wait for 100ns; - rx <= '0'; --start bit - wait for baud_rate_period; - rx <= '0'; --data4 bit 0 - wait for baud_rate_period; - rx <= '0'; --data4 bit 1 - wait for baud_rate_period; - rx <= '0'; --data4 bit 2 - wait for baud_rate_period; - rx <= '0'; --data4 bit 3 - wait for baud_rate_period; - rx <= '0'; --data4 bit 4 - wait for baud_rate_period; - rx <= '0'; --data4 bit 5 - wait for baud_rate_period; - rx <= '0'; --data4 bit 6 - wait for baud_rate_period; - rx <= '0'; --data4 bit 7 - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - --------------------------------------------------------------------------- - wait for 100ns; - rx <= '0'; --start bit - wait for baud_rate_period; - rx <= '0'; --data5 bit 0 - wait for baud_rate_period; - rx <= '0'; --data5 bit 1 - wait for baud_rate_period; - rx <= '0'; --data5 bit 2 - wait for baud_rate_period; - rx <= '0'; --data5 bit 3 - wait for baud_rate_period; - rx <= '0'; --data5 bit 4 - wait for baud_rate_period; - rx <= '0'; --data5 bit 5 - wait for baud_rate_period; - rx <= '0'; --data5 bit 6 - wait for baud_rate_period; - rx <= '0'; --data5 bit 7 - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - --------------------------------------------------------------------------- - wait for 100ns; - rx <= '0'; --start bit - wait for baud_rate_period; - rx <= '0'; --data6 bit 0 - wait for baud_rate_period; - rx <= '0'; --data6 bit 1 - wait for baud_rate_period; - rx <= '0'; --data6 bit 2 - wait for baud_rate_period; - rx <= '0'; --data6 bit 3 - wait for baud_rate_period; - rx <= '0'; --data6 bit 4 - wait for baud_rate_period; - rx <= '0'; --data6 bit 5 - wait for baud_rate_period; - rx <= '0'; --data6 bit 6 - wait for baud_rate_period; - rx <= '0'; --data6 bit 7 - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - --------------------------------------------------------------------------- - wait for 100ns; - rx <= '0'; --start bit - wait for baud_rate_period; - rx <= '0'; --data7 bit 0 - wait for baud_rate_period; - rx <= '0'; --data7 bit 1 - wait for baud_rate_period; - rx <= '0'; --data7 bit 2 - wait for baud_rate_period; - rx <= '0'; --data7 bit 3 - wait for baud_rate_period; - rx <= '0'; --data7 bit 4 - wait for baud_rate_period; - rx <= '0'; --data7 bit 5 - wait for baud_rate_period; - rx <= '0'; --data7 bit 6 - wait for baud_rate_period; - rx <= '0'; --data7 bit 7 - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - --------------------------------------------------------------------------- - wait for 100ns; - rx <= '0'; --start bit - wait for baud_rate_period; - rx <= '0'; --data8 bit 0 - wait for baud_rate_period; - rx <= '0'; --data8 bit 1 - wait for baud_rate_period; - rx <= '0'; --data8 bit 2 - wait for baud_rate_period; - rx <= '0'; --data8 bit 3 - wait for baud_rate_period; - rx <= '0'; --data8 bit 4 - wait for baud_rate_period; - rx <= '0'; --data8 bit 5 - wait for baud_rate_period; - rx <= '0'; --data8 bit 6 - wait for baud_rate_period; - rx <= '0'; --data8 bit 7 - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - --------------------------------------------------------------------------- - wait for 100ns; - rx <= '0'; --start bit - wait for baud_rate_period; - rx <= '0'; --data9 bit 0 - wait for baud_rate_period; - rx <= '0'; --data9 bit 1 - wait for baud_rate_period; - rx <= '0'; --data9 bit 2 - wait for baud_rate_period; - rx <= '0'; --data9 bit 3 - wait for baud_rate_period; - rx <= '0'; --data9 bit 4 - wait for baud_rate_period; - rx <= '0'; --data9 bit 5 - wait for baud_rate_period; - rx <= '0'; --data9 bit 6 - wait for baud_rate_period; - rx <= '0'; --data9 bit 7 - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - --------------------------------------------------------------------------- - wait for 100ns; - rx <= '0'; --start bit - wait for baud_rate_period; - rx <= '0'; --data10 bit 0 - wait for baud_rate_period; - rx <= '0'; --data10 bit 1 - wait for baud_rate_period; - rx <= '0'; --data10 bit 2 - wait for baud_rate_period; - rx <= '0'; --data10 bit 3 - wait for baud_rate_period; - rx <= '0'; --data10 bit 4 - wait for baud_rate_period; - rx <= '0'; --data10 bit 5 - wait for baud_rate_period; - rx <= '0'; --data10 bit 6 - wait for baud_rate_period; - rx <= '0'; --data10 bit 7 - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - --------------------------------------------------------------------------- - wait for 100ns; - rx <= '0'; --start bit - wait for baud_rate_period; - rx <= '0'; --data11 bit 0 - wait for baud_rate_period; - rx <= '0'; --data11 bit 1 - wait for baud_rate_period; - rx <= '0'; --data11 bit 2 - wait for baud_rate_period; - rx <= '0'; --data11 bit 3 - wait for baud_rate_period; - rx <= '0'; --data11 bit 4 - wait for baud_rate_period; - rx <= '0'; --data11 bit 5 - wait for baud_rate_period; - rx <= '0'; --data11 bit 6 - wait for baud_rate_period; - rx <= '0'; --data11 bit 7 - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - --------------------------------------------------------------------------- - wait for 100ns; - rx <= '0'; --start bit - wait for baud_rate_period; - rx <= '0'; --check sum bit 0 - wait for baud_rate_period; - rx <= '0'; --check sum bit 1 - wait for baud_rate_period; - rx <= '0'; --check sum bit 2 - wait for baud_rate_period; - rx <= '0'; --check sum bit 3 - wait for baud_rate_period; - rx <= '0'; --check sum bit 4 - wait for baud_rate_period; - rx <= '0'; --check sum bit 5 - wait for baud_rate_period; - rx <= '0'; --check sum bit 6 - wait for baud_rate_period; - rx <= '0'; --check sum bit 7 - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; - rx <= '1'; --stop bit - wait for baud_rate_period; + assign_rs485("00010000"); --data byte 01 + wait for 100ns; + assign_rs485("00000000"); --data byte 02 + wait for 100ns; + assign_rs485("10111100"); --data byte 03 + wait for 100ns; + assign_rs485("00000001"); --data byte 04 + wait for 100ns; + assign_rs485("00000000"); --data byte 05 + wait for 100ns; + assign_rs485("00000000"); --data byte 06 + wait for 100ns; + assign_rs485("00000000"); --data byte 07 + wait for 100ns; + assign_rs485("00000000"); --data byte 08 + wait for 100ns; + assign_rs485("00000000"); --data byte 09 + wait for 100ns; + assign_rs485("00000000"); --data byte 10 + wait for 100ns; + assign_rs485("00000000"); --data byte 11 + wait for 100ns; + assign_rs485("00000000"); --check sum + wait for 100ns; + --------------------------------------------------------------------------- + -- keep rx line high --------------------------------------------------------------------------- rx <= '1'; wait; - end process stim_proc; + end process rs485_proc; end; Index: /firmware/FTU/counter/FTU_rate_counter.vhd =================================================================== --- /firmware/FTU/counter/FTU_rate_counter.vhd (revision 9938) +++ /firmware/FTU/counter/FTU_rate_counter.vhd (revision 9939) @@ -119,7 +119,10 @@ begin if rising_edge(cntr_reset) then - --formula to calculate counting period from prescaling value + --calculate counting period from prescaling value + --default is 0.5s - 128s if CNTR_FREQ_DIVIDER = 1 if (prescaling = "00000000") then counting_period <= COUNTER_FREQUENCY / (2 * CNTR_FREQ_DIVIDER); + elsif (prescaling = "11111111") then + counting_period <= 128 * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER); else counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER); Index: /firmware/FTU/dac_spi/FTU_spi_controller.vhd =================================================================== --- /firmware/FTU/dac_spi/FTU_spi_controller.vhd (revision 9938) +++ /firmware/FTU/dac_spi/FTU_spi_controller.vhd (revision 9939) @@ -35,5 +35,4 @@ signal spi_cycle_cnt : integer range 0 to 25 := 0; signal shift_reg : std_logic_vector (23 downto 0) := (others => '0'); - signal data_reg : std_logic_vector (15 downto 0) := (others => '0'); BEGIN Index: /firmware/FTU/dac_spi/FTU_spi_distributor.vhd =================================================================== --- /firmware/FTU/dac_spi/FTU_spi_distributor.vhd (revision 9938) +++ /firmware/FTU/dac_spi/FTU_spi_distributor.vhd (revision 9939) @@ -51,4 +51,5 @@ spi_distr_state <= IDLE; when IDLE => + config_ready <= '0'; data <= (others => '0'); -- start DAC configuration Index: /firmware/FTU/ftu_definitions.vhd =================================================================== --- /firmware/FTU/ftu_definitions.vhd (revision 9938) +++ /firmware/FTU/ftu_definitions.vhd (revision 9939) @@ -58,5 +58,5 @@ constant INT_CLK_FREQUENCY : integer := 50000000; -- 50MHz constant COUNTER_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY - constant CNTR_FREQ_DIVIDER : integer := 500000; -- for simulation, should normally be 1 + constant CNTR_FREQ_DIVIDER : integer := 50000; -- for simulation, should normally be 1 --32byte dual-port RAM, port A: 8byte, port B: 16byte Index: /firmware/FTU/rs485/FTU_rs485_control.vhd =================================================================== --- /firmware/FTU/rs485/FTU_rs485_control.vhd (revision 9938) +++ /firmware/FTU/rs485/FTU_rs485_control.vhd (revision 9939) @@ -3,7 +3,7 @@ -- Engineer: Q. Weitzel, P. Vogler -- --- Create Date: 09/13/2010 +-- Create Date: 09/13/2010 -- Design Name: --- Module Name: FTU_rs485_control - Behavioral +-- Module Name: FTU_rs485_control - Behavioral -- Project Name: -- Target Devices: @@ -11,5 +11,5 @@ -- Description: top level entity of FTU RS485 module -- --- Dependencies: +-- Dependencies: -- -- Revision: @@ -50,12 +50,11 @@ tx_d : OUT std_logic; tx_en : OUT std_logic; - new_DACs : OUT std_logic; -- new DACs arrived via RS485 - new_enables : OUT std_logic; -- new enables arrived via RS485 - new_prescaling : OUT std_logic; -- new prescaling arrived via RS485 - read_rates : OUT std_logic; -- FTM wants to read rates - read_DACs : OUT std_logic; -- FTM wants to read DACs - read_enables : OUT std_logic; -- FTM wants to read enable pattern - read_prescaling : OUT std_logic; -- FTM wants to read prescaling value - --rs485_error : OUT std_logic; -- to be discussed! + new_DACs : OUT std_logic := '0'; -- new DACs arrived via RS485 + new_enables : OUT std_logic := '0'; -- new enables arrived via RS485 + new_prescaling : OUT std_logic := '0'; -- new prescaling arrived via RS485 + read_rates : OUT std_logic := '0'; -- FTM wants to read rates + read_DACs : OUT std_logic := '0'; -- FTM wants to read DACs + read_enables : OUT std_logic := '0'; -- FTM wants to read enable pattern + read_prescaling : OUT std_logic := '0'; -- FTM wants to read prescaling value dac_array_rs485_out : OUT dac_array_type; enable_array_rs485_out : OUT enable_array_type; @@ -278,5 +277,5 @@ when SET_DAC_WAIT=> -- wait until FTU control says "done" and then answer to FTM if (DACs_ready = '1') then - new_DACs <= '0'; + new_DACs <= '0'; FTU_rs485_control_State <= SET_DAC_TRANSMIT; else @@ -288,5 +287,5 @@ if (enables_ready = '1') then new_enables <= '0'; - FTU_rs485_control_State <= RECEIVE; + FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; else new_enables <= '1'; @@ -297,5 +296,5 @@ if (prescaling_ready = '1') then new_prescaling <= '0'; - FTU_rs485_control_State <= RECEIVE; + FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; else new_prescaling <= '1'; @@ -306,5 +305,5 @@ if (rates_ready = '1') then read_rates <= '0'; - FTU_rs485_control_State <= RECEIVE; + FTU_rs485_control_State <= READ_RATES_TRANSMIT; else read_rates <= '1'; @@ -315,5 +314,5 @@ if (DACs_ready = '1') then read_DACs <= '0'; - FTU_rs485_control_State <= RECEIVE; + FTU_rs485_control_State <= READ_DAC_TRANSMIT; else read_DACs <= '1'; @@ -324,5 +323,5 @@ if (enables_ready = '1') then read_enables <= '0'; - FTU_rs485_control_State <= RECEIVE; + FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; else read_enables <= '1'; @@ -333,5 +332,5 @@ if (prescaling_ready = '1') then read_prescaling <= '0'; - FTU_rs485_control_State <= RECEIVE; + FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; else read_prescaling <= '1'; Index: /firmware/FTU/rs485/FTU_rs485_interpreter.vhd =================================================================== --- /firmware/FTU/rs485/FTU_rs485_interpreter.vhd (revision 9938) +++ /firmware/FTU/rs485/FTU_rs485_interpreter.vhd (revision 9939) @@ -110,10 +110,12 @@ int_read_enables <= '0'; int_read_prescaling <= '0'; - dac_array_rs485_out_sig <= (conv_integer(unsigned(data_block(47 downto 32))), - conv_integer(unsigned(data_block(63 downto 48))), - conv_integer(unsigned(data_block(79 downto 64))), - conv_integer(unsigned(data_block(95 downto 80))), - 0,0,0, - conv_integer(unsigned(data_block(111 downto 96))) + dac_array_rs485_out_sig <= (conv_integer(unsigned(data_block(43 downto 32))), + conv_integer(unsigned(data_block(59 downto 48))), + conv_integer(unsigned(data_block(75 downto 64))), + conv_integer(unsigned(data_block(91 downto 80))), + DEFAULT_DAC(4), + DEFAULT_DAC(5), + DEFAULT_DAC(6), + conv_integer(unsigned(data_block(107 downto 96))) ); FTU_rs485_interpreter_State <= WAIT_FOR_DATA;