-- VHDL Entity FACT_FAD_TB_lib.dna_gen_tb.symbol
--
-- Created:
--          by - daqct3.UNKNOWN (IHP110)
--          at - 09:58:10 03.03.2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--


ENTITY dna_gen_tb IS
-- Declarations

END dna_gen_tb ;

--
-- VHDL Architecture FACT_FAD_TB_lib.dna_gen_tb.struct
--
-- Created:
--          by - daqct3.UNKNOWN (IHP110)
--          at - 09:58:10 03.03.2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;

LIBRARY FACT_FAD_lib;
LIBRARY FACT_FAD_TB_lib;

ARCHITECTURE struct OF dna_gen_tb IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL clk   : STD_LOGIC;
   SIGNAL dna   : STD_LOGIC_VECTOR(63 DOWNTO 0);
   SIGNAL ready : STD_LOGIC;


   -- Component Declarations
   COMPONENT dna_gen
   PORT (
      clk   : IN     STD_LOGIC;
      dna   : OUT    STD_LOGIC_VECTOR (63 DOWNTO 0) := (others => '0');
      ready : OUT    STD_LOGIC                      := '0'
   );
   END COMPONENT;
   COMPONENT clock_generator
   GENERIC (
      clock_period : time := 20 ns;
      reset_time   : time := 50 ns
   );
   PORT (
      clk : OUT    std_logic  := '0';
      rst : OUT    std_logic  := '0'
   );
   END COMPONENT;
   COMPONENT dna_gen_tester
   PORT (
      dna   : IN     STD_LOGIC_VECTOR (63 DOWNTO 0);
      ready : IN     STD_LOGIC 
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator;
   FOR ALL : dna_gen USE ENTITY FACT_FAD_lib.dna_gen;
   FOR ALL : dna_gen_tester USE ENTITY FACT_FAD_TB_lib.dna_gen_tester;
   -- pragma synthesis_on


BEGIN

   -- Instance port mappings.
   U_0 : dna_gen
      PORT MAP (
         clk   => clk,
         dna   => dna,
         ready => ready
      );
   U_2 : clock_generator
      GENERIC MAP (
         clock_period => 20 ns,
         reset_time   => 50 ns
      )
      PORT MAP (
         clk => clk,
         rst => OPEN
      );
   U_1 : dna_gen_tester
      PORT MAP (
         dna   => dna,
         ready => ready
      );

END struct;