-- -- VHDL Architecture FACT_FAD_TB_lib.spi_ltc2600_tester.beha -- -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) -- at - 20:02:26 03.02.2011 -- -- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10) -- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.all; ENTITY spi_ltc2600_tester IS PORT( CS : IN std_logic; MISO : IN std_logic; MOSI : IN std_logic; SCLK : IN std_logic; busy : IN std_logic; ready : IN std_logic; address : OUT std_logic_vector (3 DOWNTO 0); command : OUT std_logic_vector (3 DOWNTO 0); data : OUT std_logic_vector (15 DOWNTO 0); transmit : OUT std_logic ); -- Declarations END spi_ltc2600_tester ; -- ARCHITECTURE beha OF spi_ltc2600_tester IS BEGIN process begin command <= "0011"; address <= "1101"; data <= X"96F7"; transmit <= '0'; wait for 5000ns; transmit <= '1'; wait for 50ns; transmit <= '0'; wait for 20us; transmit <= '1'; wait for 50ns; transmit <= '0'; wait; end process; END ARCHITECTURE beha;