-- VHDL Entity FACT_FAD_TB_lib.timer_tb.symbol
--
-- Created:
--          by - dneise.UNKNOWN (E5B-LABOR6)
--          at - 12:25:01 23.02.2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
--


ENTITY timer_tb IS
   GENERIC( 
      TIMER_WIDTH : integer := 32;
      PRESCALER   : integer := 2500
   );
-- Declarations

END timer_tb ;

--
-- VHDL Architecture FACT_FAD_TB_lib.timer_tb.struct
--
-- Created:
--          by - dneise.UNKNOWN (E5B-LABOR6)
--          at - 12:25:01 23.02.2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.all;

LIBRARY FACT_FAD_lib;
LIBRARY FACT_FAD_TB_lib;

ARCHITECTURE struct OF timer_tb IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL clk           : std_logic;
   SIGNAL enable_i      : std_logic;
   SIGNAL reset_synch_i : std_logic;
   SIGNAL synch_i       : std_logic;
   SIGNAL synched_o     : std_logic := '0';
   SIGNAL time_o        : std_logic_vector( TIMER_WIDTH-1 DOWNTO 0);


   -- Component Declarations
   COMPONENT timer
   GENERIC (
      TIMER_WIDTH : integer := 32;
      PRESCALER   : integer := 5000
   );
   PORT (
      clk           : IN     std_logic;
      enable_i      : IN     std_logic;
      reset_synch_i : IN     std_logic;
      synch_i       : IN     std_logic;
      synched_o     : OUT    std_logic  := '0';
      time_o        : OUT    std_logic_vector ( TIMER_WIDTH-1 DOWNTO 0)
   );
   END COMPONENT;
   COMPONENT timer_tester
   PORT (
      synched_o     : IN     std_logic;
      time_o        : IN     std_logic_vector ( 31 DOWNTO 0);
      clk           : OUT    std_logic;
      enable_i      : OUT    std_logic;
      reset_synch_i : OUT    std_logic;
      synch_i       : OUT    std_logic
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : timer USE ENTITY FACT_FAD_lib.timer;
   FOR ALL : timer_tester USE ENTITY FACT_FAD_TB_lib.timer_tester;
   -- pragma synthesis_on


BEGIN

   -- Instance port mappings.
   U_0 : timer
      GENERIC MAP (
         TIMER_WIDTH => 32,
         PRESCALER   => 5000
      )
      PORT MAP (
         clk           => clk,
         time_o        => time_o,
         synch_i       => synch_i,
         synched_o     => synched_o,
         reset_synch_i => reset_synch_i,
         enable_i      => enable_i
      );
   U_1 : timer_tester
      PORT MAP (
         synched_o     => synched_o,
         time_o        => time_o,
         enable_i      => enable_i,
         reset_synch_i => reset_synch_i,
         clk           => clk,
         synch_i       => synch_i
      );

END struct;