-- VHDL Entity FACT_FAD_TB_lib.trigger_manager_tb.symbol -- -- Created: -- by - daqct3.UNKNOWN (IHP110) -- at - 14:19:05 14.01.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- ENTITY trigger_manager_tb IS -- Declarations END trigger_manager_tb ; -- -- VHDL Architecture FACT_FAD_TB_lib.trigger_manager_tb.struct -- -- Created: -- by - daqct3.UNKNOWN (IHP110) -- at - 14:19:06 14.01.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.all; LIBRARY FACT_FAD_lib; LIBRARY FACT_FAD_TB_lib; ARCHITECTURE struct OF trigger_manager_tb IS -- Architecture declarations -- Internal signal declarations SIGNAL clk : std_logic; SIGNAL drs_readout_ready : std_logic := '0'; SIGNAL drs_readout_ready_ack : std_logic; SIGNAL drs_write : std_logic := '1'; SIGNAL trigger_in : std_logic := '0'; SIGNAL trigger_out : std_logic := '0'; -- Component Declarations COMPONENT trigger_manager PORT ( clk : IN std_logic; drs_readout_ready : IN std_logic; trigger_in : IN std_logic; drs_readout_ready_ack : OUT std_logic := '0'; drs_write : OUT std_logic := '1'; trigger_out : OUT std_logic := '0' ); END COMPONENT; COMPONENT clock_generator GENERIC ( clock_period : time := 20 ns; reset_time : time := 50 ns ); PORT ( clk : OUT std_logic := '0'; rst : OUT std_logic := '0' ); END COMPONENT; COMPONENT trigger_manager_tester PORT ( drs_readout_ready_ack : IN std_logic ; drs_readout_ready : OUT std_logic ; trigger_in : OUT std_logic ); END COMPONENT; -- Optional embedded configurations -- pragma synthesis_off FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator; FOR ALL : trigger_manager USE ENTITY FACT_FAD_lib.trigger_manager; FOR ALL : trigger_manager_tester USE ENTITY FACT_FAD_TB_lib.trigger_manager_tester; -- pragma synthesis_on BEGIN -- Instance port mappings. U_0 : trigger_manager PORT MAP ( clk => clk, trigger_in => trigger_in, trigger_out => trigger_out, drs_write => drs_write, drs_readout_ready => drs_readout_ready, drs_readout_ready_ack => drs_readout_ready_ack ); -- synthesis translate_off U_2 : clock_generator GENERIC MAP ( clock_period => 20 ns, reset_time => 50 ns ) PORT MAP ( clk => clk, rst => OPEN ); U_1 : trigger_manager_tester PORT MAP ( drs_readout_ready_ack => drs_readout_ready_ack, drs_readout_ready => drs_readout_ready, trigger_in => trigger_in ); END struct;