-- Coregen VHDL wrapper file modified by HDL Designer -------------------------------------------------------------------------------- -- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 10.1.03 -- \ \ Application : xaw2vhdl -- / / Filename : dcm_var_ps_38ns.vhd -- /___/ /\ Timestamp : 08/30/2010 11:48:13 -- \ \ / \ -- \___\/\___\ -- --Command: xaw2vhdl-st C:/DOKUME~1/dneise/LOKALE~1/Temp/coregen_dneise/coregen/project/dcm_var_ps_38ns.xaw C:/DOKUME~1/dneise/LOKALE~1/Temp/coregen_dneise/coregen/project/dcm_var_ps_38ns --Design Name: dcm_var_ps_38ns --Device: xc3s700a-4fg400 -- -- Module dcm_var_ps_38ns -- Written for synthesis tool: Precision library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity dcm_var_ps_38ns is port ( CLKIN_IN : in std_logic; PSCLK_IN : in std_logic; PSEN_IN : in std_logic; PSINCDEC_IN : in std_logic; RST_IN : in std_logic; CLK0_OUT : out std_logic; LOCKED_OUT : out std_logic; PSDONE_OUT : out std_logic); end dcm_var_ps_38ns; architecture BEHAVIORAL of dcm_var_ps_38ns is -- hds translate_off attribute CLK_FEEDBACK : string ; attribute CLKDV_DIVIDE : string ; attribute CLKFX_DIVIDE : string ; attribute CLKFX_MULTIPLY : string ; attribute CLKIN_DIVIDE_BY_2 : string ; attribute CLKIN_PERIOD : string ; attribute CLKOUT_PHASE_SHIFT : string ; attribute DESKEW_ADJUST : string ; attribute DFS_FREQUENCY_MODE : string ; attribute DLL_FREQUENCY_MODE : string ; attribute DUTY_CYCLE_CORRECTION : string ; attribute FACTORY_JF : string ; attribute PHASE_SHIFT : string ; attribute STARTUP_WAIT : string ; signal CLKFB_IN : std_logic; signal CLK0_BUF : std_logic; signal GND_BIT : std_logic; component BUFG port ( I : in std_logic; O : out std_logic); end component; component DCM_SP -- pragma synthesis_off generic( CLK_FEEDBACK : string := "1X"; CLKDV_DIVIDE : real := 2.0; CLKFX_DIVIDE : integer := 1; CLKFX_MULTIPLY : integer := 4; CLKIN_DIVIDE_BY_2 : boolean := FALSE; CLKIN_PERIOD : real := 10.0; CLKOUT_PHASE_SHIFT : string := "NONE"; DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; DFS_FREQUENCY_MODE : string := "LOW"; DLL_FREQUENCY_MODE : string := "LOW"; DUTY_CYCLE_CORRECTION : boolean := TRUE; FACTORY_JF : bit_vector := x"C080"; PHASE_SHIFT : integer := 0; STARTUP_WAIT : boolean := FALSE; DSS_MODE : string := "NONE"); -- pragma synthesis_on port ( CLKIN : in std_logic; CLKFB : in std_logic; RST : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSCLK : in std_logic; DSSEN : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLKDV : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic; STATUS : out std_logic_vector (7 downto 0); LOCKED : out std_logic; PSDONE : out std_logic); end component; attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X"; attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0"; attribute CLKFX_DIVIDE of DCM_SP_INST : label is "1"; attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "4"; attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE"; attribute CLKIN_PERIOD of DCM_SP_INST : label is "50.000"; attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "VARIABLE"; attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS"; attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW"; attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE"; attribute FACTORY_JF of DCM_SP_INST : label is "C080"; attribute PHASE_SHIFT of DCM_SP_INST : label is "0"; attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE"; -- hds translate_on begin -- hds translate_off GND_BIT <= '0'; CLK0_OUT <= CLKFB_IN; CLK0_BUFG_INST : BUFG port map (I=>CLK0_BUF, O=>CLKFB_IN); DCM_SP_INST : DCM_SP -- pragma synthesis_off generic map( CLK_FEEDBACK => "1X", CLKDV_DIVIDE => 2.0, CLKFX_DIVIDE => 1, CLKFX_MULTIPLY => 4, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 50.000, CLKOUT_PHASE_SHIFT => "VARIABLE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) -- pragma synthesis_on port map (CLKFB=>CLKFB_IN, CLKIN=>CLKIN_IN, DSSEN=>GND_BIT, PSCLK=>PSCLK_IN, PSEN=>PSEN_IN, PSINCDEC=>PSINCDEC_IN, RST=>RST_IN, CLKDV=>open, CLKFX=>open, CLKFX180=>open, CLK0=>CLK0_BUF, CLK2X=>open, CLK2X180=>open, CLK90=>open, CLK180=>open, CLK270=>open, LOCKED=>LOCKED_OUT, PSDONE=>PSDONE_OUT, STATUS=>open); -- hds translate_on end BEHAVIORAL;