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]
)
viewicon (ZoomableIcon
uid 412,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "17250,16250,18750,17750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*32 (SaComponent
uid 514,0
optionalChildren [
*33 (CptPort
uid 482,0
ps "OnEdgeStrategy"
shape (Triangle
uid 483,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "13250,31625,14000,32375"
)
tg (CPTG
uid 484,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 485,0
va (VaSet
font "arial,8,0"
)
xt "15000,31500,18900,32500"
st "CLKIN_IN"
blo "15000,32300"
)
)
thePort (LogicalPort
decl (Decl
n "CLKIN_IN"
t "std_logic"
o 1
)
)
)
*34 (CptPort
uid 486,0
ps "OnEdgeStrategy"
shape (Triangle
uid 487,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "13250,32625,14000,33375"
)
tg (CPTG
uid 488,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 489,0
va (VaSet
font "arial,8,0"
)
xt "15000,32500,19100,33500"
st "PSCLK_IN"
blo "15000,33300"
)
)
thePort (LogicalPort
decl (Decl
n "PSCLK_IN"
t "std_logic"
o 2
)
)
)
*35 (CptPort
uid 490,0
ps "OnEdgeStrategy"
shape (Triangle
uid 491,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "13250,33625,14000,34375"
)
tg (CPTG
uid 492,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 493,0
va (VaSet
font "arial,8,0"
)
xt "15000,33500,18700,34500"
st "PSEN_IN"
blo "15000,34300"
)
)
thePort (LogicalPort
decl (Decl
n "PSEN_IN"
t "std_logic"
o 3
)
)
)
*36 (CptPort
uid 494,0
ps "OnEdgeStrategy"
shape (Triangle
uid 495,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "13250,34625,14000,35375"
)
tg (CPTG
uid 496,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 497,0
va (VaSet
font "arial,8,0"
)
xt "15000,34500,21100,35500"
st "PSINCDEC_IN"
blo "15000,35300"
)
)
thePort (LogicalPort
decl (Decl
n "PSINCDEC_IN"
t "std_logic"
o 4
)
)
)
*37 (CptPort
uid 502,0
ps "OnEdgeStrategy"
shape (Triangle
uid 503,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "29000,31625,29750,32375"
)
tg (CPTG
uid 504,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 505,0
va (VaSet
font "arial,8,0"
)
xt "23600,31500,28000,32500"
st "CLK0_OUT"
ju 2
blo "28000,32300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK0_OUT"
t "std_logic"
o 6
)
)
)
*38 (CptPort
uid 506,0
ps "OnEdgeStrategy"
shape (Triangle
uid 507,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "29000,32625,29750,33375"
)
tg (CPTG
uid 508,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 509,0
va (VaSet
font "arial,8,0"
)
xt "21900,32500,28000,33500"
st "LOCKED_OUT"
ju 2
blo "28000,33300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "LOCKED_OUT"
t "std_logic"
o 7
)
)
)
*39 (CptPort
uid 510,0
ps "OnEdgeStrategy"
shape (Triangle
uid 511,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "29000,33625,29750,34375"
)
tg (CPTG
uid 512,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 513,0
va (VaSet
font "arial,8,0"
)
xt "21800,33500,28000,34500"
st "PSDONE_OUT"
ju 2
blo "28000,34300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "PSDONE_OUT"
t "std_logic"
o 8
)
)
)
*40 (CptPort
uid 1487,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1488,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "13250,35625,14000,36375"
)
tg (CPTG
uid 1489,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1490,0
va (VaSet
font "arial,8,0"
)
xt "15000,35500,18200,36500"
st "RST_IN"
blo "15000,36300"
)
)
thePort (LogicalPort
decl (Decl
n "RST_IN"
t "std_logic"
o 5
)
)
)
]
shape (Rectangle
uid 515,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "14000,31000,29000,38000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 516,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*41 (Text
uid 517,0
va (VaSet
font "arial,8,1"
)
xt "14800,38000,21000,39000"
st "FACT_FAD_lib"
blo "14800,38800"
tm "BdLibraryNameMgr"
)
*42 (Text
uid 518,0
va (VaSet
font "arial,8,1"
)
xt "14800,39000,22200,40000"
st "dcm_var_ps_38ns"
blo "14800,39800"
tm "CptNameMgr"
)
*43 (Text
uid 519,0
va (VaSet
font "arial,8,1"
)
xt "14800,40000,21900,41000"
st "dcm_var_ps_inst"
blo "14800,40800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 520,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 521,0
text (MLText
uid 522,0
va (VaSet
font "Courier New,8,0"
)
xt "21500,31000,21500,31000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 523,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "14250,36250,15750,37750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*44 (Net
uid 524,0
decl (Decl
n "CLK0_OUT"
t "std_logic"
o 14
suid 14,0
)
declText (MLText
uid 525,0
va (VaSet
font "Courier New,8,0"
)
xt "11000,-5000,29500,-4200"
st "SIGNAL CLK0_OUT        : std_logic"
)
)
*45 (Net
uid 530,0
decl (Decl
n "PSCLK_IN"
t "std_logic"
o 16
suid 15,0
)
declText (MLText
uid 531,0
va (VaSet
font "Courier New,8,0"
)
xt "11000,-3400,29500,-2600"
st "SIGNAL PSCLK_IN        : std_logic"
)
)
*46 (Net
uid 544,0
decl (Decl
n "PSEN_IN"
t "std_logic"
o 18
suid 16,0
)
declText (MLText
uid 545,0
va (VaSet
font "Courier New,8,0"
)
xt "11000,-1800,29500,-1000"
st "SIGNAL PSEN_IN         : std_logic"
)
)
*47 (Net
uid 558,0
decl (Decl
n "PSINCDEC_IN"
t "std_logic"
o 19
suid 17,0
)
declText (MLText
uid 559,0
va (VaSet
font "Courier New,8,0"
)
xt "11000,-1000,29500,-200"
st "SIGNAL PSINCDEC_IN     : std_logic"
)
)
*48 (Net
uid 586,0
decl (Decl
n "PSDONE_OUT"
t "std_logic"
o 17
suid 19,0
)
declText (MLText
uid 587,0
va (VaSet
font "Courier New,8,0"
)
xt "11000,-2600,29500,-1800"
st "SIGNAL PSDONE_OUT      : std_logic"
)
)
*49 (Net
uid 600,0
decl (Decl
n "LOCKED_OUT"
t "std_logic"
o 15
suid 20,0
)
declText (MLText
uid 601,0
va (VaSet
font "Courier New,8,0"
)
xt "11000,-4200,29500,-3400"
st "SIGNAL LOCKED_OUT      : std_logic"
)
)
*50 (SaComponent
uid 826,0
optionalChildren [
*51 (CptPort
uid 767,0
ps "OnEdgeStrategy"
shape (Triangle
uid 768,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,28625,38000,29375"
)
tg (CPTG
uid 769,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 770,0
va (VaSet
)
xt "39000,28500,40900,29500"
st "CLK"
blo "39000,29300"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*52 (CptPort
uid 771,0
ps "OnEdgeStrategy"
shape (Triangle
uid 772,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "64000,37625,64750,38375"
)
tg (CPTG
uid 773,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 774,0
va (VaSet
)
xt "60100,37500,63000,38500"
st "PSCLK"
ju 2
blo "63000,38300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "PSCLK"
t "std_logic"
prec "-- interface to: clock_generator_variable_PS_struct.vhd"
preAdd 0
posAdd 0
o 3
suid 2,0
)
)
)
*53 (CptPort
uid 775,0
ps "OnEdgeStrategy"
shape (Triangle
uid 776,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "64000,38625,64750,39375"
)
tg (CPTG
uid 777,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 778,0
va (VaSet
)
xt "60500,38500,63000,39500"
st "PSEN"
ju 2
blo "63000,39300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "PSEN"
t "std_logic"
preAdd 0
posAdd 0
o 4
suid 3,0
i "'0'"
)
)
)
*54 (CptPort
uid 779,0
ps "OnEdgeStrategy"
shape (Triangle
uid 780,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "64000,39625,64750,40375"
)
tg (CPTG
uid 781,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 782,0
va (VaSet
)
xt "58500,39500,63000,40500"
st "PSINCDEC"
ju 2
blo "63000,40300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "PSINCDEC"
t "std_logic"
eolc "-- default is 'incrementing'"
preAdd 0
posAdd 0
o 5
suid 4,0
i "'1'"
)
)
)
*55 (CptPort
uid 783,0
ps "OnEdgeStrategy"
shape (Triangle
uid 784,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,33625,38000,34375"
)
tg (CPTG
uid 785,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 786,0
va (VaSet
)
xt "39000,33500,42700,34500"
st "PSDONE"
blo "39000,34300"
)
)
thePort (LogicalPort
decl (Decl
n "PSDONE"
t "std_logic"
eolc "-- will pulse once, if phase shifting was done."
preAdd 0
posAdd 0
o 6
suid 5,0
)
)
)
*56 (CptPort
uid 787,0
ps "OnEdgeStrategy"
shape (Triangle
uid 788,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,32625,38000,33375"
)
tg (CPTG
uid 789,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 790,0
va (VaSet
)
xt "39000,32500,42600,33500"
st "LOCKED"
blo "39000,33300"
)
)
thePort (LogicalPort
decl (Decl
n "LOCKED"
t "std_logic"
eolc "-- when is this going high?"
preAdd 0
posAdd 0
o 7
suid 6,0
)
)
)
*57 (CptPort
uid 795,0
ps "OnEdgeStrategy"
shape (Triangle
uid 796,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,38625,38000,39375"
)
tg (CPTG
uid 797,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 798,0
va (VaSet
)
xt "39000,38500,43600,39500"
st "shift_phase"
blo "39000,39300"
)
)
thePort (LogicalPort
decl (Decl
n "shift_phase"
t "std_logic"
prec "-- interface to: w5300_modul.vhd"
preAdd 0
posAdd 0
o 8
suid 8,0
)
)
)
*58 (CptPort
uid 799,0
ps "OnEdgeStrategy"
shape (Triangle
uid 800,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,39625,38000,40375"
)
tg (CPTG
uid 801,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 802,0
va (VaSet
)
xt "39000,39500,42300,40500"
st "direction"
blo "39000,40300"
)
)
thePort (LogicalPort
decl (Decl
n "direction"
t "std_logic"
eolc "-- corresponds to 'PSINCDEC'"
preAdd 0
posAdd 0
o 9
suid 9,0
)
)
)
*59 (CptPort
uid 803,0
ps "OnEdgeStrategy"
shape (Triangle
uid 804,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "64000,29625,64750,30375"
)
tg (CPTG
uid 805,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 806,0
va (VaSet
)
xt "60100,29500,63000,30500"
st "shifting"
ju 2
blo "63000,30300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "shifting"
t "std_logic"
prec "-- status:"
preAdd 0
posAdd 0
o 11
suid 10,0
i "'0'"
)
)
)
*60 (CptPort
uid 807,0
ps "OnEdgeStrategy"
shape (Triangle
uid 808,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "64000,28625,64750,29375"
)
tg (CPTG
uid 809,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 810,0
va (VaSet
)
xt "60800,28500,63000,29500"
st "ready"
ju 2
blo "63000,29300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ready"
t "std_logic"
preAdd 0
posAdd 0
o 12
suid 11,0
i "'0'"
)
)
)
*61 (CptPort
uid 811,0
ps "OnEdgeStrategy"
shape (Triangle
uid 812,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "64000,31625,64750,32375"
)
tg (CPTG
uid 813,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 814,0
va (VaSet
)
xt "57300,31500,63000,32500"
st "offset : (7:0)"
ju 2
blo "63000,32300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "offset"
t "std_logic_vector"
b "(7 DOWNTO 0)"
preAdd 0
posAdd 0
o 15
suid 12,0
i "(OTHERS => '0')"
)
)
)
*62 (CptPort
uid 1621,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2010,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,40625,38000,41375"
)
tg (CPTG
uid 1623,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1624,0
va (VaSet
)
xt "39000,40500,40300,41500"
st "rst"
blo "39000,41300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rst"
t "std_logic"
eolc "--asynch in of DCM"
posAdd 0
o 2
suid 15,0
i "'0'"
)
)
)
*63 (CptPort
uid 1975,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1976,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,41625,38000,42375"
)
tg (CPTG
uid 1977,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1978,0
va (VaSet
)
xt "39000,41500,43400,42500"
st "reset_DCM"
blo "39000,42300"
)
)
thePort (LogicalPort
decl (Decl
n "reset_DCM"
t "std_logic"
eolc "-- asynch in: orders us, to reset the DCM"
posAdd 0
o 10
suid 17,0
)
)
)
*64 (CptPort
uid 2013,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2014,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "64000,32625,64750,33375"
)
tg (CPTG
uid 2015,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2016,0
va (VaSet
)
xt "55900,32500,63000,33500"
st "locked_status_o"
ju 2
blo "63000,33300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "locked_status_o"
t "std_logic"
o 13
suid 18,0
)
)
)
*65 (CptPort
uid 2017,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2018,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "64000,33625,64750,34375"
)
tg (CPTG
uid 2019,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2020,0
va (VaSet
)
xt "56200,33500,63000,34500"
st "ready_status_o"
ju 2
blo "63000,34300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ready_status_o"
t "std_logic"
o 14
suid 19,0
)
)
)
]
shape (Rectangle
uid 827,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "38000,28000,64000,44000"
)
oxt "50000,7000,63000,25000"
ttg (MlTextGroup
uid 828,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*66 (Text
uid 829,0
va (VaSet
font "Arial,8,1"
)
xt "47700,34000,53900,35000"
st "FACT_FAD_lib"
blo "47700,34800"
tm "BdLibraryNameMgr"
)
*67 (Text
uid 830,0
va (VaSet
font "Arial,8,1"
)
xt "47700,35000,53500,36000"
st "phase_shifter"
blo "47700,35800"
tm "CptNameMgr"
)
*68 (Text
uid 831,0
va (VaSet
font "Arial,8,1"
)
xt "47700,36000,55200,37000"
st "ps_controller_inst"
blo "47700,36800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 832,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 833,0
text (MLText
uid 834,0
va (VaSet
font "Courier New,8,0"
)
xt "38000,27000,38000,27000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 835,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "38250,42250,39750,43750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*69 (PortIoOut
uid 1248,0
shape (CompositeShape
uid 1249,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1250,0
sl 0
ro 270
xt "30500,31625,32000,32375"
)
(Line
uid 1251,0
sl 0
ro 270
xt "30000,32000,30500,32000"
pts [
"30000,32000"
"30500,32000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 1252,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1253,0
va (VaSet
font "arial,8,0"
)
xt "33000,31500,37500,32500"
st "CLK_25_PS"
blo "33000,32300"
tm "WireNameMgr"
)
)
)
*70 (Net
uid 1260,0
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 22
suid 34,0
)
declText (MLText
uid 1261,0
va (VaSet
font "Courier New,8,0"
)
xt "11000,-10000,26000,-9200"
st "CLK_25_PS       : std_logic"
)
)
*71 (PortIoIn
uid 1266,0
shape (CompositeShape
uid 1267,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1268,0
sl 0
ro 270
xt "33000,38625,34500,39375"
)
(Line
uid 1269,0
sl 0
ro 270
xt "34500,39000,35000,39000"
pts [
"34500,39000"
"35000,39000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 1270,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1271,0
va (VaSet
font "arial,8,0"
)
xt "29000,38500,32000,39500"
st "do_shift"
ju 2
blo "32000,39300"
tm "WireNameMgr"
)
)
)
*72 (Net
uid 1278,0
decl (Decl
n "do_shift"
t "std_logic"
o 23
suid 35,0
)
declText (MLText
uid 1279,0
va (VaSet
font "Courier New,8,0"
)
xt "11000,-11600,26000,-10800"
st "do_shift        : std_logic"
)
)
*73 (PortIoIn
uid 1280,0
shape (CompositeShape
uid 1281,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1282,0
sl 0
ro 270
xt "33000,39625,34500,40375"
)
(Line
uid 1283,0
sl 0
ro 270
xt "34500,40000,35000,40000"
pts [
"34500,40000"
"35000,40000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 1284,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1285,0
va (VaSet
font "arial,8,0"
)
xt "28700,39500,32000,40500"
st "direction"
ju 2
blo "32000,40300"
tm "WireNameMgr"
)
)
)
*74 (Net
uid 1292,0
decl (Decl
n "direction"
t "std_logic"
o 24
suid 36,0
)
declText (MLText
uid 1293,0
va (VaSet
font "Courier New,8,0"
)
xt "11000,-12400,26000,-11600"
st "direction       : std_logic"
)
)
*75 (Net
uid 1491,0
decl (Decl
n "RST_IN"
t "std_logic"
o 22
suid 37,0
)
declText (MLText
uid 1492,0
va (VaSet
font "Courier New,8,0"
)
xt "11000,-13200,26000,-12400"
st "RST_IN          : std_logic"
)
)
*76 (PortIoIn
uid 1499,0
shape (CompositeShape
uid 1500,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1501,0
sl 0
ro 270
xt "33000,41625,34500,42375"
)
(Line
uid 1502,0
sl 0
ro 270
xt "34500,42000,35000,42000"
pts [
"34500,42000"
"35000,42000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 1503,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1504,0
va (VaSet
font "arial,8,0"
)
xt "28800,41500,32000,42500"
st "RST_IN"
ju 2
blo "32000,42300"
tm "WireNameMgr"
)
)
)
*77 (Net
uid 1607,0
decl (Decl
n "offset"
t "std_logic_vector"
b "(7 DOWNTO 0)"
preAdd 0
posAdd 0
o 14
suid 39,0
i "(OTHERS => '0')"
)
declText (MLText
uid 1608,0
va (VaSet
font "Courier New,8,0"
)
xt "11000,-7600,45500,-6800"
st "offset          : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"
)
)
*78 (PortIoOut
uid 1615,0
shape (CompositeShape
uid 1616,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1617,0
sl 0
ro 270
xt "73500,31625,75000,32375"
)
(Line
uid 1618,0
sl 0
ro 270
xt "73000,32000,73500,32000"
pts [
"73000,32000"
"73500,32000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 1619,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1620,0
va (VaSet
font "arial,8,0"
)
xt "76000,31500,78200,32500"
st "offset"
blo "76000,32300"
tm "WireNameMgr"
)
)
)
*79 (Net
uid 1979,0
decl (Decl
n "rst"
t "std_logic"
eolc "--asynch in of DCM"
posAdd 0
o 15
suid 40,0
i "'0'"
)
declText (MLText
uid 1980,0
va (VaSet
font "Courier New,8,0"
)
xt "11000,-200,52500,600"
st "SIGNAL rst             : std_logic                    := '0' --asynch in of DCM"
)
)
*80 (Net
uid 2029,0
decl (Decl
n "locked_status_o"
t "std_logic"
o 16
suid 42,0
)
declText (MLText
uid 2030,0
va (VaSet
font "Courier New,8,0"
)
xt "11000,-8400,26000,-7600"
st "locked_status_o : std_logic"
)
)
*81 (PortIoOut
uid 2037,0
shape (CompositeShape
uid 2038,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2039,0
sl 0
ro 270
xt "73500,32625,75000,33375"
)
(Line
uid 2040,0
sl 0
ro 270
xt "73000,33000,73500,33000"
pts [
"73000,33000"
"73500,33000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 2041,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2042,0
va (VaSet
font "arial,8,0"
)
xt "76000,32500,82100,33500"
st "locked_status_o"
blo "76000,33300"
tm "WireNameMgr"
)
)
)
*82 (Net
uid 2043,0
decl (Decl
n "ready_status_o"
t "std_logic"
o 17
suid 43,0
)
declText (MLText
uid 2044,0
va (VaSet
font "Courier New,8,0"
)
xt "11000,-6800,26000,-6000"
st "ready_status_o  : std_logic"
)
)
*83 (PortIoOut
uid 2051,0
shape (CompositeShape
uid 2052,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2053,0
sl 0
ro 270
xt "73500,33625,75000,34375"
)
(Line
uid 2054,0
sl 0
ro 270
xt "73000,34000,73500,34000"
pts [
"73000,34000"
"73500,34000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 2055,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2056,0
va (VaSet
font "arial,8,0"
)
xt "76000,33500,81800,34500"
st "ready_status_o"
blo "76000,34300"
tm "WireNameMgr"
)
)
)
*84 (Wire
uid 163,0
shape (OrthoPolyLine
uid 164,0
va (VaSet
vasetType 3
)
xt "10000,14000,16250,14000"
pts [
"10000,14000"
"16250,14000"
]
)
start &12
end &25
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 167,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 168,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "11000,13000,12900,14000"
st "CLK"
blo "11000,13800"
tm "WireNameMgr"
)
)
on &17
)
*85 (Wire
uid 191,0
shape (OrthoPolyLine
uid 192,0
va (VaSet
vasetType 3
)
xt "32750,16000,39000,16000"
pts [
"32750,16000"
"39000,16000"
]
)
start &28
end &13
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 195,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 196,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "34000,15000,37100,16000"
st "CLK_50"
blo "34000,15800"
tm "WireNameMgr"
)
)
on &15
)
*86 (Wire
uid 209,0
optionalChildren [
*87 (BdJunction
uid 233,0
ps "OnConnectorStrategy"
shape (Circle
uid 234,0
va (VaSet
vasetType 1
)
xt "35600,13600,36400,14400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 210,0
va (VaSet
vasetType 3
)
xt "32750,14000,39000,14000"
pts [
"32750,14000"
"39000,14000"
]
)
start &26
end &14
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 213,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 214,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "34000,13000,37100,14000"
st "CLK_25"
blo "34000,13800"
tm "WireNameMgr"
)
)
on &16
)
*88 (Wire
uid 229,0
shape (OrthoPolyLine
uid 230,0
va (VaSet
vasetType 3
)
xt "36000,11000,52250,14000"
pts [
"36000,14000"
"36000,11000"
"52250,11000"
]
)
start &87
end &19
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 231,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 232,0
va (VaSet
font "arial,8,0"
)
xt "49000,10000,52100,11000"
st "CLK_25"
blo "49000,10800"
tm "WireNameMgr"
)
)
on &16
)
*89 (Wire
uid 526,0
shape (OrthoPolyLine
uid 527,0
va (VaSet
vasetType 3
)
xt "10000,13000,68000,32000"
pts [
"64750,13000"
"68000,13000"
"68000,22000"
"10000,22000"
"10000,32000"
"13250,32000"
]
)
start &20
end &33
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 528,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 529,0
va (VaSet
font "arial,8,0"
)
xt "8750,31000,13150,32000"
st "CLK0_OUT"
blo "8750,31800"
tm "WireNameMgr"
)
)
on &44
)
*90 (Wire
uid 532,0
shape (OrthoPolyLine
uid 533,0
va (VaSet
vasetType 3
)
xt "3000,33000,67000,46000"
pts [
"64750,38000"
"67000,38000"
"67000,46000"
"3000,46000"
"3000,33000"
"13250,33000"
]
)
start &52
end &34
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 536,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 537,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "66750,37000,70850,38000"
st "PSCLK_IN"
blo "66750,37800"
tm "WireNameMgr"
)
)
on &45
)
*91 (Wire
uid 546,0
shape (OrthoPolyLine
uid 547,0
va (VaSet
vasetType 3
)
xt "4000,34000,66000,45000"
pts [
"64750,39000"
"66000,39000"
"66000,45000"
"4000,45000"
"4000,34000"
"13250,34000"
]
)
start &53
end &35
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 550,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 551,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "66750,38000,70450,39000"
st "PSEN_IN"
blo "66750,38800"
tm "WireNameMgr"
)
)
on &46
)
*92 (Wire
uid 588,0
shape (OrthoPolyLine
uid 589,0
va (VaSet
vasetType 3
)
xt "29750,34000,37250,34000"
pts [
"29750,34000"
"37250,34000"
]
)
start &39
end &55
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 592,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 593,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "31750,33000,37950,34000"
st "PSDONE_OUT"
blo "31750,33800"
tm "WireNameMgr"
)
)
on &48
)
*93 (Wire
uid 602,0
shape (OrthoPolyLine
uid 603,0
va (VaSet
vasetType 3
)
xt "29750,33000,37250,33000"
pts [
"29750,33000"
"37250,33000"
]
)
start &38
end &56
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 606,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 607,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "31750,32000,37850,33000"
st "LOCKED_OUT"
blo "31750,32800"
tm "WireNameMgr"
)
)
on &49
)
*94 (Wire
uid 841,0
shape (OrthoPolyLine
uid 842,0
va (VaSet
vasetType 3
)
xt "5000,35000,64750,44000"
pts [
"64750,40000"
"64750,44000"
"5000,44000"
"5000,35000"
"13250,35000"
]
)
start &54
end &36
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 843,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 844,0
ro 270
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "27000,39900,28000,46000"
st "PSINCDEC_IN"
blo "27800,46000"
tm "WireNameMgr"
)
)
on &47
)
*95 (Wire
uid 1254,0
shape (OrthoPolyLine
uid 1255,0
va (VaSet
vasetType 3
)
xt "29750,32000,30000,32000"
pts [
"29750,32000"
"30000,32000"
]
)
start &37
end &69
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1258,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1259,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "31750,31000,36250,32000"
st "CLK_25_PS"
blo "31750,31800"
tm "WireNameMgr"
)
)
on &70
)
*96 (Wire
uid 1272,0
shape (OrthoPolyLine
uid 1273,0
va (VaSet
vasetType 3
)
xt "35000,39000,37250,39000"
pts [
"35000,39000"
"37250,39000"
]
)
start &71
end &57
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1276,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1277,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "37000,38000,40000,39000"
st "do_shift"
blo "37000,38800"
tm "WireNameMgr"
)
)
on &72
)
*97 (Wire
uid 1286,0
shape (OrthoPolyLine
uid 1287,0
va (VaSet
vasetType 3
)
xt "35000,40000,37250,40000"
pts [
"35000,40000"
"37250,40000"
]
)
start &73
end &58
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1290,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1291,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "37000,40000,40300,41000"
st "direction"
blo "37000,40800"
tm "WireNameMgr"
)
)
on &74
)
*98 (Wire
uid 1458,0
shape (OrthoPolyLine
uid 1459,0
va (VaSet
vasetType 3
)
xt "31000,29000,37250,29000"
pts [
"31000,29000"
"37250,29000"
]
)
end &51
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1460,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1461,0
va (VaSet
font "arial,8,0"
)
xt "32250,28000,36650,29000"
st "CLK0_OUT"
blo "32250,28800"
tm "WireNameMgr"
)
)
on &44
)
*99 (Wire
uid 1493,0
shape (OrthoPolyLine
uid 1494,0
va (VaSet
vasetType 3
)
xt "35000,42000,37250,42000"
pts [
"35000,42000"
"37250,42000"
]
)
start &76
end &63
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1497,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1498,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "36000,41000,39200,42000"
st "RST_IN"
blo "36000,41800"
tm "WireNameMgr"
)
)
on &75
)
*100 (Wire
uid 1609,0
shape (OrthoPolyLine
uid 1610,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "64750,32000,73000,32000"
pts [
"64750,32000"
"73000,32000"
]
)
start &61
end &78
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1613,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1614,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "66000,31000,68200,32000"
st "offset"
blo "66000,31800"
tm "WireNameMgr"
)
)
on &77
)
*101 (Wire
uid 1981,0
shape (OrthoPolyLine
uid 1982,0
va (VaSet
vasetType 3
)
xt "8000,36000,37250,41000"
pts [
"37250,41000"
"8000,41000"
"8000,36000"
"13250,36000"
]
)
start &62
end &40
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1983,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1984,0
va (VaSet
font "arial,8,0"
)
xt "35250,40000,36550,41000"
st "rst"
blo "35250,40800"
tm "WireNameMgr"
)
)
on &79
)
*102 (Wire
uid 2031,0
shape (OrthoPolyLine
uid 2032,0
va (VaSet
vasetType 3
)
xt "64750,33000,73000,33000"
pts [
"64750,33000"
"73000,33000"
]
)
start &64
end &81
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2035,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2036,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "66000,32000,72100,33000"
st "locked_status_o"
blo "66000,32800"
tm "WireNameMgr"
)
)
on &80
)
*103 (Wire
uid 2045,0
shape (OrthoPolyLine
uid 2046,0
va (VaSet
vasetType 3
)
xt "64750,34000,73000,34000"
pts [
"64750,34000"
"73000,34000"
]
)
start &65
end &83
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2049,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2050,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "66000,33000,71800,34000"
st "ready_status_o"
blo "66000,33800"
tm "WireNameMgr"
)
)
on &82
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *104 (PackageList
uid 41,0
stg "VerticalLayoutStrategy"
textVec [
*105 (Text
uid 42,0
va (VaSet
font "arial,8,1"
)
xt "0,0,5400,1000"
st "Package List"
blo "0,800"
)
*106 (MLText
uid 43,0
va (VaSet
font "arial,8,0"
)
xt "0,1000,14500,9000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;
LIBRARY UNISIM;
--USE UNISIM.Vcomponents.all;
LIBRARY FACT_FAD_lib;
USE FACT_FAD_lib.fad_definitions.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 44,0
stg "VerticalLayoutStrategy"
textVec [
*107 (Text
uid 45,0
va (VaSet
isHidden 1
font "arial,8,1"
)
xt "20000,0,28100,1000"
st "Compiler Directives"
blo "20000,800"
)
*108 (Text
uid 46,0
va (VaSet
isHidden 1
font "arial,8,1"
)
xt "20000,1000,29600,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*109 (MLText
uid 47,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "20000,2000,27500,4000"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*110 (Text
uid 48,0
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visOptions (mwParamsVisibilityOptions
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iconMaskName "UnknownFile.msk"
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portVis (PortSigDisplay
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ga (GenericAssociation
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text (MLText
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tm "HdlTextNumberMgr"
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)
)
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va (VaSet
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vasetType 1
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xt "-400,-400,400,400"
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xt "-2000,-375,-500,375"
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tm "WireNameMgr"
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defaultPortIoOut (PortIoOut
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ro 270
xt "500,-375,2000,375"
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ro 270
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stg "STSignalDisplayStrategy"
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tm "WireNameMgr"
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defaultPortIoInOut (PortIoInOut
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va (VaSet
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fg "0,0,32768"
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xt "500,-375,2000,375"
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(Line
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xt "0,0,500,0"
pts [
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tg (WTG
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tm "WireNameMgr"
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defaultPortIoBuffer (PortIoBuffer
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lineColor "0,0,32768"
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optionalChildren [
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xt "500,-375,2000,375"
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(Line
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xt "0,0,500,0"
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]
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tg (WTG
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tm "WireNameMgr"
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)
)
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shape (OrthoPolyLine
va (VaSet
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es 0
sat 32
eat 32
st 0
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si 0
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xt "0,0,1900,1000"
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tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
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)
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es 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
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tm "WireNameMgr"
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)
)
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ss 0
es 0
sat 32
eat 32
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tm "BundleNameMgr"
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tm "BundleContentsMgr"
)
)
bundleNet &0
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fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,10000,12000"
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portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
font "arial,8,0"
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)
second (MLText
va (VaSet
font "arial,8,0"
)
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
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vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 3
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va (VaSet
font "arial,8,0"
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xt "0,-1100,12600,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
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va (VaSet
vasetType 1
fg "65535,65535,65535"
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xt "50,50,1250,1450"
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num (Text
va (VaSet
font "arial,8,0"
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xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
font "arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*132 (MLText
va (VaSet
font "arial,8,0"
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
font "arial,8,0"
)
xt "0,-1100,7400,-100"
st "b0: BLOCK (guard)"
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)
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shape (Rectangle
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vasetType 1
fg "65535,65535,65535"
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xt "50,50,1250,1450"
)
num (Text
va (VaSet
font "arial,8,0"
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xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
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)
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stg "VerticalLayoutStrategy"
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xt "14100,20000,22000,21000"
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va (VaSet
font "arial,8,0"
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xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
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]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
font "arial,8,0"
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xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
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va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
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tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
font "arial,8,0"
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xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
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)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
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uid 2,0
va (VaSet
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xt "9000,-16000,14400,-15000"
st "Declarations"
blo "9000,-15200"
)
portLabel (Text
uid 3,0
va (VaSet
font "arial,8,1"
)
xt "9000,-15000,11700,-14000"
st "Ports:"
blo "9000,-14200"
)
preUserLabel (Text
uid 4,0
va (VaSet
isHidden 1
font "arial,8,1"
)
xt "9000,-16000,12800,-15000"
st "Pre User:"
blo "9000,-15200"
)
preUserText (MLText
uid 5,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "9000,-16000,9000,-16000"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
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xt "9000,-6000,16100,-5000"
st "Diagram Signals:"
blo "9000,-5200"
)
postUserLabel (Text
uid 7,0
va (VaSet
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font "arial,8,1"
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xt "9000,-16000,13700,-15000"
st "Post User:"
blo "9000,-15200"
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postUserText (MLText
uid 8,0
va (VaSet
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font "Courier New,8,0"
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xt "9000,-16000,9000,-16000"
tm "BdDeclarativeTextMgr"
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commonDM (CommonDM
ldm (LogicalDM
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usingSuid 1
emptyRow *135 (LEmptyRow
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uid 54,0
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*137 (TitleRowHdr
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*138 (FilterRowHdr
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*139 (RefLabelColHdr
tm "RefLabelColHdrMgr"
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*140 (RowExpandColHdr
tm "RowExpandColHdrMgr"
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*141 (GroupColHdr
tm "GroupColHdrMgr"
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*142 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
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*143 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
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*144 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
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*145 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
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*146 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
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*147 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
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m 1
decl (Decl
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t "std_logic"
o 3
suid 9,0
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uid 237,0
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port (LogicalPort
m 1
decl (Decl
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t "std_logic"
o 2
suid 10,0
)
)
uid 239,0
)
*150 (LeafLogPort
port (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 13,0
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)
uid 295,0
)
*151 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
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o 14
suid 14,0
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uid 614,0
)
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port (LogicalPort
m 4
decl (Decl
n "PSCLK_IN"
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o 16
suid 15,0
)
)
uid 616,0
)
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port (LogicalPort
m 4
decl (Decl
n "PSEN_IN"
t "std_logic"
o 18
suid 16,0
)
)
uid 618,0
)
*154 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "PSINCDEC_IN"
t "std_logic"
o 19
suid 17,0
)
)
uid 620,0
)
*155 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "PSDONE_OUT"
t "std_logic"
o 17
suid 19,0
)
)
uid 624,0
)
*156 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "LOCKED_OUT"
t "std_logic"
o 15
suid 20,0
)
)
uid 626,0
)
*157 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 22
suid 34,0
)
)
uid 1246,0
scheme 0
)
*158 (LeafLogPort
port (LogicalPort
decl (Decl
n "do_shift"
t "std_logic"
o 23
suid 35,0
)
)
uid 1262,0
scheme 0
)
*159 (LeafLogPort
port (LogicalPort
decl (Decl
n "direction"
t "std_logic"
o 24
suid 36,0
)
)
uid 1264,0
scheme 0
)
*160 (LeafLogPort
port (LogicalPort
decl (Decl
n "RST_IN"
t "std_logic"
o 22
suid 37,0
)
)
uid 1505,0
)
*161 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "offset"
t "std_logic_vector"
b "(7 DOWNTO 0)"
preAdd 0
posAdd 0
o 14
suid 39,0
i "(OTHERS => '0')"
)
)
uid 1631,0
)
*162 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "rst"
t "std_logic"
eolc "--asynch in of DCM"
posAdd 0
o 15
suid 40,0
i "'0'"
)
)
uid 1985,0
)
*163 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "locked_status_o"
t "std_logic"
o 16
suid 42,0
)
)
uid 2057,0
)
*164 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "ready_status_o"
t "std_logic"
o 17
suid 43,0
)
)
uid 2059,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 67,0
optionalChildren [
*165 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *166 (MRCItem
litem &135
pos 17
dimension 20
)
uid 69,0
optionalChildren [
*167 (MRCItem
litem &136
pos 0
dimension 20
uid 70,0
)
*168 (MRCItem
litem &137
pos 1
dimension 23
uid 71,0
)
*169 (MRCItem
litem &138
pos 2
hidden 1
dimension 20
uid 72,0
)
*170 (MRCItem
litem &148
pos 0
dimension 20
uid 238,0
)
*171 (MRCItem
litem &149
pos 1
dimension 20
uid 240,0
)
*172 (MRCItem
litem &150
pos 2
dimension 20
uid 296,0
)
*173 (MRCItem
litem &151
pos 8
dimension 20
uid 615,0
)
*174 (MRCItem
litem &152
pos 3
dimension 20
uid 617,0
)
*175 (MRCItem
litem &153
pos 4
dimension 20
uid 619,0
)
*176 (MRCItem
litem &154
pos 5
dimension 20
uid 621,0
)
*177 (MRCItem
litem &155
pos 6
dimension 20
uid 625,0
)
*178 (MRCItem
litem &156
pos 7
dimension 20
uid 627,0
)
*179 (MRCItem
litem &157
pos 9
dimension 20
uid 1247,0
)
*180 (MRCItem
litem &158
pos 10
dimension 20
uid 1263,0
)
*181 (MRCItem
litem &159
pos 11
dimension 20
uid 1265,0
)
*182 (MRCItem
litem &160
pos 12
dimension 20
uid 1506,0
)
*183 (MRCItem
litem &161
pos 13
dimension 20
uid 1632,0
)
*184 (MRCItem
litem &162
pos 14
dimension 20
uid 1986,0
)
*185 (MRCItem
litem &163
pos 15
dimension 20
uid 2058,0
)
*186 (MRCItem
litem &164
pos 16
dimension 20
uid 2060,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 73,0
optionalChildren [
*187 (MRCItem
litem &139
pos 0
dimension 20
uid 74,0
)
*188 (MRCItem
litem &141
pos 1
dimension 50
uid 75,0
)
*189 (MRCItem
litem &142
pos 2
dimension 100
uid 76,0
)
*190 (MRCItem
litem &143
pos 3
dimension 50
uid 77,0
)
*191 (MRCItem
litem &144
pos 4
dimension 100
uid 78,0
)
*192 (MRCItem
litem &145
pos 5
dimension 100
uid 79,0
)
*193 (MRCItem
litem &146
pos 6
dimension 50
uid 80,0
)
*194 (MRCItem
litem &147
pos 7
dimension 80
uid 81,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 68,0
vaOverrides [
]
)
]
)
uid 53,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *195 (LEmptyRow
)
uid 83,0
optionalChildren [
*196 (RefLabelRowHdr
)
*197 (TitleRowHdr
)
*198 (FilterRowHdr
)
*199 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*200 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*201 (GroupColHdr
tm "GroupColHdrMgr"
)
*202 (NameColHdr
tm "GenericNameColHdrMgr"
)
*203 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*204 (InitColHdr
tm "GenericValueColHdrMgr"
)
*205 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*206 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 95,0
optionalChildren [
*207 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *208 (MRCItem
litem &195
pos 0
dimension 20
)
uid 97,0
optionalChildren [
*209 (MRCItem
litem &196
pos 0
dimension 20
uid 98,0
)
*210 (MRCItem
litem &197
pos 1
dimension 23
uid 99,0
)
*211 (MRCItem
litem &198
pos 2
hidden 1
dimension 20
uid 100,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 101,0
optionalChildren [
*212 (MRCItem
litem &199
pos 0
dimension 20
uid 102,0
)
*213 (MRCItem
litem &201
pos 1
dimension 50
uid 103,0
)
*214 (MRCItem
litem &202
pos 2
dimension 100
uid 104,0
)
*215 (MRCItem
litem &203
pos 3
dimension 100
uid 105,0
)
*216 (MRCItem
litem &204
pos 4
dimension 50
uid 106,0
)
*217 (MRCItem
litem &205
pos 5
dimension 50
uid 107,0
)
*218 (MRCItem
litem &206
pos 6
dimension 80
uid 108,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 96,0
vaOverrides [
]
)
]
)
uid 82,0
type 1
)
activeModelName "BlockDiag"
)