DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "std_logic_arith"
)
]
libraryRefs [
"ieee"
]
)
version "24.1"
appVersion "2009.2 (Build 10)"
model (Symbol
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ldm (LogicalDM
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tm "NameColHdrMgr"
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*11 (BoundsColHdr
tm "BoundsColHdrMgr"
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*13 (EolColHdr
tm "EolColHdrMgr"
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n "CLK_50"
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suid 6,0
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port (LogicalPort
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t "std_logic"
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suid 24,0
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*18 (LogPort
port (LogicalPort
decl (Decl
n "do_shift"
t "std_logic"
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suid 25,0
)
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port (LogicalPort
decl (Decl
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suid 26,0
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t "std_logic"
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port (LogicalPort
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decl (Decl
n "offset"
t "std_logic_vector"
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o 9
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i "(OTHERS => '0')"
)
)
uid 946,0
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port (LogicalPort
m 1
decl (Decl
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t "std_logic"
o 8
suid 29,0
)
)
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)
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port (LogicalPort
m 1
decl (Decl
n "ready_status_o"
t "std_logic"
o 10
suid 30,0
)
)
uid 1140,0
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fixedCol 4
fixedRow 2
name "Ports"
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vaOverrides [
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genericsCommonDM (CommonDM
ldm (LogicalDM
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*52 (RowExpandColHdr
tm "RowExpandColHdrMgr"
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*53 (GroupColHdr
tm "GroupColHdrMgr"
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tm "GenericNameColHdrMgr"
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tm "GenericTypeColHdrMgr"
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*56 (InitColHdr
tm "GenericValueColHdrMgr"
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*57 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
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cellVa (MVa
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groupVa (MVa
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pos 5
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fixedCol 3
fixedRow 2
name "Ports"
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vaOverrides [
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uid 81,0
type 1
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VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\clock_generator_var_ps\\symbol.sb.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\clock_generator_var_ps\\symbol.sb.user"
)
(vvPair
variable "SourceDir"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "symbol"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\clock_generator_var_ps"
)
(vvPair
variable "d_logical"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\clock_generator_var_ps"
)
(vvPair
variable "date"
value "02.08.2011"
)
(vvPair
variable "day"
value "Di"
)
(vvPair
variable "day_long"
value "Dienstag"
)
(vvPair
variable "dd"
value "02"
)
(vvPair
variable "entity_name"
value "clock_generator_var_ps"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "symbol.sb"
)
(vvPair
variable "f_logical"
value "symbol.sb"
)
(vvPair
variable "f_noext"
value "symbol"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "E5B-LABOR6"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_lib"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/work"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "mm"
value "08"
)
(vvPair
variable "module_name"
value "clock_generator_var_ps"
)
(vvPair
variable "month"
value "Aug"
)
(vvPair
variable "month_long"
value "August"
)
(vvPair
variable "p"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\clock_generator_var_ps\\symbol.sb"
)
(vvPair
variable "p_logical"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\clock_generator_var_ps\\symbol.sb"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "C:\\modeltech_6.6a\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "sb"
)
(vvPair
variable "this_file"
value "symbol"
)
(vvPair
variable "this_file_logical"
value "symbol"
)
(vvPair
variable "time"
value "14:40:19"
)
(vvPair
variable "unit"
value "clock_generator_var_ps"
)
(vvPair
variable "user"
value "dneise"
)
(vvPair
variable "version"
value "2009.2 (Build 10)"
)
(vvPair
variable "view"
value "symbol"
)
(vvPair
variable "year"
value "2011"
)
(vvPair
variable "yy"
value "11"
)
]
)
LanguageMgr "VhdlLangMgr"
uid 51,0
optionalChildren [
*71 (SymbolBody
uid 8,0
optionalChildren [
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uid 121,0
ps "OnEdgeStrategy"
shape (Triangle
uid 122,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46000,10625,46750,11375"
)
tg (CPTG
uid 123,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 124,0
va (VaSet
font "arial,8,0"
)
xt "41900,10500,45000,11500"
st "CLK_50"
ju 2
blo "45000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 125,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6800,64000,7600"
st "CLK_50          : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_50"
t "std_logic"
o 7
suid 2,0
)
)
)
*73 (CptPort
uid 126,0
ps "OnEdgeStrategy"
shape (Triangle
uid 127,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46000,11625,46750,12375"
)
tg (CPTG
uid 128,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 129,0
va (VaSet
font "arial,8,0"
)
xt "41900,11500,45000,12500"
st "CLK_25"
ju 2
blo "45000,12300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 130,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,5200,64000,6000"
st "CLK_25          : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_25"
t "std_logic"
o 5
suid 3,0
)
)
)
*74 (CptPort
uid 168,0
ps "OnEdgeStrategy"
shape (Triangle
uid 169,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27250,10625,28000,11375"
)
tg (CPTG
uid 170,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 171,0
va (VaSet
font "arial,8,0"
)
xt "29000,10500,30900,11500"
st "CLK"
blo "29000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 172,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2000,64000,2800"
st "CLK             : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 6,0
)
)
)
*75 (CptPort
uid 643,0
ps "OnEdgeStrategy"
shape (Triangle
uid 644,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46000,33625,46750,34375"
)
tg (CPTG
uid 645,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 646,0
va (VaSet
font "arial,8,0"
)
xt "40500,33500,45000,34500"
st "CLK_25_PS"
ju 2
blo "45000,34300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 647,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6000,64000,6800"
st "CLK_25_PS       : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 6
suid 24,0
)
)
)
*76 (CptPort
uid 698,0
ps "OnEdgeStrategy"
shape (Triangle
uid 699,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27250,12625,28000,13375"
)
tg (CPTG
uid 700,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 701,0
va (VaSet
font "arial,8,0"
)
xt "29000,12500,32000,13500"
st "do_shift"
blo "29000,13300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 702,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4400,64000,5200"
st "do_shift        : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "do_shift"
t "std_logic"
o 4
suid 25,0
)
)
)
*77 (CptPort
uid 703,0
ps "OnEdgeStrategy"
shape (Triangle
uid 704,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27250,14625,28000,15375"
)
tg (CPTG
uid 705,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 706,0
va (VaSet
font "arial,8,0"
)
xt "29000,14500,32300,15500"
st "direction"
blo "29000,15300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 707,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,3600,64000,4400"
st "direction       : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "direction"
t "std_logic"
o 3
suid 26,0
)
)
)
*78 (CptPort
uid 848,0
ps "OnEdgeStrategy"
shape (Triangle
uid 849,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27250,16625,28000,17375"
)
tg (CPTG
uid 850,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 851,0
va (VaSet
font "arial,8,0"
)
xt "29000,16500,32200,17500"
st "RST_IN"
blo "29000,17300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 852,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2800,64000,3600"
st "RST_IN          : IN     std_logic  ;"
)
thePort (LogicalPort
decl (Decl
n "RST_IN"
t "std_logic"
o 2
suid 27,0
)
)
)
*79 (CptPort
uid 947,0
ps "OnEdgeStrategy"
shape (Triangle
uid 948,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46000,35625,46750,36375"
)
tg (CPTG
uid 949,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 950,0
va (VaSet
font "arial,8,0"
)
xt "40200,35500,45000,36500"
st "offset : (7:0)"
ju 2
blo "45000,36300"
tm "CptPortNameMgr"
)
t (Text
uid 951,0
va (VaSet
font "arial,8,0"
)
xt "38100,36500,45000,37500"
st "(OTHERS => '0')"
ju 2
blo "45000,37300"
tm "InitValueDelayMgr"
)
)
dt (MLText
uid 952,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,8400,83500,9200"
st "offset          : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "offset"
t "std_logic_vector"
b "(7 DOWNTO 0)"
preAdd 0
posAdd 0
o 9
suid 28,0
i "(OTHERS => '0')"
)
)
)
*80 (CptPort
uid 1141,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1142,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46000,37625,46750,38375"
)
tg (CPTG
uid 1143,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1144,0
va (VaSet
font "arial,8,0"
)
xt "38900,37500,45000,38500"
st "locked_status_o"
ju 2
blo "45000,38300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1145,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,7600,64000,8400"
st "locked_status_o : OUT    std_logic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "locked_status_o"
t "std_logic"
o 8
suid 29,0
)
)
)
*81 (CptPort
uid 1146,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1147,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46000,39625,46750,40375"
)
tg (CPTG
uid 1148,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1149,0
va (VaSet
font "arial,8,0"
)
xt "39200,39500,45000,40500"
st "ready_status_o"
ju 2
blo "45000,40300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1150,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,9200,63000,10000"
st "ready_status_o  : OUT    std_logic "
)
thePort (LogicalPort
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