--------------------------------------------------------------------------------
-- Company:       IPP
-- Engineer:      Patrick Vogler
--
-- Create Date:   10:06:23 05/27/2011
-- Design Name:   
-- Module Name:   /home/pavogler/ISDC_repos/firmware/FTM/Lightpulser_interface/Basic_Version//FM_Pulse_generator_Basic_tb.vhd
-- Project Name:  Lightpulser_Basic
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: FM_pulse_generator_Basic
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY FM_Pulse_generator_Basic_tb IS
END FM_Pulse_generator_Basic_tb;
 
ARCHITECTURE behavior OF FM_Pulse_generator_Basic_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT FM_pulse_generator_Basic
    PORT(
         clk : IN  std_logic;
         pulse_freq : IN  std_logic_vector(5 downto 0);
         FM_out : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal pulse_freq : std_logic_vector(5 downto 0) := (others => '0');

 	--Outputs
   signal FM_out : std_logic;

   -- Clock period definitions
   constant clk_period : time := 20 ns;  -- 50MHz Clock
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: FM_pulse_generator_Basic PORT MAP (
          clk => clk,
          pulse_freq => pulse_freq,
          FM_out => FM_out
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ms.
--      wait for 100 ms;	

      wait for clk_period*10;

      -- insert stimulus here

      pulse_freq <= "000000";
      wait for clk_period*15000;
      pulse_freq <= "001000";
      wait for clk_period*15000;
      pulse_freq <= "111111";

      wait;
   end process;

END;