source: FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd.bak@ 692

Last change on this file since 692 was 260, checked in by dneise, 14 years ago
possible to switch off SPI SCLK now. see new revision of simple_daq in tools/FAD/
File size: 26.9 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 11:48:48 11/10/2009
6-- Design Name:
7-- Module Name: w5300_modul - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24library FACT_FAD_lib;
25use FACT_FAD_lib.fad_definitions.ALL;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32ENTITY w5300_modul IS
33 generic(
34 RAM_ADDR_WIDTH : integer := 14
35 );
36 PORT(
37 clk : IN std_logic;
38 wiz_reset : OUT std_logic := '1';
39 addr : OUT std_logic_vector (9 DOWNTO 0);
40 data : INOUT std_logic_vector (15 DOWNTO 0);
41 cs : OUT std_logic := '1';
42 wr : OUT std_logic := '1';
43 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
44 rd : OUT std_logic := '1';
45 int : IN std_logic;
46 write_length : IN std_logic_vector (16 DOWNTO 0);
47 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
48 ram_data : IN std_logic_vector (15 DOWNTO 0);
49 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
50 data_valid : IN std_logic;
51 data_valid_ack : OUT std_logic := '0';
52 busy : OUT std_logic := '1';
53 write_header_flag, write_end_flag : IN std_logic;
54 fifo_channels : IN std_logic_vector (3 downto 0);
55 s_trigger : OUT std_logic := '0';
56 new_config : OUT std_logic := '0';
57 config_started : in std_logic;
58 config_addr : out std_logic_vector (7 downto 0);
59 config_data : inout std_logic_vector (15 downto 0) := (others => 'Z');
60 config_wr_en : out std_logic := '0';
61 config_rd_en : out std_logic := '0';
62 config_busy : in std_logic;
63
64
65
66 denable : out std_logic := '0'; -- default domino wave off
67 dwrite_enable : out std_logic := '0'; -- default DWRITE low.
68 sclk_enable : out std_logic := '1' -- default DWRITE HIGH.
69 );
70
71-- Declarations
72
73END w5300_modul ;
74
75architecture Behavioral of w5300_modul is
76
77type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
78 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
79 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, CHK_RECEIVED, READ_DATA);
80type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
81 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3);
82type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
83type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
84type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END);
85
86signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
87
88signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0');
89signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0');
90signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0');
91signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
92
93signal state_init, next_state , next_state_tmp : state_init_type := RESET;
94signal count : std_logic_vector (2 downto 0) := "000";
95signal state_write : state_write_type := WR_START;
96signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
97signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
98signal state_read_data : state_read_data_type := RD_1;
99
100signal interrupt_ignore : std_logic := '1';
101signal int_flag : std_logic := '0';
102signal ram_access : std_logic := '0';
103
104signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0');
105signal data_cnt : integer := 0;
106signal drs_cnt : integer :=0;
107signal channel_cnt : integer range 0 to 9 :=0;
108signal socket_cnt : std_logic_vector (2 downto 0) := "000";
109signal roi_max : std_logic_vector (10 downto 0);
110signal data_end : integer := 0;
111
112signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
113signal write_length_bytes : std_logic_vector (16 downto 0);
114
115signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
116signal chk_recv_cntr : integer range 0 to 10000 := 0;
117signal rx_packets_cnt : std_logic_vector (15 downto 0);
118signal next_packet_data : std_logic := '0';
119signal new_config_flag : std_logic := '0';
120
121signal trigger_stop : std_logic := '1';
122
123signal local_write_length : std_logic_vector (16 DOWNTO 0);
124signal local_ram_start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
125signal local_ram_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
126signal local_socket_nr : std_logic_vector (2 DOWNTO 0);
127signal local_write_header_flag, local_write_end_flag : std_logic;
128signal local_fifo_channels : std_logic_vector (3 downto 0);
129
130begin
131
132 --synthesis translate_off
133 RST_TIME <= X"00120";
134 --synthesis translate_on
135
136 w5300_init_proc : process (clk, int)
137 begin
138
139 if rising_edge (clk) then
140
141 -- Interrupt low
142 if (int = '0') and (interrupt_ignore = '0') then
143 case state_interrupt_1 is
144 when IR1_01 =>
145 int_flag <= '1';
146 busy <= '1';
147 state_interrupt_1 <= IR1_02;
148 when IR1_02 =>
149 state_interrupt_1 <= IR1_03;
150 when IR1_03 =>
151 state_init <= INTERRUPT;
152 socket_cnt <= "000";
153 ram_access <= '0';
154 zaehler <= X"00000";
155 count <= "000";
156 int_flag <= '0';
157 interrupt_ignore <= '1';
158 state_interrupt_1 <= IR1_04;
159 when others =>
160 null;
161 end case;
162 end if; -- int = '0'
163
164 if int_flag = '0' then
165 case state_init is
166 -- Interrupt
167 when INTERRUPT =>
168 case state_interrupt_2 is
169 when IR2_01 =>
170 par_addr <= W5300_IR;
171 state_init <= READ_REG;
172 next_state <= INTERRUPT;
173 state_interrupt_2 <= IR2_02;
174 when IR2_02 =>
175 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
176 state_interrupt_2 <= IR2_03;
177 else
178 socket_cnt <= socket_cnt + 1;
179 if (socket_cnt = 7) then
180 state_interrupt_2 <= IR2_06;
181 else
182 state_interrupt_2 <= IR2_02;
183 end if;
184 end if;
185 when IR2_03 =>
186 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
187 state_init <= READ_REG;
188 next_state <= INTERRUPT;
189 state_interrupt_2 <= IR2_04;
190 when IR2_04 =>
191 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
192 par_data <= data_read; -- clear Interrupts
193 state_init <= WRITE_REG;
194 next_state <= INTERRUPT;
195 state_interrupt_2 <= IR2_05;
196 when IR2_05 =>
197 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
198 par_data <= X"0010"; -- CLOSE
199 state_init <= WRITE_REG;
200 next_state <= INTERRUPT;
201 socket_cnt <= socket_cnt + 1;
202 if (socket_cnt = 7) then
203 state_interrupt_2 <= IR2_06;
204 else
205 state_interrupt_2 <= IR2_01;
206 end if;
207
208 when IR2_06 =>
209 state_interrupt_1 <= IR1_01;
210 state_interrupt_2 <= IR2_01;
211 socket_cnt <= "000";
212 state_init <= RESET;
213 end case;
214
215 -- reset W5300
216 when RESET =>
217 zaehler <= zaehler + 1;
218 wiz_reset <= '0';
219 led <= X"FF";
220 if (zaehler >= X"00064") then -- wait 2µs
221 wiz_reset <= '1';
222 end if;
223 if (zaehler = RST_TIME) then -- wait 10ms
224 zaehler <= X"00000";
225 socket_cnt <= "000";
226 count <= "000";
227 ram_access <= '0';
228 interrupt_ignore <= '0';
229 rd <= '1';
230 wr <= '1';
231 cs <= '1';
232 state_write <= WR_START;
233 state_init <= INIT;
234 end if;
235
236 -- Init
237 when INIT =>
238 par_addr <= W5300_MR;
239 par_data <= X"0000";
240 state_init <= WRITE_REG;
241 next_state <= IM;
242
243 -- Interrupt Mask
244 when IM =>
245 par_addr <= W5300_IMR;
246 par_data <= X"00FF"; -- S0-S7 Interrupts
247 state_init <= WRITE_REG;
248 next_state <= MT;
249
250 -- Memory Type
251 when MT =>
252 par_addr <= W5300_MTYPER;
253 par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer
254 state_init <= WRITE_REG;
255 next_state <= STX;
256
257 -- Socket TX Memory Size
258 when STX =>
259 par_data <= X"0F0F"; -- 15K TX
260
261 par_addr <= W5300_TMS01R;
262 state_init <=WRITE_REG;
263 next_state <= STX1;
264 when STX1 =>
265 par_addr <= W5300_TMS23R;
266 state_init <=WRITE_REG;
267 next_state <= STX2;
268 when STX2 =>
269 par_addr <= W5300_TMS45R;
270 state_init <=WRITE_REG;
271 next_state <= STX3;
272 when STX3 =>
273 par_addr <= W5300_TMS67R;
274 state_init <=WRITE_REG;
275 next_state <= SRX;
276
277 -- Socket RX Memory Size
278 when SRX =>
279 par_data <= X"0101"; -- 1K RX
280
281 par_addr <= W5300_RMS01R;
282 state_init <=WRITE_REG;
283 next_state <= SRX1;
284 when SRX1 =>
285 par_addr <= W5300_RMS23R;
286 state_init <=WRITE_REG;
287 next_state <= SRX2;
288 when SRX2 =>
289 par_addr <= W5300_RMS45R;
290 state_init <=WRITE_REG;
291 next_state <= SRX3;
292 when SRX3 =>
293 par_addr <= W5300_RMS67R;
294 state_init <=WRITE_REG;
295 next_state <= MAC;
296
297 -- MAC
298 when MAC =>
299 par_addr <= W5300_SHAR;
300 par_data <= MAC_ADDRESS (0);
301 state_init <= WRITE_REG;
302 next_state <= MAC1;
303 when MAC1 =>
304 par_addr <= W5300_SHAR + 2;
305 par_data <= MAC_ADDRESS (1);
306 state_init <= WRITE_REG;
307 next_state <= MAC2;
308 when MAC2 =>
309 par_addr <= W5300_SHAR + 4;
310 par_data <= MAC_ADDRESS (2);
311 state_init <= WRITE_REG;
312 next_state <= GW;
313
314 -- Gateway
315 when GW =>
316 par_addr <= W5300_GAR;
317 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8);
318 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8);
319 state_init <= WRITE_REG;
320 next_state <= GW1;
321 when GW1 =>
322 par_addr <= W5300_GAR + 2;
323 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8);
324 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8);
325 state_init <= WRITE_REG;
326 next_state <= SNM;
327
328 -- Subnet Mask
329 when SNM =>
330 par_addr <= W5300_SUBR;
331 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8);
332 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8);
333 state_init <= WRITE_REG;
334 next_state <= SNM1;
335 when SNM1 =>
336 par_addr <= W5300_SUBR + 2;
337 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8);
338 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8);
339 state_init <= WRITE_REG;
340 next_state <= IP;
341 -- Own IP-Address
342 when IP =>
343 par_addr <= W5300_SIPR;
344 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8);
345 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8);
346 state_init <= WRITE_REG;
347 next_state <= IP1;
348 when IP1 =>
349 par_addr <= W5300_SIPR + 2;
350 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8);
351 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8);
352 state_init <= WRITE_REG;
353 next_state <= TIMEOUT;
354 when TIMEOUT =>
355 par_addr <= W5300_RTR;
356 par_data <= X"07D0"; -- 0x07D0 = 200ms
357 state_init <= WRITE_REG;
358 next_state <= RETRY;
359 when RETRY =>
360 par_addr <= W5300_RCR;
361 par_data <= X"0008";
362 state_init <= WRITE_REG;
363 next_state <= SI;
364
365 -- Socket Init
366 when SI =>
367 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
368 par_data <= X"0101"; -- ALIGN, TCP
369 state_init <= WRITE_REG;
370 next_state <= SI1;
371 -- Sx Interrupt Mask
372 when SI1 =>
373 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
374 par_data <= X"000A"; -- TIMEOUT, DISCON
375 state_init <= WRITE_REG;
376 next_state <= SI2;
377 when SI2 =>
378 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
379 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
380 state_init <= WRITE_REG;
381 next_state <= SI3;
382 when SI3 =>
383 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
384 par_data <= X"0001"; -- OPEN
385 state_init <= WRITE_REG;
386 next_state <= SI4;
387 when SI4 =>
388 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
389 state_init <= READ_REG;
390 next_state <= SI5;
391 when SI5 =>
392 if (data_read (7 downto 0) = X"13") then -- is open?
393 state_init <= SI6;
394 else
395 state_init <= SI4;
396 end if;
397 when SI6 =>
398 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
399 par_data <= X"0002"; -- LISTEN
400 state_init <= WRITE_REG;
401 socket_cnt <= socket_cnt + 1;
402 if (socket_cnt = 7) then
403 socket_cnt <= "000";
404 next_state <= ESTABLISH; -- All Sockets open
405 else
406 next_state <= SI; -- Next Socket
407 end if;
408 -- End Socket Init
409
410 when ESTABLISH =>
411 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
412 state_init <= READ_REG;
413 next_state <= EST1;
414 when EST1 =>
415 led <= data_read (7 downto 0);
416 case data_read (7 downto 0) is
417 when X"17" => -- established
418 if (socket_cnt = 7) then
419 socket_cnt <= "000";
420 busy <= '0';
421 state_init <= MAIN;
422 else
423 socket_cnt <= socket_cnt + 1;
424 state_init <= ESTABLISH;
425 end if;
426 when others =>
427 state_init <= ESTABLISH;
428 end case;
429
430 when CONFIG =>
431 led <= X"F0";
432 new_config <= '1';
433 if (config_started = '1') then
434 led <= X"0F";
435 new_config <= '0';
436 busy <= '0';
437 state_init <= MAIN;
438 end if;
439
440 -- main "loop"
441 when MAIN =>
442 if (trigger_stop = '1') then
443 s_trigger <= '0';
444 end if;
445 if (chk_recv_cntr = 1000) then
446 chk_recv_cntr <= 0;
447 state_read_data <= RD_1;
448 state_init <= READ_DATA;
449 busy <= '1';
450 else
451 busy <= '0';
452 data_valid_ack <= '0';
453 chk_recv_cntr <= chk_recv_cntr + 1;
454 if (data_valid = '1') then
455 data_valid_ack <= '1';
456 local_write_length <= write_length;
457 local_ram_start_addr <= ram_start_addr;
458 local_ram_addr <= (others => '0');
459 local_write_header_flag <= write_header_flag;
460 local_write_end_flag <= write_end_flag;
461 local_fifo_channels <= fifo_channels;
462 next_state <= MAIN;
463 state_init <= WRITE_DATA;
464 busy <= '1';
465 end if;
466 end if;
467
468 -- read data from socket 0
469 when READ_DATA =>
470 case state_read_data is
471 when RD_1 =>
472 par_addr <= W5300_S0_RX_RSR;
473 state_init <= READ_REG;
474 next_state <= READ_DATA;
475 state_read_data <= RD_2;
476 when RD_2 =>
477 socket_rx_received (31 downto 16) <= data_read;
478 par_addr <= W5300_S0_RX_RSR + X"2";
479 state_init <= READ_REG;
480 next_state <= READ_DATA;
481 state_read_data <= RD_3;
482 when RD_3 =>
483 socket_rx_received (15 downto 0) <= data_read;
484 state_read_data <= RD_4;
485 when RD_4 =>
486 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
487 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
488 state_read_data <= RD_5;
489 else
490 busy <= '0';
491 state_init <= MAIN;
492 end if;
493 when RD_5 =>
494 if (rx_packets_cnt > 0) then
495 rx_packets_cnt <= rx_packets_cnt - '1';
496 par_addr <= W5300_S0_RX_FIFOR;
497 state_init <= READ_REG;
498 next_state <= READ_DATA;
499 state_read_data <= RD_6;
500 else
501 state_read_data <= RD_END;
502-- if (new_config_flag = '1') then
503-- new_config_flag <= '0';
504-- state_init <= CONFIG;
505-- else
506-- busy <= '0';
507-- state_init <= MAIN;
508-- end if;
509 end if;
510 when RD_6 =>
511 led <= data_read (15 downto 8);
512 -- read command
513 if (next_packet_data = '0') then
514 case data_read (15 downto 8) is
515 when CMD_TRIGGER =>
516 trigger_stop <= '1';
517 s_trigger <= '1';
518 state_read_data <= RD_WAIT;
519 when CMD_DWRITE_RUN =>
520 dwrite_enable <= '1';
521 state_read_data <= RD_WAIT;
522 when CMD_DWRITE_STOP =>
523 dwrite_enable <= '0';
524 state_read_data <= RD_WAIT;
525 when CMD_DENABLE =>
526 denable <= '1';
527 state_read_data <= RD_WAIT;
528 when CMD_DDISABLE =>
529 denable <= '0';
530 state_read_data <= RD_WAIT;
531 when CMD_TRIGGER_C =>
532 trigger_stop <= '0';
533 s_trigger <= '1';
534 state_read_data <= RD_WAIT;
535 when CMD_TRIGGER_S =>
536 trigger_stop <= '1';
537 state_read_data <= RD_WAIT;
538 when CMD_WRITE =>
539 next_packet_data <= '1';
540 config_addr <= data_read (7 downto 0);
541 state_read_data <= RD_5;
542 when others =>
543 state_read_data <= RD_5;
544 end case;
545 -- read data
546 else
547 if (config_busy = '0') then
548 config_data <= data_read;
549 config_wr_en <= '1';
550 new_config_flag <= '1';
551 next_packet_data <= '0';
552 state_read_data <= RD_WAIT;
553 end if;
554 end if;
555 when RD_WAIT =>
556 state_read_data <= RD_WAIT1;
557 when RD_WAIT1 =>
558 config_data <= (others => 'Z');
559 config_wr_en <= '0';
560 state_read_data <= RD_5;
561 when RD_END =>
562 par_addr <= W5300_S0_CR;
563 par_data <= X"0040"; -- RECV
564 state_init <= WRITE_REG;
565 if (new_config_flag = '1') then
566 new_config_flag <= '0';
567 next_state <= CONFIG;
568 else
569-- busy <= '0';
570 next_state <= MAIN;
571 end if;
572
573 end case; -- state_data_read
574
575
576
577 when WRITE_DATA =>
578 case state_write is
579 when WR_START =>
580 if (local_write_header_flag = '1') then
581 ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ????
582 end if;
583 state_write <= WR_WAIT1;
584 when WR_WAIT1 =>
585 state_write <= WR_LENGTH;
586 when WR_LENGTH =>
587 if (local_write_header_flag = '1') then
588 local_socket_nr <= ram_data (2 downto 0);
589 end if;
590 next_state_tmp <= next_state;
591 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2)
592 data_cnt <= 0;
593 state_write <= WR_01;
594 -- Check FIFO Size
595 when WR_01 =>
596 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
597 state_init <= READ_REG;
598 next_state <= WRITE_DATA;
599 state_write <= WR_02;
600 when WR_02 =>
601 socket_tx_free (31 downto 16) <= data_read;
602 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
603 state_init <= READ_REG;
604 next_state <= WRITE_DATA;
605 state_write <= WR_03;
606 when WR_03 =>
607 socket_tx_free (15 downto 0) <= data_read;
608 state_write <= WR_04;
609 when WR_04 =>
610 if (socket_tx_free (16 downto 0) < write_length_bytes) then
611 state_write <= WR_01;
612 else
613 if (local_write_header_flag = '1') then
614 state_write <= WR_FIFO;
615 else
616 state_write <= WR_ADC;
617 end if;
618 end if;
619
620 -- Fill FIFO
621
622 -- Write Header
623 when WR_FIFO =>
624 ram_addr <= local_ram_start_addr + local_ram_addr;
625 state_write <= WR_FIFO1;
626 when WR_FIFO1 =>
627 data_cnt <= data_cnt + 1;
628 if (data_cnt < PACKAGE_HEADER_LENGTH) then --???
629 local_ram_addr <= local_ram_addr + 1;
630 if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words
631 local_ram_addr <= local_ram_addr + 2;
632 end if;
633 if (data_cnt = 9) then -- skip empty words
634 local_ram_addr <= local_ram_addr + 4;
635 end if;
636 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
637 ram_access <= '1';
638 state_init <= WRITE_REG;
639 next_state <= WRITE_DATA;
640 state_write <= WR_FIFO;
641 else
642 state_write <= WR_ADC;
643 end if;
644 -- End Write Header
645
646 -- Write ADC-Data
647 ---- Start...
648 when WR_ADC =>
649 adc_data_addr <= local_ram_start_addr + local_ram_addr;
650 drs_cnt <= 0;
651 channel_cnt <= 1;
652 data_cnt <= 0;
653 roi_max <= (others => '0');
654 data_end <= 3;
655 state_write <= WR_ADC1;
656
657 ---- Write Channel
658 when WR_ADC1 =>
659 -- read ROI and set end of Channel-Data
660 if (data_cnt = 3) then
661 data_end <= conv_integer (ram_data) + 3;
662 if (ram_data > roi_max) then
663 roi_max <= ram_data (10 downto 0);
664 end if;
665 end if;
666 ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4);
667 state_write <= WR_ADC2;
668 when WR_ADC2 =>
669 if (data_cnt < data_end) then
670 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
671 ram_access <= '1';
672 state_init <= WRITE_REG;
673 next_state <= WRITE_DATA;
674 data_cnt <= data_cnt + 1;
675 state_write <= WR_ADC1;
676 else
677 -- Next DRS
678 if (drs_cnt < 3) then
679 drs_cnt <= drs_cnt + 1;
680 data_cnt <= 0;
681 data_end <= 3;
682 state_write <= WR_ADC1;
683 else
684 -- Next Channel
685 if (channel_cnt < local_fifo_channels) then
686 channel_cnt <= channel_cnt + 1;
687 roi_max <= (others => '0');
688 drs_cnt <= 0;
689 data_cnt <= 0;
690 data_end <= 3;
691 adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
692 state_write <= WR_ADC1;
693 else
694 -- Ready
695 if (local_write_end_flag = '1') then
696 state_write <= WR_ENDFLAG;
697 else
698 state_write <= WR_05;
699 end if;
700 end if;
701 end if;
702 end if;
703 -- End Write ADC-Data
704
705 -- Write End Package Flag
706 when WR_ENDFLAG =>
707 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
708 state_write <= WR_ENDFLAG1;
709 when WR_ENDFLAG1 =>
710 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
711 ram_access <= '1';
712 state_init <= WRITE_REG;
713 next_state <= WRITE_DATA;
714 state_write <= WR_ENDFLAG2;
715 when WR_ENDFLAG2 =>
716 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1;
717 state_write <= WR_ENDFLAG3;
718 when WR_ENDFLAG3 =>
719 state_init <= WRITE_REG;
720 next_state <= WRITE_DATA;
721 state_write <= WR_05;
722
723 -- End Write End Package Flag
724
725 --Send FIFO
726 when WR_05 =>
727 ram_access <= '0';
728 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
729 par_data <= (0 => write_length_bytes (16), others => '0');
730 state_init <= WRITE_REG;
731 state_write <= WR_06;
732 when WR_06 =>
733 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
734 par_data <= write_length_bytes (15 downto 0);
735 state_init <= WRITE_REG;
736 state_write <= WR_07;
737 when WR_07 =>
738 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
739 par_data <= X"0020"; -- Send
740 state_init <= WRITE_REG;
741 state_write <= WR_08;
742 when others =>
743-- busy <= '0';
744 state_init <= next_state_tmp;
745 state_write <= WR_START;
746 end case;
747 -- End WRITE_DATA
748
749 when READ_REG =>
750 case count is
751 when "000" =>
752 cs <= '0';
753 rd <= '0';
754 wr <= '1';
755 data <= (others => 'Z'); -- !!!!!!!!!!
756 count <= "001";
757 addr <= par_addr;
758 when "001" =>
759 count <= "010";
760 when "010" =>
761 count <= "100";
762 when "100" =>
763 data_read <= data;
764 count <= "110";
765 when "110" =>
766 count <= "111";
767 when "111" =>
768 cs <= '1';
769 rd <= '1';
770 count <= "000";
771 state_init <= next_state;
772 when others =>
773 null;
774 end case;
775
776 when WRITE_REG =>
777 case count is
778 when "000" =>
779 cs <= '0';
780 wr <= '0';
781 rd <= '1';
782 addr <= par_addr;
783 if (ram_access = '1') then
784 data <= ram_data;
785 else
786 data <= par_data;
787 end if;
788 count <= "100";
789 when "100" =>
790 count <= "101";
791 when "101" =>
792 count <= "110";
793 when "110" =>
794 cs <= '1';
795 wr <= '1';
796 state_init <= next_state;
797 count <= "000";
798 when others =>
799 null;
800 end case;
801
802 when others =>
803 null;
804 end case;
805 end if; -- int_flag = '0'
806
807 end if; -- rising_edge (clk)
808
809 end process w5300_init_proc;
810
811end Behavioral;
812
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