Changeset 260 for FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd.bak

Timestamp:

07/22/10 10:33:08 (14 years ago)

Author:

dneise

Message:

possible to switch off SPI SCLK now.
see new revision of simple_daq in tools/FAD/

File:

• FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd.bak (modified) (8 diffs)

FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd.bak

@@ -49 +49 @@
       ram_addr       : OUT    std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
       data_valid     : IN     std_logic;
+          data_valid_ack : OUT    std_logic := '0';
       busy           : OUT    std_logic                     := '1';
       write_header_flag, write_end_flag : IN std_logic;
@@ -64 +65 @@
       
       denable : out std_logic := '0'; -- default domino wave off
-      dwrite_enable : out std_logic := '0' -- default DWRITE low.
+      dwrite_enable : out std_logic := '0'; -- default DWRITE low.
+      sclk_enable : out std_logic := '1' -- default DWRITE HIGH.
    );
 
@@ -74 +76 @@
 
 type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
-                         INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1,
+                         INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
                          SI, SI1, SI2, SI3, SI4, SI5, SI6,      ESTABLISH, EST1, CONFIG, MAIN, CHK_RECEIVED, READ_DATA);
 type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
@@ -349 +351 @@
                                                 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8);
                                                 state_init <= WRITE_REG;
+                                                next_state <= TIMEOUT;
+                                        when TIMEOUT =>
+                                                par_addr <=     W5300_RTR;
+                                                par_data <= X"07D0"; -- 0x07D0 = 200ms
+                                                state_init <= WRITE_REG;
+                                                next_state <= RETRY;
+                                        when RETRY =>
+                                                par_addr <=     W5300_RCR;
+                                                par_data <= X"0008";
+                                                state_init <= WRITE_REG;
                                                 next_state <= SI;
 
@@ -431 +443 @@
                                             s_trigger <= '0';
                                           end if;
-            if (chk_recv_cntr = 10) then
+            if (chk_recv_cntr = 1000) then
               chk_recv_cntr <= 0;
               state_read_data <= RD_1;
@@ -437 +449 @@
               busy <= '1';
             else
+              busy <= '0';
+              data_valid_ack <= '0';
               chk_recv_cntr <= chk_recv_cntr + 1;  
                                                   if (data_valid = '1') then
+                                                    data_valid_ack <= '1';
                 local_write_length <= write_length;
                 local_ram_start_addr <= ram_start_addr;
@@ -552 +567 @@
                   next_state <= CONFIG;
                 else
-                  busy <= '0';
+--                busy <= '0';
                   next_state <= MAIN;
                 end if;
@@ -726 +741 @@
                                                                 state_write <= WR_08;
                                                         when others =>
-                                                                busy <= '0';
+--                                                      busy <= '0';
                                                                 state_init <= next_state_tmp;
                                                                 state_write <= WR_START;