source: FPGA/FTU/FTU_top.vhd@ 8782

Last change on this file since 8782 was 268, checked in by qweitzel, 15 years ago
FTU_test5 added
File size: 8.5 KB
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1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 11:59:40 01/19/2010
6-- Design Name:
7-- Module Name: FTU_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Revision 0.02 - New design of FTU firmware, 12.07.2010, Q. Weitzel
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25library ftu_definitions;
26USE ftu_definitions.ftu_array_types.all;
27
28---- Uncomment the following library declaration if instantiating
29---- any Xilinx primitives in this code.
30--library UNISIM;
31--use UNISIM.VComponents.all;
32
33entity FTU_top is
34 port(
35 -- global control
36 ext_clk : IN STD_LOGIC; -- external clock from FTU board
37 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
38 brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID
39
40 -- rate counters LVDS inputs
41 -- use IBUFDS differential input buffer
42 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
43 patch_A_n : IN STD_LOGIC;
44 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
45 patch_B_n : IN STD_LOGIC;
46 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
47 patch_C_n : IN STD_LOGIC;
48 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
49 patch_D_n : IN STD_LOGIC;
50 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
51 trig_prim_n : IN STD_LOGIC;
52
53 -- DAC interface
54 sck : OUT STD_LOGIC; -- serial clock to DAC
55 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
56 clr : OUT STD_LOGIC; -- clear signal to DAC
57 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
58
59 -- RS-485 interface to FTM
60 rx : IN STD_LOGIC; -- serial data from FTM
61 tx : OUT STD_LOGIC; -- serial data to FTM
62 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
63 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
64
65 -- analog buffer enable
66 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
67 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
68 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
69 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
70
71 -- testpoints
72 TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints
73 );
74end FTU_top;
75
76architecture Behavioral of FTU_top is
77
78 signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up
79 signal dac_clr_sig : STD_LOGIC := '1'; -- initialize dac_clr to 1 at power up
80
81 signal config_start_sig : STD_LOGIC := '0';
82 signal config_ready_sig : STD_LOGIC := '0';
83
84 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM
85 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTU_clk_gen when DCMs have locked
86
87 signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port A
88 signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port B
89 signal ram_ada_cntr : INTEGER range 0 to 2**5 - 1 := 0;
90 signal ram_adb_cntr : INTEGER range 0 to 2**4 - 1 := 0;
91 signal ram_ada_sig : STD_LOGIC_VECTOR(4 downto 0);
92 signal ram_adb_sig : STD_LOGIC_VECTOR(3 downto 0);
93 signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0);
94 signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0);
95 signal ram_doa_sig : STD_LOGIC_VECTOR(7 downto 0);
96 signal ram_dob_sig : STD_LOGIC_VECTOR(15 downto 0);
97
98 type FTU_top_StateType is (IDLE, INIT, RUNNING, RESET);
99 signal FTU_top_State, FTU_top_NextState: FTU_top_StateType;
100
101 component FTU_clk_gen
102 port (
103 clk : IN STD_LOGIC;
104 rst : IN STD_LOGIC;
105 clk_50 : OUT STD_LOGIC;
106 ready : OUT STD_LOGIC
107 );
108 end component;
109
110 component FTU_spi_interface
111 port(
112 clk_50MHz : IN std_logic;
113 config_start : IN std_logic;
114 dac_array : IN dac_array_type;
115 config_ready : OUT std_logic;
116 config_started : OUT std_logic;
117 dac_cs : OUT std_logic;
118 mosi : OUT std_logic;
119 sclk : OUT std_logic
120 );
121 end component;
122
123 component FTU_dual_port_ram
124 port(
125 clka : IN std_logic;
126 ena : IN std_logic;
127 wea : IN std_logic_VECTOR(0 downto 0);
128 addra : IN std_logic_VECTOR(4 downto 0);
129 dina : IN std_logic_VECTOR(7 downto 0);
130 douta : OUT std_logic_VECTOR(7 downto 0);
131 clkb : IN std_logic;
132 enb : IN std_logic;
133 web : IN std_logic_VECTOR(0 downto 0);
134 addrb : IN std_logic_VECTOR(3 downto 0);
135 dinb : IN std_logic_VECTOR(15 downto 0);
136 doutb : OUT std_logic_VECTOR(15 downto 0)
137 );
138 end component;
139
140 -- Synplicity black box declaration
141 attribute syn_black_box : boolean;
142 attribute syn_black_box of FTU_dual_port_ram: component is true;
143
144begin
145
146 clr <= dac_clr_sig;
147
148 Inst_FTU_clk_gen : FTU_clk_gen
149 port map (
150 clk => ext_clk,
151 rst => reset_sig,
152 clk_50 => clk_50M_sig,
153 ready => clk_ready_sig
154 );
155
156 Inst_FTU_spi_interface : FTU_spi_interface
157 port map(
158 clk_50MHz => clk_50M_sig,
159 config_start => config_start_sig,
160 dac_array => DEFAULT_DAC, -- has to come from RAM
161 config_ready => config_ready_sig,
162 config_started => open,
163 dac_cs => cs_ld,
164 mosi => mosi,
165 sclk => sck
166 );
167
168 Inst_FTU_dual_port_ram : FTU_dual_port_ram
169 port map(
170 clka => clk_50M_sig,
171 ena => '1',
172 wea => ram_wea_sig,
173 addra => ram_ada_sig,
174 dina => ram_dia_sig,
175 douta => ram_doa_sig,
176 clkb => clk_50M_sig,
177 enb => '1',
178 web => ram_web_sig,
179 addrb => ram_adb_sig,
180 dinb => ram_dib_sig,
181 doutb => ram_dob_sig
182 );
183
184 --FTU main state machine (two-process implementation)
185 --sensitive to external clock
186
187 FTU_top_Registers: process (ext_clk)
188 begin
189 if Rising_edge(ext_clk) then
190 FTU_top_State <= FTU_top_NextState;
191 end if;
192 end process FTU_top_Registers;
193
194 FTU_top_C_logic: process (FTU_top_State, clk_ready_sig, config_ready_sig, ram_adb_cntr)
195 begin
196 FTU_top_NextState <= FTU_top_State;
197 case FTU_top_State is
198 when IDLE => -- wait for DMCs to lock
199 reset_sig <= '0';
200 dac_clr_sig <= '1';
201 config_start_sig <= '0';
202 ram_web_sig <= "0";
203 if (clk_ready_sig = '1') then
204 FTU_top_NextState <= RUNNING;
205 end if;
206 when INIT => -- load default config data to RAM
207 reset_sig <= '0';
208 dac_clr_sig <= '1';
209 config_start_sig <= '0';
210 ram_web_sig <= "1";
211 ram_adb_cntr <= ram_adb_cntr + 1;
212 ram_adb_sig <= conv_std_logic_vector(ram_adb_cntr, 4);
213 if (ram_adb_cntr < 4) then
214 ram_dib_sig <= DEFAULT_ENABLE(ram_adb_cntr);
215 FTU_top_NextState <= INIT;
216 elsif (ram_adb_cntr < 4 + 5) then
217 ram_dib_sig <= conv_std_logic_vector(DEFAULT_DAC(ram_adb_cntr - 4), 16);
218 FTU_top_NextState <= INIT;
219 elsif (ram_adb_cntr < 32) then
220 ram_dib_sig <= (others => '0');
221 FTU_top_NextState <= INIT;
222 else
223 ram_adb_cntr <= 0;
224 ram_web_sig <= "0";
225 FTU_top_NextState <= RUNNING;
226 end if;
227 when RUNNING => -- count triggers and react to commands
228 reset_sig <= '0';
229 dac_clr_sig <= '1';
230 config_start_sig <= '0';
231 ram_web_sig <= "0";
232 when RESET => -- reset/clear and start from scratch
233 reset_sig <= '1';
234 dac_clr_sig <= '0';
235 config_start_sig <= '0';
236 ram_web_sig <= "0";
237 FTU_top_NextState <= IDLE;
238 end case;
239 end process FTU_top_C_logic;
240
241end Behavioral;
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