source: firmware/FAD/FACT_FAD_TB_lib/hdl/spi_max6662_tester_beha.vhd@ 17689

Last change on this file since 17689 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 1.1 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_TB_lib.spi_max6662_tester.beha
3--
4-- Created:
5-- by - dneise.UNKNOWN (E5B-LABOR6)
6-- at - 14:21:59 31.01.2011
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10)
9--
10LIBRARY ieee;
11USE ieee.std_logic_1164.ALL;
12USE ieee.std_logic_arith.ALL;
13USE ieee.std_logic_unsigned.all;
14
15ENTITY spi_max6662_tester IS
16 PORT(
17 CS : IN std_logic;
18 MOSI : IN std_logic;
19 SCLK : IN std_logic;
20 busy : IN std_logic;
21 data : IN std_logic_vector (15 DOWNTO 0);
22 ready : IN std_logic;
23 read_temp_register : OUT std_logic
24 );
25
26-- Declarations
27
28END spi_max6662_tester ;
29
30--
31ARCHITECTURE beha OF spi_max6662_tester IS
32BEGIN
33
34 process
35 begin
36 read_temp_register <= '0';
37 wait for 5000ns;
38 read_temp_register <= '1';
39 wait for 50ns;
40 read_temp_register <= '0';
41 wait for 20us;
42 read_temp_register <= '1';
43 wait for 50ns;
44 read_temp_register <= '0';
45 wait;
46 end process ;
47
48END ARCHITECTURE beha;
49
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