source: firmware/FAD/FACT_FAD_TB_lib/hds/w5300_modul2_tb/struct.bd@ 14207

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_1164"
itemName "ALL"
)
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_ARITH"
itemName "ALL"
)
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_UNSIGNED"
itemName "ALL"
)
(DmPackageRef
library "FACT_FAD_lib"
unitName "fad_definitions"
itemName "ALL"
)
]
instances [
(Instance
name "inst_w5300_mod2"
duLibraryName "FACT_FAD_lib"
duName "w5300_modul2"
elements [
]
mwi 0
uid 211,0
)
(Instance
name "U_1"
duLibraryName "FACT_FAD_TB_lib"
duName "w5300_modul2_tester"
elements [
]
mwi 0
uid 621,0
)
(Instance
name "U_2"
duLibraryName "FACT_FAD_TB_lib"
duName "clock_generator"
elements [
(GiElement
name "clock_period"
type "time"
value "20 ns"
)
(GiElement
name "reset_time"
type "time"
value "50 ns"
)
]
mwi 0
uid 1542,0
)
(Instance
name "U_0"
duLibraryName "FACT_FAD_TB_lib"
duName "w5300_emulator"
elements [
]
mwi 0
uid 2558,0
)
]
libraryRefs [
"IEEE"
"FACT_FAD_lib"
]
)
version "29.1"
appVersion "2009.2 (Build 10)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tb\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tb\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tb"
)
(vvPair
variable "d_logical"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tb"
)
(vvPair
variable "date"
value "01.06.2011"
)
(vvPair
variable "day"
value "Mi"
)
(vvPair
variable "day_long"
value "Mittwoch"
)
(vvPair
variable "dd"
value "01"
)
(vvPair
variable "entity_name"
value "w5300_modul2_tb"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "f_noext"
value "struct"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "E5B-LABOR6"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_TB_lib"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "mm"
value "06"
)
(vvPair
variable "module_name"
value "w5300_modul2_tb"
)
(vvPair
variable "month"
value "Jun"
)
(vvPair
variable "month_long"
value "Juni"
)
(vvPair
variable "p"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tb\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tb\\struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "C:\\modeltech_6.6a\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
)
(vvPair
variable "this_file_logical"
value "struct"
)
(vvPair
variable "time"
value "09:27:27"
)
(vvPair
variable "unit"
value "w5300_modul2_tb"
)
(vvPair
variable "user"
value "dneise"
)
(vvPair
variable "version"
value "2009.2 (Build 10)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2011"
)
(vvPair
variable "yy"
value "11"
)
]
)
LanguageMgr "VhdlLangMgr"
uid 1174,0
optionalChildren [
*1 (SaComponent
uid 211,0
optionalChildren [
*2 (CptPort
uid 11,0
ps "OnEdgeStrategy"
shape (Triangle
uid 12,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,46625,34750,47375"
)
tg (CPTG
uid 13,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 14,0
va (VaSet
)
xt "28400,46500,33000,47500"
st "state : (7:0)"
ju 2
blo "33000,47300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 1
)
)
)
*3 (CptPort
uid 15,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,47625,34750,48375"
)
tg (CPTG
uid 17,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18,0
va (VaSet
)
xt "23900,47500,33000,48500"
st "debug_data_ram_empty"
ju 2
blo "33000,48300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 2
)
)
)
*4 (CptPort
uid 19,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,48625,34750,49375"
)
tg (CPTG
uid 21,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 22,0
va (VaSet
)
xt "26400,48500,33000,49500"
st "debug_data_valid"
ju 2
blo "33000,49300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "debug_data_valid"
t "std_logic"
o 3
)
)
)
*5 (CptPort
uid 23,0
ps "OnEdgeStrategy"
shape (Triangle
uid 24,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,46625,0,47375"
)
tg (CPTG
uid 25,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 26,0
va (VaSet
)
xt "1000,46500,9500,47500"
st "data_generator_idle_i"
blo "1000,47300"
)
)
thePort (LogicalPort
decl (Decl
n "data_generator_idle_i"
t "std_logic"
o 4
)
)
)
*6 (CptPort
uid 31,0
ps "OnEdgeStrategy"
shape (Triangle
uid 32,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,47625,0,48375"
)
tg (CPTG
uid 33,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 34,0
va (VaSet
)
xt "1000,47500,2300,48500"
st "clk"
blo "1000,48300"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
o 5
)
)
)
*7 (CptPort
uid 35,0
ps "OnEdgeStrategy"
shape (Triangle
uid 36,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,50625,34750,51375"
)
tg (CPTG
uid 37,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 38,0
va (VaSet
)
xt "29400,50500,33000,51500"
st "wiz_reset"
ju 2
blo "33000,51300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_reset"
t "std_logic"
o 6
i "'1'"
)
)
)
*8 (CptPort
uid 39,0
ps "OnEdgeStrategy"
shape (Triangle
uid 40,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,51625,34750,52375"
)
tg (CPTG
uid 41,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 42,0
va (VaSet
)
xt "28500,51500,33000,52500"
st "addr : (9:0)"
ju 2
blo "33000,52300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 7
)
)
)
*9 (CptPort
uid 43,0
ps "OnEdgeStrategy"
shape (Diamond
uid 44,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,52625,34750,53375"
)
tg (CPTG
uid 45,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 46,0
va (VaSet
)
xt "28200,52500,33000,53500"
st "data : (15:0)"
ju 2
blo "33000,53300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 8
)
)
)
*10 (CptPort
uid 47,0
ps "OnEdgeStrategy"
shape (Triangle
uid 48,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,53625,34750,54375"
)
tg (CPTG
uid 49,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 50,0
va (VaSet
)
xt "31800,53500,33000,54500"
st "cs"
ju 2
blo "33000,54300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "cs"
t "std_logic"
o 9
i "'1'"
)
)
)
*11 (CptPort
uid 51,0
ps "OnEdgeStrategy"
shape (Triangle
uid 52,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,54625,34750,55375"
)
tg (CPTG
uid 53,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 54,0
va (VaSet
)
xt "31800,54500,33000,55500"
st "wr"
ju 2
blo "33000,55300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wr"
t "std_logic"
o 10
i "'1'"
)
)
)
*12 (CptPort
uid 55,0
ps "OnEdgeStrategy"
shape (Triangle
uid 56,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,55625,34750,56375"
)
tg (CPTG
uid 57,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 58,0
va (VaSet
)
xt "31900,55500,33000,56500"
st "rd"
ju 2
blo "33000,56300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rd"
t "std_logic"
o 11
i "'1'"
)
)
)
*13 (CptPort
uid 63,0
ps "OnEdgeStrategy"
shape (Triangle
uid 64,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,48625,0,49375"
)
tg (CPTG
uid 65,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 66,0
va (VaSet
)
xt "1000,48500,2200,49500"
st "int"
blo "1000,49300"
)
)
thePort (LogicalPort
decl (Decl
n "int"
t "std_logic"
o 12
)
)
)
*14 (CptPort
uid 67,0
ps "OnEdgeStrategy"
shape (Triangle
uid 68,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,49625,0,50375"
)
tg (CPTG
uid 69,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 70,0
va (VaSet
)
xt "1000,49500,8900,50500"
st "write_length : (16:0)"
blo "1000,50300"
)
)
thePort (LogicalPort
decl (Decl
n "write_length"
t "std_logic_vector"
b "(16 DOWNTO 0)"
o 13
)
)
)
*15 (CptPort
uid 71,0
ps "OnEdgeStrategy"
shape (Triangle
uid 72,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,50625,0,51375"
)
tg (CPTG
uid 73,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 74,0
va (VaSet
)
xt "1000,50500,20400,51500"
st "ram_start_addr : (W5300_RAM_ADDR_WIDTH-1:0)"
blo "1000,51300"
)
)
thePort (LogicalPort
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(W5300_RAM_ADDR_WIDTH-1 DOWNTO 0)"
o 14
)
)
)
*16 (CptPort
uid 75,0
ps "OnEdgeStrategy"
shape (Triangle
uid 76,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,51625,0,52375"
)
tg (CPTG
uid 77,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 78,0
va (VaSet
)
xt "1000,51500,7500,52500"
st "ram_data : (15:0)"
blo "1000,52300"
)
)
thePort (LogicalPort
decl (Decl
n "ram_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 15
)
)
)
*17 (CptPort
uid 79,0
ps "OnEdgeStrategy"
shape (Triangle
uid 80,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,57625,34750,58375"
)
tg (CPTG
uid 81,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 82,0
va (VaSet
)
xt "15900,57500,33000,58500"
st "ram_addr : (W5300_RAM_ADDR_WIDTH-1:0)"
ju 2
blo "33000,58300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_addr"
t "std_logic_vector"
b "(W5300_RAM_ADDR_WIDTH-1 DOWNTO 0)"
o 16
)
)
)
*18 (CptPort
uid 83,0
ps "OnEdgeStrategy"
shape (Triangle
uid 84,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,52625,0,53375"
)
tg (CPTG
uid 85,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 86,0
va (VaSet
)
xt "1000,52500,5100,53500"
st "data_valid"
blo "1000,53300"
)
)
thePort (LogicalPort
decl (Decl
n "data_valid"
t "std_logic"
o 17
)
)
)
*19 (CptPort
uid 87,0
ps "OnEdgeStrategy"
shape (Triangle
uid 88,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,58625,34750,59375"
)
tg (CPTG
uid 89,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 90,0
va (VaSet
)
xt "27400,58500,33000,59500"
st "data_valid_ack"
ju 2
blo "33000,59300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data_valid_ack"
t "std_logic"
o 18
i "'0'"
)
)
)
*20 (CptPort
uid 91,0
ps "OnEdgeStrategy"
shape (Triangle
uid 92,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,59625,34750,60375"
)
tg (CPTG
uid 93,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 94,0
va (VaSet
)
xt "31100,59500,33000,60500"
st "busy"
ju 2
blo "33000,60300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "busy"
t "std_logic"
o 19
i "'1'"
)
)
)
*21 (CptPort
uid 95,0
ps "OnEdgeStrategy"
shape (Triangle
uid 96,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,53625,0,54375"
)
tg (CPTG
uid 97,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 98,0
va (VaSet
)
xt "1000,53500,7800,54500"
st "write_header_flag"
blo "1000,54300"
)
)
thePort (LogicalPort
decl (Decl
n "write_header_flag"
t "std_logic"
o 20
)
)
)
*22 (CptPort
uid 99,0
ps "OnEdgeStrategy"
shape (Triangle
uid 100,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,54625,0,55375"
)
tg (CPTG
uid 101,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 102,0
va (VaSet
)
xt "1000,54500,6700,55500"
st "write_end_flag"
blo "1000,55300"
)
)
thePort (LogicalPort
decl (Decl
n "write_end_flag"
t "std_logic"
o 21
)
)
)
*23 (CptPort
uid 103,0
ps "OnEdgeStrategy"
shape (Triangle
uid 104,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,55625,0,56375"
)
tg (CPTG
uid 105,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 106,0
va (VaSet
)
xt "1000,55500,8800,56500"
st "fifo_channels : (3:0)"
blo "1000,56300"
)
)
thePort (LogicalPort
decl (Decl
n "fifo_channels"
t "std_logic_vector"
b "(3 downto 0)"
o 22
)
)
)
*24 (CptPort
uid 107,0
ps "OnEdgeStrategy"
shape (Triangle
uid 108,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,60625,34750,61375"
)
tg (CPTG
uid 109,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 110,0
va (VaSet
)
xt "29400,60500,33000,61500"
st "s_trigger"
ju 2
blo "33000,61300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "s_trigger"
t "std_logic"
o 23
i "'0'"
)
)
)
*25 (CptPort
uid 111,0
ps "OnEdgeStrategy"
shape (Triangle
uid 112,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,61625,34750,62375"
)
tg (CPTG
uid 113,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 114,0
va (VaSet
)
xt "26400,61500,33000,62500"
st "c_trigger_enable"
ju 2
blo "33000,62300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "c_trigger_enable"
t "std_logic"
o 24
i "'0'"
)
)
)
*26 (CptPort
uid 115,0
ps "OnEdgeStrategy"
shape (Triangle
uid 116,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,62625,34750,63375"
)
tg (CPTG
uid 117,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 118,0
va (VaSet
)
xt "24200,62500,33000,63500"
st "c_trigger_mult : (15:0)"
ju 2
blo "33000,63300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "c_trigger_mult"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 25
i "conv_std_logic_vector(0 ,16)"
)
)
)
*27 (CptPort
uid 119,0
ps "OnEdgeStrategy"
shape (Triangle
uid 120,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,63625,34750,64375"
)
tg (CPTG
uid 121,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 122,0
va (VaSet
)
xt "20600,63500,33000,64500"
st "memory_manager_config_start_o"
ju 2
blo "33000,64300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memory_manager_config_start_o"
t "std_logic"
o 26
i "'0'"
)
)
)
*28 (CptPort
uid 123,0
ps "OnEdgeStrategy"
shape (Triangle
uid 124,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,56625,0,57375"
)
tg (CPTG
uid 125,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 126,0
va (VaSet
)
xt "1000,56500,13200,57500"
st "memory_manager_config_valid_i"
blo "1000,57300"
)
)
thePort (LogicalPort
decl (Decl
n "memory_manager_config_valid_i"
t "std_logic"
o 27
)
)
)
*29 (CptPort
uid 127,0
ps "OnEdgeStrategy"
shape (Triangle
uid 128,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,64625,34750,65375"
)
tg (CPTG
uid 129,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 130,0
va (VaSet
)
xt "22300,64500,33000,65500"
st "spi_interface_config_start_o"
ju 2
blo "33000,65300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "spi_interface_config_start_o"
t "std_logic"
o 28
i "'0'"
)
)
)
*30 (CptPort
uid 131,0
ps "OnEdgeStrategy"
shape (Triangle
uid 132,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,57625,0,58375"
)
tg (CPTG
uid 133,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 134,0
va (VaSet
)
xt "1000,57500,11500,58500"
st "spi_interface_config_valid_i"
blo "1000,58300"
)
)
thePort (LogicalPort
decl (Decl
n "spi_interface_config_valid_i"
t "std_logic"
o 29
)
)
)
*31 (CptPort
uid 135,0
ps "OnEdgeStrategy"
shape (Triangle
uid 136,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,65625,34750,66375"
)
tg (CPTG
uid 137,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 138,0
va (VaSet
)
xt "28300,65500,33000,66500"
st "dac_setting"
ju 2
blo "33000,66300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dac_setting"
t "dac_array_type"
o 30
i "DEFAULT_DAC"
)
)
)
*32 (CptPort
uid 139,0
ps "OnEdgeStrategy"
shape (Triangle
uid 140,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,66625,34750,67375"
)
tg (CPTG
uid 141,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 142,0
va (VaSet
)
xt "28600,66500,33000,67500"
st "roi_setting"
ju 2
blo "33000,67300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "roi_setting"
t "roi_array_type"
o 31
i "DEFAULT_ROI"
)
)
)
*33 (CptPort
uid 143,0
ps "OnEdgeStrategy"
shape (Triangle
uid 144,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,67625,34750,68375"
)
tg (CPTG
uid 145,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 146,0
va (VaSet
)
xt "26000,67500,33000,68500"
st "runnumber : (31:0)"
ju 2
blo "33000,68300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "runnumber"
t "std_logic_vector"
b "(31 DOWNTO 0)"
o 32
i "conv_std_logic_vector(0 ,32)"
)
)
)
*34 (CptPort
uid 147,0
ps "OnEdgeStrategy"
shape (Triangle
uid 148,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,68625,34750,69375"
)
tg (CPTG
uid 149,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 150,0
va (VaSet
)
xt "26700,68500,33000,69500"
st "reset_trigger_id"
ju 2
blo "33000,69300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "reset_trigger_id"
t "std_logic"
o 33
i "'0'"
)
)
)
*35 (CptPort
uid 151,0
ps "OnEdgeStrategy"
shape (Triangle
uid 152,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,58625,0,59375"
)
tg (CPTG
uid 153,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 154,0
va (VaSet
)
xt "1000,58500,7200,59500"
st "data_ram_empty"
blo "1000,59300"
)
)
thePort (LogicalPort
decl (Decl
n "data_ram_empty"
t "std_logic"
o 34
)
)
)
*36 (CptPort
uid 155,0
ps "OnEdgeStrategy"
shape (Triangle
uid 156,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,59625,0,60375"
)
tg (CPTG
uid 157,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 158,0
va (VaSet
)
xt "1000,59500,8500,60500"
st "MAC_jumper : (1:0)"
blo "1000,60300"
)
)
thePort (LogicalPort
decl (Decl
n "MAC_jumper"
t "std_logic_vector"
b "(1 downto 0)"
o 35
)
)
)
*37 (CptPort
uid 159,0
ps "OnEdgeStrategy"
shape (Triangle
uid 160,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,60625,0,61375"
)
tg (CPTG
uid 161,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 162,0
va (VaSet
)
xt "1000,60500,6800,61500"
st "BoardID : (3:0)"
blo "1000,61300"
)
)
thePort (LogicalPort
decl (Decl
n "BoardID"
t "std_logic_vector"
b "(3 downto 0)"
o 36
)
)
)
*38 (CptPort
uid 163,0
ps "OnEdgeStrategy"
shape (Triangle
uid 164,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,61625,0,62375"
)
tg (CPTG
uid 165,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 166,0
va (VaSet
)
xt "1000,61500,6700,62500"
st "CrateID : (1:0)"
blo "1000,62300"
)
)
thePort (LogicalPort
decl (Decl
n "CrateID"
t "std_logic_vector"
b "(1 downto 0)"
o 37
)
)
)
*39 (CptPort
uid 167,0
ps "OnEdgeStrategy"
shape (Triangle
uid 168,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,69625,34750,70375"
)
tg (CPTG
uid 169,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 170,0
va (VaSet
)
xt "27200,69500,33000,70500"
st "trigger_enable"
ju 2
blo "33000,70300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "trigger_enable"
t "std_logic"
o 38
)
)
)
*40 (CptPort
uid 171,0
ps "OnEdgeStrategy"
shape (Triangle
uid 172,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,70625,34750,71375"
)
tg (CPTG
uid 173,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 174,0
va (VaSet
)
xt "30000,70500,33000,71500"
st "denable"
ju 2
blo "33000,71300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "denable"
t "std_logic"
o 39
i "'0'"
)
)
)
*41 (CptPort
uid 175,0
ps "OnEdgeStrategy"
shape (Triangle
uid 176,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,71625,34750,72375"
)
tg (CPTG
uid 177,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 178,0
va (VaSet
)
xt "27600,71500,33000,72500"
st "dwrite_enable"
ju 2
blo "33000,72300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dwrite_enable"
t "std_logic"
o 40
i "'1'"
)
)
)
*42 (CptPort
uid 179,0
ps "OnEdgeStrategy"
shape (Triangle
uid 180,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,72625,34750,73375"
)
tg (CPTG
uid 181,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 182,0
va (VaSet
)
xt "28300,72500,33000,73500"
st "sclk_enable"
ju 2
blo "33000,73300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sclk_enable"
t "std_logic"
o 41
i "'1'"
)
)
)
*43 (CptPort
uid 183,0
ps "OnEdgeStrategy"
shape (Triangle
uid 184,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,73625,34750,74375"
)
tg (CPTG
uid 185,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 186,0
va (VaSet
)
xt "28000,73500,33000,74500"
st "srclk_enable"
ju 2
blo "33000,74300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "srclk_enable"
t "std_logic"
o 42
i "'1'"
)
)
)
*44 (CptPort
uid 187,0
ps "OnEdgeStrategy"
shape (Triangle
uid 188,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,74625,34750,75375"
)
tg (CPTG
uid 189,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 190,0
va (VaSet
)
xt "28100,74500,33000,75500"
st "ps_direction"
ju 2
blo "33000,75300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ps_direction"
t "std_logic"
o 43
i "'1'"
)
)
)
*45 (CptPort
uid 191,0
ps "OnEdgeStrategy"
shape (Triangle
uid 192,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,75625,34750,76375"
)
tg (CPTG
uid 193,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 194,0
va (VaSet
)
xt "26000,75500,33000,76500"
st "ps_do_phase_shift"
ju 2
blo "33000,76300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ps_do_phase_shift"
t "std_logic"
o 44
i "'0'"
)
)
)
*46 (CptPort
uid 195,0
ps "OnEdgeStrategy"
shape (Triangle
uid 196,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,76625,34750,77375"
)
tg (CPTG
uid 197,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 198,0
va (VaSet
)
xt "29700,76500,33000,77500"
st "ps_reset"
ju 2
blo "33000,77300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ps_reset"
t "std_logic"
o 45
i "'0'"
)
)
)
*47 (CptPort
uid 199,0
ps "OnEdgeStrategy"
shape (Triangle
uid 200,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-750,62625,0,63375"
)
tg (CPTG
uid 201,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 202,0
va (VaSet
)
xt "1000,62500,4400,63500"
st "ps_ready"
blo "1000,63300"
)
)
thePort (LogicalPort
decl (Decl
n "ps_ready"
t "std_logic"
o 46
)
)
)
*48 (CptPort
uid 203,0
ps "OnEdgeStrategy"
shape (Triangle
uid 204,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,77625,34750,78375"
)
tg (CPTG
uid 205,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 206,0
va (VaSet
)
xt "27500,77500,33000,78500"
st "socks_waiting"
ju 2
blo "33000,78300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "socks_waiting"
t "std_logic"
o 47
)
)
)
*49 (CptPort
uid 207,0
ps "OnEdgeStrategy"
shape (Triangle
uid 208,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,78625,34750,79375"
)
tg (CPTG
uid 209,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 210,0
va (VaSet
)
xt "26500,78500,33000,79500"
st "socks_connected"
ju 2
blo "33000,79300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "socks_connected"
t "std_logic"
o 48
)
)
)
]
shape (Rectangle
uid 212,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,46000,34000,80000"
)
ttg (MlTextGroup
uid 213,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*50 (Text
uid 214,0
va (VaSet
font "Arial,8,1"
)
xt "13900,80000,20100,81000"
st "FACT_FAD_lib"
blo "13900,80800"
tm "BdLibraryNameMgr"
)
*51 (Text
uid 215,0
va (VaSet
font "Arial,8,1"
)
xt "13900,81000,20000,82000"
st "w5300_modul2"
blo "13900,81800"
tm "CptNameMgr"
)
*52 (Text
uid 216,0
va (VaSet
font "Arial,8,1"
)
xt "13900,82000,21100,83000"
st "inst_w5300_mod2"
blo "13900,82800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 217,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 218,0
text (MLText
uid 219,0
va (VaSet
font "Courier New,8,0"
)
xt "7250,45200,26750,46000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 220,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "250,78250,1750,79750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archType 1
archFileType "UNKNOWN"
)
*53 (Net
uid 221,0
decl (Decl
n "state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 1
suid 1,0
)
declText (MLText
uid 222,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,35800,57500,36600"
st "SIGNAL state                         : std_logic_vector(7 DOWNTO 0)"
)
)
*54 (Net
uid 229,0
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 2
suid 2,0
)
declText (MLText
uid 230,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,15000,48000,15800"
st "SIGNAL debug_data_ram_empty          : std_logic"
)
)
*55 (Net
uid 237,0
decl (Decl
n "debug_data_valid"
t "std_logic"
o 3
suid 3,0
)
declText (MLText
uid 238,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,15800,48000,16600"
st "SIGNAL debug_data_valid              : std_logic"
)
)
*56 (Net
uid 253,0
lang 10
decl (Decl
n "wiz_reset"
t "std_logic"
o 5
suid 5,0
)
declText (MLText
uid 254,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,37400,48000,38200"
st "SIGNAL wiz_reset                     : std_logic"
)
)
*57 (Net
uid 261,0
decl (Decl
n "addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 6
suid 6,0
)
declText (MLText
uid 262,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,5400,57500,6200"
st "SIGNAL addr                          : std_logic_vector(9 DOWNTO 0)"
)
)
*58 (Net
uid 269,0
lang 10
decl (Decl
n "data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 7
suid 7,0
i "(others => 'Z')"
)
declText (MLText
uid 270,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,11000,67500,11800"
st "SIGNAL data                          : std_logic_vector(15 DOWNTO 0) := (others => 'Z')"
)
)
*59 (Net
uid 277,0
lang 10
decl (Decl
n "cs"
t "std_logic"
o 8
suid 8,0
)
declText (MLText
uid 278,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,9400,48000,10200"
st "SIGNAL cs                            : std_logic"
)
)
*60 (Net
uid 285,0
lang 10
decl (Decl
n "wr"
t "std_logic"
o 9
suid 9,0
)
declText (MLText
uid 286,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,38200,48000,39000"
st "SIGNAL wr                            : std_logic"
)
)
*61 (Net
uid 293,0
lang 10
decl (Decl
n "rd"
t "std_logic"
o 10
suid 10,0
)
declText (MLText
uid 294,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,27000,48000,27800"
st "SIGNAL rd                            : std_logic"
)
)
*62 (Net
uid 309,0
lang 10
decl (Decl
n "ram_addr"
t "std_logic_vector"
b "(13 DOWNTO 0)"
o 12
suid 12,0
)
declText (MLText
uid 310,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,24600,58000,25400"
st "SIGNAL ram_addr                      : std_logic_vector(13 DOWNTO 0)"
)
)
*63 (Net
uid 317,0
lang 10
decl (Decl
n "data_valid_ack"
t "std_logic"
o 13
suid 13,0
)
declText (MLText
uid 318,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,14200,48000,15000"
st "SIGNAL data_valid_ack                : std_logic"
)
)
*64 (Net
uid 325,0
lang 10
decl (Decl
n "busy"
t "std_logic"
o 14
suid 14,0
)
declText (MLText
uid 326,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,6200,48000,7000"
st "SIGNAL busy                          : std_logic"
)
)
*65 (Net
uid 333,0
lang 10
decl (Decl
n "s_trigger"
t "std_logic"
o 15
suid 15,0
)
declText (MLText
uid 334,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,30200,48000,31000"
st "SIGNAL s_trigger                     : std_logic"
)
)
*66 (Net
uid 341,0
lang 10
decl (Decl
n "c_trigger_enable"
t "std_logic"
o 16
suid 16,0
)
declText (MLText
uid 342,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,7000,48000,7800"
st "SIGNAL c_trigger_enable              : std_logic"
)
)
*67 (Net
uid 349,0
lang 10
decl (Decl
n "c_trigger_mult"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 17
suid 17,0
)
declText (MLText
uid 350,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,7800,58000,8600"
st "SIGNAL c_trigger_mult                : std_logic_vector(15 DOWNTO 0)"
)
)
*68 (Net
uid 357,0
lang 10
decl (Decl
n "memory_manager_config_start_o"
t "std_logic"
o 18
suid 18,0
)
declText (MLText
uid 358,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,19800,48000,20600"
st "SIGNAL memory_manager_config_start_o : std_logic"
)
)
*69 (Net
uid 365,0
lang 10
decl (Decl
n "spi_interface_config_start_o"
t "std_logic"
o 19
suid 19,0
)
declText (MLText
uid 366,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,33400,48000,34200"
st "SIGNAL spi_interface_config_start_o  : std_logic"
)
)
*70 (Net
uid 373,0
lang 10
decl (Decl
n "dac_setting"
t "dac_array_type"
o 20
suid 20,0
)
declText (MLText
uid 374,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,10200,50500,11000"
st "SIGNAL dac_setting                   : dac_array_type"
)
)
*71 (Net
uid 381,0
lang 10
decl (Decl
n "roi_setting"
t "roi_array_type"
o 21
suid 21,0
)
declText (MLText
uid 382,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,28600,50500,29400"
st "SIGNAL roi_setting                   : roi_array_type"
)
)
*72 (Net
uid 389,0
lang 10
decl (Decl
n "runnumber"
t "std_logic_vector"
b "(31 DOWNTO 0)"
o 22
suid 22,0
)
declText (MLText
uid 390,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,29400,58000,30200"
st "SIGNAL runnumber                     : std_logic_vector(31 DOWNTO 0)"
)
)
*73 (Net
uid 397,0
lang 10
decl (Decl
n "reset_trigger_id"
t "std_logic"
o 23
suid 23,0
)
declText (MLText
uid 398,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,27800,48000,28600"
st "SIGNAL reset_trigger_id              : std_logic"
)
)
*74 (Net
uid 405,0
decl (Decl
n "trigger_enable"
t "std_logic"
o 24
suid 24,0
)
declText (MLText
uid 406,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,36600,48000,37400"
st "SIGNAL trigger_enable                : std_logic"
)
)
*75 (Net
uid 413,0
lang 10
decl (Decl
n "denable"
t "std_logic"
o 25
suid 25,0
)
declText (MLText
uid 414,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,16600,48000,17400"
st "SIGNAL denable                       : std_logic"
)
)
*76 (Net
uid 421,0
lang 10
decl (Decl
n "dwrite_enable"
t "std_logic"
o 26
suid 26,0
)
declText (MLText
uid 422,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,17400,48000,18200"
st "SIGNAL dwrite_enable                 : std_logic"
)
)
*77 (Net
uid 429,0
lang 10
decl (Decl
n "sclk_enable"
t "std_logic"
o 27
suid 27,0
)
declText (MLText
uid 430,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,31000,48000,31800"
st "SIGNAL sclk_enable                   : std_logic"
)
)
*78 (Net
uid 437,0
lang 10
decl (Decl
n "srclk_enable"
t "std_logic"
o 28
suid 28,0
)
declText (MLText
uid 438,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,35000,48000,35800"
st "SIGNAL srclk_enable                  : std_logic"
)
)
*79 (Net
uid 445,0
lang 10
decl (Decl
n "ps_direction"
t "std_logic"
o 29
suid 29,0
)
declText (MLText
uid 446,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,21400,48000,22200"
st "SIGNAL ps_direction                  : std_logic"
)
)
*80 (Net
uid 453,0
lang 10
decl (Decl
n "ps_do_phase_shift"
t "std_logic"
o 30
suid 30,0
)
declText (MLText
uid 454,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,22200,48000,23000"
st "SIGNAL ps_do_phase_shift             : std_logic"
)
)
*81 (Net
uid 461,0
lang 10
decl (Decl
n "ps_reset"
t "std_logic"
o 31
suid 31,0
)
declText (MLText
uid 462,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,23800,48000,24600"
st "SIGNAL ps_reset                      : std_logic"
)
)
*82 (Net
uid 469,0
decl (Decl
n "socks_waiting"
t "std_logic"
o 32
suid 32,0
)
declText (MLText
uid 470,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,32600,48000,33400"
st "SIGNAL socks_waiting                 : std_logic"
)
)
*83 (Net
uid 477,0
decl (Decl
n "socks_connected"
t "std_logic"
o 33
suid 33,0
)
declText (MLText
uid 478,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,31800,48000,32600"
st "SIGNAL socks_connected               : std_logic"
)
)
*84 (Net
uid 485,0
decl (Decl
n "data_generator_idle_i"
t "std_logic"
o 34
suid 34,0
)
declText (MLText
uid 486,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,11800,48000,12600"
st "SIGNAL data_generator_idle_i         : std_logic"
)
)
*85 (Net
uid 493,0
decl (Decl
n "clk"
t "std_logic"
o 35
suid 35,0
)
declText (MLText
uid 494,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,8600,48000,9400"
st "SIGNAL clk                           : std_logic"
)
)
*86 (Net
uid 501,0
decl (Decl
n "int"
t "std_logic"
o 36
suid 36,0
)
declText (MLText
uid 502,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,19000,48000,19800"
st "SIGNAL int                           : std_logic"
)
)
*87 (Net
uid 509,0
decl (Decl
n "write_length"
t "std_logic_vector"
b "(16 DOWNTO 0)"
o 37
suid 37,0
)
declText (MLText
uid 510,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,40600,58000,41400"
st "SIGNAL write_length                  : std_logic_vector(16 DOWNTO 0)"
)
)
*88 (Net
uid 517,0
lang 10
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(13 DOWNTO 0)"
o 38
suid 38,0
)
declText (MLText
uid 518,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,26200,58000,27000"
st "SIGNAL ram_start_addr                : std_logic_vector(13 DOWNTO 0)"
)
)
*89 (Net
uid 525,0
decl (Decl
n "ram_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 39
suid 39,0
)
declText (MLText
uid 526,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,25400,58000,26200"
st "SIGNAL ram_data                      : std_logic_vector(15 DOWNTO 0)"
)
)
*90 (Net
uid 533,0
decl (Decl
n "data_valid"
t "std_logic"
o 40
suid 40,0
)
declText (MLText
uid 534,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,13400,48000,14200"
st "SIGNAL data_valid                    : std_logic"
)
)
*91 (Net
uid 541,0
decl (Decl
n "write_header_flag"
t "std_logic"
o 41
suid 41,0
)
declText (MLText
uid 542,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,39800,48000,40600"
st "SIGNAL write_header_flag             : std_logic"
)
)
*92 (Net
uid 549,0
decl (Decl
n "write_end_flag"
t "std_logic"
o 42
suid 42,0
)
declText (MLText
uid 550,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,39000,48000,39800"
st "SIGNAL write_end_flag                : std_logic"
)
)
*93 (Net
uid 557,0
lang 10
decl (Decl
n "fifo_channels"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 43
suid 43,0
)
declText (MLText
uid 558,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,18200,57500,19000"
st "SIGNAL fifo_channels                 : std_logic_vector(3 DOWNTO 0)"
)
)
*94 (Net
uid 565,0
decl (Decl
n "memory_manager_config_valid_i"
t "std_logic"
o 44
suid 44,0
)
declText (MLText
uid 566,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,20600,48000,21400"
st "SIGNAL memory_manager_config_valid_i : std_logic"
)
)
*95 (Net
uid 573,0
decl (Decl
n "spi_interface_config_valid_i"
t "std_logic"
o 45
suid 45,0
)
declText (MLText
uid 574,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,34200,48000,35000"
st "SIGNAL spi_interface_config_valid_i  : std_logic"
)
)
*96 (Net
uid 581,0
decl (Decl
n "data_ram_empty"
t "std_logic"
o 46
suid 46,0
)
declText (MLText
uid 582,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,12600,48000,13400"
st "SIGNAL data_ram_empty                : std_logic"
)
)
*97 (Net
uid 589,0
lang 10
decl (Decl
n "MAC_jumper"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 47
suid 47,0
)
declText (MLText
uid 590,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,4600,57500,5400"
st "SIGNAL MAC_jumper                    : std_logic_vector(1 DOWNTO 0)"
)
)
*98 (Net
uid 597,0
lang 10
decl (Decl
n "BoardID"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 48
suid 48,0
)
declText (MLText
uid 598,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,3000,57500,3800"
st "SIGNAL BoardID                       : std_logic_vector(3 DOWNTO 0)"
)
)
*99 (Net
uid 605,0
lang 10
decl (Decl
n "CrateID"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 49
suid 49,0
)
declText (MLText
uid 606,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,3800,57500,4600"
st "SIGNAL CrateID                       : std_logic_vector(1 DOWNTO 0)"
)
)
*100 (Net
uid 613,0
decl (Decl
n "ps_ready"
t "std_logic"
o 50
suid 50,0
)
declText (MLText
uid 614,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,23000,48000,23800"
st "SIGNAL ps_ready                      : std_logic"
)
)
*101 (Blk
uid 621,0
shape (Rectangle
uid 622,0
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "74000,45000,108000,79000"
)
ttg (MlTextGroup
uid 623,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*102 (Text
uid 624,0
va (VaSet
font "Arial,8,1"
)
xt "87150,60500,94850,61500"
st "FACT_FAD_TB_lib"
blo "87150,61300"
tm "BdLibraryNameMgr"
)
*103 (Text
uid 625,0
va (VaSet
font "Arial,8,1"
)
xt "87150,61500,95750,62500"
st "w5300_modul2_tester"
blo "87150,62300"
tm "BlkNameMgr"
)
*104 (Text
uid 626,0
va (VaSet
font "Arial,8,1"
)
xt "87150,62500,88950,63500"
st "U_1"
blo "87150,63300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 627,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 628,0
text (MLText
uid 629,0
va (VaSet
font "Courier New,8,0"
)
xt "87150,70500,87150,70500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 630,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "74250,77250,75750,78750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
blkPorts [
"clk"
"busy"
"c_trigger_enable"
"c_trigger_mult"
"dac_setting"
"data_valid_ack"
"debug_data_ram_empty"
"debug_data_valid"
"denable"
"dwrite_enable"
"memory_manager_config_start_o"
"ps_direction"
"ps_do_phase_shift"
"ps_reset"
"ram_addr"
"reset_trigger_id"
"roi_setting"
"runnumber"
"s_trigger"
"sclk_enable"
"socks_connected"
"socks_waiting"
"spi_interface_config_start_o"
"srclk_enable"
"state"
"trigger_enable"
"wiz_reset"
"BoardID"
"CrateID"
"MAC_jumper"
"data_generator_idle_i"
"data_ram_empty"
"data_valid"
"fifo_channels"
"memory_manager_config_valid_i"
"ps_ready"
"ram_data"
"ram_start_addr"
"spi_interface_config_valid_i"
"write_end_flag"
"write_header_flag"
"write_length"
]
)
*105 (SaComponent
uid 1542,0
optionalChildren [
*106 (CptPort
uid 1531,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1532,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,19625,80750,20375"
)
tg (CPTG
uid 1533,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1534,0
va (VaSet
)
xt "77700,19500,79000,20500"
st "clk"
ju 2
blo "79000,20300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "clk"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
i "'0'"
)
)
)
*107 (CptPort
uid 1535,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1536,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,20625,80750,21375"
)
tg (CPTG
uid 1537,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1538,0
va (VaSet
)
xt "77700,20500,79000,21500"
st "rst"
ju 2
blo "79000,21300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rst"
t "std_logic"
preAdd 0
posAdd 0
o 2
suid 2,0
i "'0'"
)
)
)
*108 (CommentText
uid 1539,0
ps "EdgeToEdgeStrategy"
shape (Rectangle
uid 1540,0
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "71500,8000,86500,12000"
)
oxt "21500,4000,36500,8000"
text (MLText
uid 1541,0
va (VaSet
fg "0,0,32768"
)
xt "71700,8200,81500,9200"
st "
--   synthesis translate_off
"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 15000
)
included 1
excludeCommentLeader 1
)
]
shape (Rectangle
uid 1543,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "72000,19000,80000,23000"
)
oxt "22000,15000,30000,19000"
ttg (MlTextGroup
uid 1544,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*109 (Text
uid 1545,0
va (VaSet
font "Arial,8,1"
)
xt "72150,23000,79850,24000"
st "FACT_FAD_TB_lib"
blo "72150,23800"
tm "BdLibraryNameMgr"
)
*110 (Text
uid 1546,0
va (VaSet
font "Arial,8,1"
)
xt "72150,24000,78850,25000"
st "clock_generator"
blo "72150,24800"
tm "CptNameMgr"
)
*111 (Text
uid 1547,0
va (VaSet
font "Arial,8,1"
)
xt "72150,25000,73950,26000"
st "U_2"
blo "72150,25800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1548,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1549,0
text (MLText
uid 1550,0
va (VaSet
font "Courier New,8,0"
)
xt "71500,10400,90000,12000"
st "clock_period = 20 ns    ( time )  
reset_time   = 50 ns    ( time )  "
)
header ""
)
elements [
(GiElement
name "clock_period"
type "time"
value "20 ns"
)
(GiElement
name "reset_time"
type "time"
value "50 ns"
)
]
)
viewicon (ZoomableIcon
uid 1551,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "72250,21250,73750,22750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*112 (SaComponent
uid 2558,0
optionalChildren [
*113 (CptPort
uid 2533,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2534,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "93250,27625,94000,28375"
)
tg (CPTG
uid 2535,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2536,0
va (VaSet
)
xt "95000,27500,99500,28500"
st "addr : (9:0)"
blo "95000,28300"
)
)
thePort (LogicalPort
decl (Decl
n "addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
preAdd 0
posAdd 0
o 2
suid 1,0
)
)
)
*114 (CptPort
uid 2537,0
ps "OnEdgeStrategy"
shape (Diamond
uid 2538,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "93250,28625,94000,29375"
)
tg (CPTG
uid 2539,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2540,0
va (VaSet
)
xt "95000,28500,99800,29500"
st "data : (15:0)"
blo "95000,29300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
preAdd 0
posAdd 0
o 3
suid 2,0
)
)
)
*115 (CptPort
uid 2541,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2542,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "93250,31625,94000,32375"
)
tg (CPTG
uid 2543,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2544,0
va (VaSet
)
xt "95000,31500,96100,32500"
st "rd"
blo "95000,32300"
)
)
thePort (LogicalPort
decl (Decl
n "rd"
t "std_logic"
preAdd 0
posAdd 0
o 4
suid 3,0
)
)
)
*116 (CptPort
uid 2545,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2546,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "93250,32625,94000,33375"
)
tg (CPTG
uid 2547,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2548,0
va (VaSet
)
xt "95000,32500,96200,33500"
st "wr"
blo "95000,33300"
)
)
thePort (LogicalPort
decl (Decl
n "wr"
t "std_logic"
preAdd 0
posAdd 0
o 6
suid 4,0
)
)
)
*117 (CptPort
uid 2549,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2550,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "108000,27625,108750,28375"
)
tg (CPTG
uid 2551,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2552,0
va (VaSet
)
xt "105800,27500,107000,28500"
st "int"
ju 2
blo "107000,28300"
)
t (Text
uid 2553,0
va (VaSet
)
xt "105800,28500,107000,29500"
st "'1'"
ju 2
blo "107000,29300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "int"
t "std_logic"
o 1
suid 5,0
i "'1'"
)
)
)
*118 (CptPort
uid 2554,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2555,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "93250,34625,94000,35375"
)
tg (CPTG
uid 2556,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2557,0
va (VaSet
)
xt "95000,34500,96200,35500"
st "cs"
blo "95000,35300"
)
)
thePort (LogicalPort
decl (Decl
n "cs"
t "std_logic"
o 5
suid 6,0
)
)
)
]
shape (Rectangle
uid 2559,0
va (VaSet
vasetType 1
fg "0,49152,49152"
lineColor "0,0,50000"
lineWidth 2
)
xt "94000,26000,108000,38000"
)
oxt "29000,0,43000,12000"
ttg (MlTextGroup
uid 2560,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*119 (Text
uid 2561,0
va (VaSet
font "Arial,8,1"
)
xt "94200,38000,101900,39000"
st "FACT_FAD_TB_lib"
blo "94200,38800"
tm "BdLibraryNameMgr"
)
*120 (Text
uid 2562,0
va (VaSet
font "Arial,8,1"
)
xt "94200,39000,100800,40000"
st "w5300_emulator"
blo "94200,39800"
tm "CptNameMgr"
)
*121 (Text
uid 2563,0
va (VaSet
font "Arial,8,1"
)
xt "94200,40000,96000,41000"
st "U_0"
blo "94200,40800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2564,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2565,0
text (MLText
uid 2566,0
va (VaSet
font "Courier New,8,0"
)
xt "94000,26200,94000,26200"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 2567,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "94250,36250,95750,37750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*122 (Wire
uid 223,0
shape (OrthoPolyLine
uid 224,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "34750,47000,51000,47000"
pts [
"34750,47000"
"51000,47000"
]
)
start &2
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 227,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 228,0
va (VaSet
)
xt "36000,46000,40600,47000"
st "state : (7:0)"
blo "36000,46800"
tm "WireNameMgr"
)
)
on &53
)
*123 (Wire
uid 231,0
shape (OrthoPolyLine
uid 232,0
va (VaSet
vasetType 3
)
xt "34750,48000,51000,48000"
pts [
"34750,48000"
"51000,48000"
]
)
start &3
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 235,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 236,0
va (VaSet
)
xt "36000,47000,45100,48000"
st "debug_data_ram_empty"
blo "36000,47800"
tm "WireNameMgr"
)
)
on &54
)
*124 (Wire
uid 239,0
shape (OrthoPolyLine
uid 240,0
va (VaSet
vasetType 3
)
xt "34750,49000,51000,49000"
pts [
"34750,49000"
"51000,49000"
]
)
start &4
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 243,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 244,0
va (VaSet
)
xt "36000,48000,42600,49000"
st "debug_data_valid"
blo "36000,48800"
tm "WireNameMgr"
)
)
on &55
)
*125 (Wire
uid 255,0
shape (OrthoPolyLine
uid 256,0
va (VaSet
vasetType 3
)
xt "34750,51000,51000,51000"
pts [
"34750,51000"
"51000,51000"
]
)
start &7
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 259,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 260,0
va (VaSet
)
xt "36000,50000,39600,51000"
st "wiz_reset"
blo "36000,50800"
tm "WireNameMgr"
)
)
on &56
)
*126 (Wire
uid 263,0
shape (OrthoPolyLine
uid 264,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "34750,52000,51000,52000"
pts [
"34750,52000"
"51000,52000"
]
)
start &8
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 267,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 268,0
va (VaSet
)
xt "36000,51000,40500,52000"
st "addr : (9:0)"
blo "36000,51800"
tm "WireNameMgr"
)
)
on &57
)
*127 (Wire
uid 271,0
shape (OrthoPolyLine
uid 272,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "34750,53000,51000,53000"
pts [
"34750,53000"
"51000,53000"
]
)
start &9
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 275,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 276,0
va (VaSet
)
xt "36000,52000,40800,53000"
st "data : (15:0)"
blo "36000,52800"
tm "WireNameMgr"
)
)
on &58
)
*128 (Wire
uid 279,0
shape (OrthoPolyLine
uid 280,0
va (VaSet
vasetType 3
)
xt "34750,54000,51000,54000"
pts [
"34750,54000"
"51000,54000"
]
)
start &10
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 283,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 284,0
va (VaSet
)
xt "36000,53000,37200,54000"
st "cs"
blo "36000,53800"
tm "WireNameMgr"
)
)
on &59
)
*129 (Wire
uid 287,0
shape (OrthoPolyLine
uid 288,0
va (VaSet
vasetType 3
)
xt "34750,55000,51000,55000"
pts [
"34750,55000"
"51000,55000"
]
)
start &11
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 291,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 292,0
va (VaSet
)
xt "36000,54000,37200,55000"
st "wr"
blo "36000,54800"
tm "WireNameMgr"
)
)
on &60
)
*130 (Wire
uid 295,0
shape (OrthoPolyLine
uid 296,0
va (VaSet
vasetType 3
)
xt "34750,56000,51000,56000"
pts [
"34750,56000"
"51000,56000"
]
)
start &12
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 299,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 300,0
va (VaSet
)
xt "36000,55000,37100,56000"
st "rd"
blo "36000,55800"
tm "WireNameMgr"
)
)
on &61
)
*131 (Wire
uid 311,0
shape (OrthoPolyLine
uid 312,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "34750,58000,51000,58000"
pts [
"34750,58000"
"51000,58000"
]
)
start &17
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 315,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 316,0
va (VaSet
)
xt "36000,57000,42600,58000"
st "ram_addr : (13:0)"
blo "36000,57800"
tm "WireNameMgr"
)
)
on &62
)
*132 (Wire
uid 319,0
shape (OrthoPolyLine
uid 320,0
va (VaSet
vasetType 3
)
xt "34750,59000,51000,59000"
pts [
"34750,59000"
"51000,59000"
]
)
start &19
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 323,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 324,0
va (VaSet
)
xt "36000,58000,41600,59000"
st "data_valid_ack"
blo "36000,58800"
tm "WireNameMgr"
)
)
on &63
)
*133 (Wire
uid 327,0
shape (OrthoPolyLine
uid 328,0
va (VaSet
vasetType 3
)
xt "34750,60000,51000,60000"
pts [
"34750,60000"
"51000,60000"
]
)
start &20
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 331,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 332,0
va (VaSet
)
xt "36000,59000,37900,60000"
st "busy"
blo "36000,59800"
tm "WireNameMgr"
)
)
on &64
)
*134 (Wire
uid 335,0
shape (OrthoPolyLine
uid 336,0
va (VaSet
vasetType 3
)
xt "34750,61000,51000,61000"
pts [
"34750,61000"
"51000,61000"
]
)
start &24
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 339,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 340,0
va (VaSet
)
xt "36000,60000,39600,61000"
st "s_trigger"
blo "36000,60800"
tm "WireNameMgr"
)
)
on &65
)
*135 (Wire
uid 343,0
shape (OrthoPolyLine
uid 344,0
va (VaSet
vasetType 3
)
xt "34750,62000,51000,62000"
pts [
"34750,62000"
"51000,62000"
]
)
start &25
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 347,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 348,0
va (VaSet
)
xt "36000,61000,42600,62000"
st "c_trigger_enable"
blo "36000,61800"
tm "WireNameMgr"
)
)
on &66
)
*136 (Wire
uid 351,0
shape (OrthoPolyLine
uid 352,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "34750,63000,51000,63000"
pts [
"34750,63000"
"51000,63000"
]
)
start &26
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 355,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 356,0
va (VaSet
)
xt "36000,62000,44800,63000"
st "c_trigger_mult : (15:0)"
blo "36000,62800"
tm "WireNameMgr"
)
)
on &67
)
*137 (Wire
uid 359,0
shape (OrthoPolyLine
uid 360,0
va (VaSet
vasetType 3
)
xt "34750,64000,51000,64000"
pts [
"34750,64000"
"51000,64000"
]
)
start &27
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 363,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 364,0
va (VaSet
)
xt "36000,63000,48400,64000"
st "memory_manager_config_start_o"
blo "36000,63800"
tm "WireNameMgr"
)
)
on &68
)
*138 (Wire
uid 367,0
shape (OrthoPolyLine
uid 368,0
va (VaSet
vasetType 3
)
xt "34750,65000,51000,65000"
pts [
"34750,65000"
"51000,65000"
]
)
start &29
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 371,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 372,0
va (VaSet
)
xt "36000,64000,46700,65000"
st "spi_interface_config_start_o"
blo "36000,64800"
tm "WireNameMgr"
)
)
on &69
)
*139 (Wire
uid 375,0
shape (OrthoPolyLine
uid 376,0
va (VaSet
vasetType 3
)
xt "34750,66000,51000,66000"
pts [
"34750,66000"
"51000,66000"
]
)
start &31
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 379,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 380,0
va (VaSet
)
xt "36000,65000,40700,66000"
st "dac_setting"
blo "36000,65800"
tm "WireNameMgr"
)
)
on &70
)
*140 (Wire
uid 383,0
shape (OrthoPolyLine
uid 384,0
va (VaSet
vasetType 3
)
xt "34750,67000,51000,67000"
pts [
"34750,67000"
"51000,67000"
]
)
start &32
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 387,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 388,0
va (VaSet
)
xt "36000,66000,40400,67000"
st "roi_setting"
blo "36000,66800"
tm "WireNameMgr"
)
)
on &71
)
*141 (Wire
uid 391,0
shape (OrthoPolyLine
uid 392,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "34750,68000,51000,68000"
pts [
"34750,68000"
"51000,68000"
]
)
start &33
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 395,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 396,0
va (VaSet
)
xt "36000,67000,43000,68000"
st "runnumber : (31:0)"
blo "36000,67800"
tm "WireNameMgr"
)
)
on &72
)
*142 (Wire
uid 399,0
shape (OrthoPolyLine
uid 400,0
va (VaSet
vasetType 3
)
xt "34750,69000,51000,69000"
pts [
"34750,69000"
"51000,69000"
]
)
start &34
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 403,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 404,0
va (VaSet
)
xt "36000,68000,42300,69000"
st "reset_trigger_id"
blo "36000,68800"
tm "WireNameMgr"
)
)
on &73
)
*143 (Wire
uid 407,0
shape (OrthoPolyLine
uid 408,0
va (VaSet
vasetType 3
)
xt "34750,70000,51000,70000"
pts [
"34750,70000"
"51000,70000"
]
)
start &39
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 411,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 412,0
va (VaSet
)
xt "36000,69000,41800,70000"
st "trigger_enable"
blo "36000,69800"
tm "WireNameMgr"
)
)
on &74
)
*144 (Wire
uid 415,0
shape (OrthoPolyLine
uid 416,0
va (VaSet
vasetType 3
)
xt "34750,71000,51000,71000"
pts [
"34750,71000"
"51000,71000"
]
)
start &40
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 419,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 420,0
va (VaSet
)
xt "36000,70000,39000,71000"
st "denable"
blo "36000,70800"
tm "WireNameMgr"
)
)
on &75
)
*145 (Wire
uid 423,0
shape (OrthoPolyLine
uid 424,0
va (VaSet
vasetType 3
)
xt "34750,72000,51000,72000"
pts [
"34750,72000"
"51000,72000"
]
)
start &41
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 427,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 428,0
va (VaSet
)
xt "36000,71000,41400,72000"
st "dwrite_enable"
blo "36000,71800"
tm "WireNameMgr"
)
)
on &76
)
*146 (Wire
uid 431,0
shape (OrthoPolyLine
uid 432,0
va (VaSet
vasetType 3
)
xt "34750,73000,51000,73000"
pts [
"34750,73000"
"51000,73000"
]
)
start &42
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 435,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 436,0
va (VaSet
)
xt "36000,72000,40700,73000"
st "sclk_enable"
blo "36000,72800"
tm "WireNameMgr"
)
)
on &77
)
*147 (Wire
uid 439,0
shape (OrthoPolyLine
uid 440,0
va (VaSet
vasetType 3
)
xt "34750,74000,51000,74000"
pts [
"34750,74000"
"51000,74000"
]
)
start &43
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 443,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 444,0
va (VaSet
)
xt "36000,73000,41000,74000"
st "srclk_enable"
blo "36000,73800"
tm "WireNameMgr"
)
)
on &78
)
*148 (Wire
uid 447,0
shape (OrthoPolyLine
uid 448,0
va (VaSet
vasetType 3
)
xt "34750,75000,51000,75000"
pts [
"34750,75000"
"51000,75000"
]
)
start &44
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 451,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 452,0
va (VaSet
)
xt "36000,74000,40900,75000"
st "ps_direction"
blo "36000,74800"
tm "WireNameMgr"
)
)
on &79
)
*149 (Wire
uid 455,0
shape (OrthoPolyLine
uid 456,0
va (VaSet
vasetType 3
)
xt "34750,76000,51000,76000"
pts [
"34750,76000"
"51000,76000"
]
)
start &45
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 459,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 460,0
va (VaSet
)
xt "36000,75000,43000,76000"
st "ps_do_phase_shift"
blo "36000,75800"
tm "WireNameMgr"
)
)
on &80
)
*150 (Wire
uid 463,0
shape (OrthoPolyLine
uid 464,0
va (VaSet
vasetType 3
)
xt "34750,77000,51000,77000"
pts [
"34750,77000"
"51000,77000"
]
)
start &46
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 467,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 468,0
va (VaSet
)
xt "36000,76000,39300,77000"
st "ps_reset"
blo "36000,76800"
tm "WireNameMgr"
)
)
on &81
)
*151 (Wire
uid 471,0
shape (OrthoPolyLine
uid 472,0
va (VaSet
vasetType 3
)
xt "34750,78000,51000,78000"
pts [
"34750,78000"
"51000,78000"
]
)
start &48
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 475,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 476,0
va (VaSet
)
xt "36000,77000,41500,78000"
st "socks_waiting"
blo "36000,77800"
tm "WireNameMgr"
)
)
on &82
)
*152 (Wire
uid 479,0
shape (OrthoPolyLine
uid 480,0
va (VaSet
vasetType 3
)
xt "34750,79000,51000,79000"
pts [
"34750,79000"
"51000,79000"
]
)
start &49
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 483,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 484,0
va (VaSet
)
xt "36000,78000,42500,79000"
st "socks_connected"
blo "36000,78800"
tm "WireNameMgr"
)
)
on &83
)
*153 (Wire
uid 487,0
shape (OrthoPolyLine
uid 488,0
va (VaSet
vasetType 3
)
xt "-19000,47000,-750,47000"
pts [
"-19000,47000"
"-750,47000"
]
)
end &5
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 491,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 492,0
va (VaSet
)
xt "-18000,46000,-9500,47000"
st "data_generator_idle_i"
blo "-18000,46800"
tm "WireNameMgr"
)
)
on &84
)
*154 (Wire
uid 495,0
shape (OrthoPolyLine
uid 496,0
va (VaSet
vasetType 3
)
xt "-19000,48000,-750,48000"
pts [
"-19000,48000"
"-750,48000"
]
)
end &6
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 499,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 500,0
va (VaSet
)
xt "-18000,47000,-16700,48000"
st "clk"
blo "-18000,47800"
tm "WireNameMgr"
)
)
on &85
)
*155 (Wire
uid 503,0
shape (OrthoPolyLine
uid 504,0
va (VaSet
vasetType 3
)
xt "-19000,49000,-750,49000"
pts [
"-19000,49000"
"-750,49000"
]
)
end &13
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 507,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 508,0
va (VaSet
)
xt "-18000,48000,-16800,49000"
st "int"
blo "-18000,48800"
tm "WireNameMgr"
)
)
on &86
)
*156 (Wire
uid 511,0
shape (OrthoPolyLine
uid 512,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-19000,50000,-750,50000"
pts [
"-19000,50000"
"-750,50000"
]
)
end &14
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 515,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 516,0
va (VaSet
)
xt "-18000,49000,-10100,50000"
st "write_length : (16:0)"
blo "-18000,49800"
tm "WireNameMgr"
)
)
on &87
)
*157 (Wire
uid 519,0
shape (OrthoPolyLine
uid 520,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-19000,51000,-750,51000"
pts [
"-19000,51000"
"-750,51000"
]
)
end &15
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 523,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 524,0
va (VaSet
)
xt "-18000,50000,-9100,51000"
st "ram_start_addr : (13:0)"
blo "-18000,50800"
tm "WireNameMgr"
)
)
on &88
)
*158 (Wire
uid 527,0
shape (OrthoPolyLine
uid 528,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-19000,52000,-750,52000"
pts [
"-19000,52000"
"-750,52000"
]
)
end &16
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 531,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 532,0
va (VaSet
)
xt "-18000,51000,-11500,52000"
st "ram_data : (15:0)"
blo "-18000,51800"
tm "WireNameMgr"
)
)
on &89
)
*159 (Wire
uid 535,0
shape (OrthoPolyLine
uid 536,0
va (VaSet
vasetType 3
)
xt "-19000,53000,-750,53000"
pts [
"-19000,53000"
"-750,53000"
]
)
end &18
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 539,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 540,0
va (VaSet
)
xt "-18000,52000,-13900,53000"
st "data_valid"
blo "-18000,52800"
tm "WireNameMgr"
)
)
on &90
)
*160 (Wire
uid 543,0
shape (OrthoPolyLine
uid 544,0
va (VaSet
vasetType 3
)
xt "-19000,54000,-750,54000"
pts [
"-19000,54000"
"-750,54000"
]
)
end &21
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 547,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 548,0
va (VaSet
)
xt "-18000,53000,-11200,54000"
st "write_header_flag"
blo "-18000,53800"
tm "WireNameMgr"
)
)
on &91
)
*161 (Wire
uid 551,0
shape (OrthoPolyLine
uid 552,0
va (VaSet
vasetType 3
)
xt "-19000,55000,-750,55000"
pts [
"-19000,55000"
"-750,55000"
]
)
end &22
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 555,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 556,0
va (VaSet
)
xt "-18000,54000,-12300,55000"
st "write_end_flag"
blo "-18000,54800"
tm "WireNameMgr"
)
)
on &92
)
*162 (Wire
uid 559,0
shape (OrthoPolyLine
uid 560,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-19000,56000,-750,56000"
pts [
"-19000,56000"
"-750,56000"
]
)
end &23
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 563,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 564,0
va (VaSet
)
xt "-18000,55000,-10200,56000"
st "fifo_channels : (3:0)"
blo "-18000,55800"
tm "WireNameMgr"
)
)
on &93
)
*163 (Wire
uid 567,0
shape (OrthoPolyLine
uid 568,0
va (VaSet
vasetType 3
)
xt "-19000,57000,-750,57000"
pts [
"-19000,57000"
"-750,57000"
]
)
end &28
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 571,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 572,0
va (VaSet
)
xt "-18000,56000,-5800,57000"
st "memory_manager_config_valid_i"
blo "-18000,56800"
tm "WireNameMgr"
)
)
on &94
)
*164 (Wire
uid 575,0
shape (OrthoPolyLine
uid 576,0
va (VaSet
vasetType 3
)
xt "-19000,58000,-750,58000"
pts [
"-19000,58000"
"-750,58000"
]
)
end &30
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 579,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 580,0
va (VaSet
)
xt "-18000,57000,-7500,58000"
st "spi_interface_config_valid_i"
blo "-18000,57800"
tm "WireNameMgr"
)
)
on &95
)
*165 (Wire
uid 583,0
shape (OrthoPolyLine
uid 584,0
va (VaSet
vasetType 3
)
xt "-19000,59000,-750,59000"
pts [
"-19000,59000"
"-750,59000"
]
)
end &35
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 587,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 588,0
va (VaSet
)
xt "-18000,58000,-11800,59000"
st "data_ram_empty"
blo "-18000,58800"
tm "WireNameMgr"
)
)
on &96
)
*166 (Wire
uid 591,0
shape (OrthoPolyLine
uid 592,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-19000,60000,-750,60000"
pts [
"-19000,60000"
"-750,60000"
]
)
end &36
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 595,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 596,0
va (VaSet
)
xt "-18000,59000,-10500,60000"
st "MAC_jumper : (1:0)"
blo "-18000,59800"
tm "WireNameMgr"
)
)
on &97
)
*167 (Wire
uid 599,0
shape (OrthoPolyLine
uid 600,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-19000,61000,-750,61000"
pts [
"-19000,61000"
"-750,61000"
]
)
end &37
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 603,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 604,0
va (VaSet
)
xt "-18000,60000,-12200,61000"
st "BoardID : (3:0)"
blo "-18000,60800"
tm "WireNameMgr"
)
)
on &98
)
*168 (Wire
uid 607,0
shape (OrthoPolyLine
uid 608,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-19000,62000,-750,62000"
pts [
"-19000,62000"
"-750,62000"
]
)
end &38
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 611,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 612,0
va (VaSet
)
xt "-18000,61000,-12300,62000"
st "CrateID : (1:0)"
blo "-18000,61800"
tm "WireNameMgr"
)
)
on &99
)
*169 (Wire
uid 615,0
shape (OrthoPolyLine
uid 616,0
va (VaSet
vasetType 3
)
xt "-19000,63000,-750,63000"
pts [
"-19000,63000"
"-750,63000"
]
)
end &47
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 619,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 620,0
va (VaSet
)
xt "-18000,62000,-14600,63000"
st "ps_ready"
blo "-18000,62800"
tm "WireNameMgr"
)
)
on &100
)
*170 (Wire
uid 639,0
shape (OrthoPolyLine
uid 640,0
va (VaSet
vasetType 3
)
xt "108000,58000,125000,58000"
pts [
"108000,58000"
"125000,58000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 645,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 646,0
va (VaSet
)
xt "109000,57000,114600,58000"
st "data_valid_ack"
blo "109000,57800"
tm "WireNameMgr"
)
)
on &63
)
*171 (Wire
uid 647,0
shape (OrthoPolyLine
uid 648,0
va (VaSet
vasetType 3
)
xt "108000,50000,125000,50000"
pts [
"108000,50000"
"125000,50000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 653,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 654,0
va (VaSet
)
xt "109000,49000,112600,50000"
st "wiz_reset"
blo "109000,49800"
tm "WireNameMgr"
)
)
on &56
)
*172 (Wire
uid 655,0
shape (OrthoPolyLine
uid 656,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "68000,29000,93250,33000"
pts [
"68000,33000"
"93250,29000"
]
)
end &114
es 0
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 661,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 662,0
va (VaSet
)
xt "69000,32000,73800,33000"
st "data : (15:0)"
blo "69000,32800"
tm "WireNameMgr"
)
)
on &58
)
*173 (Wire
uid 663,0
shape (OrthoPolyLine
uid 664,0
va (VaSet
vasetType 3
)
xt "108000,59000,125000,59000"
pts [
"108000,59000"
"125000,59000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 669,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 670,0
va (VaSet
)
xt "109000,58000,110900,59000"
st "busy"
blo "109000,58800"
tm "WireNameMgr"
)
)
on &64
)
*174 (Wire
uid 671,0
shape (OrthoPolyLine
uid 672,0
va (VaSet
vasetType 3
)
xt "108000,63000,125000,63000"
pts [
"108000,63000"
"125000,63000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 677,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 678,0
va (VaSet
)
xt "109000,62000,121400,63000"
st "memory_manager_config_start_o"
blo "109000,62800"
tm "WireNameMgr"
)
)
on &68
)
*175 (Wire
uid 679,0
shape (OrthoPolyLine
uid 680,0
va (VaSet
vasetType 3
)
xt "108000,47000,125000,47000"
pts [
"108000,47000"
"125000,47000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 685,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 686,0
va (VaSet
)
xt "109000,46000,118100,47000"
st "debug_data_ram_empty"
blo "109000,46800"
tm "WireNameMgr"
)
)
on &54
)
*176 (Wire
uid 687,0
shape (OrthoPolyLine
uid 688,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "108000,46000,125000,46000"
pts [
"108000,46000"
"125000,46000"
]
)
start &101
sat 1
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 693,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 694,0
va (VaSet
)
xt "109000,45000,113600,46000"
st "state : (7:0)"
blo "109000,45800"
tm "WireNameMgr"
)
)
on &53
)
*177 (Wire
uid 695,0
shape (OrthoPolyLine
uid 696,0
va (VaSet
vasetType 3
)
xt "108000,61000,125000,61000"
pts [
"108000,61000"
"125000,61000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 701,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 702,0
va (VaSet
)
xt "109000,60000,115600,61000"
st "c_trigger_enable"
blo "109000,60800"
tm "WireNameMgr"
)
)
on &66
)
*178 (Wire
uid 711,0
shape (OrthoPolyLine
uid 712,0
va (VaSet
vasetType 3
)
xt "108000,48000,125000,48000"
pts [
"108000,48000"
"125000,48000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 717,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 718,0
va (VaSet
)
xt "109000,47000,115600,48000"
st "debug_data_valid"
blo "109000,47800"
tm "WireNameMgr"
)
)
on &55
)
*179 (Wire
uid 719,0
shape (OrthoPolyLine
uid 720,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "108000,57000,125000,57000"
pts [
"108000,57000"
"125000,57000"
]
)
start &101
sat 1
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 725,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 726,0
va (VaSet
)
xt "110000,56000,116600,57000"
st "ram_addr : (13:0)"
blo "110000,56800"
tm "WireNameMgr"
)
)
on &62
)
*180 (Wire
uid 727,0
shape (OrthoPolyLine
uid 728,0
va (VaSet
vasetType 3
)
xt "108000,60000,125000,60000"
pts [
"108000,60000"
"125000,60000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 733,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 734,0
va (VaSet
)
xt "109000,59000,112600,60000"
st "s_trigger"
blo "109000,59800"
tm "WireNameMgr"
)
)
on &65
)
*181 (Wire
uid 735,0
shape (OrthoPolyLine
uid 736,0
va (VaSet
vasetType 3
)
xt "71000,33000,93250,34000"
pts [
"71000,34000"
"93250,33000"
]
)
end &116
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 741,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 742,0
va (VaSet
)
xt "72000,33000,73200,34000"
st "wr"
blo "72000,33800"
tm "WireNameMgr"
)
)
on &60
)
*182 (Wire
uid 743,0
shape (OrthoPolyLine
uid 744,0
va (VaSet
vasetType 3
)
xt "63000,32000,93250,35000"
pts [
"63000,35000"
"93250,32000"
]
)
end &115
es 0
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 749,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 750,0
va (VaSet
)
xt "64000,34000,65100,35000"
st "rd"
blo "64000,34800"
tm "WireNameMgr"
)
)
on &61
)
*183 (Wire
uid 751,0
shape (OrthoPolyLine
uid 752,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "70000,28000,93250,30000"
pts [
"70000,30000"
"93250,28000"
]
)
end &113
es 0
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 757,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 758,0
va (VaSet
)
xt "71000,29000,75500,30000"
st "addr : (9:0)"
blo "71000,29800"
tm "WireNameMgr"
)
)
on &57
)
*184 (Wire
uid 759,0
shape (OrthoPolyLine
uid 760,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "108000,67000,125000,67000"
pts [
"108000,67000"
"125000,67000"
]
)
start &101
sat 1
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 765,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 766,0
va (VaSet
)
xt "109000,66000,116000,67000"
st "runnumber : (31:0)"
blo "109000,66800"
tm "WireNameMgr"
)
)
on &72
)
*185 (Wire
uid 767,0
shape (OrthoPolyLine
uid 768,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "55000,49000,74000,49000"
pts [
"55000,49000"
"74000,49000"
]
)
end &101
sat 16
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 773,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 774,0
va (VaSet
)
xt "56000,48000,63900,49000"
st "write_length : (16:0)"
blo "56000,48800"
tm "WireNameMgr"
)
)
on &87
)
*186 (Wire
uid 775,0
shape (OrthoPolyLine
uid 776,0
va (VaSet
vasetType 3
)
xt "108000,70000,125000,70000"
pts [
"108000,70000"
"125000,70000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 781,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 782,0
va (VaSet
)
xt "109000,69000,112000,70000"
st "denable"
blo "109000,69800"
tm "WireNameMgr"
)
)
on &75
)
*187 (Wire
uid 783,0
shape (OrthoPolyLine
uid 784,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "55000,50000,74000,50000"
pts [
"55000,50000"
"74000,50000"
]
)
end &101
sat 16
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 789,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 790,0
va (VaSet
)
xt "57000,49000,65900,50000"
st "ram_start_addr : (13:0)"
blo "57000,49800"
tm "WireNameMgr"
)
)
on &88
)
*188 (Wire
uid 791,0
shape (OrthoPolyLine
uid 792,0
va (VaSet
vasetType 3
)
xt "108000,71000,125000,71000"
pts [
"108000,71000"
"125000,71000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 797,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 798,0
va (VaSet
)
xt "109000,70000,114400,71000"
st "dwrite_enable"
blo "109000,70800"
tm "WireNameMgr"
)
)
on &76
)
*189 (Wire
uid 799,0
shape (OrthoPolyLine
uid 800,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "55000,51000,74000,51000"
pts [
"55000,51000"
"74000,51000"
]
)
end &101
sat 16
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 805,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 806,0
va (VaSet
)
xt "56000,50000,62500,51000"
st "ram_data : (15:0)"
blo "56000,50800"
tm "WireNameMgr"
)
)
on &89
)
*190 (Wire
uid 807,0
shape (OrthoPolyLine
uid 808,0
va (VaSet
vasetType 3
)
xt "108000,73000,125000,73000"
pts [
"108000,73000"
"125000,73000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 813,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 814,0
va (VaSet
)
xt "109000,72000,114000,73000"
st "srclk_enable"
blo "109000,72800"
tm "WireNameMgr"
)
)
on &78
)
*191 (Wire
uid 815,0
shape (OrthoPolyLine
uid 816,0
va (VaSet
vasetType 3
)
xt "108000,68000,125000,68000"
pts [
"108000,68000"
"125000,68000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 821,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 822,0
va (VaSet
)
xt "109000,67000,115300,68000"
st "reset_trigger_id"
blo "109000,67800"
tm "WireNameMgr"
)
)
on &73
)
*192 (Wire
uid 823,0
shape (OrthoPolyLine
uid 824,0
va (VaSet
vasetType 3
)
xt "108000,74000,125000,74000"
pts [
"108000,74000"
"125000,74000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 829,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 830,0
va (VaSet
)
xt "109000,73000,113900,74000"
st "ps_direction"
blo "109000,73800"
tm "WireNameMgr"
)
)
on &79
)
*193 (Wire
uid 831,0
shape (OrthoPolyLine
uid 832,0
va (VaSet
vasetType 3
)
xt "108000,65000,125000,65000"
pts [
"108000,65000"
"125000,65000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 837,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 838,0
va (VaSet
)
xt "109000,64000,113700,65000"
st "dac_setting"
blo "109000,64800"
tm "WireNameMgr"
)
)
on &70
)
*194 (Wire
uid 839,0
shape (OrthoPolyLine
uid 840,0
va (VaSet
vasetType 3
)
xt "108000,69000,125000,69000"
pts [
"108000,69000"
"125000,69000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 845,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 846,0
va (VaSet
)
xt "109000,68000,114800,69000"
st "trigger_enable"
blo "109000,68800"
tm "WireNameMgr"
)
)
on &74
)
*195 (Wire
uid 847,0
shape (OrthoPolyLine
uid 848,0
va (VaSet
vasetType 3
)
xt "108000,72000,125000,72000"
pts [
"108000,72000"
"125000,72000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 853,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 854,0
va (VaSet
)
xt "109000,71000,113700,72000"
st "sclk_enable"
blo "109000,71800"
tm "WireNameMgr"
)
)
on &77
)
*196 (Wire
uid 855,0
shape (OrthoPolyLine
uid 856,0
va (VaSet
vasetType 3
)
xt "108000,75000,125000,75000"
pts [
"108000,75000"
"125000,75000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 861,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 862,0
va (VaSet
)
xt "109000,74000,116000,75000"
st "ps_do_phase_shift"
blo "109000,74800"
tm "WireNameMgr"
)
)
on &80
)
*197 (Wire
uid 863,0
shape (OrthoPolyLine
uid 864,0
va (VaSet
vasetType 3
)
xt "108000,64000,125000,64000"
pts [
"108000,64000"
"125000,64000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 869,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 870,0
va (VaSet
)
xt "109000,63000,119700,64000"
st "spi_interface_config_start_o"
blo "109000,63800"
tm "WireNameMgr"
)
)
on &69
)
*198 (Wire
uid 871,0
shape (OrthoPolyLine
uid 872,0
va (VaSet
vasetType 3
)
xt "68000,35000,93250,38000"
pts [
"68000,38000"
"93250,35000"
]
)
end &118
es 0
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 877,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 878,0
va (VaSet
)
xt "69000,37000,70200,38000"
st "cs"
blo "69000,37800"
tm "WireNameMgr"
)
)
on &59
)
*199 (Wire
uid 879,0
shape (OrthoPolyLine
uid 880,0
va (VaSet
vasetType 3
)
xt "108000,66000,125000,66000"
pts [
"108000,66000"
"125000,66000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 885,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 886,0
va (VaSet
)
xt "109000,65000,113400,66000"
st "roi_setting"
blo "109000,65800"
tm "WireNameMgr"
)
)
on &71
)
*200 (Wire
uid 887,0
shape (OrthoPolyLine
uid 888,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "108000,62000,125000,62000"
pts [
"108000,62000"
"125000,62000"
]
)
start &101
sat 1
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 893,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 894,0
va (VaSet
)
xt "109000,61000,117800,62000"
st "c_trigger_mult : (15:0)"
blo "109000,61800"
tm "WireNameMgr"
)
)
on &67
)
*201 (Wire
uid 895,0
shape (OrthoPolyLine
uid 896,0
va (VaSet
vasetType 3
)
xt "55000,46000,74000,46000"
pts [
"55000,46000"
"74000,46000"
]
)
end &101
sat 16
eat 2
st 0
sf 1
si 0
tg (WTG
uid 901,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 902,0
va (VaSet
)
xt "56000,45000,64500,46000"
st "data_generator_idle_i"
blo "56000,45800"
tm "WireNameMgr"
)
)
on &84
)
*202 (Wire
uid 903,0
shape (OrthoPolyLine
uid 904,0
va (VaSet
vasetType 3
)
xt "55000,52000,74000,52000"
pts [
"55000,52000"
"74000,52000"
]
)
end &101
sat 16
eat 2
st 0
sf 1
si 0
tg (WTG
uid 909,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 910,0
va (VaSet
)
xt "56000,51000,60100,52000"
st "data_valid"
blo "56000,51800"
tm "WireNameMgr"
)
)
on &90
)
*203 (Wire
uid 911,0
shape (OrthoPolyLine
uid 912,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "55000,55000,74000,55000"
pts [
"55000,55000"
"74000,55000"
]
)
end &101
sat 16
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 917,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 918,0
va (VaSet
)
xt "56000,54000,63800,55000"
st "fifo_channels : (3:0)"
blo "56000,54800"
tm "WireNameMgr"
)
)
on &93
)
*204 (Wire
uid 919,0
shape (OrthoPolyLine
uid 920,0
va (VaSet
vasetType 3
)
xt "55000,54000,74000,54000"
pts [
"55000,54000"
"74000,54000"
]
)
end &101
sat 16
eat 2
st 0
sf 1
si 0
tg (WTG
uid 925,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 926,0
va (VaSet
)
xt "56000,53000,61700,54000"
st "write_end_flag"
blo "56000,53800"
tm "WireNameMgr"
)
)
on &92
)
*205 (Wire
uid 927,0
shape (OrthoPolyLine
uid 928,0
va (VaSet
vasetType 3
)
xt "55000,56000,74000,56000"
pts [
"55000,56000"
"74000,56000"
]
)
end &101
sat 16
eat 2
st 0
sf 1
si 0
tg (WTG
uid 933,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 934,0
va (VaSet
)
xt "56000,55000,68200,56000"
st "memory_manager_config_valid_i"
blo "56000,55800"
tm "WireNameMgr"
)
)
on &94
)
*206 (Wire
uid 935,0
shape (OrthoPolyLine
uid 936,0
va (VaSet
vasetType 3
)
xt "55000,58000,74000,58000"
pts [
"55000,58000"
"74000,58000"
]
)
end &101
sat 16
eat 2
st 0
sf 1
si 0
tg (WTG
uid 941,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 942,0
va (VaSet
)
xt "56000,57000,62200,58000"
st "data_ram_empty"
blo "56000,57800"
tm "WireNameMgr"
)
)
on &96
)
*207 (Wire
uid 943,0
shape (OrthoPolyLine
uid 944,0
va (VaSet
vasetType 3
)
xt "55000,57000,74000,57000"
pts [
"55000,57000"
"74000,57000"
]
)
end &101
sat 16
eat 2
st 0
sf 1
si 0
tg (WTG
uid 949,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 950,0
va (VaSet
)
xt "56000,56000,66500,57000"
st "spi_interface_config_valid_i"
blo "56000,56800"
tm "WireNameMgr"
)
)
on &95
)
*208 (Wire
uid 951,0
shape (OrthoPolyLine
uid 952,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "55000,59000,74000,59000"
pts [
"55000,59000"
"74000,59000"
]
)
end &101
sat 16
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 957,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 958,0
va (VaSet
)
xt "56000,58000,63500,59000"
st "MAC_jumper : (1:0)"
blo "56000,58800"
tm "WireNameMgr"
)
)
on &97
)
*209 (Wire
uid 959,0
shape (OrthoPolyLine
uid 960,0
va (VaSet
vasetType 3
)
xt "108000,76000,125000,76000"
pts [
"108000,76000"
"125000,76000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 965,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 966,0
va (VaSet
)
xt "109000,75000,112300,76000"
st "ps_reset"
blo "109000,75800"
tm "WireNameMgr"
)
)
on &81
)
*210 (Wire
uid 967,0
shape (OrthoPolyLine
uid 968,0
va (VaSet
vasetType 3
)
xt "108000,77000,125000,77000"
pts [
"108000,77000"
"125000,77000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 973,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 974,0
va (VaSet
)
xt "109000,76000,114500,77000"
st "socks_waiting"
blo "109000,76800"
tm "WireNameMgr"
)
)
on &82
)
*211 (Wire
uid 975,0
shape (OrthoPolyLine
uid 976,0
va (VaSet
vasetType 3
)
xt "55000,53000,74000,53000"
pts [
"55000,53000"
"74000,53000"
]
)
end &101
sat 16
eat 2
st 0
sf 1
si 0
tg (WTG
uid 981,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 982,0
va (VaSet
)
xt "56000,52000,62800,53000"
st "write_header_flag"
blo "56000,52800"
tm "WireNameMgr"
)
)
on &91
)
*212 (Wire
uid 983,0
shape (OrthoPolyLine
uid 984,0
va (VaSet
vasetType 3
)
xt "108000,78000,125000,78000"
pts [
"108000,78000"
"125000,78000"
]
)
start &101
sat 1
eat 16
st 0
sf 1
si 0
tg (WTG
uid 989,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 990,0
va (VaSet
)
xt "109000,77000,115500,78000"
st "socks_connected"
blo "109000,77800"
tm "WireNameMgr"
)
)
on &83
)
*213 (Wire
uid 991,0
shape (OrthoPolyLine
uid 992,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "55000,60000,74000,60000"
pts [
"55000,60000"
"74000,60000"
]
)
end &101
sat 16
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 997,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 998,0
va (VaSet
)
xt "56000,59000,61800,60000"
st "BoardID : (3:0)"
blo "56000,59800"
tm "WireNameMgr"
)
)
on &98
)
*214 (Wire
uid 999,0
shape (OrthoPolyLine
uid 1000,0
va (VaSet
vasetType 3
)
xt "55000,62000,74000,62000"
pts [
"55000,62000"
"74000,62000"
]
)
end &101
sat 16
eat 2
st 0
sf 1
si 0
tg (WTG
uid 1005,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1006,0
va (VaSet
)
xt "56000,61000,59400,62000"
st "ps_ready"
blo "56000,61800"
tm "WireNameMgr"
)
)
on &100
)
*215 (Wire
uid 1007,0
shape (OrthoPolyLine
uid 1008,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "55000,61000,74000,61000"
pts [
"55000,61000"
"74000,61000"
]
)
end &101
sat 16
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 1013,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1014,0
va (VaSet
)
xt "56000,60000,61700,61000"
st "CrateID : (1:0)"
blo "56000,60800"
tm "WireNameMgr"
)
)
on &99
)
*216 (Wire
uid 1015,0
shape (OrthoPolyLine
uid 1016,0
va (VaSet
vasetType 3
)
xt "108750,27000,124000,28000"
pts [
"108750,28000"
"124000,27000"
]
)
start &117
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1021,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1022,0
va (VaSet
)
xt "110000,27000,111200,28000"
st "int"
blo "110000,27800"
tm "WireNameMgr"
)
)
on &86
)
*217 (Wire
uid 1023,0
shape (OrthoPolyLine
uid 1024,0
va (VaSet
vasetType 3
)
xt "55000,47000,74000,47000"
pts [
"55000,47000"
"74000,47000"
]
)
end &101
sat 16
eat 1
st 0
sf 1
si 0
tg (WTG
uid 1029,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1030,0
va (VaSet
)
xt "56000,46000,57300,47000"
st "clk"
blo "56000,46800"
tm "WireNameMgr"
)
)
on &85
)
*218 (Wire
uid 1552,0
shape (OrthoPolyLine
uid 1553,0
va (VaSet
vasetType 3
)
xt "80750,20000,84000,20000"
pts [
"80750,20000"
"84000,20000"
]
)
start &106
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 1556,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1557,0
va (VaSet
)
xt "82000,19000,83300,20000"
st "clk"
blo "82000,19800"
tm "WireNameMgr"
)
)
on &85
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *219 (PackageList
uid 1163,0
stg "VerticalLayoutStrategy"
textVec [
*220 (Text
uid 1164,0
va (VaSet
font "arial,8,1"
)
xt "0,0,5400,1000"
st "Package List"
blo "0,800"
)
*221 (MLText
uid 1165,0
va (VaSet
)
xt "0,1000,15600,7000"
st "LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY FACT_FAD_lib;
USE FACT_FAD_lib.fad_definitions.ALL;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 1166,0
stg "VerticalLayoutStrategy"
textVec [
*222 (Text
uid 1167,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,28100,1000"
st "Compiler Directives"
blo "20000,800"
)
*223 (Text
uid 1168,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,1000,29600,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*224 (MLText
uid 1169,0
va (VaSet
isHidden 1
)
xt "20000,2000,27500,4000"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*225 (Text
uid 1170,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,4000,30100,5000"
st "Post-module directives:"
blo "20000,4800"
)
*226 (MLText
uid 1171,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*227 (Text
uid 1172,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,5000,29900,6000"
st "End-module directives:"
blo "20000,5800"
)
*228 (MLText
uid 1173,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "0,22,1281,1024"
viewArea "-24461,12268,58572,79024"
cachedDiagramExtent "-19400,0,125400,83000"
hasePageBreakOrigin 1
pageBreakOrigin "-20000,0"
lastUid 2880,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,2000,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Arial,8,1"
)
xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*229 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,3500,5800,4500"
st "<library>"
blo "2200,4300"
tm "BdLibraryNameMgr"
)
*230 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,4500,5600,5500"
st "<block>"
blo "2200,5300"
tm "BlkNameMgr"
)
*231 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,5500,4000,6500"
st "U_0"
blo "2200,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "2200,13500,2200,13500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*232 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,3500,3450,4500"
st "Library"
blo "550,4300"
)
*233 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,4500,7450,5500"
st "MWComponent"
blo "550,5300"
)
*234 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,5500,2350,6500"
st "U_0"
blo "550,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6450,1500,-6450,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*235 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,3500,3800,4500"
st "Library"
blo "900,4300"
tm "BdLibraryNameMgr"
)
*236 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,4500,7100,5500"
st "SaComponent"
blo "900,5300"
tm "CptNameMgr"
)
*237 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,5500,2700,6500"
st "U_0"
blo "900,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6100,1500,-6100,1500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*238 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,3500,3400,4500"
st "Library"
blo "500,4300"
)
*239 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,4500,7500,5500"
st "VhdlComponent"
blo "500,5300"
)
*240 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,5500,2300,6500"
st "U_0"
blo "500,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6500,1500,-6500,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-450,0,8450,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*241 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,3500,2950,4500"
st "Library"
blo "50,4300"
)
*242 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,4500,7950,5500"
st "VerilogComponent"
blo "50,5300"
)
*243 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,5500,1850,6500"
st "U_0"
blo "50,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6950,1500,-6950,1500"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*244 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,4000,4850,5000"
st "eb1"
blo "3150,4800"
tm "HdlTextNameMgr"
)
*245 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,5000,3950,6000"
st "1"
blo "3150,5800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,2000,1200"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
font "Arial,8,1"
)
xt "-500,-500,500,500"
st "G"
blo "-500,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,1900,1000"
st "sig0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,2400,1000"
st "dbus0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineColor "32768,0,0"
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,3000,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1000,1000,2000"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
)
second (MLText
va (VaSet
)
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,12600,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*246 (Text
va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*247 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,7400,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*248 (Text
va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*249 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Courier New,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Arial,8,1"
)
xt "20000,0,25400,1000"
st "Declarations"
blo "20000,800"
)
portLabel (Text
uid 3,0
va (VaSet
font "Arial,8,1"
)
xt "20000,1000,22700,2000"
st "Ports:"
blo "20000,1800"
)
preUserLabel (Text
uid 4,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,23800,1000"
st "Pre User:"
blo "20000,800"
)
preUserText (MLText
uid 5,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "20000,0,20000,0"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Arial,8,1"
)
xt "20000,2000,27100,3000"
st "Diagram Signals:"
blo "20000,2800"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,24700,1000"
st "Post User:"
blo "20000,800"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "20000,0,20000,0"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 50,0
usingSuid 1
emptyRow *250 (LEmptyRow
)
uid 1176,0
optionalChildren [
*251 (RefLabelRowHdr
)
*252 (TitleRowHdr
)
*253 (FilterRowHdr
)
*254 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*255 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*256 (GroupColHdr
tm "GroupColHdrMgr"
)
*257 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*258 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*259 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*260 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*261 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*262 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*263 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 1
suid 1,0
)
)
uid 1063,0
)
*264 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 2
suid 2,0
)
)
uid 1065,0
)
*265 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "debug_data_valid"
t "std_logic"
o 3
suid 3,0
)
)
uid 1067,0
)
*266 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "wiz_reset"
t "std_logic"
o 5
suid 5,0
)
)
uid 1071,0
)
*267 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 6
suid 6,0
)
)
uid 1073,0
)
*268 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 7
suid 7,0
i "(others => 'Z')"
)
)
uid 1075,0
)
*269 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "cs"
t "std_logic"
o 8
suid 8,0
)
)
uid 1077,0
)
*270 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "wr"
t "std_logic"
o 9
suid 9,0
)
)
uid 1079,0
)
*271 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "rd"
t "std_logic"
o 10
suid 10,0
)
)
uid 1081,0
)
*272 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "ram_addr"
t "std_logic_vector"
b "(13 DOWNTO 0)"
o 12
suid 12,0
)
)
uid 1085,0
)
*273 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "data_valid_ack"
t "std_logic"
o 13
suid 13,0
)
)
uid 1087,0
)
*274 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "busy"
t "std_logic"
o 14
suid 14,0
)
)
uid 1089,0
)
*275 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "s_trigger"
t "std_logic"
o 15
suid 15,0
)
)
uid 1091,0
)
*276 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "c_trigger_enable"
t "std_logic"
o 16
suid 16,0
)
)
uid 1093,0
)
*277 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "c_trigger_mult"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 17
suid 17,0
)
)
uid 1095,0
)
*278 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "memory_manager_config_start_o"
t "std_logic"
o 18
suid 18,0
)
)
uid 1097,0
)
*279 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "spi_interface_config_start_o"
t "std_logic"
o 19
suid 19,0
)
)
uid 1099,0
)
*280 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "dac_setting"
t "dac_array_type"
o 20
suid 20,0
)
)
uid 1101,0
)
*281 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "roi_setting"
t "roi_array_type"
o 21
suid 21,0
)
)
uid 1103,0
)
*282 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "runnumber"
t "std_logic_vector"
b "(31 DOWNTO 0)"
o 22
suid 22,0
)
)
uid 1105,0
)
*283 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "reset_trigger_id"
t "std_logic"
o 23
suid 23,0
)
)
uid 1107,0
)
*284 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "trigger_enable"
t "std_logic"
o 24
suid 24,0
)
)
uid 1109,0
)
*285 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "denable"
t "std_logic"
o 25
suid 25,0
)
)
uid 1111,0
)
*286 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "dwrite_enable"
t "std_logic"
o 26
suid 26,0
)
)
uid 1113,0
)
*287 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "sclk_enable"
t "std_logic"
o 27
suid 27,0
)
)
uid 1115,0
)
*288 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "srclk_enable"
t "std_logic"
o 28
suid 28,0
)
)
uid 1117,0
)
*289 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "ps_direction"
t "std_logic"
o 29
suid 29,0
)
)
uid 1119,0
)
*290 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "ps_do_phase_shift"
t "std_logic"
o 30
suid 30,0
)
)
uid 1121,0
)
*291 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "ps_reset"
t "std_logic"
o 31
suid 31,0
)
)
uid 1123,0
)
*292 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "socks_waiting"
t "std_logic"
o 32
suid 32,0
)
)
uid 1125,0
)
*293 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "socks_connected"
t "std_logic"
o 33
suid 33,0
)
)
uid 1127,0
)
*294 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "data_generator_idle_i"
t "std_logic"
o 34
suid 34,0
)
)
uid 1129,0
)
*295 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "clk"
t "std_logic"
o 35
suid 35,0
)
)
uid 1131,0
)
*296 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "int"
t "std_logic"
o 36
suid 36,0
)
)
uid 1133,0
)
*297 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "write_length"
t "std_logic_vector"
b "(16 DOWNTO 0)"
o 37
suid 37,0
)
)
uid 1135,0
)
*298 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(13 DOWNTO 0)"
o 38
suid 38,0
)
)
uid 1137,0
)
*299 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ram_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 39
suid 39,0
)
)
uid 1139,0
)
*300 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "data_valid"
t "std_logic"
o 40
suid 40,0
)
)
uid 1141,0
)
*301 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "write_header_flag"
t "std_logic"
o 41
suid 41,0
)
)
uid 1143,0
)
*302 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "write_end_flag"
t "std_logic"
o 42
suid 42,0
)
)
uid 1145,0
)
*303 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "fifo_channels"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 43
suid 43,0
)
)
uid 1147,0
)
*304 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memory_manager_config_valid_i"
t "std_logic"
o 44
suid 44,0
)
)
uid 1149,0
)
*305 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "spi_interface_config_valid_i"
t "std_logic"
o 45
suid 45,0
)
)
uid 1151,0
)
*306 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "data_ram_empty"
t "std_logic"
o 46
suid 46,0
)
)
uid 1153,0
)
*307 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "MAC_jumper"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 47
suid 47,0
)
)
uid 1155,0
)
*308 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "BoardID"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 48
suid 48,0
)
)
uid 1157,0
)
*309 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "CrateID"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 49
suid 49,0
)
)
uid 1159,0
)
*310 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ps_ready"
t "std_logic"
o 50
suid 50,0
)
)
uid 1161,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 1189,0
optionalChildren [
*311 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *312 (MRCItem
litem &250
pos 48
dimension 20
)
uid 1191,0
optionalChildren [
*313 (MRCItem
litem &251
pos 0
dimension 20
uid 1192,0
)
*314 (MRCItem
litem &252
pos 1
dimension 23
uid 1193,0
)
*315 (MRCItem
litem &253
pos 2
hidden 1
dimension 20
uid 1194,0
)
*316 (MRCItem
litem &263
pos 0
dimension 20
uid 1064,0
)
*317 (MRCItem
litem &264
pos 1
dimension 20
uid 1066,0
)
*318 (MRCItem
litem &265
pos 2
dimension 20
uid 1068,0
)
*319 (MRCItem
litem &266
pos 3
dimension 20
uid 1072,0
)
*320 (MRCItem
litem &267
pos 4
dimension 20
uid 1074,0
)
*321 (MRCItem
litem &268
pos 5
dimension 20
uid 1076,0
)
*322 (MRCItem
litem &269
pos 6
dimension 20
uid 1078,0
)
*323 (MRCItem
litem &270
pos 7
dimension 20
uid 1080,0
)
*324 (MRCItem
litem &271
pos 8
dimension 20
uid 1082,0
)
*325 (MRCItem
litem &272
pos 9
dimension 20
uid 1086,0
)
*326 (MRCItem
litem &273
pos 10
dimension 20
uid 1088,0
)
*327 (MRCItem
litem &274
pos 11
dimension 20
uid 1090,0
)
*328 (MRCItem
litem &275
pos 12
dimension 20
uid 1092,0
)
*329 (MRCItem
litem &276
pos 13
dimension 20
uid 1094,0
)
*330 (MRCItem
litem &277
pos 14
dimension 20
uid 1096,0
)
*331 (MRCItem
litem &278
pos 15
dimension 20
uid 1098,0
)
*332 (MRCItem
litem &279
pos 16
dimension 20
uid 1100,0
)
*333 (MRCItem
litem &280
pos 17
dimension 20
uid 1102,0
)
*334 (MRCItem
litem &281
pos 18
dimension 20
uid 1104,0
)
*335 (MRCItem
litem &282
pos 19
dimension 20
uid 1106,0
)
*336 (MRCItem
litem &283
pos 20
dimension 20
uid 1108,0
)
*337 (MRCItem
litem &284
pos 21
dimension 20
uid 1110,0
)
*338 (MRCItem
litem &285
pos 22
dimension 20
uid 1112,0
)
*339 (MRCItem
litem &286
pos 23
dimension 20
uid 1114,0
)
*340 (MRCItem
litem &287
pos 24
dimension 20
uid 1116,0
)
*341 (MRCItem
litem &288
pos 25
dimension 20
uid 1118,0
)
*342 (MRCItem
litem &289
pos 26
dimension 20
uid 1120,0
)
*343 (MRCItem
litem &290
pos 27
dimension 20
uid 1122,0
)
*344 (MRCItem
litem &291
pos 28
dimension 20
uid 1124,0
)
*345 (MRCItem
litem &292
pos 29
dimension 20
uid 1126,0
)
*346 (MRCItem
litem &293
pos 30
dimension 20
uid 1128,0
)
*347 (MRCItem
litem &294
pos 31
dimension 20
uid 1130,0
)
*348 (MRCItem
litem &295
pos 32
dimension 20
uid 1132,0
)
*349 (MRCItem
litem &296
pos 33
dimension 20
uid 1134,0
)
*350 (MRCItem
litem &297
pos 34
dimension 20
uid 1136,0
)
*351 (MRCItem
litem &298
pos 35
dimension 20
uid 1138,0
)
*352 (MRCItem
litem &299
pos 36
dimension 20
uid 1140,0
)
*353 (MRCItem
litem &300
pos 37
dimension 20
uid 1142,0
)
*354 (MRCItem
litem &301
pos 38
dimension 20
uid 1144,0
)
*355 (MRCItem
litem &302
pos 39
dimension 20
uid 1146,0
)
*356 (MRCItem
litem &303
pos 40
dimension 20
uid 1148,0
)
*357 (MRCItem
litem &304
pos 41
dimension 20
uid 1150,0
)
*358 (MRCItem
litem &305
pos 42
dimension 20
uid 1152,0
)
*359 (MRCItem
litem &306
pos 43
dimension 20
uid 1154,0
)
*360 (MRCItem
litem &307
pos 44
dimension 20
uid 1156,0
)
*361 (MRCItem
litem &308
pos 45
dimension 20
uid 1158,0
)
*362 (MRCItem
litem &309
pos 46
dimension 20
uid 1160,0
)
*363 (MRCItem
litem &310
pos 47
dimension 20
uid 1162,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 1195,0
optionalChildren [
*364 (MRCItem
litem &254
pos 0
dimension 20
uid 1196,0
)
*365 (MRCItem
litem &256
pos 1
dimension 50
uid 1197,0
)
*366 (MRCItem
litem &257
pos 2
dimension 100
uid 1198,0
)
*367 (MRCItem
litem &258
pos 3
dimension 50
uid 1199,0
)
*368 (MRCItem
litem &259
pos 4
dimension 100
uid 1200,0
)
*369 (MRCItem
litem &260
pos 5
dimension 100
uid 1201,0
)
*370 (MRCItem
litem &261
pos 6
dimension 50
uid 1202,0
)
*371 (MRCItem
litem &262
pos 7
dimension 80
uid 1203,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 1190,0
vaOverrides [
]
)
]
)
uid 1175,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *372 (LEmptyRow
)
uid 1205,0
optionalChildren [
*373 (RefLabelRowHdr
)
*374 (TitleRowHdr
)
*375 (FilterRowHdr
)
*376 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*377 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*378 (GroupColHdr
tm "GroupColHdrMgr"
)
*379 (NameColHdr
tm "GenericNameColHdrMgr"
)
*380 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*381 (InitColHdr
tm "GenericValueColHdrMgr"
)
*382 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*383 (EolColHdr
tm "GenericEolColHdrMgr"
)
*384 (LogGeneric
generic (GiElement
name "RAM_ADDR_WIDTH"
type "integer"
value "14"
)
uid 9,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 1217,0
optionalChildren [
*385 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *386 (MRCItem
litem &372
pos 1
dimension 20
)
uid 1219,0
optionalChildren [
*387 (MRCItem
litem &373
pos 0
dimension 20
uid 1220,0
)
*388 (MRCItem
litem &374
pos 1
dimension 23
uid 1221,0
)
*389 (MRCItem
litem &375
pos 2
hidden 1
dimension 20
uid 1222,0
)
*390 (MRCItem
litem &384
pos 0
dimension 20
uid 10,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 1223,0
optionalChildren [
*391 (MRCItem
litem &376
pos 0
dimension 20
uid 1224,0
)
*392 (MRCItem
litem &378
pos 1
dimension 50
uid 1225,0
)
*393 (MRCItem
litem &379
pos 2
dimension 100
uid 1226,0
)
*394 (MRCItem
litem &380
pos 3
dimension 100
uid 1227,0
)
*395 (MRCItem
litem &381
pos 4
dimension 50
uid 1228,0
)
*396 (MRCItem
litem &382
pos 5
dimension 50
uid 1229,0
)
*397 (MRCItem
litem &383
pos 6
dimension 80
uid 1230,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 1218,0
vaOverrides [
]
)
]
)
uid 1204,0
type 1
)
activeModelName "BlockDiag"
)