source: firmware/FAD/FACT_FAD_TB_lib/hds/w5300_modul2_tester/interface@ 18258

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_1164"
itemName "ALL"
)
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_ARITH"
itemName "ALL"
)
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_UNSIGNED"
itemName "ALL"
)
(DmPackageRef
library "FACT_FAD_lib"
unitName "fad_definitions"
itemName "ALL"
)
]
libraryRefs [
"IEEE"
"FACT_FAD_lib"
]
)
version "24.1"
appVersion "2009.2 (Build 10)"
model (Symbol
commonDM (CommonDM
ldm (LogicalDM
ordering 1
suid 336,0
usingSuid 1
emptyRow *1 (LEmptyRow
)
uid 403,0
optionalChildren [
*2 (RefLabelRowHdr
)
*3 (TitleRowHdr
)
*4 (FilterRowHdr
)
*5 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*6 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*7 (GroupColHdr
tm "GroupColHdrMgr"
)
*8 (NameColHdr
tm "NameColHdrMgr"
)
*9 (ModeColHdr
tm "ModeColHdrMgr"
)
*10 (TypeColHdr
tm "TypeColHdrMgr"
)
*11 (BoundsColHdr
tm "BoundsColHdrMgr"
)
*12 (InitColHdr
tm "InitColHdrMgr"
)
*13 (EolColHdr
tm "EolColHdrMgr"
)
*14 (LogPort
port (LogicalPort
lang 10
m 1
decl (Decl
n "BoardID"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 28
suid 295,0
)
)
uid 2514,0
)
*15 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "busy"
t "std_logic"
o 2
suid 296,0
)
)
uid 2516,0
)
*16 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "c_trigger_enable"
t "std_logic"
o 3
suid 297,0
)
)
uid 2518,0
)
*17 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "c_trigger_mult"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 4
suid 298,0
)
)
uid 2520,0
)
*18 (LogPort
port (LogicalPort
decl (Decl
n "clk"
t "std_logic"
o 1
suid 299,0
)
)
uid 2522,0
)
*19 (LogPort
port (LogicalPort
lang 10
m 1
decl (Decl
n "CrateID"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 29
suid 300,0
)
)
uid 2524,0
)
*20 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "dac_setting"
t "dac_array_type"
o 5
suid 301,0
)
)
uid 2526,0
)
*21 (LogPort
port (LogicalPort
m 1
decl (Decl
n "data_generator_idle_i"
t "std_logic"
o 31
suid 302,0
)
)
uid 2528,0
)
*22 (LogPort
port (LogicalPort
m 1
decl (Decl
n "data_ram_empty"
t "std_logic"
o 32
suid 303,0
)
)
uid 2530,0
)
*23 (LogPort
port (LogicalPort
m 1
decl (Decl
n "data_valid"
t "std_logic"
o 33
suid 304,0
)
)
uid 2532,0
)
*24 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "data_valid_ack"
t "std_logic"
o 6
suid 305,0
)
)
uid 2534,0
)
*25 (LogPort
port (LogicalPort
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 7
suid 306,0
)
)
uid 2536,0
)
*26 (LogPort
port (LogicalPort
decl (Decl
n "debug_data_valid"
t "std_logic"
o 8
suid 307,0
)
)
uid 2538,0
)
*27 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "denable"
t "std_logic"
o 9
suid 308,0
)
)
uid 2540,0
)
*28 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "dwrite_enable"
t "std_logic"
o 10
suid 309,0
)
)
uid 2542,0
)
*29 (LogPort
port (LogicalPort
lang 10
m 1
decl (Decl
n "fifo_channels"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 34
suid 310,0
)
)
uid 2544,0
)
*30 (LogPort
port (LogicalPort
lang 10
m 1
decl (Decl
n "MAC_jumper"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 30
suid 311,0
)
)
uid 2546,0
)
*31 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "memory_manager_config_start_o"
t "std_logic"
o 11
suid 312,0
)
)
uid 2548,0
)
*32 (LogPort
port (LogicalPort
m 1
decl (Decl
n "memory_manager_config_valid_i"
t "std_logic"
o 35
suid 313,0
)
)
uid 2550,0
)
*33 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "ps_direction"
t "std_logic"
o 12
suid 314,0
)
)
uid 2552,0
)
*34 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "ps_do_phase_shift"
t "std_logic"
o 13
suid 315,0
)
)
uid 2554,0
)
*35 (LogPort
port (LogicalPort
m 1
decl (Decl
n "ps_ready"
t "std_logic"
o 36
suid 316,0
)
)
uid 2556,0
)
*36 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "ps_reset"
t "std_logic"
o 14
suid 317,0
)
)
uid 2558,0
)
*37 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "ram_addr"
t "std_logic_vector"
b "(13 DOWNTO 0)"
o 15
suid 318,0
)
)
uid 2560,0
)
*38 (LogPort
port (LogicalPort
m 1
decl (Decl
n "ram_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 37
suid 319,0
)
)
uid 2562,0
)
*39 (LogPort
port (LogicalPort
lang 10
m 1
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(13 DOWNTO 0)"
o 38
suid 320,0
)
)
uid 2564,0
)
*40 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "reset_trigger_id"
t "std_logic"
o 16
suid 321,0
)
)
uid 2566,0
)
*41 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "roi_setting"
t "roi_array_type"
o 17
suid 322,0
)
)
uid 2568,0
)
*42 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "runnumber"
t "std_logic_vector"
b "(31 DOWNTO 0)"
o 18
suid 323,0
)
)
uid 2570,0
)
*43 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "s_trigger"
t "std_logic"
o 19
suid 324,0
)
)
uid 2572,0
)
*44 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "sclk_enable"
t "std_logic"
o 20
suid 325,0
)
)
uid 2574,0
)
*45 (LogPort
port (LogicalPort
decl (Decl
n "socks_connected"
t "std_logic"
o 21
suid 326,0
)
)
uid 2576,0
)
*46 (LogPort
port (LogicalPort
decl (Decl
n "socks_waiting"
t "std_logic"
o 22
suid 327,0
)
)
uid 2578,0
)
*47 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "spi_interface_config_start_o"
t "std_logic"
o 23
suid 328,0
)
)
uid 2580,0
)
*48 (LogPort
port (LogicalPort
m 1
decl (Decl
n "spi_interface_config_valid_i"
t "std_logic"
o 39
suid 329,0
)
)
uid 2582,0
)
*49 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "srclk_enable"
t "std_logic"
o 24
suid 330,0
)
)
uid 2584,0
)
*50 (LogPort
port (LogicalPort
decl (Decl
n "state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 25
suid 331,0
)
)
uid 2586,0
)
*51 (LogPort
port (LogicalPort
decl (Decl
n "trigger_enable"
t "std_logic"
o 26
suid 332,0
)
)
uid 2588,0
)
*52 (LogPort
port (LogicalPort
lang 10
decl (Decl
n "wiz_reset"
t "std_logic"
o 27
suid 333,0
)
)
uid 2590,0
)
*53 (LogPort
port (LogicalPort
m 1
decl (Decl
n "write_end_flag"
t "std_logic"
o 40
suid 334,0
)
)
uid 2592,0
)
*54 (LogPort
port (LogicalPort
m 1
decl (Decl
n "write_header_flag"
t "std_logic"
o 41
suid 335,0
)
)
uid 2594,0
)
*55 (LogPort
port (LogicalPort
m 1
decl (Decl
n "write_length"
t "std_logic_vector"
b "(16 DOWNTO 0)"
o 42
suid 336,0
)
)
uid 2596,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 416,0
optionalChildren [
*56 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *57 (MRCItem
litem &1
pos 3
dimension 20
)
uid 418,0
optionalChildren [
*58 (MRCItem
litem &2
pos 0
dimension 20
uid 419,0
)
*59 (MRCItem
litem &3
pos 1
dimension 23
uid 420,0
)
*60 (MRCItem
litem &4
pos 2
hidden 1
dimension 20
uid 421,0
)
*61 (MRCItem
litem &14
pos 0
dimension 20
uid 2515,0
)
*62 (MRCItem
litem &15
pos 1
dimension 20
uid 2517,0
)
*63 (MRCItem
litem &16
pos 2
dimension 20
uid 2519,0
)
*64 (MRCItem
litem &17
pos 3
dimension 20
uid 2521,0
)
*65 (MRCItem
litem &18
pos 4
dimension 20
uid 2523,0
)
*66 (MRCItem
litem &19
pos 5
dimension 20
uid 2525,0
)
*67 (MRCItem
litem &20
pos 6
dimension 20
uid 2527,0
)
*68 (MRCItem
litem &21
pos 7
dimension 20
uid 2529,0
)
*69 (MRCItem
litem &22
pos 8
dimension 20
uid 2531,0
)
*70 (MRCItem
litem &23
pos 9
dimension 20
uid 2533,0
)
*71 (MRCItem
litem &24
pos 10
dimension 20
uid 2535,0
)
*72 (MRCItem
litem &25
pos 11
dimension 20
uid 2537,0
)
*73 (MRCItem
litem &26
pos 12
dimension 20
uid 2539,0
)
*74 (MRCItem
litem &27
pos 13
dimension 20
uid 2541,0
)
*75 (MRCItem
litem &28
pos 14
dimension 20
uid 2543,0
)
*76 (MRCItem
litem &29
pos 15
dimension 20
uid 2545,0
)
*77 (MRCItem
litem &30
pos 16
dimension 20
uid 2547,0
)
*78 (MRCItem
litem &31
pos 17
dimension 20
uid 2549,0
)
*79 (MRCItem
litem &32
pos 18
dimension 20
uid 2551,0
)
*80 (MRCItem
litem &33
pos 19
dimension 20
uid 2553,0
)
*81 (MRCItem
litem &34
pos 20
dimension 20
uid 2555,0
)
*82 (MRCItem
litem &35
pos 21
dimension 20
uid 2557,0
)
*83 (MRCItem
litem &36
pos 22
dimension 20
uid 2559,0
)
*84 (MRCItem
litem &37
pos 23
dimension 20
uid 2561,0
)
*85 (MRCItem
litem &38
pos 24
dimension 20
uid 2563,0
)
*86 (MRCItem
litem &39
pos 25
dimension 20
uid 2565,0
)
*87 (MRCItem
litem &40
pos 26
dimension 20
uid 2567,0
)
*88 (MRCItem
litem &41
pos 27
dimension 20
uid 2569,0
)
*89 (MRCItem
litem &42
pos 28
dimension 20
uid 2571,0
)
*90 (MRCItem
litem &43
pos 29
dimension 20
uid 2573,0
)
*91 (MRCItem
litem &44
pos 30
dimension 20
uid 2575,0
)
*92 (MRCItem
litem &45
pos 31
dimension 20
uid 2577,0
)
*93 (MRCItem
litem &46
pos 32
dimension 20
uid 2579,0
)
*94 (MRCItem
litem &47
pos 33
dimension 20
uid 2581,0
)
*95 (MRCItem
litem &48
pos 34
dimension 20
uid 2583,0
)
*96 (MRCItem
litem &49
pos 35
dimension 20
uid 2585,0
)
*97 (MRCItem
litem &50
pos 36
dimension 20
uid 2587,0
)
*98 (MRCItem
litem &51
pos 37
dimension 20
uid 2589,0
)
*99 (MRCItem
litem &52
pos 38
dimension 20
uid 2591,0
)
*100 (MRCItem
litem &53
pos 39
dimension 20
uid 2593,0
)
*101 (MRCItem
litem &54
pos 40
dimension 20
uid 2595,0
)
*102 (MRCItem
litem &55
pos 41
dimension 20
uid 2597,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 422,0
optionalChildren [
*103 (MRCItem
litem &5
pos 0
dimension 20
uid 423,0
)
*104 (MRCItem
litem &7
pos 1
dimension 50
uid 424,0
)
*105 (MRCItem
litem &8
pos 2
dimension 100
uid 425,0
)
*106 (MRCItem
litem &9
pos 3
dimension 50
uid 426,0
)
*107 (MRCItem
litem &10
pos 4
dimension 100
uid 427,0
)
*108 (MRCItem
litem &11
pos 5
dimension 100
uid 428,0
)
*109 (MRCItem
litem &12
pos 6
dimension 50
uid 429,0
)
*110 (MRCItem
litem &13
pos 7
dimension 80
uid 430,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 417,0
vaOverrides [
]
)
]
)
uid 402,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *111 (LEmptyRow
)
uid 432,0
optionalChildren [
*112 (RefLabelRowHdr
)
*113 (TitleRowHdr
)
*114 (FilterRowHdr
)
*115 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*116 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*117 (GroupColHdr
tm "GroupColHdrMgr"
)
*118 (NameColHdr
tm "GenericNameColHdrMgr"
)
*119 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*120 (InitColHdr
tm "GenericValueColHdrMgr"
)
*121 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*122 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 444,0
optionalChildren [
*123 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *124 (MRCItem
litem &111
pos 3
dimension 20
)
uid 446,0
optionalChildren [
*125 (MRCItem
litem &112
pos 0
dimension 20
uid 447,0
)
*126 (MRCItem
litem &113
pos 1
dimension 23
uid 448,0
)
*127 (MRCItem
litem &114
pos 2
hidden 1
dimension 20
uid 449,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 450,0
optionalChildren [
*128 (MRCItem
litem &115
pos 0
dimension 20
uid 451,0
)
*129 (MRCItem
litem &117
pos 1
dimension 50
uid 452,0
)
*130 (MRCItem
litem &118
pos 2
dimension 100
uid 453,0
)
*131 (MRCItem
litem &119
pos 3
dimension 100
uid 454,0
)
*132 (MRCItem
litem &120
pos 4
dimension 50
uid 455,0
)
*133 (MRCItem
litem &121
pos 5
dimension 50
uid 456,0
)
*134 (MRCItem
litem &122
pos 6
dimension 80
uid 457,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 445,0
vaOverrides [
]
)
]
)
uid 431,0
type 1
)
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester\\interface.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester\\interface.user"
)
(vvPair
variable "SourceDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "interface"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester"
)
(vvPair
variable "d_logical"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester"
)
(vvPair
variable "date"
value "01.06.2011"
)
(vvPair
variable "day"
value "Mi"
)
(vvPair
variable "day_long"
value "Mittwoch"
)
(vvPair
variable "dd"
value "01"
)
(vvPair
variable "entity_name"
value "w5300_modul2_tester"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "interface"
)
(vvPair
variable "f_logical"
value "interface"
)
(vvPair
variable "f_noext"
value "interface"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "E5B-LABOR6"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_TB_lib"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
)
(vvPair
variable "mm"
value "06"
)
(vvPair
variable "module_name"
value "w5300_modul2_tester"
)
(vvPair
variable "month"
value "Jun"
)
(vvPair
variable "month_long"
value "Juni"
)
(vvPair
variable "p"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester\\interface"
)
(vvPair
variable "p_logical"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester\\interface"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "C:\\modeltech_6.6a\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "<TBD>"
)
(vvPair
variable "this_file"
value "interface"
)
(vvPair
variable "this_file_logical"
value "interface"
)
(vvPair
variable "time"
value "09:26:48"
)
(vvPair
variable "unit"
value "w5300_modul2_tester"
)
(vvPair
variable "user"
value "dneise"
)
(vvPair
variable "version"
value "2009.2 (Build 10)"
)
(vvPair
variable "view"
value "interface"
)
(vvPair
variable "year"
value "2011"
)
(vvPair
variable "yy"
value "11"
)
]
)
LanguageMgr "VhdlLangMgr"
uid 401,0
optionalChildren [
*135 (SymbolBody
uid 8,0
optionalChildren [
*136 (CptPort
uid 2304,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2305,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,20625,15000,21375"
)
tg (CPTG
uid 2306,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2307,0
va (VaSet
)
xt "16000,20500,19200,21500"
st "BoardID"
blo "16000,21300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2308,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "BoardID"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 28
suid 295,0
)
)
)
*137 (CptPort
uid 2309,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2310,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,19625,49750,20375"
)
tg (CPTG
uid 2311,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2312,0
va (VaSet
)
xt "46100,19500,48000,20500"
st "busy"
ju 2
blo "48000,20300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2313,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "busy"
t "std_logic"
o 2
suid 296,0
)
)
)
*138 (CptPort
uid 2314,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2315,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,21625,49750,22375"
)
tg (CPTG
uid 2316,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2317,0
va (VaSet
)
xt "41400,21500,48000,22500"
st "c_trigger_enable"
ju 2
blo "48000,22300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2318,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "c_trigger_enable"
t "std_logic"
o 3
suid 297,0
)
)
)
*139 (CptPort
uid 2319,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2320,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,22625,49750,23375"
)
tg (CPTG
uid 2321,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2322,0
va (VaSet
)
xt "42200,22500,48000,23500"
st "c_trigger_mult"
ju 2
blo "48000,23300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2323,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "c_trigger_mult"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 4
suid 298,0
)
)
)
*140 (CptPort
uid 2324,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2325,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,7625,15000,8375"
)
tg (CPTG
uid 2326,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2327,0
va (VaSet
)
xt "16000,7500,17300,8500"
st "clk"
blo "16000,8300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2328,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
o 1
suid 299,0
)
)
)
*141 (CptPort
uid 2329,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2330,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,21625,15000,22375"
)
tg (CPTG
uid 2331,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2332,0
va (VaSet
)
xt "16000,21500,19100,22500"
st "CrateID"
blo "16000,22300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2333,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "CrateID"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 29
suid 300,0
)
)
)
*142 (CptPort
uid 2334,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2335,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,25625,49750,26375"
)
tg (CPTG
uid 2336,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2337,0
va (VaSet
)
xt "43300,25500,48000,26500"
st "dac_setting"
ju 2
blo "48000,26300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2338,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "dac_setting"
t "dac_array_type"
o 5
suid 301,0
)
)
)
*143 (CptPort
uid 2339,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2340,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,6625,15000,7375"
)
tg (CPTG
uid 2341,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2342,0
va (VaSet
)
xt "16000,6500,24500,7500"
st "data_generator_idle_i"
blo "16000,7300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2343,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data_generator_idle_i"
t "std_logic"
o 31
suid 302,0
)
)
)
*144 (CptPort
uid 2344,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2345,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,18625,15000,19375"
)
tg (CPTG
uid 2346,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2347,0
va (VaSet
)
xt "16000,18500,22200,19500"
st "data_ram_empty"
blo "16000,19300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2348,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data_ram_empty"
t "std_logic"
o 32
suid 303,0
)
)
)
*145 (CptPort
uid 2349,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2350,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,12625,15000,13375"
)
tg (CPTG
uid 2351,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2352,0
va (VaSet
)
xt "16000,12500,20100,13500"
st "data_valid"
blo "16000,13300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2353,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data_valid"
t "std_logic"
o 33
suid 304,0
)
)
)
*146 (CptPort
uid 2354,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2355,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,18625,49750,19375"
)
tg (CPTG
uid 2356,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2357,0
va (VaSet
)
xt "42400,18500,48000,19500"
st "data_valid_ack"
ju 2
blo "48000,19300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2358,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "data_valid_ack"
t "std_logic"
o 6
suid 305,0
)
)
)
*147 (CptPort
uid 2359,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2360,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,7625,49750,8375"
)
tg (CPTG
uid 2361,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2362,0
va (VaSet
)
xt "38900,7500,48000,8500"
st "debug_data_ram_empty"
ju 2
blo "48000,8300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2363,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 7
suid 306,0
)
)
)
*148 (CptPort
uid 2364,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2365,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,8625,49750,9375"
)
tg (CPTG
uid 2366,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2367,0
va (VaSet
)
xt "41400,8500,48000,9500"
st "debug_data_valid"
ju 2
blo "48000,9300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2368,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "debug_data_valid"
t "std_logic"
o 8
suid 307,0
)
)
)
*149 (CptPort
uid 2369,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2370,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,30625,49750,31375"
)
tg (CPTG
uid 2371,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2372,0
va (VaSet
)
xt "45000,30500,48000,31500"
st "denable"
ju 2
blo "48000,31300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2373,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "denable"
t "std_logic"
o 9
suid 308,0
)
)
)
*150 (CptPort
uid 2374,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2375,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,31625,49750,32375"
)
tg (CPTG
uid 2376,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2377,0
va (VaSet
)
xt "42600,31500,48000,32500"
st "dwrite_enable"
ju 2
blo "48000,32300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2378,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "dwrite_enable"
t "std_logic"
o 10
suid 309,0
)
)
)
*151 (CptPort
uid 2379,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2380,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,15625,15000,16375"
)
tg (CPTG
uid 2381,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2382,0
va (VaSet
)
xt "16000,15500,21200,16500"
st "fifo_channels"
blo "16000,16300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2383,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "fifo_channels"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 34
suid 310,0
)
)
)
*152 (CptPort
uid 2384,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2385,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,19625,15000,20375"
)
tg (CPTG
uid 2386,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2387,0
va (VaSet
)
xt "16000,19500,21300,20500"
st "MAC_jumper"
blo "16000,20300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2388,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "MAC_jumper"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 30
suid 311,0
)
)
)
*153 (CptPort
uid 2389,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2390,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,23625,49750,24375"
)
tg (CPTG
uid 2391,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2392,0
va (VaSet
)
xt "35600,23500,48000,24500"
st "memory_manager_config_start_o"
ju 2
blo "48000,24300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2393,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "memory_manager_config_start_o"
t "std_logic"
o 11
suid 312,0
)
)
)
*154 (CptPort
uid 2394,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2395,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,16625,15000,17375"
)
tg (CPTG
uid 2396,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2397,0
va (VaSet
)
xt "16000,16500,28200,17500"
st "memory_manager_config_valid_i"
blo "16000,17300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2398,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memory_manager_config_valid_i"
t "std_logic"
o 35
suid 313,0
)
)
)
*155 (CptPort
uid 2399,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2400,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,34625,49750,35375"
)
tg (CPTG
uid 2401,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2402,0
va (VaSet
)
xt "43100,34500,48000,35500"
st "ps_direction"
ju 2
blo "48000,35300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2403,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "ps_direction"
t "std_logic"
o 12
suid 314,0
)
)
)
*156 (CptPort
uid 2404,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2405,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,35625,49750,36375"
)
tg (CPTG
uid 2406,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2407,0
va (VaSet
)
xt "41000,35500,48000,36500"
st "ps_do_phase_shift"
ju 2
blo "48000,36300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2408,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "ps_do_phase_shift"
t "std_logic"
o 13
suid 315,0
)
)
)
*157 (CptPort
uid 2409,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2410,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,22625,15000,23375"
)
tg (CPTG
uid 2411,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2412,0
va (VaSet
)
xt "16000,22500,19400,23500"
st "ps_ready"
blo "16000,23300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2413,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ps_ready"
t "std_logic"
o 36
suid 316,0
)
)
)
*158 (CptPort
uid 2414,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2415,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,36625,49750,37375"
)
tg (CPTG
uid 2416,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2417,0
va (VaSet
)
xt "44700,36500,48000,37500"
st "ps_reset"
ju 2
blo "48000,37300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2418,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "ps_reset"
t "std_logic"
o 14
suid 317,0
)
)
)
*159 (CptPort
uid 2419,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2420,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,17625,49750,18375"
)
tg (CPTG
uid 2421,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2422,0
va (VaSet
)
xt "44400,17500,48000,18500"
st "ram_addr"
ju 2
blo "48000,18300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2423,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "ram_addr"
t "std_logic_vector"
b "(13 DOWNTO 0)"
o 15
suid 318,0
)
)
)
*160 (CptPort
uid 2424,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2425,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,11625,15000,12375"
)
tg (CPTG
uid 2426,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2427,0
va (VaSet
)
xt "16000,11500,19500,12500"
st "ram_data"
blo "16000,12300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2428,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 37
suid 319,0
)
)
)
*161 (CptPort
uid 2429,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2430,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,10625,15000,11375"
)
tg (CPTG
uid 2431,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2432,0
va (VaSet
)
xt "16000,10500,21900,11500"
st "ram_start_addr"
blo "16000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2433,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(13 DOWNTO 0)"
o 38
suid 320,0
)
)
)
*162 (CptPort
uid 2434,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2435,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,28625,49750,29375"
)
tg (CPTG
uid 2436,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2437,0
va (VaSet
)
xt "41700,28500,48000,29500"
st "reset_trigger_id"
ju 2
blo "48000,29300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2438,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "reset_trigger_id"
t "std_logic"
o 16
suid 321,0
)
)
)
*163 (CptPort
uid 2439,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2440,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,26625,49750,27375"
)
tg (CPTG
uid 2441,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2442,0
va (VaSet
)
xt "43600,26500,48000,27500"
st "roi_setting"
ju 2
blo "48000,27300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2443,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "roi_setting"
t "roi_array_type"
o 17
suid 322,0
)
)
)
*164 (CptPort
uid 2444,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2445,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,27625,49750,28375"
)
tg (CPTG
uid 2446,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2447,0
va (VaSet
)
xt "44000,27500,48000,28500"
st "runnumber"
ju 2
blo "48000,28300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2448,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "runnumber"
t "std_logic_vector"
b "(31 DOWNTO 0)"
o 18
suid 323,0
)
)
)
*165 (CptPort
uid 2449,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2450,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,20625,49750,21375"
)
tg (CPTG
uid 2451,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2452,0
va (VaSet
)
xt "44400,20500,48000,21500"
st "s_trigger"
ju 2
blo "48000,21300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2453,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "s_trigger"
t "std_logic"
o 19
suid 324,0
)
)
)
*166 (CptPort
uid 2454,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2455,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,32625,49750,33375"
)
tg (CPTG
uid 2456,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2457,0
va (VaSet
)
xt "43300,32500,48000,33500"
st "sclk_enable"
ju 2
blo "48000,33300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2458,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "sclk_enable"
t "std_logic"
o 20
suid 325,0
)
)
)
*167 (CptPort
uid 2459,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2460,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,38625,49750,39375"
)
tg (CPTG
uid 2461,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2462,0
va (VaSet
)
xt "41500,38500,48000,39500"
st "socks_connected"
ju 2
blo "48000,39300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2463,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "socks_connected"
t "std_logic"
o 21
suid 326,0
)
)
)
*168 (CptPort
uid 2464,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2465,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,37625,49750,38375"
)
tg (CPTG
uid 2466,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2467,0
va (VaSet
)
xt "42500,37500,48000,38500"
st "socks_waiting"
ju 2
blo "48000,38300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2468,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "socks_waiting"
t "std_logic"
o 22
suid 327,0
)
)
)
*169 (CptPort
uid 2469,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2470,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,24625,49750,25375"
)
tg (CPTG
uid 2471,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2472,0
va (VaSet
)
xt "37300,24500,48000,25500"
st "spi_interface_config_start_o"
ju 2
blo "48000,25300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2473,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "spi_interface_config_start_o"
t "std_logic"
o 23
suid 328,0
)
)
)
*170 (CptPort
uid 2474,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2475,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,17625,15000,18375"
)
tg (CPTG
uid 2476,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2477,0
va (VaSet
)
xt "16000,17500,26500,18500"
st "spi_interface_config_valid_i"
blo "16000,18300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2478,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "spi_interface_config_valid_i"
t "std_logic"
o 39
suid 329,0
)
)
)
*171 (CptPort
uid 2479,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2480,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,33625,49750,34375"
)
tg (CPTG
uid 2481,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2482,0
va (VaSet
)
xt "43000,33500,48000,34500"
st "srclk_enable"
ju 2
blo "48000,34300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2483,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "srclk_enable"
t "std_logic"
o 24
suid 330,0
)
)
)
*172 (CptPort
uid 2484,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2485,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,6625,49750,7375"
)
tg (CPTG
uid 2486,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2487,0
va (VaSet
)
xt "46000,6500,48000,7500"
st "state"
ju 2
blo "48000,7300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2488,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 25
suid 331,0
)
)
)
*173 (CptPort
uid 2489,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2490,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,29625,49750,30375"
)
tg (CPTG
uid 2491,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2492,0
va (VaSet
)
xt "42200,29500,48000,30500"
st "trigger_enable"
ju 2
blo "48000,30300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2493,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "trigger_enable"
t "std_logic"
o 26
suid 332,0
)
)
)
*174 (CptPort
uid 2494,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2495,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,10625,49750,11375"
)
tg (CPTG
uid 2496,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2497,0
va (VaSet
)
xt "44400,10500,48000,11500"
st "wiz_reset"
ju 2
blo "48000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2498,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "wiz_reset"
t "std_logic"
o 27
suid 333,0
)
)
)
*175 (CptPort
uid 2499,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2500,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,14625,15000,15375"
)
tg (CPTG
uid 2501,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2502,0
va (VaSet
)
xt "16000,14500,21700,15500"
st "write_end_flag"
blo "16000,15300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2503,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "write_end_flag"
t "std_logic"
o 40
suid 334,0
)
)
)
*176 (CptPort
uid 2504,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2505,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,13625,15000,14375"
)
tg (CPTG
uid 2506,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2507,0
va (VaSet
)
xt "16000,13500,22800,14500"
st "write_header_flag"
blo "16000,14300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2508,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "write_header_flag"
t "std_logic"
o 41
suid 335,0
)
)
)
*177 (CptPort
uid 2509,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2510,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,9625,15000,10375"
)
tg (CPTG
uid 2511,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2512,0
va (VaSet
)
xt "16000,9500,20900,10500"
st "write_length"
blo "16000,10300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2513,0
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "write_length"
t "std_logic_vector"
b "(16 DOWNTO 0)"
o 42
suid 336,0
)
)
)
]
shape (Rectangle
uid 9,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,6000,49000,40000"
)
biTextGroup (BiTextGroup
uid 10,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
uid 11,0
va (VaSet
font "Arial,8,1"
)
xt "27700,22000,35400,23000"
st "FACT_FAD_TB_lib"
blo "27700,22800"
)
second (Text
uid 12,0
va (VaSet
font "Arial,8,1"
)
xt "27700,23000,36300,24000"
st "w5300_modul2_tester"
blo "27700,23800"
)
)
gi *178 (GenericInterface
uid 13,0
ps "CenterOffsetStrategy"
matrix (Matrix
uid 14,0
text (MLText
uid 15,0
va (VaSet
font "Courier New,8,0"
)
xt "8000,19000,19500,19800"
st "Generic Declarations"
)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
elements [
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
sTC 0
sF 0
)
portVis (PortSigDisplay
sTC 0
sF 0
)
)
*179 (Grouping
uid 16,0
optionalChildren [
*180 (CommentText
uid 18,0
shape (Rectangle
uid 19,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,48000,53000,49000"
)
oxt "18000,70000,35000,71000"
text (MLText
uid 20,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,48000,45800,49000"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*181 (CommentText
uid 21,0
shape (Rectangle
uid 22,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,44000,57000,45000"
)
oxt "35000,66000,39000,67000"
text (MLText
uid 23,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,44000,56200,45000"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*182 (CommentText
uid 24,0
shape (Rectangle
uid 25,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,46000,53000,47000"
)
oxt "18000,68000,35000,69000"
text (MLText
uid 26,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,46000,46200,47000"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*183 (CommentText
uid 27,0
shape (Rectangle
uid 28,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,46000,36000,47000"
)
oxt "14000,68000,18000,69000"
text (MLText
uid 29,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,46000,34300,47000"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*184 (CommentText
uid 30,0
shape (Rectangle
uid 31,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,45000,73000,49000"
)
oxt "35000,67000,55000,71000"
text (MLText
uid 32,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,45200,62400,46200"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
titleBlock 1
)
*185 (CommentText
uid 33,0
shape (Rectangle
uid 34,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "57000,44000,73000,45000"
)
oxt "39000,66000,55000,67000"
text (MLText
uid 35,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "57200,44000,61700,45000"
st "
%project_name
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
titleBlock 1
)
*186 (CommentText
uid 36,0
shape (Rectangle
uid 37,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,44000,53000,46000"
)
oxt "14000,66000,35000,68000"
text (MLText
uid 38,0
va (VaSet
fg "32768,0,0"
)
xt "39150,44500,45850,45500"
st "
<company name>
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
titleBlock 1
)
*187 (CommentText
uid 39,0
shape (Rectangle
uid 40,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,47000,36000,48000"
)
oxt "14000,69000,18000,70000"
text (MLText
uid 41,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,47000,34300,48000"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*188 (CommentText
uid 42,0
shape (Rectangle
uid 43,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,48000,36000,49000"
)
oxt "14000,70000,18000,71000"
text (MLText
uid 44,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,48000,34900,49000"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*189 (CommentText
uid 45,0
shape (Rectangle
uid 46,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,47000,53000,48000"
)
oxt "18000,69000,35000,70000"
text (MLText
uid 47,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,47000,51700,48000"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
]
shape (GroupingShape
uid 17,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "32000,44000,73000,49000"
)
oxt "14000,66000,55000,71000"
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *190 (PackageList
uid 48,0
stg "VerticalLayoutStrategy"
textVec [
*191 (Text
uid 49,0
va (VaSet
font "arial,8,1"
)
xt "0,0,5400,1000"
st "Package List"
blo "0,800"
)
*192 (MLText
uid 50,0
va (VaSet
)
xt "0,1000,15600,7000"
st "LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY FACT_FAD_lib;
USE FACT_FAD_lib.fad_definitions.ALL;"
tm "PackageList"
)
]
)
windowSize "0,0,1015,690"
viewArea "0,0,0,0"
cachedDiagramExtent "0,0,0,0"
pageBreakOrigin "0,0"
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,2000,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Arial,8,1"
)
xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
parentGraphicsRef (HdmGraphicsRef
libraryName "FACT_FAD_TB_lib"
entityName "w5300_modul2_tb"
viewName "struct.bd"
)
defaultSymbolBody (SymbolBody
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,6000,33000,26000"
)
biTextGroup (BiTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
font "Arial,8,1"
)
xt "22200,15000,25800,16000"
st "<library>"
blo "22200,15800"
)
second (Text
va (VaSet
font "Arial,8,1"
)
xt "22200,16000,24800,17000"
st "<cell>"
blo "22200,16800"
)
)
gi *193 (GenericInterface
ps "CenterOffsetStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "0,12000,11500,12800"
st "Generic Declarations"
)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
elements [
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
sIVOD 1
)
portVis (PortSigDisplay
sIVOD 1
)
)
defaultCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "In0"
blo "0,1550"
tm "CptPortNameMgr"
)
)
dt (MLText
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "In0"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
defaultCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
bg "0,0,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,2800,1750"
st "Buffer0"
blo "0,1550"
tm "CptPortNameMgr"
)
)
dt (MLText
va (VaSet
font "Courier New,8,0"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Buffer0"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
DeclarativeBlock *194 (SymDeclBlock
uid 1,0
stg "SymDeclLayoutStrategy"
declLabel (Text
uid 2,0
va (VaSet
font "Arial,8,1"
)
xt "42000,0,47400,1000"
st "Declarations"
blo "42000,800"
)
portLabel (Text
uid 3,0
va (VaSet
font "Arial,8,1"
)
xt "42000,1000,44700,2000"
st "Ports:"
blo "42000,1800"
)
externalLabel (Text
uid 4,0
va (VaSet
font "Arial,8,1"
)
xt "42000,42000,44400,43000"
st "User:"
blo "42000,42800"
)
internalLabel (Text
uid 6,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "42000,0,47800,1000"
st "Internal User:"
blo "42000,800"
)
externalText (MLText
uid 5,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,43000,44000,43000"
tm "SyDeclarativeTextMgr"
)
internalText (MLText
uid 7,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "42000,0,42000,0"
tm "SyDeclarativeTextMgr"
)
)
lastUid 2597,0
activeModelName "Symbol:CDM"
)