source: firmware/FAD/FACT_FAD_lib/hds/data_generator/symbol.sb@ 13449

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_1164"
itemName "ALL"
)
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_ARITH"
itemName "ALL"
)
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_UNSIGNED"
itemName "ALL"
)
(DmPackageRef
library "fact_fad_lib"
unitName "fad_definitions"
)
]
libraryRefs [
"IEEE"
"fact_fad_lib"
]
)
version "24.1"
appVersion "2009.1 (Build 12)"
model (Symbol
commonDM (CommonDM
ldm (LogicalDM
ordering 1
suid 105,0
usingSuid 1
emptyRow *1 (LEmptyRow
)
uid 136,0
optionalChildren [
*2 (RefLabelRowHdr
)
*3 (TitleRowHdr
)
*4 (FilterRowHdr
)
*5 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*6 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*7 (GroupColHdr
tm "GroupColHdrMgr"
)
*8 (NameColHdr
tm "NameColHdrMgr"
)
*9 (ModeColHdr
tm "ModeColHdrMgr"
)
*10 (TypeColHdr
tm "TypeColHdrMgr"
)
*11 (BoundsColHdr
tm "BoundsColHdrMgr"
)
*12 (InitColHdr
tm "InitColHdrMgr"
)
*13 (EolColHdr
tm "EolColHdrMgr"
)
*14 (LogPort
port (LogicalPort
decl (Decl
n "clk"
t "std_logic"
eolc "-- CLK_25."
preAdd 0
posAdd 0
o 3
suid 1,0
)
)
uid 109,0
)
*15 (LogPort
port (LogicalPort
m 1
decl (Decl
n "data_out"
t "std_logic_vector"
b "(63 downto 0)"
preAdd 0
posAdd 0
o 4
suid 2,0
)
)
uid 111,0
)
*16 (LogPort
port (LogicalPort
m 1
decl (Decl
n "addr_out"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 downto 0)"
preAdd 0
posAdd 0
o 5
suid 3,0
)
)
uid 113,0
)
*17 (LogPort
port (LogicalPort
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 downto 0)"
preAdd 0
posAdd 0
o 7
suid 7,0
)
)
uid 121,0
)
*18 (LogPort
port (LogicalPort
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
prec "-- EVT HEADER - part 4"
preAdd 0
posAdd 0
o 33
suid 9,0
)
)
uid 125,0
)
*19 (LogPort
port (LogicalPort
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
posAdd 0
o 34
suid 12,0
)
)
uid 290,0
)
*20 (LogPort
port (LogicalPort
decl (Decl
n "ram_write_ea"
t "std_logic"
o 8
suid 16,0
)
)
uid 421,0
)
*21 (LogPort
port (LogicalPort
m 1
decl (Decl
n "ram_write_ready"
t "std_logic"
posAdd 0
o 9
suid 17,0
i "'0'"
)
)
uid 423,0
)
*22 (LogPort
port (LogicalPort
decl (Decl
n "roi_max"
t "roi_max_type"
o 11
suid 18,0
)
)
uid 425,0
)
*23 (LogPort
port (LogicalPort
decl (Decl
n "roi_array"
t "roi_array_type"
o 10
suid 19,0
)
)
uid 478,0
)
*24 (LogPort
port (LogicalPort
decl (Decl
n "package_length"
t "std_logic_vector"
b "(15 downto 0)"
prec "-- EVT HEADER - part 1"
preAdd 0
o 17
suid 20,0
)
)
uid 531,0
)
*25 (LogPort
port (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
posAdd 0
o 49
suid 25,0
i "(others => '0')"
)
)
uid 701,0
)
*26 (LogPort
port (LogicalPort
m 1
decl (Decl
n "drs_clk_en"
t "std_logic"
preAdd 0
posAdd 0
o 52
suid 26,0
i "'0'"
)
)
uid 703,0
)
*27 (LogPort
port (LogicalPort
decl (Decl
n "drs_read_s_cell_ready"
t "std_logic"
o 58
suid 34,0
)
)
uid 818,0
)
*28 (LogPort
port (LogicalPort
decl (Decl
n "drs_s_cell_array"
t "drs_s_cell_array_type"
o 59
suid 35,0
)
)
uid 820,0
)
*29 (LogPort
port (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 45
suid 37,0
)
)
uid 903,0
)
*30 (LogPort
port (LogicalPort
decl (Decl
n "sensor_array"
t "sensor_array_type"
o 12
suid 44,0
)
)
uid 1095,0
)
*31 (LogPort
port (LogicalPort
decl (Decl
n "sensor_ready"
t "std_logic"
o 13
suid 45,0
)
)
uid 1097,0
)
*32 (LogPort
port (LogicalPort
decl (Decl
n "dac_array"
t "dac_array_type"
posAdd 0
o 14
suid 53,0
)
)
uid 1245,0
)
*33 (LogPort
port (LogicalPort
m 1
decl (Decl
n "adc_clk_en"
t "std_logic"
o 47
suid 54,0
i "'0'"
)
)
uid 1400,0
)
*34 (LogPort
port (LogicalPort
decl (Decl
n "adc_otr"
t "std_logic_vector"
b "(3 downto 0)"
o 48
suid 55,0
)
)
uid 1432,0
)
*35 (LogPort
port (LogicalPort
m 1
decl (Decl
n "drs_srin_data"
t "std_logic_vector"
b "(7 downto 0)"
o 56
suid 56,0
i "(others => '0')"
)
)
uid 1484,0
)
*36 (LogPort
port (LogicalPort
m 1
decl (Decl
n "drs_srin_write_8b"
t "std_logic"
o 54
suid 57,0
i "'0'"
)
)
uid 1486,0
)
*37 (LogPort
port (LogicalPort
decl (Decl
n "drs_srin_write_ack"
t "std_logic"
o 55
suid 58,0
)
)
uid 1488,0
)
*38 (LogPort
port (LogicalPort
decl (Decl
n "drs_srin_write_ready"
t "std_logic"
o 57
suid 59,0
)
)
uid 1490,0
)
*39 (LogPort
port (LogicalPort
m 1
decl (Decl
n "drs_readout_started"
t "std_logic"
o 60
suid 61,0
i "'0'"
)
)
uid 1524,0
)
*40 (LogPort
port (LogicalPort
m 1
decl (Decl
n "drs_readout_ready"
t "std_logic"
prec "--drs_dwrite : out std_logic := '1';"
preAdd 0
posAdd 0
o 50
suid 62,0
i "'0'"
)
)
uid 1556,0
)
*41 (LogPort
port (LogicalPort
decl (Decl
n "drs_readout_ready_ack"
t "std_logic"
posAdd 0
o 51
suid 63,0
)
)
uid 1588,0
)
*42 (LogPort
port (LogicalPort
decl (Decl
n "pll_lock"
t "std_logic_vector"
b "( 3 downto 0)"
posAdd 0
o 18
suid 64,0
)
)
uid 1620,0
)
*43 (LogPort
port (LogicalPort
decl (Decl
n "fad_event_counter"
t "std_logic_vector"
b "(31 downto 0)"
prec "-- EVT HEADER - part 3"
preAdd 0
o 29
suid 65,0
)
)
uid 1652,0
)
*44 (LogPort
port (LogicalPort
decl (Decl
n "refclk_counter"
t "std_logic_vector"
b "(11 downto 0)"
o 30
suid 66,0
)
)
uid 1694,0
)
*45 (LogPort
port (LogicalPort
decl (Decl
n "refclk_too_high"
t "std_logic"
o 31
suid 67,0
)
)
uid 1696,0
)
*46 (LogPort
port (LogicalPort
decl (Decl
n "refclk_too_low"
t "std_logic"
posAdd 0
o 32
suid 68,0
)
)
uid 1698,0
)
*47 (LogPort
port (LogicalPort
decl (Decl
n "FTM_RS485_ready"
t "std_logic"
prec "-- EVT HEADER - part 2  --> FTM trigger informaton, comes in late ...
-- during EVT header wrinting, this field is left out ... and only written into event header,
-- when the DRS chip were read out already."
preAdd 0
o 26
suid 69,0
)
)
uid 1735,0
)
*48 (LogPort
port (LogicalPort
decl (Decl
n "FTM_trigger_info"
t "std_logic_vector"
b "(55 downto 0)"
eolc "--7 byte"
posAdd 0
o 27
suid 70,0
)
)
uid 1737,0
)
*49 (LogPort
port (LogicalPort
decl (Decl
n "DCM_PS_status"
t "std_logic_vector"
b "(7 downto 0)"
o 35
suid 71,0
)
)
uid 1779,0
)
*50 (LogPort
port (LogicalPort
decl (Decl
n "TRG_GEN_div"
t "std_logic_vector"
b "(15 downto 0)"
posAdd 0
o 39
suid 72,0
)
)
uid 1781,0
)
*51 (LogPort
port (LogicalPort
decl (Decl
n "dna"
t "std_logic_vector"
b "(63 downto 0)"
prec "-- EVT HEADER - part 5"
preAdd 0
posAdd 0
o 40
suid 74,0
)
)
uid 1815,0
)
*52 (LogPort
port (LogicalPort
decl (Decl
n "timer_value"
t "std_logic_vector"
b "(31 downto 0)"
eolc "-- time in units of 100us"
preAdd 0
posAdd 0
o 42
suid 75,0
)
)
uid 1847,0
)
*53 (LogPort
port (LogicalPort
m 1
decl (Decl
n "adc_output_enable_inverted"
t "std_logic"
o 46
suid 76,0
i "'1'"
)
)
uid 1947,0
)
*54 (LogPort
port (LogicalPort
m 1
decl (Decl
n "dataRAM_write_ea_o"
t "std_logic_vector"
b "(0 downto 0)"
o 6
suid 78,0
i "\"0\""
)
)
uid 1951,0
)
*55 (LogPort
port (LogicalPort
m 1
decl (Decl
n "start_read_drs_stop_cell"
t "std_logic"
o 53
suid 80,0
i "'0'"
)
)
uid 1955,0
)
*56 (LogPort
port (LogicalPort
m 1
decl (Decl
n "config_done"
t "std_logic"
o 16
suid 83,0
i "'0'"
)
)
uid 2056,0
)
*57 (LogPort
port (LogicalPort
decl (Decl
n "config_start"
t "std_logic"
o 15
suid 84,0
)
)
uid 2058,0
)
*58 (LogPort
port (LogicalPort
decl (Decl
n "DCM_locked_status"
t "std_logic"
o 36
suid 85,0
)
)
uid 2105,0
)
*59 (LogPort
port (LogicalPort
decl (Decl
n "DCM_ready_status"
t "std_logic"
o 37
suid 86,0
)
)
uid 2107,0
)
*60 (LogPort
port (LogicalPort
decl (Decl
n "denable_enable_in"
t "std_logic"
o 20
suid 87,0
)
)
uid 2109,0
)
*61 (LogPort
port (LogicalPort
decl (Decl
n "dwrite_enable_in"
t "std_logic"
o 19
suid 88,0
)
)
uid 2111,0
)
*62 (LogPort
port (LogicalPort
decl (Decl
n "SPI_SCLK_enable_status"
t "std_logic"
o 38
suid 89,0
)
)
uid 2143,0
)
*63 (LogPort
port (LogicalPort
m 1
decl (Decl
n "trigger_veto"
t "std_logic"
o 61
suid 90,0
i "'1'"
)
)
uid 2175,0
)
*64 (LogPort
port (LogicalPort
decl (Decl
n "FTM_receiver_status"
t "std_logic"
o 28
suid 91,0
)
)
uid 2207,0
)
*65 (LogPort
port (LogicalPort
decl (Decl
n "runnumber"
t "std_logic_vector"
b "(31 downto 0)"
prec "-- EVT HEADER - part 6"
preAdd 0
posAdd 0
o 41
suid 92,0
)
)
uid 2239,0
)
*66 (LogPort
port (LogicalPort
decl (Decl
n "hardware_trigger_in"
t "std_logic"
o 43
suid 96,0
)
)
uid 2347,0
)
*67 (LogPort
port (LogicalPort
decl (Decl
n "software_trigger_in"
t "std_logic"
o 44
suid 97,0
)
)
uid 2349,0
)
*68 (LogPort
port (LogicalPort
m 1
decl (Decl
n "state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 1
suid 99,0
)
)
uid 2388,0
)
*69 (LogPort
port (LogicalPort
m 1
decl (Decl
n "is_idle"
t "std_logic"
o 2
suid 100,0
)
)
uid 2420,0
)
*70 (LogPort
port (LogicalPort
decl (Decl
n "busy_enable_in"
t "std_logic"
o 21
suid 101,0
)
)
uid 2492,0
)
*71 (LogPort
port (LogicalPort
decl (Decl
n "cont_trigger_en_in"
t "std_logic"
o 23
suid 102,0
)
)
uid 2494,0
)
*72 (LogPort
port (LogicalPort
decl (Decl
n "socket_send_mode_in"
t "std_logic"
o 24
suid 103,0
)
)
uid 2496,0
)
*73 (LogPort
port (LogicalPort
decl (Decl
n "trigger_enable_in"
t "std_logic"
o 22
suid 104,0
)
)
uid 2498,0
)
*74 (LogPort
port (LogicalPort
decl (Decl
n "busy_manual_in"
t "std_logic"
o 25
suid 105,0
)
)
uid 2530,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 149,0
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headerVa (MVa
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fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
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emptyMRCItem *76 (MRCItem
litem &1
pos 3
dimension 20
)
uid 151,0
optionalChildren [
*77 (MRCItem
litem &2
pos 0
dimension 20
uid 152,0
)
*78 (MRCItem
litem &3
pos 1
dimension 23
uid 153,0
)
*79 (MRCItem
litem &4
pos 2
hidden 1
dimension 20
uid 154,0
)
*80 (MRCItem
litem &14
pos 0
dimension 20
uid 110,0
)
*81 (MRCItem
litem &15
pos 1
dimension 20
uid 112,0
)
*82 (MRCItem
litem &16
pos 2
dimension 20
uid 114,0
)
*83 (MRCItem
litem &17
pos 3
dimension 20
uid 122,0
)
*84 (MRCItem
litem &18
pos 4
dimension 20
uid 126,0
)
*85 (MRCItem
litem &19
pos 5
dimension 20
uid 291,0
)
*86 (MRCItem
litem &20
pos 6
dimension 20
uid 422,0
)
*87 (MRCItem
litem &21
pos 7
dimension 20
uid 424,0
)
*88 (MRCItem
litem &22
pos 8
dimension 20
uid 426,0
)
*89 (MRCItem
litem &23
pos 9
dimension 20
uid 479,0
)
*90 (MRCItem
litem &24
pos 10
dimension 20
uid 532,0
)
*91 (MRCItem
litem &25
pos 11
dimension 20
uid 702,0
)
*92 (MRCItem
litem &26
pos 12
dimension 20
uid 704,0
)
*93 (MRCItem
litem &27
pos 13
dimension 20
uid 819,0
)
*94 (MRCItem
litem &28
pos 14
dimension 20
uid 821,0
)
*95 (MRCItem
litem &29
pos 15
dimension 20
uid 904,0
)
*96 (MRCItem
litem &30
pos 16
dimension 20
uid 1096,0
)
*97 (MRCItem
litem &31
pos 17
dimension 20
uid 1098,0
)
*98 (MRCItem
litem &32
pos 18
dimension 20
uid 1246,0
)
*99 (MRCItem
litem &33
pos 19
dimension 20
uid 1401,0
)
*100 (MRCItem
litem &34
pos 20
dimension 20
uid 1433,0
)
*101 (MRCItem
litem &35
pos 21
dimension 20
uid 1485,0
)
*102 (MRCItem
litem &36
pos 22
dimension 20
uid 1487,0
)
*103 (MRCItem
litem &37
pos 23
dimension 20
uid 1489,0
)
*104 (MRCItem
litem &38
pos 24
dimension 20
uid 1491,0
)
*105 (MRCItem
litem &39
pos 25
dimension 20
uid 1525,0
)
*106 (MRCItem
litem &40
pos 26
dimension 20
uid 1557,0
)
*107 (MRCItem
litem &41
pos 27
dimension 20
uid 1589,0
)
*108 (MRCItem
litem &42
pos 28
dimension 20
uid 1621,0
)
*109 (MRCItem
litem &43
pos 29
dimension 20
uid 1653,0
)
*110 (MRCItem
litem &44
pos 30
dimension 20
uid 1695,0
)
*111 (MRCItem
litem &45
pos 31
dimension 20
uid 1697,0
)
*112 (MRCItem
litem &46
pos 32
dimension 20
uid 1699,0
)
*113 (MRCItem
litem &47
pos 33
dimension 20
uid 1736,0
)
*114 (MRCItem
litem &48
pos 34
dimension 20
uid 1738,0
)
*115 (MRCItem
litem &49
pos 35
dimension 20
uid 1780,0
)
*116 (MRCItem
litem &50
pos 36
dimension 20
uid 1782,0
)
*117 (MRCItem
litem &51
pos 37
dimension 20
uid 1816,0
)
*118 (MRCItem
litem &52
pos 38
dimension 20
uid 1848,0
)
*119 (MRCItem
litem &53
pos 39
dimension 20
uid 1948,0
)
*120 (MRCItem
litem &54
pos 40
dimension 20
uid 1952,0
)
*121 (MRCItem
litem &55
pos 41
dimension 20
uid 1956,0
)
*122 (MRCItem
litem &56
pos 42
dimension 20
uid 2057,0
)
*123 (MRCItem
litem &57
pos 43
dimension 20
uid 2059,0
)
*124 (MRCItem
litem &58
pos 44
dimension 20
uid 2106,0
)
*125 (MRCItem
litem &59
pos 45
dimension 20
uid 2108,0
)
*126 (MRCItem
litem &60
pos 46
dimension 20
uid 2110,0
)
*127 (MRCItem
litem &61
pos 47
dimension 20
uid 2112,0
)
*128 (MRCItem
litem &62
pos 48
dimension 20
uid 2144,0
)
*129 (MRCItem
litem &63
pos 49
dimension 20
uid 2176,0
)
*130 (MRCItem
litem &64
pos 50
dimension 20
uid 2208,0
)
*131 (MRCItem
litem &65
pos 51
dimension 20
uid 2240,0
)
*132 (MRCItem
litem &66
pos 52
dimension 20
uid 2348,0
)
*133 (MRCItem
litem &67
pos 53
dimension 20
uid 2350,0
)
*134 (MRCItem
litem &68
pos 54
dimension 20
uid 2389,0
)
*135 (MRCItem
litem &69
pos 55
dimension 20
uid 2421,0
)
*136 (MRCItem
litem &70
pos 56
dimension 20
uid 2493,0
)
*137 (MRCItem
litem &71
pos 57
dimension 20
uid 2495,0
)
*138 (MRCItem
litem &72
pos 58
dimension 20
uid 2497,0
)
*139 (MRCItem
litem &73
pos 59
dimension 20
uid 2499,0
)
*140 (MRCItem
litem &74
pos 60
dimension 20
uid 2531,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
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uid 155,0
optionalChildren [
*141 (MRCItem
litem &5
pos 0
dimension 20
uid 156,0
)
*142 (MRCItem
litem &7
pos 1
dimension 50
uid 157,0
)
*143 (MRCItem
litem &8
pos 2
dimension 100
uid 158,0
)
*144 (MRCItem
litem &9
pos 3
dimension 50
uid 159,0
)
*145 (MRCItem
litem &10
pos 4
dimension 100
uid 160,0
)
*146 (MRCItem
litem &11
pos 5
dimension 100
uid 161,0
)
*147 (MRCItem
litem &12
pos 6
dimension 50
uid 162,0
)
*148 (MRCItem
litem &13
pos 7
dimension 80
uid 163,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 150,0
vaOverrides [
]
)
]
)
uid 135,0
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genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *149 (LEmptyRow
)
uid 165,0
optionalChildren [
*150 (RefLabelRowHdr
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*151 (TitleRowHdr
)
*152 (FilterRowHdr
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*153 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*154 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*155 (GroupColHdr
tm "GroupColHdrMgr"
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*156 (NameColHdr
tm "GenericNameColHdrMgr"
)
*157 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*158 (InitColHdr
tm "GenericValueColHdrMgr"
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*159 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
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*160 (EolColHdr
tm "GenericEolColHdrMgr"
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*161 (LogGeneric
generic (GiElement
name "RAM_ADDR_WIDTH"
type "integer"
value "12"
)
uid 2532,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 177,0
optionalChildren [
*162 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *163 (MRCItem
litem &149
pos 3
dimension 20
)
uid 179,0
optionalChildren [
*164 (MRCItem
litem &150
pos 0
dimension 20
uid 180,0
)
*165 (MRCItem
litem &151
pos 1
dimension 23
uid 181,0
)
*166 (MRCItem
litem &152
pos 2
hidden 1
dimension 20
uid 182,0
)
*167 (MRCItem
litem &161
pos 0
dimension 20
uid 2533,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 183,0
optionalChildren [
*168 (MRCItem
litem &153
pos 0
dimension 20
uid 184,0
)
*169 (MRCItem
litem &155
pos 1
dimension 50
uid 185,0
)
*170 (MRCItem
litem &156
pos 2
dimension 100
uid 186,0
)
*171 (MRCItem
litem &157
pos 3
dimension 100
uid 187,0
)
*172 (MRCItem
litem &158
pos 4
dimension 50
uid 188,0
)
*173 (MRCItem
litem &159
pos 5
dimension 50
uid 189,0
)
*174 (MRCItem
litem &160
pos 6
dimension 80
uid 190,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 178,0
vaOverrides [
]
)
]
)
uid 164,0
type 1
)
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "D:\\juli25\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "D:\\juli25\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\juli25\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\juli25\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb.user"
)
(vvPair
variable "SourceDir"
value "D:\\juli25\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "symbol"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "D:\\juli25\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator"
)
(vvPair
variable "d_logical"
value "D:\\juli25\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator"
)
(vvPair
variable "date"
value "26.07.2011"
)
(vvPair
variable "day"
value "Di"
)
(vvPair
variable "day_long"
value "Dienstag"
)
(vvPair
variable "dd"
value "26"
)
(vvPair
variable "entity_name"
value "data_generator"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "symbol.sb"
)
(vvPair
variable "f_logical"
value "symbol.sb"
)
(vvPair
variable "f_noext"
value "symbol"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "IHP110"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_lib"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/work"
)
(vvPair
variable "library_downstream_PrecisionSynthesisDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "mm"
value "07"
)
(vvPair
variable "module_name"
value "data_generator"
)
(vvPair
variable "month"
value "Jul"
)
(vvPair
variable "month_long"
value "Juli"
)
(vvPair
variable "p"
value "D:\\juli25\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb"
)
(vvPair
variable "p_logical"
value "D:\\juli25\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "D:\\modeltech_6.5e\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "sb"
)
(vvPair
variable "this_file"
value "symbol"
)
(vvPair
variable "this_file_logical"
value "symbol"
)
(vvPair
variable "time"
value "11:33:39"
)
(vvPair
variable "unit"
value "data_generator"
)
(vvPair
variable "user"
value "daqct3"
)
(vvPair
variable "version"
value "2009.1 (Build 12)"
)
(vvPair
variable "view"
value "symbol"
)
(vvPair
variable "year"
value "2011"
)
(vvPair
variable "yy"
value "11"
)
]
)
LanguageMgr "VhdlLangMgr"
uid 134,0
optionalChildren [
*175 (SymbolBody
uid 8,0
optionalChildren [
*176 (CptPort
uid 48,0
ps "OnEdgeStrategy"
shape (Triangle
uid 49,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,1625,37000,2375"
)
tg (CPTG
uid 50,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 51,0
va (VaSet
)
xt "38000,1500,39500,2500"
st "clk"
blo "38000,2300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 52,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,14400,33500,15200"
st "clk                        : IN     std_logic  ; -- CLK_25.
"
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
eolc "-- CLK_25."
preAdd 0
posAdd 0
o 3
suid 1,0
)
)
)
*177 (CptPort
uid 53,0
ps "OnEdgeStrategy"
shape (Triangle
uid 54,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,3625,67750,4375"
)
tg (CPTG
uid 55,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 56,0
va (VaSet
)
xt "58800,3500,66000,4500"
st "data_out : (63:0)"
ju 2
blo "66000,4300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 57,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,15200,38000,16000"
st "data_out                   : OUT    std_logic_vector (63 downto 0) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "data_out"
t "std_logic_vector"
b "(63 downto 0)"
preAdd 0
posAdd 0
o 4
suid 2,0
)
)
)
*178 (CptPort
uid 58,0
ps "OnEdgeStrategy"
shape (Triangle
uid 59,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,2625,67750,3375"
)
tg (CPTG
uid 60,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 61,0
va (VaSet
)
xt "50300,2500,66000,3500"
st "addr_out : (RAM_ADDR_WIDTH-1:0)"
ju 2
blo "66000,3300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 62,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,16000,45000,16800"
st "addr_out                   : OUT    std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "addr_out"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 downto 0)"
preAdd 0
posAdd 0
o 5
suid 3,0
)
)
)
*179 (CptPort
uid 78,0
ps "OnEdgeStrategy"
shape (Triangle
uid 391,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,18625,67750,19375"
)
tg (CPTG
uid 80,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 81,0
va (VaSet
)
xt "47600,18500,66000,19500"
st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
ju 2
blo "66000,19300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 82,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,17600,45000,18400"
st "ram_start_addr             : IN     std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 downto 0)"
preAdd 0
posAdd 0
o 7
suid 7,0
)
)
)
*180 (CptPort
uid 88,0
ps "OnEdgeStrategy"
shape (Triangle
uid 89,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,10625,37000,11375"
)
tg (CPTG
uid 90,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 91,0
va (VaSet
)
xt "38000,10500,44700,11500"
st "board_id : (3:0)"
blo "38000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 92,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,42400,37500,44000"
st "-- EVT HEADER - part 4
board_id                   : IN     std_logic_vector (3 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
prec "-- EVT HEADER - part 4"
preAdd 0
posAdd 0
o 33
suid 9,0
)
)
)
*181 (CommentText
uid 106,0
ps "EdgeToEdgeStrategy"
shape (Rectangle
uid 107,0
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "37000,2000,52000,6400"
)
oxt "37000,2000,52000,6000"
text (MLText
uid 108,0
va (VaSet
fg "0,0,32768"
)
xt "37200,2200,51000,6200"
st "
-- -- Uncomment the following library declaration if instantiating
-- -- any Xilinx primitives in this code.
-- library UNISIM;
-- use UNISIM.VComponents.all;
"
tm "CommentText"
wrapOption 3
visibleHeight 4400
visibleWidth 15000
)
included 1
excludeCommentLeader 1
)
*182 (CptPort
uid 285,0
ps "OnEdgeStrategy"
shape (Triangle
uid 286,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,12625,37000,13375"
)
tg (CPTG
uid 287,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 288,0
va (VaSet
)
xt "38000,12500,44400,13500"
st "crate_id : (1:0)"
blo "38000,13300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 289,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,44000,37500,44800"
st "crate_id                   : IN     std_logic_vector (1 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
posAdd 0
o 34
suid 12,0
)
)
)
*183 (CptPort
uid 402,0
ps "OnEdgeStrategy"
shape (Triangle
uid 403,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,14625,37000,15375"
)
tg (CPTG
uid 404,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 405,0
va (VaSet
)
xt "38000,14500,44100,15500"
st "ram_write_ea"
blo "38000,15300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 406,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,18400,28000,19200"
st "ram_write_ea               : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "ram_write_ea"
t "std_logic"
o 8
suid 16,0
)
)
)
*184 (CptPort
uid 407,0
ps "OnEdgeStrategy"
shape (Triangle
uid 408,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,20625,67750,21375"
)
tg (CPTG
uid 409,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 410,0
va (VaSet
)
xt "58600,20500,66000,21500"
st "ram_write_ready"
ju 2
blo "66000,21300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 411,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,19200,41000,20000"
st "ram_write_ready            : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_write_ready"
t "std_logic"
posAdd 0
o 9
suid 17,0
i "'0'"
)
)
)
*185 (CptPort
uid 412,0
ps "OnEdgeStrategy"
shape (Triangle
uid 413,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,15625,37000,16375"
)
tg (CPTG
uid 414,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 415,0
va (VaSet
)
xt "38000,15500,41400,16500"
st "roi_max"
blo "38000,16300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 416,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,20800,29500,21600"
st "roi_max                    : IN     roi_max_type  ;
"
)
thePort (LogicalPort
decl (Decl
n "roi_max"
t "roi_max_type"
o 11
suid 18,0
)
)
)
*186 (CptPort
uid 473,0
ps "OnEdgeStrategy"
shape (Triangle
uid 474,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,16625,37000,17375"
)
tg (CPTG
uid 475,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 476,0
va (VaSet
)
xt "38000,16500,41900,17500"
st "roi_array"
blo "38000,17300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 477,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,20000,30500,20800"
st "roi_array                  : IN     roi_array_type  ;
"
)
thePort (LogicalPort
decl (Decl
n "roi_array"
t "roi_array_type"
o 10
suid 19,0
)
)
)
*187 (CptPort
uid 526,0
ps "OnEdgeStrategy"
shape (Triangle
uid 527,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,17625,37000,18375"
)
tg (CPTG
uid 528,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 529,0
va (VaSet
)
xt "38000,17500,47900,18500"
st "package_length : (15:0)"
blo "38000,18300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 530,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,25600,38000,27200"
st "-- EVT HEADER - part 1
package_length             : IN     std_logic_vector (15 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "package_length"
t "std_logic_vector"
b "(15 downto 0)"
prec "-- EVT HEADER - part 1"
preAdd 0
o 17
suid 20,0
)
)
)
*188 (CptPort
uid 676,0
ps "OnEdgeStrategy"
shape (Triangle
uid 677,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,22625,67750,23375"
)
tg (CPTG
uid 678,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 679,0
va (VaSet
)
xt "56500,22500,66000,23500"
st "drs_channel_id : (3:0)"
ju 2
blo "66000,23300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 680,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,57600,47000,58400"
st "drs_channel_id             : OUT    std_logic_vector (3 downto 0) := (others => '0') ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
posAdd 0
o 49
suid 25,0
i "(others => '0')"
)
)
)
*189 (CptPort
uid 681,0
ps "OnEdgeStrategy"
shape (Triangle
uid 682,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,23625,67750,24375"
)
tg (CPTG
uid 683,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 684,0
va (VaSet
)
xt "60900,23500,66000,24500"
st "drs_clk_en"
ju 2
blo "66000,24300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 685,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,60800,41000,61600"
st "drs_clk_en                 : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_clk_en"
t "std_logic"
preAdd 0
posAdd 0
o 52
suid 26,0
i "'0'"
)
)
)
*190 (CptPort
uid 806,0
ps "OnEdgeStrategy"
shape (Triangle
uid 807,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,20625,37000,21375"
)
tg (CPTG
uid 808,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 809,0
va (VaSet
)
xt "38000,20500,48100,21500"
st "drs_read_s_cell_ready"
blo "38000,21300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 810,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,65600,28000,66400"
st "drs_read_s_cell_ready      : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "drs_read_s_cell_ready"
t "std_logic"
o 58
suid 34,0
)
)
)
*191 (CptPort
uid 811,0
ps "OnEdgeStrategy"
shape (Triangle
uid 812,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,21625,37000,22375"
)
tg (CPTG
uid 813,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 814,0
va (VaSet
)
xt "38000,21500,45300,22500"
st "drs_s_cell_array"
blo "38000,22300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 815,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,66400,34000,67200"
st "drs_s_cell_array           : IN     drs_s_cell_array_type  ;
"
)
thePort (LogicalPort
decl (Decl
n "drs_s_cell_array"
t "drs_s_cell_array_type"
o 59
suid 35,0
)
)
)
*192 (CptPort
uid 898,0
ps "OnEdgeStrategy"
shape (Triangle
uid 899,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,22625,37000,23375"
)
tg (CPTG
uid 900,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 901,0
va (VaSet
)
xt "38000,22500,44900,23500"
st "adc_data_array"
blo "38000,23300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 902,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,54400,33000,55200"
st "adc_data_array             : IN     adc_data_array_type  ;
"
)
thePort (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 45
suid 37,0
)
)
)
*193 (CptPort
uid 1085,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1086,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,27625,37000,28375"
)
tg (CPTG
uid 1087,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1088,0
va (VaSet
)
xt "38000,27500,43800,28500"
st "sensor_array"
blo "38000,28300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1089,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,21600,32000,22400"
st "sensor_array               : IN     sensor_array_type  ;
"
)
thePort (LogicalPort
decl (Decl
n "sensor_array"
t "sensor_array_type"
o 12
suid 44,0
)
)
)
*194 (CptPort
uid 1090,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1091,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,28625,37000,29375"
)
tg (CPTG
uid 1092,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1093,0
va (VaSet
)
xt "38000,28500,43900,29500"
st "sensor_ready"
blo "38000,29300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1094,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,22400,28000,23200"
st "sensor_ready               : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "sensor_ready"
t "std_logic"
o 13
suid 45,0
)
)
)
*195 (CptPort
uid 1240,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1241,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,33625,37000,34375"
)
tg (CPTG
uid 1242,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1243,0
va (VaSet
)
xt "38000,33500,42200,34500"
st "dac_array"
blo "38000,34300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1244,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,23200,30500,24000"
st "dac_array                  : IN     dac_array_type  ;
"
)
thePort (LogicalPort
decl (Decl
n "dac_array"
t "dac_array_type"
posAdd 0
o 14
suid 53,0
)
)
)
*196 (CptPort
uid 1395,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1396,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,31625,67750,32375"
)
tg (CPTG
uid 1397,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1398,0
va (VaSet
)
xt "60900,31500,66000,32500"
st "adc_clk_en"
ju 2
blo "66000,32300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1399,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,56000,41000,56800"
st "adc_clk_en                 : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_clk_en"
t "std_logic"
o 47
suid 54,0
i "'0'"
)
)
)
*197 (CptPort
uid 1427,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1428,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,34625,37000,35375"
)
tg (CPTG
uid 1429,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1430,0
va (VaSet
)
xt "38000,34500,44300,35500"
st "adc_otr : (3:0)"
blo "38000,35300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1431,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,56800,37500,57600"
st "adc_otr                    : IN     std_logic_vector (3 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "adc_otr"
t "std_logic_vector"
b "(3 downto 0)"
o 48
suid 55,0
)
)
)
*198 (CptPort
uid 1459,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1460,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,32625,67750,33375"
)
tg (CPTG
uid 1461,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1462,0
va (VaSet
)
xt "56800,32500,66000,33500"
st "drs_srin_data : (7:0)"
ju 2
blo "66000,33300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1463,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,64000,47000,64800"
st "drs_srin_data              : OUT    std_logic_vector (7 downto 0) := (others => '0') ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_srin_data"
t "std_logic_vector"
b "(7 downto 0)"
o 56
suid 56,0
i "(others => '0')"
)
)
)
*199 (CptPort
uid 1464,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1465,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,33625,67750,34375"
)
tg (CPTG
uid 1466,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1467,0
va (VaSet
)
xt "57900,33500,66000,34500"
st "drs_srin_write_8b"
ju 2
blo "66000,34300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1468,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,62400,41000,63200"
st "drs_srin_write_8b          : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_srin_write_8b"
t "std_logic"
o 54
suid 57,0
i "'0'"
)
)
)
*200 (CptPort
uid 1469,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1470,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,35625,37000,36375"
)
tg (CPTG
uid 1471,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1472,0
va (VaSet
)
xt "38000,35500,46400,36500"
st "drs_srin_write_ack"
blo "38000,36300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1473,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,63200,28000,64000"
st "drs_srin_write_ack         : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "drs_srin_write_ack"
t "std_logic"
o 55
suid 58,0
)
)
)
*201 (CptPort
uid 1474,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1475,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,36625,37000,37375"
)
tg (CPTG
uid 1476,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1477,0
va (VaSet
)
xt "38000,36500,47700,37500"
st "drs_srin_write_ready"
blo "38000,37300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1478,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,64800,28000,65600"
st "drs_srin_write_ready       : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "drs_srin_write_ready"
t "std_logic"
o 57
suid 59,0
)
)
)
*202 (CptPort
uid 1519,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1520,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,34625,67750,35375"
)
tg (CPTG
uid 1521,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1522,0
va (VaSet
)
xt "57000,34500,66000,35500"
st "drs_readout_started"
ju 2
blo "66000,35300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1523,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,67200,41000,68000"
st "drs_readout_started        : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_readout_started"
t "std_logic"
o 60
suid 61,0
i "'0'"
)
)
)
*203 (CptPort
uid 1551,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1552,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,35625,67750,36375"
)
tg (CPTG
uid 1553,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1554,0
va (VaSet
)
xt "57800,35500,66000,36500"
st "drs_readout_ready"
ju 2
blo "66000,36300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1555,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,58400,41000,60000"
st "--drs_dwrite : out std_logic := '1';
drs_readout_ready          : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_readout_ready"
t "std_logic"
prec "--drs_dwrite : out std_logic := '1';"
preAdd 0
posAdd 0
o 50
suid 62,0
i "'0'"
)
)
)
*204 (CptPort
uid 1583,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1584,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,38625,37000,39375"
)
tg (CPTG
uid 1585,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1586,0
va (VaSet
)
xt "38000,38500,48500,39500"
st "drs_readout_ready_ack"
blo "38000,39300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1587,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,60000,28000,60800"
st "drs_readout_ready_ack      : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "drs_readout_ready_ack"
t "std_logic"
posAdd 0
o 51
suid 63,0
)
)
)
*205 (CptPort
uid 1615,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1616,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,39625,37000,40375"
)
tg (CPTG
uid 1617,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1618,0
va (VaSet
)
xt "38000,39500,44100,40500"
st "pll_lock : (3:0)"
blo "38000,40300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1619,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,27200,38000,28000"
st "pll_lock                   : IN     std_logic_vector ( 3 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "pll_lock"
t "std_logic_vector"
b "( 3 downto 0)"
posAdd 0
o 18
suid 64,0
)
)
)
*206 (CptPort
uid 1647,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1648,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,40625,37000,41375"
)
tg (CPTG
uid 1649,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1650,0
va (VaSet
)
xt "38000,40500,49300,41500"
st "fad_event_counter : (31:0)"
blo "38000,41300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1651,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,38400,38000,40000"
st "-- EVT HEADER - part 3
fad_event_counter          : IN     std_logic_vector (31 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "fad_event_counter"
t "std_logic_vector"
b "(31 downto 0)"
prec "-- EVT HEADER - part 3"
preAdd 0
o 29
suid 65,0
)
)
)
*207 (CptPort
uid 1679,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1680,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,41625,37000,42375"
)
tg (CPTG
uid 1681,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1682,0
va (VaSet
)
xt "38000,41500,47700,42500"
st "refclk_counter : (11:0)"
blo "38000,42300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1683,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,40000,38000,40800"
st "refclk_counter             : IN     std_logic_vector (11 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "refclk_counter"
t "std_logic_vector"
b "(11 downto 0)"
o 30
suid 66,0
)
)
)
*208 (CptPort
uid 1684,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1685,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,42625,37000,43375"
)
tg (CPTG
uid 1686,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1687,0
va (VaSet
)
xt "38000,42500,45000,43500"
st "refclk_too_high"
blo "38000,43300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1688,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,40800,28000,41600"
st "refclk_too_high            : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "refclk_too_high"
t "std_logic"
o 31
suid 67,0
)
)
)
*209 (CptPort
uid 1689,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1690,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,43625,37000,44375"
)
tg (CPTG
uid 1691,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1692,0
va (VaSet
)
xt "38000,43500,44600,44500"
st "refclk_too_low"
blo "38000,44300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1693,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,41600,28000,42400"
st "refclk_too_low             : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "refclk_too_low"
t "std_logic"
posAdd 0
o 32
suid 68,0
)
)
)
*210 (CptPort
uid 1725,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1726,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,44625,37000,45375"
)
tg (CPTG
uid 1727,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1728,0
va (VaSet
)
xt "38000,44500,46300,45500"
st "FTM_RS485_ready"
blo "38000,45300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1729,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,33600,50500,36800"
st "-- EVT HEADER - part 2  --> FTM trigger informaton, comes in late ...
-- during EVT header wrinting, this field is left out ... and only written into event header,
-- when the DRS chip were read out already.
FTM_RS485_ready            : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "FTM_RS485_ready"
t "std_logic"
prec "-- EVT HEADER - part 2  --> FTM trigger informaton, comes in late ...
-- during EVT header wrinting, this field is left out ... and only written into event header,
-- when the DRS chip were read out already."
preAdd 0
o 26
suid 69,0
)
)
)
*211 (CptPort
uid 1730,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1731,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,45625,37000,46375"
)
tg (CPTG
uid 1732,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1733,0
va (VaSet
)
xt "38000,45500,49000,46500"
st "FTM_trigger_info : (55:0)"
blo "38000,46300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1734,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,36800,42500,37600"
st "FTM_trigger_info           : IN     std_logic_vector (55 downto 0) ; --7 byte
"
)
thePort (LogicalPort
decl (Decl
n "FTM_trigger_info"
t "std_logic_vector"
b "(55 downto 0)"
eolc "--7 byte"
posAdd 0
o 27
suid 70,0
)
)
)
*212 (CptPort
uid 1764,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1765,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,46625,37000,47375"
)
tg (CPTG
uid 1766,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1767,0
va (VaSet
)
xt "38000,46500,48000,47500"
st "DCM_PS_status : (7:0)"
blo "38000,47300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1768,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,44800,37500,45600"
st "DCM_PS_status              : IN     std_logic_vector (7 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "DCM_PS_status"
t "std_logic_vector"
b "(7 downto 0)"
o 35
suid 71,0
)
)
)
*213 (CptPort
uid 1769,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1770,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,47625,37000,48375"
)
tg (CPTG
uid 1771,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1772,0
va (VaSet
)
xt "38000,47500,47400,48500"
st "TRG_GEN_div : (15:0)"
blo "38000,48300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1773,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,48000,38000,48800"
st "TRG_GEN_div                : IN     std_logic_vector (15 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "TRG_GEN_div"
t "std_logic_vector"
b "(15 downto 0)"
posAdd 0
o 39
suid 72,0
)
)
)
*214 (CptPort
uid 1810,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1811,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,49625,37000,50375"
)
tg (CPTG
uid 1812,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1813,0
va (VaSet
)
xt "38000,49500,43100,50500"
st "dna : (63:0)"
blo "38000,50300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1814,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,48800,38000,50400"
st "-- EVT HEADER - part 5
dna                        : IN     std_logic_vector (63 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "dna"
t "std_logic_vector"
b "(63 downto 0)"
prec "-- EVT HEADER - part 5"
preAdd 0
posAdd 0
o 40
suid 74,0
)
)
)
*215 (CptPort
uid 1842,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1843,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,50625,37000,51375"
)
tg (CPTG
uid 1844,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1845,0
va (VaSet
)
xt "38000,50500,46500,51500"
st "timer_value : (31:0)"
blo "38000,51300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1846,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,52000,51000,52800"
st "timer_value                : IN     std_logic_vector (31 downto 0) ; -- time in units of 100us
"
)
thePort (LogicalPort
decl (Decl
n "timer_value"
t "std_logic_vector"
b "(31 downto 0)"
eolc "-- time in units of 100us"
preAdd 0
posAdd 0
o 42
suid 75,0
)
)
)
*216 (CptPort
uid 1922,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1923,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,36625,67750,37375"
)
tg (CPTG
uid 1924,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1925,0
va (VaSet
)
xt "54000,36500,66000,37500"
st "adc_output_enable_inverted"
ju 2
blo "66000,37300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1926,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,55200,41000,56000"
st "adc_output_enable_inverted : OUT    std_logic                     := '1' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_output_enable_inverted"
t "std_logic"
o 46
suid 76,0
i "'1'"
)
)
)
*217 (CptPort
uid 1932,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1933,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,38625,67750,39375"
)
tg (CPTG
uid 1934,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1935,0
va (VaSet
)
xt "54000,38500,66000,39500"
st "dataRAM_write_ea_o : (0:0)"
ju 2
blo "66000,39300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1936,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,16800,41000,17600"
st "dataRAM_write_ea_o         : OUT    std_logic_vector (0 downto 0) := \"0\" ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "dataRAM_write_ea_o"
t "std_logic_vector"
b "(0 downto 0)"
o 6
suid 78,0
i "\"0\""
)
)
)
*218 (CptPort
uid 1942,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1943,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,39625,67750,40375"
)
tg (CPTG
uid 1944,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1945,0
va (VaSet
)
xt "54800,39500,66000,40500"
st "start_read_drs_stop_cell"
ju 2
blo "66000,40300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1946,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,61600,41000,62400"
st "start_read_drs_stop_cell   : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "start_read_drs_stop_cell"
t "std_logic"
o 53
suid 80,0
i "'0'"
)
)
)
*219 (CptPort
uid 2046,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2047,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,40625,67750,41375"
)
tg (CPTG
uid 2048,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2049,0
va (VaSet
)
xt "60700,40500,66000,41500"
st "config_done"
ju 2
blo "66000,41300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2050,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,24800,41000,25600"
st "config_done                : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "config_done"
t "std_logic"
o 16
suid 83,0
i "'0'"
)
)
)
*220 (CptPort
uid 2051,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2052,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,51625,37000,52375"
)
tg (CPTG
uid 2053,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2054,0
va (VaSet
)
xt "38000,51500,43600,52500"
st "config_start"
blo "38000,52300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2055,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,24000,28000,24800"
st "config_start               : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "config_start"
t "std_logic"
o 15
suid 84,0
)
)
)
*221 (CptPort
uid 2085,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2086,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,52625,37000,53375"
)
tg (CPTG
uid 2087,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2088,0
va (VaSet
)
xt "38000,52500,46500,53500"
st "DCM_locked_status"
blo "38000,53300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2089,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,45600,28000,46400"
st "DCM_locked_status          : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "DCM_locked_status"
t "std_logic"
o 36
suid 85,0
)
)
)
*222 (CptPort
uid 2090,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2091,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,53625,37000,54375"
)
tg (CPTG
uid 2092,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2093,0
va (VaSet
)
xt "38000,53500,46200,54500"
st "DCM_ready_status"
blo "38000,54300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2094,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,46400,28000,47200"
st "DCM_ready_status           : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "DCM_ready_status"
t "std_logic"
o 37
suid 86,0
)
)
)
*223 (CptPort
uid 2095,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2096,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,54625,37000,55375"
)
tg (CPTG
uid 2097,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2098,0
va (VaSet
)
xt "38000,54500,45600,55500"
st "denable_enable_in"
blo "38000,55300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2099,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,28800,28000,29600"
st "denable_enable_in          : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "denable_enable_in"
t "std_logic"
o 20
suid 87,0
)
)
)
*224 (CptPort
uid 2100,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2101,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,55625,37000,56375"
)
tg (CPTG
uid 2102,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2103,0
va (VaSet
)
xt "38000,55500,45300,56500"
st "dwrite_enable_in"
blo "38000,56300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2104,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,28000,28000,28800"
st "dwrite_enable_in           : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "dwrite_enable_in"
t "std_logic"
o 19
suid 88,0
)
)
)
*225 (CptPort
uid 2138,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2139,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,56625,37000,57375"
)
tg (CPTG
uid 2140,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2141,0
va (VaSet
)
xt "38000,56500,49000,57500"
st "SPI_SCLK_enable_status"
blo "38000,57300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2142,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,47200,28000,48000"
st "SPI_SCLK_enable_status     : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "SPI_SCLK_enable_status"
t "std_logic"
o 38
suid 89,0
)
)
)
*226 (CptPort
uid 2170,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2171,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,41625,67750,42375"
)
tg (CPTG
uid 2172,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2173,0
va (VaSet
)
xt "60400,41500,66000,42500"
st "trigger_veto"
ju 2
blo "66000,42300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2174,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,68000,40000,68800"
st "trigger_veto               : OUT    std_logic                     := '1'
"
)
thePort (LogicalPort
m 1
decl (Decl
n "trigger_veto"
t "std_logic"
o 61
suid 90,0
i "'1'"
)
)
)
*227 (CptPort
uid 2202,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2203,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,57625,37000,58375"
)
tg (CPTG
uid 2204,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2205,0
va (VaSet
)
xt "38000,57500,47000,58500"
st "FTM_receiver_status"
blo "38000,58300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2206,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,37600,28000,38400"
st "FTM_receiver_status        : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "FTM_receiver_status"
t "std_logic"
o 28
suid 91,0
)
)
)
*228 (CptPort
uid 2234,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2235,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,58625,37000,59375"
)
tg (CPTG
uid 2236,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2237,0
va (VaSet
)
xt "38000,58500,45600,59500"
st "runnumber : (31:0)"
blo "38000,59300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2238,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,50400,38000,52000"
st "-- EVT HEADER - part 6
runnumber                  : IN     std_logic_vector (31 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "runnumber"
t "std_logic_vector"
b "(31 downto 0)"
prec "-- EVT HEADER - part 6"
preAdd 0
posAdd 0
o 41
suid 92,0
)
)
)
*229 (CptPort
uid 2337,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2338,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,59625,37000,60375"
)
tg (CPTG
uid 2339,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2340,0
va (VaSet
)
xt "38000,59500,46700,60500"
st "hardware_trigger_in"
blo "38000,60300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2341,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,52800,28000,53600"
st "hardware_trigger_in        : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "hardware_trigger_in"
t "std_logic"
o 43
suid 96,0
)
)
)
*230 (CptPort
uid 2342,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2343,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,60625,37000,61375"
)
tg (CPTG
uid 2344,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2345,0
va (VaSet
)
xt "38000,60500,46500,61500"
st "software_trigger_in"
blo "38000,61300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2346,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,53600,28000,54400"
st "software_trigger_in        : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "software_trigger_in"
t "std_logic"
o 44
suid 97,0
)
)
)
*231 (CptPort
uid 2381,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2382,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,43625,67750,44375"
)
tg (CPTG
uid 2383,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2384,0
va (VaSet
)
xt "60700,43500,66000,44500"
st "state : (7:0)"
ju 2
blo "66000,44300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2385,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,12000,37500,13600"
st "-- for debugging
state                      : OUT    std_logic_vector (7 downto 0) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 1
suid 99,0
)
)
)
*232 (CptPort
uid 2415,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2416,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67000,44625,67750,45375"
)
tg (CPTG
uid 2417,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2418,0
va (VaSet
)
xt "63200,44500,66000,45500"
st "is_idle"
ju 2
blo "66000,45300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2419,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,13600,28000,14400"
st "is_idle                    : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "is_idle"
t "std_logic"
o 2
suid 100,0
)
)
)
*233 (CptPort
uid 2472,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2473,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,61625,37000,62375"
)
tg (CPTG
uid 2474,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2475,0
va (VaSet
)
xt "38000,61500,44500,62500"
st "busy_enable_in"
blo "38000,62300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2476,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,29600,28000,30400"
st "busy_enable_in             : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "busy_enable_in"
t "std_logic"
o 21
suid 101,0
)
)
)
*234 (CptPort
uid 2477,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2478,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,62625,37000,63375"
)
tg (CPTG
uid 2479,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2480,0
va (VaSet
)
xt "38000,62500,46000,63500"
st "cont_trigger_en_in"
blo "38000,63300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2481,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,31200,28000,32000"
st "cont_trigger_en_in         : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "cont_trigger_en_in"
t "std_logic"
o 23
suid 102,0
)
)
)
*235 (CptPort
uid 2482,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2483,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,63625,37000,64375"
)
tg (CPTG
uid 2484,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2485,0
va (VaSet
)
xt "38000,63500,47100,64500"
st "socket_send_mode_in"
blo "38000,64300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2486,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,32000,28000,32800"
st "socket_send_mode_in        : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "socket_send_mode_in"
t "std_logic"
o 24
suid 103,0
)
)
)
*236 (CptPort
uid 2487,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2488,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,64625,37000,65375"
)
tg (CPTG
uid 2489,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2490,0
va (VaSet
)
xt "38000,64500,45400,65500"
st "trigger_enable_in"
blo "38000,65300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2491,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,30400,28000,31200"
st "trigger_enable_in          : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "trigger_enable_in"
t "std_logic"
o 22
suid 104,0
)
)
)
*237 (CptPort
uid 2525,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2526,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,65625,37000,66375"
)
tg (CPTG
uid 2527,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2528,0
va (VaSet
)
xt "38000,65500,44600,66500"
st "busy_manual_in"
blo "38000,66300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2529,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,32800,28000,33600"
st "busy_manual_in             : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "busy_manual_in"
t "std_logic"
o 25
suid 105,0
)
)
)
]
shape (Rectangle
uid 238,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "37000,1000,67000,67000"
)
oxt "37000,1000,51000,21000"
biTextGroup (BiTextGroup
uid 10,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
uid 11,0
va (VaSet
font "Arial,8,1"
)
xt "38300,21000,44500,22000"
st "FACT_FAD_lib"
blo "38300,21800"
)
second (Text
uid 12,0
va (VaSet
font "Arial,8,1"
)
xt "38300,22000,44700,23000"
st "data_generator"
blo "38300,22800"
)
)
gi *238 (GenericInterface
uid 13,0
ps "CenterOffsetStrategy"
matrix (Matrix
uid 14,0
text (MLText
uid 15,0
va (VaSet
font "Courier New,8,0"
)
xt "37000,5200,52000,7600"
st "Generic Declarations

RAM_ADDR_WIDTH integer 12  
"
)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
elements [
(GiElement
name "RAM_ADDR_WIDTH"
type "integer"
value "12"
)
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
)
portVis (PortSigDisplay
)
)
*239 (Grouping
uid 16,0
optionalChildren [
*240 (CommentText
uid 18,0
shape (Rectangle
uid 19,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "41000,29000,58000,30000"
)
oxt "18000,70000,35000,71000"
text (MLText
uid 20,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "41200,29000,51900,30000"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*241 (CommentText
uid 21,0
shape (Rectangle
uid 22,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "58000,25000,62000,26000"
)
oxt "35000,66000,39000,67000"
text (MLText
uid 23,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "58200,25000,61500,26000"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*242 (CommentText
uid 24,0
shape (Rectangle
uid 25,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "41000,27000,58000,28000"
)
oxt "18000,68000,35000,69000"
text (MLText
uid 26,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "41200,27000,52100,28000"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*243 (CommentText
uid 27,0
shape (Rectangle
uid 28,0
sl 0
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