| 1 | \documentclass[a4paper,twoside]{article} |
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| 2 | |
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| 3 | \setlength{\topmargin}{0mm} %1 inch is always there! |
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| 4 | \setlength{\oddsidemargin}{0mm} %1 inch is always there! |
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| 5 | \setlength{\evensidemargin}{0mm} %1 inch is always there! |
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| 6 | |
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| 7 | \setlength{\textwidth}{16cm} |
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| 8 | \setlength{\textheight}{25cm} |
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| 9 | |
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| 10 | |
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| 11 | \setlength{\headheight}{0mm} |
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| 12 | \setlength{\headsep}{0mm} |
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| 13 | |
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| 14 | \usepackage[T1]{fontenc} |
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| 15 | \usepackage[utf8]{inputenc} |
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| 16 | |
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| 17 | \usepackage{graphicx} % for pictures |
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| 18 | \usepackage{float} % for figures (english) |
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| 19 | \restylefloat{figure} |
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| 20 | \restylefloat{table} |
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| 21 | |
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| 22 | \usepackage{arydshln} |
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| 23 | |
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| 24 | \title{FAD Data Generation} |
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| 25 | \author{D. Neise} |
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| 26 | \date{08.02.2011} |
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| 27 | |
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| 28 | \begin{document} |
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| 29 | |
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| 30 | \maketitle |
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| 31 | \tableofcontents |
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| 32 | \newpage |
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| 33 | |
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| 34 | |
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| 35 | \section{data order in 64bit address space} |
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| 36 | |
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| 37 | When data is input into Data-RAM by the DataGenerator, the data is fed in as words of 64bit. |
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| 38 | |
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| 39 | Each Event constists of an EventHeader, the so called ChannelData, and a small EventFooter. |
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| 40 | Figure (\ref{64bitRAM}) shows how the data is stored as 64bit words in the DataRAM. |
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| 41 | Assume the Event Start-Address beeing {\tt 0x2000} and each package of ChannelData consists 100 samples. |
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| 42 | \\ \\ |
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| 43 | %\emph{Erklaeren, dass auch wenn nur ein channel kleiner ist, die selbe Anzahl Daten versendet wird.} |
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| 44 | |
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| 45 | |
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| 46 | \begin{table}[htbp] |
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| 47 | \begin{tabular}{||l||l|l|l|l||l||} |
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| 48 | \hline |
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| 49 | address & word 3 & word 2 & word 1 & word 0 & description \\ |
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| 50 | \hline |
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| 51 | 0x2000 & 0x0000 & version & length & 0xFB01 & Header \\ |
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| 52 | 0x2001 & 0x0000 & TRG ID 45 & EVT cntr 10 & EVT cntr 32 & Externl trigger ID\\ |
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| 53 | 0x2002 & 0x0000 & TRG ID 45 & EVT cntr 10 & EVT cntr 32 & Internal trigger ID\\ |
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| 54 | 0x2003 & 0x0000 & 0x0000 & 0x0000 & 0x0(cid)8(bid) & Board ID \\ |
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| 55 | 0x2004 & Temp 3 & Temp 2 & Temp 1 & Temp 0 & Temperatures \\ |
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| 56 | 0x2005 & DAC 3 & DAC 2 & DAC 1 & DAC 0 & DAC values part 1 \\ |
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| 57 | 0x2006 & DAC 7 & DAC 6 & DAC 5 & DAC 4 & DAC values part 2 \\ |
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| 58 | \hline |
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| 59 | 0x2007 & 0x0030 & 0x0020 & 0x0010 & 0x0000 & chip-n-channel ID (group 0) \\ |
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| 60 | 0x2008 & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 & DRS stop positions \\ |
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| 61 | 0x2009 & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\ |
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| 62 | 0x200A & data adc3 & data adc2 & data adc1 & data adc0 & ADC Data start of ROI \\ |
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| 63 | 0x20.. &&&&& ... \\ |
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| 64 | 0x206D & data adc3 & data adc2 & data adc1 & data adc0 & ADC Data end of ROI \\ |
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| 65 | \hline |
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| 66 | 0x206E & 0x0031 & 0x0021 & 0x0011 & 0x0001 & chip-n-channel ID (group 1) \\ |
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| 67 | 0x206F & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 & DRS stop positions \\ |
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| 68 | 0x2070 & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\ |
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| 69 | 0x2071 & data adc3 & data adc2 & data adc1 & data adc0 & ADC Data start of ROI \\ |
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| 70 | 0x20.. &&&&& ... \\ |
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| 71 | 0x20D4 & data adc3 & data adc2 & data adc1 & data adc0 & ADC Data end of ROI \\ |
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| 72 | \hline |
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| 73 | 0x20.. &&&&& ... \\ |
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| 74 | \hline |
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| 75 | 0x233F & 0x0039 & 0x0029 & 0x0019 & 0x0009 & chip-n-channel ID (group 9) \\ |
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| 76 | 0x2340 & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 & DRS stop positions \\ |
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| 77 | 0x2341 & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\ |
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| 78 | 0x2342 & data adc3 & data adc2 & data adc1 & data adc0 & ADC Data start of ROI \\ |
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| 79 | 0x23.. &&&&& ... \\ |
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| 80 | 0x23A5 & data adc3 & data adc2 & data adc1 & data adc0 & ADC Data end of ROI \\ |
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| 81 | \hline |
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| 82 | 0x23A6 & 0x0000 & 0x0000 & 0x04FE & 0x4242 & FOOTER \\ |
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| 83 | \hline |
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| 84 | \end {tabular} |
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| 85 | |
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| 86 | \caption{word order of event in Data RAM. 64bit addressing. As of 08.02.2011} |
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| 87 | \label{64bitRAM} |
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| 88 | \end{table} |
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| 89 | |
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| 90 | |
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| 91 | During DRS readout and data digitzation, the Trigger ID is coming in through RS485 interface from FTM board. |
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| 92 | The Trigger ID reciption takes about $40 {\mu}$s. Therefor the 2 words containing Trigger information in the EventHeader are |
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| 93 | left empty in the first place. The digitazed analog data is read in as quickly as possible. Only after finishing the Readout, |
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| 94 | the Trigger ID is filled into the EventHeader. |
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| 95 | Then the EventFooter is added and the Readout is finished. |
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| 96 | |
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| 97 | \newpage |
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| 98 | \section{data order in 16bit address space} |
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| 99 | |
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| 100 | After an Event is stored in data RAM, is is ready to be read out by {\tt w5300 modul.vhd}. |
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| 101 | Since the FIFOs of FADs W5300 ethernet controller are of 16bit width, data is read out of the dataRAM |
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| 102 | as 16bit words. Empty 16bit words are left out. |
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| 103 | |
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| 104 | The following table shows how the data is ordered inside data RAM, when accessed in 16bit address space |
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| 105 | |
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| 106 | \begin{table}[htbp] |
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| 107 | \begin{tabular}{|l|l|l|} |
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| 108 | \hline |
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| 109 | address & 16bit word & description \\ |
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| 110 | \hline |
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| 111 | 0x8000 & 0xFB01 & Start Flag - fix value \\ |
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| 112 | 0x8001 & 0xllll & package length in 16bit words \\ |
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| 113 | 0x8002 & 0xvvvv & version - deduced from SVN revision number \\ |
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| 114 | 0x8004 & EVT cntr 32 & trigger ID upper word \\ |
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| 115 | 0x8005 & EVT cntr 10 & trigger ID lower word \\ |
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| 116 | 0x8006 & 0xAA55 & trigger type and CRC-fake \\ |
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| 117 | 0x8008 & EVT cntr 32 & trigger ID upper word \\ |
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| 118 | 0x8009 & EVT cntr 10 & trigger ID lower word \\ |
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| 119 | 0x800A & 0xAA55 & trigger type and CRC-fake \\ |
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| 120 | 0x800C & 0x0(cid)8(bid) & Board ID \\ |
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| 121 | 0x8010 & 0xttt0 & temperature sensor next to DRS 0 \\ |
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| 122 | 0x8011 & 0xttt1 & temperature sensor next to DRS 1 \\ |
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| 123 | 0x8012 & 0xttt2 & temperature sensor next to DRS 2 \\ |
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| 124 | 0x8013 & 0xttt3 & temperature sensor next to DRS 3 \\ |
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| 125 | 0x8014 & 0xdac0 & setting of DAC channel A \\ |
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| 126 | 0x8015 & 0xdac1 & setting of DAC channel B \\ |
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| 127 | 0x8016 & 0xdac2 & setting of DAC channel C \\ |
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| 128 | 0x8017 & 0xdac3 & setting of DAC channel D \\ |
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| 129 | 0x8018 & 0xdac4 & setting of DAC channel E \\ |
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| 130 | 0x8019 & 0xdac5 & setting of DAC channel F \\ |
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| 131 | 0x801A & 0xdac6 & setting of DAC channel G \\ |
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| 132 | 0x801B & 0xdac7 & setting of DAC channel H \\ |
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| 133 | \hline |
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| 134 | 0x801C & 0x0000 & DRS 0 - channel 0 \\ |
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| 135 | 0x8020 & trg pos 0 & DRS 0 stop position \\ |
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| 136 | 0x8024 & ROI 00 & ROI width of this channel \\ |
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| 137 | 0x8028 & adc data 0& ADC data start \\ |
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| 138 | 0x8... & ... & ...data ... \\ |
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| 139 | 0x81B4 & adc data ROI-1 & ADC data stop\\ |
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| 140 | \hline |
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| 141 | 0x801D & 0x0010 & DRS 1 - channel 0 \\ |
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| 142 | 0x8021 & trg pos 1 & DRS 1 stop position \\ |
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| 143 | 0x8025 & ROI 10 & ROI width of this channel \\ |
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| 144 | 0x8029 & adc data 0& ADC data start \\ |
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| 145 | 0x8... & ... & ...data ... \\ |
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| 146 | 0x81B5 & adc data ROI-1 & ADC data stop\\ |
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| 147 | \hline |
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| 148 | 0x8... & ... & ...data ... \\ |
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| 149 | \hline |
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| 150 | 0x8CFC & 0x0039 & DRS 3 - channel 9 \\ |
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| 151 | 0x8D03 & trg pos 3 & DRS 3 stop position \\ |
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| 152 | 0x8D07 & ROI 39 & ROI width of this channel \\ |
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| 153 | 0x8D0B & adc data 0& ADC data start \\ |
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| 154 | 0x8... & ... & ...data ... \\ |
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| 155 | 0x8E97 & adc data ROI-1 & ADC data stop\\ |
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| 156 | \hline |
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| 157 | 0x8E98 & 0x4242 & packet CRC-fake \\ |
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| 158 | 0x8E99 & 0x04FE & End Flag \\ |
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| 159 | \hline |
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| 160 | \end {tabular} |
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| 161 | |
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| 162 | \caption{word order of event in Data RAM. 16bit addressing. As of 08.02.2011} |
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| 163 | \label{16bitRAM} |
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| 164 | \end{table} |
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| 165 | |
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| 166 | As one can see, the way of reading out of the RAM changes, from header to data section and again when data section ends. |
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| 167 | When reading the header, the addresses are increased by 1 usually and only jumps, when empty words show up in the RAM. |
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| 168 | One can picture it as if reading the words in each line from right to left, sometimes jumping over zeroes. |
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| 169 | When reading out the data sections, the words are read out as columns, i.e. addresses are incremented by 4 usually. One column is read until the data of a channel is completely read out, then either the next DRS chip is read out, which means to decrease the address or, if one group of channels was finished, the next group starts, which means address is increased by 1 only. |
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| 170 | The footer consisting of the CRC-16 (when finally implemented) and the end package flag is again read out by reading each word from right to left. |
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| 171 | |
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| 172 | |
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| 173 | \newpage |
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| 174 | \section{NEW data order} |
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| 175 | |
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| 176 | Some data is going to be added to the Event header changing the data order like this. |
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| 177 | |
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| 178 | \begin{table}[htbp] |
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| 179 | \begin{tabular}{||l||l|l|l|l||} |
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| 180 | \hline |
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| 181 | address & word 3 & word 2 & word 1 & word 0 \\ |
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| 182 | \hline |
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| 183 | 0x2000 & 12bit status + PLLLOCK & version & length & 0xFB01 \\ |
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| 184 | 0x2001 & 0xT1T0 & 0xT3T2 & 0xT5T4 & 0x00T6 \\ |
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| 185 | 0x2002 & REFCLK cntr 10 & REFCLK cntr 32 & EVT cntr 10 & EVT cntr 32 \\ |
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| 186 | 0x2003 & TRG-GEN-DIV & TRG-GEN-No & DCM-PS-STATUS & 0x0(cid)8(bid) \\ |
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| 187 | 0x2004 & more status & more status & time10 & time32 \\ |
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| 188 | 0x2005 & Temp 3 & Temp 2 & Temp 1 & Temp 0 \\ |
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| 189 | 0x2006 & DAC 3 & DAC 2 & DAC 1 & DAC 0 \\ |
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| 190 | 0x2007 & DAC 7 & DAC 6 & DAC 5 & DAC 4 \\ |
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| 191 | \hline |
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| 192 | 0x2007 & 0x0030 & 0x0020 & 0x0010 & 0x0000 \\ |
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| 193 | 0x2008 & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 \\ |
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| 194 | 0x2009 & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\ |
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| 195 | 0x200A & data adc3 & data adc2 & data adc1 & data adc0 \\ |
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| 196 | 0x20.. &&&& ... \\ |
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| 197 | 0x206D & data adc3 & data adc2 & data adc1 & data adc0 \\ |
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| 198 | \hline |
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| 199 | 0x20.. &&&& ... \\ |
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| 200 | \hline |
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| 201 | 0x233F & 0x0039 & 0x0029 & 0x0019 & 0x0009 \\ |
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| 202 | 0x2340 & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 \\ |
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| 203 | 0x2341 & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\ |
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| 204 | 0x2342 & data adc3 & data adc2 & data adc1 & data adc0 \\ |
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| 205 | 0x23.. &&&& ... \\ |
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| 206 | 0x23A5 & data adc3 & data adc2 & data adc1 & data adc0 \\ |
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| 207 | \hline |
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| 208 | 0x23A6 & 0x0000 & 0x0000 & 0x04FE & 0x4242\\ |
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| 209 | \hline |
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| 210 | \end {tabular} |
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| 211 | |
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| 212 | \caption{NEW word order of event in Data RAM. 64bit addressing. As of > 08.02.2011} |
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| 213 | \label{new64bitRAM} |
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| 214 | \end{table} |
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| 215 | |
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| 216 | \newpage |
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| 217 | Which in turn changes the the word order in the 16bit address space like this |
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| 218 | \begin{table}[htbp] |
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| 219 | \begin{tabular}{|l|l|l|} |
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| 220 | \hline |
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| 221 | address & 16bit word & description \\ |
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| 222 | \hline |
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| 223 | 0x8000 & 0xFB01 & Start Flag - fix value \\ |
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| 224 | 0x8001 & 0xllll & package length in 16bit words \\ |
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| 225 | 0x8002 & 0xvvvv & version - deduced from SVN revision number \\ |
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| 226 | 0x8003 & 0xsssP & 12 bits for status - TBD - 4 bit showing PLLLCK status \\ \hdashline |
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| 227 | 0x8004 & 0x00T6 & FTM trigger ID byte 6 : CRC \\ |
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| 228 | 0x8005 & 0xT5T4 & ... bytes 5 and 4 : Type 2 and Type 1\\ |
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| 229 | 0x8006 & 0xT3T2 & ... bytes 3 and 2 : TRG number high word \\ |
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| 230 | 0x8007 & 0xT1T0 & ... bytes 1 and 0 : TRG number low word \\ \hdashline |
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| 231 | 0x8008 & 0xev32 & FAD event counter high word \\ |
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| 232 | 0x8009 & 0xev10 & FAD event counter low word -- should be equal to T3T2T1T0\\ |
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| 233 | 0x800A & 0xRC32 & REFCLK counter high word \\ |
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| 234 | 0x800B & 0xRC10 & REFCLK counter low word \\ \hdashline |
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| 235 | 0x800C & 0x0(cid)8(bid) & Board ID \\ |
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| 236 | 0x800D & DCM-PS & status of ADC clock phase shifter , value and locked-bit\\ |
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| 237 | 0x800E & TRG-GEN-No& Number of Triggers to generare, when 'trigger continous' issued \\ |
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| 238 | 0x800F & TRG-GEN-DIV& continous trigger generator clock prescaler \\ \hdashline |
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| 239 | 0x8010 & timer32 & timer high word \\ |
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| 240 | 0x8011 & timer10 & timer low word \\ |
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| 241 | 0x8012 & more status1 & reserved for status info; high word \\ |
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| 242 | 0x8013 & more status0 & reserved for status info; low word \\ \hdashline |
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| 243 | 0x8014 & 0xttt0 & temperature sensor next to DRS 0 \\ |
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| 244 | 0x8015 & 0xttt1 & temperature sensor next to DRS 1 \\ |
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| 245 | 0x8016 & 0xttt2 & temperature sensor next to DRS 2 \\ |
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| 246 | 0x8017 & 0xttt3 & temperature sensor next to DRS 3 \\ \hdashline |
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| 247 | 0x8018 & 0xdac0 & setting of DAC channel A \\ |
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| 248 | 0x8019 & 0xdac1 & setting of DAC channel B \\ |
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| 249 | 0x801A & 0xdac2 & setting of DAC channel C \\ |
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| 250 | 0x801B & 0xdac3 & setting of DAC channel D \\ \hdashline |
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| 251 | 0x801C & 0xdac4 & setting of DAC channel E \\ |
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| 252 | 0x801D & 0xdac5 & setting of DAC channel F \\ |
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| 253 | 0x801E & 0xdac6 & setting of DAC channel G \\ |
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| 254 | 0x801F & 0xdac7 & setting of DAC channel H \\ |
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| 255 | \hline |
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| 256 | 0x8... & ... & ...data ... \\ |
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| 257 | \hline |
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| 258 | |
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| 259 | \end {tabular} |
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| 260 | \caption{word order of event in Data RAM. 16bit addressing. As of > 08.02.2011} |
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| 261 | \label{16bitRAM} |
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| 262 | \end{table} |
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| 263 | |
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| 264 | This new order has several advantages apart from the additional information included. |
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| 265 | All data may be treated as 64bit aligned. And the data readout process does not have to jump over word during data sending. |
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| 266 | |
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| 267 | \newpage |
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| 268 | \subsection{new {\tt FADFormat.h}} |
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| 269 | |
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| 270 | \begin{verbatim} |
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| 271 | typedef struct { |
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| 272 | // ------------------------------ |
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| 273 | unsigned short start_package_flag; |
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| 274 | unsigned short package_length; |
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| 275 | unsigned short version_no; |
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| 276 | unsinged short PLLLCK; |
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| 277 | // ------------------------------ |
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| 278 | unsigned short trigger_crc; |
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| 279 | unsigned short tigger_type; |
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| 280 | unsigned long trigger_id; |
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| 281 | // ------------------------------ |
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| 282 | unsigned long fad_evt_counter; |
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| 283 | unsigned long REFCLK_frequency; |
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| 284 | // ------------------------------ |
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| 285 | unsigned short board_id; |
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| 286 | unsigned short adc_clock_phase_shift; |
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| 287 | unsgined short number_of_triggers_to_generate; |
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| 288 | unsigned short trigger_generator_prescaler; |
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| 289 | // ------------------------------ |
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| 290 | unsigned long time; |
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| 291 | unsigned long fad_status; |
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| 292 | // ------------------------------ |
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| 293 | short drs_temperature[NTemp]; |
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| 294 | // ------------------------------ |
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| 295 | unsigned short dac[NDAC]; |
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| 296 | // ------------------------------ |
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| 297 | } __attribute__((__packed__)) PEVNT_HEADER; |
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| 298 | |
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| 299 | typedef struct { |
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| 300 | unsigned short id; |
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| 301 | unsigned short start_cell; |
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| 302 | unsigned short roi; |
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| 303 | unsigned short adc_data[]; |
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| 304 | } __attribute__((__packed__)) PCHANNEL; |
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| 305 | |
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| 306 | typedef struct { |
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| 307 | unsigned short package_crc; |
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| 308 | unsigned short end_package_flag; |
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| 309 | } __attribute__((__packed__)) PEVNT_FOOTER; |
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| 310 | \end{verbatim} |
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| 311 | |
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| 312 | |
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| 313 | \end{document} |
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